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ixgbevf: Limit lowest interrupt rate for adaptive interrupt moderation to 12K
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
9a799d71
AK		 68
69char ixgbe_driver_name[] = "ixgbe";
9c8eb720 70static const char ixgbe_driver_string[] =
e8e9f696 71 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 72#ifdef IXGBE_FCOE
ea81875a
NP		 73char ixgbe_default_device_descr[] =
74 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 75#else
76static char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
78#endif
21dd5601 79#define DRV_VERSION "4.2.1-k"
9c8eb720 80const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 81static const char ixgbe_copyright[] =
67359c3c 82 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 83
f44e751b
DS		 84static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
85
9a799d71 86static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 87 [board_82598] = &ixgbe_82598_info,
88 [board_82599] = &ixgbe_82599_info,
89 [board_X540] = &ixgbe_X540_info,
90 [board_X550] = &ixgbe_X550_info,
91 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 92};
93
94/* ixgbe_pci_tbl - PCI Device ID Table
95 *
96 * Wildcard entries (PCI_ANY_ID) should come last
97 * Last entry must be all 0s
98 *
99 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
100 * Class, Class Mask, private data (not used) }
101 */
9baa3c34 102static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
9a799d71
AK		 138 /* required last entry */
139 {0, }
140};
141MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
142
5dd2d332 143#ifdef CONFIG_IXGBE_DCA
bd0362dd 144static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 145 void *p);
bd0362dd
JC		 146static struct notifier_block dca_notifier = {
147 .notifier_call = ixgbe_notify_dca,
148 .next = NULL,
149 .priority = 0
150};
151#endif
152
1cdd1ec8
GR		 153#ifdef CONFIG_PCI_IOV
154static unsigned int max_vfs;
155module_param(max_vfs, uint, 0);
e8e9f696 156MODULE_PARM_DESC(max_vfs,
170e8543 157 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 158#endif /* CONFIG_PCI_IOV */
159
8ef78adc
PWJ		 160static unsigned int allow_unsupported_sfp;
161module_param(allow_unsupported_sfp, uint, 0);
162MODULE_PARM_DESC(allow_unsupported_sfp,
163 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
164
b3f4d599 165#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
166static int debug = -1;
167module_param(debug, int, 0);
168MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
169
9a799d71
AK		 170MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
171MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
172MODULE_LICENSE("GPL");
173MODULE_VERSION(DRV_VERSION);
174
14438464
MR		 175static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
176
b8e82001
JK		 177static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
178 u32 reg, u16 *value)
179{
b8e82001
JK		 180 struct pci_dev *parent_dev;
181 struct pci_bus *parent_bus;
182
183 parent_bus = adapter->pdev->bus->parent;
184 if (!parent_bus)
185 return -1;
186
187 parent_dev = parent_bus->self;
188 if (!parent_dev)
189 return -1;
190
c0798edf 191 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 192 return -1;
193
c0798edf 194 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 195 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
196 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
197 return -1;
b8e82001
JK		 198 return 0;
199}
200
201static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
202{
203 struct ixgbe_hw *hw = &adapter->hw;
204 u16 link_status = 0;
205 int err;
206
207 hw->bus.type = ixgbe_bus_type_pci_express;
208
209 /* Get the negotiated link width and speed from PCI config space of the
210 * parent, as this device is behind a switch
211 */
212 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
213
214 /* assume caller will handle error case */
215 if (err)
216 return err;
217
218 hw->bus.width = ixgbe_convert_bus_width(link_status);
219 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
220
221 return 0;
222}
223
e027d1ae
JK		 224/**
225 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
226 * @hw: hw specific details
227 *
228 * This function is used by probe to determine whether a device's PCI-Express
229 * bandwidth details should be gathered from the parent bus instead of from the
230 * device. Used to ensure that various locations all have the correct device ID
231 * checks.
232 */
233static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
234{
235 switch (hw->device_id) {
236 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 237 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 238 return true;
239 default:
240 return false;
241 }
242}
243
244static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
245 int expected_gts)
246{
f9328bc6 247 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 248 int max_gts = 0;
249 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
250 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
251 struct pci_dev *pdev;
252
f9328bc6
DS		 253 /* Some devices are not connected over PCIe and thus do not negotiate
254 * speed. These devices do not have valid bus info, and thus any report
255 * we generate may not be correct.
256 */
257 if (hw->bus.type == ixgbe_bus_type_internal)
258 return;
259
56d1392f 260 /* determine whether to use the parent device */
e027d1ae
JK		 261 if (ixgbe_pcie_from_parent(&adapter->hw))
262 pdev = adapter->pdev->bus->parent->self;
263 else
264 pdev = adapter->pdev;
265
266 if (pcie_get_minimum_link(pdev, &speed, &width) ||
267 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
268 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
269 return;
270 }
271
272 switch (speed) {
273 case PCIE_SPEED_2_5GT:
274 /* 8b/10b encoding reduces max throughput by 20% */
275 max_gts = 2 * width;
276 break;
277 case PCIE_SPEED_5_0GT:
278 /* 8b/10b encoding reduces max throughput by 20% */
279 max_gts = 4 * width;
280 break;
281 case PCIE_SPEED_8_0GT:
9f0a433c 282 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 283 max_gts = 8 * width;
284 break;
285 default:
286 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
287 return;
288 }
289
290 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
291 max_gts);
292 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
293 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
294 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
295 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
296 "Unknown"),
297 width,
298 (speed == PCIE_SPEED_2_5GT ? "20%" :
299 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 300 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 301 "Unknown"));
302
303 if (max_gts < expected_gts) {
304 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
305 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
306 expected_gts);
307 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
308 }
309}
310
7086400d
AD		 311static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
312{
313 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 314 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 315 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
316 schedule_work(&adapter->service_task);
317}
318
2a1a091c
MR		 319static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
320{
321 struct ixgbe_adapter *adapter = hw->back;
322
323 if (!hw->hw_addr)
324 return;
325 hw->hw_addr = NULL;
326 e_dev_err("Adapter removed\n");
58cf663f
MR		 327 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
328 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 329}
330
f8e2472f 331static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 332{
333 u32 value;
334
335 /* The following check not only optimizes a bit by not
336 * performing a read on the status register when the
337 * register just read was a status register read that
338 * returned IXGBE_FAILED_READ_REG. It also blocks any
339 * potential recursion.
340 */
341 if (reg == IXGBE_STATUS) {
342 ixgbe_remove_adapter(hw);
343 return;
344 }
345 value = ixgbe_read_reg(hw, IXGBE_STATUS);
346 if (value == IXGBE_FAILED_READ_REG)
347 ixgbe_remove_adapter(hw);
348}
349
f8e2472f
MR		 350/**
351 * ixgbe_read_reg - Read from device register
352 * @hw: hw specific details
353 * @reg: offset of register to read
354 *
355 * Returns : value read or IXGBE_FAILED_READ_REG if removed
356 *
357 * This function is used to read device registers. It checks for device
358 * removal by confirming any read that returns all ones by checking the
359 * status register value for all ones. This function avoids reading from
360 * the hardware if a removal was previously detected in which case it
361 * returns IXGBE_FAILED_READ_REG (all ones).
362 */
363u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
364{
365 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
366 u32 value;
367
368 if (ixgbe_removed(reg_addr))
369 return IXGBE_FAILED_READ_REG;
370 value = readl(reg_addr + reg);
371 if (unlikely(value == IXGBE_FAILED_READ_REG))
372 ixgbe_check_remove(hw, reg);
373 return value;
374}
375
14438464
MR		 376static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
377{
378 u16 value;
379
380 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
381 if (value == IXGBE_FAILED_READ_CFG_WORD) {
382 ixgbe_remove_adapter(hw);
383 return true;
384 }
385 return false;
386}
387
388u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
389{
390 struct ixgbe_adapter *adapter = hw->back;
391 u16 value;
392
393 if (ixgbe_removed(hw->hw_addr))
394 return IXGBE_FAILED_READ_CFG_WORD;
395 pci_read_config_word(adapter->pdev, reg, &value);
396 if (value == IXGBE_FAILED_READ_CFG_WORD &&
397 ixgbe_check_cfg_remove(hw, adapter->pdev))
398 return IXGBE_FAILED_READ_CFG_WORD;
399 return value;
400}
401
402#ifdef CONFIG_PCI_IOV
403static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
404{
405 struct ixgbe_adapter *adapter = hw->back;
406 u32 value;
407
408 if (ixgbe_removed(hw->hw_addr))
409 return IXGBE_FAILED_READ_CFG_DWORD;
410 pci_read_config_dword(adapter->pdev, reg, &value);
411 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
412 ixgbe_check_cfg_remove(hw, adapter->pdev))
413 return IXGBE_FAILED_READ_CFG_DWORD;
414 return value;
415}
416#endif /* CONFIG_PCI_IOV */
417
ed19231c
JK		 418void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
419{
420 struct ixgbe_adapter *adapter = hw->back;
421
422 if (ixgbe_removed(hw->hw_addr))
423 return;
424 pci_write_config_word(adapter->pdev, reg, value);
425}
426
7086400d
AD		 427static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
428{
429 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
430
52f33af8 431 /* flush memory to make sure state is correct before next watchdog */
4e857c58 432 smp_mb__before_atomic();
7086400d
AD		 433 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
434}
435
dcd79aeb
TI		 436struct ixgbe_reg_info {
437 u32 ofs;
438 char *name;
439};
440
441static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
442
443 /* General Registers */
444 {IXGBE_CTRL, "CTRL"},
445 {IXGBE_STATUS, "STATUS"},
446 {IXGBE_CTRL_EXT, "CTRL_EXT"},
447
448 /* Interrupt Registers */
449 {IXGBE_EICR, "EICR"},
450
451 /* RX Registers */
452 {IXGBE_SRRCTL(0), "SRRCTL"},
453 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
454 {IXGBE_RDLEN(0), "RDLEN"},
455 {IXGBE_RDH(0), "RDH"},
456 {IXGBE_RDT(0), "RDT"},
457 {IXGBE_RXDCTL(0), "RXDCTL"},
458 {IXGBE_RDBAL(0), "RDBAL"},
459 {IXGBE_RDBAH(0), "RDBAH"},
460
461 /* TX Registers */
462 {IXGBE_TDBAL(0), "TDBAL"},
463 {IXGBE_TDBAH(0), "TDBAH"},
464 {IXGBE_TDLEN(0), "TDLEN"},
465 {IXGBE_TDH(0), "TDH"},
466 {IXGBE_TDT(0), "TDT"},
467 {IXGBE_TXDCTL(0), "TXDCTL"},
468
469 /* List Terminator */
ca8dfe25 470 { .name = NULL }
dcd79aeb
TI		 471};
472
473
474/*
475 * ixgbe_regdump - register printout routine
476 */
477static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
478{
479 int i = 0, j = 0;
480 char rname[16];
481 u32 regs[64];
482
483 switch (reginfo->ofs) {
484 case IXGBE_SRRCTL(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
487 break;
488 case IXGBE_DCA_RXCTRL(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
491 break;
492 case IXGBE_RDLEN(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
495 break;
496 case IXGBE_RDH(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
499 break;
500 case IXGBE_RDT(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
503 break;
504 case IXGBE_RXDCTL(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
507 break;
508 case IXGBE_RDBAL(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
511 break;
512 case IXGBE_RDBAH(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
515 break;
516 case IXGBE_TDBAL(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
519 break;
520 case IXGBE_TDBAH(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
523 break;
524 case IXGBE_TDLEN(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
527 break;
528 case IXGBE_TDH(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
531 break;
532 case IXGBE_TDT(0):
533 for (i = 0; i < 64; i++)
534 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
535 break;
536 case IXGBE_TXDCTL(0):
537 for (i = 0; i < 64; i++)
538 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
539 break;
540 default:
c7689578 541 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 542 IXGBE_READ_REG(hw, reginfo->ofs));
543 return;
544 }
545
546 for (i = 0; i < 8; i++) {
547 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 548 pr_err("%-15s", rname);
dcd79aeb 549 for (j = 0; j < 8; j++)
c7689578
JP		 550 pr_cont(" %08x", regs[i*8+j]);
551 pr_cont("\n");
dcd79aeb
TI		 552 }
553
554}
555
556/*
557 * ixgbe_dump - Print registers, tx-rings and rx-rings
558 */
559static void ixgbe_dump(struct ixgbe_adapter *adapter)
560{
561 struct net_device *netdev = adapter->netdev;
562 struct ixgbe_hw *hw = &adapter->hw;
563 struct ixgbe_reg_info *reginfo;
564 int n = 0;
565 struct ixgbe_ring *tx_ring;
729739b7 566 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 567 union ixgbe_adv_tx_desc *tx_desc;
568 struct my_u0 { u64 a; u64 b; } *u0;
569 struct ixgbe_ring *rx_ring;
570 union ixgbe_adv_rx_desc *rx_desc;
571 struct ixgbe_rx_buffer *rx_buffer_info;
572 u32 staterr;
573 int i = 0;
574
575 if (!netif_msg_hw(adapter))
576 return;
577
578 /* Print netdevice Info */
579 if (netdev) {
580 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 581 pr_info("Device Name state "
dcd79aeb 582 "trans_start last_rx\n");
c7689578
JP		 583 pr_info("%-15s %016lX %016lX %016lX\n",
584 netdev->name,
585 netdev->state,
586 netdev->trans_start,
587 netdev->last_rx);
dcd79aeb
TI		 588 }
589
590 /* Print Registers */
591 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 592 pr_info(" Register Name Value\n");
dcd79aeb
TI		 593 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
594 reginfo->name; reginfo++) {
595 ixgbe_regdump(hw, reginfo);
596 }
597
598 /* Print TX Ring Summary */
599 if (!netdev || !netif_running(netdev))
e90dd264 600 return;
dcd79aeb
TI		 601
602 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 603 pr_info(" %s %s %s %s\n",
604 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
605 "leng", "ntw", "timestamp");
dcd79aeb
TI		 606 for (n = 0; n < adapter->num_tx_queues; n++) {
607 tx_ring = adapter->tx_ring[n];
729739b7 608 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 609 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 610 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 611 (u64)dma_unmap_addr(tx_buffer, dma),
612 dma_unmap_len(tx_buffer, len),
613 tx_buffer->next_to_watch,
614 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 615 }
616
617 /* Print TX Rings */
618 if (!netif_msg_tx_done(adapter))
619 goto rx_ring_summary;
620
621 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
622
623 /* Transmit Descriptor Formats
624 *
39ac868a 625 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 626 * +--------------------------------------------------------------+
627 * 0 | Buffer Address [63:0] |
628 * +--------------------------------------------------------------+
39ac868a 629 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 630 * +--------------------------------------------------------------+
631 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 632 *
633 * 82598 Advanced Transmit Descriptor (Write-Back Format)
634 * +--------------------------------------------------------------+
635 * 0 | RSV [63:0] |
636 * +--------------------------------------------------------------+
637 * 8 | RSV | STA | NXTSEQ |
638 * +--------------------------------------------------------------+
639 * 63 36 35 32 31 0
640 *
641 * 82599+ Advanced Transmit Descriptor
642 * +--------------------------------------------------------------+
643 * 0 | Buffer Address [63:0] |
644 * +--------------------------------------------------------------+
645 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
646 * +--------------------------------------------------------------+
647 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
648 *
649 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
650 * +--------------------------------------------------------------+
651 * 0 | RSV [63:0] |
652 * +--------------------------------------------------------------+
653 * 8 | RSV | STA | RSV |
654 * +--------------------------------------------------------------+
655 * 63 36 35 32 31 0
dcd79aeb
TI		 656 */
657
658 for (n = 0; n < adapter->num_tx_queues; n++) {
659 tx_ring = adapter->tx_ring[n];
c7689578
JP		 660 pr_info("------------------------------------\n");
661 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
662 pr_info("------------------------------------\n");
8ad88e37
JH		 663 pr_info("%s%s %s %s %s %s\n",
664 "T [desc] [address 63:0 ] ",
665 "[PlPOIdStDDt Ln] [bi->dma ] ",
666 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 667
668 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 669 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 670 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 671 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 672 if (dma_unmap_len(tx_buffer, len) > 0) {
673 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
674 i,
675 le64_to_cpu(u0->a),
676 le64_to_cpu(u0->b),
677 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 678 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 679 tx_buffer->next_to_watch,
680 (u64)tx_buffer->time_stamp,
681 tx_buffer->skb);
682 if (i == tx_ring->next_to_use &&
683 i == tx_ring->next_to_clean)
684 pr_cont(" NTC/U\n");
685 else if (i == tx_ring->next_to_use)
686 pr_cont(" NTU\n");
687 else if (i == tx_ring->next_to_clean)
688 pr_cont(" NTC\n");
689 else
690 pr_cont("\n");
691
692 if (netif_msg_pktdata(adapter) &&
693 tx_buffer->skb)
694 print_hex_dump(KERN_INFO, "",
695 DUMP_PREFIX_ADDRESS, 16, 1,
696 tx_buffer->skb->data,
697 dma_unmap_len(tx_buffer, len),
698 true);
699 }
dcd79aeb
TI		 700 }
701 }
702
703 /* Print RX Rings Summary */
704rx_ring_summary:
705 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 706 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 707 for (n = 0; n < adapter->num_rx_queues; n++) {
708 rx_ring = adapter->rx_ring[n];
c7689578
JP		 709 pr_info("%5d %5X %5X\n",
710 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 711 }
712
713 /* Print RX Rings */
714 if (!netif_msg_rx_status(adapter))
e90dd264 715 return;
dcd79aeb
TI		 716
717 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
718
39ac868a
JH		 719 /* Receive Descriptor Formats
720 *
721 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 722 * 63 1 0
723 * +-----------------------------------------------------+
724 * 0 | Packet Buffer Address [63:1] |A0/NSE|
725 * +----------------------------------------------+------+
726 * 8 | Header Buffer Address [63:1] | DD |
727 * +-----------------------------------------------------+
728 *
729 *
39ac868a 730 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 731 *
732 * 63 48 47 32 31 30 21 20 16 15 4 3 0
733 * +------------------------------------------------------+
39ac868a
JH		 734 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
735 * | Packet | IP | | | | Type | Type |
736 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 737 * +------------------------------------------------------+
738 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
739 * +------------------------------------------------------+
740 * 63 48 47 32 31 20 19 0
39ac868a
JH		 741 *
742 * 82599+ Advanced Receive Descriptor (Read) Format
743 * 63 1 0
744 * +-----------------------------------------------------+
745 * 0 | Packet Buffer Address [63:1] |A0/NSE|
746 * +----------------------------------------------+------+
747 * 8 | Header Buffer Address [63:1] | DD |
748 * +-----------------------------------------------------+
749 *
750 *
751 * 82599+ Advanced Receive Descriptor (Write-Back) Format
752 *
753 * 63 48 47 32 31 30 21 20 17 16 4 3 0
754 * +------------------------------------------------------+
755 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
756 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
757 * |/ Flow Dir Flt ID | | | | | |
758 * +------------------------------------------------------+
759 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
760 * +------------------------------------------------------+
761 * 63 48 47 32 31 20 19 0
dcd79aeb 762 */
39ac868a 763
dcd79aeb
TI		 764 for (n = 0; n < adapter->num_rx_queues; n++) {
765 rx_ring = adapter->rx_ring[n];
c7689578
JP		 766 pr_info("------------------------------------\n");
767 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
768 pr_info("------------------------------------\n");
8ad88e37
JH		 769 pr_info("%s%s%s",
770 "R [desc] [ PktBuf A0] ",
771 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 772 "<-- Adv Rx Read format\n");
8ad88e37
JH		 773 pr_info("%s%s%s",
774 "RWB[desc] [PcsmIpSHl PtRs] ",
775 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 776 "<-- Adv Rx Write-Back format\n");
777
778 for (i = 0; i < rx_ring->count; i++) {
779 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 780 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 781 u0 = (struct my_u0 *)rx_desc;
782 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
783 if (staterr & IXGBE_RXD_STAT_DD) {
784 /* Descriptor Done */
c7689578 785 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 786 "%016llX ---------------- %p", i,
787 le64_to_cpu(u0->a),
788 le64_to_cpu(u0->b),
789 rx_buffer_info->skb);
790 } else {
c7689578 791 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 792 "%016llX %016llX %p", i,
793 le64_to_cpu(u0->a),
794 le64_to_cpu(u0->b),
795 (u64)rx_buffer_info->dma,
796 rx_buffer_info->skb);
797
9c50c035
ET		 798 if (netif_msg_pktdata(adapter) &&
799 rx_buffer_info->dma) {
dcd79aeb
TI		 800 print_hex_dump(KERN_INFO, "",
801 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 802 page_address(rx_buffer_info->page) +
803 rx_buffer_info->page_offset,
f800326d 804 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 805 }
806 }
807
808 if (i == rx_ring->next_to_use)
c7689578 809 pr_cont(" NTU\n");
dcd79aeb 810 else if (i == rx_ring->next_to_clean)
c7689578 811 pr_cont(" NTC\n");
dcd79aeb 812 else
c7689578 813 pr_cont("\n");
dcd79aeb
TI		 814
815 }
816 }
dcd79aeb
TI		 817}
818
5eba3699
AV		 819static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
820{
821 u32 ctrl_ext;
822
823 /* Let firmware take over control of h/w */
824 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
825 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 826 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 827}
828
829static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
830{
831 u32 ctrl_ext;
832
833 /* Let firmware know the driver has taken over */
834 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 836 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 837}
9a799d71 838
49ce9c2c 839/**
e8e26350
PW		 840 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
841 * @adapter: pointer to adapter struct
842 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
843 * @queue: queue to map the corresponding interrupt to
844 * @msix_vector: the vector to map to the corresponding queue
845 *
846 */
847static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 848 u8 queue, u8 msix_vector)
9a799d71
AK		 849{
850 u32 ivar, index;
e8e26350
PW		 851 struct ixgbe_hw *hw = &adapter->hw;
852 switch (hw->mac.type) {
853 case ixgbe_mac_82598EB:
854 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
855 if (direction == -1)
856 direction = 0;
857 index = (((direction * 64) + queue) >> 2) & 0x1F;
858 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
859 ivar &= ~(0xFF << (8 * (queue & 0x3)));
860 ivar |= (msix_vector << (8 * (queue & 0x3)));
861 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
862 break;
863 case ixgbe_mac_82599EB:
b93a2226 864 case ixgbe_mac_X540:
9a75a1ac
DS		 865 case ixgbe_mac_X550:
866 case ixgbe_mac_X550EM_x:
e8e26350
PW		 867 if (direction == -1) {
868 /* other causes */
869 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
870 index = ((queue & 1) * 8);
871 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
872 ivar &= ~(0xFF << index);
873 ivar |= (msix_vector << index);
874 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
875 break;
876 } else {
877 /* tx or rx causes */
878 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
879 index = ((16 * (queue & 1)) + (8 * direction));
880 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
881 ivar &= ~(0xFF << index);
882 ivar |= (msix_vector << index);
883 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
884 break;
885 }
886 default:
887 break;
888 }
9a799d71
AK		 889}
890
fe49f04a 891static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 892 u64 qmask)
fe49f04a
AD		 893{
894 u32 mask;
895
bd508178
AD		 896 switch (adapter->hw.mac.type) {
897 case ixgbe_mac_82598EB:
fe49f04a
AD		 898 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
899 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 900 break;
901 case ixgbe_mac_82599EB:
b93a2226 902 case ixgbe_mac_X540:
9a75a1ac
DS		 903 case ixgbe_mac_X550:
904 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 905 mask = (qmask & 0xFFFFFFFF);
906 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
907 mask = (qmask >> 32);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 909 break;
910 default:
911 break;
fe49f04a
AD		 912 }
913}
914
729739b7
AD		 915void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
916 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 917{
729739b7
AD		 918 if (tx_buffer->skb) {
919 dev_kfree_skb_any(tx_buffer->skb);
920 if (dma_unmap_len(tx_buffer, len))
d3d00239 921 dma_unmap_single(ring->dev,
729739b7
AD		 922 dma_unmap_addr(tx_buffer, dma),
923 dma_unmap_len(tx_buffer, len),
924 DMA_TO_DEVICE);
925 } else if (dma_unmap_len(tx_buffer, len)) {
926 dma_unmap_page(ring->dev,
927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
e5a43549 930 }
729739b7
AD		 931 tx_buffer->next_to_watch = NULL;
932 tx_buffer->skb = NULL;
933 dma_unmap_len_set(tx_buffer, len, 0);
934 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 935}
936
943561d3 937static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 938{
939 struct ixgbe_hw *hw = &adapter->hw;
940 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 941 int i;
943561d3 942 u32 data;
c84d324c 943
943561d3
AD		 944 if ((hw->fc.current_mode != ixgbe_fc_full) &&
945 (hw->fc.current_mode != ixgbe_fc_rx_pause))
946 return;
c84d324c 947
943561d3
AD		 948 switch (hw->mac.type) {
949 case ixgbe_mac_82598EB:
950 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
951 break;
952 default:
953 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
954 }
955 hwstats->lxoffrxc += data;
c84d324c 956
943561d3
AD		 957 /* refill credits (no tx hang) if we received xoff */
958 if (!data)
c84d324c 959 return;
943561d3
AD		 960
961 for (i = 0; i < adapter->num_tx_queues; i++)
962 clear_bit(__IXGBE_HANG_CHECK_ARMED,
963 &adapter->tx_ring[i]->state);
964}
965
966static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
967{
968 struct ixgbe_hw *hw = &adapter->hw;
969 struct ixgbe_hw_stats *hwstats = &adapter->stats;
970 u32 xoff[8] = {0};
2afaa00d 971 u8 tc;
943561d3
AD		 972 int i;
973 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
974
975 if (adapter->ixgbe_ieee_pfc)
976 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
977
978 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
979 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 980 return;
943561d3 981 }
c84d324c
JF		 982
983 /* update stats for each tc, only valid with PFC enabled */
984 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 985 u32 pxoffrxc;
986
c84d324c
JF		 987 switch (hw->mac.type) {
988 case ixgbe_mac_82598EB:
2afaa00d 989 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 990 break;
c84d324c 991 default:
2afaa00d 992 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 993 }
2afaa00d
PN		 994 hwstats->pxoffrxc[i] += pxoffrxc;
995 /* Get the TC for given UP */
996 tc = netdev_get_prio_tc_map(adapter->netdev, i);
997 xoff[tc] += pxoffrxc;
c84d324c
JF		 998 }
999
1000 /* disarm tx queues that have received xoff frames */
1001 for (i = 0; i < adapter->num_tx_queues; i++) {
1002 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1003
2afaa00d 1004 tc = tx_ring->dcb_tc;
c84d324c
JF		 1005 if (xoff[tc])
1006 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1007 }
26f23d82
YZ		 1008}
1009
c84d324c 1010static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1011{
7d7ce682 1012 return ring->stats.packets;
c84d324c
JF		 1013}
1014
1015static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1016{
2a47fa45
JF		 1017 struct ixgbe_adapter *adapter;
1018 struct ixgbe_hw *hw;
1019 u32 head, tail;
1020
1021 if (ring->l2_accel_priv)
1022 adapter = ring->l2_accel_priv->real_adapter;
1023 else
1024 adapter = netdev_priv(ring->netdev);
e01c31a5 1025
2a47fa45
JF		 1026 hw = &adapter->hw;
1027 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1028 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1029
1030 if (head != tail)
1031 return (head < tail) ?
1032 tail - head : (tail + ring->count - head);
1033
1034 return 0;
1035}
1036
1037static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1038{
1039 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1040 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1041 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1042
7d637bcc 1043 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1044
1045 /*
1046 * Check for a hung queue, but be thorough. This verifies
1047 * that a transmit has been completed since the previous
1048 * check AND there is at least one packet pending. The
1049 * ARMED bit is set to indicate a potential hang. The
1050 * bit is cleared if a pause frame is received to remove
1051 * false hang detection due to PFC or 802.3x frames. By
1052 * requiring this to fail twice we avoid races with
1053 * pfc clearing the ARMED bit and conditions where we
1054 * run the check_tx_hang logic with a transmit completion
1055 * pending but without time to complete it yet.
1056 */
e90dd264 1057 if (tx_done_old == tx_done && tx_pending)
c84d324c 1058 /* make sure it is true for two checks in a row */
e90dd264
MR		 1059 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1060 &tx_ring->state);
1061 /* update completed stats and continue */
1062 tx_ring->tx_stats.tx_done_old = tx_done;
1063 /* reset the countdown */
1064 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1065
e90dd264 1066 return false;
9a799d71
AK		 1067}
1068
c83c6cbd
AD		 1069/**
1070 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1071 * @adapter: driver private struct
1072 **/
1073static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1074{
1075
1076 /* Do the reset outside of interrupt context */
1077 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1078 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1079 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1080 ixgbe_service_event_schedule(adapter);
1081 }
1082}
e01c31a5 1083
9a799d71
AK		 1084/**
1085 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1086 * @q_vector: structure containing interrupt and ring information
e01c31a5 1087 * @tx_ring: tx ring to clean
9a799d71 1088 **/
fe49f04a 1089static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1090 struct ixgbe_ring *tx_ring)
9a799d71 1091{
fe49f04a 1092 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1093 struct ixgbe_tx_buffer *tx_buffer;
1094 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1095 unsigned int total_bytes = 0, total_packets = 0;
59224555 1096 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1097 unsigned int i = tx_ring->next_to_clean;
1098
1099 if (test_bit(__IXGBE_DOWN, &adapter->state))
1100 return true;
9a799d71 1101
d3d00239 1102 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1103 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1104 i -= tx_ring->count;
12207e49 1105
729739b7 1106 do {
d3d00239
AD		 1107 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1108
1109 /* if next_to_watch is not set then there is no work pending */
1110 if (!eop_desc)
1111 break;
1112
7f83a9e6 1113 /* prevent any other reads prior to eop_desc */
7e63bf49 1114 read_barrier_depends();
7f83a9e6 1115
d3d00239
AD		 1116 /* if DD is not set pending work has not been completed */
1117 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1118 break;
8ad494b0 1119
d3d00239
AD		 1120 /* clear next_to_watch to prevent false hangs */
1121 tx_buffer->next_to_watch = NULL;
8ad494b0 1122
091a6246
AD		 1123 /* update the statistics for this packet */
1124 total_bytes += tx_buffer->bytecount;
1125 total_packets += tx_buffer->gso_segs;
1126
fd0db0ed 1127 /* free the skb */
fe1f2a97 1128 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1129
729739b7
AD		 1130 /* unmap skb header data */
1131 dma_unmap_single(tx_ring->dev,
1132 dma_unmap_addr(tx_buffer, dma),
1133 dma_unmap_len(tx_buffer, len),
1134 DMA_TO_DEVICE);
1135
fd0db0ed
AD		 1136 /* clear tx_buffer data */
1137 tx_buffer->skb = NULL;
729739b7 1138 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1139
729739b7
AD		 1140 /* unmap remaining buffers */
1141 while (tx_desc != eop_desc) {
d3d00239
AD		 1142 tx_buffer++;
1143 tx_desc++;
8ad494b0 1144 i++;
729739b7
AD		 1145 if (unlikely(!i)) {
1146 i -= tx_ring->count;
d3d00239 1147 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1148 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1149 }
e01c31a5 1150
729739b7
AD		 1151 /* unmap any remaining paged data */
1152 if (dma_unmap_len(tx_buffer, len)) {
1153 dma_unmap_page(tx_ring->dev,
1154 dma_unmap_addr(tx_buffer, dma),
1155 dma_unmap_len(tx_buffer, len),
1156 DMA_TO_DEVICE);
1157 dma_unmap_len_set(tx_buffer, len, 0);
1158 }
1159 }
1160
1161 /* move us one more past the eop_desc for start of next pkt */
1162 tx_buffer++;
1163 tx_desc++;
1164 i++;
1165 if (unlikely(!i)) {
1166 i -= tx_ring->count;
1167 tx_buffer = tx_ring->tx_buffer_info;
1168 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1169 }
1170
1171 /* issue prefetch for next Tx descriptor */
1172 prefetch(tx_desc);
12207e49 1173
729739b7
AD		 1174 /* update budget accounting */
1175 budget--;
1176 } while (likely(budget));
1177
1178 i += tx_ring->count;
9a799d71 1179 tx_ring->next_to_clean = i;
d3d00239 1180 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1181 tx_ring->stats.bytes += total_bytes;
bd198058 1182 tx_ring->stats.packets += total_packets;
d3d00239 1183 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1184 q_vector->tx.total_bytes += total_bytes;
1185 q_vector->tx.total_packets += total_packets;
b953799e 1186
c84d324c
JF		 1187 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1188 /* schedule immediate reset if we believe we hung */
1189 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1190 e_err(drv, "Detected Tx Unit Hang\n"
1191 " Tx Queue <%d>\n"
1192 " TDH, TDT <%x>, <%x>\n"
1193 " next_to_use <%x>\n"
1194 " next_to_clean <%x>\n"
1195 "tx_buffer_info[next_to_clean]\n"
1196 " time_stamp <%lx>\n"
1197 " jiffies <%lx>\n",
1198 tx_ring->queue_index,
1199 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1200 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1201 tx_ring->next_to_use, i,
1202 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1203
1204 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1205
1206 e_info(probe,
1207 "tx hang %d detected on queue %d, resetting adapter\n",
1208 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1209
b953799e 1210 /* schedule immediate reset if we believe we hung */
c83c6cbd 1211 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1212
1213 /* the adapter is about to reset, no point in enabling stuff */
59224555 1214 return true;
b953799e 1215 }
9a799d71 1216
b2d96e0a
AD		 1217 netdev_tx_completed_queue(txring_txq(tx_ring),
1218 total_packets, total_bytes);
1219
e092be60 1220#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1221 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1222 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1223 /* Make sure that anybody stopping the queue after this
1224 * sees the new next_to_clean.
1225 */
1226 smp_mb();
729739b7
AD		 1227 if (__netif_subqueue_stopped(tx_ring->netdev,
1228 tx_ring->queue_index)
1229 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1230 netif_wake_subqueue(tx_ring->netdev,
1231 tx_ring->queue_index);
5b7da515 1232 ++tx_ring->tx_stats.restart_queue;
30eba97a 1233 }
e092be60 1234 }
9a799d71 1235
59224555 1236 return !!budget;
9a799d71
AK		 1237}
1238
5dd2d332 1239#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1240static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1241 struct ixgbe_ring *tx_ring,
33cf09c9 1242 int cpu)
bd0362dd 1243{
33cf09c9 1244 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1245 u32 txctrl = 0;
bdda1a61 1246 u16 reg_offset;
33cf09c9 1247
9de7605e
MR		 1248 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1249 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1250
33cf09c9
AD		 1251 switch (hw->mac.type) {
1252 case ixgbe_mac_82598EB:
bdda1a61 1253 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1254 break;
1255 case ixgbe_mac_82599EB:
b93a2226 1256 case ixgbe_mac_X540:
bdda1a61
AD		 1257 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1258 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1259 break;
1260 default:
bdda1a61
AD		 1261 /* for unknown hardware do not write register */
1262 return;
bd0362dd 1263 }
bdda1a61
AD		 1264
1265 /*
1266 * We can enable relaxed ordering for reads, but not writes when
1267 * DCA is enabled. This is due to a known issue in some chipsets
1268 * which will cause the DCA tag to be cleared.
1269 */
1270 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1271 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1272 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1273
1274 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1275}
1276
bdda1a61
AD		 1277static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1278 struct ixgbe_ring *rx_ring,
33cf09c9 1279 int cpu)
bd0362dd 1280{
33cf09c9 1281 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1282 u32 rxctrl = 0;
bdda1a61
AD		 1283 u8 reg_idx = rx_ring->reg_idx;
1284
9de7605e
MR		 1285 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1286 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1287
1288 switch (hw->mac.type) {
33cf09c9 1289 case ixgbe_mac_82599EB:
b93a2226 1290 case ixgbe_mac_X540:
bdda1a61 1291 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1292 break;
1293 default:
1294 break;
1295 }
bdda1a61
AD		 1296
1297 /*
1298 * We can enable relaxed ordering for reads, but not writes when
1299 * DCA is enabled. This is due to a known issue in some chipsets
1300 * which will cause the DCA tag to be cleared.
1301 */
1302 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1303 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1304 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1305
1306 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1307}
1308
1309static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1310{
1311 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1312 struct ixgbe_ring *ring;
bd0362dd 1313 int cpu = get_cpu();
bd0362dd 1314
33cf09c9
AD		 1315 if (q_vector->cpu == cpu)
1316 goto out_no_update;
1317
a557928e 1318 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1319 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1320
a557928e 1321 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1322 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1323
1324 q_vector->cpu = cpu;
1325out_no_update:
bd0362dd
JC		 1326 put_cpu();
1327}
1328
1329static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1330{
1331 int i;
1332
e35ec126 1333 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1334 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1335 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1336 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1337 else
1338 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1339 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1340
49c7ffbe 1341 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1342 adapter->q_vector[i]->cpu = -1;
1343 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1344 }
1345}
1346
1347static int __ixgbe_notify_dca(struct device *dev, void *data)
1348{
c60fbb00 1349 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1350 unsigned long event = *(unsigned long *)data;
1351
2a72c31e 1352 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1353 return 0;
1354
bd0362dd
JC		 1355 switch (event) {
1356 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1357 /* if we're already enabled, don't do it again */
1358 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1359 break;
652f093f 1360 if (dca_add_requester(dev) == 0) {
96b0e0f6 1361 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1362 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1363 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1364 break;
1365 }
1366 /* Fall Through since DCA is disabled. */
1367 case DCA_PROVIDER_REMOVE:
1368 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1369 dca_remove_requester(dev);
1370 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1371 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1372 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1373 }
1374 break;
1375 }
1376
652f093f 1377 return 0;
bd0362dd 1378}
67a74ee2 1379
bdda1a61 1380#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1381
1382#define IXGBE_RSS_L4_TYPES_MASK \
1383 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1384 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1385 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1386 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1387
8a0da21b
AD		 1388static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1389 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1390 struct sk_buff *skb)
1391{
7edda4b8
FD		 1392 u16 rss_type;
1393
1394 if (!(ring->netdev->features & NETIF_F_RXHASH))
1395 return;
1396
1397 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1398 IXGBE_RXDADV_RSSTYPE_MASK;
1399
1400 if (!rss_type)
1401 return;
1402
1403 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1404 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1405 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1406}
1407
f800326d 1408#ifdef IXGBE_FCOE
ff886dfc
AD		 1409/**
1410 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1411 * @ring: structure containing ring specific data
ff886dfc
AD		 1412 * @rx_desc: advanced rx descriptor
1413 *
1414 * Returns : true if it is FCoE pkt
1415 */
57efd44c 1416static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1417 union ixgbe_adv_rx_desc *rx_desc)
1418{
1419 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1420
57efd44c 1421 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1422 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1423 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1424 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1425}
1426
f800326d 1427#endif /* IXGBE_FCOE */
e59bd25d
AV		 1428/**
1429 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1430 * @ring: structure containing ring specific data
1431 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1432 * @skb: skb currently being received and modified
1433 **/
8a0da21b 1434static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1435 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1436 struct sk_buff *skb)
9a799d71 1437{
3f207800
DS		 1438 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1439 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1440 bool encap_pkt = false;
1441
8a0da21b 1442 skb_checksum_none_assert(skb);
9a799d71 1443
712744be 1444 /* Rx csum disabled */
8a0da21b 1445 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1446 return;
e59bd25d 1447
3f207800
DS		 1448 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1449 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1450 encap_pkt = true;
1451 skb->encapsulation = 1;
3f207800
DS		 1452 }
1453
e59bd25d 1454 /* if IP and error */
f56e0cb1
AD		 1455 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1456 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1457 ring->rx_stats.csum_err++;
9a799d71
AK		 1458 return;
1459 }
e59bd25d 1460
f56e0cb1 1461 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1462 return;
1463
f56e0cb1 1464 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1465 /*
1466 * 82599 errata, UDP frames with a 0 checksum can be marked as
1467 * checksum errors.
1468 */
8a0da21b
AD		 1469 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1470 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1471 return;
1472
8a0da21b 1473 ring->rx_stats.csum_err++;
e59bd25d
AV		 1474 return;
1475 }
1476
9a799d71 1477 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1478 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1479 if (encap_pkt) {
1480 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1481 return;
1482
1483 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1484 ring->rx_stats.csum_err++;
1485 return;
1486 }
1487 /* If we checked the outer header let the stack know */
1488 skb->csum_level = 1;
1489 }
9a799d71
AK		 1490}
1491
f990b79b
AD		 1492static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1493 struct ixgbe_rx_buffer *bi)
1494{
1495 struct page *page = bi->page;
18cb652a 1496 dma_addr_t dma;
f990b79b 1497
f800326d 1498 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1499 if (likely(page))
f990b79b
AD		 1500 return true;
1501
f800326d 1502 /* alloc new page for storage */
18cb652a
AD		 1503 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1504 if (unlikely(!page)) {
1505 rx_ring->rx_stats.alloc_rx_page_failed++;
1506 return false;
f990b79b
AD		 1507 }
1508
f800326d
AD		 1509 /* map page for use */
1510 dma = dma_map_page(rx_ring->dev, page, 0,
1511 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1512
1513 /*
1514 * if mapping failed free memory back to system since
1515 * there isn't much point in holding memory we can't use
1516 */
1517 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1518 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1519
f990b79b
AD		 1520 rx_ring->rx_stats.alloc_rx_page_failed++;
1521 return false;
1522 }
1523
f800326d 1524 bi->dma = dma;
18cb652a 1525 bi->page = page;
afaa9459 1526 bi->page_offset = 0;
f800326d 1527
f990b79b
AD		 1528 return true;
1529}
1530
9a799d71 1531/**
f990b79b 1532 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1533 * @rx_ring: ring to place buffers on
1534 * @cleaned_count: number of buffers to replace
9a799d71 1535 **/
fc77dc3c 1536void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1537{
9a799d71 1538 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1539 struct ixgbe_rx_buffer *bi;
d5f398ed 1540 u16 i = rx_ring->next_to_use;
9a799d71 1541
f800326d
AD		 1542 /* nothing to do */
1543 if (!cleaned_count)
fc77dc3c
AD		 1544 return;
1545
e4f74028 1546 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1547 bi = &rx_ring->rx_buffer_info[i];
1548 i -= rx_ring->count;
9a799d71 1549
f800326d
AD		 1550 do {
1551 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1552 break;
d5f398ed 1553
f800326d
AD		 1554 /*
1555 * Refresh the desc even if buffer_addrs didn't change
1556 * because each write-back erases this info.
1557 */
1558 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1559
f990b79b
AD		 1560 rx_desc++;
1561 bi++;
9a799d71 1562 i++;
f990b79b 1563 if (unlikely(!i)) {
e4f74028 1564 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1565 bi = rx_ring->rx_buffer_info;
1566 i -= rx_ring->count;
1567 }
1568
18cb652a
AD		 1569 /* clear the status bits for the next_to_use descriptor */
1570 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1571
1572 cleaned_count--;
1573 } while (cleaned_count);
7c6e0a43 1574
f990b79b
AD		 1575 i += rx_ring->count;
1576
ad435ec6
AD		 1577 if (rx_ring->next_to_use != i) {
1578 rx_ring->next_to_use = i;
1579
1580 /* update next to alloc since we have filled the ring */
1581 rx_ring->next_to_alloc = i;
1582
1583 /* Force memory writes to complete before letting h/w
1584 * know there are new descriptors to fetch. (Only
1585 * applicable for weak-ordered memory model archs,
1586 * such as IA-64).
1587 */
1588 wmb();
1589 writel(i, rx_ring->tail);
1590 }
9a799d71
AK		 1591}
1592
1d2024f6
AD		 1593static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1594 struct sk_buff *skb)
1595{
f800326d 1596 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1597
1598 /* set gso_size to avoid messing up TCP MSS */
1599 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1600 IXGBE_CB(skb)->append_cnt);
96be80ab 1601 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1602}
1603
1604static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1605 struct sk_buff *skb)
1606{
1607 /* if append_cnt is 0 then frame is not RSC */
1608 if (!IXGBE_CB(skb)->append_cnt)
1609 return;
1610
1611 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1612 rx_ring->rx_stats.rsc_flush++;
1613
1614 ixgbe_set_rsc_gso_size(rx_ring, skb);
1615
1616 /* gso_size is computed using append_cnt so always clear it last */
1617 IXGBE_CB(skb)->append_cnt = 0;
1618}
1619
8a0da21b
AD		 1620/**
1621 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1622 * @rx_ring: rx descriptor ring packet is being transacted on
1623 * @rx_desc: pointer to the EOP Rx descriptor
1624 * @skb: pointer to current skb being populated
f8212f97 1625 *
8a0da21b
AD		 1626 * This function checks the ring, descriptor, and packet information in
1627 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1628 * other fields within the skb.
f8212f97 1629 **/
8a0da21b
AD		 1630static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1631 union ixgbe_adv_rx_desc *rx_desc,
1632 struct sk_buff *skb)
f8212f97 1633{
43e95f11
JF		 1634 struct net_device *dev = rx_ring->netdev;
1635
8a0da21b
AD		 1636 ixgbe_update_rsc_stats(rx_ring, skb);
1637
1638 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1639
8a0da21b
AD		 1640 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1641
eda183c2
JK		 1642 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1643 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1644
f646968f 1645 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1646 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1647 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1648 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1649 }
1650
8a0da21b 1651 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1652
43e95f11 1653 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1654}
1655
8a0da21b
AD		 1656static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1657 struct sk_buff *skb)
aa80175a 1658{
93f93a44 1659 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1660 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1661 netif_receive_skb(skb);
8a0da21b 1662 else
856f606e 1663 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1664}
43634e82 1665
f800326d
AD		 1666/**
1667 * ixgbe_is_non_eop - process handling of non-EOP buffers
1668 * @rx_ring: Rx ring being processed
1669 * @rx_desc: Rx descriptor for current buffer
1670 * @skb: Current socket buffer containing buffer in progress
1671 *
1672 * This function updates next to clean. If the buffer is an EOP buffer
1673 * this function exits returning false, otherwise it will place the
1674 * sk_buff in the next buffer to be chained and return true indicating
1675 * that this is in fact a non-EOP buffer.
1676 **/
1677static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1678 union ixgbe_adv_rx_desc *rx_desc,
1679 struct sk_buff *skb)
1680{
1681 u32 ntc = rx_ring->next_to_clean + 1;
1682
1683 /* fetch, update, and store next to clean */
1684 ntc = (ntc < rx_ring->count) ? ntc : 0;
1685 rx_ring->next_to_clean = ntc;
1686
1687 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1688
5a02cbd1
AD		 1689 /* update RSC append count if present */
1690 if (ring_is_rsc_enabled(rx_ring)) {
1691 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1692 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1693
1694 if (unlikely(rsc_enabled)) {
1695 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1696
1697 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1698 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1699
5a02cbd1
AD		 1700 /* update ntc based on RSC value */
1701 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1702 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1703 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1704 }
f800326d
AD		 1705 }
1706
5a02cbd1
AD		 1707 /* if we are the last buffer then there is nothing else to do */
1708 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1709 return false;
1710
f800326d
AD		 1711 /* place skb in next buffer to be received */
1712 rx_ring->rx_buffer_info[ntc].skb = skb;
1713 rx_ring->rx_stats.non_eop_descs++;
1714
1715 return true;
1716}
1717
19861ce2
AD		 1718/**
1719 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1720 * @rx_ring: rx descriptor ring packet is being transacted on
1721 * @skb: pointer to current skb being adjusted
1722 *
1723 * This function is an ixgbe specific version of __pskb_pull_tail. The
1724 * main difference between this version and the original function is that
1725 * this function can make several assumptions about the state of things
1726 * that allow for significant optimizations versus the standard function.
1727 * As a result we can do things like drop a frag and maintain an accurate
1728 * truesize for the skb.
1729 */
1730static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1731 struct sk_buff *skb)
1732{
1733 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1734 unsigned char *va;
1735 unsigned int pull_len;
1736
1737 /*
1738 * it is valid to use page_address instead of kmap since we are
1739 * working with pages allocated out of the lomem pool per
1740 * alloc_page(GFP_ATOMIC)
1741 */
1742 va = skb_frag_address(frag);
1743
1744 /*
1745 * we need the header to contain the greater of either ETH_HLEN or
1746 * 60 bytes if the skb->len is less than 60 for skb_pad.
1747 */
8496e338 1748 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1749
1750 /* align pull length to size of long to optimize memcpy performance */
1751 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1752
1753 /* update all of the pointers */
1754 skb_frag_size_sub(frag, pull_len);
1755 frag->page_offset += pull_len;
1756 skb->data_len -= pull_len;
1757 skb->tail += pull_len;
19861ce2
AD		 1758}
1759
42073d91
AD		 1760/**
1761 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1762 * @rx_ring: rx descriptor ring packet is being transacted on
1763 * @skb: pointer to current skb being updated
1764 *
1765 * This function provides a basic DMA sync up for the first fragment of an
1766 * skb. The reason for doing this is that the first fragment cannot be
1767 * unmapped until we have reached the end of packet descriptor for a buffer
1768 * chain.
1769 */
1770static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1771 struct sk_buff *skb)
1772{
1773 /* if the page was released unmap it, else just sync our portion */
1774 if (unlikely(IXGBE_CB(skb)->page_released)) {
1775 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1776 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1777 IXGBE_CB(skb)->page_released = false;
1778 } else {
1779 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1780
1781 dma_sync_single_range_for_cpu(rx_ring->dev,
1782 IXGBE_CB(skb)->dma,
1783 frag->page_offset,
1784 ixgbe_rx_bufsz(rx_ring),
1785 DMA_FROM_DEVICE);
1786 }
1787 IXGBE_CB(skb)->dma = 0;
1788}
1789
f800326d
AD		 1790/**
1791 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1792 * @rx_ring: rx descriptor ring packet is being transacted on
1793 * @rx_desc: pointer to the EOP Rx descriptor
1794 * @skb: pointer to current skb being fixed
1795 *
1796 * Check for corrupted packet headers caused by senders on the local L2
1797 * embedded NIC switch not setting up their Tx Descriptors right. These
1798 * should be very rare.
1799 *
1800 * Also address the case where we are pulling data in on pages only
1801 * and as such no data is present in the skb header.
1802 *
1803 * In addition if skb is not at least 60 bytes we need to pad it so that
1804 * it is large enough to qualify as a valid Ethernet frame.
1805 *
1806 * Returns true if an error was encountered and skb was freed.
1807 **/
1808static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1809 union ixgbe_adv_rx_desc *rx_desc,
1810 struct sk_buff *skb)
1811{
f800326d 1812 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1813
1814 /* verify that the packet does not have any known errors */
1815 if (unlikely(ixgbe_test_staterr(rx_desc,
1816 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1817 !(netdev->features & NETIF_F_RXALL))) {
1818 dev_kfree_skb_any(skb);
1819 return true;
1820 }
1821
19861ce2 1822 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1823 if (skb_is_nonlinear(skb))
1824 ixgbe_pull_tail(rx_ring, skb);
f800326d 1825
57efd44c
AD		 1826#ifdef IXGBE_FCOE
1827 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1828 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1829 return false;
1830
1831#endif
a94d9e22
AD		 1832 /* if eth_skb_pad returns an error the skb was freed */
1833 if (eth_skb_pad(skb))
1834 return true;
f800326d
AD		 1835
1836 return false;
1837}
1838
f800326d
AD		 1839/**
1840 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1841 * @rx_ring: rx descriptor ring to store buffers on
1842 * @old_buff: donor buffer to have page reused
1843 *
0549ae20 1844 * Synchronizes page for reuse by the adapter
f800326d
AD		 1845 **/
1846static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1847 struct ixgbe_rx_buffer *old_buff)
1848{
1849 struct ixgbe_rx_buffer *new_buff;
1850 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1851
1852 new_buff = &rx_ring->rx_buffer_info[nta];
1853
1854 /* update, and store next to alloc */
1855 nta++;
1856 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1857
1858 /* transfer page from old buffer to new buffer */
18cb652a 1859 *new_buff = *old_buff;
f800326d
AD		 1860
1861 /* sync the buffer for use by the device */
1862 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1863 new_buff->page_offset,
1864 ixgbe_rx_bufsz(rx_ring),
f800326d 1865 DMA_FROM_DEVICE);
f800326d
AD		 1866}
1867
18cb652a
AD		 1868static inline bool ixgbe_page_is_reserved(struct page *page)
1869{
2f064f34 1870 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1871}
1872
f800326d
AD		 1873/**
1874 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1875 * @rx_ring: rx descriptor ring to transact packets on
1876 * @rx_buffer: buffer containing page to add
1877 * @rx_desc: descriptor containing length of buffer written by hardware
1878 * @skb: sk_buff to place the data into
1879 *
0549ae20
AD		 1880 * This function will add the data contained in rx_buffer->page to the skb.
1881 * This is done either through a direct copy if the data in the buffer is
1882 * less than the skb header size, otherwise it will just attach the page as
1883 * a frag to the skb.
1884 *
1885 * The function will then update the page offset if necessary and return
1886 * true if the buffer can be reused by the adapter.
f800326d 1887 **/
0549ae20 1888static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1889 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1890 union ixgbe_adv_rx_desc *rx_desc,
1891 struct sk_buff *skb)
f800326d 1892{
0549ae20
AD		 1893 struct page *page = rx_buffer->page;
1894 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1895#if (PAGE_SIZE < 8192)
0549ae20 1896 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1897#else
1898 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1899 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1900 ixgbe_rx_bufsz(rx_ring);
1901#endif
0549ae20 1902
cf3fe7ac
AD		 1903 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1904 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1905
1906 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1907
18cb652a
AD		 1908 /* page is not reserved, we can reuse buffer as-is */
1909 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1910 return true;
1911
1912 /* this page cannot be reused so discard it */
18cb652a 1913 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1914 return false;
1915 }
1916
0549ae20
AD		 1917 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1918 rx_buffer->page_offset, size, truesize);
1919
09816fbe 1920 /* avoid re-using remote pages */
18cb652a 1921 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1922 return false;
1923
1924#if (PAGE_SIZE < 8192)
1925 /* if we are only owner of page we can reuse it */
1926 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1927 return false;
1928
1929 /* flip page offset to other buffer */
1930 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1931#else
1932 /* move offset up to the next cache line */
1933 rx_buffer->page_offset += truesize;
1934
1935 if (rx_buffer->page_offset > last_offset)
1936 return false;
09816fbe 1937#endif
0549ae20 1938
18cb652a
AD		 1939 /* Even if we own the page, we are not allowed to use atomic_set()
1940 * This would break get_page_unless_zero() users.
1941 */
1942 atomic_inc(&page->_count);
1943
0549ae20 1944 return true;
f800326d
AD		 1945}
1946
18806c9e
AD		 1947static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1948 union ixgbe_adv_rx_desc *rx_desc)
1949{
1950 struct ixgbe_rx_buffer *rx_buffer;
1951 struct sk_buff *skb;
1952 struct page *page;
1953
1954 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1955 page = rx_buffer->page;
1956 prefetchw(page);
1957
1958 skb = rx_buffer->skb;
1959
1960 if (likely(!skb)) {
1961 void *page_addr = page_address(page) +
1962 rx_buffer->page_offset;
1963
1964 /* prefetch first cache line of first page */
1965 prefetch(page_addr);
1966#if L1_CACHE_BYTES < 128
1967 prefetch(page_addr + L1_CACHE_BYTES);
1968#endif
1969
1970 /* allocate a skb to store the frags */
67fd893e
AD		 1971 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1972 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1973 if (unlikely(!skb)) {
1974 rx_ring->rx_stats.alloc_rx_buff_failed++;
1975 return NULL;
1976 }
1977
1978 /*
1979 * we will be copying header into skb->data in
1980 * pskb_may_pull so it is in our interest to prefetch
1981 * it now to avoid a possible cache miss
1982 */
1983 prefetchw(skb->data);
1984
1985 /*
1986 * Delay unmapping of the first packet. It carries the
1987 * header information, HW may still access the header
1988 * after the writeback. Only unmap it when EOP is
1989 * reached
1990 */
1991 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1992 goto dma_sync;
1993
1994 IXGBE_CB(skb)->dma = rx_buffer->dma;
1995 } else {
1996 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1997 ixgbe_dma_sync_frag(rx_ring, skb);
1998
1999dma_sync:
2000 /* we are reusing so sync this buffer for CPU use */
2001 dma_sync_single_range_for_cpu(rx_ring->dev,
2002 rx_buffer->dma,
2003 rx_buffer->page_offset,
2004 ixgbe_rx_bufsz(rx_ring),
2005 DMA_FROM_DEVICE);
18cb652a
AD		 2006
2007 rx_buffer->skb = NULL;
18806c9e
AD		 2008 }
2009
2010 /* pull page into skb */
2011 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2012 /* hand second half of page back to the ring */
2013 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2014 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2015 /* the page has been released from the ring */
2016 IXGBE_CB(skb)->page_released = true;
2017 } else {
2018 /* we are not reusing the buffer so unmap it */
2019 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2020 ixgbe_rx_pg_size(rx_ring),
2021 DMA_FROM_DEVICE);
2022 }
2023
2024 /* clear contents of buffer_info */
18806c9e
AD		 2025 rx_buffer->page = NULL;
2026
2027 return skb;
f800326d
AD		 2028}
2029
2030/**
2031 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2032 * @q_vector: structure containing interrupt and ring information
2033 * @rx_ring: rx descriptor ring to transact packets on
2034 * @budget: Total limit on number of packets to process
2035 *
2036 * This function provides a "bounce buffer" approach to Rx interrupt
2037 * processing. The advantage to this is that on systems that have
2038 * expensive overhead for IOMMU access this provides a means of avoiding
2039 * it by maintaining the mapping of the page to the syste.
2040 *
5a85e737 2041 * Returns amount of work completed
f800326d 2042 **/
5a85e737 2043static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2044 struct ixgbe_ring *rx_ring,
f4de00ed 2045 const int budget)
9a799d71 2046{
d2f4fbe2 2047 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2048#ifdef IXGBE_FCOE
f800326d 2049 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2050 int ddp_bytes;
2051 unsigned int mss = 0;
3d8fd385 2052#endif /* IXGBE_FCOE */
f800326d 2053 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2054
fdabfc8a 2055 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2056 union ixgbe_adv_rx_desc *rx_desc;
2057 struct sk_buff *skb;
f800326d
AD		 2058
2059 /* return some buffers to hardware, one at a time is too slow */
2060 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2061 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2062 cleaned_count = 0;
2063 }
2064
18806c9e 2065 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2066
124b74c1 2067 if (!rx_desc->wb.upper.status_error)
f800326d 2068 break;
9a799d71 2069
124b74c1 2070 /* This memory barrier is needed to keep us from reading
f800326d 2071 * any other fields out of the rx_desc until we know the
124b74c1 2072 * descriptor has been written back
f800326d 2073 */
124b74c1 2074 dma_rmb();
9a799d71 2075
18806c9e
AD		 2076 /* retrieve a buffer from the ring */
2077 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2078
18806c9e
AD		 2079 /* exit if we failed to retrieve a buffer */
2080 if (!skb)
2081 break;
9a799d71 2082
9a799d71 2083 cleaned_count++;
f8212f97 2084
f800326d
AD		 2085 /* place incomplete frames back on ring for completion */
2086 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2087 continue;
c267fc16 2088
f800326d
AD		 2089 /* verify the packet layout is correct */
2090 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2091 continue;
9a799d71 2092
d2f4fbe2
AV		 2093 /* probably a little skewed due to removing CRC */
2094 total_rx_bytes += skb->len;
d2f4fbe2 2095
8a0da21b
AD		 2096 /* populate checksum, timestamp, VLAN, and protocol */
2097 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2098
332d4a7d
YZ		 2099#ifdef IXGBE_FCOE
2100 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2101 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2102 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2103 /* include DDPed FCoE data */
2104 if (ddp_bytes > 0) {
2105 if (!mss) {
2106 mss = rx_ring->netdev->mtu -
2107 sizeof(struct fcoe_hdr) -
2108 sizeof(struct fc_frame_header) -
2109 sizeof(struct fcoe_crc_eof);
2110 if (mss > 512)
2111 mss &= ~511;
2112 }
2113 total_rx_bytes += ddp_bytes;
2114 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2115 mss);
2116 }
63d635b2
AD		 2117 if (!ddp_bytes) {
2118 dev_kfree_skb_any(skb);
f800326d 2119 continue;
63d635b2 2120 }
3d8fd385 2121 }
f800326d 2122
332d4a7d 2123#endif /* IXGBE_FCOE */
8a0da21b 2124 ixgbe_rx_skb(q_vector, skb);
9a799d71 2125
f800326d 2126 /* update budget accounting */
f4de00ed 2127 total_rx_packets++;
fdabfc8a 2128 }
9a799d71 2129
c267fc16
AD		 2130 u64_stats_update_begin(&rx_ring->syncp);
2131 rx_ring->stats.packets += total_rx_packets;
2132 rx_ring->stats.bytes += total_rx_bytes;
2133 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2134 q_vector->rx.total_packets += total_rx_packets;
2135 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2136
5a85e737 2137 return total_rx_packets;
9a799d71
AK		 2138}
2139
e0d1095a 2140#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2141/* must be called with local_bh_disable()d */
2142static int ixgbe_low_latency_recv(struct napi_struct *napi)
2143{
2144 struct ixgbe_q_vector *q_vector =
2145 container_of(napi, struct ixgbe_q_vector, napi);
2146 struct ixgbe_adapter *adapter = q_vector->adapter;
2147 struct ixgbe_ring *ring;
2148 int found = 0;
2149
2150 if (test_bit(__IXGBE_DOWN, &adapter->state))
2151 return LL_FLUSH_FAILED;
2152
2153 if (!ixgbe_qv_lock_poll(q_vector))
2154 return LL_FLUSH_BUSY;
2155
2156 ixgbe_for_each_ring(ring, q_vector->rx) {
2157 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2158#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2159 if (found)
2160 ring->stats.cleaned += found;
2161 else
2162 ring->stats.misses++;
2163#endif
5a85e737
ET		 2164 if (found)
2165 break;
2166 }
2167
2168 ixgbe_qv_unlock_poll(q_vector);
2169
2170 return found;
2171}
e0d1095a 2172#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2173
9a799d71
AK		 2174/**
2175 * ixgbe_configure_msix - Configure MSI-X hardware
2176 * @adapter: board private structure
2177 *
2178 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2179 * interrupts.
2180 **/
2181static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2182{
021230d4 2183 struct ixgbe_q_vector *q_vector;
49c7ffbe 2184 int v_idx;
021230d4 2185 u32 mask;
9a799d71 2186
8e34d1aa
AD		 2187 /* Populate MSIX to EITR Select */
2188 if (adapter->num_vfs > 32) {
2189 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2190 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2191 }
2192
4df10466
JB		 2193 /*
2194 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2195 * corresponding register.
2196 */
49c7ffbe 2197 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2198 struct ixgbe_ring *ring;
7a921c93 2199 q_vector = adapter->q_vector[v_idx];
021230d4 2200
a557928e 2201 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2202 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2203
a557928e 2204 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2205 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2206
fe49f04a 2207 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2208 }
2209
bd508178
AD		 2210 switch (adapter->hw.mac.type) {
2211 case ixgbe_mac_82598EB:
e8e26350 2212 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2213 v_idx);
bd508178
AD		 2214 break;
2215 case ixgbe_mac_82599EB:
b93a2226 2216 case ixgbe_mac_X540:
9a75a1ac
DS		 2217 case ixgbe_mac_X550:
2218 case ixgbe_mac_X550EM_x:
e8e26350 2219 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2220 break;
bd508178
AD		 2221 default:
2222 break;
2223 }
021230d4
AV		 2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2225
41fb9248 2226 /* set up to autoclear timer, and the vectors */
021230d4 2227 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2228 mask &= ~(IXGBE_EIMS_OTHER |
2229 IXGBE_EIMS_MAILBOX |
2230 IXGBE_EIMS_LSC);
2231
021230d4 2232 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2233}
2234
f494e8fa
AV		 2235enum latency_range {
2236 lowest_latency = 0,
2237 low_latency = 1,
2238 bulk_latency = 2,
2239 latency_invalid = 255
2240};
2241
2242/**
2243 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2244 * @q_vector: structure containing interrupt and ring information
2245 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2246 *
2247 * Stores a new ITR value based on packets and byte
2248 * counts during the last interrupt. The advantage of per interrupt
2249 * computation is faster updates and more accurate ITR for the current
2250 * traffic pattern. Constants in this function were computed
2251 * based on theoretical maximum wire speed and thresholds were set based
2252 * on testing data as well as attempting to minimize response time
2253 * while increasing bulk throughput.
2254 * this functionality is controlled by the InterruptThrottleRate module
2255 * parameter (see ixgbe_param.c)
2256 **/
bd198058
AD		 2257static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2258 struct ixgbe_ring_container *ring_container)
f494e8fa 2259{
bd198058
AD		 2260 int bytes = ring_container->total_bytes;
2261 int packets = ring_container->total_packets;
2262 u32 timepassed_us;
621bd70e 2263 u64 bytes_perint;
bd198058 2264 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2265
2266 if (packets == 0)
bd198058 2267 return;
f494e8fa
AV		 2268
2269 /* simple throttlerate management
621bd70e
AD		 2270 * 0-10MB/s lowest (100000 ints/s)
2271 * 10-20MB/s low (20000 ints/s)
8ac34f10 2272 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2273 */
2274 /* what was last interrupt timeslice? */
d5bf4f67 2275 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2276 if (timepassed_us == 0)
2277 return;
2278
f494e8fa
AV		 2279 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2280
2281 switch (itr_setting) {
2282 case lowest_latency:
621bd70e 2283 if (bytes_perint > 10)
bd198058 2284 itr_setting = low_latency;
f494e8fa
AV		 2285 break;
2286 case low_latency:
621bd70e 2287 if (bytes_perint > 20)
bd198058 2288 itr_setting = bulk_latency;
621bd70e 2289 else if (bytes_perint <= 10)
bd198058 2290 itr_setting = lowest_latency;
f494e8fa
AV		 2291 break;
2292 case bulk_latency:
621bd70e 2293 if (bytes_perint <= 20)
bd198058 2294 itr_setting = low_latency;
f494e8fa
AV		 2295 break;
2296 }
2297
bd198058
AD		 2298 /* clear work counters since we have the values we need */
2299 ring_container->total_bytes = 0;
2300 ring_container->total_packets = 0;
2301
2302 /* write updated itr to ring container */
2303 ring_container->itr = itr_setting;
f494e8fa
AV		 2304}
2305
509ee935
JB		 2306/**
2307 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2308 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2309 *
2310 * This function is made to be called by ethtool and by the driver
2311 * when it needs to update EITR registers at runtime. Hardware
2312 * specific quirks/differences are taken care of here.
2313 */
fe49f04a 2314void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2315{
fe49f04a 2316 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2317 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2318 int v_idx = q_vector->v_idx;
5d967eb7 2319 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2320
bd508178
AD		 2321 switch (adapter->hw.mac.type) {
2322 case ixgbe_mac_82598EB:
509ee935
JB		 2323 /* must write high and low 16 bits to reset counter */
2324 itr_reg |= (itr_reg << 16);
bd508178
AD		 2325 break;
2326 case ixgbe_mac_82599EB:
b93a2226 2327 case ixgbe_mac_X540:
9a75a1ac
DS		 2328 case ixgbe_mac_X550:
2329 case ixgbe_mac_X550EM_x:
509ee935
JB		 2330 /*
2331 * set the WDIS bit to not clear the timer bits and cause an
2332 * immediate assertion of the interrupt
2333 */
2334 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2335 break;
2336 default:
2337 break;
509ee935
JB		 2338 }
2339 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2340}
2341
bd198058 2342static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2343{
d5bf4f67 2344 u32 new_itr = q_vector->itr;
bd198058 2345 u8 current_itr;
f494e8fa 2346
bd198058
AD		 2347 ixgbe_update_itr(q_vector, &q_vector->tx);
2348 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2349
08c8833b 2350 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2351
2352 switch (current_itr) {
2353 /* counts and packets in update_itr are dependent on these numbers */
2354 case lowest_latency:
d5bf4f67 2355 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2356 break;
2357 case low_latency:
d5bf4f67 2358 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2359 break;
2360 case bulk_latency:
8ac34f10 2361 new_itr = IXGBE_12K_ITR;
f494e8fa 2362 break;
bd198058
AD		 2363 default:
2364 break;
f494e8fa
AV		 2365 }
2366
d5bf4f67 2367 if (new_itr != q_vector->itr) {
fe49f04a 2368 /* do an exponential smoothing */
d5bf4f67
ET		 2369 new_itr = (10 * new_itr * q_vector->itr) /
2370 ((9 * new_itr) + q_vector->itr);
509ee935 2371
bd198058 2372 /* save the algorithm value here */
5d967eb7 2373 q_vector->itr = new_itr;
fe49f04a
AD		 2374
2375 ixgbe_write_eitr(q_vector);
f494e8fa 2376 }
f494e8fa
AV		 2377}
2378
119fc60a 2379/**
de88eeeb 2380 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2381 * @adapter: pointer to adapter
119fc60a 2382 **/
f0f9778d 2383static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2384{
119fc60a
MC		 2385 struct ixgbe_hw *hw = &adapter->hw;
2386 u32 eicr = adapter->interrupt_event;
2387
f0f9778d 2388 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2389 return;
2390
f0f9778d
AD		 2391 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2392 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2393 return;
2394
2395 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2396
7ca647bd 2397 switch (hw->device_id) {
f0f9778d
AD		 2398 case IXGBE_DEV_ID_82599_T3_LOM:
2399 /*
2400 * Since the warning interrupt is for both ports
2401 * we don't have to check if:
2402 * - This interrupt wasn't for our port.
2403 * - We may have missed the interrupt so always have to
2404 * check if we got a LSC
2405 */
9a900eca 2406 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2407 !(eicr & IXGBE_EICR_LSC))
2408 return;
2409
2410 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2411 u32 speed;
f0f9778d 2412 bool link_up = false;
7ca647bd 2413
3d292265 2414 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2415
f0f9778d
AD		 2416 if (link_up)
2417 return;
2418 }
2419
2420 /* Check if this is not due to overtemp */
2421 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2422 return;
2423
2424 break;
7ca647bd 2425 default:
597f22d6
DS		 2426 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2427 return;
9a900eca 2428 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2429 return;
7ca647bd 2430 break;
119fc60a 2431 }
f44e751b 2432 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2433
2434 adapter->interrupt_event = 0;
119fc60a
MC		 2435}
2436
0befdb3e
JB		 2437static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2438{
2439 struct ixgbe_hw *hw = &adapter->hw;
2440
2441 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2442 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2443 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2444 /* write to clear the interrupt */
9a900eca 2445 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2446 }
2447}
cf8280ee 2448
4f51bf70
JK		 2449static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2450{
9a900eca
DS		 2451 struct ixgbe_hw *hw = &adapter->hw;
2452
4f51bf70
JK		 2453 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2454 return;
2455
2456 switch (adapter->hw.mac.type) {
2457 case ixgbe_mac_82599EB:
2458 /*
2459 * Need to check link state so complete overtemp check
2460 * on service task
2461 */
9a900eca
DS		 2462 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2463 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2464 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2465 adapter->interrupt_event = eicr;
2466 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2467 ixgbe_service_event_schedule(adapter);
2468 return;
2469 }
2470 return;
2471 case ixgbe_mac_X540:
2472 if (!(eicr & IXGBE_EICR_TS))
2473 return;
2474 break;
2475 default:
2476 return;
2477 }
2478
f44e751b 2479 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2480}
2481
45788d2a
DS		 2482static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2483{
2484 switch (hw->mac.type) {
2485 case ixgbe_mac_82598EB:
2486 if (hw->phy.type == ixgbe_phy_nl)
2487 return true;
2488 return false;
2489 case ixgbe_mac_82599EB:
2490 case ixgbe_mac_X550EM_x:
2491 switch (hw->mac.ops.get_media_type(hw)) {
2492 case ixgbe_media_type_fiber:
2493 case ixgbe_media_type_fiber_qsfp:
2494 return true;
2495 default:
2496 return false;
2497 }
2498 default:
2499 return false;
2500 }
2501}
2502
e8e26350
PW		 2503static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2504{
2505 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2506 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2507
4ccc650c
DS		 2508 if (!ixgbe_is_sfp(hw))
2509 return;
2510
2511 /* Later MAC's use different SDP */
2512 if (hw->mac.type >= ixgbe_mac_X540)
2513 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2514
2515 if (eicr & eicr_mask) {
73c4b7cd 2516 /* Clear the interrupt */
4ccc650c 2517 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2518 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2519 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2520 adapter->sfp_poll_time = 0;
7086400d
AD		 2521 ixgbe_service_event_schedule(adapter);
2522 }
73c4b7cd
AD		 2523 }
2524
4ccc650c
DS		 2525 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2526 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2527 /* Clear the interrupt */
9a900eca 2528 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2529 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2530 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2531 ixgbe_service_event_schedule(adapter);
2532 }
e8e26350
PW		 2533 }
2534}
2535
cf8280ee
JB		 2536static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2537{
2538 struct ixgbe_hw *hw = &adapter->hw;
2539
2540 adapter->lsc_int++;
2541 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2542 adapter->link_check_timeout = jiffies;
2543 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2544 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2545 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2546 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2547 }
2548}
2549
fe49f04a
AD		 2550static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2551 u64 qmask)
2552{
2553 u32 mask;
bd508178 2554 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2555
bd508178
AD		 2556 switch (hw->mac.type) {
2557 case ixgbe_mac_82598EB:
fe49f04a 2558 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2559 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2560 break;
2561 case ixgbe_mac_82599EB:
b93a2226 2562 case ixgbe_mac_X540:
9a75a1ac
DS		 2563 case ixgbe_mac_X550:
2564 case ixgbe_mac_X550EM_x:
fe49f04a 2565 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2566 if (mask)
2567 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2568 mask = (qmask >> 32);
bd508178
AD		 2569 if (mask)
2570 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2571 break;
2572 default:
2573 break;
fe49f04a
AD		 2574 }
2575 /* skip the flush */
2576}
2577
2578static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2579 u64 qmask)
fe49f04a
AD		 2580{
2581 u32 mask;
bd508178 2582 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2583
bd508178
AD		 2584 switch (hw->mac.type) {
2585 case ixgbe_mac_82598EB:
fe49f04a 2586 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2587 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2588 break;
2589 case ixgbe_mac_82599EB:
b93a2226 2590 case ixgbe_mac_X540:
9a75a1ac
DS		 2591 case ixgbe_mac_X550:
2592 case ixgbe_mac_X550EM_x:
fe49f04a 2593 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2594 if (mask)
2595 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2596 mask = (qmask >> 32);
bd508178
AD		 2597 if (mask)
2598 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2599 break;
2600 default:
2601 break;
fe49f04a
AD		 2602 }
2603 /* skip the flush */
2604}
2605
021230d4 2606/**
2c4af694
AD		 2607 * ixgbe_irq_enable - Enable default interrupt generation settings
2608 * @adapter: board private structure
021230d4 2609 **/
2c4af694
AD		 2610static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2611 bool flush)
9a799d71 2612{
9a900eca 2613 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2614 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2615
2c4af694
AD		 2616 /* don't reenable LSC while waiting for link */
2617 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2618 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2619
2c4af694 2620 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2621 switch (adapter->hw.mac.type) {
2622 case ixgbe_mac_82599EB:
9a900eca 2623 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2624 break;
2625 case ixgbe_mac_X540:
9a75a1ac
DS		 2626 case ixgbe_mac_X550:
2627 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2628 mask |= IXGBE_EIMS_TS;
2629 break;
2630 default:
2631 break;
2632 }
2c4af694 2633 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2634 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2635 switch (adapter->hw.mac.type) {
2636 case ixgbe_mac_82599EB:
9a900eca
DS		 2637 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2638 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2639 /* fall through */
858bc081 2640 case ixgbe_mac_X540:
9a75a1ac
DS		 2641 case ixgbe_mac_X550:
2642 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2643 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2644 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2645 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2646 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2647 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2648 mask |= IXGBE_EIMS_MAILBOX;
2649 break;
2650 default:
2651 break;
9a799d71 2652 }
db0677fa 2653
2c4af694
AD		 2654 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2655 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2656 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2657
2c4af694
AD		 2658 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2659 if (queues)
2660 ixgbe_irq_enable_queues(adapter, ~0);
2661 if (flush)
2662 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2663}
2664
2c4af694 2665static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2666{
a65151ba 2667 struct ixgbe_adapter *adapter = data;
9a799d71 2668 struct ixgbe_hw *hw = &adapter->hw;
54037505 2669 u32 eicr;
91281fd3 2670
54037505
DS		 2671 /*
2672 * Workaround for Silicon errata. Use clear-by-write instead
2673 * of clear-by-read. Reading with EICS will return the
2674 * interrupt causes without clearing, which later be done
2675 * with the write to EICR.
2676 */
2677 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2678
2679 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2680 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2681 * the bits are high when ixgbe_msix_other is called. There is a race
2682 * condition otherwise which results in possible performance loss
2683 * especially if the ixgbe_msix_other interrupt is triggering
2684 * consistently (as it would when PPS is turned on for the X540 device)
2685 */
2686 eicr &= 0xFFFF0000;
2687
54037505 2688 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2689
cf8280ee
JB		 2690 if (eicr & IXGBE_EICR_LSC)
2691 ixgbe_check_lsc(adapter);
f0848276 2692
1cdd1ec8
GR		 2693 if (eicr & IXGBE_EICR_MAILBOX)
2694 ixgbe_msg_task(adapter);
efe3d3c8 2695
bd508178
AD		 2696 switch (hw->mac.type) {
2697 case ixgbe_mac_82599EB:
b93a2226 2698 case ixgbe_mac_X540:
9a75a1ac
DS		 2699 case ixgbe_mac_X550:
2700 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2701 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2702 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2703 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2704 ixgbe_service_event_schedule(adapter);
2705 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2706 IXGBE_EICR_GPI_SDP0_X540);
2707 }
d773ce2d
DS		 2708 if (eicr & IXGBE_EICR_ECC) {
2709 e_info(link, "Received ECC Err, initiating reset\n");
2710 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2711 ixgbe_service_event_schedule(adapter);
2712 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2713 }
c4cf55e5
PWJ		 2714 /* Handle Flow Director Full threshold interrupt */
2715 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2716 int reinit_count = 0;
c4cf55e5 2717 int i;
c4cf55e5 2718 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2719 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2720 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2721 &ring->state))
2722 reinit_count++;
2723 }
2724 if (reinit_count) {
2725 /* no more flow director interrupts until after init */
2726 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2727 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2728 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2729 }
2730 }
f0f9778d 2731 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2732 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2733 break;
2734 default:
2735 break;
c4cf55e5 2736 }
f0848276 2737
bd508178 2738 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2739
db0677fa
JK		 2740 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2741 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2742
7086400d 2743 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2744 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2745 ixgbe_irq_enable(adapter, false, false);
f0848276 2746
9a799d71 2747 return IRQ_HANDLED;
f0848276 2748}
91281fd3 2749
4ff7fb12 2750static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2751{
021230d4 2752 struct ixgbe_q_vector *q_vector = data;
91281fd3 2753
9b471446 2754 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2755
4ff7fb12
AD		 2756 if (q_vector->rx.ring || q_vector->tx.ring)
2757 napi_schedule(&q_vector->napi);
91281fd3 2758
9a799d71 2759 return IRQ_HANDLED;
91281fd3
AD		 2760}
2761
eb01b975
AD		 2762/**
2763 * ixgbe_poll - NAPI Rx polling callback
2764 * @napi: structure for representing this polling device
2765 * @budget: how many packets driver is allowed to clean
2766 *
2767 * This function is used for legacy and MSI, NAPI mode
2768 **/
8af3c33f 2769int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2770{
2771 struct ixgbe_q_vector *q_vector =
2772 container_of(napi, struct ixgbe_q_vector, napi);
2773 struct ixgbe_adapter *adapter = q_vector->adapter;
2774 struct ixgbe_ring *ring;
32b3e08f 2775 int per_ring_budget, work_done = 0;
eb01b975
AD		 2776 bool clean_complete = true;
2777
2778#ifdef CONFIG_IXGBE_DCA
2779 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2780 ixgbe_update_dca(q_vector);
2781#endif
2782
2783 ixgbe_for_each_ring(ring, q_vector->tx)
2784 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2785
5d6002b7
AD		 2786 /* Exit if we are called by netpoll or busy polling is active */
2787 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2788 return budget;
2789
eb01b975
AD		 2790 /* attempt to distribute budget to each queue fairly, but don't allow
2791 * the budget to go below 1 because we'll exit polling */
2792 if (q_vector->rx.count > 1)
2793 per_ring_budget = max(budget/q_vector->rx.count, 1);
2794 else
2795 per_ring_budget = budget;
2796
32b3e08f
JB		 2797 ixgbe_for_each_ring(ring, q_vector->rx) {
2798 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2799 per_ring_budget);
2800
2801 work_done += cleaned;
2802 clean_complete &= (cleaned < per_ring_budget);
2803 }
eb01b975 2804
5a85e737 2805 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2806 /* If all work not completed, return budget and keep polling */
2807 if (!clean_complete)
2808 return budget;
2809
2810 /* all work done, exit the polling mode */
32b3e08f 2811 napi_complete_done(napi, work_done);
eb01b975
AD		 2812 if (adapter->rx_itr_setting & 1)
2813 ixgbe_set_itr(q_vector);
2814 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2815 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2816
2817 return 0;
2818}
2819
021230d4
AV		 2820/**
2821 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2822 * @adapter: board private structure
2823 *
2824 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2825 * interrupts from the kernel.
2826 **/
2827static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2828{
2829 struct net_device *netdev = adapter->netdev;
207867f5 2830 int vector, err;
e8e9f696 2831 int ri = 0, ti = 0;
021230d4 2832
49c7ffbe 2833 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2834 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2835 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2836
4ff7fb12 2837 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2838 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2839 "%s-%s-%d", netdev->name, "TxRx", ri++);
2840 ti++;
2841 } else if (q_vector->rx.ring) {
9fe93afd 2842 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2843 "%s-%s-%d", netdev->name, "rx", ri++);
2844 } else if (q_vector->tx.ring) {
9fe93afd 2845 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2846 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2847 } else {
2848 /* skip this unused q_vector */
2849 continue;
32aa77a4 2850 }
207867f5
AD		 2851 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2852 q_vector->name, q_vector);
9a799d71 2853 if (err) {
396e799c 2854 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2855 "Error: %d\n", err);
021230d4 2856 goto free_queue_irqs;
9a799d71 2857 }
207867f5
AD		 2858 /* If Flow Director is enabled, set interrupt affinity */
2859 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2860 /* assign the mask for this irq */
2861 irq_set_affinity_hint(entry->vector,
de88eeeb 2862 &q_vector->affinity_mask);
207867f5 2863 }
9a799d71
AK		 2864 }
2865
021230d4 2866 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2867 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2868 if (err) {
de88eeeb 2869 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2870 goto free_queue_irqs;
9a799d71
AK		 2871 }
2872
9a799d71
AK		 2873 return 0;
2874
021230d4 2875free_queue_irqs:
207867f5
AD		 2876 while (vector) {
2877 vector--;
2878 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2879 NULL);
2880 free_irq(adapter->msix_entries[vector].vector,
2881 adapter->q_vector[vector]);
2882 }
021230d4
AV		 2883 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2884 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2885 kfree(adapter->msix_entries);
2886 adapter->msix_entries = NULL;
9a799d71
AK		 2887 return err;
2888}
2889
2890/**
021230d4 2891 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2892 * @irq: interrupt number
2893 * @data: pointer to a network interface device structure
9a799d71
AK		 2894 **/
2895static irqreturn_t ixgbe_intr(int irq, void *data)
2896{
a65151ba 2897 struct ixgbe_adapter *adapter = data;
9a799d71 2898 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2899 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2900 u32 eicr;
2901
54037505 2902 /*
24ddd967 2903 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2904 * before the read of EICR.
2905 */
2906 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2907
021230d4 2908 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2909 * therefore no explicit interrupt disable is necessary */
021230d4 2910 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2911 if (!eicr) {
6af3b9eb
ET		 2912 /*
2913 * shared interrupt alert!
f47cf66e 2914 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2915 * have disabled interrupts due to EIAM
2916 * finish the workaround of silicon errata on 82598. Unmask
2917 * the interrupt that we masked before the EICR read.
2918 */
2919 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2920 ixgbe_irq_enable(adapter, true, true);
9a799d71 2921 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2922 }
9a799d71 2923
cf8280ee
JB		 2924 if (eicr & IXGBE_EICR_LSC)
2925 ixgbe_check_lsc(adapter);
021230d4 2926
bd508178
AD		 2927 switch (hw->mac.type) {
2928 case ixgbe_mac_82599EB:
e8e26350 2929 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2930 /* Fall through */
2931 case ixgbe_mac_X540:
9a75a1ac
DS		 2932 case ixgbe_mac_X550:
2933 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2934 if (eicr & IXGBE_EICR_ECC) {
2935 e_info(link, "Received ECC Err, initiating reset\n");
2936 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2937 ixgbe_service_event_schedule(adapter);
2938 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2939 }
4f51bf70 2940 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2941 break;
2942 default:
2943 break;
2944 }
e8e26350 2945
0befdb3e 2946 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2947 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2948 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2949
b9f6ed2b
AD		 2950 /* would disable interrupts here but EIAM disabled it */
2951 napi_schedule(&q_vector->napi);
9a799d71 2952
6af3b9eb
ET		 2953 /*
2954 * re-enable link(maybe) and non-queue interrupts, no flush.
2955 * ixgbe_poll will re-enable the queue interrupts
2956 */
6af3b9eb
ET		 2957 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2958 ixgbe_irq_enable(adapter, false, false);
2959
9a799d71
AK		 2960 return IRQ_HANDLED;
2961}
2962
2963/**
2964 * ixgbe_request_irq - initialize interrupts
2965 * @adapter: board private structure
2966 *
2967 * Attempts to configure interrupts using the best available
2968 * capabilities of the hardware and kernel.
2969 **/
021230d4 2970static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2971{
2972 struct net_device *netdev = adapter->netdev;
021230d4 2973 int err;
9a799d71 2974
4cc6df29 2975 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2976 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2977 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2978 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2979 netdev->name, adapter);
4cc6df29 2980 else
a0607fd3 2981 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2982 netdev->name, adapter);
9a799d71 2983
de88eeeb 2984 if (err)
396e799c 2985 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2986
9a799d71
AK		 2987 return err;
2988}
2989
2990static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2991{
49c7ffbe 2992 int vector;
9a799d71 2993
49c7ffbe
AD		 2994 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2995 free_irq(adapter->pdev->irq, adapter);
2996 return;
2997 }
4cc6df29 2998
49c7ffbe
AD		 2999 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3000 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3001 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3002
49c7ffbe
AD		 3003 /* free only the irqs that were actually requested */
3004 if (!q_vector->rx.ring && !q_vector->tx.ring)
3005 continue;
207867f5 3006
49c7ffbe
AD		 3007 /* clear the affinity_mask in the IRQ descriptor */
3008 irq_set_affinity_hint(entry->vector, NULL);
3009
3010 free_irq(entry->vector, q_vector);
9a799d71 3011 }
49c7ffbe
AD		 3012
3013 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3014}
3015
22d5a71b
JB		 3016/**
3017 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3018 * @adapter: board private structure
3019 **/
3020static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3021{
bd508178
AD		 3022 switch (adapter->hw.mac.type) {
3023 case ixgbe_mac_82598EB:
835462fc 3024 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3025 break;
3026 case ixgbe_mac_82599EB:
b93a2226 3027 case ixgbe_mac_X540:
9a75a1ac
DS		 3028 case ixgbe_mac_X550:
3029 case ixgbe_mac_X550EM_x:
835462fc
NS		 3030 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3031 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3032 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3033 break;
3034 default:
3035 break;
22d5a71b
JB		 3036 }
3037 IXGBE_WRITE_FLUSH(&adapter->hw);
3038 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3039 int vector;
3040
3041 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3042 synchronize_irq(adapter->msix_entries[vector].vector);
3043
3044 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3045 } else {
3046 synchronize_irq(adapter->pdev->irq);
3047 }
3048}
3049
9a799d71
AK		 3050/**
3051 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3052 *
3053 **/
3054static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3055{
d5bf4f67 3056 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3057
d5bf4f67 3058 ixgbe_write_eitr(q_vector);
9a799d71 3059
e8e26350
PW		 3060 ixgbe_set_ivar(adapter, 0, 0, 0);
3061 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3062
396e799c 3063 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3064}
3065
43e69bf0
AD		 3066/**
3067 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3068 * @adapter: board private structure
3069 * @ring: structure containing ring specific data
3070 *
3071 * Configure the Tx descriptor ring after a reset.
3072 **/
84418e3b
AD		 3073void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3074 struct ixgbe_ring *ring)
43e69bf0
AD		 3075{
3076 struct ixgbe_hw *hw = &adapter->hw;
3077 u64 tdba = ring->dma;
2f1860b8 3078 int wait_loop = 10;
b88c6de2 3079 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3080 u8 reg_idx = ring->reg_idx;
43e69bf0 3081
2f1860b8 3082 /* disable queue to avoid issues while updating state */
b88c6de2 3083 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3084 IXGBE_WRITE_FLUSH(hw);
3085
43e69bf0 3086 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3087 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3088 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3089 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3090 ring->count * sizeof(union ixgbe_adv_tx_desc));
3091 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3092 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3093 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3094
b88c6de2
AD		 3095 /*
3096 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3097 * higher than 1 when:
3098 * - ITR is 0 as it could cause false TX hangs
3099 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3100 *
3101 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3102 * to or less than the number of on chip descriptors, which is
3103 * currently 40.
3104 */
67da097e 3105 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3106 txdctl |= (1 << 16); /* WTHRESH = 1 */
3107 else
3108 txdctl |= (8 << 16); /* WTHRESH = 8 */
3109
e954b374
AD		 3110 /*
3111 * Setting PTHRESH to 32 both improves performance
3112 * and avoids a TX hang with DFP enabled
3113 */
b88c6de2
AD		 3114 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3115 32; /* PTHRESH = 32 */
2f1860b8
AD		 3116
3117 /* reinitialize flowdirector state */
39cb681b 3118 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3119 ring->atr_sample_rate = adapter->atr_sample_rate;
3120 ring->atr_count = 0;
3121 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3122 } else {
3123 ring->atr_sample_rate = 0;
3124 }
2f1860b8 3125
fd786b7b
AD		 3126 /* initialize XPS */
3127 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3128 struct ixgbe_q_vector *q_vector = ring->q_vector;
3129
3130 if (q_vector)
2a47fa45 3131 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3132 &q_vector->affinity_mask,
3133 ring->queue_index);
3134 }
3135
c84d324c
JF		 3136 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3137
2f1860b8 3138 /* enable queue */
2f1860b8
AD		 3139 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3140
3141 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3142 if (hw->mac.type == ixgbe_mac_82598EB &&
3143 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3144 return;
3145
3146 /* poll to verify queue is enabled */
3147 do {
032b4325 3148 usleep_range(1000, 2000);
2f1860b8
AD		 3149 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3150 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3151 if (!wait_loop)
3152 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3153}
3154
120ff942
AD		 3155static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3156{
3157 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3158 u32 rttdcs, mtqc;
8b1c0b24 3159 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3160
3161 if (hw->mac.type == ixgbe_mac_82598EB)
3162 return;
3163
3164 /* disable the arbiter while setting MTQC */
3165 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3166 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3167 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3168
3169 /* set transmit pool layout */
671c0adb
AD		 3170 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3171 mtqc = IXGBE_MTQC_VT_ENA;
3172 if (tcs > 4)
3173 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3174 else if (tcs > 1)
3175 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3176 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3177 mtqc |= IXGBE_MTQC_32VF;
3178 else
3179 mtqc |= IXGBE_MTQC_64VF;
3180 } else {
3181 if (tcs > 4)
3182 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3183 else if (tcs > 1)
3184 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3185 else
671c0adb
AD		 3186 mtqc = IXGBE_MTQC_64Q_1PB;
3187 }
120ff942 3188
671c0adb 3189 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3190
671c0adb
AD		 3191 /* Enable Security TX Buffer IFG for multiple pb */
3192 if (tcs) {
3193 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3194 sectx |= IXGBE_SECTX_DCB;
3195 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3196 }
3197
3198 /* re-enable the arbiter */
3199 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3200 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3201}
3202
9a799d71 3203/**
3a581073 3204 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3205 * @adapter: board private structure
3206 *
3207 * Configure the Tx unit of the MAC after a reset.
3208 **/
3209static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3210{
2f1860b8
AD		 3211 struct ixgbe_hw *hw = &adapter->hw;
3212 u32 dmatxctl;
43e69bf0 3213 u32 i;
9a799d71 3214
2f1860b8
AD		 3215 ixgbe_setup_mtqc(adapter);
3216
3217 if (hw->mac.type != ixgbe_mac_82598EB) {
3218 /* DMATXCTL.EN must be before Tx queues are enabled */
3219 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3220 dmatxctl |= IXGBE_DMATXCTL_TE;
3221 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3222 }
3223
9a799d71 3224 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3225 for (i = 0; i < adapter->num_tx_queues; i++)
3226 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3227}
3228
3ebe8fde
AD		 3229static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3230 struct ixgbe_ring *ring)
3231{
3232 struct ixgbe_hw *hw = &adapter->hw;
3233 u8 reg_idx = ring->reg_idx;
3234 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3235
3236 srrctl |= IXGBE_SRRCTL_DROP_EN;
3237
3238 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3239}
3240
3241static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3242 struct ixgbe_ring *ring)
3243{
3244 struct ixgbe_hw *hw = &adapter->hw;
3245 u8 reg_idx = ring->reg_idx;
3246 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3247
3248 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3249
3250 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3251}
3252
3253#ifdef CONFIG_IXGBE_DCB
3254void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3255#else
3256static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3257#endif
3258{
3259 int i;
3260 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3261
3262 if (adapter->ixgbe_ieee_pfc)
3263 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3264
3265 /*
3266 * We should set the drop enable bit if:
3267 * SR-IOV is enabled
3268 * or
3269 * Number of Rx queues > 1 and flow control is disabled
3270 *
3271 * This allows us to avoid head of line blocking for security
3272 * and performance reasons.
3273 */
3274 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3275 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3276 for (i = 0; i < adapter->num_rx_queues; i++)
3277 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3278 } else {
3279 for (i = 0; i < adapter->num_rx_queues; i++)
3280 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3281 }
3282}
3283
e8e26350 3284#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3285
a6616b42 3286static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3287 struct ixgbe_ring *rx_ring)
cc41ac7c 3288{
45e9baa5 3289 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3290 u32 srrctl;
bf29ee6c 3291 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3292
45e9baa5
AD		 3293 if (hw->mac.type == ixgbe_mac_82598EB) {
3294 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3295
45e9baa5
AD		 3296 /*
3297 * if VMDq is not active we must program one srrctl register
3298 * per RSS queue since we have enabled RDRXCTL.MVMEN
3299 */
3300 reg_idx &= mask;
3301 }
cc41ac7c 3302
45e9baa5
AD		 3303 /* configure header buffer length, needed for RSC */
3304 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3305
45e9baa5 3306 /* configure the packet buffer length */
f800326d 3307 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3308
3309 /* configure descriptor type */
f800326d 3310 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3311
45e9baa5 3312 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3313}
9a799d71 3314
dfaf891d 3315/**
a897a2ad 3316 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3317 * @adapter: device handle
3318 *
3319 * - 82598/82599/X540: 128
3320 * - X550(non-SRIOV mode): 512
3321 * - X550(SRIOV mode): 64
3322 */
7f276efb 3323u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3324{
3325 if (adapter->hw.mac.type < ixgbe_mac_X550)
3326 return 128;
3327 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3328 return 64;
3329 else
3330 return 512;
3331}
3332
3333/**
a897a2ad 3334 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3335 * @adapter: device handle
3336 *
3337 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3338 */
1c7cf078 3339void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3340{
dfaf891d 3341 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3342 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3343 u32 reta = 0;
dfaf891d
VZ		 3344 u32 indices_multi;
3345 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3346
0f9b232b 3347 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3348 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3349 * indices.
3350 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3351 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3352 */
3353 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3354 indices_multi = 0x11;
3355 else
3356 indices_multi = 0x1;
3357
dfaf891d
VZ		 3358 /* Write redirection table to HW */
3359 for (i = 0; i < reta_entries; i++) {
3360 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3361 if ((i & 3) == 3) {
3362 if (i < 128)
3363 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3364 else
3365 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3366 reta);
dfaf891d 3367 reta = 0;
0f9b232b
DS		 3368 }
3369 }
3370}
3371
dfaf891d 3372/**
a897a2ad 3373 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3374 * @adapter: device handle
3375 *
3376 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3377 */
3378static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3379{
dfaf891d 3380 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3381 struct ixgbe_hw *hw = &adapter->hw;
3382 u32 vfreta = 0;
dfaf891d
VZ		 3383 unsigned int pf_pool = adapter->num_vfs;
3384
3385 /* Write redirection table to HW */
3386 for (i = 0; i < reta_entries; i++) {
3387 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3388 if ((i & 3) == 3) {
3389 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3390 vfreta);
3391 vfreta = 0;
3392 }
3393 }
3394}
3395
3396static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3397{
3398 struct ixgbe_hw *hw = &adapter->hw;
3399 u32 i, j;
3400 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3401 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3402
3403 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3404 * make full use of any rings they may have. We will use the
3405 * PSRTYPE register to control how many rings we use within the PF.
3406 */
3407 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3408 rss_i = 2;
3409
3410 /* Fill out hash function seeds */
3411 for (i = 0; i < 10; i++)
3412 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3413
3414 /* Fill out redirection table */
3415 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3416
3417 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3418 if (j == rss_i)
3419 j = 0;
3420
3421 adapter->rss_indir_tbl[i] = j;
3422 }
3423
3424 ixgbe_store_reta(adapter);
3425}
3426
3427static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3428{
3429 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3430 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3431 unsigned int pf_pool = adapter->num_vfs;
3432 int i, j;
3433
3434 /* Fill out hash function seeds */
3435 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3436 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3437 adapter->rss_key[i]);
0f9b232b
DS		 3438
3439 /* Fill out the redirection table */
3440 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3441 if (j == rss_i)
05abb126 3442 j = 0;
dfaf891d
VZ		 3443
3444 adapter->rss_indir_tbl[i] = j;
05abb126 3445 }
dfaf891d
VZ		 3446
3447 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3448}
3449
3450static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3451{
3452 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3453 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3454 u32 rxcsum;
0cefafad 3455
05abb126
AD		 3456 /* Disable indicating checksum in descriptor, enables RSS hash */
3457 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3458 rxcsum |= IXGBE_RXCSUM_PCSD;
3459 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3460
671c0adb 3461 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3462 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3463 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3464 } else {
671c0adb
AD		 3465 u8 tcs = netdev_get_num_tc(adapter->netdev);
3466
3467 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3468 if (tcs > 4)
3469 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3470 else if (tcs > 1)
3471 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3472 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3473 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3474 else
671c0adb
AD		 3475 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3476 } else {
3477 if (tcs > 4)
8b1c0b24 3478 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3479 else if (tcs > 1)
3480 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3481 else
3482 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3483 }
0cefafad
JB		 3484 }
3485
05abb126 3486 /* Perform hash on these packet types */
d1b849b9
DS		 3487 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3488 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3489 IXGBE_MRQC_RSS_FIELD_IPV6 |
3490 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3491
ef6afc0c 3492 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3493 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3494 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3495 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3496
dfaf891d 3497 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3498 if ((hw->mac.type >= ixgbe_mac_X550) &&
3499 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3500 unsigned int pf_pool = adapter->num_vfs;
3501
3502 /* Enable VF RSS mode */
3503 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3504 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3505
3506 /* Setup RSS through the VF registers */
dfaf891d 3507 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3508 vfmrqc = IXGBE_MRQC_RSSEN;
3509 vfmrqc |= rss_field;
3510 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3511 } else {
dfaf891d 3512 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3513 mrqc |= rss_field;
3514 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3515 }
0cefafad
JB		 3516}
3517
bb5a9ad2
NS		 3518/**
3519 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3520 * @adapter: address of board private structure
3521 * @index: index of ring to set
bb5a9ad2 3522 **/
082757af 3523static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3524 struct ixgbe_ring *ring)
bb5a9ad2 3525{
bb5a9ad2 3526 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3527 u32 rscctrl;
bf29ee6c 3528 u8 reg_idx = ring->reg_idx;
7367096a 3529
7d637bcc 3530 if (!ring_is_rsc_enabled(ring))
7367096a 3531 return;
bb5a9ad2 3532
7367096a 3533 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3534 rscctrl |= IXGBE_RSCCTL_RSCEN;
3535 /*
3536 * we must limit the number of descriptors so that the
3537 * total size of max desc * buf_len is not greater
642c680e 3538 * than 65536
bb5a9ad2 3539 */
f800326d 3540 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3541 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3542}
3543
9e10e045
AD		 3544#define IXGBE_MAX_RX_DESC_POLL 10
3545static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3546 struct ixgbe_ring *ring)
3547{
3548 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3549 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3550 u32 rxdctl;
bf29ee6c 3551 u8 reg_idx = ring->reg_idx;
9e10e045 3552
b0483c8f
MR		 3553 if (ixgbe_removed(hw->hw_addr))
3554 return;
9e10e045
AD		 3555 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3556 if (hw->mac.type == ixgbe_mac_82598EB &&
3557 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3558 return;
3559
3560 do {
032b4325 3561 usleep_range(1000, 2000);
9e10e045
AD		 3562 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3563 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3564
3565 if (!wait_loop) {
3566 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3567 "the polling period\n", reg_idx);
3568 }
3569}
3570
2d39d576
YZ		 3571void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3572 struct ixgbe_ring *ring)
3573{
3574 struct ixgbe_hw *hw = &adapter->hw;
3575 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3576 u32 rxdctl;
3577 u8 reg_idx = ring->reg_idx;
3578
b0483c8f
MR		 3579 if (ixgbe_removed(hw->hw_addr))
3580 return;
2d39d576
YZ		 3581 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3582 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3583
3584 /* write value back with RXDCTL.ENABLE bit cleared */
3585 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3586
3587 if (hw->mac.type == ixgbe_mac_82598EB &&
3588 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3589 return;
3590
3591 /* the hardware may take up to 100us to really disable the rx queue */
3592 do {
3593 udelay(10);
3594 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3595 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3596
3597 if (!wait_loop) {
3598 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3599 "the polling period\n", reg_idx);
3600 }
3601}
3602
84418e3b
AD		 3603void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3604 struct ixgbe_ring *ring)
acd37177
AD		 3605{
3606 struct ixgbe_hw *hw = &adapter->hw;
3607 u64 rdba = ring->dma;
9e10e045 3608 u32 rxdctl;
bf29ee6c 3609 u8 reg_idx = ring->reg_idx;
acd37177 3610
9e10e045
AD		 3611 /* disable queue to avoid issues while updating state */
3612 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3613 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3614
acd37177
AD		 3615 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3616 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3617 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3618 ring->count * sizeof(union ixgbe_adv_rx_desc));
3619 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3620 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3621 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3622
3623 ixgbe_configure_srrctl(adapter, ring);
3624 ixgbe_configure_rscctl(adapter, ring);
3625
3626 if (hw->mac.type == ixgbe_mac_82598EB) {
3627 /*
3628 * enable cache line friendly hardware writes:
3629 * PTHRESH=32 descriptors (half the internal cache),
3630 * this also removes ugly rx_no_buffer_count increment
3631 * HTHRESH=4 descriptors (to minimize latency on fetch)
3632 * WTHRESH=8 burst writeback up to two cache lines
3633 */
3634 rxdctl &= ~0x3FFFFF;
3635 rxdctl |= 0x080420;
3636 }
3637
3638 /* enable receive descriptor ring */
3639 rxdctl |= IXGBE_RXDCTL_ENABLE;
3640 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3641
3642 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3643 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3644}
3645
48654521
AD		 3646static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3647{
3648 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3649 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3650 u16 pool;
48654521
AD		 3651
3652 /* PSRTYPE must be initialized in non 82598 adapters */
3653 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3654 IXGBE_PSRTYPE_UDPHDR |
3655 IXGBE_PSRTYPE_IPV4HDR |
48654521 3656 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3657 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3658
3659 if (hw->mac.type == ixgbe_mac_82598EB)
3660 return;
3661
fbe7ca7f
AD		 3662 if (rss_i > 3)
3663 psrtype |= 2 << 29;
3664 else if (rss_i > 1)
3665 psrtype |= 1 << 29;
48654521 3666
2a47fa45
JF		 3667 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3668 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3669}
3670
f5b4a52e
AD		 3671static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3672{
3673 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3674 u32 reg_offset, vf_shift;
435b19f6 3675 u32 gcr_ext, vmdctl;
de4c7f65 3676 int i;
f5b4a52e
AD		 3677
3678 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3679 return;
3680
3681 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3682 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3683 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3684 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3685 vmdctl |= IXGBE_VT_CTL_REPLEN;
3686 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3687
1d9c0bfd
AD		 3688 vf_shift = VMDQ_P(0) % 32;
3689 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3690
3691 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3692 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3693 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3694 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3695 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3696 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3697 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3698
3699 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3700 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3701
3702 /*
3703 * Set up VF register offsets for selected VT Mode,
3704 * i.e. 32 or 64 VFs for SR-IOV
3705 */
73079ea0
AD		 3706 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3707 case IXGBE_82599_VMDQ_8Q_MASK:
3708 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3709 break;
3710 case IXGBE_82599_VMDQ_4Q_MASK:
3711 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3712 break;
3713 default:
3714 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3715 break;
3716 }
3717
f5b4a52e
AD		 3718 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3719
435b19f6 3720
a985b6c3 3721 /* Enable MAC Anti-Spoofing */
435b19f6 3722 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3723 adapter->num_vfs);
5b7f000f 3724
f079fa00 3725 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
5b7f000f
DS		 3726 * calling set_ethertype_anti_spoofing for each VF in loop below
3727 */
f079fa00 3728 if (hw->mac.ops.set_ethertype_anti_spoofing) {
5b7f000f 3729 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
f079fa00
ET		 3730 (IXGBE_ETQF_FILTER_EN |
3731 IXGBE_ETQF_TX_ANTISPOOF |
3732 IXGBE_ETH_P_LLDP));
3733
3734 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3735 (IXGBE_ETQF_FILTER_EN |
3736 IXGBE_ETQF_TX_ANTISPOOF |
3737 ETH_P_PAUSE));
3738 }
5b7f000f 3739
de4c7f65
GR		 3740 /* For VFs that have spoof checking turned off */
3741 for (i = 0; i < adapter->num_vfs; i++) {
3742 if (!adapter->vfinfo[i].spoofchk_enabled)
3743 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3744
3745 /* enable ethertype anti spoofing if hw supports it */
3746 if (hw->mac.ops.set_ethertype_anti_spoofing)
3747 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3748
3749 /* Enable/Disable RSS query feature */
3750 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3751 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3752 }
f5b4a52e
AD		 3753}
3754
477de6ed 3755static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3756{
9a799d71
AK		 3757 struct ixgbe_hw *hw = &adapter->hw;
3758 struct net_device *netdev = adapter->netdev;
3759 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3760 struct ixgbe_ring *rx_ring;
3761 int i;
3762 u32 mhadd, hlreg0;
48654521 3763
63f39bd1 3764#ifdef IXGBE_FCOE
477de6ed
AD		 3765 /* adjust max frame to be able to do baby jumbo for FCoE */
3766 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3767 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3768 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3769
477de6ed 3770#endif /* IXGBE_FCOE */
872844dd
AD		 3771
3772 /* adjust max frame to be at least the size of a standard frame */
3773 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3774 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3775
477de6ed
AD		 3776 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3777 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3778 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3779 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3780
3781 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3782 }
3783
3784 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3785 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3786 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3787 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3788
0cefafad
JB		 3789 /*
3790 * Setup the HW Rx Head and Tail Descriptor Pointers and
3791 * the Base and Length of the Rx Descriptor Ring
3792 */
9a799d71 3793 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3794 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3795 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3796 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3797 else
7d637bcc 3798 clear_ring_rsc_enabled(rx_ring);
477de6ed 3799 }
477de6ed
AD		 3800}
3801
7367096a
AD		 3802static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3803{
3804 struct ixgbe_hw *hw = &adapter->hw;
3805 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3806
3807 switch (hw->mac.type) {
3808 case ixgbe_mac_82598EB:
3809 /*
3810 * For VMDq support of different descriptor types or
3811 * buffer sizes through the use of multiple SRRCTL
3812 * registers, RDRXCTL.MVMEN must be set to 1
3813 *
3814 * also, the manual doesn't mention it clearly but DCA hints
3815 * will only use queue 0's tags unless this bit is set. Side
3816 * effects of setting this bit are only that SRRCTL must be
3817 * fully programmed [0..15]
3818 */
3819 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3820 break;
052a1a72
MR		 3821 case ixgbe_mac_X550:
3822 case ixgbe_mac_X550EM_x:
f961ddae
MR		 3823 if (adapter->num_vfs)
3824 rdrxctl |= IXGBE_RDRXCTL_PSP;
3825 /* fall through for older HW */
7367096a 3826 case ixgbe_mac_82599EB:
b93a2226 3827 case ixgbe_mac_X540:
7367096a
AD		 3828 /* Disable RSC for ACK packets */
3829 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3830 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3831 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3832 /* hardware requires some bits to be set by default */
3833 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3834 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3835 break;
3836 default:
3837 /* We should do nothing since we don't know this hardware */
3838 return;
3839 }
3840
3841 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3842}
3843
477de6ed
AD		 3844/**
3845 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3846 * @adapter: board private structure
3847 *
3848 * Configure the Rx unit of the MAC after a reset.
3849 **/
3850static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3851{
3852 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3853 int i;
6dcc28b9 3854 u32 rxctrl, rfctl;
477de6ed
AD		 3855
3856 /* disable receives while setting up the descriptors */
1f9ac57c 3857 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3858
3859 ixgbe_setup_psrtype(adapter);
7367096a 3860 ixgbe_setup_rdrxctl(adapter);
477de6ed 3861
6dcc28b9
JK		 3862 /* RSC Setup */
3863 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3864 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3865 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3866 rfctl |= IXGBE_RFCTL_RSC_DIS;
3867 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3868
9e10e045 3869 /* Program registers for the distribution of queues */
f5b4a52e 3870 ixgbe_setup_mrqc(adapter);
f5b4a52e 3871
477de6ed
AD		 3872 /* set_rx_buffer_len must be called before ring initialization */
3873 ixgbe_set_rx_buffer_len(adapter);
3874
3875 /*
3876 * Setup the HW Rx Head and Tail Descriptor Pointers and
3877 * the Base and Length of the Rx Descriptor Ring
3878 */
9e10e045
AD		 3879 for (i = 0; i < adapter->num_rx_queues; i++)
3880 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3881
1f9ac57c 3882 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3883 /* disable drop enable for 82598 parts */
3884 if (hw->mac.type == ixgbe_mac_82598EB)
3885 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3886
3887 /* enable all receives */
3888 rxctrl |= IXGBE_RXCTRL_RXEN;
3889 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3890}
3891
80d5c368
PM		 3892static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3893 __be16 proto, u16 vid)
068c89b0
DS		 3894{
3895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3896 struct ixgbe_hw *hw = &adapter->hw;
3897
3898 /* add VID to filter table */
1d9c0bfd 3899 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3900 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3901
3902 return 0;
068c89b0
DS		 3903}
3904
80d5c368
PM		 3905static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3906 __be16 proto, u16 vid)
068c89b0
DS		 3907{
3908 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3909 struct ixgbe_hw *hw = &adapter->hw;
3910
068c89b0 3911 /* remove VID from filter table */
1d9c0bfd 3912 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3913 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3914
3915 return 0;
068c89b0
DS		 3916}
3917
f62bbb5e
JG		 3918/**
3919 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3920 * @adapter: driver data
3921 */
3922static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3923{
3924 struct ixgbe_hw *hw = &adapter->hw;
3925 u32 vlnctrl;
5f6c0181
JB		 3926 int i, j;
3927
3928 switch (hw->mac.type) {
3929 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3930 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3931 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3932 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3933 break;
3934 case ixgbe_mac_82599EB:
b93a2226 3935 case ixgbe_mac_X540:
9a75a1ac
DS		 3936 case ixgbe_mac_X550:
3937 case ixgbe_mac_X550EM_x:
5f6c0181 3938 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3939 struct ixgbe_ring *ring = adapter->rx_ring[i];
3940
3941 if (ring->l2_accel_priv)
3942 continue;
3943 j = ring->reg_idx;
5f6c0181
JB		 3944 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3945 vlnctrl &= ~IXGBE_RXDCTL_VME;
3946 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3947 }
3948 break;
3949 default:
3950 break;
3951 }
3952}
3953
3954/**
f62bbb5e 3955 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3956 * @adapter: driver data
3957 */
f62bbb5e 3958static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3959{
3960 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3961 u32 vlnctrl;
5f6c0181
JB		 3962 int i, j;
3963
3964 switch (hw->mac.type) {
3965 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3966 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3967 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3968 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3969 break;
3970 case ixgbe_mac_82599EB:
b93a2226 3971 case ixgbe_mac_X540:
9a75a1ac
DS		 3972 case ixgbe_mac_X550:
3973 case ixgbe_mac_X550EM_x:
5f6c0181 3974 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3975 struct ixgbe_ring *ring = adapter->rx_ring[i];
3976
3977 if (ring->l2_accel_priv)
3978 continue;
3979 j = ring->reg_idx;
5f6c0181
JB		 3980 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3981 vlnctrl |= IXGBE_RXDCTL_VME;
3982 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3983 }
3984 break;
3985 default:
3986 break;
3987 }
3988}
3989
9a799d71
AK		 3990static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3991{
f62bbb5e 3992 u16 vid;
9a799d71 3993
80d5c368 3994 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3995
3996 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3997 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3998}
3999
b335e75b
JK		 4000/**
4001 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4002 * @netdev: network interface device structure
4003 *
4004 * Writes multicast address list to the MTA hash table.
4005 * Returns: -ENOMEM on failure
4006 * 0 on no addresses written
4007 * X on writing X addresses to MTA
4008 **/
4009static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4010{
4011 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4012 struct ixgbe_hw *hw = &adapter->hw;
4013
4014 if (!netif_running(netdev))
4015 return 0;
4016
4017 if (hw->mac.ops.update_mc_addr_list)
4018 hw->mac.ops.update_mc_addr_list(hw, netdev);
4019 else
4020 return -ENOMEM;
4021
4022#ifdef CONFIG_PCI_IOV
5d7daa35 4023 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4024#endif
4025
4026 return netdev_mc_count(netdev);
4027}
4028
5d7daa35
JK		 4029#ifdef CONFIG_PCI_IOV
4030void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4031{
4032 struct ixgbe_hw *hw = &adapter->hw;
4033 int i;
4034 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4035 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4036 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4037 adapter->mac_table[i].queue,
4038 IXGBE_RAH_AV);
4039 else
4040 hw->mac.ops.clear_rar(hw, i);
4041
4042 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4043 }
4044}
4045#endif
4046
4047static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4048{
4049 struct ixgbe_hw *hw = &adapter->hw;
4050 int i;
4051 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4052 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4053 if (adapter->mac_table[i].state &
4054 IXGBE_MAC_STATE_IN_USE)
4055 hw->mac.ops.set_rar(hw, i,
4056 adapter->mac_table[i].addr,
4057 adapter->mac_table[i].queue,
4058 IXGBE_RAH_AV);
4059 else
4060 hw->mac.ops.clear_rar(hw, i);
4061
4062 adapter->mac_table[i].state &=
4063 ~(IXGBE_MAC_STATE_MODIFIED);
4064 }
4065 }
4066}
4067
4068static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4069{
4070 int i;
4071 struct ixgbe_hw *hw = &adapter->hw;
4072
4073 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4074 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4075 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4076 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4077 adapter->mac_table[i].queue = 0;
4078 }
4079 ixgbe_sync_mac_table(adapter);
4080}
4081
4082static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4083{
4084 struct ixgbe_hw *hw = &adapter->hw;
4085 int i, count = 0;
4086
4087 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4088 if (adapter->mac_table[i].state == 0)
4089 count++;
4090 }
4091 return count;
4092}
4093
4094/* this function destroys the first RAR entry */
4095static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4096 u8 *addr)
4097{
4098 struct ixgbe_hw *hw = &adapter->hw;
4099
4100 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4101 adapter->mac_table[0].queue = VMDQ_P(0);
4102 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4103 IXGBE_MAC_STATE_IN_USE);
4104 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4105 adapter->mac_table[0].queue,
4106 IXGBE_RAH_AV);
4107}
4108
4109int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4110{
4111 struct ixgbe_hw *hw = &adapter->hw;
4112 int i;
4113
4114 if (is_zero_ether_addr(addr))
4115 return -EINVAL;
4116
4117 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4118 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4119 continue;
4120 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4121 IXGBE_MAC_STATE_IN_USE);
4122 ether_addr_copy(adapter->mac_table[i].addr, addr);
4123 adapter->mac_table[i].queue = queue;
4124 ixgbe_sync_mac_table(adapter);
4125 return i;
4126 }
4127 return -ENOMEM;
4128}
4129
4130int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4131{
4132 /* search table for addr, if found, set to 0 and sync */
4133 int i;
4134 struct ixgbe_hw *hw = &adapter->hw;
4135
4136 if (is_zero_ether_addr(addr))
4137 return -EINVAL;
4138
4139 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4140 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4141 adapter->mac_table[i].queue == queue) {
4142 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4143 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4144 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4145 adapter->mac_table[i].queue = 0;
4146 ixgbe_sync_mac_table(adapter);
4147 return 0;
4148 }
4149 }
4150 return -ENOMEM;
4151}
2850062a
AD		 4152/**
4153 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4154 * @netdev: network interface device structure
4155 *
4156 * Writes unicast address list to the RAR table.
4157 * Returns: -ENOMEM on failure/insufficient address space
4158 * 0 on no addresses written
4159 * X on writing X addresses to the RAR table
4160 **/
5d7daa35 4161static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4162{
4163 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4164 int count = 0;
4165
4166 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4167 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4168 return -ENOMEM;
4169
95447461 4170 if (!netdev_uc_empty(netdev)) {
2850062a 4171 struct netdev_hw_addr *ha;
2850062a 4172 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4173 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4174 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4175 count++;
4176 }
4177 }
2850062a
AD		 4178 return count;
4179}
4180
9a799d71 4181/**
2c5645cf 4182 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4183 * @netdev: network interface device structure
4184 *
2c5645cf
CL		 4185 * The set_rx_method entry point is called whenever the unicast/multicast
4186 * address list or the network interface flags are updated. This routine is
4187 * responsible for configuring the hardware for proper unicast, multicast and
4188 * promiscuous mode.
9a799d71 4189 **/
7f870475 4190void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4191{
4192 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4193 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4194 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4195 u32 vlnctrl;
2850062a 4196 int count;
9a799d71
AK		 4197
4198 /* Check for Promiscuous and All Multicast modes */
9a799d71 4199 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4200 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4201
f5dc442b 4202 /* set all bits that we expect to always be set */
3f2d1c0f 4203 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4204 fctrl |= IXGBE_FCTRL_BAM;
4205 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4206 fctrl |= IXGBE_FCTRL_PMCF;
4207
2850062a
AD		 4208 /* clear the bits we are changing the status of */
4209 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4210 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4211 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4212 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4213 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4214 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4215 /* Only disable hardware filter vlans in promiscuous mode
4216 * if SR-IOV and VMDQ are disabled - otherwise ensure
4217 * that hardware VLAN filters remain enabled.
4218 */
4556dc59
VY		 4219 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4220 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4221 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4222 } else {
746b9f02
PM		 4223 if (netdev->flags & IFF_ALLMULTI) {
4224 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4225 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4226 }
a9b8943e 4227 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4228 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4229 }
4230
4231 /*
4232 * Write addresses to available RAR registers, if there is not
4233 * sufficient space to store all the addresses then enable
4234 * unicast promiscuous mode
4235 */
5d7daa35 4236 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4237 if (count < 0) {
4238 fctrl |= IXGBE_FCTRL_UPE;
4239 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4240 }
4241
cf78959c
ET		 4242 /* Write addresses to the MTA, if the attempt fails
4243 * then we should just turn on promiscuous mode so
4244 * that we can at least receive multicast traffic
4245 */
b335e75b
JK		 4246 count = ixgbe_write_mc_addr_list(netdev);
4247 if (count < 0) {
4248 fctrl |= IXGBE_FCTRL_MPE;
4249 vmolr |= IXGBE_VMOLR_MPE;
4250 } else if (count) {
4251 vmolr |= IXGBE_VMOLR_ROMPE;
4252 }
1d9c0bfd
AD		 4253
4254 if (hw->mac.type != ixgbe_mac_82598EB) {
4255 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4256 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4257 IXGBE_VMOLR_ROPE);
1d9c0bfd 4258 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4259 }
4260
3f2d1c0f
BG		 4261 /* This is useful for sniffing bad packets. */
4262 if (adapter->netdev->features & NETIF_F_RXALL) {
4263 /* UPE and MPE will be handled by normal PROMISC logic
4264 * in e1000e_set_rx_mode */
4265 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4266 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4267 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4268
4269 fctrl &= ~(IXGBE_FCTRL_DPF);
4270 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4271 }
4272
a9b8943e 4273 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4274 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4275
f646968f 4276 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4277 ixgbe_vlan_strip_enable(adapter);
4278 else
4279 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4280}
4281
021230d4
AV		 4282static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4283{
4284 int q_idx;
021230d4 4285
5a85e737
ET		 4286 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4287 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4288 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4289 }
021230d4
AV		 4290}
4291
4292static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4293{
4294 int q_idx;
021230d4 4295
5a85e737 4296 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4297 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4298 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4299 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4300 usleep_range(1000, 20000);
5a85e737
ET		 4301 }
4302 }
021230d4
AV		 4303}
4304
67359c3c
MR		 4305static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4306{
4307 switch (adapter->hw.mac.type) {
4308 case ixgbe_mac_X550:
4309 case ixgbe_mac_X550EM_x:
4310 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4311#ifdef CONFIG_IXGBE_VXLAN
4312 adapter->vxlan_port = 0;
4313#endif
4314 break;
4315 default:
4316 break;
4317 }
4318}
4319
7a6b6f51 4320#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4321/**
2f90b865
AD		 4322 * ixgbe_configure_dcb - Configure DCB hardware
4323 * @adapter: ixgbe adapter struct
4324 *
4325 * This is called by the driver on open to configure the DCB hardware.
4326 * This is also called by the gennetlink interface when reconfiguring
4327 * the DCB state.
4328 */
4329static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4330{
4331 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4332 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4333
67ebd791
AD		 4334 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4335 if (hw->mac.type == ixgbe_mac_82598EB)
4336 netif_set_gso_max_size(adapter->netdev, 65536);
4337 return;
4338 }
4339
4340 if (hw->mac.type == ixgbe_mac_82598EB)
4341 netif_set_gso_max_size(adapter->netdev, 32768);
4342
971060b1 4343#ifdef IXGBE_FCOE
b120818e
JF		 4344 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4345 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4346#endif
b120818e
JF		 4347
4348 /* reconfigure the hardware */
4349 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4350 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4351 DCB_TX_CONFIG);
4352 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4353 DCB_RX_CONFIG);
4354 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4355 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4356 ixgbe_dcb_hw_ets(&adapter->hw,
4357 adapter->ixgbe_ieee_ets,
4358 max_frame);
4359 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4360 adapter->ixgbe_ieee_pfc->pfc_en,
4361 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4362 }
8187cd48
JF		 4363
4364 /* Enable RSS Hash per TC */
4365 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4366 u32 msb = 0;
4367 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4368
d411a936
AD		 4369 while (rss_i) {
4370 msb++;
4371 rss_i >>= 1;
4372 }
8187cd48 4373
4ae63730
AD		 4374 /* write msb to all 8 TCs in one write */
4375 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4376 }
2f90b865 4377}
9da712d2
JF		 4378#endif
4379
4380/* Additional bittime to account for IXGBE framing */
4381#define IXGBE_ETH_FRAMING 20
4382
49ce9c2c 4383/**
9da712d2
JF		 4384 * ixgbe_hpbthresh - calculate high water mark for flow control
4385 *
4386 * @adapter: board private structure to calculate for
49ce9c2c 4387 * @pb: packet buffer to calculate
9da712d2
JF		 4388 */
4389static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4390{
4391 struct ixgbe_hw *hw = &adapter->hw;
4392 struct net_device *dev = adapter->netdev;
4393 int link, tc, kb, marker;
4394 u32 dv_id, rx_pba;
4395
4396 /* Calculate max LAN frame size */
4397 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4398
4399#ifdef IXGBE_FCOE
4400 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4401 if ((dev->features & NETIF_F_FCOE_MTU) &&
4402 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4403 (pb == ixgbe_fcoe_get_tc(adapter)))
4404 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4405#endif
e5776620 4406
9da712d2
JF		 4407 /* Calculate delay value for device */
4408 switch (hw->mac.type) {
4409 case ixgbe_mac_X540:
9a75a1ac
DS		 4410 case ixgbe_mac_X550:
4411 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4412 dv_id = IXGBE_DV_X540(link, tc);
4413 break;
4414 default:
4415 dv_id = IXGBE_DV(link, tc);
4416 break;
4417 }
4418
4419 /* Loopback switch introduces additional latency */
4420 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4421 dv_id += IXGBE_B2BT(tc);
4422
4423 /* Delay value is calculated in bit times convert to KB */
4424 kb = IXGBE_BT2KB(dv_id);
4425 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4426
4427 marker = rx_pba - kb;
4428
4429 /* It is possible that the packet buffer is not large enough
4430 * to provide required headroom. In this case throw an error
4431 * to user and a do the best we can.
4432 */
4433 if (marker < 0) {
4434 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4435 "headroom to support flow control."
4436 "Decrease MTU or number of traffic classes\n", pb);
4437 marker = tc + 1;
4438 }
4439
4440 return marker;
4441}
4442
49ce9c2c 4443/**
9da712d2
JF		 4444 * ixgbe_lpbthresh - calculate low water mark for for flow control
4445 *
4446 * @adapter: board private structure to calculate for
49ce9c2c 4447 * @pb: packet buffer to calculate
9da712d2 4448 */
e5776620 4449static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4450{
4451 struct ixgbe_hw *hw = &adapter->hw;
4452 struct net_device *dev = adapter->netdev;
4453 int tc;
4454 u32 dv_id;
4455
4456 /* Calculate max LAN frame size */
4457 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4458
e5776620
JK		 4459#ifdef IXGBE_FCOE
4460 /* FCoE traffic class uses FCOE jumbo frames */
4461 if ((dev->features & NETIF_F_FCOE_MTU) &&
4462 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4463 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4464 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4465#endif
4466
9da712d2
JF		 4467 /* Calculate delay value for device */
4468 switch (hw->mac.type) {
4469 case ixgbe_mac_X540:
9a75a1ac
DS		 4470 case ixgbe_mac_X550:
4471 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4472 dv_id = IXGBE_LOW_DV_X540(tc);
4473 break;
4474 default:
4475 dv_id = IXGBE_LOW_DV(tc);
4476 break;
4477 }
4478
4479 /* Delay value is calculated in bit times convert to KB */
4480 return IXGBE_BT2KB(dv_id);
4481}
4482
4483/*
4484 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4485 */
4486static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4487{
4488 struct ixgbe_hw *hw = &adapter->hw;
4489 int num_tc = netdev_get_num_tc(adapter->netdev);
4490 int i;
4491
4492 if (!num_tc)
4493 num_tc = 1;
4494
9da712d2
JF		 4495 for (i = 0; i < num_tc; i++) {
4496 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4497 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4498
4499 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4500 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4501 hw->fc.low_water[i] = 0;
9da712d2 4502 }
e5776620
JK		 4503
4504 for (; i < MAX_TRAFFIC_CLASS; i++)
4505 hw->fc.high_water[i] = 0;
9da712d2
JF		 4506}
4507
80605c65
JF		 4508static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4509{
80605c65 4510 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4511 int hdrm;
4512 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4513
4514 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4515 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4516 hdrm = 32 << adapter->fdir_pballoc;
4517 else
4518 hdrm = 0;
80605c65 4519
f7e1027f 4520 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4521 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4522}
4523
e4911d57
AD		 4524static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4525{
4526 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4527 struct hlist_node *node2;
e4911d57
AD		 4528 struct ixgbe_fdir_filter *filter;
4529
4530 spin_lock(&adapter->fdir_perfect_lock);
4531
4532 if (!hlist_empty(&adapter->fdir_filter_list))
4533 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4534
b67bfe0d 4535 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4536 &adapter->fdir_filter_list, fdir_node) {
4537 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4538 &filter->filter,
4539 filter->sw_idx,
4540 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4541 IXGBE_FDIR_DROP_QUEUE :
4542 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4543 }
4544
4545 spin_unlock(&adapter->fdir_perfect_lock);
4546}
4547
2a47fa45
JF		 4548static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4549 struct ixgbe_adapter *adapter)
4550{
4551 struct ixgbe_hw *hw = &adapter->hw;
4552 u32 vmolr;
4553
4554 /* No unicast promiscuous support for VMDQ devices. */
4555 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4556 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4557
4558 /* clear the affected bit */
4559 vmolr &= ~IXGBE_VMOLR_MPE;
4560
4561 if (dev->flags & IFF_ALLMULTI) {
4562 vmolr |= IXGBE_VMOLR_MPE;
4563 } else {
4564 vmolr |= IXGBE_VMOLR_ROMPE;
4565 hw->mac.ops.update_mc_addr_list(hw, dev);
4566 }
5d7daa35 4567 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4568 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4569}
4570
2a47fa45
JF		 4571static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4572{
4573 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4574 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4575 struct ixgbe_hw *hw = &adapter->hw;
4576 u16 pool = vadapter->pool;
4577 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4578 IXGBE_PSRTYPE_UDPHDR |
4579 IXGBE_PSRTYPE_IPV4HDR |
4580 IXGBE_PSRTYPE_L2HDR |
4581 IXGBE_PSRTYPE_IPV6HDR;
4582
4583 if (hw->mac.type == ixgbe_mac_82598EB)
4584 return;
4585
4586 if (rss_i > 3)
4587 psrtype |= 2 << 29;
4588 else if (rss_i > 1)
4589 psrtype |= 1 << 29;
4590
4591 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4592}
4593
4594/**
4595 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4596 * @rx_ring: ring to free buffers from
4597 **/
4598static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4599{
4600 struct device *dev = rx_ring->dev;
4601 unsigned long size;
4602 u16 i;
4603
4604 /* ring already cleared, nothing to do */
4605 if (!rx_ring->rx_buffer_info)
4606 return;
4607
4608 /* Free all the Rx ring sk_buffs */
4609 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4610 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4611
2a47fa45
JF		 4612 if (rx_buffer->skb) {
4613 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4614 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4615 dma_unmap_page(dev,
4616 IXGBE_CB(skb)->dma,
4617 ixgbe_rx_bufsz(rx_ring),
4618 DMA_FROM_DEVICE);
2a47fa45 4619 dev_kfree_skb(skb);
4d2fcfbc 4620 rx_buffer->skb = NULL;
2a47fa45 4621 }
18cb652a
AD		 4622
4623 if (!rx_buffer->page)
4624 continue;
4625
4626 dma_unmap_page(dev, rx_buffer->dma,
4627 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4628 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4629
2a47fa45
JF		 4630 rx_buffer->page = NULL;
4631 }
4632
4633 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4634 memset(rx_ring->rx_buffer_info, 0, size);
4635
4636 /* Zero out the descriptor ring */
4637 memset(rx_ring->desc, 0, rx_ring->size);
4638
4639 rx_ring->next_to_alloc = 0;
4640 rx_ring->next_to_clean = 0;
4641 rx_ring->next_to_use = 0;
4642}
4643
4644static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4645 struct ixgbe_ring *rx_ring)
4646{
4647 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4648 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4649
4650 /* shutdown specific queue receive and wait for dma to settle */
4651 ixgbe_disable_rx_queue(adapter, rx_ring);
4652 usleep_range(10000, 20000);
4653 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4654 ixgbe_clean_rx_ring(rx_ring);
4655 rx_ring->l2_accel_priv = NULL;
4656}
4657
ae72c8d0
JF		 4658static int ixgbe_fwd_ring_down(struct net_device *vdev,
4659 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4660{
4661 struct ixgbe_adapter *adapter = accel->real_adapter;
4662 unsigned int rxbase = accel->rx_base_queue;
4663 unsigned int txbase = accel->tx_base_queue;
4664 int i;
4665
4666 netif_tx_stop_all_queues(vdev);
4667
4668 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4669 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4670 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4671 }
4672
4673 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4674 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4675 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4676 }
4677
4678
4679 return 0;
4680}
4681
4682static int ixgbe_fwd_ring_up(struct net_device *vdev,
4683 struct ixgbe_fwd_adapter *accel)
4684{
4685 struct ixgbe_adapter *adapter = accel->real_adapter;
4686 unsigned int rxbase, txbase, queues;
4687 int i, baseq, err = 0;
4688
4689 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4690 return 0;
4691
4692 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4693 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4694 accel->pool, adapter->num_rx_pools,
4695 baseq, baseq + adapter->num_rx_queues_per_pool,
4696 adapter->fwd_bitmask);
4697
4698 accel->netdev = vdev;
4699 accel->rx_base_queue = rxbase = baseq;
4700 accel->tx_base_queue = txbase = baseq;
4701
4702 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4703 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4704
4705 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4706 adapter->rx_ring[rxbase + i]->netdev = vdev;
4707 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4708 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4709 }
4710
4711 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4712 adapter->tx_ring[txbase + i]->netdev = vdev;
4713 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4714 }
4715
4716 queues = min_t(unsigned int,
4717 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4718 err = netif_set_real_num_tx_queues(vdev, queues);
4719 if (err)
4720 goto fwd_queue_err;
4721
2a47fa45
JF		 4722 err = netif_set_real_num_rx_queues(vdev, queues);
4723 if (err)
4724 goto fwd_queue_err;
4725
4726 if (is_valid_ether_addr(vdev->dev_addr))
4727 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4728
4729 ixgbe_fwd_psrtype(accel);
4730 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4731 return err;
4732fwd_queue_err:
4733 ixgbe_fwd_ring_down(vdev, accel);
4734 return err;
4735}
4736
4737static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4738{
4739 struct net_device *upper;
4740 struct list_head *iter;
4741 int err;
4742
4743 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4744 if (netif_is_macvlan(upper)) {
4745 struct macvlan_dev *dfwd = netdev_priv(upper);
4746 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4747
4748 if (dfwd->fwd_priv) {
4749 err = ixgbe_fwd_ring_up(upper, vadapter);
4750 if (err)
4751 continue;
4752 }
4753 }
4754 }
4755}
4756
9a799d71
AK		 4757static void ixgbe_configure(struct ixgbe_adapter *adapter)
4758{
d2f5e7f3
AS		 4759 struct ixgbe_hw *hw = &adapter->hw;
4760
80605c65 4761 ixgbe_configure_pb(adapter);
7a6b6f51 4762#ifdef CONFIG_IXGBE_DCB
67ebd791 4763 ixgbe_configure_dcb(adapter);
2f90b865 4764#endif
b35d4d42
AD		 4765 /*
4766 * We must restore virtualization before VLANs or else
4767 * the VLVF registers will not be populated
4768 */
4769 ixgbe_configure_virtualization(adapter);
9a799d71 4770
4c1d7b4b 4771 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4772 ixgbe_restore_vlan(adapter);
4773
d2f5e7f3
AS		 4774 switch (hw->mac.type) {
4775 case ixgbe_mac_82599EB:
4776 case ixgbe_mac_X540:
4777 hw->mac.ops.disable_rx_buff(hw);
4778 break;
4779 default:
4780 break;
4781 }
4782
c4cf55e5 4783 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4784 ixgbe_init_fdir_signature_82599(&adapter->hw,
4785 adapter->fdir_pballoc);
e4911d57
AD		 4786 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4787 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4788 adapter->fdir_pballoc);
4789 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4790 }
4c1d7b4b 4791
d2f5e7f3
AS		 4792 switch (hw->mac.type) {
4793 case ixgbe_mac_82599EB:
4794 case ixgbe_mac_X540:
4795 hw->mac.ops.enable_rx_buff(hw);
4796 break;
4797 default:
4798 break;
4799 }
4800
9de7605e
MR		 4801#ifdef CONFIG_IXGBE_DCA
4802 /* configure DCA */
4803 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
4804 ixgbe_setup_dca(adapter);
4805#endif /* CONFIG_IXGBE_DCA */
4806
7c8ae65a
AD		 4807#ifdef IXGBE_FCOE
4808 /* configure FCoE L2 filters, redirection table, and Rx control */
4809 ixgbe_configure_fcoe(adapter);
4810
4811#endif /* IXGBE_FCOE */
9a799d71
AK		 4812 ixgbe_configure_tx(adapter);
4813 ixgbe_configure_rx(adapter);
2a47fa45 4814 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4815}
4816
0ecc061d 4817/**
e8e26350
PW		 4818 * ixgbe_sfp_link_config - set up SFP+ link
4819 * @adapter: pointer to private adapter struct
4820 **/
4821static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4822{
7086400d 4823 /*
52f33af8 4824 * We are assuming the worst case scenario here, and that
7086400d
AD		 4825 * is that an SFP was inserted/removed after the reset
4826 * but before SFP detection was enabled. As such the best
4827 * solution is to just start searching as soon as we start
4828 */
4829 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4830 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4831
7086400d 4832 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 4833 adapter->sfp_poll_time = 0;
e8e26350
PW		 4834}
4835
4836/**
4837 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4838 * @hw: pointer to private hardware struct
4839 *
4840 * Returns 0 on success, negative on failure
4841 **/
e8e26350 4842static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4843{
3d292265
JH		 4844 u32 speed;
4845 bool autoneg, link_up = false;
a1e869de 4846 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 4847
4848 if (hw->mac.ops.check_link)
3d292265 4849 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4850
4851 if (ret)
e90dd264 4852 return ret;
0ecc061d 4853
3d292265
JH		 4854 speed = hw->phy.autoneg_advertised;
4855 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4856 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4857 &autoneg);
0ecc061d 4858 if (ret)
e90dd264 4859 return ret;
0ecc061d 4860
8620a103 4861 if (hw->mac.ops.setup_link)
fd0326f2 4862 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4863
0ecc061d
PWJ		 4864 return ret;
4865}
4866
a34bcfff 4867static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4868{
9a799d71 4869 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4870 u32 gpie = 0;
9a799d71 4871
9b471446 4872 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4873 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4874 IXGBE_GPIE_OCD;
4875 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4876 /*
4877 * use EIAM to auto-mask when MSI-X interrupt is asserted
4878 * this saves a register write for every interrupt
4879 */
4880 switch (hw->mac.type) {
4881 case ixgbe_mac_82598EB:
4882 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4883 break;
9b471446 4884 case ixgbe_mac_82599EB:
b93a2226 4885 case ixgbe_mac_X540:
9a75a1ac
DS		 4886 case ixgbe_mac_X550:
4887 case ixgbe_mac_X550EM_x:
b93a2226 4888 default:
9b471446
JB		 4889 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4890 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4891 break;
4892 }
4893 } else {
021230d4
AV		 4894 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4895 * specifically only auto mask tx and rx interrupts */
4896 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4897 }
9a799d71 4898
a34bcfff
AD		 4899 /* XXX: to interrupt immediately for EICS writes, enable this */
4900 /* gpie |= IXGBE_GPIE_EIMEN; */
4901
4902 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4903 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4904
4905 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4906 case IXGBE_82599_VMDQ_8Q_MASK:
4907 gpie |= IXGBE_GPIE_VTMODE_16;
4908 break;
4909 case IXGBE_82599_VMDQ_4Q_MASK:
4910 gpie |= IXGBE_GPIE_VTMODE_32;
4911 break;
4912 default:
4913 gpie |= IXGBE_GPIE_VTMODE_64;
4914 break;
4915 }
119fc60a
MC		 4916 }
4917
5fdd31f9 4918 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4919 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4920 switch (adapter->hw.mac.type) {
4921 case ixgbe_mac_82599EB:
9a900eca 4922 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 4923 break;
f3df98ec
DS		 4924 default:
4925 break;
4926 }
4927 }
5fdd31f9 4928
a34bcfff
AD		 4929 /* Enable fan failure interrupt */
4930 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 4931 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 4932
a023bbd0
DS		 4933 switch (hw->mac.type) {
4934 case ixgbe_mac_82599EB:
4935 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
4936 break;
4937 case ixgbe_mac_X550EM_x:
4938 gpie |= IXGBE_SDP0_GPIEN_X540;
4939 break;
4940 default:
4941 break;
2698b208 4942 }
a34bcfff
AD		 4943
4944 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4945}
4946
c7ccde0f 4947static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4948{
4949 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4950 int err;
a34bcfff
AD		 4951 u32 ctrl_ext;
4952
4953 ixgbe_get_hw_control(adapter);
4954 ixgbe_setup_gpie(adapter);
e8e26350 4955
9a799d71
AK		 4956 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4957 ixgbe_configure_msix(adapter);
4958 else
4959 ixgbe_configure_msi_and_legacy(adapter);
4960
ec74a471
ET		 4961 /* enable the optics for 82599 SFP+ fiber */
4962 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4963 hw->mac.ops.enable_tx_laser(hw);
4964
961fac88
DS		 4965 if (hw->phy.ops.set_phy_power)
4966 hw->phy.ops.set_phy_power(hw, true);
4967
4e857c58 4968 smp_mb__before_atomic();
9a799d71 4969 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4970 ixgbe_napi_enable_all(adapter);
4971
73c4b7cd
AD		 4972 if (ixgbe_is_sfp(hw)) {
4973 ixgbe_sfp_link_config(adapter);
4974 } else {
4975 err = ixgbe_non_sfp_link_config(hw);
4976 if (err)
4977 e_err(probe, "link_config FAILED %d\n", err);
4978 }
4979
021230d4
AV		 4980 /* clear any pending interrupts, may auto mask */
4981 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4982 ixgbe_irq_enable(adapter, true, true);
9a799d71 4983
bf069c97
DS		 4984 /*
4985 * If this adapter has a fan, check to see if we had a failure
4986 * before we enabled the interrupt.
4987 */
4988 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4989 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4990 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4991 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4992 }
4993
9a799d71
AK		 4994 /* bring the link up in the watchdog, this could race with our first
4995 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4996 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4997 adapter->link_check_timeout = jiffies;
7086400d 4998 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4999
5000 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5001 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5002 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5003 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5004}
5005
d4f80882
AV		 5006void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5007{
5008 WARN_ON(in_interrupt());
7086400d
AD		 5009 /* put off any impending NetWatchDogTimeout */
5010 adapter->netdev->trans_start = jiffies;
5011
d4f80882 5012 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5013 usleep_range(1000, 2000);
d4f80882 5014 ixgbe_down(adapter);
5809a1ae
GR		 5015 /*
5016 * If SR-IOV enabled then wait a bit before bringing the adapter
5017 * back up to give the VFs time to respond to the reset. The
5018 * two second wait is based upon the watchdog timer cycle in
5019 * the VF driver.
5020 */
5021 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5022 msleep(2000);
d4f80882
AV		 5023 ixgbe_up(adapter);
5024 clear_bit(__IXGBE_RESETTING, &adapter->state);
5025}
5026
c7ccde0f 5027void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5028{
5029 /* hardware has been reset, we need to reload some things */
5030 ixgbe_configure(adapter);
5031
c7ccde0f 5032 ixgbe_up_complete(adapter);
9a799d71
AK		 5033}
5034
5035void ixgbe_reset(struct ixgbe_adapter *adapter)
5036{
c44ade9e 5037 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5038 struct net_device *netdev = adapter->netdev;
8ca783ab 5039 int err;
5d7daa35 5040 u8 old_addr[ETH_ALEN];
8ca783ab 5041
b0483c8f
MR		 5042 if (ixgbe_removed(hw->hw_addr))
5043 return;
7086400d
AD		 5044 /* lock SFP init bit to prevent race conditions with the watchdog */
5045 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5046 usleep_range(1000, 2000);
5047
5048 /* clear all SFP and link config related flags while holding SFP_INIT */
5049 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5050 IXGBE_FLAG2_SFP_NEEDS_RESET);
5051 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5052
8ca783ab 5053 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5054 switch (err) {
5055 case 0:
5056 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5057 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5058 break;
5059 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5060 e_dev_err("master disable timed out\n");
da4dd0f7 5061 break;
794caeb2
PWJ		 5062 case IXGBE_ERR_EEPROM_VERSION:
5063 /* We are running on a pre-production device, log a warning */
849c4542 5064 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5065 "Please be aware there may be issues associated with "
849c4542
ET		 5066 "your hardware. If you are experiencing problems "
5067 "please contact your Intel or hardware "
5068 "representative who provided you with this "
5069 "hardware.\n");
794caeb2 5070 break;
da4dd0f7 5071 default:
849c4542 5072 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5073 }
9a799d71 5074
7086400d 5075 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 5076 /* do not flush user set addresses */
5077 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5078 ixgbe_flush_sw_mac_table(adapter);
5079 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 5080
5081 /* update SAN MAC vmdq pool selection */
5082 if (hw->mac.san_mac_rar_index)
5083 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5084
8fecf67c 5085 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5086 ixgbe_ptp_reset(adapter);
961fac88
DS		 5087
5088 if (hw->phy.ops.set_phy_power) {
5089 if (!netif_running(adapter->netdev) && !adapter->wol)
5090 hw->phy.ops.set_phy_power(hw, false);
5091 else
5092 hw->phy.ops.set_phy_power(hw, true);
5093 }
9a799d71
AK		 5094}
5095
9a799d71
AK		 5096/**
5097 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5098 * @tx_ring: ring to be cleaned
5099 **/
b6ec895e 5100static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5101{
5102 struct ixgbe_tx_buffer *tx_buffer_info;
5103 unsigned long size;
b6ec895e 5104 u16 i;
9a799d71 5105
84418e3b
AD		 5106 /* ring already cleared, nothing to do */
5107 if (!tx_ring->tx_buffer_info)
5108 return;
9a799d71 5109
84418e3b 5110 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5111 for (i = 0; i < tx_ring->count; i++) {
5112 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5113 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5114 }
5115
dad8a3b3
JF		 5116 netdev_tx_reset_queue(txring_txq(tx_ring));
5117
9a799d71
AK		 5118 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5119 memset(tx_ring->tx_buffer_info, 0, size);
5120
5121 /* Zero out the descriptor ring */
5122 memset(tx_ring->desc, 0, tx_ring->size);
5123
5124 tx_ring->next_to_use = 0;
5125 tx_ring->next_to_clean = 0;
9a799d71
AK		 5126}
5127
5128/**
021230d4 5129 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5130 * @adapter: board private structure
5131 **/
021230d4 5132static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5133{
5134 int i;
5135
021230d4 5136 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5137 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5138}
5139
5140/**
021230d4 5141 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5142 * @adapter: board private structure
5143 **/
021230d4 5144static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5145{
5146 int i;
5147
021230d4 5148 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5149 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5150}
5151
e4911d57
AD		 5152static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5153{
b67bfe0d 5154 struct hlist_node *node2;
e4911d57
AD		 5155 struct ixgbe_fdir_filter *filter;
5156
5157 spin_lock(&adapter->fdir_perfect_lock);
5158
b67bfe0d 5159 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5160 &adapter->fdir_filter_list, fdir_node) {
5161 hlist_del(&filter->fdir_node);
5162 kfree(filter);
5163 }
5164 adapter->fdir_filter_count = 0;
5165
5166 spin_unlock(&adapter->fdir_perfect_lock);
5167}
5168
9a799d71
AK		 5169void ixgbe_down(struct ixgbe_adapter *adapter)
5170{
5171 struct net_device *netdev = adapter->netdev;
7f821875 5172 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5173 struct net_device *upper;
5174 struct list_head *iter;
bf29ee6c 5175 int i;
9a799d71
AK		 5176
5177 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5178 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5179 return; /* do nothing if already down */
9a799d71
AK		 5180
5181 /* disable receives */
1f9ac57c 5182 hw->mac.ops.disable_rx(hw);
9a799d71 5183
2d39d576
YZ		 5184 /* disable all enabled rx queues */
5185 for (i = 0; i < adapter->num_rx_queues; i++)
5186 /* this call also flushes the previous write */
5187 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5188
032b4325 5189 usleep_range(10000, 20000);
9a799d71 5190
7f821875
JB		 5191 netif_tx_stop_all_queues(netdev);
5192
7086400d 5193 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5194 netif_carrier_off(netdev);
5195 netif_tx_disable(netdev);
5196
2a47fa45
JF		 5197 /* disable any upper devices */
5198 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5199 if (netif_is_macvlan(upper)) {
5200 struct macvlan_dev *vlan = netdev_priv(upper);
5201
5202 if (vlan->fwd_priv) {
5203 netif_tx_stop_all_queues(upper);
5204 netif_carrier_off(upper);
5205 netif_tx_disable(upper);
5206 }
5207 }
5208 }
5209
c0dfb90e
JF		 5210 ixgbe_irq_disable(adapter);
5211
5212 ixgbe_napi_disable_all(adapter);
5213
d034acf1
AD		 5214 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5215 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5216 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5217
5218 del_timer_sync(&adapter->service_timer);
5219
34cecbbf 5220 if (adapter->num_vfs) {
8e34d1aa
AD		 5221 /* Clear EITR Select mapping */
5222 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5223
5224 /* Mark all the VFs as inactive */
5225 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5226 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5227
34cecbbf
AD		 5228 /* ping all the active vfs to let them know we are going down */
5229 ixgbe_ping_all_vfs(adapter);
5230
5231 /* Disable all VFTE/VFRE TX/RX */
5232 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5233 }
5234
7f821875
JB		 5235 /* disable transmits in the hardware now that interrupts are off */
5236 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5237 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5238 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5239 }
34cecbbf 5240
9a75a1ac 5241 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5242 switch (hw->mac.type) {
5243 case ixgbe_mac_82599EB:
b93a2226 5244 case ixgbe_mac_X540:
9a75a1ac
DS		 5245 case ixgbe_mac_X550:
5246 case ixgbe_mac_X550EM_x:
88512539 5247 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5248 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5249 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5250 break;
5251 default:
5252 break;
5253 }
7f821875 5254
6f4a0e45
PL		 5255 if (!pci_channel_offline(adapter->pdev))
5256 ixgbe_reset(adapter);
c6ecf39a 5257
ec74a471
ET		 5258 /* power down the optics for 82599 SFP+ fiber */
5259 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5260 hw->mac.ops.disable_tx_laser(hw);
5261
9a799d71
AK		 5262 ixgbe_clean_all_tx_rings(adapter);
5263 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5264}
5265
9a799d71
AK		 5266/**
5267 * ixgbe_tx_timeout - Respond to a Tx Hang
5268 * @netdev: network interface device structure
5269 **/
5270static void ixgbe_tx_timeout(struct net_device *netdev)
5271{
5272 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5273
5274 /* Do the reset outside of interrupt context */
c83c6cbd 5275 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5276}
5277
9a799d71
AK		 5278/**
5279 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5280 * @adapter: board private structure to initialize
5281 *
5282 * ixgbe_sw_init initializes the Adapter private data structure.
5283 * Fields are initialized based on PCI device information and
5284 * OS network device settings (MTU size).
5285 **/
9f9a12f8 5286static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5287{
5288 struct ixgbe_hw *hw = &adapter->hw;
5289 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5290 unsigned int rss, fdir;
cb6d0f5e 5291 u32 fwsm;
7a6b6f51 5292#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5293 int j;
5294 struct tc_configuration *tc;
5295#endif
021230d4 5296
c44ade9e
JB		 5297 /* PCI config space info */
5298
5299 hw->vendor_id = pdev->vendor;
5300 hw->device_id = pdev->device;
5301 hw->revision_id = pdev->revision;
5302 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5303 hw->subsystem_device_id = pdev->subsystem_device;
5304
8fc3bb6d 5305 /* Set common capability flags and settings */
0f9b232b 5306 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5307 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5308 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5309 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5310 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5311 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5312 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5313 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5314#ifdef CONFIG_IXGBE_DCA
5315 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5316#endif
5317#ifdef IXGBE_FCOE
5318 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5319 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5320#ifdef CONFIG_IXGBE_DCB
5321 /* Default traffic class to use for FCoE */
5322 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5323#endif /* CONFIG_IXGBE_DCB */
5324#endif /* IXGBE_FCOE */
5325
5d7daa35
JK		 5326 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5327 hw->mac.num_rar_entries,
5328 GFP_ATOMIC);
5329
8fc3bb6d 5330 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5331 switch (hw->mac.type) {
5332 case ixgbe_mac_82598EB:
8fc3bb6d 5333 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5334
bf069c97
DS		 5335 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5336 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5337
49c7ffbe 5338 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5339 adapter->ring_feature[RING_F_FDIR].limit = 0;
5340 adapter->atr_sample_rate = 0;
5341 adapter->fdir_pballoc = 0;
5342#ifdef IXGBE_FCOE
5343 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5344 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5345#ifdef CONFIG_IXGBE_DCB
5346 adapter->fcoe.up = 0;
5347#endif /* IXGBE_DCB */
5348#endif /* IXGBE_FCOE */
5349 break;
5350 case ixgbe_mac_82599EB:
5351 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5352 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5353 break;
b93a2226 5354 case ixgbe_mac_X540:
9a900eca 5355 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5356 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5357 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5358 break;
9a75a1ac
DS		 5359 case ixgbe_mac_X550EM_x:
5360 case ixgbe_mac_X550:
5361#ifdef CONFIG_IXGBE_DCA
5362 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5363#endif
5364#ifdef CONFIG_IXGBE_VXLAN
5365 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5366#endif
5367 break;
bd508178
AD		 5368 default:
5369 break;
f8212f97 5370 }
2f90b865 5371
7c8ae65a
AD		 5372#ifdef IXGBE_FCOE
5373 /* FCoE support exists, always init the FCoE lock */
5374 spin_lock_init(&adapter->fcoe.lock);
5375
5376#endif
1fc5f038
AD		 5377 /* n-tuple support exists, always init our spinlock */
5378 spin_lock_init(&adapter->fdir_perfect_lock);
5379
7a6b6f51 5380#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5381 switch (hw->mac.type) {
5382 case ixgbe_mac_X540:
9a75a1ac
DS		 5383 case ixgbe_mac_X550:
5384 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5385 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5386 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5387 break;
5388 default:
5389 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5390 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5391 break;
5392 }
5393
2f90b865
AD		 5394 /* Configure DCB traffic classes */
5395 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5396 tc = &adapter->dcb_cfg.tc_config[j];
5397 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5398 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5399 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5400 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5401 tc->dcb_pfc = pfc_disabled;
5402 }
4de2a022
JF		 5403
5404 /* Initialize default user to priority mapping, UPx->TC0 */
5405 tc = &adapter->dcb_cfg.tc_config[0];
5406 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5407 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5408
2f90b865
AD		 5409 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5410 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5411 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5412 adapter->dcb_set_bitmap = 0x00;
3032309b 5413 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5414 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5415 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5416
5417#endif
9a799d71
AK		 5418
5419 /* default flow control settings */
cd7664f6 5420 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5421 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5422 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5423 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5424 hw->fc.send_xon = true;
73d80953 5425 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5426
99d74487 5427#ifdef CONFIG_PCI_IOV
170e8543
JK		 5428 if (max_vfs > 0)
5429 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5430
99d74487 5431 /* assign number of SR-IOV VFs */
170e8543 5432 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5433 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5434 adapter->num_vfs = 0;
5435 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5436 } else {
5437 adapter->num_vfs = max_vfs;
5438 }
5439 }
5440#endif /* CONFIG_PCI_IOV */
99d74487 5441
30efa5a3 5442 /* enable itr by default in dynamic mode */
f7554a2b 5443 adapter->rx_itr_setting = 1;
f7554a2b 5444 adapter->tx_itr_setting = 1;
30efa5a3 5445
30efa5a3
JB		 5446 /* set default ring sizes */
5447 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5448 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5449
bd198058 5450 /* set default work limits */
59224555 5451 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5452
9a799d71 5453 /* initialize eeprom parameters */
c44ade9e 5454 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5455 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5456 return -EIO;
5457 }
5458
2a47fa45
JF		 5459 /* PF holds first pool slot */
5460 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5461 set_bit(__IXGBE_DOWN, &adapter->state);
5462
5463 return 0;
5464}
5465
5466/**
5467 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5468 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5469 *
5470 * Return 0 on success, negative on failure
5471 **/
b6ec895e 5472int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5473{
b6ec895e 5474 struct device *dev = tx_ring->dev;
de88eeeb 5475 int orig_node = dev_to_node(dev);
ca8dfe25 5476 int ring_node = -1;
9a799d71
AK		 5477 int size;
5478
3a581073 5479 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5480
5481 if (tx_ring->q_vector)
ca8dfe25 5482 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5483
ca8dfe25 5484 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5485 if (!tx_ring->tx_buffer_info)
89bf67f1 5486 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5487 if (!tx_ring->tx_buffer_info)
5488 goto err;
9a799d71 5489
827da44c
JS		 5490 u64_stats_init(&tx_ring->syncp);
5491
9a799d71 5492 /* round up to nearest 4K */
12207e49 5493 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5494 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5495
ca8dfe25 5496 set_dev_node(dev, ring_node);
de88eeeb
AD		 5497 tx_ring->desc = dma_alloc_coherent(dev,
5498 tx_ring->size,
5499 &tx_ring->dma,
5500 GFP_KERNEL);
5501 set_dev_node(dev, orig_node);
5502 if (!tx_ring->desc)
5503 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5504 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5505 if (!tx_ring->desc)
5506 goto err;
9a799d71 5507
3a581073
JB		 5508 tx_ring->next_to_use = 0;
5509 tx_ring->next_to_clean = 0;
9a799d71 5510 return 0;
e01c31a5
JB		 5511
5512err:
5513 vfree(tx_ring->tx_buffer_info);
5514 tx_ring->tx_buffer_info = NULL;
b6ec895e 5515 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5516 return -ENOMEM;
9a799d71
AK		 5517}
5518
69888674
AD		 5519/**
5520 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5521 * @adapter: board private structure
5522 *
5523 * If this function returns with an error, then it's possible one or
5524 * more of the rings is populated (while the rest are not). It is the
5525 * callers duty to clean those orphaned rings.
5526 *
5527 * Return 0 on success, negative on failure
5528 **/
5529static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5530{
5531 int i, err = 0;
5532
5533 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5534 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5535 if (!err)
5536 continue;
de3d5b94 5537
396e799c 5538 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5539 goto err_setup_tx;
69888674
AD		 5540 }
5541
de3d5b94
AD		 5542 return 0;
5543err_setup_tx:
5544 /* rewind the index freeing the rings as we go */
5545 while (i--)
5546 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5547 return err;
5548}
5549
9a799d71
AK		 5550/**
5551 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5552 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5553 *
5554 * Returns 0 on success, negative on failure
5555 **/
b6ec895e 5556int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5557{
b6ec895e 5558 struct device *dev = rx_ring->dev;
de88eeeb 5559 int orig_node = dev_to_node(dev);
ca8dfe25 5560 int ring_node = -1;
021230d4 5561 int size;
9a799d71 5562
3a581073 5563 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5564
5565 if (rx_ring->q_vector)
ca8dfe25 5566 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5567
ca8dfe25 5568 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5569 if (!rx_ring->rx_buffer_info)
89bf67f1 5570 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5571 if (!rx_ring->rx_buffer_info)
5572 goto err;
9a799d71 5573
827da44c
JS		 5574 u64_stats_init(&rx_ring->syncp);
5575
9a799d71 5576 /* Round up to nearest 4K */
3a581073
JB		 5577 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5578 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5579
ca8dfe25 5580 set_dev_node(dev, ring_node);
de88eeeb
AD		 5581 rx_ring->desc = dma_alloc_coherent(dev,
5582 rx_ring->size,
5583 &rx_ring->dma,
5584 GFP_KERNEL);
5585 set_dev_node(dev, orig_node);
5586 if (!rx_ring->desc)
5587 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5588 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5589 if (!rx_ring->desc)
5590 goto err;
9a799d71 5591
3a581073
JB		 5592 rx_ring->next_to_clean = 0;
5593 rx_ring->next_to_use = 0;
9a799d71
AK		 5594
5595 return 0;
b6ec895e
AD		 5596err:
5597 vfree(rx_ring->rx_buffer_info);
5598 rx_ring->rx_buffer_info = NULL;
5599 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5600 return -ENOMEM;
9a799d71
AK		 5601}
5602
69888674
AD		 5603/**
5604 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5605 * @adapter: board private structure
5606 *
5607 * If this function returns with an error, then it's possible one or
5608 * more of the rings is populated (while the rest are not). It is the
5609 * callers duty to clean those orphaned rings.
5610 *
5611 * Return 0 on success, negative on failure
5612 **/
69888674
AD		 5613static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5614{
5615 int i, err = 0;
5616
5617 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5618 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5619 if (!err)
5620 continue;
de3d5b94 5621
396e799c 5622 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5623 goto err_setup_rx;
69888674
AD		 5624 }
5625
7c8ae65a
AD		 5626#ifdef IXGBE_FCOE
5627 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5628 if (!err)
5629#endif
5630 return 0;
de3d5b94
AD		 5631err_setup_rx:
5632 /* rewind the index freeing the rings as we go */
5633 while (i--)
5634 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5635 return err;
5636}
5637
9a799d71
AK		 5638/**
5639 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5640 * @tx_ring: Tx descriptor ring for a specific queue
5641 *
5642 * Free all transmit software resources
5643 **/
b6ec895e 5644void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5645{
b6ec895e 5646 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5647
5648 vfree(tx_ring->tx_buffer_info);
5649 tx_ring->tx_buffer_info = NULL;
5650
b6ec895e
AD		 5651 /* if not set, then don't free */
5652 if (!tx_ring->desc)
5653 return;
5654
5655 dma_free_coherent(tx_ring->dev, tx_ring->size,
5656 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5657
5658 tx_ring->desc = NULL;
5659}
5660
5661/**
5662 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5663 * @adapter: board private structure
5664 *
5665 * Free all transmit software resources
5666 **/
5667static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5668{
5669 int i;
5670
5671 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5672 if (adapter->tx_ring[i]->desc)
b6ec895e 5673 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5674}
5675
5676/**
b4617240 5677 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5678 * @rx_ring: ring to clean the resources from
5679 *
5680 * Free all receive software resources
5681 **/
b6ec895e 5682void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5683{
b6ec895e 5684 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5685
5686 vfree(rx_ring->rx_buffer_info);
5687 rx_ring->rx_buffer_info = NULL;
5688
b6ec895e
AD		 5689 /* if not set, then don't free */
5690 if (!rx_ring->desc)
5691 return;
5692
5693 dma_free_coherent(rx_ring->dev, rx_ring->size,
5694 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5695
5696 rx_ring->desc = NULL;
5697}
5698
5699/**
5700 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5701 * @adapter: board private structure
5702 *
5703 * Free all receive software resources
5704 **/
5705static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5706{
5707 int i;
5708
7c8ae65a
AD		 5709#ifdef IXGBE_FCOE
5710 ixgbe_free_fcoe_ddp_resources(adapter);
5711
5712#endif
9a799d71 5713 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5714 if (adapter->rx_ring[i]->desc)
b6ec895e 5715 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5716}
5717
9a799d71
AK		 5718/**
5719 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5720 * @netdev: network interface device structure
5721 * @new_mtu: new value for maximum frame size
5722 *
5723 * Returns 0 on success, negative on failure
5724 **/
5725static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5726{
5727 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5728 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5729
42c783c5 5730 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5731 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5732 return -EINVAL;
5733
5734 /*
872844dd
AD		 5735 * For 82599EB we cannot allow legacy VFs to enable their receive
5736 * paths when MTU greater than 1500 is configured. So display a
5737 * warning that legacy VFs will be disabled.
655309e9
AD		 5738 */
5739 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5740 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5741 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5742 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5743
396e799c 5744 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5745
021230d4 5746 /* must set new MTU before calling down or up */
9a799d71
AK		 5747 netdev->mtu = new_mtu;
5748
d4f80882
AV		 5749 if (netif_running(netdev))
5750 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5751
5752 return 0;
5753}
5754
5755/**
5756 * ixgbe_open - Called when a network interface is made active
5757 * @netdev: network interface device structure
5758 *
5759 * Returns 0 on success, negative value on failure
5760 *
5761 * The open entry point is called when a network interface is made
5762 * active by the system (IFF_UP). At this point all resources needed
5763 * for transmit and receive operations are allocated, the interrupt
5764 * handler is registered with the OS, the watchdog timer is started,
5765 * and the stack is notified that the interface is ready.
5766 **/
5767static int ixgbe_open(struct net_device *netdev)
5768{
5769 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5770 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5771 int err, queues;
4bebfaa5
AK		 5772
5773 /* disallow open during test */
5774 if (test_bit(__IXGBE_TESTING, &adapter->state))
5775 return -EBUSY;
9a799d71 5776
54386467
JB		 5777 netif_carrier_off(netdev);
5778
9a799d71
AK		 5779 /* allocate transmit descriptors */
5780 err = ixgbe_setup_all_tx_resources(adapter);
5781 if (err)
5782 goto err_setup_tx;
5783
9a799d71
AK		 5784 /* allocate receive descriptors */
5785 err = ixgbe_setup_all_rx_resources(adapter);
5786 if (err)
5787 goto err_setup_rx;
5788
5789 ixgbe_configure(adapter);
5790
021230d4 5791 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5792 if (err)
5793 goto err_req_irq;
5794
ac802f5d 5795 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5796 if (adapter->num_rx_pools > 1)
5797 queues = adapter->num_rx_queues_per_pool;
5798 else
5799 queues = adapter->num_tx_queues;
5800
5801 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5802 if (err)
5803 goto err_set_queues;
5804
2a47fa45
JF		 5805 if (adapter->num_rx_pools > 1 &&
5806 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5807 queues = IXGBE_MAX_L2A_QUEUES;
5808 else
5809 queues = adapter->num_rx_queues;
5810 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5811 if (err)
5812 goto err_set_queues;
5813
1a71ab24 5814 ixgbe_ptp_init(adapter);
1a71ab24 5815
c7ccde0f 5816 ixgbe_up_complete(adapter);
9a799d71 5817
67359c3c
MR		 5818 ixgbe_clear_vxlan_port(adapter);
5819#ifdef CONFIG_IXGBE_VXLAN
3f207800 5820 vxlan_get_rx_port(netdev);
3f207800 5821#endif
67359c3c 5822
9a799d71
AK		 5823 return 0;
5824
ac802f5d
AD		 5825err_set_queues:
5826 ixgbe_free_irq(adapter);
9a799d71 5827err_req_irq:
a20a1199 5828 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 5829 if (hw->phy.ops.set_phy_power && !adapter->wol)
5830 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 5831err_setup_rx:
a20a1199 5832 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5833err_setup_tx:
9a799d71
AK		 5834 ixgbe_reset(adapter);
5835
5836 return err;
5837}
5838
a0cccce2
JK		 5839static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5840{
5841 ixgbe_ptp_suspend(adapter);
5842
6ac74394
DS		 5843 if (adapter->hw.phy.ops.enter_lplu) {
5844 adapter->hw.phy.reset_disable = true;
5845 ixgbe_down(adapter);
5846 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5847 adapter->hw.phy.reset_disable = false;
5848 } else {
5849 ixgbe_down(adapter);
5850 }
5851
a0cccce2
JK		 5852 ixgbe_free_irq(adapter);
5853
5854 ixgbe_free_all_tx_resources(adapter);
5855 ixgbe_free_all_rx_resources(adapter);
5856}
5857
9a799d71
AK		 5858/**
5859 * ixgbe_close - Disables a network interface
5860 * @netdev: network interface device structure
5861 *
5862 * Returns 0, this is not allowed to fail
5863 *
5864 * The close entry point is called when an interface is de-activated
5865 * by the OS. The hardware is still under the drivers control, but
5866 * needs to be disabled. A global MAC reset is issued to stop the
5867 * hardware, and all transmit and receive resources are freed.
5868 **/
5869static int ixgbe_close(struct net_device *netdev)
5870{
5871 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5872
1a71ab24 5873 ixgbe_ptp_stop(adapter);
1a71ab24 5874
a0cccce2 5875 ixgbe_close_suspend(adapter);
9a799d71 5876
e4911d57
AD		 5877 ixgbe_fdir_filter_exit(adapter);
5878
5eba3699 5879 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5880
5881 return 0;
5882}
5883
b3c8b4ba
AD		 5884#ifdef CONFIG_PM
5885static int ixgbe_resume(struct pci_dev *pdev)
5886{
c60fbb00
AD		 5887 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5888 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5889 u32 err;
5890
0391bbe3 5891 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5892 pci_set_power_state(pdev, PCI_D0);
5893 pci_restore_state(pdev);
656ab817
DS		 5894 /*
5895 * pci_restore_state clears dev->state_saved so call
5896 * pci_save_state to restore it.
5897 */
5898 pci_save_state(pdev);
9ce77666 5899
5900 err = pci_enable_device_mem(pdev);
b3c8b4ba 5901 if (err) {
849c4542 5902 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5903 return err;
5904 }
4e857c58 5905 smp_mb__before_atomic();
41c62843 5906 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5907 pci_set_master(pdev);
5908
dd4d8ca6 5909 pci_wake_from_d3(pdev, false);
b3c8b4ba 5910
b3c8b4ba
AD		 5911 ixgbe_reset(adapter);
5912
495dce12
WJP		 5913 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5914
ac802f5d
AD		 5915 rtnl_lock();
5916 err = ixgbe_init_interrupt_scheme(adapter);
5917 if (!err && netif_running(netdev))
c60fbb00 5918 err = ixgbe_open(netdev);
ac802f5d
AD		 5919
5920 rtnl_unlock();
5921
5922 if (err)
5923 return err;
b3c8b4ba
AD		 5924
5925 netif_device_attach(netdev);
5926
5927 return 0;
5928}
b3c8b4ba 5929#endif /* CONFIG_PM */
9d8d05ae
RW		 5930
5931static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5932{
c60fbb00
AD		 5933 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5934 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5935 struct ixgbe_hw *hw = &adapter->hw;
5936 u32 ctrl, fctrl;
5937 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5938#ifdef CONFIG_PM
5939 int retval = 0;
5940#endif
5941
5942 netif_device_detach(netdev);
5943
499ab5cc 5944 rtnl_lock();
a0cccce2
JK		 5945 if (netif_running(netdev))
5946 ixgbe_close_suspend(adapter);
499ab5cc 5947 rtnl_unlock();
b3c8b4ba 5948
5f5ae6fc
AD		 5949 ixgbe_clear_interrupt_scheme(adapter);
5950
b3c8b4ba
AD		 5951#ifdef CONFIG_PM
5952 retval = pci_save_state(pdev);
5953 if (retval)
5954 return retval;
4df10466 5955
b3c8b4ba 5956#endif
f4f1040a
JK		 5957 if (hw->mac.ops.stop_link_on_d3)
5958 hw->mac.ops.stop_link_on_d3(hw);
5959
e8e26350
PW		 5960 if (wufc) {
5961 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5962
ec74a471
ET		 5963 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5964 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5965 hw->mac.ops.enable_tx_laser(hw);
5966
e8e26350
PW		 5967 /* turn on all-multi mode if wake on multicast is enabled */
5968 if (wufc & IXGBE_WUFC_MC) {
5969 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5970 fctrl |= IXGBE_FCTRL_MPE;
5971 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5972 }
5973
5974 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5975 ctrl |= IXGBE_CTRL_GIO_DIS;
5976 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5977
5978 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5979 } else {
5980 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5981 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5982 }
5983
bd508178
AD		 5984 switch (hw->mac.type) {
5985 case ixgbe_mac_82598EB:
dd4d8ca6 5986 pci_wake_from_d3(pdev, false);
bd508178
AD		 5987 break;
5988 case ixgbe_mac_82599EB:
b93a2226 5989 case ixgbe_mac_X540:
9a75a1ac
DS		 5990 case ixgbe_mac_X550:
5991 case ixgbe_mac_X550EM_x:
bd508178
AD		 5992 pci_wake_from_d3(pdev, !!wufc);
5993 break;
5994 default:
5995 break;
5996 }
b3c8b4ba 5997
9d8d05ae 5998 *enable_wake = !!wufc;
961fac88
DS		 5999 if (hw->phy.ops.set_phy_power && !*enable_wake)
6000 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6001
b3c8b4ba
AD		 6002 ixgbe_release_hw_control(adapter);
6003
41c62843
MR		 6004 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6005 pci_disable_device(pdev);
b3c8b4ba 6006
9d8d05ae
RW		 6007 return 0;
6008}
6009
6010#ifdef CONFIG_PM
6011static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6012{
6013 int retval;
6014 bool wake;
6015
6016 retval = __ixgbe_shutdown(pdev, &wake);
6017 if (retval)
6018 return retval;
6019
6020 if (wake) {
6021 pci_prepare_to_sleep(pdev);
6022 } else {
6023 pci_wake_from_d3(pdev, false);
6024 pci_set_power_state(pdev, PCI_D3hot);
6025 }
b3c8b4ba
AD		 6026
6027 return 0;
6028}
9d8d05ae 6029#endif /* CONFIG_PM */
b3c8b4ba
AD		 6030
6031static void ixgbe_shutdown(struct pci_dev *pdev)
6032{
9d8d05ae
RW		 6033 bool wake;
6034
6035 __ixgbe_shutdown(pdev, &wake);
6036
6037 if (system_state == SYSTEM_POWER_OFF) {
6038 pci_wake_from_d3(pdev, wake);
6039 pci_set_power_state(pdev, PCI_D3hot);
6040 }
b3c8b4ba
AD		 6041}
6042
9a799d71
AK		 6043/**
6044 * ixgbe_update_stats - Update the board statistics counters.
6045 * @adapter: board private structure
6046 **/
6047void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6048{
2d86f139 6049 struct net_device *netdev = adapter->netdev;
9a799d71 6050 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6051 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6052 u64 total_mpc = 0;
6053 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6054 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6055 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6056 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6057
d08935c2
DS		 6058 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6059 test_bit(__IXGBE_RESETTING, &adapter->state))
6060 return;
6061
94b982b2 6062 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6063 u64 rsc_count = 0;
94b982b2 6064 u64 rsc_flush = 0;
94b982b2 6065 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6066 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6067 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6068 }
6069 adapter->rsc_total_count = rsc_count;
6070 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6071 }
6072
5b7da515
AD		 6073 for (i = 0; i < adapter->num_rx_queues; i++) {
6074 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6075 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6076 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6077 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6078 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6079 bytes += rx_ring->stats.bytes;
6080 packets += rx_ring->stats.packets;
6081 }
6082 adapter->non_eop_descs = non_eop_descs;
6083 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6084 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6085 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6086 netdev->stats.rx_bytes = bytes;
6087 netdev->stats.rx_packets = packets;
6088
6089 bytes = 0;
6090 packets = 0;
7ca3bc58 6091 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6092 for (i = 0; i < adapter->num_tx_queues; i++) {
6093 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6094 restart_queue += tx_ring->tx_stats.restart_queue;
6095 tx_busy += tx_ring->tx_stats.tx_busy;
6096 bytes += tx_ring->stats.bytes;
6097 packets += tx_ring->stats.packets;
6098 }
eb985f09 6099 adapter->restart_queue = restart_queue;
5b7da515
AD		 6100 adapter->tx_busy = tx_busy;
6101 netdev->stats.tx_bytes = bytes;
6102 netdev->stats.tx_packets = packets;
7ca3bc58 6103
7ca647bd 6104 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6105
6106 /* 8 register reads */
6f11eef7
AV		 6107 for (i = 0; i < 8; i++) {
6108 /* for packet buffers not used, the register should read 0 */
6109 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6110 missed_rx += mpc;
7ca647bd
JP		 6111 hwstats->mpc[i] += mpc;
6112 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6113 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6114 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6115 switch (hw->mac.type) {
6116 case ixgbe_mac_82598EB:
1a70db4b
ET		 6117 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6118 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6119 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6120 hwstats->pxonrxc[i] +=
6121 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6122 break;
6123 case ixgbe_mac_82599EB:
b93a2226 6124 case ixgbe_mac_X540:
9a75a1ac
DS		 6125 case ixgbe_mac_X550:
6126 case ixgbe_mac_X550EM_x:
bd508178
AD		 6127 hwstats->pxonrxc[i] +=
6128 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6129 break;
6130 default:
6131 break;
e8e26350 6132 }
6f11eef7 6133 }
1a70db4b
ET		 6134
6135 /*16 register reads */
6136 for (i = 0; i < 16; i++) {
6137 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6138 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6139 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6140 (hw->mac.type == ixgbe_mac_X540) ||
6141 (hw->mac.type == ixgbe_mac_X550) ||
6142 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6143 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6144 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6145 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6146 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6147 }
6148 }
6149
7ca647bd 6150 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6151 /* work around hardware counting issue */
7ca647bd 6152 hwstats->gprc -= missed_rx;
6f11eef7 6153
c84d324c
JF		 6154 ixgbe_update_xoff_received(adapter);
6155
6f11eef7 6156 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6157 switch (hw->mac.type) {
6158 case ixgbe_mac_82598EB:
6159 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6160 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6161 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6162 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6163 break;
b93a2226 6164 case ixgbe_mac_X540:
9a75a1ac
DS		 6165 case ixgbe_mac_X550:
6166 case ixgbe_mac_X550EM_x:
6167 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6168 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6169 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6170 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6171 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6172 case ixgbe_mac_82599EB:
a4d4f629
AD		 6173 for (i = 0; i < 16; i++)
6174 adapter->hw_rx_no_dma_resources +=
6175 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6176 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6177 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6178 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6179 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6180 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6181 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6182 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6183 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6184 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6185#ifdef IXGBE_FCOE
7ca647bd
JP		 6186 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6187 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6188 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6189 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6190 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6191 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6192 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6193 if (adapter->fcoe.ddp_pool) {
6194 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6195 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6196 unsigned int cpu;
6197 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6198 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6199 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6200 noddp += ddp_pool->noddp;
6201 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6202 }
5a1ee270
AD		 6203 hwstats->fcoe_noddp = noddp;
6204 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6205 }
6d45522c 6206#endif /* IXGBE_FCOE */
bd508178
AD		 6207 break;
6208 default:
6209 break;
e8e26350 6210 }
9a799d71 6211 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6212 hwstats->bprc += bprc;
6213 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6214 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6215 hwstats->mprc -= bprc;
6216 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6217 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6218 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6219 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6220 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6221 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6222 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6223 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6224 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6225 hwstats->lxontxc += lxon;
6f11eef7 6226 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6227 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6228 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6229 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6230 /*
6231 * 82598 errata - tx of flow control packets is included in tx counters
6232 */
6233 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6234 hwstats->gptc -= xon_off_tot;
6235 hwstats->mptc -= xon_off_tot;
6236 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6237 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6238 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6239 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6240 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6241 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6242 hwstats->ptc64 -= xon_off_tot;
6243 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6244 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6245 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6246 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6247 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6248 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6249
6250 /* Fill out the OS statistics structure */
7ca647bd 6251 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6252
6253 /* Rx Errors */
7ca647bd 6254 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6255 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6256 netdev->stats.rx_length_errors = hwstats->rlec;
6257 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6258 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6259}
6260
6261/**
d034acf1 6262 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6263 * @adapter: pointer to the device adapter structure
9a799d71 6264 **/
d034acf1 6265static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6266{
cf8280ee 6267 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6268 int i;
cf8280ee 6269
d034acf1
AD		 6270 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6271 return;
6272
6273 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6274
d034acf1 6275 /* if interface is down do nothing */
fe49f04a 6276 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6277 return;
6278
6279 /* do nothing if we are not using signature filters */
6280 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6281 return;
6282
6283 adapter->fdir_overflow++;
6284
93c52dd0
AD		 6285 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6286 for (i = 0; i < adapter->num_tx_queues; i++)
6287 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6288 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6289 /* re-enable flow director interrupts */
6290 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6291 } else {
6292 e_err(probe, "failed to finish FDIR re-initialization, "
6293 "ignored adding FDIR ATR filters\n");
6294 }
93c52dd0
AD		 6295}
6296
6297/**
6298 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6299 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6300 *
6301 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6302 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6303 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6304 * determine if a hang has occurred.
93c52dd0
AD		 6305 */
6306static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6307{
cf8280ee 6308 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6309 u64 eics = 0;
6310 int i;
cf8280ee 6311
09f40aed 6312 /* If we're down, removing or resetting, just bail */
93c52dd0 6313 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6314 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6315 test_bit(__IXGBE_RESETTING, &adapter->state))
6316 return;
22d5a71b 6317
93c52dd0
AD		 6318 /* Force detection of hung controller */
6319 if (netif_carrier_ok(adapter->netdev)) {
6320 for (i = 0; i < adapter->num_tx_queues; i++)
6321 set_check_for_tx_hang(adapter->tx_ring[i]);
6322 }
22d5a71b 6323
fe49f04a
AD		 6324 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6325 /*
6326 * for legacy and MSI interrupts don't set any bits
6327 * that are enabled for EIAM, because this operation
6328 * would set *both* EIMS and EICS for any bit in EIAM
6329 */
6330 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6331 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6332 } else {
6333 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6334 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6335 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6336 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6337 eics |= ((u64)1 << i);
6338 }
cf8280ee 6339 }
9a799d71 6340
93c52dd0 6341 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6342 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6343}
6344
e8e26350 6345/**
93c52dd0 6346 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6347 * @adapter: pointer to the device adapter structure
6348 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6349 **/
93c52dd0 6350static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6351{
e8e26350 6352 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6353 u32 link_speed = adapter->link_speed;
6354 bool link_up = adapter->link_up;
041441d0 6355 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6356
93c52dd0
AD		 6357 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6358 return;
6359
6360 if (hw->mac.ops.check_link) {
6361 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6362 } else {
93c52dd0
AD		 6363 /* always assume link is up, if no check link function */
6364 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6365 link_up = true;
c4cf55e5 6366 }
041441d0
AD		 6367
6368 if (adapter->ixgbe_ieee_pfc)
6369 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6370
3ebe8fde 6371 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6372 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6373 ixgbe_set_rx_drop_en(adapter);
6374 }
93c52dd0
AD		 6375
6376 if (link_up ||
6377 time_after(jiffies, (adapter->link_check_timeout +
6378 IXGBE_TRY_LINK_TIMEOUT))) {
6379 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6380 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6381 IXGBE_WRITE_FLUSH(hw);
6382 }
6383
6384 adapter->link_up = link_up;
6385 adapter->link_speed = link_speed;
e8e26350
PW		 6386}
6387
107d3018
AD		 6388static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6389{
6390#ifdef CONFIG_IXGBE_DCB
6391 struct net_device *netdev = adapter->netdev;
6392 struct dcb_app app = {
6393 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6394 .protocol = 0,
6395 };
6396 u8 up = 0;
6397
6398 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6399 up = dcb_ieee_getapp_mask(netdev, &app);
6400
6401 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6402#endif
6403}
6404
e8e26350 6405/**
93c52dd0
AD		 6406 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6407 * print link up message
49ce9c2c 6408 * @adapter: pointer to the device adapter structure
e8e26350 6409 **/
93c52dd0 6410static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6411{
93c52dd0 6412 struct net_device *netdev = adapter->netdev;
e8e26350 6413 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6414 struct net_device *upper;
6415 struct list_head *iter;
93c52dd0 6416 u32 link_speed = adapter->link_speed;
454adb00 6417 const char *speed_str;
93c52dd0 6418 bool flow_rx, flow_tx;
e8e26350 6419
93c52dd0
AD		 6420 /* only continue if link was previously down */
6421 if (netif_carrier_ok(netdev))
a985b6c3 6422 return;
63d6e1d8 6423
93c52dd0 6424 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6425
93c52dd0
AD		 6426 switch (hw->mac.type) {
6427 case ixgbe_mac_82598EB: {
6428 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6429 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6430 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6431 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6432 }
6433 break;
6434 case ixgbe_mac_X540:
9a75a1ac
DS		 6435 case ixgbe_mac_X550:
6436 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6437 case ixgbe_mac_82599EB: {
6438 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6439 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6440 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6441 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6442 }
6443 break;
6444 default:
6445 flow_tx = false;
6446 flow_rx = false;
6447 break;
e8e26350 6448 }
3a6a4eda 6449
6cb562d6
JK		 6450 adapter->last_rx_ptp_check = jiffies;
6451
8fecf67c 6452 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6453 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6454
454adb00
MR		 6455 switch (link_speed) {
6456 case IXGBE_LINK_SPEED_10GB_FULL:
6457 speed_str = "10 Gbps";
6458 break;
6459 case IXGBE_LINK_SPEED_2_5GB_FULL:
6460 speed_str = "2.5 Gbps";
6461 break;
6462 case IXGBE_LINK_SPEED_1GB_FULL:
6463 speed_str = "1 Gbps";
6464 break;
6465 case IXGBE_LINK_SPEED_100_FULL:
6466 speed_str = "100 Mbps";
6467 break;
6468 default:
6469 speed_str = "unknown speed";
6470 break;
6471 }
6472 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6473 ((flow_rx && flow_tx) ? "RX/TX" :
6474 (flow_rx ? "RX" :
6475 (flow_tx ? "TX" : "None"))));
e8e26350 6476
93c52dd0 6477 netif_carrier_on(netdev);
93c52dd0 6478 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6479
cdc04dcc
ET		 6480 /* enable transmits */
6481 netif_tx_wake_all_queues(adapter->netdev);
6482
6483 /* enable any upper devices */
6484 rtnl_lock();
6485 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6486 if (netif_is_macvlan(upper)) {
6487 struct macvlan_dev *vlan = netdev_priv(upper);
6488
6489 if (vlan->fwd_priv)
6490 netif_tx_wake_all_queues(upper);
6491 }
6492 }
6493 rtnl_unlock();
6494
107d3018
AD		 6495 /* update the default user priority for VFs */
6496 ixgbe_update_default_up(adapter);
6497
befa2af7
AD		 6498 /* ping all the active vfs to let them know link has changed */
6499 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6500}
6501
c4cf55e5 6502/**
93c52dd0
AD		 6503 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6504 * print link down message
49ce9c2c 6505 * @adapter: pointer to the adapter structure
c4cf55e5 6506 **/
581330ba 6507static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6508{
cf8280ee 6509 struct net_device *netdev = adapter->netdev;
c4cf55e5 6510 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6511
93c52dd0
AD		 6512 adapter->link_up = false;
6513 adapter->link_speed = 0;
cf8280ee 6514
93c52dd0
AD		 6515 /* only continue if link was up previously */
6516 if (!netif_carrier_ok(netdev))
6517 return;
264857b8 6518
93c52dd0
AD		 6519 /* poll for SFP+ cable when link is down */
6520 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6521 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6522
8fecf67c 6523 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6524 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6525
93c52dd0
AD		 6526 e_info(drv, "NIC Link is Down\n");
6527 netif_carrier_off(netdev);
befa2af7
AD		 6528
6529 /* ping all the active vfs to let them know link has changed */
6530 ixgbe_ping_all_vfs(adapter);
93c52dd0 6531}
e8e26350 6532
07923c17
ET		 6533static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6534{
6535 int i;
6536
6537 for (i = 0; i < adapter->num_tx_queues; i++) {
6538 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6539
6540 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6541 return true;
6542 }
6543
6544 return false;
6545}
6546
6547static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6548{
6549 struct ixgbe_hw *hw = &adapter->hw;
6550 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6551 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6552
6553 int i, j;
6554
6555 if (!adapter->num_vfs)
6556 return false;
6557
9a75a1ac
DS		 6558 /* resetting the PF is only needed for MAC before X550 */
6559 if (hw->mac.type >= ixgbe_mac_X550)
6560 return false;
6561
07923c17
ET		 6562 for (i = 0; i < adapter->num_vfs; i++) {
6563 for (j = 0; j < q_per_pool; j++) {
6564 u32 h, t;
6565
6566 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6567 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6568
6569 if (h != t)
6570 return true;
6571 }
6572 }
6573
6574 return false;
6575}
6576
93c52dd0
AD		 6577/**
6578 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6579 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6580 **/
6581static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6582{
93c52dd0 6583 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6584 if (ixgbe_ring_tx_pending(adapter) ||
6585 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6586 /* We've lost link, so the controller stops DMA,
6587 * but we've got queued Tx work that's never going
6588 * to get done, so reset controller to flush Tx.
6589 * (Do the reset outside of interrupt context).
6590 */
12ff3f3b 6591 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6592 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6593 }
c4cf55e5 6594 }
c4cf55e5
PWJ		 6595}
6596
9079e416
ET		 6597#ifdef CONFIG_PCI_IOV
6598static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6599 struct pci_dev *vfdev)
6600{
6601 if (!pci_wait_for_pending_transaction(vfdev))
6602 e_dev_warn("Issuing VFLR with pending transactions\n");
6603
6604 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6605 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6606
6607 msleep(100);
6608}
6609
6610static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6611{
6612 struct ixgbe_hw *hw = &adapter->hw;
6613 struct pci_dev *pdev = adapter->pdev;
6614 struct pci_dev *vfdev;
6615 u32 gpc;
6616 int pos;
6617 unsigned short vf_id;
6618
6619 if (!(netif_carrier_ok(adapter->netdev)))
6620 return;
6621
6622 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6623 if (gpc) /* If incrementing then no need for the check below */
6624 return;
6625 /* Check to see if a bad DMA write target from an errant or
6626 * malicious VF has caused a PCIe error. If so then we can
6627 * issue a VFLR to the offending VF(s) and then resume without
6628 * requesting a full slot reset.
6629 */
6630
6631 if (!pdev)
6632 return;
6633
6634 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6635 if (!pos)
6636 return;
6637
6638 /* get the device ID for the VF */
6639 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6640
6641 /* check status reg for all VFs owned by this PF */
6642 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6643 while (vfdev) {
6644 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6645 u16 status_reg;
6646
6647 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6648 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6649 /* issue VFLR */
6650 ixgbe_issue_vf_flr(adapter, vfdev);
6651 }
6652
6653 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6654 }
6655}
6656
a985b6c3
GR		 6657static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6658{
6659 u32 ssvpc;
6660
0584d999
GR		 6661 /* Do not perform spoof check for 82598 or if not in IOV mode */
6662 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6663 adapter->num_vfs == 0)
a985b6c3
GR		 6664 return;
6665
6666 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6667
6668 /*
6669 * ssvpc register is cleared on read, if zero then no
6670 * spoofed packets in the last interval.
6671 */
6672 if (!ssvpc)
6673 return;
6674
d6ea0754 6675 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6676}
9079e416
ET		 6677#else
6678static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6679{
6680}
6681
6682static void
6683ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6684{
6685}
6686#endif /* CONFIG_PCI_IOV */
6687
a985b6c3 6688
93c52dd0
AD		 6689/**
6690 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6691 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6692 **/
6693static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6694{
09f40aed 6695 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6696 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6697 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6698 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6699 return;
6700
6701 ixgbe_watchdog_update_link(adapter);
6702
6703 if (adapter->link_up)
6704 ixgbe_watchdog_link_is_up(adapter);
6705 else
6706 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6707
9079e416 6708 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6709 ixgbe_spoof_check(adapter);
9a799d71 6710 ixgbe_update_stats(adapter);
93c52dd0
AD		 6711
6712 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6713}
10eec955 6714
cf8280ee 6715/**
7086400d 6716 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6717 * @adapter: the ixgbe adapter structure
cf8280ee 6718 **/
7086400d 6719static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6720{
cf8280ee 6721 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6722 s32 err;
cf8280ee 6723
7086400d
AD		 6724 /* not searching for SFP so there is nothing to do here */
6725 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6726 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6727 return;
10eec955 6728
58e7cd24
MR		 6729 if (adapter->sfp_poll_time &&
6730 time_after(adapter->sfp_poll_time, jiffies))
6731 return; /* If not yet time to poll for SFP */
6732
7086400d
AD		 6733 /* someone else is in init, wait until next service event */
6734 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6735 return;
cf8280ee 6736
58e7cd24
MR		 6737 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6738
7086400d
AD		 6739 err = hw->phy.ops.identify_sfp(hw);
6740 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6741 goto sfp_out;
264857b8 6742
7086400d
AD		 6743 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6744 /* If no cable is present, then we need to reset
6745 * the next time we find a good cable. */
6746 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6747 }
9a799d71 6748
7086400d
AD		 6749 /* exit on error */
6750 if (err)
6751 goto sfp_out;
e8e26350 6752
7086400d
AD		 6753 /* exit if reset not needed */
6754 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6755 goto sfp_out;
9a799d71 6756
7086400d 6757 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6758
7086400d
AD		 6759 /*
6760 * A module may be identified correctly, but the EEPROM may not have
6761 * support for that module. setup_sfp() will fail in that case, so
6762 * we should not allow that module to load.
6763 */
6764 if (hw->mac.type == ixgbe_mac_82598EB)
6765 err = hw->phy.ops.reset(hw);
6766 else
6767 err = hw->mac.ops.setup_sfp(hw);
6768
6769 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6770 goto sfp_out;
6771
6772 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6773 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6774
6775sfp_out:
6776 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6777
6778 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6779 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6780 e_dev_err("failed to initialize because an unsupported "
6781 "SFP+ module type was detected.\n");
6782 e_dev_err("Reload the driver after installing a "
6783 "supported module.\n");
6784 unregister_netdev(adapter->netdev);
bc59fcda 6785 }
7086400d 6786}
bc59fcda 6787
7086400d
AD		 6788/**
6789 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6790 * @adapter: the ixgbe adapter structure
7086400d
AD		 6791 **/
6792static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6793{
6794 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6795 u32 speed;
6796 bool autoneg = false;
7086400d
AD		 6797
6798 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6799 return;
6800
6801 /* someone else is in init, wait until next service event */
6802 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6803 return;
6804
6805 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6806
3d292265 6807 speed = hw->phy.autoneg_advertised;
ed33ff66 6808 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6809 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6810
6811 /* setup the highest link when no autoneg */
6812 if (!autoneg) {
6813 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6814 speed = IXGBE_LINK_SPEED_10GB_FULL;
6815 }
6816 }
6817
7086400d 6818 if (hw->mac.ops.setup_link)
fd0326f2 6819 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6820
6821 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6822 adapter->link_check_timeout = jiffies;
6823 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6824}
6825
6826/**
6827 * ixgbe_service_timer - Timer Call-back
6828 * @data: pointer to adapter cast into an unsigned long
6829 **/
6830static void ixgbe_service_timer(unsigned long data)
6831{
6832 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6833 unsigned long next_event_offset;
6834
6bb78cfb
AD		 6835 /* poll faster when waiting for link */
6836 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6837 next_event_offset = HZ / 10;
6838 else
6839 next_event_offset = HZ * 2;
83c61fa9 6840
7086400d
AD		 6841 /* Reset the timer */
6842 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6843
9079e416 6844 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6845}
6846
597f22d6
DS		 6847static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6848{
6849 struct ixgbe_hw *hw = &adapter->hw;
6850 u32 status;
6851
6852 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6853 return;
6854
6855 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6856
6857 if (!hw->phy.ops.handle_lasi)
6858 return;
6859
6860 status = hw->phy.ops.handle_lasi(&adapter->hw);
6861 if (status != IXGBE_ERR_OVERTEMP)
6862 return;
6863
6864 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6865}
6866
c83c6cbd
AD		 6867static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6868{
6869 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6870 return;
6871
6872 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6873
09f40aed 6874 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6875 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6876 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6877 test_bit(__IXGBE_RESETTING, &adapter->state))
6878 return;
6879
6880 ixgbe_dump(adapter);
6881 netdev_err(adapter->netdev, "Reset adapter\n");
6882 adapter->tx_timeout_count++;
6883
8f4c5c9f 6884 rtnl_lock();
c83c6cbd 6885 ixgbe_reinit_locked(adapter);
8f4c5c9f 6886 rtnl_unlock();
c83c6cbd
AD		 6887}
6888
7086400d
AD		 6889/**
6890 * ixgbe_service_task - manages and runs subtasks
6891 * @work: pointer to work_struct containing our data
6892 **/
6893static void ixgbe_service_task(struct work_struct *work)
6894{
6895 struct ixgbe_adapter *adapter = container_of(work,
6896 struct ixgbe_adapter,
6897 service_task);
b0483c8f
MR		 6898 if (ixgbe_removed(adapter->hw.hw_addr)) {
6899 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6900 rtnl_lock();
6901 ixgbe_down(adapter);
6902 rtnl_unlock();
6903 }
6904 ixgbe_service_event_complete(adapter);
6905 return;
6906 }
67359c3c
MR		 6907#ifdef CONFIG_IXGBE_VXLAN
6908 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6909 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6910 vxlan_get_rx_port(adapter->netdev);
6911 }
6912#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 6913 ixgbe_reset_subtask(adapter);
597f22d6 6914 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 6915 ixgbe_sfp_detection_subtask(adapter);
6916 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6917 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6918 ixgbe_watchdog_subtask(adapter);
d034acf1 6919 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6920 ixgbe_check_hang_subtask(adapter);
891dc082 6921
8fecf67c 6922 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6923 ixgbe_ptp_overflow_check(adapter);
6924 ixgbe_ptp_rx_hang(adapter);
6925 }
7086400d
AD		 6926
6927 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6928}
6929
fd0db0ed
AD		 6930static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6931 struct ixgbe_tx_buffer *first,
244e27ad 6932 u8 *hdr_len)
897ab156 6933{
fd0db0ed 6934 struct sk_buff *skb = first->skb;
897ab156
AD		 6935 u32 vlan_macip_lens, type_tucmd;
6936 u32 mss_l4len_idx, l4len;
2049e1f6 6937 int err;
9a799d71 6938
8f4fbb9b
AD		 6939 if (skb->ip_summed != CHECKSUM_PARTIAL)
6940 return 0;
6941
897ab156
AD		 6942 if (!skb_is_gso(skb))
6943 return 0;
9a799d71 6944
2049e1f6
FR		 6945 err = skb_cow_head(skb, 0);
6946 if (err < 0)
6947 return err;
9a799d71 6948
897ab156
AD		 6949 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6950 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6951
a1108ffd 6952 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6953 struct iphdr *iph = ip_hdr(skb);
6954 iph->tot_len = 0;
6955 iph->check = 0;
6956 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6957 iph->daddr, 0,
6958 IPPROTO_TCP,
6959 0);
6960 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6961 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6962 IXGBE_TX_FLAGS_CSUM |
6963 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6964 } else if (skb_is_gso_v6(skb)) {
6965 ipv6_hdr(skb)->payload_len = 0;
6966 tcp_hdr(skb)->check =
6967 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6968 &ipv6_hdr(skb)->daddr,
6969 0, IPPROTO_TCP, 0);
244e27ad
AD		 6970 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6971 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6972 }
6973
091a6246 6974 /* compute header lengths */
897ab156
AD		 6975 l4len = tcp_hdrlen(skb);
6976 *hdr_len = skb_transport_offset(skb) + l4len;
6977
091a6246
AD		 6978 /* update gso size and bytecount with header size */
6979 first->gso_segs = skb_shinfo(skb)->gso_segs;
6980 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6981
c44f5f51 6982 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6983 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6984 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6985
6986 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6987 vlan_macip_lens = skb_network_header_len(skb);
6988 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6989 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6990
6991 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6992 mss_l4len_idx);
897ab156
AD		 6993
6994 return 1;
6995}
6996
244e27ad
AD		 6997static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6998 struct ixgbe_tx_buffer *first)
7ca647bd 6999{
fd0db0ed 7000 struct sk_buff *skb = first->skb;
897ab156
AD		 7001 u32 vlan_macip_lens = 0;
7002 u32 mss_l4len_idx = 0;
7003 u32 type_tucmd = 0;
7ca647bd 7004
897ab156 7005 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 7006 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7007 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7008 return;
f467bc06
MR		 7009 vlan_macip_lens = skb_network_offset(skb) <<
7010 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 7011 } else {
7012 u8 l4_hdr = 0;
f467bc06
MR		 7013 union {
7014 struct iphdr *ipv4;
7015 struct ipv6hdr *ipv6;
7016 u8 *raw;
7017 } network_hdr;
7018 union {
7019 struct tcphdr *tcphdr;
7020 u8 *raw;
7021 } transport_hdr;
7022
7023 if (skb->encapsulation) {
7024 network_hdr.raw = skb_inner_network_header(skb);
7025 transport_hdr.raw = skb_inner_transport_header(skb);
7026 vlan_macip_lens = skb_inner_network_offset(skb) <<
7027 IXGBE_ADVTXD_MACLEN_SHIFT;
7028 } else {
7029 network_hdr.raw = skb_network_header(skb);
7030 transport_hdr.raw = skb_transport_header(skb);
7031 vlan_macip_lens = skb_network_offset(skb) <<
7032 IXGBE_ADVTXD_MACLEN_SHIFT;
7033 }
7034
7035 /* use first 4 bits to determine IP version */
7036 switch (network_hdr.ipv4->version) {
7037 case IPVERSION:
7038 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7039 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7040 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7041 break;
f467bc06
MR		 7042 case 6:
7043 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7044 l4_hdr = network_hdr.ipv6->nexthdr;
897ab156
AD		 7045 break;
7046 default:
7047 if (unlikely(net_ratelimit())) {
7048 dev_warn(tx_ring->dev,
f467bc06
MR		 7049 "partial checksum but version=%d\n",
7050 network_hdr.ipv4->version);
897ab156 7051 }
7ca647bd 7052 }
897ab156
AD		 7053
7054 switch (l4_hdr) {
7ca647bd 7055 case IPPROTO_TCP:
897ab156 7056 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7057 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7058 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7059 break;
7060 case IPPROTO_SCTP:
897ab156
AD		 7061 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7062 mss_l4len_idx = sizeof(struct sctphdr) <<
7063 IXGBE_ADVTXD_L4LEN_SHIFT;
7064 break;
7065 case IPPROTO_UDP:
7066 mss_l4len_idx = sizeof(struct udphdr) <<
7067 IXGBE_ADVTXD_L4LEN_SHIFT;
7068 break;
7069 default:
7070 if (unlikely(net_ratelimit())) {
7071 dev_warn(tx_ring->dev,
7072 "partial checksum but l4 proto=%x!\n",
244e27ad 7073 l4_hdr);
897ab156 7074 }
7ca647bd
JP		 7075 break;
7076 }
244e27ad
AD		 7077
7078 /* update TX checksum flag */
7079 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7080 }
7081
244e27ad 7082 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7083 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7084
897ab156
AD		 7085 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7086 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7087}
7088
472148c3
AD		 7089#define IXGBE_SET_FLAG(_input, _flag, _result) \
7090 ((_flag <= _result) ? \
7091 ((u32)(_input & _flag) * (_result / _flag)) : \
7092 ((u32)(_input & _flag) / (_flag / _result)))
7093
7094static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7095{
d3d00239 7096 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7097 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7098 IXGBE_ADVTXD_DCMD_DEXT |
7099 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7100
d3d00239 7101 /* set HW vlan bit if vlan is present */
472148c3
AD		 7102 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7103 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7104
d3d00239 7105 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7106 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7107 IXGBE_ADVTXD_DCMD_TSE);
7108
7109 /* set timestamp bit if present */
7110 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7111 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7112
62748b7b 7113 /* insert frame checksum */
472148c3 7114 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7115
d3d00239
AD		 7116 return cmd_type;
7117}
9a799d71 7118
729739b7
AD		 7119static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7120 u32 tx_flags, unsigned int paylen)
d3d00239 7121{
472148c3 7122 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7123
d3d00239 7124 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7125 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7126 IXGBE_TX_FLAGS_CSUM,
7127 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7128
93f5b3c1 7129 /* enble IPv4 checksum for TSO */
472148c3
AD		 7130 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7131 IXGBE_TX_FLAGS_IPV4,
7132 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7133
7f9643fd
AD		 7134 /*
7135 * Check Context must be set if Tx switch is enabled, which it
7136 * always is for case where virtual functions are running
7137 */
472148c3
AD		 7138 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7139 IXGBE_TX_FLAGS_CC,
7140 IXGBE_ADVTXD_CC);
7f9643fd 7141
472148c3 7142 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7143}
44df32c5 7144
2367a173
DB		 7145static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7146{
7147 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7148
7149 /* Herbert's original patch had:
7150 * smp_mb__after_netif_stop_queue();
7151 * but since that doesn't exist yet, just open code it.
7152 */
7153 smp_mb();
7154
7155 /* We need to check again in a case another CPU has just
7156 * made room available.
7157 */
7158 if (likely(ixgbe_desc_unused(tx_ring) < size))
7159 return -EBUSY;
7160
7161 /* A reprieve! - use start_queue because it doesn't call schedule */
7162 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7163 ++tx_ring->tx_stats.restart_queue;
7164 return 0;
7165}
7166
7167static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7168{
7169 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7170 return 0;
7171
7172 return __ixgbe_maybe_stop_tx(tx_ring, size);
7173}
7174
d3d00239
AD		 7175#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7176 IXGBE_TXD_CMD_RS)
7177
7178static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7179 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7180 const u8 hdr_len)
7181{
fd0db0ed 7182 struct sk_buff *skb = first->skb;
729739b7 7183 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7184 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7185 struct skb_frag_struct *frag;
7186 dma_addr_t dma;
7187 unsigned int data_len, size;
244e27ad 7188 u32 tx_flags = first->tx_flags;
472148c3 7189 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7190 u16 i = tx_ring->next_to_use;
d3d00239 7191
729739b7
AD		 7192 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7193
ec718254
AD		 7194 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7195
7196 size = skb_headlen(skb);
7197 data_len = skb->data_len;
729739b7 7198
d3d00239
AD		 7199#ifdef IXGBE_FCOE
7200 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7201 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7202 size -= sizeof(struct fcoe_crc_eof) - data_len;
7203 data_len = 0;
729739b7
AD		 7204 } else {
7205 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7206 }
7207 }
44df32c5 7208
d3d00239 7209#endif
729739b7 7210 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7211
ec718254 7212 tx_buffer = first;
9a799d71 7213
ec718254
AD		 7214 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7215 if (dma_mapping_error(tx_ring->dev, dma))
7216 goto dma_error;
7217
7218 /* record length, and DMA address */
7219 dma_unmap_len_set(tx_buffer, len, size);
7220 dma_unmap_addr_set(tx_buffer, dma, dma);
7221
7222 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7223
729739b7 7224 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7225 tx_desc->read.cmd_type_len =
472148c3 7226 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7227
d3d00239 7228 i++;
729739b7 7229 tx_desc++;
d3d00239 7230 if (i == tx_ring->count) {
e4f74028 7231 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7232 i = 0;
7233 }
ec718254 7234 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7235
7236 dma += IXGBE_MAX_DATA_PER_TXD;
7237 size -= IXGBE_MAX_DATA_PER_TXD;
7238
7239 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7240 }
e5a43549 7241
729739b7
AD		 7242 if (likely(!data_len))
7243 break;
9a799d71 7244
472148c3 7245 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7246
729739b7
AD		 7247 i++;
7248 tx_desc++;
7249 if (i == tx_ring->count) {
7250 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7251 i = 0;
7252 }
ec718254 7253 tx_desc->read.olinfo_status = 0;
9a799d71 7254
d3d00239 7255#ifdef IXGBE_FCOE
9e903e08 7256 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7257#else
9e903e08 7258 size = skb_frag_size(frag);
d3d00239
AD		 7259#endif
7260 data_len -= size;
9a799d71 7261
729739b7
AD		 7262 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7263 DMA_TO_DEVICE);
9a799d71 7264
729739b7 7265 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7266 }
9a799d71 7267
729739b7 7268 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7269 cmd_type |= size | IXGBE_TXD_CMD;
7270 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7271
091a6246 7272 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7273
d3d00239
AD		 7274 /* set the timestamp */
7275 first->time_stamp = jiffies;
9a799d71
AK		 7276
7277 /*
729739b7
AD		 7278 * Force memory writes to complete before letting h/w know there
7279 * are new descriptors to fetch. (Only applicable for weak-ordered
7280 * memory model archs, such as IA-64).
7281 *
7282 * We also need this memory barrier to make certain all of the
7283 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7284 */
7285 wmb();
7286
d3d00239
AD		 7287 /* set next_to_watch value indicating a packet is present */
7288 first->next_to_watch = tx_desc;
7289
729739b7
AD		 7290 i++;
7291 if (i == tx_ring->count)
7292 i = 0;
7293
7294 tx_ring->next_to_use = i;
7295
2367a173
DB		 7296 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7297
7298 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7299 writel(i, tx_ring->tail);
7300
7301 /* we need this if more than one processor can write to our tail
7302 * at a time, it synchronizes IO on IA64/Altix systems
7303 */
7304 mmiowb();
9c938cdd 7305 }
2367a173 7306
d3d00239
AD		 7307 return;
7308dma_error:
729739b7 7309 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7310
7311 /* clear dma mappings for failed tx_buffer_info map */
7312 for (;;) {
729739b7
AD		 7313 tx_buffer = &tx_ring->tx_buffer_info[i];
7314 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7315 if (tx_buffer == first)
d3d00239
AD		 7316 break;
7317 if (i == 0)
7318 i = tx_ring->count;
7319 i--;
7320 }
7321
d3d00239 7322 tx_ring->next_to_use = i;
9a799d71
AK		 7323}
7324
fd0db0ed 7325static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7326 struct ixgbe_tx_buffer *first)
69830529
AD		 7327{
7328 struct ixgbe_q_vector *q_vector = ring->q_vector;
7329 union ixgbe_atr_hash_dword input = { .dword = 0 };
7330 union ixgbe_atr_hash_dword common = { .dword = 0 };
7331 union {
7332 unsigned char *network;
7333 struct iphdr *ipv4;
7334 struct ipv6hdr *ipv6;
7335 } hdr;
ee9e0f0b 7336 struct tcphdr *th;
67359c3c
MR		 7337 struct sk_buff *skb;
7338#ifdef CONFIG_IXGBE_VXLAN
7339 u8 encap = false;
7340#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7341 __be16 vlan_id;
c4cf55e5 7342
69830529
AD		 7343 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7344 if (!q_vector)
7345 return;
7346
7347 /* do nothing if sampling is disabled */
7348 if (!ring->atr_sample_rate)
d3ead241 7349 return;
c4cf55e5 7350
69830529 7351 ring->atr_count++;
c4cf55e5 7352
69830529 7353 /* snag network header to get L4 type and address */
67359c3c
MR		 7354 skb = first->skb;
7355 hdr.network = skb_network_header(skb);
7356 if (skb->encapsulation) {
7357#ifdef CONFIG_IXGBE_VXLAN
7358 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7359
67359c3c
MR		 7360 if (!adapter->vxlan_port)
7361 return;
7362 if (first->protocol != htons(ETH_P_IP) ||
7363 hdr.ipv4->version != IPVERSION ||
7364 hdr.ipv4->protocol != IPPROTO_UDP) {
7365 return;
7366 }
7367 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7368 return;
7369 encap = true;
7370 hdr.network = skb_inner_network_header(skb);
7371 th = inner_tcp_hdr(skb);
7372#else
69830529 7373 return;
67359c3c
MR		 7374#endif /* CONFIG_IXGBE_VXLAN */
7375 } else {
7376 /* Currently only IPv4/IPv6 with TCP is supported */
7377 if ((first->protocol != htons(ETH_P_IPV6) ||
7378 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7379 (first->protocol != htons(ETH_P_IP) ||
7380 hdr.ipv4->protocol != IPPROTO_TCP))
7381 return;
7382 th = tcp_hdr(skb);
7383 }
c4cf55e5 7384
66f32a8b
AD		 7385 /* skip this packet since it is invalid or the socket is closing */
7386 if (!th || th->fin)
69830529
AD		 7387 return;
7388
7389 /* sample on all syn packets or once every atr sample count */
7390 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7391 return;
7392
7393 /* reset sample count */
7394 ring->atr_count = 0;
7395
244e27ad 7396 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7397
7398 /*
7399 * src and dst are inverted, think how the receiver sees them
7400 *
7401 * The input is broken into two sections, a non-compressed section
7402 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7403 * is XORed together and stored in the compressed dword.
7404 */
7405 input.formatted.vlan_id = vlan_id;
7406
7407 /*
7408 * since src port and flex bytes occupy the same word XOR them together
7409 * and write the value to source port portion of compressed dword
7410 */
244e27ad 7411 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7412 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7413 else
244e27ad 7414 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7415 common.port.dst ^= th->source;
7416
a1108ffd 7417 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7418 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7419 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7420 } else {
7421 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7422 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7423 hdr.ipv6->saddr.s6_addr32[1] ^
7424 hdr.ipv6->saddr.s6_addr32[2] ^
7425 hdr.ipv6->saddr.s6_addr32[3] ^
7426 hdr.ipv6->daddr.s6_addr32[0] ^
7427 hdr.ipv6->daddr.s6_addr32[1] ^
7428 hdr.ipv6->daddr.s6_addr32[2] ^
7429 hdr.ipv6->daddr.s6_addr32[3];
7430 }
c4cf55e5 7431
67359c3c
MR		 7432#ifdef CONFIG_IXGBE_VXLAN
7433 if (encap)
7434 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7435#endif /* CONFIG_IXGBE_VXLAN */
7436
c4cf55e5 7437 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7438 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7439 input, common, ring->queue_index);
c4cf55e5
PWJ		 7440}
7441
f663dd9a 7442static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7443 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7444{
f663dd9a
JW		 7445 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7446#ifdef IXGBE_FCOE
97488bd1
AD		 7447 struct ixgbe_adapter *adapter;
7448 struct ixgbe_ring_feature *f;
7449 int txq;
f663dd9a
JW		 7450#endif
7451
7452 if (fwd_adapter)
7453 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7454
7455#ifdef IXGBE_FCOE
5e09a105 7456
97488bd1
AD		 7457 /*
7458 * only execute the code below if protocol is FCoE
7459 * or FIP and we have FCoE enabled on the adapter
7460 */
7461 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7462 case htons(ETH_P_FCOE):
7463 case htons(ETH_P_FIP):
97488bd1 7464 adapter = netdev_priv(dev);
c087663e 7465
97488bd1
AD		 7466 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7467 break;
7468 default:
99932d4f 7469 return fallback(dev, skb);
97488bd1 7470 }
c087663e 7471
97488bd1 7472 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7473
97488bd1
AD		 7474 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7475 smp_processor_id();
56075a98 7476
97488bd1
AD		 7477 while (txq >= f->indices)
7478 txq -= f->indices;
c4cf55e5 7479
97488bd1 7480 return txq + f->offset;
f663dd9a 7481#else
99932d4f 7482 return fallback(dev, skb);
f663dd9a 7483#endif
09a3b1f8
SH		 7484}
7485
fc77dc3c 7486netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7487 struct ixgbe_adapter *adapter,
7488 struct ixgbe_ring *tx_ring)
9a799d71 7489{
d3d00239 7490 struct ixgbe_tx_buffer *first;
5f715823 7491 int tso;
d3d00239 7492 u32 tx_flags = 0;
a535c30e 7493 unsigned short f;
a535c30e 7494 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7495 __be16 protocol = skb->protocol;
63544e9c 7496 u8 hdr_len = 0;
5e09a105 7497
a535c30e
AD		 7498 /*
7499 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7500 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7501 * + 2 desc gap to keep tail from touching head,
7502 * + 1 desc for context descriptor,
7503 * otherwise try next time
7504 */
a535c30e
AD		 7505 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7506 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7507
a535c30e
AD		 7508 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7509 tx_ring->tx_stats.tx_busy++;
7510 return NETDEV_TX_BUSY;
7511 }
7512
fd0db0ed
AD		 7513 /* record the location of the first descriptor for this packet */
7514 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7515 first->skb = skb;
091a6246
AD		 7516 first->bytecount = skb->len;
7517 first->gso_segs = 1;
fd0db0ed 7518
66f32a8b 7519 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7520 if (skb_vlan_tag_present(skb)) {
7521 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7522 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7523 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7524 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7525 struct vlan_hdr *vhdr, _vhdr;
7526 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7527 if (!vhdr)
7528 goto out_drop;
7529
9e0c5648
AD		 7530 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7531 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7532 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7533 }
0213668f 7534 protocol = vlan_get_protocol(skb);
66f32a8b 7535
d5234933
MR		 7536 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7537 adapter->ptp_clock &&
7538 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7539 &adapter->state)) {
3a6a4eda
JK		 7540 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7541 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7542
7543 /* schedule check for Tx timestamp */
7544 adapter->ptp_tx_skb = skb_get(skb);
7545 adapter->ptp_tx_start = jiffies;
7546 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7547 }
3a6a4eda 7548
ff29a86e
JK		 7549 skb_tx_timestamp(skb);
7550
9e0c5648
AD		 7551#ifdef CONFIG_PCI_IOV
7552 /*
7553 * Use the l2switch_enable flag - would be false if the DMA
7554 * Tx switch had been disabled.
7555 */
7556 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7557 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7558
7559#endif
32701dc2 7560 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7561 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7562 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7563 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7564 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7565 tx_flags |= (skb->priority & 0x7) <<
7566 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7567 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7568 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7569
7570 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7571 goto out_drop;
7572 vhdr = (struct vlan_ethhdr *)skb->data;
7573 vhdr->h_vlan_TCI = htons(tx_flags >>
7574 IXGBE_TX_FLAGS_VLAN_SHIFT);
7575 } else {
7576 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7577 }
9a799d71 7578 }
eacd73f7 7579
244e27ad
AD		 7580 /* record initial flags and protocol */
7581 first->tx_flags = tx_flags;
7582 first->protocol = protocol;
7583
eacd73f7 7584#ifdef IXGBE_FCOE
66f32a8b 7585 /* setup tx offload for FCoE */
a1108ffd 7586 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7587 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7588 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7589 if (tso < 0)
7590 goto out_drop;
9a799d71 7591
66f32a8b 7592 goto xmit_fcoe;
eacd73f7 7593 }
9a799d71 7594
66f32a8b 7595#endif /* IXGBE_FCOE */
244e27ad 7596 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7597 if (tso < 0)
897ab156 7598 goto out_drop;
244e27ad
AD		 7599 else if (!tso)
7600 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7601
7602 /* add the ATR filter if ATR is on */
7603 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7604 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7605
7606#ifdef IXGBE_FCOE
7607xmit_fcoe:
7608#endif /* IXGBE_FCOE */
244e27ad 7609 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7610
9a799d71 7611 return NETDEV_TX_OK;
897ab156
AD		 7612
7613out_drop:
fd0db0ed
AD		 7614 dev_kfree_skb_any(first->skb);
7615 first->skb = NULL;
7616
897ab156 7617 return NETDEV_TX_OK;
9a799d71
AK		 7618}
7619
2a47fa45
JF		 7620static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7621 struct net_device *netdev,
7622 struct ixgbe_ring *ring)
84418e3b
AD		 7623{
7624 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7625 struct ixgbe_ring *tx_ring;
7626
a50c29dd
AD		 7627 /*
7628 * The minimum packet size for olinfo paylen is 17 so pad the skb
7629 * in order to meet this minimum size requirement.
7630 */
a94d9e22
AD		 7631 if (skb_put_padto(skb, 17))
7632 return NETDEV_TX_OK;
a50c29dd 7633
2a47fa45
JF		 7634 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7635
fc77dc3c 7636 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7637}
7638
2a47fa45
JF		 7639static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7640 struct net_device *netdev)
7641{
7642 return __ixgbe_xmit_frame(skb, netdev, NULL);
7643}
7644
9a799d71
AK		 7645/**
7646 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7647 * @netdev: network interface device structure
7648 * @p: pointer to an address structure
7649 *
7650 * Returns 0 on success, negative on failure
7651 **/
7652static int ixgbe_set_mac(struct net_device *netdev, void *p)
7653{
7654 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7655 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7656 struct sockaddr *addr = p;
5d7daa35 7657 int ret;
9a799d71
AK		 7658
7659 if (!is_valid_ether_addr(addr->sa_data))
7660 return -EADDRNOTAVAIL;
7661
5d7daa35 7662 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7663 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7664 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7665
5d7daa35
JK		 7666 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7667 return ret > 0 ? 0 : ret;
9a799d71
AK		 7668}
7669
6b73e10d
BH		 7670static int
7671ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7672{
7673 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7674 struct ixgbe_hw *hw = &adapter->hw;
7675 u16 value;
7676 int rc;
7677
7678 if (prtad != hw->phy.mdio.prtad)
7679 return -EINVAL;
7680 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7681 if (!rc)
7682 rc = value;
7683 return rc;
7684}
7685
7686static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7687 u16 addr, u16 value)
7688{
7689 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7690 struct ixgbe_hw *hw = &adapter->hw;
7691
7692 if (prtad != hw->phy.mdio.prtad)
7693 return -EINVAL;
7694 return hw->phy.ops.write_reg(hw, addr, devad, value);
7695}
7696
7697static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7698{
7699 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7700
3a6a4eda 7701 switch (cmd) {
3a6a4eda 7702 case SIOCSHWTSTAMP:
93501d48
JK		 7703 return ixgbe_ptp_set_ts_config(adapter, req);
7704 case SIOCGHWTSTAMP:
7705 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7706 default:
7707 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7708 }
6b73e10d
BH		 7709}
7710
0365e6e4
PW		 7711/**
7712 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7713 * netdev->dev_addrs
0365e6e4
PW		 7714 * @netdev: network interface device structure
7715 *
7716 * Returns non-zero on failure
7717 **/
7718static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7719{
7720 int err = 0;
7721 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7722 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7723
7fa7c9dc 7724 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7725 rtnl_lock();
7fa7c9dc 7726 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7727 rtnl_unlock();
7fa7c9dc
AD		 7728
7729 /* update SAN MAC vmdq pool selection */
7730 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7731 }
7732 return err;
7733}
7734
7735/**
7736 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7737 * netdev->dev_addrs
0365e6e4
PW		 7738 * @netdev: network interface device structure
7739 *
7740 * Returns non-zero on failure
7741 **/
7742static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7743{
7744 int err = 0;
7745 struct ixgbe_adapter *adapter = netdev_priv(dev);
7746 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7747
7748 if (is_valid_ether_addr(mac->san_addr)) {
7749 rtnl_lock();
7750 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7751 rtnl_unlock();
7752 }
7753 return err;
7754}
7755
9a799d71
AK		 7756#ifdef CONFIG_NET_POLL_CONTROLLER
7757/*
7758 * Polling 'interrupt' - used by things like netconsole to send skbs
7759 * without having to re-enable interrupts. It's not called while
7760 * the interrupt routine is executing.
7761 */
7762static void ixgbe_netpoll(struct net_device *netdev)
7763{
7764 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7765 int i;
9a799d71 7766
1a647bd2
AD		 7767 /* if interface is down do nothing */
7768 if (test_bit(__IXGBE_DOWN, &adapter->state))
7769 return;
7770
856f606e
AD		 7771 /* loop through and schedule all active queues */
7772 for (i = 0; i < adapter->num_q_vectors; i++)
7773 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7774}
9a799d71 7775
581330ba 7776#endif
de1036b1
ED		 7777static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7778 struct rtnl_link_stats64 *stats)
7779{
7780 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7781 int i;
7782
1a51502b 7783 rcu_read_lock();
de1036b1 7784 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7785 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7786 u64 bytes, packets;
7787 unsigned int start;
7788
1a51502b
ED		 7789 if (ring) {
7790 do {
57a7744e 7791 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7792 packets = ring->stats.packets;
7793 bytes = ring->stats.bytes;
57a7744e 7794 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7795 stats->rx_packets += packets;
7796 stats->rx_bytes += bytes;
7797 }
de1036b1 7798 }
1ac9ad13
ED		 7799
7800 for (i = 0; i < adapter->num_tx_queues; i++) {
7801 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7802 u64 bytes, packets;
7803 unsigned int start;
7804
7805 if (ring) {
7806 do {
57a7744e 7807 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7808 packets = ring->stats.packets;
7809 bytes = ring->stats.bytes;
57a7744e 7810 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7811 stats->tx_packets += packets;
7812 stats->tx_bytes += bytes;
7813 }
7814 }
1a51502b 7815 rcu_read_unlock();
de1036b1
ED		 7816 /* following stats updated by ixgbe_watchdog_task() */
7817 stats->multicast = netdev->stats.multicast;
7818 stats->rx_errors = netdev->stats.rx_errors;
7819 stats->rx_length_errors = netdev->stats.rx_length_errors;
7820 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7821 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7822 return stats;
7823}
7824
8af3c33f 7825#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7826/**
7827 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7828 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7829 * @tc: number of traffic classes currently enabled
7830 *
7831 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7832 * 802.1Q priority maps to a packet buffer that exists.
7833 */
7834static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7835{
7836 struct ixgbe_hw *hw = &adapter->hw;
7837 u32 reg, rsave;
7838 int i;
7839
7840 /* 82598 have a static priority to TC mapping that can not
7841 * be changed so no validation is needed.
7842 */
7843 if (hw->mac.type == ixgbe_mac_82598EB)
7844 return;
7845
7846 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7847 rsave = reg;
7848
7849 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7850 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7851
7852 /* If up2tc is out of bounds default to zero */
7853 if (up2tc > tc)
7854 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7855 }
7856
7857 if (reg != rsave)
7858 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7859
7860 return;
7861}
7862
02debdc9
AD		 7863/**
7864 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7865 * @adapter: Pointer to adapter struct
7866 *
7867 * Populate the netdev user priority to tc map
7868 */
7869static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7870{
7871 struct net_device *dev = adapter->netdev;
7872 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7873 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7874 u8 prio;
7875
7876 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7877 u8 tc = 0;
7878
7879 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7880 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7881 else if (ets)
7882 tc = ets->prio_tc[prio];
7883
7884 netdev_set_prio_tc_map(dev, prio, tc);
7885 }
7886}
7887
cca73c59 7888#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7889/**
7890 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7891 *
7892 * @netdev: net device to configure
7893 * @tc: number of traffic classes to enable
7894 */
7895int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7896{
8b1c0b24
JF		 7897 struct ixgbe_adapter *adapter = netdev_priv(dev);
7898 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7899 bool pools;
8b1c0b24 7900
8b1c0b24 7901 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 7902 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
7903 return -EINVAL;
7904
7905 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 7906 return -EINVAL;
7907
2a47fa45
JF		 7908 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7909 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7910 return -EBUSY;
7911
8b1c0b24 7912 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7913 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7914 * hardware is not flexible enough to do this dynamically.
7915 */
7916 if (netif_running(dev))
7917 ixgbe_close(dev);
7918 ixgbe_clear_interrupt_scheme(adapter);
7919
cca73c59 7920#ifdef CONFIG_IXGBE_DCB
e7589eab 7921 if (tc) {
8b1c0b24 7922 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7923 ixgbe_set_prio_tc_map(adapter);
7924
e7589eab 7925 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7926
943561d3
AD		 7927 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7928 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7929 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7930 }
e7589eab 7931 } else {
8b1c0b24 7932 netdev_reset_tc(dev);
02debdc9 7933
943561d3
AD		 7934 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7935 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7936
7937 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7938
7939 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7940 adapter->dcb_cfg.pfc_mode_enable = false;
7941 }
7942
8b1c0b24 7943 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7944
7945#endif /* CONFIG_IXGBE_DCB */
7946 ixgbe_init_interrupt_scheme(adapter);
7947
8b1c0b24 7948 if (netif_running(dev))
cca73c59 7949 return ixgbe_open(dev);
8b1c0b24
JF		 7950
7951 return 0;
7952}
de1036b1 7953
da36b647
GR		 7954#ifdef CONFIG_PCI_IOV
7955void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7956{
7957 struct net_device *netdev = adapter->netdev;
7958
7959 rtnl_lock();
da36b647 7960 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7961 rtnl_unlock();
7962}
7963
7964#endif
082757af
DS		 7965void ixgbe_do_reset(struct net_device *netdev)
7966{
7967 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7968
7969 if (netif_running(netdev))
7970 ixgbe_reinit_locked(adapter);
7971 else
7972 ixgbe_reset(adapter);
7973}
7974
c8f44aff 7975static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7976 netdev_features_t features)
082757af
DS		 7977{
7978 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7979
082757af 7980 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7981 if (!(features & NETIF_F_RXCSUM))
7982 features &= ~NETIF_F_LRO;
082757af 7983
567d2de2
AD		 7984 /* Turn off LRO if not RSC capable */
7985 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7986 features &= ~NETIF_F_LRO;
8e2813f5 7987
567d2de2 7988 return features;
082757af
DS		 7989}
7990
c8f44aff 7991static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7992 netdev_features_t features)
082757af
DS		 7993{
7994 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7995 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7996 bool need_reset = false;
7997
082757af 7998 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7999 if (!(features & NETIF_F_LRO)) {
8000 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8001 need_reset = true;
567d2de2
AD		 8002 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8003 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8004 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8005 if (adapter->rx_itr_setting == 1 ||
8006 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8007 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8008 need_reset = true;
8009 } else if ((changed ^ features) & NETIF_F_LRO) {
8010 e_info(probe, "rx-usecs set too low, "
8011 "disabling RSC\n");
082757af
DS		 8012 }
8013 }
8014
8015 /*
8016 * Check if Flow Director n-tuple support was enabled or disabled. If
8017 * the state changed, we need to reset.
8018 */
39cb681b
AD		 8019 switch (features & NETIF_F_NTUPLE) {
8020 case NETIF_F_NTUPLE:
567d2de2 8021 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8022 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8023 need_reset = true;
8024
567d2de2
AD		 8025 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8026 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 8027 break;
8028 default:
8029 /* turn off perfect filters, enable ATR and reset */
8030 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8031 need_reset = true;
8032
8033 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8034
8035 /* We cannot enable ATR if SR-IOV is enabled */
8036 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8037 break;
8038
8039 /* We cannot enable ATR if we have 2 or more traffic classes */
8040 if (netdev_get_num_tc(netdev) > 1)
8041 break;
8042
8043 /* We cannot enable ATR if RSS is disabled */
8044 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
8045 break;
8046
8047 /* A sample rate of 0 indicates ATR disabled */
8048 if (!adapter->atr_sample_rate)
8049 break;
8050
8051 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8052 break;
082757af
DS		 8053 }
8054
f646968f 8055 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8056 ixgbe_vlan_strip_enable(adapter);
8057 else
8058 ixgbe_vlan_strip_disable(adapter);
8059
3f2d1c0f
BG		 8060 if (changed & NETIF_F_RXALL)
8061 need_reset = true;
8062
567d2de2 8063 netdev->features = features;
67359c3c
MR		 8064
8065#ifdef CONFIG_IXGBE_VXLAN
8066 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8067 if (features & NETIF_F_RXCSUM)
8068 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8069 else
8070 ixgbe_clear_vxlan_port(adapter);
8071 }
8072#endif /* CONFIG_IXGBE_VXLAN */
8073
082757af
DS		 8074 if (need_reset)
8075 ixgbe_do_reset(netdev);
8076
8077 return 0;
082757af
DS		 8078}
8079
67359c3c 8080#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8081/**
8082 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8083 * @dev: The port's netdev
8084 * @sa_family: Socket Family that VXLAN is notifiying us about
8085 * @port: New UDP port number that VXLAN started listening to
8086 **/
8087static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8088 __be16 port)
8089{
8090 struct ixgbe_adapter *adapter = netdev_priv(dev);
8091 struct ixgbe_hw *hw = &adapter->hw;
8092 u16 new_port = ntohs(port);
8093
67359c3c
MR		 8094 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8095 return;
8096
3f207800
DS		 8097 if (sa_family == AF_INET6)
8098 return;
8099
67359c3c 8100 if (adapter->vxlan_port == new_port)
3f207800 8101 return;
3f207800
DS		 8102
8103 if (adapter->vxlan_port) {
8104 netdev_info(dev,
67359c3c 8105 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8106 new_port);
8107 return;
8108 }
8109
8110 adapter->vxlan_port = new_port;
8111 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8112}
8113
8114/**
8115 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8116 * @dev: The port's netdev
8117 * @sa_family: Socket Family that VXLAN is notifying us about
8118 * @port: UDP port number that VXLAN stopped listening to
8119 **/
8120static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8121 __be16 port)
8122{
8123 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8124 u16 new_port = ntohs(port);
8125
67359c3c
MR		 8126 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8127 return;
8128
3f207800
DS		 8129 if (sa_family == AF_INET6)
8130 return;
8131
8132 if (adapter->vxlan_port != new_port) {
8133 netdev_info(dev, "Port %d was not found, not deleting\n",
8134 new_port);
8135 return;
8136 }
8137
67359c3c
MR		 8138 ixgbe_clear_vxlan_port(adapter);
8139 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8140}
67359c3c 8141#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8142
edc7d573 8143static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8144 struct net_device *dev,
f6f6424b 8145 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8146 u16 flags)
8147{
bcfd3432 8148 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8149 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 8150 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8151 return -ENOMEM;
0f4b0add
JF		 8152 }
8153
f6f6424b 8154 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8155}
8156
219efe97
DS		 8157/**
8158 * ixgbe_configure_bridge_mode - set various bridge modes
8159 * @adapter - the private structure
8160 * @mode - requested bridge mode
8161 *
8162 * Configure some settings require for various bridge modes.
8163 **/
8164static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8165 __u16 mode)
8166{
6d4c96ad
DS		 8167 struct ixgbe_hw *hw = &adapter->hw;
8168 unsigned int p, num_pools;
8169 u32 vmdctl;
8170
219efe97
DS		 8171 switch (mode) {
8172 case BRIDGE_MODE_VEPA:
6d4c96ad 8173 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8174 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8175
8176 /* must enable Rx switching replication to allow multicast
8177 * packet reception on all VFs, and to enable source address
8178 * pruning.
8179 */
8180 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8181 vmdctl |= IXGBE_VT_CTL_REPLEN;
8182 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8183
8184 /* enable Rx source address pruning. Note, this requires
8185 * replication to be enabled or else it does nothing.
8186 */
8187 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8188 for (p = 0; p < num_pools; p++) {
8189 if (hw->mac.ops.set_source_address_pruning)
8190 hw->mac.ops.set_source_address_pruning(hw,
8191 true,
8192 p);
8193 }
219efe97
DS		 8194 break;
8195 case BRIDGE_MODE_VEB:
6d4c96ad 8196 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8197 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8198 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8199
8200 /* disable Rx switching replication unless we have SR-IOV
8201 * virtual functions
8202 */
8203 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8204 if (!adapter->num_vfs)
8205 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8206 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8207
8208 /* disable Rx source address pruning, since we don't expect to
8209 * be receiving external loopback of our transmitted frames.
8210 */
8211 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8212 for (p = 0; p < num_pools; p++) {
8213 if (hw->mac.ops.set_source_address_pruning)
8214 hw->mac.ops.set_source_address_pruning(hw,
8215 false,
8216 p);
8217 }
219efe97
DS		 8218 break;
8219 default:
8220 return -EINVAL;
8221 }
8222
8223 adapter->bridge_mode = mode;
8224
8225 e_info(drv, "enabling bridge mode: %s\n",
8226 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8227
8228 return 0;
8229}
8230
815cccbf 8231static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8232 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8233{
8234 struct ixgbe_adapter *adapter = netdev_priv(dev);
8235 struct nlattr *attr, *br_spec;
8236 int rem;
8237
8238 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8239 return -EOPNOTSUPP;
8240
8241 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8242 if (!br_spec)
8243 return -EINVAL;
815cccbf
JF		 8244
8245 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8246 int status;
815cccbf 8247 __u16 mode;
815cccbf
JF		 8248
8249 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8250 continue;
8251
b7c1a314
TG		 8252 if (nla_len(attr) < sizeof(mode))
8253 return -EINVAL;
8254
815cccbf 8255 mode = nla_get_u16(attr);
219efe97
DS		 8256 status = ixgbe_configure_bridge_mode(adapter, mode);
8257 if (status)
8258 return status;
aa2bacb6
DS		 8259
8260 break;
815cccbf
JF		 8261 }
8262
8263 return 0;
8264}
8265
8266static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8267 struct net_device *dev,
46c264da 8268 u32 filter_mask, int nlflags)
815cccbf
JF		 8269{
8270 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8271
8272 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8273 return 0;
8274
aa2bacb6 8275 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8276 adapter->bridge_mode, 0, 0, nlflags,
8277 filter_mask, NULL);
815cccbf
JF		 8278}
8279
2a47fa45
JF		 8280static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8281{
8282 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8283 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8284 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8285 unsigned int limit;
2a47fa45
JF		 8286 int pool, err;
8287
aac2f1bf
JK		 8288 /* Hardware has a limited number of available pools. Each VF, and the
8289 * PF require a pool. Check to ensure we don't attempt to use more
8290 * then the available number of pools.
8291 */
8292 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8293 return ERR_PTR(-EINVAL);
8294
219354d4
JF		 8295#ifdef CONFIG_RPS
8296 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8297 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8298 vdev->name);
8299 return ERR_PTR(-EINVAL);
8300 }
8301#endif
2a47fa45 8302 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8303 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8304 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8305 netdev_info(pdev,
8306 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8307 pdev->name);
8308 return ERR_PTR(-EINVAL);
8309 }
8310
8311 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8312 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8313 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8314 return ERR_PTR(-EBUSY);
8315
bc52f951 8316 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8317 if (!fwd_adapter)
8318 return ERR_PTR(-ENOMEM);
8319
8320 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8321 adapter->num_rx_pools++;
8322 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8323 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8324
8325 /* Enable VMDq flag so device will be set in VM mode */
8326 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8327 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8328 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8329
8330 /* Force reinit of ring allocation with VMDQ enabled */
8331 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8332 if (err)
8333 goto fwd_add_err;
8334 fwd_adapter->pool = pool;
8335 fwd_adapter->real_adapter = adapter;
8336 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8337 if (err)
8338 goto fwd_add_err;
8339 netif_tx_start_all_queues(vdev);
8340 return fwd_adapter;
8341fwd_add_err:
8342 /* unwind counter and free adapter struct */
8343 netdev_info(pdev,
8344 "%s: dfwd hardware acceleration failed\n", vdev->name);
8345 clear_bit(pool, &adapter->fwd_bitmask);
8346 adapter->num_rx_pools--;
8347 kfree(fwd_adapter);
8348 return ERR_PTR(err);
8349}
8350
8351static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8352{
8353 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8354 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8355 unsigned int limit;
2a47fa45
JF		 8356
8357 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8358 adapter->num_rx_pools--;
8359
51f3773b
JF		 8360 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8361 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8362 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8363 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8364 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8365 fwd_adapter->pool, adapter->num_rx_pools,
8366 fwd_adapter->rx_base_queue,
8367 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8368 adapter->fwd_bitmask);
8369 kfree(fwd_adapter);
8370}
8371
f467bc06
MR		 8372#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8373static netdev_features_t
8374ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8375 netdev_features_t features)
8376{
8377 if (!skb->encapsulation)
8378 return features;
8379
8380 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8381 IXGBE_MAX_TUNNEL_HDR_LEN))
8382 return features & ~NETIF_F_ALL_CSUM;
8383
8384 return features;
8385}
8386
0edc3527 8387static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8388 .ndo_open = ixgbe_open,
0edc3527 8389 .ndo_stop = ixgbe_close,
00829823 8390 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8391 .ndo_select_queue = ixgbe_select_queue,
581330ba 8392 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8393 .ndo_validate_addr = eth_validate_addr,
8394 .ndo_set_mac_address = ixgbe_set_mac,
8395 .ndo_change_mtu = ixgbe_change_mtu,
8396 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8397 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8398 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8399 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8400 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8401 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8402 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8403 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8404 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8405 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8406 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8407 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8408#ifdef CONFIG_IXGBE_DCB
24095aa3 8409 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8410#endif
0edc3527
SH		 8411#ifdef CONFIG_NET_POLL_CONTROLLER
8412 .ndo_poll_controller = ixgbe_netpoll,
8413#endif
e0d1095a 8414#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8415 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8416#endif
332d4a7d
YZ		 8417#ifdef IXGBE_FCOE
8418 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8419 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8420 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8421 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8422 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8423 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8424 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8425#endif /* IXGBE_FCOE */
082757af
DS		 8426 .ndo_set_features = ixgbe_set_features,
8427 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8428 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8429 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8430 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8431 .ndo_dfwd_add_station = ixgbe_fwd_add,
8432 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8433#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8434 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8435 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8436#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8437 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8438};
8439
e027d1ae
JK		 8440/**
8441 * ixgbe_enumerate_functions - Get the number of ports this device has
8442 * @adapter: adapter structure
8443 *
8444 * This function enumerates the phsyical functions co-located on a single slot,
8445 * in order to determine how many ports a device has. This is most useful in
8446 * determining the required GT/s of PCIe bandwidth necessary for optimal
8447 * performance.
8448 **/
8449static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8450{
caafb95d 8451 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8452 int physfns = 0;
8453
f1f96579
JK		 8454 /* Some cards can not use the generic count PCIe functions method,
8455 * because they are behind a parent switch, so we hardcode these with
8456 * the correct number of functions.
e027d1ae 8457 */
8818970d 8458 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8459 physfns = 4;
8818970d
JK		 8460
8461 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8462 /* don't count virtual functions */
caafb95d
JK		 8463 if (entry->is_virtfn)
8464 continue;
8465
8466 /* When the devices on the bus don't all match our device ID,
8467 * we can't reliably determine the correct number of
8468 * functions. This can occur if a function has been direct
8469 * attached to a virtual machine using VT-d, for example. In
8470 * this case, simply return -1 to indicate this.
8471 */
8472 if ((entry->vendor != pdev->vendor) ||
8473 (entry->device != pdev->device))
8474 return -1;
8475
8476 physfns++;
e027d1ae
JK		 8477 }
8478
8479 return physfns;
8480}
8481
8e2813f5
JK		 8482/**
8483 * ixgbe_wol_supported - Check whether device supports WoL
8484 * @hw: hw specific details
8485 * @device_id: the device ID
8486 * @subdev_id: the subsystem device ID
8487 *
8488 * This function is used by probe and ethtool to determine
8489 * which devices have WoL support
8490 *
8491 **/
8492int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8493 u16 subdevice_id)
8494{
8495 struct ixgbe_hw *hw = &adapter->hw;
8496 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8497 int is_wol_supported = 0;
8498
8499 switch (device_id) {
8500 case IXGBE_DEV_ID_82599_SFP:
8501 /* Only these subdevices could supports WOL */
8502 switch (subdevice_id) {
87557440 8503 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8504 case IXGBE_SUBDEV_ID_82599_560FLR:
8505 /* only support first port */
8506 if (hw->bus.func != 0)
8507 break;
5700ff26 8508 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8509 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8510 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8511 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8512 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8513 is_wol_supported = 1;
8514 break;
8515 }
8516 break;
5daebbb0
DS		 8517 case IXGBE_DEV_ID_82599EN_SFP:
8518 /* Only this subdevice supports WOL */
8519 switch (subdevice_id) {
8520 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8521 is_wol_supported = 1;
8522 break;
8523 }
8524 break;
8e2813f5
JK		 8525 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8526 /* All except this subdevice support WOL */
8527 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8528 is_wol_supported = 1;
8529 break;
8530 case IXGBE_DEV_ID_82599_KX4:
8531 is_wol_supported = 1;
8532 break;
8533 case IXGBE_DEV_ID_X540T:
df376f0d 8534 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8535 case IXGBE_DEV_ID_X550T:
8536 case IXGBE_DEV_ID_X550EM_X_KX4:
8537 case IXGBE_DEV_ID_X550EM_X_KR:
8538 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8539 /* check eeprom to see if enabled wol */
8540 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8541 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8542 (hw->bus.func == 0))) {
8543 is_wol_supported = 1;
8544 }
8545 break;
8546 }
8547
8548 return is_wol_supported;
8549}
8550
c762dff2
MP		 8551/**
8552 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8553 * @adapter: Pointer to adapter struct
8554 */
8555static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8556{
8557#ifdef CONFIG_OF
8558 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8559 struct ixgbe_hw *hw = &adapter->hw;
8560 const unsigned char *addr;
8561
8562 addr = of_get_mac_address(dp);
8563 if (addr) {
8564 ether_addr_copy(hw->mac.perm_addr, addr);
8565 return;
8566 }
8567#endif /* CONFIG_OF */
8568
8569#ifdef CONFIG_SPARC
8570 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8571#endif /* CONFIG_SPARC */
8572}
8573
9a799d71
AK		 8574/**
8575 * ixgbe_probe - Device Initialization Routine
8576 * @pdev: PCI device information struct
8577 * @ent: entry in ixgbe_pci_tbl
8578 *
8579 * Returns 0 on success, negative on failure
8580 *
8581 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8582 * The OS initialization, configuring of the adapter private structure,
8583 * and a hardware reset occur.
8584 **/
1dd06ae8 8585static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8586{
8587 struct net_device *netdev;
8588 struct ixgbe_adapter *adapter = NULL;
8589 struct ixgbe_hw *hw;
8590 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8591 int i, err, pci_using_dac, expected_gts;
d3cb9869 8592 unsigned int indices = MAX_TX_QUEUES;
289700db 8593 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8594 bool disable_dev = false;
eacd73f7
YZ		 8595#ifdef IXGBE_FCOE
8596 u16 device_caps;
8597#endif
289700db 8598 u32 eec;
9a799d71 8599
bded64a7
AG		 8600 /* Catch broken hardware that put the wrong VF device ID in
8601 * the PCIe SR-IOV capability.
8602 */
8603 if (pdev->is_virtfn) {
8604 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8605 pci_name(pdev), pdev->vendor, pdev->device);
8606 return -EINVAL;
8607 }
8608
9ce77666 8609 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8610 if (err)
8611 return err;
8612
f5f2eda8 8613 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8614 pci_using_dac = 1;
8615 } else {
f5f2eda8 8616 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8617 if (err) {
f5f2eda8
RK		 8618 dev_err(&pdev->dev,
8619 "No usable DMA configuration, aborting\n");
8620 goto err_dma;
9a799d71
AK		 8621 }
8622 pci_using_dac = 0;
8623 }
8624
9ce77666 8625 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8626 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8627 if (err) {
b8bc0421
DC		 8628 dev_err(&pdev->dev,
8629 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8630 goto err_pci_reg;
8631 }
8632
19d5afd4 8633 pci_enable_pcie_error_reporting(pdev);
6fabd715 8634
9a799d71 8635 pci_set_master(pdev);
fb3b27bc 8636 pci_save_state(pdev);
9a799d71 8637
d3cb9869 8638 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8639#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8640 /* 8 TC w/ 4 queues per TC */
8641 indices = 4 * MAX_TRAFFIC_CLASS;
8642#else
8643 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8644#endif
d3cb9869 8645 }
e901acd6 8646
c85a2618 8647 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8648 if (!netdev) {
8649 err = -ENOMEM;
8650 goto err_alloc_etherdev;
8651 }
8652
9a799d71
AK		 8653 SET_NETDEV_DEV(netdev, &pdev->dev);
8654
9a799d71
AK		 8655 adapter = netdev_priv(netdev);
8656
8657 adapter->netdev = netdev;
8658 adapter->pdev = pdev;
8659 hw = &adapter->hw;
8660 hw->back = adapter;
b3f4d599 8661 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8662
05857980 8663 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8664 pci_resource_len(pdev, 0));
2a1a091c 8665 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8666 if (!hw->hw_addr) {
8667 err = -EIO;
8668 goto err_ioremap;
8669 }
8670
0edc3527 8671 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8672 ixgbe_set_ethtool_ops(netdev);
9a799d71 8673 netdev->watchdog_timeo = 5 * HZ;
339de30f 8674 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8675
9a799d71
AK		 8676 /* Setup hw api */
8677 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8678 hw->mac.type = ii->mac;
9a900eca 8679 hw->mvals = ii->mvals;
9a799d71 8680
c44ade9e
JB		 8681 /* EEPROM */
8682 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8683 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8684 if (ixgbe_removed(hw->hw_addr)) {
8685 err = -EIO;
8686 goto err_ioremap;
8687 }
c44ade9e
JB		 8688 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8689 if (!(eec & (1 << 8)))
8690 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8691
8692 /* PHY */
8693 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8694 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8695 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8696 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8697 hw->phy.mdio.mmds = 0;
8698 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8699 hw->phy.mdio.dev = netdev;
8700 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8701 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8702
8ca783ab 8703 ii->get_invariants(hw);
9a799d71
AK		 8704
8705 /* setup the private structure */
8706 err = ixgbe_sw_init(adapter);
8707 if (err)
8708 goto err_sw_init;
8709
e86bff0e 8710 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8711 switch (adapter->hw.mac.type) {
8712 case ixgbe_mac_82599EB:
8713 case ixgbe_mac_X540:
9a75a1ac
DS		 8714 case ixgbe_mac_X550:
8715 case ixgbe_mac_X550EM_x:
e86bff0e 8716 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8717 break;
8718 default:
8719 break;
8720 }
e86bff0e 8721
bf069c97
DS		 8722 /*
8723 * If there is a fan on this device and it has failed log the
8724 * failure.
8725 */
8726 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8727 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8728 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8729 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8730 }
8731
8ef78adc
PWJ		 8732 if (allow_unsupported_sfp)
8733 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8734
c44ade9e 8735 /* reset_hw fills in the perm_addr as well */
119fc60a 8736 hw->phy.reset_if_overtemp = true;
c44ade9e 8737 err = hw->mac.ops.reset_hw(hw);
119fc60a 8738 hw->phy.reset_if_overtemp = false;
29a8dca1 8739 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 8740 err = 0;
8741 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8742 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8743 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8744 goto err_sw_init;
8745 } else if (err) {
849c4542 8746 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8747 goto err_sw_init;
8748 }
8749
99d74487 8750#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8751 /* SR-IOV not supported on the 82598 */
8752 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8753 goto skip_sriov;
8754 /* Mailbox */
8755 ixgbe_init_mbx_params_pf(hw);
8756 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8757 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8758 ixgbe_enable_sriov(adapter);
60a1a680 8759skip_sriov:
1cdd1ec8 8760
99d74487 8761#endif
396e799c 8762 netdev->features = NETIF_F_SG |
e8e9f696 8763 NETIF_F_IP_CSUM |
082757af 8764 NETIF_F_IPV6_CSUM |
f646968f
PM		 8765 NETIF_F_HW_VLAN_CTAG_TX |
8766 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8767 NETIF_F_TSO |
8768 NETIF_F_TSO6 |
082757af 8769 NETIF_F_RXHASH |
8bf1264d 8770 NETIF_F_RXCSUM;
9a799d71 8771
8bf1264d 8772 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8773
58be7666
DS		 8774 switch (adapter->hw.mac.type) {
8775 case ixgbe_mac_82599EB:
8776 case ixgbe_mac_X540:
9a75a1ac
DS		 8777 case ixgbe_mac_X550:
8778 case ixgbe_mac_X550EM_x:
45a5ead0 8779 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8780 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8781 NETIF_F_NTUPLE;
58be7666
DS		 8782 break;
8783 default:
8784 break;
8785 }
45a5ead0 8786
3f2d1c0f 8787 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8788 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8789
ad31c402
JK		 8790 netdev->vlan_features |= NETIF_F_TSO;
8791 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8792 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8793 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8794 netdev->vlan_features |= NETIF_F_SG;
8795
f467bc06
MR		 8796 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8797 NETIF_F_IPV6_CSUM;
8798
01789349 8799 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8800 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8801
67359c3c 8802#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8803 switch (adapter->hw.mac.type) {
8804 case ixgbe_mac_X550:
8805 case ixgbe_mac_X550EM_x:
67359c3c
MR		 8806 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8807 NETIF_F_IP_CSUM |
8808 NETIF_F_IPV6_CSUM;
3f207800
DS		 8809 break;
8810 default:
8811 break;
8812 }
67359c3c 8813#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8814
7a6b6f51 8815#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8816 netdev->dcbnl_ops = &dcbnl_ops;
8817#endif
8818
eacd73f7 8819#ifdef IXGBE_FCOE
0d551589 8820 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8821 unsigned int fcoe_l;
8822
eacd73f7
YZ		 8823 if (hw->mac.ops.get_device_caps) {
8824 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8825 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8826 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8827 }
7c8ae65a 8828
d3cb9869
AD		 8829
8830 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8831 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8832
a58915c7
AD		 8833 netdev->features |= NETIF_F_FSO |
8834 NETIF_F_FCOE_CRC;
8835
7c8ae65a
AD		 8836 netdev->vlan_features |= NETIF_F_FSO |
8837 NETIF_F_FCOE_CRC |
8838 NETIF_F_FCOE_MTU;
5e09d7f6 8839 }
eacd73f7 8840#endif /* IXGBE_FCOE */
7b872a55 8841 if (pci_using_dac) {
9a799d71 8842 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8843 netdev->vlan_features |= NETIF_F_HIGHDMA;
8844 }
9a799d71 8845
082757af
DS		 8846 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8847 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8848 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8849 netdev->features |= NETIF_F_LRO;
8850
9a799d71 8851 /* make sure the EEPROM is good */
c44ade9e 8852 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8853 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8854 err = -EIO;
35937c05 8855 goto err_sw_init;
9a799d71
AK		 8856 }
8857
c762dff2
MP		 8858 ixgbe_get_platform_mac_addr(adapter);
8859
9a799d71 8860 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8861
aaeb6cdf 8862 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8863 e_dev_err("invalid MAC address\n");
9a799d71 8864 err = -EIO;
35937c05 8865 goto err_sw_init;
9a799d71
AK		 8866 }
8867
5d7daa35
JK		 8868 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8869
7086400d 8870 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8871 (unsigned long) adapter);
9a799d71 8872
58cf663f
MR		 8873 if (ixgbe_removed(hw->hw_addr)) {
8874 err = -EIO;
8875 goto err_sw_init;
8876 }
7086400d 8877 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8878 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8879 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8880
021230d4
AV		 8881 err = ixgbe_init_interrupt_scheme(adapter);
8882 if (err)
8883 goto err_sw_init;
9a799d71 8884
8e2813f5 8885 /* WOL not supported for all devices */
c23f5b6b 8886 adapter->wol = 0;
8e2813f5 8887 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8888 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8889 pdev->subsystem_device);
6b92b0ba 8890 if (hw->wol_enabled)
9417c464 8891 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8892
e8e26350
PW		 8893 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8894
15e5209f
ET		 8895 /* save off EEPROM version number */
8896 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8897 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8898
04f165ef 8899 /* pick up the PCI bus settings for reporting later */
e027d1ae 8900 if (ixgbe_pcie_from_parent(hw))
b8e82001 8901 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 8902 else
8903 hw->mac.ops.get_bus_info(hw);
04f165ef 8904
e027d1ae
JK		 8905 /* calculate the expected PCIe bandwidth required for optimal
8906 * performance. Note that some older parts will never have enough
8907 * bandwidth due to being older generation PCIe parts. We clamp these
8908 * parts to ensure no warning is displayed if it can't be fixed.
8909 */
8910 switch (hw->mac.type) {
8911 case ixgbe_mac_82598EB:
8912 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8913 break;
8914 default:
8915 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8916 break;
0c254d86 8917 }
caafb95d
JK		 8918
8919 /* don't check link if we failed to enumerate functions */
8920 if (expected_gts > 0)
8921 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8922
339de30f 8923 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8924 if (err)
339de30f 8925 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8926 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8927 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8928 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8929 part_str);
6a2aae5a
JK		 8930 else
8931 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8932 hw->mac.type, hw->phy.type, part_str);
8933
8934 e_dev_info("%pM\n", netdev->dev_addr);
8935
9a799d71 8936 /* reset the hardware with the new settings */
794caeb2 8937 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8938 if (err == IXGBE_ERR_EEPROM_VERSION) {
8939 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8940 e_dev_warn("This device is a pre-production adapter/LOM. "
8941 "Please be aware there may be issues associated "
8942 "with your hardware. If you are experiencing "
8943 "problems please contact your Intel or hardware "
8944 "representative who provided you with this "
8945 "hardware.\n");
794caeb2 8946 }
9a799d71
AK		 8947 strcpy(netdev->name, "eth%d");
8948 err = register_netdev(netdev);
8949 if (err)
8950 goto err_register;
8951
0fb6a55c
ET		 8952 pci_set_drvdata(pdev, adapter);
8953
ec74a471
ET		 8954 /* power down the optics for 82599 SFP+ fiber */
8955 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8956 hw->mac.ops.disable_tx_laser(hw);
8957
54386467
JB		 8958 /* carrier off reporting is important to ethtool even BEFORE open */
8959 netif_carrier_off(netdev);
8960
5dd2d332 8961#ifdef CONFIG_IXGBE_DCA
652f093f 8962 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8963 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8964 ixgbe_setup_dca(adapter);
8965 }
8966#endif
1cdd1ec8 8967 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8968 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8969 for (i = 0; i < adapter->num_vfs; i++)
8970 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8971 }
8972
2466dd9c
JK		 8973 /* firmware requires driver version to be 0xFFFFFFFF
8974 * since os does not support feature
8975 */
9612de92 8976 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8977 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8978 0xFF);
9612de92 8979
0365e6e4
PW		 8980 /* add san mac addr to netdev */
8981 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8982
ea81875a 8983 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8984
1210982b 8985#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8986 if (ixgbe_sysfs_init(adapter))
8987 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8988#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8989
00949167 8990 ixgbe_dbg_adapter_init(adapter);
00949167 8991
d1a35ee2
ET		 8992 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8993 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8994 hw->mac.ops.setup_link(hw,
8995 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8996 true);
8997
9a799d71
AK		 8998 return 0;
8999
9000err_register:
5eba3699 9001 ixgbe_release_hw_control(adapter);
7a921c93 9002 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9003err_sw_init:
99d74487 9004 ixgbe_disable_sriov(adapter);
7086400d 9005 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9006 iounmap(adapter->io_addr);
5d7daa35 9007 kfree(adapter->mac_table);
9a799d71 9008err_ioremap:
b5b2ffc0 9009 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9010 free_netdev(netdev);
9011err_alloc_etherdev:
e8e9f696
JP		 9012 pci_release_selected_regions(pdev,
9013 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9014err_pci_reg:
9015err_dma:
b5b2ffc0 9016 if (!adapter || disable_dev)
41c62843 9017 pci_disable_device(pdev);
9a799d71
AK		 9018 return err;
9019}
9020
9021/**
9022 * ixgbe_remove - Device Removal Routine
9023 * @pdev: PCI device information struct
9024 *
9025 * ixgbe_remove is called by the PCI subsystem to alert the driver
9026 * that it should release a PCI device. The could be caused by a
9027 * Hot-Plug event, or because the driver is going to be removed from
9028 * memory.
9029 **/
9f9a12f8 9030static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9031{
c60fbb00 9032 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9033 struct net_device *netdev;
b5b2ffc0 9034 bool disable_dev;
9a799d71 9035
0fb6a55c
ET		 9036 /* if !adapter then we already cleaned up in probe */
9037 if (!adapter)
9038 return;
9039
9040 netdev = adapter->netdev;
00949167 9041 ixgbe_dbg_adapter_exit(adapter);
00949167 9042
09f40aed 9043 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9044 cancel_work_sync(&adapter->service_task);
9a799d71 9045
3a6a4eda 9046
5dd2d332 9047#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9048 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9049 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9050 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9051 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9052 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9053 }
9054
9055#endif
1210982b 9056#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9057 ixgbe_sysfs_exit(adapter);
1210982b 9058#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9059
0365e6e4
PW		 9060 /* remove the added san mac */
9061 ixgbe_del_sanmac_netdev(netdev);
9062
da36b647 9063#ifdef CONFIG_PCI_IOV
7837e286 9064 ixgbe_disable_sriov(adapter);
da36b647 9065#endif
6b010e9b
AW		 9066 if (netdev->reg_state == NETREG_REGISTERED)
9067 unregister_netdev(netdev);
9068
7a921c93 9069 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9070
021230d4 9071 ixgbe_release_hw_control(adapter);
9a799d71 9072
2b1588c3
AD		 9073#ifdef CONFIG_DCB
9074 kfree(adapter->ixgbe_ieee_pfc);
9075 kfree(adapter->ixgbe_ieee_ets);
9076
9077#endif
2a1a091c 9078 iounmap(adapter->io_addr);
9ce77666 9079 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9080 IORESOURCE_MEM));
9a799d71 9081
849c4542 9082 e_dev_info("complete\n");
021230d4 9083
5d7daa35 9084 kfree(adapter->mac_table);
b5b2ffc0 9085 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9086 free_netdev(netdev);
9087
19d5afd4 9088 pci_disable_pcie_error_reporting(pdev);
6fabd715 9089
b5b2ffc0 9090 if (disable_dev)
41c62843 9091 pci_disable_device(pdev);
9a799d71
AK		 9092}
9093
9094/**
9095 * ixgbe_io_error_detected - called when PCI error is detected
9096 * @pdev: Pointer to PCI device
9097 * @state: The current pci connection state
9098 *
9099 * This function is called after a PCI bus error affecting
9100 * this device has been detected.
9101 */
9102static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9103 pci_channel_state_t state)
9a799d71 9104{
c60fbb00
AD		 9105 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9106 struct net_device *netdev = adapter->netdev;
9a799d71 9107
83c61fa9 9108#ifdef CONFIG_PCI_IOV
14438464 9109 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9110 struct pci_dev *bdev, *vfdev;
9111 u32 dw0, dw1, dw2, dw3;
9112 int vf, pos;
9113 u16 req_id, pf_func;
9114
9115 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9116 adapter->num_vfs == 0)
9117 goto skip_bad_vf_detection;
9118
9119 bdev = pdev->bus->self;
62f87c0e 9120 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9121 bdev = bdev->bus->self;
9122
9123 if (!bdev)
9124 goto skip_bad_vf_detection;
9125
9126 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9127 if (!pos)
9128 goto skip_bad_vf_detection;
9129
14438464
MR		 9130 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9131 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9132 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9133 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9134 if (ixgbe_removed(hw->hw_addr))
9135 goto skip_bad_vf_detection;
83c61fa9
GR		 9136
9137 req_id = dw1 >> 16;
9138 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9139 if (!(req_id & 0x0080))
9140 goto skip_bad_vf_detection;
9141
9142 pf_func = req_id & 0x01;
9143 if ((pf_func & 1) == (pdev->devfn & 1)) {
9144 unsigned int device_id;
9145
9146 vf = (req_id & 0x7F) >> 1;
9147 e_dev_err("VF %d has caused a PCIe error\n", vf);
9148 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9149 "%8.8x\tdw3: %8.8x\n",
9150 dw0, dw1, dw2, dw3);
9151 switch (adapter->hw.mac.type) {
9152 case ixgbe_mac_82599EB:
9153 device_id = IXGBE_82599_VF_DEVICE_ID;
9154 break;
9155 case ixgbe_mac_X540:
9156 device_id = IXGBE_X540_VF_DEVICE_ID;
9157 break;
9a75a1ac
DS		 9158 case ixgbe_mac_X550:
9159 device_id = IXGBE_DEV_ID_X550_VF;
9160 break;
9161 case ixgbe_mac_X550EM_x:
9162 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9163 break;
83c61fa9
GR		 9164 default:
9165 device_id = 0;
9166 break;
9167 }
9168
9169 /* Find the pci device of the offending VF */
36e90319 9170 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9171 while (vfdev) {
9172 if (vfdev->devfn == (req_id & 0xFF))
9173 break;
36e90319 9174 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9175 device_id, vfdev);
9176 }
9177 /*
9178 * There's a slim chance the VF could have been hot plugged,
9179 * so if it is no longer present we don't need to issue the
9180 * VFLR. Just clean up the AER in that case.
9181 */
9182 if (vfdev) {
9079e416 9183 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9184 /* Free device reference count */
9185 pci_dev_put(vfdev);
83c61fa9
GR		 9186 }
9187
9188 pci_cleanup_aer_uncorrect_error_status(pdev);
9189 }
9190
9191 /*
9192 * Even though the error may have occurred on the other port
9193 * we still need to increment the vf error reference count for
9194 * both ports because the I/O resume function will be called
9195 * for both of them.
9196 */
9197 adapter->vferr_refcount++;
9198
9199 return PCI_ERS_RESULT_RECOVERED;
9200
9201skip_bad_vf_detection:
9202#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9203 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9204 return PCI_ERS_RESULT_DISCONNECT;
9205
41c62843 9206 rtnl_lock();
9a799d71
AK		 9207 netif_device_detach(netdev);
9208
41c62843
MR		 9209 if (state == pci_channel_io_perm_failure) {
9210 rtnl_unlock();
3044b8d1 9211 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9212 }
3044b8d1 9213
9a799d71
AK		 9214 if (netif_running(netdev))
9215 ixgbe_down(adapter);
41c62843
MR		 9216
9217 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9218 pci_disable_device(pdev);
9219 rtnl_unlock();
9a799d71 9220
b4617240 9221 /* Request a slot reset. */
9a799d71
AK		 9222 return PCI_ERS_RESULT_NEED_RESET;
9223}
9224
9225/**
9226 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9227 * @pdev: Pointer to PCI device
9228 *
9229 * Restart the card from scratch, as if from a cold-boot.
9230 */
9231static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9232{
c60fbb00 9233 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9234 pci_ers_result_t result;
9235 int err;
9a799d71 9236
9ce77666 9237 if (pci_enable_device_mem(pdev)) {
396e799c 9238 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9239 result = PCI_ERS_RESULT_DISCONNECT;
9240 } else {
4e857c58 9241 smp_mb__before_atomic();
41c62843 9242 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9243 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9244 pci_set_master(pdev);
9245 pci_restore_state(pdev);
c0e1f68b 9246 pci_save_state(pdev);
9a799d71 9247
dd4d8ca6 9248 pci_wake_from_d3(pdev, false);
9a799d71 9249
6fabd715 9250 ixgbe_reset(adapter);
88512539 9251 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9252 result = PCI_ERS_RESULT_RECOVERED;
9253 }
9254
9255 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9256 if (err) {
849c4542
ET		 9257 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9258 "failed 0x%0x\n", err);
6fabd715
PWJ		 9259 /* non-fatal, continue */
9260 }
9a799d71 9261
6fabd715 9262 return result;
9a799d71
AK		 9263}
9264
9265/**
9266 * ixgbe_io_resume - called when traffic can start flowing again.
9267 * @pdev: Pointer to PCI device
9268 *
9269 * This callback is called when the error recovery driver tells us that
9270 * its OK to resume normal operation.
9271 */
9272static void ixgbe_io_resume(struct pci_dev *pdev)
9273{
c60fbb00
AD		 9274 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9275 struct net_device *netdev = adapter->netdev;
9a799d71 9276
83c61fa9
GR		 9277#ifdef CONFIG_PCI_IOV
9278 if (adapter->vferr_refcount) {
9279 e_info(drv, "Resuming after VF err\n");
9280 adapter->vferr_refcount--;
9281 return;
9282 }
9283
9284#endif
c7ccde0f
AD		 9285 if (netif_running(netdev))
9286 ixgbe_up(adapter);
9a799d71
AK		 9287
9288 netif_device_attach(netdev);
9a799d71
AK		 9289}
9290
3646f0e5 9291static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9292 .error_detected = ixgbe_io_error_detected,
9293 .slot_reset = ixgbe_io_slot_reset,
9294 .resume = ixgbe_io_resume,
9295};
9296
9297static struct pci_driver ixgbe_driver = {
9298 .name = ixgbe_driver_name,
9299 .id_table = ixgbe_pci_tbl,
9300 .probe = ixgbe_probe,
9f9a12f8 9301 .remove = ixgbe_remove,
9a799d71
AK		 9302#ifdef CONFIG_PM
9303 .suspend = ixgbe_suspend,
9304 .resume = ixgbe_resume,
9305#endif
9306 .shutdown = ixgbe_shutdown,
da36b647 9307 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9308 .err_handler = &ixgbe_err_handler
9309};
9310
9311/**
9312 * ixgbe_init_module - Driver Registration Routine
9313 *
9314 * ixgbe_init_module is the first routine called when the driver is
9315 * loaded. All it does is register with the PCI subsystem.
9316 **/
9317static int __init ixgbe_init_module(void)
9318{
9319 int ret;
c7689578 9320 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9321 pr_info("%s\n", ixgbe_copyright);
9a799d71 9322
00949167 9323 ixgbe_dbg_init();
00949167 9324
f01fc1a8
JK		 9325 ret = pci_register_driver(&ixgbe_driver);
9326 if (ret) {
f01fc1a8 9327 ixgbe_dbg_exit();
f01fc1a8
JK		 9328 return ret;
9329 }
9330
5dd2d332 9331#ifdef CONFIG_IXGBE_DCA
bd0362dd 9332 dca_register_notify(&dca_notifier);
bd0362dd 9333#endif
5dd2d332 9334
f01fc1a8 9335 return 0;
9a799d71 9336}
b4617240 9337
9a799d71
AK		 9338module_init(ixgbe_init_module);
9339
9340/**
9341 * ixgbe_exit_module - Driver Exit Cleanup Routine
9342 *
9343 * ixgbe_exit_module is called just before the driver is removed
9344 * from memory.
9345 **/
9346static void __exit ixgbe_exit_module(void)
9347{
5dd2d332 9348#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9349 dca_unregister_notify(&dca_notifier);
9350#endif
9a799d71 9351 pci_unregister_driver(&ixgbe_driver);
00949167 9352
00949167 9353 ixgbe_dbg_exit();
9a799d71 9354}
bd0362dd 9355
5dd2d332 9356#ifdef CONFIG_IXGBE_DCA
bd0362dd 9357static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9358 void *p)
bd0362dd
JC		 9359{
9360 int ret_val;
9361
9362 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9363 __ixgbe_notify_dca);
bd0362dd
JC		 9364
9365 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9366}
b453368d 9367
5dd2d332 9368#endif /* CONFIG_IXGBE_DCA */
849c4542 9369
9a799d71
AK		 9370module_exit(ixgbe_exit_module);
9371
9372/* ixgbe_main.c */
Linux kernel - Deliverables
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