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ixgbe: fix panic while dumping packets on Tx hang with IOMMU
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 58#ifdef IXGBE_FCOE
ea81875a
NP		 59char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 61#else
62static char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
64#endif
75e3d3c6 65#define MAJ 3
eef4560f
DS		 66#define MIN 9
67#define BUILD 15
75e3d3c6 68#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 69 __stringify(BUILD) "-k"
9c8eb720 70const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 71static const char ixgbe_copyright[] =
94971820 72 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 73
74static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 75 [board_82598] = &ixgbe_82598_info,
e8e26350 76 [board_82599] = &ixgbe_82599_info,
fe15e8e1 77 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 78};
79
80/* ixgbe_pci_tbl - PCI Device ID Table
81 *
82 * Wildcard entries (PCI_ANY_ID) should come last
83 * Last entry must be all 0s
84 *
85 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
86 * Class, Class Mask, private data (not used) }
87 */
a3aa1884 88static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 117 /* required last entry */
118 {0, }
119};
120MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
121
5dd2d332 122#ifdef CONFIG_IXGBE_DCA
bd0362dd 123static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 124 void *p);
bd0362dd
JC		 125static struct notifier_block dca_notifier = {
126 .notifier_call = ixgbe_notify_dca,
127 .next = NULL,
128 .priority = 0
129};
130#endif
131
1cdd1ec8
GR		 132#ifdef CONFIG_PCI_IOV
133static unsigned int max_vfs;
134module_param(max_vfs, uint, 0);
e8e9f696 135MODULE_PARM_DESC(max_vfs,
6b42a9c5 136 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 137#endif /* CONFIG_PCI_IOV */
138
8ef78adc
PWJ		 139static unsigned int allow_unsupported_sfp;
140module_param(allow_unsupported_sfp, uint, 0);
141MODULE_PARM_DESC(allow_unsupported_sfp,
142 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
143
b3f4d599 144#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
145static int debug = -1;
146module_param(debug, int, 0);
147MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
148
9a799d71
AK		 149MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
150MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
151MODULE_LICENSE("GPL");
152MODULE_VERSION(DRV_VERSION);
153
7086400d
AD		 154static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
155{
156 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
157 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
158 schedule_work(&adapter->service_task);
159}
160
161static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
162{
163 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
164
52f33af8 165 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 166 smp_mb__before_clear_bit();
167 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
168}
169
dcd79aeb
TI		 170struct ixgbe_reg_info {
171 u32 ofs;
172 char *name;
173};
174
175static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
176
177 /* General Registers */
178 {IXGBE_CTRL, "CTRL"},
179 {IXGBE_STATUS, "STATUS"},
180 {IXGBE_CTRL_EXT, "CTRL_EXT"},
181
182 /* Interrupt Registers */
183 {IXGBE_EICR, "EICR"},
184
185 /* RX Registers */
186 {IXGBE_SRRCTL(0), "SRRCTL"},
187 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
188 {IXGBE_RDLEN(0), "RDLEN"},
189 {IXGBE_RDH(0), "RDH"},
190 {IXGBE_RDT(0), "RDT"},
191 {IXGBE_RXDCTL(0), "RXDCTL"},
192 {IXGBE_RDBAL(0), "RDBAL"},
193 {IXGBE_RDBAH(0), "RDBAH"},
194
195 /* TX Registers */
196 {IXGBE_TDBAL(0), "TDBAL"},
197 {IXGBE_TDBAH(0), "TDBAH"},
198 {IXGBE_TDLEN(0), "TDLEN"},
199 {IXGBE_TDH(0), "TDH"},
200 {IXGBE_TDT(0), "TDT"},
201 {IXGBE_TXDCTL(0), "TXDCTL"},
202
203 /* List Terminator */
204 {}
205};
206
207
208/*
209 * ixgbe_regdump - register printout routine
210 */
211static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
212{
213 int i = 0, j = 0;
214 char rname[16];
215 u32 regs[64];
216
217 switch (reginfo->ofs) {
218 case IXGBE_SRRCTL(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
221 break;
222 case IXGBE_DCA_RXCTRL(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
225 break;
226 case IXGBE_RDLEN(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
229 break;
230 case IXGBE_RDH(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
233 break;
234 case IXGBE_RDT(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
237 break;
238 case IXGBE_RXDCTL(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
241 break;
242 case IXGBE_RDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
245 break;
246 case IXGBE_RDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
249 break;
250 case IXGBE_TDBAL(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
253 break;
254 case IXGBE_TDBAH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
257 break;
258 case IXGBE_TDLEN(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
261 break;
262 case IXGBE_TDH(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
265 break;
266 case IXGBE_TDT(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
269 break;
270 case IXGBE_TXDCTL(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
273 break;
274 default:
c7689578 275 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 276 IXGBE_READ_REG(hw, reginfo->ofs));
277 return;
278 }
279
280 for (i = 0; i < 8; i++) {
281 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 282 pr_err("%-15s", rname);
dcd79aeb 283 for (j = 0; j < 8; j++)
c7689578
JP		 284 pr_cont(" %08x", regs[i*8+j]);
285 pr_cont("\n");
dcd79aeb
TI		 286 }
287
288}
289
290/*
291 * ixgbe_dump - Print registers, tx-rings and rx-rings
292 */
293static void ixgbe_dump(struct ixgbe_adapter *adapter)
294{
295 struct net_device *netdev = adapter->netdev;
296 struct ixgbe_hw *hw = &adapter->hw;
297 struct ixgbe_reg_info *reginfo;
298 int n = 0;
299 struct ixgbe_ring *tx_ring;
729739b7 300 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 301 union ixgbe_adv_tx_desc *tx_desc;
302 struct my_u0 { u64 a; u64 b; } *u0;
303 struct ixgbe_ring *rx_ring;
304 union ixgbe_adv_rx_desc *rx_desc;
305 struct ixgbe_rx_buffer *rx_buffer_info;
306 u32 staterr;
307 int i = 0;
308
309 if (!netif_msg_hw(adapter))
310 return;
311
312 /* Print netdevice Info */
313 if (netdev) {
314 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 315 pr_info("Device Name state "
dcd79aeb 316 "trans_start last_rx\n");
c7689578
JP		 317 pr_info("%-15s %016lX %016lX %016lX\n",
318 netdev->name,
319 netdev->state,
320 netdev->trans_start,
321 netdev->last_rx);
dcd79aeb
TI		 322 }
323
324 /* Print Registers */
325 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 326 pr_info(" Register Name Value\n");
dcd79aeb
TI		 327 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
328 reginfo->name; reginfo++) {
329 ixgbe_regdump(hw, reginfo);
330 }
331
332 /* Print TX Ring Summary */
333 if (!netdev || !netif_running(netdev))
334 goto exit;
335
336 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 337 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 338 for (n = 0; n < adapter->num_tx_queues; n++) {
339 tx_ring = adapter->tx_ring[n];
729739b7 340 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 341 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb 342 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 343 (u64)dma_unmap_addr(tx_buffer, dma),
344 dma_unmap_len(tx_buffer, len),
345 tx_buffer->next_to_watch,
346 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 347 }
348
349 /* Print TX Rings */
350 if (!netif_msg_tx_done(adapter))
351 goto rx_ring_summary;
352
353 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
354
355 /* Transmit Descriptor Formats
356 *
357 * Advanced Transmit Descriptor
358 * +--------------------------------------------------------------+
359 * 0 | Buffer Address [63:0] |
360 * +--------------------------------------------------------------+
361 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
362 * +--------------------------------------------------------------+
363 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
364 */
365
366 for (n = 0; n < adapter->num_tx_queues; n++) {
367 tx_ring = adapter->tx_ring[n];
c7689578
JP		 368 pr_info("------------------------------------\n");
369 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
370 pr_info("------------------------------------\n");
371 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 372 "[PlPOIdStDDt Ln] [bi->dma ] "
373 "leng ntw timestamp bi->skb\n");
374
375 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 376 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 377 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 378 u0 = (struct my_u0 *)tx_desc;
c7689578 379 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 380 " %04X %p %016llX %p", i,
dcd79aeb
TI		 381 le64_to_cpu(u0->a),
382 le64_to_cpu(u0->b),
729739b7
AD		 383 (u64)dma_unmap_addr(tx_buffer, dma),
384 dma_unmap_len(tx_buffer, len),
385 tx_buffer->next_to_watch,
386 (u64)tx_buffer->time_stamp,
387 tx_buffer->skb);
dcd79aeb
TI		 388 if (i == tx_ring->next_to_use &&
389 i == tx_ring->next_to_clean)
c7689578 390 pr_cont(" NTC/U\n");
dcd79aeb 391 else if (i == tx_ring->next_to_use)
c7689578 392 pr_cont(" NTU\n");
dcd79aeb 393 else if (i == tx_ring->next_to_clean)
c7689578 394 pr_cont(" NTC\n");
dcd79aeb 395 else
c7689578 396 pr_cont("\n");
dcd79aeb
TI		 397
398 if (netif_msg_pktdata(adapter) &&
9c50c035 399 tx_buffer->skb)
dcd79aeb
TI		 400 print_hex_dump(KERN_INFO, "",
401 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035 402 tx_buffer->skb->data,
729739b7
AD		 403 dma_unmap_len(tx_buffer, len),
404 true);
dcd79aeb
TI		 405 }
406 }
407
408 /* Print RX Rings Summary */
409rx_ring_summary:
410 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 411 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 412 for (n = 0; n < adapter->num_rx_queues; n++) {
413 rx_ring = adapter->rx_ring[n];
c7689578
JP		 414 pr_info("%5d %5X %5X\n",
415 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 416 }
417
418 /* Print RX Rings */
419 if (!netif_msg_rx_status(adapter))
420 goto exit;
421
422 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
423
424 /* Advanced Receive Descriptor (Read) Format
425 * 63 1 0
426 * +-----------------------------------------------------+
427 * 0 | Packet Buffer Address [63:1] |A0/NSE|
428 * +----------------------------------------------+------+
429 * 8 | Header Buffer Address [63:1] | DD |
430 * +-----------------------------------------------------+
431 *
432 *
433 * Advanced Receive Descriptor (Write-Back) Format
434 *
435 * 63 48 47 32 31 30 21 20 16 15 4 3 0
436 * +------------------------------------------------------+
437 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
438 * | Checksum Ident | | | | Type | Type |
439 * +------------------------------------------------------+
440 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
441 * +------------------------------------------------------+
442 * 63 48 47 32 31 20 19 0
443 */
444 for (n = 0; n < adapter->num_rx_queues; n++) {
445 rx_ring = adapter->rx_ring[n];
c7689578
JP		 446 pr_info("------------------------------------\n");
447 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
448 pr_info("------------------------------------\n");
449 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 450 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
451 "<-- Adv Rx Read format\n");
c7689578 452 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 453 "[vl er S cks ln] ---------------- [bi->skb] "
454 "<-- Adv Rx Write-Back format\n");
455
456 for (i = 0; i < rx_ring->count; i++) {
457 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 458 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 459 u0 = (struct my_u0 *)rx_desc;
460 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
461 if (staterr & IXGBE_RXD_STAT_DD) {
462 /* Descriptor Done */
c7689578 463 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 464 "%016llX ---------------- %p", i,
465 le64_to_cpu(u0->a),
466 le64_to_cpu(u0->b),
467 rx_buffer_info->skb);
468 } else {
c7689578 469 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 470 "%016llX %016llX %p", i,
471 le64_to_cpu(u0->a),
472 le64_to_cpu(u0->b),
473 (u64)rx_buffer_info->dma,
474 rx_buffer_info->skb);
475
9c50c035
ET		 476 if (netif_msg_pktdata(adapter) &&
477 rx_buffer_info->dma) {
dcd79aeb
TI		 478 print_hex_dump(KERN_INFO, "",
479 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 480 page_address(rx_buffer_info->page) +
481 rx_buffer_info->page_offset,
f800326d 482 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
49ce9c2c 520/**
e8e26350
PW		 521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
729739b7
AD		 592void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
729739b7
AD		 595 if (tx_buffer->skb) {
596 dev_kfree_skb_any(tx_buffer->skb);
597 if (dma_unmap_len(tx_buffer, len))
d3d00239 598 dma_unmap_single(ring->dev,
729739b7
AD		 599 dma_unmap_addr(tx_buffer, dma),
600 dma_unmap_len(tx_buffer, len),
601 DMA_TO_DEVICE);
602 } else if (dma_unmap_len(tx_buffer, len)) {
603 dma_unmap_page(ring->dev,
604 dma_unmap_addr(tx_buffer, dma),
605 dma_unmap_len(tx_buffer, len),
606 DMA_TO_DEVICE);
e5a43549 607 }
729739b7
AD		 608 tx_buffer->next_to_watch = NULL;
609 tx_buffer->skb = NULL;
610 dma_unmap_len_set(tx_buffer, len, 0);
611 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 612}
613
943561d3 614static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 615{
616 struct ixgbe_hw *hw = &adapter->hw;
617 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 618 int i;
943561d3 619 u32 data;
c84d324c 620
943561d3
AD		 621 if ((hw->fc.current_mode != ixgbe_fc_full) &&
622 (hw->fc.current_mode != ixgbe_fc_rx_pause))
623 return;
c84d324c 624
943561d3
AD		 625 switch (hw->mac.type) {
626 case ixgbe_mac_82598EB:
627 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
628 break;
629 default:
630 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
631 }
632 hwstats->lxoffrxc += data;
c84d324c 633
943561d3
AD		 634 /* refill credits (no tx hang) if we received xoff */
635 if (!data)
c84d324c 636 return;
943561d3
AD		 637
638 for (i = 0; i < adapter->num_tx_queues; i++)
639 clear_bit(__IXGBE_HANG_CHECK_ARMED,
640 &adapter->tx_ring[i]->state);
641}
642
643static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
644{
645 struct ixgbe_hw *hw = &adapter->hw;
646 struct ixgbe_hw_stats *hwstats = &adapter->stats;
647 u32 xoff[8] = {0};
648 int i;
649 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
650
651 if (adapter->ixgbe_ieee_pfc)
652 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
653
654 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
655 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 656 return;
943561d3 657 }
c84d324c
JF		 658
659 /* update stats for each tc, only valid with PFC enabled */
660 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
661 switch (hw->mac.type) {
662 case ixgbe_mac_82598EB:
663 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 664 break;
c84d324c
JF		 665 default:
666 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 667 }
c84d324c
JF		 668 hwstats->pxoffrxc[i] += xoff[i];
669 }
670
671 /* disarm tx queues that have received xoff frames */
672 for (i = 0; i < adapter->num_tx_queues; i++) {
673 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 674 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 675
676 if (xoff[tc])
677 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 678 }
26f23d82
YZ		 679}
680
c84d324c 681static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 682{
7d7ce682 683 return ring->stats.packets;
c84d324c
JF		 684}
685
686static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
687{
688 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 689 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 690
c84d324c
JF		 691 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
692 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
693
694 if (head != tail)
695 return (head < tail) ?
696 tail - head : (tail + ring->count - head);
697
698 return 0;
699}
700
701static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
702{
703 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
704 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
705 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
706 bool ret = false;
707
7d637bcc 708 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 709
710 /*
711 * Check for a hung queue, but be thorough. This verifies
712 * that a transmit has been completed since the previous
713 * check AND there is at least one packet pending. The
714 * ARMED bit is set to indicate a potential hang. The
715 * bit is cleared if a pause frame is received to remove
716 * false hang detection due to PFC or 802.3x frames. By
717 * requiring this to fail twice we avoid races with
718 * pfc clearing the ARMED bit and conditions where we
719 * run the check_tx_hang logic with a transmit completion
720 * pending but without time to complete it yet.
721 */
722 if ((tx_done_old == tx_done) && tx_pending) {
723 /* make sure it is true for two checks in a row */
724 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
725 &tx_ring->state);
726 } else {
727 /* update completed stats and continue */
728 tx_ring->tx_stats.tx_done_old = tx_done;
729 /* reset the countdown */
730 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 731 }
732
c84d324c 733 return ret;
9a799d71
AK		 734}
735
c83c6cbd
AD		 736/**
737 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
738 * @adapter: driver private struct
739 **/
740static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
741{
742
743 /* Do the reset outside of interrupt context */
744 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
745 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
746 ixgbe_service_event_schedule(adapter);
747 }
748}
e01c31a5 749
9a799d71
AK		 750/**
751 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 752 * @q_vector: structure containing interrupt and ring information
e01c31a5 753 * @tx_ring: tx ring to clean
9a799d71 754 **/
fe49f04a 755static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 756 struct ixgbe_ring *tx_ring)
9a799d71 757{
fe49f04a 758 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 759 struct ixgbe_tx_buffer *tx_buffer;
760 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 761 unsigned int total_bytes = 0, total_packets = 0;
59224555 762 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 763 unsigned int i = tx_ring->next_to_clean;
764
765 if (test_bit(__IXGBE_DOWN, &adapter->state))
766 return true;
9a799d71 767
d3d00239 768 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 769 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 770 i -= tx_ring->count;
12207e49 771
729739b7 772 do {
d3d00239
AD		 773 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
774
775 /* if next_to_watch is not set then there is no work pending */
776 if (!eop_desc)
777 break;
778
7f83a9e6
AD		 779 /* prevent any other reads prior to eop_desc */
780 rmb();
781
d3d00239
AD		 782 /* if DD is not set pending work has not been completed */
783 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
784 break;
8ad494b0 785
d3d00239
AD		 786 /* clear next_to_watch to prevent false hangs */
787 tx_buffer->next_to_watch = NULL;
8ad494b0 788
091a6246
AD		 789 /* update the statistics for this packet */
790 total_bytes += tx_buffer->bytecount;
791 total_packets += tx_buffer->gso_segs;
792
3a6a4eda 793#ifdef CONFIG_IXGBE_PTP
0ede4a60
JK		 794 if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP))
795 ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb);
3a6a4eda 796#endif
0ede4a60 797
fd0db0ed
AD		 798 /* free the skb */
799 dev_kfree_skb_any(tx_buffer->skb);
800
729739b7
AD		 801 /* unmap skb header data */
802 dma_unmap_single(tx_ring->dev,
803 dma_unmap_addr(tx_buffer, dma),
804 dma_unmap_len(tx_buffer, len),
805 DMA_TO_DEVICE);
806
fd0db0ed
AD		 807 /* clear tx_buffer data */
808 tx_buffer->skb = NULL;
729739b7 809 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 810
729739b7
AD		 811 /* unmap remaining buffers */
812 while (tx_desc != eop_desc) {
d3d00239
AD		 813 tx_buffer++;
814 tx_desc++;
8ad494b0 815 i++;
729739b7
AD		 816 if (unlikely(!i)) {
817 i -= tx_ring->count;
d3d00239 818 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 819 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 820 }
e01c31a5 821
729739b7
AD		 822 /* unmap any remaining paged data */
823 if (dma_unmap_len(tx_buffer, len)) {
824 dma_unmap_page(tx_ring->dev,
825 dma_unmap_addr(tx_buffer, dma),
826 dma_unmap_len(tx_buffer, len),
827 DMA_TO_DEVICE);
828 dma_unmap_len_set(tx_buffer, len, 0);
829 }
830 }
831
832 /* move us one more past the eop_desc for start of next pkt */
833 tx_buffer++;
834 tx_desc++;
835 i++;
836 if (unlikely(!i)) {
837 i -= tx_ring->count;
838 tx_buffer = tx_ring->tx_buffer_info;
839 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
840 }
841
842 /* issue prefetch for next Tx descriptor */
843 prefetch(tx_desc);
12207e49 844
729739b7
AD		 845 /* update budget accounting */
846 budget--;
847 } while (likely(budget));
848
849 i += tx_ring->count;
9a799d71 850 tx_ring->next_to_clean = i;
d3d00239 851 u64_stats_update_begin(&tx_ring->syncp);
b953799e 852 tx_ring->stats.bytes += total_bytes;
bd198058 853 tx_ring->stats.packets += total_packets;
d3d00239 854 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 855 q_vector->tx.total_bytes += total_bytes;
856 q_vector->tx.total_packets += total_packets;
b953799e 857
c84d324c
JF		 858 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
859 /* schedule immediate reset if we believe we hung */
860 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 861 e_err(drv, "Detected Tx Unit Hang\n"
862 " Tx Queue <%d>\n"
863 " TDH, TDT <%x>, <%x>\n"
864 " next_to_use <%x>\n"
865 " next_to_clean <%x>\n"
866 "tx_buffer_info[next_to_clean]\n"
867 " time_stamp <%lx>\n"
868 " jiffies <%lx>\n",
869 tx_ring->queue_index,
870 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
871 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 872 tx_ring->next_to_use, i,
873 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 874
875 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
876
877 e_info(probe,
878 "tx hang %d detected on queue %d, resetting adapter\n",
879 adapter->tx_timeout_count + 1, tx_ring->queue_index);
880
b953799e 881 /* schedule immediate reset if we believe we hung */
c83c6cbd 882 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 883
884 /* the adapter is about to reset, no point in enabling stuff */
59224555 885 return true;
b953799e 886 }
9a799d71 887
b2d96e0a
AD		 888 netdev_tx_completed_queue(txring_txq(tx_ring),
889 total_packets, total_bytes);
890
e092be60 891#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 892 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 893 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 894 /* Make sure that anybody stopping the queue after this
895 * sees the new next_to_clean.
896 */
897 smp_mb();
729739b7
AD		 898 if (__netif_subqueue_stopped(tx_ring->netdev,
899 tx_ring->queue_index)
900 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
901 netif_wake_subqueue(tx_ring->netdev,
902 tx_ring->queue_index);
5b7da515 903 ++tx_ring->tx_stats.restart_queue;
30eba97a 904 }
e092be60 905 }
9a799d71 906
59224555 907 return !!budget;
9a799d71
AK		 908}
909
5dd2d332 910#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 911static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
912 struct ixgbe_ring *tx_ring,
33cf09c9 913 int cpu)
bd0362dd 914{
33cf09c9 915 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 916 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
917 u16 reg_offset;
33cf09c9 918
33cf09c9
AD		 919 switch (hw->mac.type) {
920 case ixgbe_mac_82598EB:
bdda1a61 921 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 922 break;
923 case ixgbe_mac_82599EB:
b93a2226 924 case ixgbe_mac_X540:
bdda1a61
AD		 925 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
926 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 927 break;
928 default:
bdda1a61
AD		 929 /* for unknown hardware do not write register */
930 return;
bd0362dd 931 }
bdda1a61
AD		 932
933 /*
934 * We can enable relaxed ordering for reads, but not writes when
935 * DCA is enabled. This is due to a known issue in some chipsets
936 * which will cause the DCA tag to be cleared.
937 */
938 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
939 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
940 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
941
942 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 943}
944
bdda1a61
AD		 945static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
946 struct ixgbe_ring *rx_ring,
33cf09c9 947 int cpu)
bd0362dd 948{
33cf09c9 949 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 950 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
951 u8 reg_idx = rx_ring->reg_idx;
952
33cf09c9
AD		 953
954 switch (hw->mac.type) {
33cf09c9 955 case ixgbe_mac_82599EB:
b93a2226 956 case ixgbe_mac_X540:
bdda1a61 957 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 958 break;
959 default:
960 break;
961 }
bdda1a61
AD		 962
963 /*
964 * We can enable relaxed ordering for reads, but not writes when
965 * DCA is enabled. This is due to a known issue in some chipsets
966 * which will cause the DCA tag to be cleared.
967 */
968 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
969 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
970 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
971
972 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 973}
974
975static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
976{
977 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 978 struct ixgbe_ring *ring;
bd0362dd 979 int cpu = get_cpu();
bd0362dd 980
33cf09c9
AD		 981 if (q_vector->cpu == cpu)
982 goto out_no_update;
983
a557928e 984 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 985 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 986
a557928e 987 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 988 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 989
990 q_vector->cpu = cpu;
991out_no_update:
bd0362dd
JC		 992 put_cpu();
993}
994
995static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
996{
997 int i;
998
999 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1000 return;
1001
e35ec126
AD		 1002 /* always use CB2 mode, difference is masked in the CB driver */
1003 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1004
49c7ffbe 1005 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1006 adapter->q_vector[i]->cpu = -1;
1007 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1008 }
1009}
1010
1011static int __ixgbe_notify_dca(struct device *dev, void *data)
1012{
c60fbb00 1013 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1014 unsigned long event = *(unsigned long *)data;
1015
2a72c31e 1016 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1017 return 0;
1018
bd0362dd
JC		 1019 switch (event) {
1020 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1021 /* if we're already enabled, don't do it again */
1022 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1023 break;
652f093f 1024 if (dca_add_requester(dev) == 0) {
96b0e0f6 1025 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1026 ixgbe_setup_dca(adapter);
1027 break;
1028 }
1029 /* Fall Through since DCA is disabled. */
1030 case DCA_PROVIDER_REMOVE:
1031 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1032 dca_remove_requester(dev);
1033 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1035 }
1036 break;
1037 }
1038
652f093f 1039 return 0;
bd0362dd 1040}
67a74ee2 1041
bdda1a61 1042#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1043static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1044 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1045 struct sk_buff *skb)
1046{
8a0da21b
AD		 1047 if (ring->netdev->features & NETIF_F_RXHASH)
1048 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1049}
1050
f800326d 1051#ifdef IXGBE_FCOE
ff886dfc
AD		 1052/**
1053 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1054 * @ring: structure containing ring specific data
ff886dfc
AD		 1055 * @rx_desc: advanced rx descriptor
1056 *
1057 * Returns : true if it is FCoE pkt
1058 */
57efd44c 1059static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1060 union ixgbe_adv_rx_desc *rx_desc)
1061{
1062 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1063
57efd44c 1064 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1065 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1066 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1067 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1068}
1069
f800326d 1070#endif /* IXGBE_FCOE */
e59bd25d
AV		 1071/**
1072 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1073 * @ring: structure containing ring specific data
1074 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1075 * @skb: skb currently being received and modified
1076 **/
8a0da21b 1077static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1078 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1079 struct sk_buff *skb)
9a799d71 1080{
8a0da21b 1081 skb_checksum_none_assert(skb);
9a799d71 1082
712744be 1083 /* Rx csum disabled */
8a0da21b 1084 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1085 return;
e59bd25d
AV		 1086
1087 /* if IP and error */
f56e0cb1
AD		 1088 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1089 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1090 ring->rx_stats.csum_err++;
9a799d71
AK		 1091 return;
1092 }
e59bd25d 1093
f56e0cb1 1094 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1095 return;
1096
f56e0cb1 1097 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1098 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1099
1100 /*
1101 * 82599 errata, UDP frames with a 0 checksum can be marked as
1102 * checksum errors.
1103 */
8a0da21b
AD		 1104 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1105 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1106 return;
1107
8a0da21b 1108 ring->rx_stats.csum_err++;
e59bd25d
AV		 1109 return;
1110 }
1111
9a799d71 1112 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1113 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1114}
1115
84ea2591 1116static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1117{
f56e0cb1 1118 rx_ring->next_to_use = val;
f800326d
AD		 1119
1120 /* update next to alloc since we have filled the ring */
1121 rx_ring->next_to_alloc = val;
e8e26350
PW		 1122 /*
1123 * Force memory writes to complete before letting h/w
1124 * know there are new descriptors to fetch. (Only
1125 * applicable for weak-ordered memory model archs,
1126 * such as IA-64).
1127 */
1128 wmb();
84ea2591 1129 writel(val, rx_ring->tail);
e8e26350
PW		 1130}
1131
f990b79b
AD		 1132static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1133 struct ixgbe_rx_buffer *bi)
1134{
1135 struct page *page = bi->page;
f800326d 1136 dma_addr_t dma = bi->dma;
f990b79b 1137
f800326d
AD		 1138 /* since we are recycling buffers we should seldom need to alloc */
1139 if (likely(dma))
f990b79b
AD		 1140 return true;
1141
f800326d
AD		 1142 /* alloc new page for storage */
1143 if (likely(!page)) {
8633c084 1144 page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
f800326d 1145 ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1146 if (unlikely(!page)) {
1147 rx_ring->rx_stats.alloc_rx_page_failed++;
1148 return false;
1149 }
f800326d 1150 bi->page = page;
f990b79b
AD		 1151 }
1152
f800326d
AD		 1153 /* map page for use */
1154 dma = dma_map_page(rx_ring->dev, page, 0,
1155 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1156
1157 /*
1158 * if mapping failed free memory back to system since
1159 * there isn't much point in holding memory we can't use
1160 */
1161 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1162 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1163 bi->page = NULL;
f990b79b 1164
f990b79b
AD		 1165 rx_ring->rx_stats.alloc_rx_page_failed++;
1166 return false;
1167 }
1168
f800326d
AD		 1169 bi->dma = dma;
1170 bi->page_offset ^= ixgbe_rx_bufsz(rx_ring);
1171
f990b79b
AD		 1172 return true;
1173}
1174
9a799d71 1175/**
f990b79b 1176 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1177 * @rx_ring: ring to place buffers on
1178 * @cleaned_count: number of buffers to replace
9a799d71 1179 **/
fc77dc3c 1180void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1181{
9a799d71 1182 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1183 struct ixgbe_rx_buffer *bi;
d5f398ed 1184 u16 i = rx_ring->next_to_use;
9a799d71 1185
f800326d
AD		 1186 /* nothing to do */
1187 if (!cleaned_count)
fc77dc3c
AD		 1188 return;
1189
e4f74028 1190 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1191 bi = &rx_ring->rx_buffer_info[i];
1192 i -= rx_ring->count;
9a799d71 1193
f800326d
AD		 1194 do {
1195 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1196 break;
d5f398ed 1197
f800326d
AD		 1198 /*
1199 * Refresh the desc even if buffer_addrs didn't change
1200 * because each write-back erases this info.
1201 */
1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1203
f990b79b
AD		 1204 rx_desc++;
1205 bi++;
9a799d71 1206 i++;
f990b79b 1207 if (unlikely(!i)) {
e4f74028 1208 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1209 bi = rx_ring->rx_buffer_info;
1210 i -= rx_ring->count;
1211 }
1212
1213 /* clear the hdr_addr for the next_to_use descriptor */
1214 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1215
1216 cleaned_count--;
1217 } while (cleaned_count);
7c6e0a43 1218
f990b79b
AD		 1219 i += rx_ring->count;
1220
f56e0cb1 1221 if (rx_ring->next_to_use != i)
84ea2591 1222 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1223}
1224
1d2024f6
AD		 1225/**
1226 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1227 * @data: pointer to the start of the headers
1228 * @max_len: total length of section to find headers in
1229 *
1230 * This function is meant to determine the length of headers that will
1231 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1232 * motivation of doing this is to only perform one pull for IPv4 TCP
1233 * packets so that we can do basic things like calculating the gso_size
1234 * based on the average data per packet.
1235 **/
1236static unsigned int ixgbe_get_headlen(unsigned char *data,
1237 unsigned int max_len)
1238{
1239 union {
1240 unsigned char *network;
1241 /* l2 headers */
1242 struct ethhdr *eth;
1243 struct vlan_hdr *vlan;
1244 /* l3 headers */
1245 struct iphdr *ipv4;
1246 } hdr;
1247 __be16 protocol;
1248 u8 nexthdr = 0; /* default to not TCP */
1249 u8 hlen;
1250
1251 /* this should never happen, but better safe than sorry */
1252 if (max_len < ETH_HLEN)
1253 return max_len;
1254
1255 /* initialize network frame pointer */
1256 hdr.network = data;
1257
1258 /* set first protocol and move network header forward */
1259 protocol = hdr.eth->h_proto;
1260 hdr.network += ETH_HLEN;
1261
1262 /* handle any vlan tag if present */
1263 if (protocol == __constant_htons(ETH_P_8021Q)) {
1264 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1265 return max_len;
1266
1267 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1268 hdr.network += VLAN_HLEN;
1269 }
1270
1271 /* handle L3 protocols */
1272 if (protocol == __constant_htons(ETH_P_IP)) {
1273 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1274 return max_len;
1275
1276 /* access ihl as a u8 to avoid unaligned access on ia64 */
1277 hlen = (hdr.network[0] & 0x0F) << 2;
1278
1279 /* verify hlen meets minimum size requirements */
1280 if (hlen < sizeof(struct iphdr))
1281 return hdr.network - data;
1282
1283 /* record next protocol */
1284 nexthdr = hdr.ipv4->protocol;
1285 hdr.network += hlen;
f800326d 1286#ifdef IXGBE_FCOE
1d2024f6
AD		 1287 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1288 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1289 return max_len;
1290 hdr.network += FCOE_HEADER_LEN;
1291#endif
1292 } else {
1293 return hdr.network - data;
1294 }
1295
1296 /* finally sort out TCP */
1297 if (nexthdr == IPPROTO_TCP) {
1298 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1299 return max_len;
1300
1301 /* access doff as a u8 to avoid unaligned access on ia64 */
1302 hlen = (hdr.network[12] & 0xF0) >> 2;
1303
1304 /* verify hlen meets minimum size requirements */
1305 if (hlen < sizeof(struct tcphdr))
1306 return hdr.network - data;
1307
1308 hdr.network += hlen;
1309 }
1310
1311 /*
1312 * If everything has gone correctly hdr.network should be the
1313 * data section of the packet and will be the end of the header.
1314 * If not then it probably represents the end of the last recognized
1315 * header.
1316 */
1317 if ((hdr.network - data) < max_len)
1318 return hdr.network - data;
1319 else
1320 return max_len;
1321}
1322
4c1975d7
AD		 1323static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1324 union ixgbe_adv_rx_desc *rx_desc,
1325 struct sk_buff *skb)
aa80175a 1326{
4c1975d7
AD		 1327 __le32 rsc_enabled;
1328 u32 rsc_cnt;
1329
1330 if (!ring_is_rsc_enabled(rx_ring))
1331 return;
1332
1333 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1334 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1335
1336 /* If this is an RSC frame rsc_cnt should be non-zero */
1337 if (!rsc_enabled)
1338 return;
1339
1340 rsc_cnt = le32_to_cpu(rsc_enabled);
1341 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1342
1343 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1344}
43634e82 1345
1d2024f6
AD		 1346static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1347 struct sk_buff *skb)
1348{
f800326d 1349 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1350
1351 /* set gso_size to avoid messing up TCP MSS */
1352 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1353 IXGBE_CB(skb)->append_cnt);
1354}
1355
1356static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1357 struct sk_buff *skb)
1358{
1359 /* if append_cnt is 0 then frame is not RSC */
1360 if (!IXGBE_CB(skb)->append_cnt)
1361 return;
1362
1363 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1364 rx_ring->rx_stats.rsc_flush++;
1365
1366 ixgbe_set_rsc_gso_size(rx_ring, skb);
1367
1368 /* gso_size is computed using append_cnt so always clear it last */
1369 IXGBE_CB(skb)->append_cnt = 0;
1370}
1371
8a0da21b
AD		 1372/**
1373 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1374 * @rx_ring: rx descriptor ring packet is being transacted on
1375 * @rx_desc: pointer to the EOP Rx descriptor
1376 * @skb: pointer to current skb being populated
f8212f97 1377 *
8a0da21b
AD		 1378 * This function checks the ring, descriptor, and packet information in
1379 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1380 * other fields within the skb.
f8212f97 1381 **/
8a0da21b
AD		 1382static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1383 union ixgbe_adv_rx_desc *rx_desc,
1384 struct sk_buff *skb)
f8212f97 1385{
43e95f11
JF		 1386 struct net_device *dev = rx_ring->netdev;
1387
8a0da21b
AD		 1388 ixgbe_update_rsc_stats(rx_ring, skb);
1389
1390 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1391
8a0da21b
AD		 1392 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1393
3a6a4eda 1394#ifdef CONFIG_IXGBE_PTP
1d1a79b5 1395 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb);
3a6a4eda
JK		 1396#endif
1397
43e95f11
JF		 1398 if ((dev->features & NETIF_F_HW_VLAN_RX) &&
1399 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b
AD		 1400 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1401 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1402 }
1403
8a0da21b 1404 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1405
43e95f11 1406 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1407}
1408
8a0da21b
AD		 1409static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1410 struct sk_buff *skb)
aa80175a 1411{
8a0da21b
AD		 1412 struct ixgbe_adapter *adapter = q_vector->adapter;
1413
1414 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1415 napi_gro_receive(&q_vector->napi, skb);
1416 else
1417 netif_rx(skb);
aa80175a 1418}
43634e82 1419
f800326d
AD		 1420/**
1421 * ixgbe_is_non_eop - process handling of non-EOP buffers
1422 * @rx_ring: Rx ring being processed
1423 * @rx_desc: Rx descriptor for current buffer
1424 * @skb: Current socket buffer containing buffer in progress
1425 *
1426 * This function updates next to clean. If the buffer is an EOP buffer
1427 * this function exits returning false, otherwise it will place the
1428 * sk_buff in the next buffer to be chained and return true indicating
1429 * that this is in fact a non-EOP buffer.
1430 **/
1431static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1432 union ixgbe_adv_rx_desc *rx_desc,
1433 struct sk_buff *skb)
1434{
1435 u32 ntc = rx_ring->next_to_clean + 1;
1436
1437 /* fetch, update, and store next to clean */
1438 ntc = (ntc < rx_ring->count) ? ntc : 0;
1439 rx_ring->next_to_clean = ntc;
1440
1441 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1442
1443 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1444 return false;
1445
1446 /* append_cnt indicates packet is RSC, if so fetch nextp */
1447 if (IXGBE_CB(skb)->append_cnt) {
1448 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1449 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1450 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1451 }
1452
1453 /* place skb in next buffer to be received */
1454 rx_ring->rx_buffer_info[ntc].skb = skb;
1455 rx_ring->rx_stats.non_eop_descs++;
1456
1457 return true;
1458}
1459
1460/**
1461 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1462 * @rx_ring: rx descriptor ring packet is being transacted on
1463 * @rx_desc: pointer to the EOP Rx descriptor
1464 * @skb: pointer to current skb being fixed
1465 *
1466 * Check for corrupted packet headers caused by senders on the local L2
1467 * embedded NIC switch not setting up their Tx Descriptors right. These
1468 * should be very rare.
1469 *
1470 * Also address the case where we are pulling data in on pages only
1471 * and as such no data is present in the skb header.
1472 *
1473 * In addition if skb is not at least 60 bytes we need to pad it so that
1474 * it is large enough to qualify as a valid Ethernet frame.
1475 *
1476 * Returns true if an error was encountered and skb was freed.
1477 **/
1478static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1479 union ixgbe_adv_rx_desc *rx_desc,
1480 struct sk_buff *skb)
1481{
1482 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1483 struct net_device *netdev = rx_ring->netdev;
1484 unsigned char *va;
1485 unsigned int pull_len;
1486
1487 /* if the page was released unmap it, else just sync our portion */
1488 if (unlikely(IXGBE_CB(skb)->page_released)) {
1489 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1490 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1491 IXGBE_CB(skb)->page_released = false;
1492 } else {
1493 dma_sync_single_range_for_cpu(rx_ring->dev,
1494 IXGBE_CB(skb)->dma,
1495 frag->page_offset,
1496 ixgbe_rx_bufsz(rx_ring),
1497 DMA_FROM_DEVICE);
1498 }
1499 IXGBE_CB(skb)->dma = 0;
1500
1501 /* verify that the packet does not have any known errors */
1502 if (unlikely(ixgbe_test_staterr(rx_desc,
1503 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1504 !(netdev->features & NETIF_F_RXALL))) {
1505 dev_kfree_skb_any(skb);
1506 return true;
1507 }
1508
1509 /*
1510 * it is valid to use page_address instead of kmap since we are
1511 * working with pages allocated out of the lomem pool per
1512 * alloc_page(GFP_ATOMIC)
1513 */
1514 va = skb_frag_address(frag);
1515
1516 /*
1517 * we need the header to contain the greater of either ETH_HLEN or
1518 * 60 bytes if the skb->len is less than 60 for skb_pad.
1519 */
1520 pull_len = skb_frag_size(frag);
252562c2
AD		 1521 if (pull_len > IXGBE_RX_HDR_SIZE)
1522 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
f800326d
AD		 1523
1524 /* align pull length to size of long to optimize memcpy performance */
1525 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1526
1527 /* update all of the pointers */
1528 skb_frag_size_sub(frag, pull_len);
1529 frag->page_offset += pull_len;
1530 skb->data_len -= pull_len;
1531 skb->tail += pull_len;
1532
1533 /*
1534 * if we sucked the frag empty then we should free it,
1535 * if there are other frags here something is screwed up in hardware
1536 */
1537 if (skb_frag_size(frag) == 0) {
1538 BUG_ON(skb_shinfo(skb)->nr_frags != 1);
1539 skb_shinfo(skb)->nr_frags = 0;
1540 __skb_frag_unref(frag);
1541 skb->truesize -= ixgbe_rx_bufsz(rx_ring);
1542 }
1543
57efd44c
AD		 1544#ifdef IXGBE_FCOE
1545 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1546 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1547 return false;
1548
1549#endif
f800326d
AD		 1550 /* if skb_pad returns an error the skb was freed */
1551 if (unlikely(skb->len < 60)) {
1552 int pad_len = 60 - skb->len;
1553
1554 if (skb_pad(skb, pad_len))
1555 return true;
1556 __skb_put(skb, pad_len);
1557 }
1558
1559 return false;
1560}
1561
1562/**
1563 * ixgbe_can_reuse_page - determine if we can reuse a page
1564 * @rx_buffer: pointer to rx_buffer containing the page we want to reuse
1565 *
1566 * Returns true if page can be reused in another Rx buffer
1567 **/
1568static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer)
1569{
1570 struct page *page = rx_buffer->page;
1571
1572 /* if we are only owner of page and it is local we can reuse it */
1573 return likely(page_count(page) == 1) &&
1574 likely(page_to_nid(page) == numa_node_id());
1575}
1576
1577/**
1578 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1579 * @rx_ring: rx descriptor ring to store buffers on
1580 * @old_buff: donor buffer to have page reused
1581 *
1582 * Syncronizes page for reuse by the adapter
1583 **/
1584static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1585 struct ixgbe_rx_buffer *old_buff)
1586{
1587 struct ixgbe_rx_buffer *new_buff;
1588 u16 nta = rx_ring->next_to_alloc;
1589 u16 bufsz = ixgbe_rx_bufsz(rx_ring);
1590
1591 new_buff = &rx_ring->rx_buffer_info[nta];
1592
1593 /* update, and store next to alloc */
1594 nta++;
1595 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1596
1597 /* transfer page from old buffer to new buffer */
1598 new_buff->page = old_buff->page;
1599 new_buff->dma = old_buff->dma;
1600
1601 /* flip page offset to other buffer and store to new_buff */
1602 new_buff->page_offset = old_buff->page_offset ^ bufsz;
1603
1604 /* sync the buffer for use by the device */
1605 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
1606 new_buff->page_offset, bufsz,
1607 DMA_FROM_DEVICE);
1608
1609 /* bump ref count on page before it is given to the stack */
1610 get_page(new_buff->page);
1611}
1612
1613/**
1614 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1615 * @rx_ring: rx descriptor ring to transact packets on
1616 * @rx_buffer: buffer containing page to add
1617 * @rx_desc: descriptor containing length of buffer written by hardware
1618 * @skb: sk_buff to place the data into
1619 *
1620 * This function is based on skb_add_rx_frag. I would have used that
1621 * function however it doesn't handle the truesize case correctly since we
1622 * are allocating more memory than might be used for a single receive.
1623 **/
1624static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
1625 struct ixgbe_rx_buffer *rx_buffer,
1626 struct sk_buff *skb, int size)
1627{
1628 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1629 rx_buffer->page, rx_buffer->page_offset,
1630 size);
1631 skb->len += size;
1632 skb->data_len += size;
1633 skb->truesize += ixgbe_rx_bufsz(rx_ring);
1634}
1635
1636/**
1637 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1638 * @q_vector: structure containing interrupt and ring information
1639 * @rx_ring: rx descriptor ring to transact packets on
1640 * @budget: Total limit on number of packets to process
1641 *
1642 * This function provides a "bounce buffer" approach to Rx interrupt
1643 * processing. The advantage to this is that on systems that have
1644 * expensive overhead for IOMMU access this provides a means of avoiding
1645 * it by maintaining the mapping of the page to the syste.
1646 *
1647 * Returns true if all work is completed without reaching budget
1648 **/
4ff7fb12 1649static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1650 struct ixgbe_ring *rx_ring,
4ff7fb12 1651 int budget)
9a799d71 1652{
d2f4fbe2 1653 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1654#ifdef IXGBE_FCOE
f800326d 1655 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1656 int ddp_bytes = 0;
1657#endif /* IXGBE_FCOE */
f800326d 1658 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1659
f800326d
AD		 1660 do {
1661 struct ixgbe_rx_buffer *rx_buffer;
1662 union ixgbe_adv_rx_desc *rx_desc;
1663 struct sk_buff *skb;
1664 struct page *page;
1665 u16 ntc;
1666
1667 /* return some buffers to hardware, one at a time is too slow */
1668 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1669 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1670 cleaned_count = 0;
1671 }
1672
1673 ntc = rx_ring->next_to_clean;
1674 rx_desc = IXGBE_RX_DESC(rx_ring, ntc);
1675 rx_buffer = &rx_ring->rx_buffer_info[ntc];
1676
1677 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
1678 break;
9a799d71 1679
f800326d
AD		 1680 /*
1681 * This memory barrier is needed to keep us from reading
1682 * any other fields out of the rx_desc until we know the
1683 * RXD_STAT_DD bit is set
1684 */
1685 rmb();
9a799d71 1686
f800326d
AD		 1687 page = rx_buffer->page;
1688 prefetchw(page);
9a799d71 1689
f800326d 1690 skb = rx_buffer->skb;
c267fc16 1691
f800326d
AD		 1692 if (likely(!skb)) {
1693 void *page_addr = page_address(page) +
1694 rx_buffer->page_offset;
9a799d71 1695
f800326d
AD		 1696 /* prefetch first cache line of first page */
1697 prefetch(page_addr);
1698#if L1_CACHE_BYTES < 128
1699 prefetch(page_addr + L1_CACHE_BYTES);
1700#endif
1701
1702 /* allocate a skb to store the frags */
1703 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1704 IXGBE_RX_HDR_SIZE);
1705 if (unlikely(!skb)) {
1706 rx_ring->rx_stats.alloc_rx_buff_failed++;
1707 break;
c267fc16
AD		 1708 }
1709
f800326d
AD		 1710 /*
1711 * we will be copying header into skb->data in
1712 * pskb_may_pull so it is in our interest to prefetch
1713 * it now to avoid a possible cache miss
1714 */
1715 prefetchw(skb->data);
4c1975d7
AD		 1716
1717 /*
1718 * Delay unmapping of the first packet. It carries the
1719 * header information, HW may still access the header
f800326d
AD		 1720 * after the writeback. Only unmap it when EOP is
1721 * reached
4c1975d7 1722 */
f800326d 1723 IXGBE_CB(skb)->dma = rx_buffer->dma;
c267fc16 1724 } else {
f800326d
AD		 1725 /* we are reusing so sync this buffer for CPU use */
1726 dma_sync_single_range_for_cpu(rx_ring->dev,
1727 rx_buffer->dma,
1728 rx_buffer->page_offset,
1729 ixgbe_rx_bufsz(rx_ring),
1730 DMA_FROM_DEVICE);
9a799d71
AK		 1731 }
1732
f800326d
AD		 1733 /* pull page into skb */
1734 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb,
1735 le16_to_cpu(rx_desc->wb.upper.length));
9a799d71 1736
f800326d
AD		 1737 if (ixgbe_can_reuse_page(rx_buffer)) {
1738 /* hand second half of page back to the ring */
1739 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1740 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1741 /* the page has been released from the ring */
1742 IXGBE_CB(skb)->page_released = true;
1743 } else {
1744 /* we are not reusing the buffer so unmap it */
1745 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1746 ixgbe_rx_pg_size(rx_ring),
1747 DMA_FROM_DEVICE);
9a799d71
AK		 1748 }
1749
f800326d
AD		 1750 /* clear contents of buffer_info */
1751 rx_buffer->skb = NULL;
1752 rx_buffer->dma = 0;
1753 rx_buffer->page = NULL;
4c1975d7 1754
f800326d 1755 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
9a799d71 1756
9a799d71 1757 cleaned_count++;
f8212f97 1758
f800326d
AD		 1759 /* place incomplete frames back on ring for completion */
1760 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
1761 continue;
c267fc16 1762
f800326d
AD		 1763 /* verify the packet layout is correct */
1764 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
1765 continue;
9a799d71 1766
d2f4fbe2
AV		 1767 /* probably a little skewed due to removing CRC */
1768 total_rx_bytes += skb->len;
1769 total_rx_packets++;
1770
8a0da21b
AD		 1771 /* populate checksum, timestamp, VLAN, and protocol */
1772 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1773
332d4a7d
YZ		 1774#ifdef IXGBE_FCOE
1775 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 1776 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 1777 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1778 if (!ddp_bytes) {
1779 dev_kfree_skb_any(skb);
f800326d 1780 continue;
63d635b2 1781 }
3d8fd385 1782 }
f800326d 1783
332d4a7d 1784#endif /* IXGBE_FCOE */
8a0da21b 1785 ixgbe_rx_skb(q_vector, skb);
9a799d71 1786
f800326d 1787 /* update budget accounting */
4ff7fb12 1788 budget--;
f800326d 1789 } while (likely(budget));
9a799d71 1790
3d8fd385
YZ		 1791#ifdef IXGBE_FCOE
1792 /* include DDPed FCoE data */
1793 if (ddp_bytes > 0) {
1794 unsigned int mss;
1795
fc77dc3c 1796 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1797 sizeof(struct fc_frame_header) -
1798 sizeof(struct fcoe_crc_eof);
1799 if (mss > 512)
1800 mss &= ~511;
1801 total_rx_bytes += ddp_bytes;
1802 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1803 }
3d8fd385 1804
f800326d 1805#endif /* IXGBE_FCOE */
c267fc16
AD		 1806 u64_stats_update_begin(&rx_ring->syncp);
1807 rx_ring->stats.packets += total_rx_packets;
1808 rx_ring->stats.bytes += total_rx_bytes;
1809 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1810 q_vector->rx.total_packets += total_rx_packets;
1811 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 1812
f800326d
AD		 1813 if (cleaned_count)
1814 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1815
4ff7fb12 1816 return !!budget;
9a799d71
AK		 1817}
1818
9a799d71
AK		 1819/**
1820 * ixgbe_configure_msix - Configure MSI-X hardware
1821 * @adapter: board private structure
1822 *
1823 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1824 * interrupts.
1825 **/
1826static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1827{
021230d4 1828 struct ixgbe_q_vector *q_vector;
49c7ffbe 1829 int v_idx;
021230d4 1830 u32 mask;
9a799d71 1831
8e34d1aa
AD		 1832 /* Populate MSIX to EITR Select */
1833 if (adapter->num_vfs > 32) {
1834 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1835 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1836 }
1837
4df10466
JB		 1838 /*
1839 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1840 * corresponding register.
1841 */
49c7ffbe 1842 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 1843 struct ixgbe_ring *ring;
7a921c93 1844 q_vector = adapter->q_vector[v_idx];
021230d4 1845
a557928e 1846 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 1847 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1848
a557928e 1849 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 1850 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1851
d5bf4f67
ET		 1852 if (q_vector->tx.ring && !q_vector->rx.ring) {
1853 /* tx only vector */
1854 if (adapter->tx_itr_setting == 1)
1855 q_vector->itr = IXGBE_10K_ITR;
1856 else
1857 q_vector->itr = adapter->tx_itr_setting;
1858 } else {
1859 /* rx or rx/tx vector */
1860 if (adapter->rx_itr_setting == 1)
1861 q_vector->itr = IXGBE_20K_ITR;
1862 else
1863 q_vector->itr = adapter->rx_itr_setting;
1864 }
021230d4 1865
fe49f04a 1866 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1867 }
1868
bd508178
AD		 1869 switch (adapter->hw.mac.type) {
1870 case ixgbe_mac_82598EB:
e8e26350 1871 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1872 v_idx);
bd508178
AD		 1873 break;
1874 case ixgbe_mac_82599EB:
b93a2226 1875 case ixgbe_mac_X540:
e8e26350 1876 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1877 break;
bd508178
AD		 1878 default:
1879 break;
1880 }
021230d4
AV		 1881 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1882
41fb9248 1883 /* set up to autoclear timer, and the vectors */
021230d4 1884 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1885 mask &= ~(IXGBE_EIMS_OTHER |
1886 IXGBE_EIMS_MAILBOX |
1887 IXGBE_EIMS_LSC);
1888
021230d4 1889 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1890}
1891
f494e8fa
AV		 1892enum latency_range {
1893 lowest_latency = 0,
1894 low_latency = 1,
1895 bulk_latency = 2,
1896 latency_invalid = 255
1897};
1898
1899/**
1900 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1901 * @q_vector: structure containing interrupt and ring information
1902 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1903 *
1904 * Stores a new ITR value based on packets and byte
1905 * counts during the last interrupt. The advantage of per interrupt
1906 * computation is faster updates and more accurate ITR for the current
1907 * traffic pattern. Constants in this function were computed
1908 * based on theoretical maximum wire speed and thresholds were set based
1909 * on testing data as well as attempting to minimize response time
1910 * while increasing bulk throughput.
1911 * this functionality is controlled by the InterruptThrottleRate module
1912 * parameter (see ixgbe_param.c)
1913 **/
bd198058
AD		 1914static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1915 struct ixgbe_ring_container *ring_container)
f494e8fa 1916{
bd198058
AD		 1917 int bytes = ring_container->total_bytes;
1918 int packets = ring_container->total_packets;
1919 u32 timepassed_us;
621bd70e 1920 u64 bytes_perint;
bd198058 1921 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1922
1923 if (packets == 0)
bd198058 1924 return;
f494e8fa
AV		 1925
1926 /* simple throttlerate management
621bd70e
AD		 1927 * 0-10MB/s lowest (100000 ints/s)
1928 * 10-20MB/s low (20000 ints/s)
1929 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 1930 */
1931 /* what was last interrupt timeslice? */
d5bf4f67 1932 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1933 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1934
1935 switch (itr_setting) {
1936 case lowest_latency:
621bd70e 1937 if (bytes_perint > 10)
bd198058 1938 itr_setting = low_latency;
f494e8fa
AV		 1939 break;
1940 case low_latency:
621bd70e 1941 if (bytes_perint > 20)
bd198058 1942 itr_setting = bulk_latency;
621bd70e 1943 else if (bytes_perint <= 10)
bd198058 1944 itr_setting = lowest_latency;
f494e8fa
AV		 1945 break;
1946 case bulk_latency:
621bd70e 1947 if (bytes_perint <= 20)
bd198058 1948 itr_setting = low_latency;
f494e8fa
AV		 1949 break;
1950 }
1951
bd198058
AD		 1952 /* clear work counters since we have the values we need */
1953 ring_container->total_bytes = 0;
1954 ring_container->total_packets = 0;
1955
1956 /* write updated itr to ring container */
1957 ring_container->itr = itr_setting;
f494e8fa
AV		 1958}
1959
509ee935
JB		 1960/**
1961 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1962 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1963 *
1964 * This function is made to be called by ethtool and by the driver
1965 * when it needs to update EITR registers at runtime. Hardware
1966 * specific quirks/differences are taken care of here.
1967 */
fe49f04a 1968void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1969{
fe49f04a 1970 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1971 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1972 int v_idx = q_vector->v_idx;
5d967eb7 1973 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 1974
bd508178
AD		 1975 switch (adapter->hw.mac.type) {
1976 case ixgbe_mac_82598EB:
509ee935
JB		 1977 /* must write high and low 16 bits to reset counter */
1978 itr_reg |= (itr_reg << 16);
bd508178
AD		 1979 break;
1980 case ixgbe_mac_82599EB:
b93a2226 1981 case ixgbe_mac_X540:
509ee935
JB		 1982 /*
1983 * set the WDIS bit to not clear the timer bits and cause an
1984 * immediate assertion of the interrupt
1985 */
1986 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1987 break;
1988 default:
1989 break;
509ee935
JB		 1990 }
1991 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1992}
1993
bd198058 1994static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1995{
d5bf4f67 1996 u32 new_itr = q_vector->itr;
bd198058 1997 u8 current_itr;
f494e8fa 1998
bd198058
AD		 1999 ixgbe_update_itr(q_vector, &q_vector->tx);
2000 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2001
08c8833b 2002 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2003
2004 switch (current_itr) {
2005 /* counts and packets in update_itr are dependent on these numbers */
2006 case lowest_latency:
d5bf4f67 2007 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2008 break;
2009 case low_latency:
d5bf4f67 2010 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2011 break;
2012 case bulk_latency:
d5bf4f67 2013 new_itr = IXGBE_8K_ITR;
f494e8fa 2014 break;
bd198058
AD		 2015 default:
2016 break;
f494e8fa
AV		 2017 }
2018
d5bf4f67 2019 if (new_itr != q_vector->itr) {
fe49f04a 2020 /* do an exponential smoothing */
d5bf4f67
ET		 2021 new_itr = (10 * new_itr * q_vector->itr) /
2022 ((9 * new_itr) + q_vector->itr);
509ee935 2023
bd198058 2024 /* save the algorithm value here */
5d967eb7 2025 q_vector->itr = new_itr;
fe49f04a
AD		 2026
2027 ixgbe_write_eitr(q_vector);
f494e8fa 2028 }
f494e8fa
AV		 2029}
2030
119fc60a 2031/**
de88eeeb 2032 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2033 * @adapter: pointer to adapter
119fc60a 2034 **/
f0f9778d 2035static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2036{
119fc60a
MC		 2037 struct ixgbe_hw *hw = &adapter->hw;
2038 u32 eicr = adapter->interrupt_event;
2039
f0f9778d 2040 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2041 return;
2042
f0f9778d
AD		 2043 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2044 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2045 return;
2046
2047 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2048
7ca647bd 2049 switch (hw->device_id) {
f0f9778d
AD		 2050 case IXGBE_DEV_ID_82599_T3_LOM:
2051 /*
2052 * Since the warning interrupt is for both ports
2053 * we don't have to check if:
2054 * - This interrupt wasn't for our port.
2055 * - We may have missed the interrupt so always have to
2056 * check if we got a LSC
2057 */
2058 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2059 !(eicr & IXGBE_EICR_LSC))
2060 return;
2061
2062 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2063 u32 autoneg;
2064 bool link_up = false;
7ca647bd 2065
7ca647bd
JP		 2066 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2067
f0f9778d
AD		 2068 if (link_up)
2069 return;
2070 }
2071
2072 /* Check if this is not due to overtemp */
2073 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2074 return;
2075
2076 break;
7ca647bd
JP		 2077 default:
2078 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2079 return;
7ca647bd 2080 break;
119fc60a 2081 }
7ca647bd
JP		 2082 e_crit(drv,
2083 "Network adapter has been stopped because it has over heated. "
2084 "Restart the computer. If the problem persists, "
2085 "power off the system and replace the adapter\n");
f0f9778d
AD		 2086
2087 adapter->interrupt_event = 0;
119fc60a
MC		 2088}
2089
0befdb3e
JB		 2090static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2091{
2092 struct ixgbe_hw *hw = &adapter->hw;
2093
2094 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2095 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2096 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2097 /* write to clear the interrupt */
2098 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2099 }
2100}
cf8280ee 2101
4f51bf70
JK		 2102static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2103{
2104 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2105 return;
2106
2107 switch (adapter->hw.mac.type) {
2108 case ixgbe_mac_82599EB:
2109 /*
2110 * Need to check link state so complete overtemp check
2111 * on service task
2112 */
2113 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2114 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2115 adapter->interrupt_event = eicr;
2116 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2117 ixgbe_service_event_schedule(adapter);
2118 return;
2119 }
2120 return;
2121 case ixgbe_mac_X540:
2122 if (!(eicr & IXGBE_EICR_TS))
2123 return;
2124 break;
2125 default:
2126 return;
2127 }
2128
2129 e_crit(drv,
2130 "Network adapter has been stopped because it has over heated. "
2131 "Restart the computer. If the problem persists, "
2132 "power off the system and replace the adapter\n");
2133}
2134
e8e26350
PW		 2135static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2136{
2137 struct ixgbe_hw *hw = &adapter->hw;
2138
73c4b7cd
AD		 2139 if (eicr & IXGBE_EICR_GPI_SDP2) {
2140 /* Clear the interrupt */
2141 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2142 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2143 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2144 ixgbe_service_event_schedule(adapter);
2145 }
73c4b7cd
AD		 2146 }
2147
e8e26350
PW		 2148 if (eicr & IXGBE_EICR_GPI_SDP1) {
2149 /* Clear the interrupt */
2150 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2151 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2152 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2153 ixgbe_service_event_schedule(adapter);
2154 }
e8e26350
PW		 2155 }
2156}
2157
cf8280ee
JB		 2158static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2159{
2160 struct ixgbe_hw *hw = &adapter->hw;
2161
2162 adapter->lsc_int++;
2163 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2164 adapter->link_check_timeout = jiffies;
2165 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2166 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2167 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2168 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2169 }
2170}
2171
fe49f04a
AD		 2172static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2173 u64 qmask)
2174{
2175 u32 mask;
bd508178 2176 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2177
bd508178
AD		 2178 switch (hw->mac.type) {
2179 case ixgbe_mac_82598EB:
fe49f04a 2180 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2181 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2182 break;
2183 case ixgbe_mac_82599EB:
b93a2226 2184 case ixgbe_mac_X540:
fe49f04a 2185 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2186 if (mask)
2187 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2188 mask = (qmask >> 32);
bd508178
AD		 2189 if (mask)
2190 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2191 break;
2192 default:
2193 break;
fe49f04a
AD		 2194 }
2195 /* skip the flush */
2196}
2197
2198static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2199 u64 qmask)
fe49f04a
AD		 2200{
2201 u32 mask;
bd508178 2202 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2203
bd508178
AD		 2204 switch (hw->mac.type) {
2205 case ixgbe_mac_82598EB:
fe49f04a 2206 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2207 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2208 break;
2209 case ixgbe_mac_82599EB:
b93a2226 2210 case ixgbe_mac_X540:
fe49f04a 2211 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2212 if (mask)
2213 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2214 mask = (qmask >> 32);
bd508178
AD		 2215 if (mask)
2216 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2217 break;
2218 default:
2219 break;
fe49f04a
AD		 2220 }
2221 /* skip the flush */
2222}
2223
021230d4 2224/**
2c4af694
AD		 2225 * ixgbe_irq_enable - Enable default interrupt generation settings
2226 * @adapter: board private structure
021230d4 2227 **/
2c4af694
AD		 2228static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2229 bool flush)
9a799d71 2230{
2c4af694 2231 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2232
2c4af694
AD		 2233 /* don't reenable LSC while waiting for link */
2234 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2235 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2236
2c4af694 2237 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2238 switch (adapter->hw.mac.type) {
2239 case ixgbe_mac_82599EB:
2240 mask |= IXGBE_EIMS_GPI_SDP0;
2241 break;
2242 case ixgbe_mac_X540:
2243 mask |= IXGBE_EIMS_TS;
2244 break;
2245 default:
2246 break;
2247 }
2c4af694
AD		 2248 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2249 mask |= IXGBE_EIMS_GPI_SDP1;
2250 switch (adapter->hw.mac.type) {
2251 case ixgbe_mac_82599EB:
2c4af694
AD		 2252 mask |= IXGBE_EIMS_GPI_SDP1;
2253 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2254 case ixgbe_mac_X540:
2255 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2256 mask |= IXGBE_EIMS_MAILBOX;
2257 break;
2258 default:
2259 break;
9a799d71 2260 }
2c4af694
AD		 2261 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2262 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2263 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2264
2c4af694
AD		 2265 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2266 if (queues)
2267 ixgbe_irq_enable_queues(adapter, ~0);
2268 if (flush)
2269 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2270}
2271
2c4af694 2272static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2273{
a65151ba 2274 struct ixgbe_adapter *adapter = data;
9a799d71 2275 struct ixgbe_hw *hw = &adapter->hw;
54037505 2276 u32 eicr;
91281fd3 2277
54037505
DS		 2278 /*
2279 * Workaround for Silicon errata. Use clear-by-write instead
2280 * of clear-by-read. Reading with EICS will return the
2281 * interrupt causes without clearing, which later be done
2282 * with the write to EICR.
2283 */
2284 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2285 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2286
cf8280ee
JB		 2287 if (eicr & IXGBE_EICR_LSC)
2288 ixgbe_check_lsc(adapter);
f0848276 2289
1cdd1ec8
GR		 2290 if (eicr & IXGBE_EICR_MAILBOX)
2291 ixgbe_msg_task(adapter);
efe3d3c8 2292
bd508178
AD		 2293 switch (hw->mac.type) {
2294 case ixgbe_mac_82599EB:
b93a2226 2295 case ixgbe_mac_X540:
2c4af694
AD		 2296 if (eicr & IXGBE_EICR_ECC)
2297 e_info(link, "Received unrecoverable ECC Err, please "
2298 "reboot\n");
c4cf55e5
PWJ		 2299 /* Handle Flow Director Full threshold interrupt */
2300 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2301 int reinit_count = 0;
c4cf55e5 2302 int i;
c4cf55e5 2303 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2304 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2305 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2306 &ring->state))
2307 reinit_count++;
2308 }
2309 if (reinit_count) {
2310 /* no more flow director interrupts until after init */
2311 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2312 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2313 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2314 }
2315 }
f0f9778d 2316 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2317 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2318 break;
2319 default:
2320 break;
c4cf55e5 2321 }
f0848276 2322
bd508178 2323 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2324#ifdef CONFIG_IXGBE_PTP
2325 ixgbe_ptp_check_pps_event(adapter, eicr);
2326#endif
efe3d3c8 2327
7086400d 2328 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2329 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2330 ixgbe_irq_enable(adapter, false, false);
f0848276 2331
9a799d71 2332 return IRQ_HANDLED;
f0848276 2333}
91281fd3 2334
4ff7fb12 2335static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2336{
021230d4 2337 struct ixgbe_q_vector *q_vector = data;
91281fd3 2338
9b471446 2339 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2340
4ff7fb12
AD		 2341 if (q_vector->rx.ring || q_vector->tx.ring)
2342 napi_schedule(&q_vector->napi);
91281fd3 2343
9a799d71 2344 return IRQ_HANDLED;
91281fd3
AD		 2345}
2346
eb01b975
AD		 2347/**
2348 * ixgbe_poll - NAPI Rx polling callback
2349 * @napi: structure for representing this polling device
2350 * @budget: how many packets driver is allowed to clean
2351 *
2352 * This function is used for legacy and MSI, NAPI mode
2353 **/
8af3c33f 2354int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2355{
2356 struct ixgbe_q_vector *q_vector =
2357 container_of(napi, struct ixgbe_q_vector, napi);
2358 struct ixgbe_adapter *adapter = q_vector->adapter;
2359 struct ixgbe_ring *ring;
2360 int per_ring_budget;
2361 bool clean_complete = true;
2362
2363#ifdef CONFIG_IXGBE_DCA
2364 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2365 ixgbe_update_dca(q_vector);
2366#endif
2367
2368 ixgbe_for_each_ring(ring, q_vector->tx)
2369 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2370
2371 /* attempt to distribute budget to each queue fairly, but don't allow
2372 * the budget to go below 1 because we'll exit polling */
2373 if (q_vector->rx.count > 1)
2374 per_ring_budget = max(budget/q_vector->rx.count, 1);
2375 else
2376 per_ring_budget = budget;
2377
2378 ixgbe_for_each_ring(ring, q_vector->rx)
2379 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
2380 per_ring_budget);
2381
2382 /* If all work not completed, return budget and keep polling */
2383 if (!clean_complete)
2384 return budget;
2385
2386 /* all work done, exit the polling mode */
2387 napi_complete(napi);
2388 if (adapter->rx_itr_setting & 1)
2389 ixgbe_set_itr(q_vector);
2390 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2391 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2392
2393 return 0;
2394}
2395
021230d4
AV		 2396/**
2397 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2398 * @adapter: board private structure
2399 *
2400 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2401 * interrupts from the kernel.
2402 **/
2403static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2404{
2405 struct net_device *netdev = adapter->netdev;
207867f5 2406 int vector, err;
e8e9f696 2407 int ri = 0, ti = 0;
021230d4 2408
49c7ffbe 2409 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2410 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2411 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2412
4ff7fb12 2413 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2414 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2415 "%s-%s-%d", netdev->name, "TxRx", ri++);
2416 ti++;
2417 } else if (q_vector->rx.ring) {
9fe93afd 2418 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2419 "%s-%s-%d", netdev->name, "rx", ri++);
2420 } else if (q_vector->tx.ring) {
9fe93afd 2421 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2422 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2423 } else {
2424 /* skip this unused q_vector */
2425 continue;
32aa77a4 2426 }
207867f5
AD		 2427 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2428 q_vector->name, q_vector);
9a799d71 2429 if (err) {
396e799c 2430 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2431 "Error: %d\n", err);
021230d4 2432 goto free_queue_irqs;
9a799d71 2433 }
207867f5
AD		 2434 /* If Flow Director is enabled, set interrupt affinity */
2435 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2436 /* assign the mask for this irq */
2437 irq_set_affinity_hint(entry->vector,
de88eeeb 2438 &q_vector->affinity_mask);
207867f5 2439 }
9a799d71
AK		 2440 }
2441
021230d4 2442 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2443 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2444 if (err) {
de88eeeb 2445 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2446 goto free_queue_irqs;
9a799d71
AK		 2447 }
2448
9a799d71
AK		 2449 return 0;
2450
021230d4 2451free_queue_irqs:
207867f5
AD		 2452 while (vector) {
2453 vector--;
2454 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2455 NULL);
2456 free_irq(adapter->msix_entries[vector].vector,
2457 adapter->q_vector[vector]);
2458 }
021230d4
AV		 2459 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2460 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2461 kfree(adapter->msix_entries);
2462 adapter->msix_entries = NULL;
9a799d71
AK		 2463 return err;
2464}
2465
2466/**
021230d4 2467 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2468 * @irq: interrupt number
2469 * @data: pointer to a network interface device structure
9a799d71
AK		 2470 **/
2471static irqreturn_t ixgbe_intr(int irq, void *data)
2472{
a65151ba 2473 struct ixgbe_adapter *adapter = data;
9a799d71 2474 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2475 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2476 u32 eicr;
2477
54037505 2478 /*
24ddd967 2479 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2480 * before the read of EICR.
2481 */
2482 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2483
021230d4 2484 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2485 * therefore no explicit interrupt disable is necessary */
021230d4 2486 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2487 if (!eicr) {
6af3b9eb
ET		 2488 /*
2489 * shared interrupt alert!
f47cf66e 2490 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2491 * have disabled interrupts due to EIAM
2492 * finish the workaround of silicon errata on 82598. Unmask
2493 * the interrupt that we masked before the EICR read.
2494 */
2495 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2496 ixgbe_irq_enable(adapter, true, true);
9a799d71 2497 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2498 }
9a799d71 2499
cf8280ee
JB		 2500 if (eicr & IXGBE_EICR_LSC)
2501 ixgbe_check_lsc(adapter);
021230d4 2502
bd508178
AD		 2503 switch (hw->mac.type) {
2504 case ixgbe_mac_82599EB:
e8e26350 2505 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2506 /* Fall through */
2507 case ixgbe_mac_X540:
2508 if (eicr & IXGBE_EICR_ECC)
2509 e_info(link, "Received unrecoverable ECC err, please "
2510 "reboot\n");
4f51bf70 2511 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2512 break;
2513 default:
2514 break;
2515 }
e8e26350 2516
0befdb3e 2517 ixgbe_check_fan_failure(adapter, eicr);
681ae1ad
JK		 2518#ifdef CONFIG_IXGBE_PTP
2519 ixgbe_ptp_check_pps_event(adapter, eicr);
2520#endif
0befdb3e 2521
b9f6ed2b
AD		 2522 /* would disable interrupts here but EIAM disabled it */
2523 napi_schedule(&q_vector->napi);
9a799d71 2524
6af3b9eb
ET		 2525 /*
2526 * re-enable link(maybe) and non-queue interrupts, no flush.
2527 * ixgbe_poll will re-enable the queue interrupts
2528 */
6af3b9eb
ET		 2529 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2530 ixgbe_irq_enable(adapter, false, false);
2531
9a799d71
AK		 2532 return IRQ_HANDLED;
2533}
2534
2535/**
2536 * ixgbe_request_irq - initialize interrupts
2537 * @adapter: board private structure
2538 *
2539 * Attempts to configure interrupts using the best available
2540 * capabilities of the hardware and kernel.
2541 **/
021230d4 2542static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2543{
2544 struct net_device *netdev = adapter->netdev;
021230d4 2545 int err;
9a799d71 2546
4cc6df29 2547 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2548 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2549 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2550 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2551 netdev->name, adapter);
4cc6df29 2552 else
a0607fd3 2553 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2554 netdev->name, adapter);
9a799d71 2555
de88eeeb 2556 if (err)
396e799c 2557 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2558
9a799d71
AK		 2559 return err;
2560}
2561
2562static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2563{
49c7ffbe 2564 int vector;
9a799d71 2565
49c7ffbe
AD		 2566 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2567 free_irq(adapter->pdev->irq, adapter);
2568 return;
2569 }
4cc6df29 2570
49c7ffbe
AD		 2571 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2572 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2573 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2574
49c7ffbe
AD		 2575 /* free only the irqs that were actually requested */
2576 if (!q_vector->rx.ring && !q_vector->tx.ring)
2577 continue;
207867f5 2578
49c7ffbe
AD		 2579 /* clear the affinity_mask in the IRQ descriptor */
2580 irq_set_affinity_hint(entry->vector, NULL);
2581
2582 free_irq(entry->vector, q_vector);
9a799d71 2583 }
49c7ffbe
AD		 2584
2585 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2586}
2587
22d5a71b
JB		 2588/**
2589 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2590 * @adapter: board private structure
2591 **/
2592static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2593{
bd508178
AD		 2594 switch (adapter->hw.mac.type) {
2595 case ixgbe_mac_82598EB:
835462fc 2596 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2597 break;
2598 case ixgbe_mac_82599EB:
b93a2226 2599 case ixgbe_mac_X540:
835462fc
NS		 2600 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2601 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2602 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2603 break;
2604 default:
2605 break;
22d5a71b
JB		 2606 }
2607 IXGBE_WRITE_FLUSH(&adapter->hw);
2608 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2609 int vector;
2610
2611 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2612 synchronize_irq(adapter->msix_entries[vector].vector);
2613
2614 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2615 } else {
2616 synchronize_irq(adapter->pdev->irq);
2617 }
2618}
2619
9a799d71
AK		 2620/**
2621 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2622 *
2623 **/
2624static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2625{
d5bf4f67 2626 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2627
d5bf4f67
ET		 2628 /* rx/tx vector */
2629 if (adapter->rx_itr_setting == 1)
2630 q_vector->itr = IXGBE_20K_ITR;
2631 else
2632 q_vector->itr = adapter->rx_itr_setting;
2633
2634 ixgbe_write_eitr(q_vector);
9a799d71 2635
e8e26350
PW		 2636 ixgbe_set_ivar(adapter, 0, 0, 0);
2637 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2638
396e799c 2639 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2640}
2641
43e69bf0
AD		 2642/**
2643 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2644 * @adapter: board private structure
2645 * @ring: structure containing ring specific data
2646 *
2647 * Configure the Tx descriptor ring after a reset.
2648 **/
84418e3b
AD		 2649void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2650 struct ixgbe_ring *ring)
43e69bf0
AD		 2651{
2652 struct ixgbe_hw *hw = &adapter->hw;
2653 u64 tdba = ring->dma;
2f1860b8 2654 int wait_loop = 10;
b88c6de2 2655 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2656 u8 reg_idx = ring->reg_idx;
43e69bf0 2657
2f1860b8 2658 /* disable queue to avoid issues while updating state */
b88c6de2 2659 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2660 IXGBE_WRITE_FLUSH(hw);
2661
43e69bf0 2662 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2663 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2664 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2665 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2666 ring->count * sizeof(union ixgbe_adv_tx_desc));
2667 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2668 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2669 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2670
b88c6de2
AD		 2671 /*
2672 * set WTHRESH to encourage burst writeback, it should not be set
2673 * higher than 1 when ITR is 0 as it could cause false TX hangs
2674 *
2675 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2676 * to or less than the number of on chip descriptors, which is
2677 * currently 40.
2678 */
e954b374 2679 if (!ring->q_vector || (ring->q_vector->itr < 8))
b88c6de2
AD		 2680 txdctl |= (1 << 16); /* WTHRESH = 1 */
2681 else
2682 txdctl |= (8 << 16); /* WTHRESH = 8 */
2683
e954b374
AD		 2684 /*
2685 * Setting PTHRESH to 32 both improves performance
2686 * and avoids a TX hang with DFP enabled
2687 */
b88c6de2
AD		 2688 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2689 32; /* PTHRESH = 32 */
2f1860b8
AD		 2690
2691 /* reinitialize flowdirector state */
39cb681b 2692 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2693 ring->atr_sample_rate = adapter->atr_sample_rate;
2694 ring->atr_count = 0;
2695 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2696 } else {
2697 ring->atr_sample_rate = 0;
2698 }
2f1860b8 2699
c84d324c
JF		 2700 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2701
2f1860b8 2702 /* enable queue */
2f1860b8
AD		 2703 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2704
2705 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2706 if (hw->mac.type == ixgbe_mac_82598EB &&
2707 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2708 return;
2709
2710 /* poll to verify queue is enabled */
2711 do {
032b4325 2712 usleep_range(1000, 2000);
2f1860b8
AD		 2713 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2714 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2715 if (!wait_loop)
2716 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2717}
2718
120ff942
AD		 2719static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2720{
2721 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 2722 u32 rttdcs, mtqc;
8b1c0b24 2723 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2724
2725 if (hw->mac.type == ixgbe_mac_82598EB)
2726 return;
2727
2728 /* disable the arbiter while setting MTQC */
2729 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2730 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2731 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2732
2733 /* set transmit pool layout */
671c0adb
AD		 2734 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2735 mtqc = IXGBE_MTQC_VT_ENA;
2736 if (tcs > 4)
2737 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2738 else if (tcs > 1)
2739 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2740 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2741 mtqc |= IXGBE_MTQC_32VF;
2742 else
2743 mtqc |= IXGBE_MTQC_64VF;
2744 } else {
2745 if (tcs > 4)
2746 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2747 else if (tcs > 1)
2748 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 2749 else
671c0adb
AD		 2750 mtqc = IXGBE_MTQC_64Q_1PB;
2751 }
120ff942 2752
671c0adb 2753 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 2754
671c0adb
AD		 2755 /* Enable Security TX Buffer IFG for multiple pb */
2756 if (tcs) {
2757 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2758 sectx |= IXGBE_SECTX_DCB;
2759 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 2760 }
2761
2762 /* re-enable the arbiter */
2763 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2764 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2765}
2766
9a799d71 2767/**
3a581073 2768 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2769 * @adapter: board private structure
2770 *
2771 * Configure the Tx unit of the MAC after a reset.
2772 **/
2773static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2774{
2f1860b8
AD		 2775 struct ixgbe_hw *hw = &adapter->hw;
2776 u32 dmatxctl;
43e69bf0 2777 u32 i;
9a799d71 2778
2f1860b8
AD		 2779 ixgbe_setup_mtqc(adapter);
2780
2781 if (hw->mac.type != ixgbe_mac_82598EB) {
2782 /* DMATXCTL.EN must be before Tx queues are enabled */
2783 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2784 dmatxctl |= IXGBE_DMATXCTL_TE;
2785 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2786 }
2787
9a799d71 2788 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2789 for (i = 0; i < adapter->num_tx_queues; i++)
2790 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2791}
2792
3ebe8fde
AD		 2793static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
2794 struct ixgbe_ring *ring)
2795{
2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u8 reg_idx = ring->reg_idx;
2798 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2799
2800 srrctl |= IXGBE_SRRCTL_DROP_EN;
2801
2802 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2803}
2804
2805static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
2806 struct ixgbe_ring *ring)
2807{
2808 struct ixgbe_hw *hw = &adapter->hw;
2809 u8 reg_idx = ring->reg_idx;
2810 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
2811
2812 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
2813
2814 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
2815}
2816
2817#ifdef CONFIG_IXGBE_DCB
2818void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2819#else
2820static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
2821#endif
2822{
2823 int i;
2824 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
2825
2826 if (adapter->ixgbe_ieee_pfc)
2827 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
2828
2829 /*
2830 * We should set the drop enable bit if:
2831 * SR-IOV is enabled
2832 * or
2833 * Number of Rx queues > 1 and flow control is disabled
2834 *
2835 * This allows us to avoid head of line blocking for security
2836 * and performance reasons.
2837 */
2838 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
2839 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
2840 for (i = 0; i < adapter->num_rx_queues; i++)
2841 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
2842 } else {
2843 for (i = 0; i < adapter->num_rx_queues; i++)
2844 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
2845 }
2846}
2847
e8e26350 2848#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2849
a6616b42 2850static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2851 struct ixgbe_ring *rx_ring)
cc41ac7c 2852{
45e9baa5 2853 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 2854 u32 srrctl;
bf29ee6c 2855 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2856
45e9baa5
AD		 2857 if (hw->mac.type == ixgbe_mac_82598EB) {
2858 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 2859
45e9baa5
AD		 2860 /*
2861 * if VMDq is not active we must program one srrctl register
2862 * per RSS queue since we have enabled RDRXCTL.MVMEN
2863 */
2864 reg_idx &= mask;
2865 }
cc41ac7c 2866
45e9baa5
AD		 2867 /* configure header buffer length, needed for RSC */
2868 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 2869
45e9baa5 2870 /* configure the packet buffer length */
f800326d
AD		 2871#if PAGE_SIZE > IXGBE_MAX_RXBUFFER
2872 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2873#else
f800326d 2874 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
afafd5b0 2875#endif
45e9baa5
AD		 2876
2877 /* configure descriptor type */
f800326d 2878 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 2879
45e9baa5 2880 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2881}
9a799d71 2882
05abb126 2883static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2884{
05abb126
AD		 2885 struct ixgbe_hw *hw = &adapter->hw;
2886 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2887 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2888 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2889 u32 mrqc = 0, reta = 0;
2890 u32 rxcsum;
2891 int i, j;
671c0adb
AD		 2892 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2893
671c0adb
AD		 2894 /*
2895 * Program table for at least 2 queues w/ SR-IOV so that VFs can
2896 * make full use of any rings they may have. We will use the
2897 * PSRTYPE register to control how many rings we use within the PF.
2898 */
2899 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
2900 rss_i = 2;
0cefafad 2901
05abb126
AD		 2902 /* Fill out hash function seeds */
2903 for (i = 0; i < 10; i++)
2904 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2905
2906 /* Fill out redirection table */
2907 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 2908 if (j == rss_i)
05abb126
AD		 2909 j = 0;
2910 /* reta = 4-byte sliding window of
2911 * 0x00..(indices-1)(indices-1)00..etc. */
2912 reta = (reta << 8) | (j * 0x11);
2913 if ((i & 3) == 3)
2914 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2915 }
0cefafad 2916
05abb126
AD		 2917 /* Disable indicating checksum in descriptor, enables RSS hash */
2918 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2919 rxcsum |= IXGBE_RXCSUM_PCSD;
2920 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2921
671c0adb 2922 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 2923 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 2924 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2925 } else {
671c0adb
AD		 2926 u8 tcs = netdev_get_num_tc(adapter->netdev);
2927
2928 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2929 if (tcs > 4)
2930 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
2931 else if (tcs > 1)
2932 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
2933 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
2934 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 2935 else
671c0adb
AD		 2936 mrqc = IXGBE_MRQC_VMDQRSS64EN;
2937 } else {
2938 if (tcs > 4)
8b1c0b24 2939 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 2940 else if (tcs > 1)
2941 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2942 else
2943 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 2944 }
0cefafad
JB		 2945 }
2946
05abb126 2947 /* Perform hash on these packet types */
671c0adb
AD		 2948 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
2949 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
2950 IXGBE_MRQC_RSS_FIELD_IPV6 |
2951 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 2952
ef6afc0c
AD		 2953 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
2954 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
2955 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
2956 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2957
05abb126 2958 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2959}
2960
bb5a9ad2
NS		 2961/**
2962 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2963 * @adapter: address of board private structure
2964 * @index: index of ring to set
bb5a9ad2 2965 **/
082757af 2966static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2967 struct ixgbe_ring *ring)
bb5a9ad2 2968{
bb5a9ad2 2969 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2970 u32 rscctrl;
bf29ee6c 2971 u8 reg_idx = ring->reg_idx;
7367096a 2972
7d637bcc 2973 if (!ring_is_rsc_enabled(ring))
7367096a 2974 return;
bb5a9ad2 2975
7367096a 2976 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2977 rscctrl |= IXGBE_RSCCTL_RSCEN;
2978 /*
2979 * we must limit the number of descriptors so that the
2980 * total size of max desc * buf_len is not greater
642c680e 2981 * than 65536
bb5a9ad2 2982 */
f800326d
AD		 2983#if (PAGE_SIZE <= 8192)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2985#elif (PAGE_SIZE <= 16384)
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
bb5a9ad2 2987#else
f800326d 2988 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
bb5a9ad2 2989#endif
7367096a 2990 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2991}
2992
9e10e045
AD		 2993#define IXGBE_MAX_RX_DESC_POLL 10
2994static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2995 struct ixgbe_ring *ring)
2996{
2997 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2998 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2999 u32 rxdctl;
bf29ee6c 3000 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3001
3002 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3003 if (hw->mac.type == ixgbe_mac_82598EB &&
3004 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3005 return;
3006
3007 do {
032b4325 3008 usleep_range(1000, 2000);
9e10e045
AD		 3009 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3010 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3011
3012 if (!wait_loop) {
3013 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3014 "the polling period\n", reg_idx);
3015 }
3016}
3017
2d39d576
YZ		 3018void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3019 struct ixgbe_ring *ring)
3020{
3021 struct ixgbe_hw *hw = &adapter->hw;
3022 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3023 u32 rxdctl;
3024 u8 reg_idx = ring->reg_idx;
3025
3026 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3027 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3028
3029 /* write value back with RXDCTL.ENABLE bit cleared */
3030 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3031
3032 if (hw->mac.type == ixgbe_mac_82598EB &&
3033 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3034 return;
3035
3036 /* the hardware may take up to 100us to really disable the rx queue */
3037 do {
3038 udelay(10);
3039 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3040 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3041
3042 if (!wait_loop) {
3043 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3044 "the polling period\n", reg_idx);
3045 }
3046}
3047
84418e3b
AD		 3048void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
acd37177
AD		 3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 u64 rdba = ring->dma;
9e10e045 3053 u32 rxdctl;
bf29ee6c 3054 u8 reg_idx = ring->reg_idx;
acd37177 3055
9e10e045
AD		 3056 /* disable queue to avoid issues while updating state */
3057 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3058 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3059
acd37177
AD		 3060 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3061 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3062 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3063 ring->count * sizeof(union ixgbe_adv_rx_desc));
3064 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3065 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3066 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3067
3068 ixgbe_configure_srrctl(adapter, ring);
3069 ixgbe_configure_rscctl(adapter, ring);
3070
e9f98072
GR		 3071 /* If operating in IOV mode set RLPML for X540 */
3072 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3073 hw->mac.type == ixgbe_mac_X540) {
3074 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3075 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3076 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3077 }
3078
9e10e045
AD		 3079 if (hw->mac.type == ixgbe_mac_82598EB) {
3080 /*
3081 * enable cache line friendly hardware writes:
3082 * PTHRESH=32 descriptors (half the internal cache),
3083 * this also removes ugly rx_no_buffer_count increment
3084 * HTHRESH=4 descriptors (to minimize latency on fetch)
3085 * WTHRESH=8 burst writeback up to two cache lines
3086 */
3087 rxdctl &= ~0x3FFFFF;
3088 rxdctl |= 0x080420;
3089 }
3090
3091 /* enable receive descriptor ring */
3092 rxdctl |= IXGBE_RXDCTL_ENABLE;
3093 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3094
3095 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3096 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3097}
3098
48654521
AD		 3099static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3100{
3101 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3102 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3103 int p;
3104
3105 /* PSRTYPE must be initialized in non 82598 adapters */
3106 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3107 IXGBE_PSRTYPE_UDPHDR |
3108 IXGBE_PSRTYPE_IPV4HDR |
48654521 3109 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3110 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3111
3112 if (hw->mac.type == ixgbe_mac_82598EB)
3113 return;
3114
fbe7ca7f
AD		 3115 if (rss_i > 3)
3116 psrtype |= 2 << 29;
3117 else if (rss_i > 1)
3118 psrtype |= 1 << 29;
48654521
AD		 3119
3120 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3121 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3122 psrtype);
3123}
3124
f5b4a52e
AD		 3125static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3126{
3127 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3128 u32 reg_offset, vf_shift;
435b19f6 3129 u32 gcr_ext, vmdctl;
de4c7f65 3130 int i;
f5b4a52e
AD		 3131
3132 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3133 return;
3134
3135 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3136 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3137 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3138 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3139 vmdctl |= IXGBE_VT_CTL_REPLEN;
3140 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3141
1d9c0bfd
AD		 3142 vf_shift = VMDQ_P(0) % 32;
3143 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3144
3145 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3146 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3147 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3148 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3149 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
f5b4a52e
AD		 3150 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3151
3152 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3153 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3154
3155 /*
3156 * Set up VF register offsets for selected VT Mode,
3157 * i.e. 32 or 64 VFs for SR-IOV
3158 */
73079ea0
AD		 3159 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3160 case IXGBE_82599_VMDQ_8Q_MASK:
3161 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3162 break;
3163 case IXGBE_82599_VMDQ_4Q_MASK:
3164 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3165 break;
3166 default:
3167 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3168 break;
3169 }
3170
f5b4a52e
AD		 3171 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3172
3173 /* enable Tx loopback for VF/PF communication */
3174 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
435b19f6 3175
a985b6c3 3176 /* Enable MAC Anti-Spoofing */
435b19f6 3177 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3178 adapter->num_vfs);
de4c7f65
GR		 3179 /* For VFs that have spoof checking turned off */
3180 for (i = 0; i < adapter->num_vfs; i++) {
3181 if (!adapter->vfinfo[i].spoofchk_enabled)
3182 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3183 }
f5b4a52e
AD		 3184}
3185
477de6ed 3186static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3187{
9a799d71
AK		 3188 struct ixgbe_hw *hw = &adapter->hw;
3189 struct net_device *netdev = adapter->netdev;
3190 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3191 struct ixgbe_ring *rx_ring;
3192 int i;
3193 u32 mhadd, hlreg0;
48654521 3194
63f39bd1 3195#ifdef IXGBE_FCOE
477de6ed
AD		 3196 /* adjust max frame to be able to do baby jumbo for FCoE */
3197 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3198 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3199 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3200
477de6ed
AD		 3201#endif /* IXGBE_FCOE */
3202 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3203 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3204 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3205 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3206
3207 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3208 }
3209
919e78a6
AD		 3210 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3211 max_frame += VLAN_HLEN;
3212
477de6ed
AD		 3213 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3214 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3215 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3216 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3217
0cefafad
JB		 3218 /*
3219 * Setup the HW Rx Head and Tail Descriptor Pointers and
3220 * the Base and Length of the Rx Descriptor Ring
3221 */
9a799d71 3222 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3223 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3224 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3225 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3226 else
7d637bcc 3227 clear_ring_rsc_enabled(rx_ring);
477de6ed 3228 }
477de6ed
AD		 3229}
3230
7367096a
AD		 3231static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3232{
3233 struct ixgbe_hw *hw = &adapter->hw;
3234 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3235
3236 switch (hw->mac.type) {
3237 case ixgbe_mac_82598EB:
3238 /*
3239 * For VMDq support of different descriptor types or
3240 * buffer sizes through the use of multiple SRRCTL
3241 * registers, RDRXCTL.MVMEN must be set to 1
3242 *
3243 * also, the manual doesn't mention it clearly but DCA hints
3244 * will only use queue 0's tags unless this bit is set. Side
3245 * effects of setting this bit are only that SRRCTL must be
3246 * fully programmed [0..15]
3247 */
3248 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3249 break;
3250 case ixgbe_mac_82599EB:
b93a2226 3251 case ixgbe_mac_X540:
7367096a
AD		 3252 /* Disable RSC for ACK packets */
3253 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3254 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3255 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3256 /* hardware requires some bits to be set by default */
3257 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3258 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3259 break;
3260 default:
3261 /* We should do nothing since we don't know this hardware */
3262 return;
3263 }
3264
3265 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3266}
3267
477de6ed
AD		 3268/**
3269 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3270 * @adapter: board private structure
3271 *
3272 * Configure the Rx unit of the MAC after a reset.
3273 **/
3274static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3275{
3276 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3277 int i;
3278 u32 rxctrl;
477de6ed
AD		 3279
3280 /* disable receives while setting up the descriptors */
3281 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3282 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3283
3284 ixgbe_setup_psrtype(adapter);
7367096a 3285 ixgbe_setup_rdrxctl(adapter);
477de6ed 3286
9e10e045 3287 /* Program registers for the distribution of queues */
f5b4a52e 3288 ixgbe_setup_mrqc(adapter);
f5b4a52e 3289
477de6ed
AD		 3290 /* set_rx_buffer_len must be called before ring initialization */
3291 ixgbe_set_rx_buffer_len(adapter);
3292
3293 /*
3294 * Setup the HW Rx Head and Tail Descriptor Pointers and
3295 * the Base and Length of the Rx Descriptor Ring
3296 */
9e10e045
AD		 3297 for (i = 0; i < adapter->num_rx_queues; i++)
3298 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3299
9e10e045
AD		 3300 /* disable drop enable for 82598 parts */
3301 if (hw->mac.type == ixgbe_mac_82598EB)
3302 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3303
3304 /* enable all receives */
3305 rxctrl |= IXGBE_RXCTRL_RXEN;
3306 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3307}
3308
8e586137 3309static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3310{
3311 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3312 struct ixgbe_hw *hw = &adapter->hw;
3313
3314 /* add VID to filter table */
1d9c0bfd 3315 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3316 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3317
3318 return 0;
068c89b0
DS		 3319}
3320
8e586137 3321static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3322{
3323 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3324 struct ixgbe_hw *hw = &adapter->hw;
3325
068c89b0 3326 /* remove VID from filter table */
1d9c0bfd 3327 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3328 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3329
3330 return 0;
068c89b0
DS		 3331}
3332
5f6c0181
JB		 3333/**
3334 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3335 * @adapter: driver data
3336 */
3337static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3338{
3339 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3340 u32 vlnctrl;
3341
3342 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3343 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3344 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3345}
3346
3347/**
3348 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3349 * @adapter: driver data
3350 */
3351static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3352{
3353 struct ixgbe_hw *hw = &adapter->hw;
3354 u32 vlnctrl;
3355
3356 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3357 vlnctrl |= IXGBE_VLNCTRL_VFE;
3358 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3359 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3360}
3361
3362/**
3363 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3364 * @adapter: driver data
3365 */
3366static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3367{
3368 struct ixgbe_hw *hw = &adapter->hw;
3369 u32 vlnctrl;
5f6c0181
JB		 3370 int i, j;
3371
3372 switch (hw->mac.type) {
3373 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3374 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3375 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3376 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3377 break;
3378 case ixgbe_mac_82599EB:
b93a2226 3379 case ixgbe_mac_X540:
5f6c0181
JB		 3380 for (i = 0; i < adapter->num_rx_queues; i++) {
3381 j = adapter->rx_ring[i]->reg_idx;
3382 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3383 vlnctrl &= ~IXGBE_RXDCTL_VME;
3384 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3385 }
3386 break;
3387 default:
3388 break;
3389 }
3390}
3391
3392/**
f62bbb5e 3393 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3394 * @adapter: driver data
3395 */
f62bbb5e 3396static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3397{
3398 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3399 u32 vlnctrl;
5f6c0181
JB		 3400 int i, j;
3401
3402 switch (hw->mac.type) {
3403 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3404 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3405 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3406 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3407 break;
3408 case ixgbe_mac_82599EB:
b93a2226 3409 case ixgbe_mac_X540:
5f6c0181
JB		 3410 for (i = 0; i < adapter->num_rx_queues; i++) {
3411 j = adapter->rx_ring[i]->reg_idx;
3412 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3413 vlnctrl |= IXGBE_RXDCTL_VME;
3414 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3415 }
3416 break;
3417 default:
3418 break;
3419 }
3420}
3421
9a799d71
AK		 3422static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3423{
f62bbb5e 3424 u16 vid;
9a799d71 3425
f62bbb5e
JG		 3426 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3427
3428 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3429 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3430}
3431
2850062a
AD		 3432/**
3433 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3434 * @netdev: network interface device structure
3435 *
3436 * Writes unicast address list to the RAR table.
3437 * Returns: -ENOMEM on failure/insufficient address space
3438 * 0 on no addresses written
3439 * X on writing X addresses to the RAR table
3440 **/
3441static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3442{
3443 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3444 struct ixgbe_hw *hw = &adapter->hw;
95447461 3445 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3446 int count = 0;
3447
95447461
JF		 3448 /* In SR-IOV mode significantly less RAR entries are available */
3449 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3450 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3451
2850062a
AD		 3452 /* return ENOMEM indicating insufficient memory for addresses */
3453 if (netdev_uc_count(netdev) > rar_entries)
3454 return -ENOMEM;
3455
95447461 3456 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3457 struct netdev_hw_addr *ha;
3458 /* return error if we do not support writing to RAR table */
3459 if (!hw->mac.ops.set_rar)
3460 return -ENOMEM;
3461
3462 netdev_for_each_uc_addr(ha, netdev) {
3463 if (!rar_entries)
3464 break;
3465 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3466 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3467 count++;
3468 }
3469 }
3470 /* write the addresses in reverse order to avoid write combining */
3471 for (; rar_entries > 0 ; rar_entries--)
3472 hw->mac.ops.clear_rar(hw, rar_entries);
3473
3474 return count;
3475}
3476
9a799d71 3477/**
2c5645cf 3478 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3479 * @netdev: network interface device structure
3480 *
2c5645cf
CL		 3481 * The set_rx_method entry point is called whenever the unicast/multicast
3482 * address list or the network interface flags are updated. This routine is
3483 * responsible for configuring the hardware for proper unicast, multicast and
3484 * promiscuous mode.
9a799d71 3485 **/
7f870475 3486void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3487{
3488 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3489 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3490 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3491 int count;
9a799d71
AK		 3492
3493 /* Check for Promiscuous and All Multicast modes */
3494
3495 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3496
f5dc442b 3497 /* set all bits that we expect to always be set */
3f2d1c0f 3498 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3499 fctrl |= IXGBE_FCTRL_BAM;
3500 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3501 fctrl |= IXGBE_FCTRL_PMCF;
3502
2850062a
AD		 3503 /* clear the bits we are changing the status of */
3504 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3505
9a799d71 3506 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3507 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3508 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3509 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3510 /* don't hardware filter vlans in promisc mode */
3511 ixgbe_vlan_filter_disable(adapter);
9a799d71 3512 } else {
746b9f02
PM		 3513 if (netdev->flags & IFF_ALLMULTI) {
3514 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3515 vmolr |= IXGBE_VMOLR_MPE;
3516 } else {
3517 /*
3518 * Write addresses to the MTA, if the attempt fails
25985edc 3519 * then we should just turn on promiscuous mode so
2850062a
AD		 3520 * that we can at least receive multicast traffic
3521 */
3522 hw->mac.ops.update_mc_addr_list(hw, netdev);
3523 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3524 }
5f6c0181 3525 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3526 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3527 }
3528
3529 /*
3530 * Write addresses to available RAR registers, if there is not
3531 * sufficient space to store all the addresses then enable
3532 * unicast promiscuous mode
3533 */
3534 count = ixgbe_write_uc_addr_list(netdev);
3535 if (count < 0) {
3536 fctrl |= IXGBE_FCTRL_UPE;
3537 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3538 }
3539
1d9c0bfd 3540 if (adapter->num_vfs)
1cdd1ec8 3541 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3542
3543 if (hw->mac.type != ixgbe_mac_82598EB) {
3544 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3545 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3546 IXGBE_VMOLR_ROPE);
1d9c0bfd 3547 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3548 }
3549
3f2d1c0f
BG		 3550 /* This is useful for sniffing bad packets. */
3551 if (adapter->netdev->features & NETIF_F_RXALL) {
3552 /* UPE and MPE will be handled by normal PROMISC logic
3553 * in e1000e_set_rx_mode */
3554 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3555 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3556 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3557
3558 fctrl &= ~(IXGBE_FCTRL_DPF);
3559 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3560 }
3561
2850062a 3562 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3563
3564 if (netdev->features & NETIF_F_HW_VLAN_RX)
3565 ixgbe_vlan_strip_enable(adapter);
3566 else
3567 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3568}
3569
021230d4
AV		 3570static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3571{
3572 int q_idx;
021230d4 3573
49c7ffbe
AD		 3574 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3575 napi_enable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3576}
3577
3578static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3579{
3580 int q_idx;
021230d4 3581
49c7ffbe
AD		 3582 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
3583 napi_disable(&adapter->q_vector[q_idx]->napi);
021230d4
AV		 3584}
3585
7a6b6f51 3586#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3587/**
2f90b865
AD		 3588 * ixgbe_configure_dcb - Configure DCB hardware
3589 * @adapter: ixgbe adapter struct
3590 *
3591 * This is called by the driver on open to configure the DCB hardware.
3592 * This is also called by the gennetlink interface when reconfiguring
3593 * the DCB state.
3594 */
3595static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3596{
3597 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3598 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3599
67ebd791
AD		 3600 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3601 if (hw->mac.type == ixgbe_mac_82598EB)
3602 netif_set_gso_max_size(adapter->netdev, 65536);
3603 return;
3604 }
3605
3606 if (hw->mac.type == ixgbe_mac_82598EB)
3607 netif_set_gso_max_size(adapter->netdev, 32768);
3608
2f90b865 3609 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3610
971060b1 3611#ifdef IXGBE_FCOE
b120818e
JF		 3612 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3613 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3614#endif
b120818e
JF		 3615
3616 /* reconfigure the hardware */
3617 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3618 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3619 DCB_TX_CONFIG);
3620 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3621 DCB_RX_CONFIG);
3622 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3623 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3624 ixgbe_dcb_hw_ets(&adapter->hw,
3625 adapter->ixgbe_ieee_ets,
3626 max_frame);
3627 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3628 adapter->ixgbe_ieee_pfc->pfc_en,
3629 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3630 }
8187cd48
JF		 3631
3632 /* Enable RSS Hash per TC */
3633 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3634 u32 msb = 0;
3635 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3636
d411a936
AD		 3637 while (rss_i) {
3638 msb++;
3639 rss_i >>= 1;
3640 }
8187cd48 3641
4ae63730
AD		 3642 /* write msb to all 8 TCs in one write */
3643 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3644 }
2f90b865 3645}
9da712d2
JF		 3646#endif
3647
3648/* Additional bittime to account for IXGBE framing */
3649#define IXGBE_ETH_FRAMING 20
3650
49ce9c2c 3651/**
9da712d2
JF		 3652 * ixgbe_hpbthresh - calculate high water mark for flow control
3653 *
3654 * @adapter: board private structure to calculate for
49ce9c2c 3655 * @pb: packet buffer to calculate
9da712d2
JF		 3656 */
3657static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3658{
3659 struct ixgbe_hw *hw = &adapter->hw;
3660 struct net_device *dev = adapter->netdev;
3661 int link, tc, kb, marker;
3662 u32 dv_id, rx_pba;
3663
3664 /* Calculate max LAN frame size */
3665 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3666
3667#ifdef IXGBE_FCOE
3668 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3669 if ((dev->features & NETIF_F_FCOE_MTU) &&
3670 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3671 (pb == ixgbe_fcoe_get_tc(adapter)))
3672 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3673
3674#endif
9da712d2
JF		 3675 /* Calculate delay value for device */
3676 switch (hw->mac.type) {
3677 case ixgbe_mac_X540:
3678 dv_id = IXGBE_DV_X540(link, tc);
3679 break;
3680 default:
3681 dv_id = IXGBE_DV(link, tc);
3682 break;
3683 }
3684
3685 /* Loopback switch introduces additional latency */
3686 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3687 dv_id += IXGBE_B2BT(tc);
3688
3689 /* Delay value is calculated in bit times convert to KB */
3690 kb = IXGBE_BT2KB(dv_id);
3691 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3692
3693 marker = rx_pba - kb;
3694
3695 /* It is possible that the packet buffer is not large enough
3696 * to provide required headroom. In this case throw an error
3697 * to user and a do the best we can.
3698 */
3699 if (marker < 0) {
3700 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3701 "headroom to support flow control."
3702 "Decrease MTU or number of traffic classes\n", pb);
3703 marker = tc + 1;
3704 }
3705
3706 return marker;
3707}
3708
49ce9c2c 3709/**
9da712d2
JF		 3710 * ixgbe_lpbthresh - calculate low water mark for for flow control
3711 *
3712 * @adapter: board private structure to calculate for
49ce9c2c 3713 * @pb: packet buffer to calculate
9da712d2
JF		 3714 */
3715static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3716{
3717 struct ixgbe_hw *hw = &adapter->hw;
3718 struct net_device *dev = adapter->netdev;
3719 int tc;
3720 u32 dv_id;
3721
3722 /* Calculate max LAN frame size */
3723 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3724
3725 /* Calculate delay value for device */
3726 switch (hw->mac.type) {
3727 case ixgbe_mac_X540:
3728 dv_id = IXGBE_LOW_DV_X540(tc);
3729 break;
3730 default:
3731 dv_id = IXGBE_LOW_DV(tc);
3732 break;
3733 }
3734
3735 /* Delay value is calculated in bit times convert to KB */
3736 return IXGBE_BT2KB(dv_id);
3737}
3738
3739/*
3740 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3741 */
3742static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3743{
3744 struct ixgbe_hw *hw = &adapter->hw;
3745 int num_tc = netdev_get_num_tc(adapter->netdev);
3746 int i;
3747
3748 if (!num_tc)
3749 num_tc = 1;
3750
3751 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3752
3753 for (i = 0; i < num_tc; i++) {
3754 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3755
3756 /* Low water marks must not be larger than high water marks */
3757 if (hw->fc.low_water > hw->fc.high_water[i])
3758 hw->fc.low_water = 0;
3759 }
3760}
3761
80605c65
JF		 3762static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3763{
80605c65 3764 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3765 int hdrm;
3766 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3767
3768 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3769 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3770 hdrm = 32 << adapter->fdir_pballoc;
3771 else
3772 hdrm = 0;
80605c65 3773
f7e1027f 3774 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3775 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3776}
3777
e4911d57
AD		 3778static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3779{
3780 struct ixgbe_hw *hw = &adapter->hw;
3781 struct hlist_node *node, *node2;
3782 struct ixgbe_fdir_filter *filter;
3783
3784 spin_lock(&adapter->fdir_perfect_lock);
3785
3786 if (!hlist_empty(&adapter->fdir_filter_list))
3787 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3788
3789 hlist_for_each_entry_safe(filter, node, node2,
3790 &adapter->fdir_filter_list, fdir_node) {
3791 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3792 &filter->filter,
3793 filter->sw_idx,
3794 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3795 IXGBE_FDIR_DROP_QUEUE :
3796 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3797 }
3798
3799 spin_unlock(&adapter->fdir_perfect_lock);
3800}
3801
9a799d71
AK		 3802static void ixgbe_configure(struct ixgbe_adapter *adapter)
3803{
d2f5e7f3
AS		 3804 struct ixgbe_hw *hw = &adapter->hw;
3805
80605c65 3806 ixgbe_configure_pb(adapter);
7a6b6f51 3807#ifdef CONFIG_IXGBE_DCB
67ebd791 3808 ixgbe_configure_dcb(adapter);
2f90b865 3809#endif
9a799d71 3810
4c1d7b4b 3811 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3812 ixgbe_restore_vlan(adapter);
3813
d2f5e7f3
AS		 3814 switch (hw->mac.type) {
3815 case ixgbe_mac_82599EB:
3816 case ixgbe_mac_X540:
3817 hw->mac.ops.disable_rx_buff(hw);
3818 break;
3819 default:
3820 break;
3821 }
3822
c4cf55e5 3823 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3824 ixgbe_init_fdir_signature_82599(&adapter->hw,
3825 adapter->fdir_pballoc);
e4911d57
AD		 3826 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3827 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3828 adapter->fdir_pballoc);
3829 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3830 }
4c1d7b4b 3831
d2f5e7f3
AS		 3832 switch (hw->mac.type) {
3833 case ixgbe_mac_82599EB:
3834 case ixgbe_mac_X540:
3835 hw->mac.ops.enable_rx_buff(hw);
3836 break;
3837 default:
3838 break;
3839 }
3840
933d41f1 3841 ixgbe_configure_virtualization(adapter);
c4cf55e5 3842
7c8ae65a
AD		 3843#ifdef IXGBE_FCOE
3844 /* configure FCoE L2 filters, redirection table, and Rx control */
3845 ixgbe_configure_fcoe(adapter);
3846
3847#endif /* IXGBE_FCOE */
9a799d71
AK		 3848 ixgbe_configure_tx(adapter);
3849 ixgbe_configure_rx(adapter);
9a799d71
AK		 3850}
3851
e8e26350
PW		 3852static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3853{
3854 switch (hw->phy.type) {
3855 case ixgbe_phy_sfp_avago:
3856 case ixgbe_phy_sfp_ftl:
3857 case ixgbe_phy_sfp_intel:
3858 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3859 case ixgbe_phy_sfp_passive_tyco:
3860 case ixgbe_phy_sfp_passive_unknown:
3861 case ixgbe_phy_sfp_active_unknown:
3862 case ixgbe_phy_sfp_ftl_active:
e8e26350 3863 return true;
8917b447
AD		 3864 case ixgbe_phy_nl:
3865 if (hw->mac.type == ixgbe_mac_82598EB)
3866 return true;
e8e26350
PW		 3867 default:
3868 return false;
3869 }
3870}
3871
0ecc061d 3872/**
e8e26350
PW		 3873 * ixgbe_sfp_link_config - set up SFP+ link
3874 * @adapter: pointer to private adapter struct
3875 **/
3876static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3877{
7086400d 3878 /*
52f33af8 3879 * We are assuming the worst case scenario here, and that
7086400d
AD		 3880 * is that an SFP was inserted/removed after the reset
3881 * but before SFP detection was enabled. As such the best
3882 * solution is to just start searching as soon as we start
3883 */
3884 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3885 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3886
7086400d 3887 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3888}
3889
3890/**
3891 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3892 * @hw: pointer to private hardware struct
3893 *
3894 * Returns 0 on success, negative on failure
3895 **/
e8e26350 3896static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3897{
3898 u32 autoneg;
8620a103 3899 bool negotiation, link_up = false;
0ecc061d
PWJ		 3900 u32 ret = IXGBE_ERR_LINK_SETUP;
3901
3902 if (hw->mac.ops.check_link)
3903 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3904
3905 if (ret)
3906 goto link_cfg_out;
3907
0b0c2b31
ET		 3908 autoneg = hw->phy.autoneg_advertised;
3909 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3910 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3911 &negotiation);
0ecc061d
PWJ		 3912 if (ret)
3913 goto link_cfg_out;
3914
8620a103
MC		 3915 if (hw->mac.ops.setup_link)
3916 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3917link_cfg_out:
3918 return ret;
3919}
3920
a34bcfff 3921static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3922{
9a799d71 3923 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3924 u32 gpie = 0;
9a799d71 3925
9b471446 3926 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3927 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3928 IXGBE_GPIE_OCD;
3929 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3930 /*
3931 * use EIAM to auto-mask when MSI-X interrupt is asserted
3932 * this saves a register write for every interrupt
3933 */
3934 switch (hw->mac.type) {
3935 case ixgbe_mac_82598EB:
3936 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3937 break;
9b471446 3938 case ixgbe_mac_82599EB:
b93a2226
DS		 3939 case ixgbe_mac_X540:
3940 default:
9b471446
JB		 3941 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3942 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3943 break;
3944 }
3945 } else {
021230d4
AV		 3946 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3947 * specifically only auto mask tx and rx interrupts */
3948 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3949 }
9a799d71 3950
a34bcfff
AD		 3951 /* XXX: to interrupt immediately for EICS writes, enable this */
3952 /* gpie |= IXGBE_GPIE_EIMEN; */
3953
3954 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3955 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 3956
3957 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3958 case IXGBE_82599_VMDQ_8Q_MASK:
3959 gpie |= IXGBE_GPIE_VTMODE_16;
3960 break;
3961 case IXGBE_82599_VMDQ_4Q_MASK:
3962 gpie |= IXGBE_GPIE_VTMODE_32;
3963 break;
3964 default:
3965 gpie |= IXGBE_GPIE_VTMODE_64;
3966 break;
3967 }
119fc60a
MC		 3968 }
3969
5fdd31f9 3970 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3971 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3972 switch (adapter->hw.mac.type) {
3973 case ixgbe_mac_82599EB:
3974 gpie |= IXGBE_SDP0_GPIEN;
3975 break;
3976 case ixgbe_mac_X540:
3977 gpie |= IXGBE_EIMS_TS;
3978 break;
3979 default:
3980 break;
3981 }
3982 }
5fdd31f9 3983
a34bcfff
AD		 3984 /* Enable fan failure interrupt */
3985 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3986 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3987
2698b208 3988 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3989 gpie |= IXGBE_SDP1_GPIEN;
3990 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3991 }
a34bcfff
AD		 3992
3993 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3994}
3995
c7ccde0f 3996static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3997{
3998 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3999 int err;
a34bcfff
AD		 4000 u32 ctrl_ext;
4001
4002 ixgbe_get_hw_control(adapter);
4003 ixgbe_setup_gpie(adapter);
e8e26350 4004
9a799d71
AK		 4005 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4006 ixgbe_configure_msix(adapter);
4007 else
4008 ixgbe_configure_msi_and_legacy(adapter);
4009
c6ecf39a
DS		 4010 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
4011 if (hw->mac.ops.enable_tx_laser &&
4012 ((hw->phy.multispeed_fiber) ||
9f911707 4013 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 4014 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 4015 hw->mac.ops.enable_tx_laser(hw);
4016
9a799d71 4017 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4018 ixgbe_napi_enable_all(adapter);
4019
73c4b7cd
AD		 4020 if (ixgbe_is_sfp(hw)) {
4021 ixgbe_sfp_link_config(adapter);
4022 } else {
4023 err = ixgbe_non_sfp_link_config(hw);
4024 if (err)
4025 e_err(probe, "link_config FAILED %d\n", err);
4026 }
4027
021230d4
AV		 4028 /* clear any pending interrupts, may auto mask */
4029 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4030 ixgbe_irq_enable(adapter, true, true);
9a799d71 4031
bf069c97
DS		 4032 /*
4033 * If this adapter has a fan, check to see if we had a failure
4034 * before we enabled the interrupt.
4035 */
4036 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4037 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4038 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4039 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4040 }
4041
1da100bb 4042 /* enable transmits */
477de6ed 4043 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4044
9a799d71
AK		 4045 /* bring the link up in the watchdog, this could race with our first
4046 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4047 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4048 adapter->link_check_timeout = jiffies;
7086400d 4049 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4050
4051 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4052 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4053 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4054 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4055}
4056
d4f80882
AV		 4057void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4058{
4059 WARN_ON(in_interrupt());
7086400d
AD		 4060 /* put off any impending NetWatchDogTimeout */
4061 adapter->netdev->trans_start = jiffies;
4062
d4f80882 4063 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4064 usleep_range(1000, 2000);
d4f80882 4065 ixgbe_down(adapter);
5809a1ae
GR		 4066 /*
4067 * If SR-IOV enabled then wait a bit before bringing the adapter
4068 * back up to give the VFs time to respond to the reset. The
4069 * two second wait is based upon the watchdog timer cycle in
4070 * the VF driver.
4071 */
4072 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4073 msleep(2000);
d4f80882
AV		 4074 ixgbe_up(adapter);
4075 clear_bit(__IXGBE_RESETTING, &adapter->state);
4076}
4077
c7ccde0f 4078void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4079{
4080 /* hardware has been reset, we need to reload some things */
4081 ixgbe_configure(adapter);
4082
c7ccde0f 4083 ixgbe_up_complete(adapter);
9a799d71
AK		 4084}
4085
4086void ixgbe_reset(struct ixgbe_adapter *adapter)
4087{
c44ade9e 4088 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4089 int err;
4090
7086400d
AD		 4091 /* lock SFP init bit to prevent race conditions with the watchdog */
4092 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4093 usleep_range(1000, 2000);
4094
4095 /* clear all SFP and link config related flags while holding SFP_INIT */
4096 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4097 IXGBE_FLAG2_SFP_NEEDS_RESET);
4098 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4099
8ca783ab 4100 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4101 switch (err) {
4102 case 0:
4103 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4104 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4105 break;
4106 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4107 e_dev_err("master disable timed out\n");
da4dd0f7 4108 break;
794caeb2
PWJ		 4109 case IXGBE_ERR_EEPROM_VERSION:
4110 /* We are running on a pre-production device, log a warning */
849c4542 4111 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4112 "Please be aware there may be issues associated with "
849c4542
ET		 4113 "your hardware. If you are experiencing problems "
4114 "please contact your Intel or hardware "
4115 "representative who provided you with this "
4116 "hardware.\n");
794caeb2 4117 break;
da4dd0f7 4118 default:
849c4542 4119 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4120 }
9a799d71 4121
7086400d
AD		 4122 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4123
9a799d71 4124 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4125 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4126
4127 /* update SAN MAC vmdq pool selection */
4128 if (hw->mac.san_mac_rar_index)
4129 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
9a799d71
AK		 4130}
4131
f800326d
AD		 4132/**
4133 * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers
4134 * @rx_ring: ring to setup
4135 *
4136 * On many IA platforms the L1 cache has a critical stride of 4K, this
4137 * results in each receive buffer starting in the same cache set. To help
4138 * reduce the pressure on this cache set we can interleave the offsets so
4139 * that only every other buffer will be in the same cache set.
4140 **/
4141static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring)
4142{
4143 struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info;
4144 u16 i;
4145
4146 for (i = 0; i < rx_ring->count; i += 2) {
4147 rx_buffer[0].page_offset = 0;
4148 rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring);
4149 rx_buffer = &rx_buffer[2];
4150 }
4151}
4152
9a799d71
AK		 4153/**
4154 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4155 * @rx_ring: ring to free buffers from
4156 **/
b6ec895e 4157static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4158{
b6ec895e 4159 struct device *dev = rx_ring->dev;
9a799d71 4160 unsigned long size;
b6ec895e 4161 u16 i;
9a799d71 4162
84418e3b
AD		 4163 /* ring already cleared, nothing to do */
4164 if (!rx_ring->rx_buffer_info)
4165 return;
9a799d71 4166
84418e3b 4167 /* Free all the Rx ring sk_buffs */
9a799d71 4168 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4169 struct ixgbe_rx_buffer *rx_buffer;
4170
4171 rx_buffer = &rx_ring->rx_buffer_info[i];
4172 if (rx_buffer->skb) {
4173 struct sk_buff *skb = rx_buffer->skb;
4174 if (IXGBE_CB(skb)->page_released) {
4175 dma_unmap_page(dev,
4176 IXGBE_CB(skb)->dma,
4177 ixgbe_rx_bufsz(rx_ring),
4178 DMA_FROM_DEVICE);
4179 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4180 }
4181 dev_kfree_skb(skb);
9a799d71 4182 }
f800326d
AD		 4183 rx_buffer->skb = NULL;
4184 if (rx_buffer->dma)
4185 dma_unmap_page(dev, rx_buffer->dma,
4186 ixgbe_rx_pg_size(rx_ring),
4187 DMA_FROM_DEVICE);
4188 rx_buffer->dma = 0;
4189 if (rx_buffer->page)
dd411ec4
AD		 4190 __free_pages(rx_buffer->page,
4191 ixgbe_rx_pg_order(rx_ring));
f800326d 4192 rx_buffer->page = NULL;
9a799d71
AK		 4193 }
4194
4195 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4196 memset(rx_ring->rx_buffer_info, 0, size);
4197
f800326d
AD		 4198 ixgbe_init_rx_page_offset(rx_ring);
4199
9a799d71
AK		 4200 /* Zero out the descriptor ring */
4201 memset(rx_ring->desc, 0, rx_ring->size);
4202
f800326d 4203 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4204 rx_ring->next_to_clean = 0;
4205 rx_ring->next_to_use = 0;
9a799d71
AK		 4206}
4207
4208/**
4209 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4210 * @tx_ring: ring to be cleaned
4211 **/
b6ec895e 4212static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4213{
4214 struct ixgbe_tx_buffer *tx_buffer_info;
4215 unsigned long size;
b6ec895e 4216 u16 i;
9a799d71 4217
84418e3b
AD		 4218 /* ring already cleared, nothing to do */
4219 if (!tx_ring->tx_buffer_info)
4220 return;
9a799d71 4221
84418e3b 4222 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4223 for (i = 0; i < tx_ring->count; i++) {
4224 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4225 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4226 }
4227
dad8a3b3
JF		 4228 netdev_tx_reset_queue(txring_txq(tx_ring));
4229
9a799d71
AK		 4230 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4231 memset(tx_ring->tx_buffer_info, 0, size);
4232
4233 /* Zero out the descriptor ring */
4234 memset(tx_ring->desc, 0, tx_ring->size);
4235
4236 tx_ring->next_to_use = 0;
4237 tx_ring->next_to_clean = 0;
9a799d71
AK		 4238}
4239
4240/**
021230d4 4241 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4242 * @adapter: board private structure
4243 **/
021230d4 4244static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4245{
4246 int i;
4247
021230d4 4248 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4249 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4250}
4251
4252/**
021230d4 4253 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4254 * @adapter: board private structure
4255 **/
021230d4 4256static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4257{
4258 int i;
4259
021230d4 4260 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4261 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4262}
4263
e4911d57
AD		 4264static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4265{
4266 struct hlist_node *node, *node2;
4267 struct ixgbe_fdir_filter *filter;
4268
4269 spin_lock(&adapter->fdir_perfect_lock);
4270
4271 hlist_for_each_entry_safe(filter, node, node2,
4272 &adapter->fdir_filter_list, fdir_node) {
4273 hlist_del(&filter->fdir_node);
4274 kfree(filter);
4275 }
4276 adapter->fdir_filter_count = 0;
4277
4278 spin_unlock(&adapter->fdir_perfect_lock);
4279}
4280
9a799d71
AK		 4281void ixgbe_down(struct ixgbe_adapter *adapter)
4282{
4283 struct net_device *netdev = adapter->netdev;
7f821875 4284 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4285 u32 rxctrl;
bf29ee6c 4286 int i;
9a799d71
AK		 4287
4288 /* signal that we are down to the interrupt handler */
4289 set_bit(__IXGBE_DOWN, &adapter->state);
4290
4291 /* disable receives */
7f821875
JB		 4292 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4293 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4294
2d39d576
YZ		 4295 /* disable all enabled rx queues */
4296 for (i = 0; i < adapter->num_rx_queues; i++)
4297 /* this call also flushes the previous write */
4298 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4299
032b4325 4300 usleep_range(10000, 20000);
9a799d71 4301
7f821875
JB		 4302 netif_tx_stop_all_queues(netdev);
4303
7086400d 4304 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4305 netif_carrier_off(netdev);
4306 netif_tx_disable(netdev);
4307
4308 ixgbe_irq_disable(adapter);
4309
4310 ixgbe_napi_disable_all(adapter);
4311
d034acf1
AD		 4312 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4313 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4314 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4315
4316 del_timer_sync(&adapter->service_timer);
4317
34cecbbf 4318 if (adapter->num_vfs) {
8e34d1aa
AD		 4319 /* Clear EITR Select mapping */
4320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4321
4322 /* Mark all the VFs as inactive */
4323 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4324 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4325
34cecbbf
AD		 4326 /* ping all the active vfs to let them know we are going down */
4327 ixgbe_ping_all_vfs(adapter);
4328
4329 /* Disable all VFTE/VFRE TX/RX */
4330 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4331 }
4332
7f821875
JB		 4333 /* disable transmits in the hardware now that interrupts are off */
4334 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4335 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4336 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4337 }
34cecbbf
AD		 4338
4339 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4340 switch (hw->mac.type) {
4341 case ixgbe_mac_82599EB:
b93a2226 4342 case ixgbe_mac_X540:
88512539 4343 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4344 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4345 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4346 break;
4347 default:
4348 break;
4349 }
7f821875 4350
6f4a0e45
PL		 4351 if (!pci_channel_offline(adapter->pdev))
4352 ixgbe_reset(adapter);
c6ecf39a
DS		 4353
4354 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4355 if (hw->mac.ops.disable_tx_laser &&
4356 ((hw->phy.multispeed_fiber) ||
9f911707 4357 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4358 (hw->mac.type == ixgbe_mac_82599EB))))
4359 hw->mac.ops.disable_tx_laser(hw);
4360
9a799d71
AK		 4361 ixgbe_clean_all_tx_rings(adapter);
4362 ixgbe_clean_all_rx_rings(adapter);
4363
5dd2d332 4364#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4365 /* since we reset the hardware DCA settings were cleared */
e35ec126 4366 ixgbe_setup_dca(adapter);
96b0e0f6 4367#endif
9a799d71
AK		 4368}
4369
9a799d71
AK		 4370/**
4371 * ixgbe_tx_timeout - Respond to a Tx Hang
4372 * @netdev: network interface device structure
4373 **/
4374static void ixgbe_tx_timeout(struct net_device *netdev)
4375{
4376 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4377
4378 /* Do the reset outside of interrupt context */
c83c6cbd 4379 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4380}
4381
9a799d71
AK		 4382/**
4383 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4384 * @adapter: board private structure to initialize
4385 *
4386 * ixgbe_sw_init initializes the Adapter private data structure.
4387 * Fields are initialized based on PCI device information and
4388 * OS network device settings (MTU size).
4389 **/
4390static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4391{
4392 struct ixgbe_hw *hw = &adapter->hw;
4393 struct pci_dev *pdev = adapter->pdev;
021230d4 4394 unsigned int rss;
7a6b6f51 4395#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4396 int j;
4397 struct tc_configuration *tc;
4398#endif
021230d4 4399
c44ade9e
JB		 4400 /* PCI config space info */
4401
4402 hw->vendor_id = pdev->vendor;
4403 hw->device_id = pdev->device;
4404 hw->revision_id = pdev->revision;
4405 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4406 hw->subsystem_device_id = pdev->subsystem_device;
4407
021230d4 4408 /* Set capability flags */
3ed69d7e 4409 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4410 adapter->ring_feature[RING_F_RSS].limit = rss;
bd508178
AD		 4411 switch (hw->mac.type) {
4412 case ixgbe_mac_82598EB:
bf069c97
DS		 4413 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4414 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
49c7ffbe 4415 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
bd508178 4416 break;
b93a2226 4417 case ixgbe_mac_X540:
4f51bf70
JK		 4418 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4419 case ixgbe_mac_82599EB:
49c7ffbe 4420 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
0c19d6af
PWJ		 4421 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4422 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4423 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4424 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509 4425 /* Flow Director hash filters enabled */
45b9f509 4426 adapter->atr_sample_rate = 20;
c087663e 4427 adapter->ring_feature[RING_F_FDIR].limit =
e8e9f696 4428 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4429 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4430#ifdef IXGBE_FCOE
0d551589
YZ		 4431 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4432 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
61a0f421 4433#ifdef CONFIG_IXGBE_DCB
6ee16520 4434 /* Default traffic class to use for FCoE */
56075a98 4435 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4436#endif
eacd73f7 4437#endif /* IXGBE_FCOE */
bd508178
AD		 4438 break;
4439 default:
4440 break;
f8212f97 4441 }
2f90b865 4442
7c8ae65a
AD		 4443#ifdef IXGBE_FCOE
4444 /* FCoE support exists, always init the FCoE lock */
4445 spin_lock_init(&adapter->fcoe.lock);
4446
4447#endif
1fc5f038
AD		 4448 /* n-tuple support exists, always init our spinlock */
4449 spin_lock_init(&adapter->fdir_perfect_lock);
4450
7a6b6f51 4451#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4452 switch (hw->mac.type) {
4453 case ixgbe_mac_X540:
4454 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4455 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4456 break;
4457 default:
4458 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4459 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4460 break;
4461 }
4462
2f90b865
AD		 4463 /* Configure DCB traffic classes */
4464 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4465 tc = &adapter->dcb_cfg.tc_config[j];
4466 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4467 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4468 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4469 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4470 tc->dcb_pfc = pfc_disabled;
4471 }
4de2a022
JF		 4472
4473 /* Initialize default user to priority mapping, UPx->TC0 */
4474 tc = &adapter->dcb_cfg.tc_config[0];
4475 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4476 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4477
2f90b865
AD		 4478 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4479 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4480 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4481 adapter->dcb_set_bitmap = 0x00;
3032309b 4482 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4483 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4484 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4485
4486#endif
9a799d71
AK		 4487
4488 /* default flow control settings */
cd7664f6 4489 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4490 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4491 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4492 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4493 hw->fc.send_xon = true;
71fd570b 4494 hw->fc.disable_fc_autoneg = false;
9a799d71 4495
99d74487
AD		 4496#ifdef CONFIG_PCI_IOV
4497 /* assign number of SR-IOV VFs */
4498 if (hw->mac.type != ixgbe_mac_82598EB)
4499 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4500
4501#endif
30efa5a3 4502 /* enable itr by default in dynamic mode */
f7554a2b 4503 adapter->rx_itr_setting = 1;
f7554a2b 4504 adapter->tx_itr_setting = 1;
30efa5a3 4505
30efa5a3
JB		 4506 /* set default ring sizes */
4507 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4508 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4509
bd198058 4510 /* set default work limits */
59224555 4511 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4512
9a799d71 4513 /* initialize eeprom parameters */
c44ade9e 4514 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4515 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4516 return -EIO;
4517 }
4518
9a799d71
AK		 4519 set_bit(__IXGBE_DOWN, &adapter->state);
4520
4521 return 0;
4522}
4523
4524/**
4525 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4526 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4527 *
4528 * Return 0 on success, negative on failure
4529 **/
b6ec895e 4530int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4531{
b6ec895e 4532 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4533 int orig_node = dev_to_node(dev);
4534 int numa_node = -1;
9a799d71
AK		 4535 int size;
4536
3a581073 4537 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4538
4539 if (tx_ring->q_vector)
4540 numa_node = tx_ring->q_vector->numa_node;
4541
4542 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4543 if (!tx_ring->tx_buffer_info)
89bf67f1 4544 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4545 if (!tx_ring->tx_buffer_info)
4546 goto err;
9a799d71
AK		 4547
4548 /* round up to nearest 4K */
12207e49 4549 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4550 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4551
de88eeeb
AD		 4552 set_dev_node(dev, numa_node);
4553 tx_ring->desc = dma_alloc_coherent(dev,
4554 tx_ring->size,
4555 &tx_ring->dma,
4556 GFP_KERNEL);
4557 set_dev_node(dev, orig_node);
4558 if (!tx_ring->desc)
4559 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4560 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4561 if (!tx_ring->desc)
4562 goto err;
9a799d71 4563
3a581073
JB		 4564 tx_ring->next_to_use = 0;
4565 tx_ring->next_to_clean = 0;
9a799d71 4566 return 0;
e01c31a5
JB		 4567
4568err:
4569 vfree(tx_ring->tx_buffer_info);
4570 tx_ring->tx_buffer_info = NULL;
b6ec895e 4571 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4572 return -ENOMEM;
9a799d71
AK		 4573}
4574
69888674
AD		 4575/**
4576 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4577 * @adapter: board private structure
4578 *
4579 * If this function returns with an error, then it's possible one or
4580 * more of the rings is populated (while the rest are not). It is the
4581 * callers duty to clean those orphaned rings.
4582 *
4583 * Return 0 on success, negative on failure
4584 **/
4585static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4586{
4587 int i, err = 0;
4588
4589 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4590 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4591 if (!err)
4592 continue;
de3d5b94 4593
396e799c 4594 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4595 goto err_setup_tx;
69888674
AD		 4596 }
4597
de3d5b94
AD		 4598 return 0;
4599err_setup_tx:
4600 /* rewind the index freeing the rings as we go */
4601 while (i--)
4602 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4603 return err;
4604}
4605
9a799d71
AK		 4606/**
4607 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4608 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4609 *
4610 * Returns 0 on success, negative on failure
4611 **/
b6ec895e 4612int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4613{
b6ec895e 4614 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4615 int orig_node = dev_to_node(dev);
4616 int numa_node = -1;
021230d4 4617 int size;
9a799d71 4618
3a581073 4619 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4620
4621 if (rx_ring->q_vector)
4622 numa_node = rx_ring->q_vector->numa_node;
4623
4624 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4625 if (!rx_ring->rx_buffer_info)
89bf67f1 4626 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4627 if (!rx_ring->rx_buffer_info)
4628 goto err;
9a799d71 4629
9a799d71 4630 /* Round up to nearest 4K */
3a581073
JB		 4631 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4632 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4633
de88eeeb
AD		 4634 set_dev_node(dev, numa_node);
4635 rx_ring->desc = dma_alloc_coherent(dev,
4636 rx_ring->size,
4637 &rx_ring->dma,
4638 GFP_KERNEL);
4639 set_dev_node(dev, orig_node);
4640 if (!rx_ring->desc)
4641 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4642 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4643 if (!rx_ring->desc)
4644 goto err;
9a799d71 4645
3a581073
JB		 4646 rx_ring->next_to_clean = 0;
4647 rx_ring->next_to_use = 0;
9a799d71 4648
f800326d
AD		 4649 ixgbe_init_rx_page_offset(rx_ring);
4650
9a799d71 4651 return 0;
b6ec895e
AD		 4652err:
4653 vfree(rx_ring->rx_buffer_info);
4654 rx_ring->rx_buffer_info = NULL;
4655 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4656 return -ENOMEM;
9a799d71
AK		 4657}
4658
69888674
AD		 4659/**
4660 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4661 * @adapter: board private structure
4662 *
4663 * If this function returns with an error, then it's possible one or
4664 * more of the rings is populated (while the rest are not). It is the
4665 * callers duty to clean those orphaned rings.
4666 *
4667 * Return 0 on success, negative on failure
4668 **/
69888674
AD		 4669static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4670{
4671 int i, err = 0;
4672
4673 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4674 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4675 if (!err)
4676 continue;
de3d5b94 4677
396e799c 4678 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4679 goto err_setup_rx;
69888674
AD		 4680 }
4681
7c8ae65a
AD		 4682#ifdef IXGBE_FCOE
4683 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4684 if (!err)
4685#endif
4686 return 0;
de3d5b94
AD		 4687err_setup_rx:
4688 /* rewind the index freeing the rings as we go */
4689 while (i--)
4690 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4691 return err;
4692}
4693
9a799d71
AK		 4694/**
4695 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 4696 * @tx_ring: Tx descriptor ring for a specific queue
4697 *
4698 * Free all transmit software resources
4699 **/
b6ec895e 4700void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4701{
b6ec895e 4702 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 4703
4704 vfree(tx_ring->tx_buffer_info);
4705 tx_ring->tx_buffer_info = NULL;
4706
b6ec895e
AD		 4707 /* if not set, then don't free */
4708 if (!tx_ring->desc)
4709 return;
4710
4711 dma_free_coherent(tx_ring->dev, tx_ring->size,
4712 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 4713
4714 tx_ring->desc = NULL;
4715}
4716
4717/**
4718 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4719 * @adapter: board private structure
4720 *
4721 * Free all transmit software resources
4722 **/
4723static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4724{
4725 int i;
4726
4727 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4728 if (adapter->tx_ring[i]->desc)
b6ec895e 4729 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 4730}
4731
4732/**
b4617240 4733 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 4734 * @rx_ring: ring to clean the resources from
4735 *
4736 * Free all receive software resources
4737 **/
b6ec895e 4738void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4739{
b6ec895e 4740 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 4741
4742 vfree(rx_ring->rx_buffer_info);
4743 rx_ring->rx_buffer_info = NULL;
4744
b6ec895e
AD		 4745 /* if not set, then don't free */
4746 if (!rx_ring->desc)
4747 return;
4748
4749 dma_free_coherent(rx_ring->dev, rx_ring->size,
4750 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 4751
4752 rx_ring->desc = NULL;
4753}
4754
4755/**
4756 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4757 * @adapter: board private structure
4758 *
4759 * Free all receive software resources
4760 **/
4761static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4762{
4763 int i;
4764
7c8ae65a
AD		 4765#ifdef IXGBE_FCOE
4766 ixgbe_free_fcoe_ddp_resources(adapter);
4767
4768#endif
9a799d71 4769 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4770 if (adapter->rx_ring[i]->desc)
b6ec895e 4771 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 4772}
4773
9a799d71
AK		 4774/**
4775 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4776 * @netdev: network interface device structure
4777 * @new_mtu: new value for maximum frame size
4778 *
4779 * Returns 0 on success, negative on failure
4780 **/
4781static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4782{
4783 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4784 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4785
42c783c5 4786 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 4787 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4788 return -EINVAL;
4789
4790 /*
4791 * For 82599EB we cannot allow PF to change MTU greater than 1500
4792 * in SR-IOV mode as it may cause buffer overruns in guest VFs that
4793 * don't allocate and chain buffers correctly.
4794 */
4795 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
4796 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
4797 (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
e9f98072 4798 return -EINVAL;
9a799d71 4799
396e799c 4800 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 4801
021230d4 4802 /* must set new MTU before calling down or up */
9a799d71
AK		 4803 netdev->mtu = new_mtu;
4804
d4f80882
AV		 4805 if (netif_running(netdev))
4806 ixgbe_reinit_locked(adapter);
9a799d71
AK		 4807
4808 return 0;
4809}
4810
4811/**
4812 * ixgbe_open - Called when a network interface is made active
4813 * @netdev: network interface device structure
4814 *
4815 * Returns 0 on success, negative value on failure
4816 *
4817 * The open entry point is called when a network interface is made
4818 * active by the system (IFF_UP). At this point all resources needed
4819 * for transmit and receive operations are allocated, the interrupt
4820 * handler is registered with the OS, the watchdog timer is started,
4821 * and the stack is notified that the interface is ready.
4822 **/
4823static int ixgbe_open(struct net_device *netdev)
4824{
4825 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4826 int err;
4bebfaa5
AK		 4827
4828 /* disallow open during test */
4829 if (test_bit(__IXGBE_TESTING, &adapter->state))
4830 return -EBUSY;
9a799d71 4831
54386467
JB		 4832 netif_carrier_off(netdev);
4833
9a799d71
AK		 4834 /* allocate transmit descriptors */
4835 err = ixgbe_setup_all_tx_resources(adapter);
4836 if (err)
4837 goto err_setup_tx;
4838
9a799d71
AK		 4839 /* allocate receive descriptors */
4840 err = ixgbe_setup_all_rx_resources(adapter);
4841 if (err)
4842 goto err_setup_rx;
4843
4844 ixgbe_configure(adapter);
4845
021230d4 4846 err = ixgbe_request_irq(adapter);
9a799d71
AK		 4847 if (err)
4848 goto err_req_irq;
4849
ac802f5d
AD		 4850 /* Notify the stack of the actual queue counts. */
4851 err = netif_set_real_num_tx_queues(netdev,
4852 adapter->num_rx_pools > 1 ? 1 :
4853 adapter->num_tx_queues);
4854 if (err)
4855 goto err_set_queues;
4856
4857
4858 err = netif_set_real_num_rx_queues(netdev,
4859 adapter->num_rx_pools > 1 ? 1 :
4860 adapter->num_rx_queues);
4861 if (err)
4862 goto err_set_queues;
4863
c7ccde0f 4864 ixgbe_up_complete(adapter);
9a799d71
AK		 4865
4866 return 0;
4867
ac802f5d
AD		 4868err_set_queues:
4869 ixgbe_free_irq(adapter);
9a799d71 4870err_req_irq:
a20a1199 4871 ixgbe_free_all_rx_resources(adapter);
de3d5b94 4872err_setup_rx:
a20a1199 4873 ixgbe_free_all_tx_resources(adapter);
de3d5b94 4874err_setup_tx:
9a799d71
AK		 4875 ixgbe_reset(adapter);
4876
4877 return err;
4878}
4879
4880/**
4881 * ixgbe_close - Disables a network interface
4882 * @netdev: network interface device structure
4883 *
4884 * Returns 0, this is not allowed to fail
4885 *
4886 * The close entry point is called when an interface is de-activated
4887 * by the OS. The hardware is still under the drivers control, but
4888 * needs to be disabled. A global MAC reset is issued to stop the
4889 * hardware, and all transmit and receive resources are freed.
4890 **/
4891static int ixgbe_close(struct net_device *netdev)
4892{
4893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 4894
4895 ixgbe_down(adapter);
4896 ixgbe_free_irq(adapter);
4897
e4911d57
AD		 4898 ixgbe_fdir_filter_exit(adapter);
4899
9a799d71
AK		 4900 ixgbe_free_all_tx_resources(adapter);
4901 ixgbe_free_all_rx_resources(adapter);
4902
5eba3699 4903 ixgbe_release_hw_control(adapter);
9a799d71
AK		 4904
4905 return 0;
4906}
4907
b3c8b4ba
AD		 4908#ifdef CONFIG_PM
4909static int ixgbe_resume(struct pci_dev *pdev)
4910{
c60fbb00
AD		 4911 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4912 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 4913 u32 err;
4914
4915 pci_set_power_state(pdev, PCI_D0);
4916 pci_restore_state(pdev);
656ab817
DS		 4917 /*
4918 * pci_restore_state clears dev->state_saved so call
4919 * pci_save_state to restore it.
4920 */
4921 pci_save_state(pdev);
9ce77666 4922
4923 err = pci_enable_device_mem(pdev);
b3c8b4ba 4924 if (err) {
849c4542 4925 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 4926 return err;
4927 }
4928 pci_set_master(pdev);
4929
dd4d8ca6 4930 pci_wake_from_d3(pdev, false);
b3c8b4ba 4931
b3c8b4ba
AD		 4932 ixgbe_reset(adapter);
4933
495dce12
WJP		 4934 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4935
ac802f5d
AD		 4936 rtnl_lock();
4937 err = ixgbe_init_interrupt_scheme(adapter);
4938 if (!err && netif_running(netdev))
c60fbb00 4939 err = ixgbe_open(netdev);
ac802f5d
AD		 4940
4941 rtnl_unlock();
4942
4943 if (err)
4944 return err;
b3c8b4ba
AD		 4945
4946 netif_device_attach(netdev);
4947
4948 return 0;
4949}
b3c8b4ba 4950#endif /* CONFIG_PM */
9d8d05ae
RW		 4951
4952static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 4953{
c60fbb00
AD		 4954 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
4955 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 4956 struct ixgbe_hw *hw = &adapter->hw;
4957 u32 ctrl, fctrl;
4958 u32 wufc = adapter->wol;
b3c8b4ba
AD		 4959#ifdef CONFIG_PM
4960 int retval = 0;
4961#endif
4962
4963 netif_device_detach(netdev);
4964
4965 if (netif_running(netdev)) {
ab6039a7 4966 rtnl_lock();
b3c8b4ba
AD		 4967 ixgbe_down(adapter);
4968 ixgbe_free_irq(adapter);
4969 ixgbe_free_all_tx_resources(adapter);
4970 ixgbe_free_all_rx_resources(adapter);
ab6039a7 4971 rtnl_unlock();
b3c8b4ba 4972 }
b3c8b4ba 4973
5f5ae6fc
AD		 4974 ixgbe_clear_interrupt_scheme(adapter);
4975
b3c8b4ba
AD		 4976#ifdef CONFIG_PM
4977 retval = pci_save_state(pdev);
4978 if (retval)
4979 return retval;
4df10466 4980
b3c8b4ba 4981#endif
e8e26350
PW		 4982 if (wufc) {
4983 ixgbe_set_rx_mode(netdev);
b3c8b4ba 4984
c509e754
DS		 4985 /*
4986 * enable the optics for both mult-speed fiber and
4987 * 82599 SFP+ fiber as we can WoL.
4988 */
4989 if (hw->mac.ops.enable_tx_laser &&
4990 (hw->phy.multispeed_fiber ||
4991 (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber &&
4992 hw->mac.type == ixgbe_mac_82599EB)))
4993 hw->mac.ops.enable_tx_laser(hw);
4994
e8e26350
PW		 4995 /* turn on all-multi mode if wake on multicast is enabled */
4996 if (wufc & IXGBE_WUFC_MC) {
4997 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4998 fctrl |= IXGBE_FCTRL_MPE;
4999 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5000 }
5001
5002 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5003 ctrl |= IXGBE_CTRL_GIO_DIS;
5004 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5005
5006 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5007 } else {
5008 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5009 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5010 }
5011
bd508178
AD		 5012 switch (hw->mac.type) {
5013 case ixgbe_mac_82598EB:
dd4d8ca6 5014 pci_wake_from_d3(pdev, false);
bd508178
AD		 5015 break;
5016 case ixgbe_mac_82599EB:
b93a2226 5017 case ixgbe_mac_X540:
bd508178
AD		 5018 pci_wake_from_d3(pdev, !!wufc);
5019 break;
5020 default:
5021 break;
5022 }
b3c8b4ba 5023
9d8d05ae
RW		 5024 *enable_wake = !!wufc;
5025
b3c8b4ba
AD		 5026 ixgbe_release_hw_control(adapter);
5027
5028 pci_disable_device(pdev);
5029
9d8d05ae
RW		 5030 return 0;
5031}
5032
5033#ifdef CONFIG_PM
5034static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5035{
5036 int retval;
5037 bool wake;
5038
5039 retval = __ixgbe_shutdown(pdev, &wake);
5040 if (retval)
5041 return retval;
5042
5043 if (wake) {
5044 pci_prepare_to_sleep(pdev);
5045 } else {
5046 pci_wake_from_d3(pdev, false);
5047 pci_set_power_state(pdev, PCI_D3hot);
5048 }
b3c8b4ba
AD		 5049
5050 return 0;
5051}
9d8d05ae 5052#endif /* CONFIG_PM */
b3c8b4ba
AD		 5053
5054static void ixgbe_shutdown(struct pci_dev *pdev)
5055{
9d8d05ae
RW		 5056 bool wake;
5057
5058 __ixgbe_shutdown(pdev, &wake);
5059
5060 if (system_state == SYSTEM_POWER_OFF) {
5061 pci_wake_from_d3(pdev, wake);
5062 pci_set_power_state(pdev, PCI_D3hot);
5063 }
b3c8b4ba
AD		 5064}
5065
9a799d71
AK		 5066/**
5067 * ixgbe_update_stats - Update the board statistics counters.
5068 * @adapter: board private structure
5069 **/
5070void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5071{
2d86f139 5072 struct net_device *netdev = adapter->netdev;
9a799d71 5073 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5074 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5075 u64 total_mpc = 0;
5076 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5077 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5078 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5079 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5080
d08935c2
DS		 5081 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5082 test_bit(__IXGBE_RESETTING, &adapter->state))
5083 return;
5084
94b982b2 5085 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5086 u64 rsc_count = 0;
94b982b2 5087 u64 rsc_flush = 0;
94b982b2 5088 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5089 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5090 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5091 }
5092 adapter->rsc_total_count = rsc_count;
5093 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5094 }
5095
5b7da515
AD		 5096 for (i = 0; i < adapter->num_rx_queues; i++) {
5097 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5098 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5099 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5100 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5101 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5102 bytes += rx_ring->stats.bytes;
5103 packets += rx_ring->stats.packets;
5104 }
5105 adapter->non_eop_descs = non_eop_descs;
5106 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5107 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5108 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5109 netdev->stats.rx_bytes = bytes;
5110 netdev->stats.rx_packets = packets;
5111
5112 bytes = 0;
5113 packets = 0;
7ca3bc58 5114 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5115 for (i = 0; i < adapter->num_tx_queues; i++) {
5116 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5117 restart_queue += tx_ring->tx_stats.restart_queue;
5118 tx_busy += tx_ring->tx_stats.tx_busy;
5119 bytes += tx_ring->stats.bytes;
5120 packets += tx_ring->stats.packets;
5121 }
eb985f09 5122 adapter->restart_queue = restart_queue;
5b7da515
AD		 5123 adapter->tx_busy = tx_busy;
5124 netdev->stats.tx_bytes = bytes;
5125 netdev->stats.tx_packets = packets;
7ca3bc58 5126
7ca647bd 5127 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5128
5129 /* 8 register reads */
6f11eef7
AV		 5130 for (i = 0; i < 8; i++) {
5131 /* for packet buffers not used, the register should read 0 */
5132 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5133 missed_rx += mpc;
7ca647bd
JP		 5134 hwstats->mpc[i] += mpc;
5135 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5136 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5137 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5138 switch (hw->mac.type) {
5139 case ixgbe_mac_82598EB:
1a70db4b
ET		 5140 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5141 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5142 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5143 hwstats->pxonrxc[i] +=
5144 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5145 break;
5146 case ixgbe_mac_82599EB:
b93a2226 5147 case ixgbe_mac_X540:
bd508178
AD		 5148 hwstats->pxonrxc[i] +=
5149 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5150 break;
5151 default:
5152 break;
e8e26350 5153 }
6f11eef7 5154 }
1a70db4b
ET		 5155
5156 /*16 register reads */
5157 for (i = 0; i < 16; i++) {
5158 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5159 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5160 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5161 (hw->mac.type == ixgbe_mac_X540)) {
5162 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5163 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5164 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5165 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5166 }
5167 }
5168
7ca647bd 5169 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5170 /* work around hardware counting issue */
7ca647bd 5171 hwstats->gprc -= missed_rx;
6f11eef7 5172
c84d324c
JF		 5173 ixgbe_update_xoff_received(adapter);
5174
6f11eef7 5175 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5176 switch (hw->mac.type) {
5177 case ixgbe_mac_82598EB:
5178 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5179 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5180 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5181 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5182 break;
b93a2226 5183 case ixgbe_mac_X540:
58f6bcf9
ET		 5184 /* OS2BMC stats are X540 only*/
5185 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5186 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5187 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5188 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5189 case ixgbe_mac_82599EB:
a4d4f629
AD		 5190 for (i = 0; i < 16; i++)
5191 adapter->hw_rx_no_dma_resources +=
5192 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5193 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5194 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5195 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5196 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5197 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5198 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5199 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5200 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5201 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5202#ifdef IXGBE_FCOE
7ca647bd
JP		 5203 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5204 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5205 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5206 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5207 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5208 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5209 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5210 if (adapter->fcoe.ddp_pool) {
5211 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5212 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5213 unsigned int cpu;
5214 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5215 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5216 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5217 noddp += ddp_pool->noddp;
5218 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5219 }
5a1ee270
AD		 5220 hwstats->fcoe_noddp = noddp;
5221 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5222 }
6d45522c 5223#endif /* IXGBE_FCOE */
bd508178
AD		 5224 break;
5225 default:
5226 break;
e8e26350 5227 }
9a799d71 5228 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5229 hwstats->bprc += bprc;
5230 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5231 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5232 hwstats->mprc -= bprc;
5233 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5234 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5235 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5236 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5237 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5238 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5239 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5240 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5241 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5242 hwstats->lxontxc += lxon;
6f11eef7 5243 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5244 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5245 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5246 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5247 /*
5248 * 82598 errata - tx of flow control packets is included in tx counters
5249 */
5250 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5251 hwstats->gptc -= xon_off_tot;
5252 hwstats->mptc -= xon_off_tot;
5253 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5254 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5255 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5256 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5257 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5258 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5259 hwstats->ptc64 -= xon_off_tot;
5260 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5261 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5262 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5263 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5264 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5265 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5266
5267 /* Fill out the OS statistics structure */
7ca647bd 5268 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5269
5270 /* Rx Errors */
7ca647bd 5271 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5272 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5273 netdev->stats.rx_length_errors = hwstats->rlec;
5274 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5275 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5276}
5277
5278/**
d034acf1 5279 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5280 * @adapter: pointer to the device adapter structure
9a799d71 5281 **/
d034acf1 5282static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5283{
cf8280ee 5284 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5285 int i;
cf8280ee 5286
d034acf1
AD		 5287 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5288 return;
5289
5290 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5291
d034acf1 5292 /* if interface is down do nothing */
fe49f04a 5293 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5294 return;
5295
5296 /* do nothing if we are not using signature filters */
5297 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5298 return;
5299
5300 adapter->fdir_overflow++;
5301
93c52dd0
AD		 5302 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5303 for (i = 0; i < adapter->num_tx_queues; i++)
5304 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5305 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5306 /* re-enable flow director interrupts */
5307 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5308 } else {
5309 e_err(probe, "failed to finish FDIR re-initialization, "
5310 "ignored adding FDIR ATR filters\n");
5311 }
93c52dd0
AD		 5312}
5313
5314/**
5315 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5316 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5317 *
5318 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5319 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5320 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5321 * determine if a hang has occurred.
93c52dd0
AD		 5322 */
5323static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5324{
cf8280ee 5325 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5326 u64 eics = 0;
5327 int i;
cf8280ee 5328
93c52dd0
AD		 5329 /* If we're down or resetting, just bail */
5330 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5331 test_bit(__IXGBE_RESETTING, &adapter->state))
5332 return;
22d5a71b 5333
93c52dd0
AD		 5334 /* Force detection of hung controller */
5335 if (netif_carrier_ok(adapter->netdev)) {
5336 for (i = 0; i < adapter->num_tx_queues; i++)
5337 set_check_for_tx_hang(adapter->tx_ring[i]);
5338 }
22d5a71b 5339
fe49f04a
AD		 5340 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5341 /*
5342 * for legacy and MSI interrupts don't set any bits
5343 * that are enabled for EIAM, because this operation
5344 * would set *both* EIMS and EICS for any bit in EIAM
5345 */
5346 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5347 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5348 } else {
5349 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5350 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5351 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5352 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5353 eics |= ((u64)1 << i);
5354 }
cf8280ee 5355 }
9a799d71 5356
93c52dd0 5357 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5358 ixgbe_irq_rearm_queues(adapter, eics);
5359
cf8280ee
JB		 5360}
5361
e8e26350 5362/**
93c52dd0 5363 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5364 * @adapter: pointer to the device adapter structure
5365 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5366 **/
93c52dd0 5367static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5368{
e8e26350 5369 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5370 u32 link_speed = adapter->link_speed;
5371 bool link_up = adapter->link_up;
041441d0 5372 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5373
93c52dd0
AD		 5374 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5375 return;
5376
5377 if (hw->mac.ops.check_link) {
5378 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5379 } else {
93c52dd0
AD		 5380 /* always assume link is up, if no check link function */
5381 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5382 link_up = true;
c4cf55e5 5383 }
041441d0
AD		 5384
5385 if (adapter->ixgbe_ieee_pfc)
5386 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5387
3ebe8fde 5388 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5389 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5390 ixgbe_set_rx_drop_en(adapter);
5391 }
93c52dd0
AD		 5392
5393 if (link_up ||
5394 time_after(jiffies, (adapter->link_check_timeout +
5395 IXGBE_TRY_LINK_TIMEOUT))) {
5396 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5397 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5398 IXGBE_WRITE_FLUSH(hw);
5399 }
5400
5401 adapter->link_up = link_up;
5402 adapter->link_speed = link_speed;
e8e26350
PW		 5403}
5404
5405/**
93c52dd0
AD		 5406 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5407 * print link up message
49ce9c2c 5408 * @adapter: pointer to the device adapter structure
e8e26350 5409 **/
93c52dd0 5410static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5411{
93c52dd0 5412 struct net_device *netdev = adapter->netdev;
e8e26350 5413 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5414 u32 link_speed = adapter->link_speed;
5415 bool flow_rx, flow_tx;
e8e26350 5416
93c52dd0
AD		 5417 /* only continue if link was previously down */
5418 if (netif_carrier_ok(netdev))
a985b6c3 5419 return;
63d6e1d8 5420
93c52dd0 5421 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5422
93c52dd0
AD		 5423 switch (hw->mac.type) {
5424 case ixgbe_mac_82598EB: {
5425 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5426 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5427 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5428 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5429 }
5430 break;
5431 case ixgbe_mac_X540:
5432 case ixgbe_mac_82599EB: {
5433 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5434 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5435 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5436 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5437 }
5438 break;
5439 default:
5440 flow_tx = false;
5441 flow_rx = false;
5442 break;
e8e26350 5443 }
3a6a4eda
JK		 5444
5445#ifdef CONFIG_IXGBE_PTP
5446 ixgbe_ptp_start_cyclecounter(adapter);
5447#endif
5448
93c52dd0
AD		 5449 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5450 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5451 "10 Gbps" :
5452 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5453 "1 Gbps" :
5454 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5455 "100 Mbps" :
5456 "unknown speed"))),
5457 ((flow_rx && flow_tx) ? "RX/TX" :
5458 (flow_rx ? "RX" :
5459 (flow_tx ? "TX" : "None"))));
e8e26350 5460
93c52dd0 5461 netif_carrier_on(netdev);
93c52dd0 5462 ixgbe_check_vf_rate_limit(adapter);
befa2af7
AD		 5463
5464 /* ping all the active vfs to let them know link has changed */
5465 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5466}
5467
c4cf55e5 5468/**
93c52dd0
AD		 5469 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5470 * print link down message
49ce9c2c 5471 * @adapter: pointer to the adapter structure
c4cf55e5 5472 **/
581330ba 5473static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5474{
cf8280ee 5475 struct net_device *netdev = adapter->netdev;
c4cf55e5 5476 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5477
93c52dd0
AD		 5478 adapter->link_up = false;
5479 adapter->link_speed = 0;
cf8280ee 5480
93c52dd0
AD		 5481 /* only continue if link was up previously */
5482 if (!netif_carrier_ok(netdev))
5483 return;
264857b8 5484
93c52dd0
AD		 5485 /* poll for SFP+ cable when link is down */
5486 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5487 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5488
3a6a4eda
JK		 5489#ifdef CONFIG_IXGBE_PTP
5490 ixgbe_ptp_start_cyclecounter(adapter);
5491#endif
5492
93c52dd0
AD		 5493 e_info(drv, "NIC Link is Down\n");
5494 netif_carrier_off(netdev);
befa2af7
AD		 5495
5496 /* ping all the active vfs to let them know link has changed */
5497 ixgbe_ping_all_vfs(adapter);
93c52dd0 5498}
e8e26350 5499
93c52dd0
AD		 5500/**
5501 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5502 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5503 **/
5504static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5505{
c4cf55e5 5506 int i;
93c52dd0 5507 int some_tx_pending = 0;
c4cf55e5 5508
93c52dd0 5509 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5510 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5511 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5512 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5513 some_tx_pending = 1;
5514 break;
5515 }
5516 }
5517
5518 if (some_tx_pending) {
5519 /* We've lost link, so the controller stops DMA,
5520 * but we've got queued Tx work that's never going
5521 * to get done, so reset controller to flush Tx.
5522 * (Do the reset outside of interrupt context).
5523 */
c83c6cbd 5524 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5525 }
c4cf55e5 5526 }
c4cf55e5
PWJ		 5527}
5528
a985b6c3
GR		 5529static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5530{
5531 u32 ssvpc;
5532
5533 /* Do not perform spoof check for 82598 */
5534 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5535 return;
5536
5537 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5538
5539 /*
5540 * ssvpc register is cleared on read, if zero then no
5541 * spoofed packets in the last interval.
5542 */
5543 if (!ssvpc)
5544 return;
5545
5546 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
5547}
5548
93c52dd0
AD		 5549/**
5550 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5551 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5552 **/
5553static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5554{
5555 /* if interface is down do nothing */
7edebf9a
ET		 5556 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5557 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5558 return;
5559
5560 ixgbe_watchdog_update_link(adapter);
5561
5562 if (adapter->link_up)
5563 ixgbe_watchdog_link_is_up(adapter);
5564 else
5565 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5566
a985b6c3 5567 ixgbe_spoof_check(adapter);
9a799d71 5568 ixgbe_update_stats(adapter);
93c52dd0
AD		 5569
5570 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5571}
10eec955 5572
cf8280ee 5573/**
7086400d 5574 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5575 * @adapter: the ixgbe adapter structure
cf8280ee 5576 **/
7086400d 5577static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5578{
cf8280ee 5579 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5580 s32 err;
cf8280ee 5581
7086400d
AD		 5582 /* not searching for SFP so there is nothing to do here */
5583 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5584 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5585 return;
10eec955 5586
7086400d
AD		 5587 /* someone else is in init, wait until next service event */
5588 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5589 return;
cf8280ee 5590
7086400d
AD		 5591 err = hw->phy.ops.identify_sfp(hw);
5592 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5593 goto sfp_out;
264857b8 5594
7086400d
AD		 5595 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5596 /* If no cable is present, then we need to reset
5597 * the next time we find a good cable. */
5598 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5599 }
9a799d71 5600
7086400d
AD		 5601 /* exit on error */
5602 if (err)
5603 goto sfp_out;
e8e26350 5604
7086400d
AD		 5605 /* exit if reset not needed */
5606 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5607 goto sfp_out;
9a799d71 5608
7086400d 5609 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5610
7086400d
AD		 5611 /*
5612 * A module may be identified correctly, but the EEPROM may not have
5613 * support for that module. setup_sfp() will fail in that case, so
5614 * we should not allow that module to load.
5615 */
5616 if (hw->mac.type == ixgbe_mac_82598EB)
5617 err = hw->phy.ops.reset(hw);
5618 else
5619 err = hw->mac.ops.setup_sfp(hw);
5620
5621 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5622 goto sfp_out;
5623
5624 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5625 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5626
5627sfp_out:
5628 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5629
5630 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5631 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5632 e_dev_err("failed to initialize because an unsupported "
5633 "SFP+ module type was detected.\n");
5634 e_dev_err("Reload the driver after installing a "
5635 "supported module.\n");
5636 unregister_netdev(adapter->netdev);
bc59fcda 5637 }
7086400d 5638}
bc59fcda 5639
7086400d
AD		 5640/**
5641 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5642 * @adapter: the ixgbe adapter structure
7086400d
AD		 5643 **/
5644static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5645{
5646 struct ixgbe_hw *hw = &adapter->hw;
5647 u32 autoneg;
5648 bool negotiation;
5649
5650 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5651 return;
5652
5653 /* someone else is in init, wait until next service event */
5654 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5655 return;
5656
5657 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5658
5659 autoneg = hw->phy.autoneg_advertised;
5660 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5661 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 5662 if (hw->mac.ops.setup_link)
5663 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5664
5665 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5666 adapter->link_check_timeout = jiffies;
5667 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5668}
5669
83c61fa9
GR		 5670#ifdef CONFIG_PCI_IOV
5671static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5672{
5673 int vf;
5674 struct ixgbe_hw *hw = &adapter->hw;
5675 struct net_device *netdev = adapter->netdev;
5676 u32 gpc;
5677 u32 ciaa, ciad;
5678
5679 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
5680 if (gpc) /* If incrementing then no need for the check below */
5681 return;
5682 /*
5683 * Check to see if a bad DMA write target from an errant or
5684 * malicious VF has caused a PCIe error. If so then we can
5685 * issue a VFLR to the offending VF(s) and then resume without
5686 * requesting a full slot reset.
5687 */
5688
5689 for (vf = 0; vf < adapter->num_vfs; vf++) {
5690 ciaa = (vf << 16) | 0x80000000;
5691 /* 32 bit read so align, we really want status at offset 6 */
5692 ciaa |= PCI_COMMAND;
5693 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5694 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
5695 ciaa &= 0x7FFFFFFF;
5696 /* disable debug mode asap after reading data */
5697 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5698 /* Get the upper 16 bits which will be the PCI status reg */
5699 ciad >>= 16;
5700 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
5701 netdev_err(netdev, "VF %d Hung DMA\n", vf);
5702 /* Issue VFLR */
5703 ciaa = (vf << 16) | 0x80000000;
5704 ciaa |= 0xA8;
5705 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5706 ciad = 0x00008000; /* VFLR */
5707 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
5708 ciaa &= 0x7FFFFFFF;
5709 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
5710 }
5711 }
5712}
5713
5714#endif
7086400d
AD		 5715/**
5716 * ixgbe_service_timer - Timer Call-back
5717 * @data: pointer to adapter cast into an unsigned long
5718 **/
5719static void ixgbe_service_timer(unsigned long data)
5720{
5721 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5722 unsigned long next_event_offset;
83c61fa9 5723 bool ready = true;
7086400d 5724
6bb78cfb
AD		 5725 /* poll faster when waiting for link */
5726 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
5727 next_event_offset = HZ / 10;
5728 else
5729 next_event_offset = HZ * 2;
83c61fa9 5730
6bb78cfb 5731#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 5732 /*
5733 * don't bother with SR-IOV VF DMA hang check if there are
5734 * no VFs or the link is down
5735 */
5736 if (!adapter->num_vfs ||
6bb78cfb 5737 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 5738 goto normal_timer_service;
83c61fa9
GR		 5739
5740 /* If we have VFs allocated then we must check for DMA hangs */
5741 ixgbe_check_for_bad_vf(adapter);
5742 next_event_offset = HZ / 50;
5743 adapter->timer_event_accumulator++;
5744
6bb78cfb 5745 if (adapter->timer_event_accumulator >= 100)
83c61fa9 5746 adapter->timer_event_accumulator = 0;
7086400d 5747 else
6bb78cfb 5748 ready = false;
7086400d 5749
6bb78cfb 5750normal_timer_service:
83c61fa9 5751#endif
7086400d
AD		 5752 /* Reset the timer */
5753 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
5754
83c61fa9
GR		 5755 if (ready)
5756 ixgbe_service_event_schedule(adapter);
7086400d
AD		 5757}
5758
c83c6cbd
AD		 5759static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
5760{
5761 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
5762 return;
5763
5764 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
5765
5766 /* If we're already down or resetting, just bail */
5767 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5768 test_bit(__IXGBE_RESETTING, &adapter->state))
5769 return;
5770
5771 ixgbe_dump(adapter);
5772 netdev_err(adapter->netdev, "Reset adapter\n");
5773 adapter->tx_timeout_count++;
5774
5775 ixgbe_reinit_locked(adapter);
5776}
5777
7086400d
AD		 5778/**
5779 * ixgbe_service_task - manages and runs subtasks
5780 * @work: pointer to work_struct containing our data
5781 **/
5782static void ixgbe_service_task(struct work_struct *work)
5783{
5784 struct ixgbe_adapter *adapter = container_of(work,
5785 struct ixgbe_adapter,
5786 service_task);
5787
c83c6cbd 5788 ixgbe_reset_subtask(adapter);
7086400d
AD		 5789 ixgbe_sfp_detection_subtask(adapter);
5790 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 5791 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 5792 ixgbe_watchdog_subtask(adapter);
d034acf1 5793 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 5794 ixgbe_check_hang_subtask(adapter);
3a6a4eda
JK		 5795#ifdef CONFIG_IXGBE_PTP
5796 ixgbe_ptp_overflow_check(adapter);
5797#endif
7086400d
AD		 5798
5799 ixgbe_service_event_complete(adapter);
9a799d71
AK		 5800}
5801
fd0db0ed
AD		 5802static int ixgbe_tso(struct ixgbe_ring *tx_ring,
5803 struct ixgbe_tx_buffer *first,
244e27ad 5804 u8 *hdr_len)
897ab156 5805{
fd0db0ed 5806 struct sk_buff *skb = first->skb;
897ab156
AD		 5807 u32 vlan_macip_lens, type_tucmd;
5808 u32 mss_l4len_idx, l4len;
9a799d71 5809
897ab156
AD		 5810 if (!skb_is_gso(skb))
5811 return 0;
9a799d71 5812
897ab156 5813 if (skb_header_cloned(skb)) {
244e27ad 5814 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 5815 if (err)
5816 return err;
9a799d71 5817 }
9a799d71 5818
897ab156
AD		 5819 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5820 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
5821
244e27ad 5822 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 5823 struct iphdr *iph = ip_hdr(skb);
5824 iph->tot_len = 0;
5825 iph->check = 0;
5826 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5827 iph->daddr, 0,
5828 IPPROTO_TCP,
5829 0);
5830 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 5831 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5832 IXGBE_TX_FLAGS_CSUM |
5833 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 5834 } else if (skb_is_gso_v6(skb)) {
5835 ipv6_hdr(skb)->payload_len = 0;
5836 tcp_hdr(skb)->check =
5837 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5838 &ipv6_hdr(skb)->daddr,
5839 0, IPPROTO_TCP, 0);
244e27ad
AD		 5840 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
5841 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 5842 }
5843
091a6246 5844 /* compute header lengths */
897ab156
AD		 5845 l4len = tcp_hdrlen(skb);
5846 *hdr_len = skb_transport_offset(skb) + l4len;
5847
091a6246
AD		 5848 /* update gso size and bytecount with header size */
5849 first->gso_segs = skb_shinfo(skb)->gso_segs;
5850 first->bytecount += (first->gso_segs - 1) * *hdr_len;
5851
897ab156
AD		 5852 /* mss_l4len_id: use 1 as index for TSO */
5853 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
5854 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
5855 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
5856
5857 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
5858 vlan_macip_lens = skb_network_header_len(skb);
5859 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5860 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 5861
5862 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 5863 mss_l4len_idx);
897ab156
AD		 5864
5865 return 1;
5866}
5867
244e27ad
AD		 5868static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
5869 struct ixgbe_tx_buffer *first)
7ca647bd 5870{
fd0db0ed 5871 struct sk_buff *skb = first->skb;
897ab156
AD		 5872 u32 vlan_macip_lens = 0;
5873 u32 mss_l4len_idx = 0;
5874 u32 type_tucmd = 0;
7ca647bd 5875
897ab156 5876 if (skb->ip_summed != CHECKSUM_PARTIAL) {
244e27ad
AD		 5877 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
5878 !(first->tx_flags & IXGBE_TX_FLAGS_TXSW))
5879 return;
897ab156
AD		 5880 } else {
5881 u8 l4_hdr = 0;
244e27ad 5882 switch (first->protocol) {
897ab156
AD		 5883 case __constant_htons(ETH_P_IP):
5884 vlan_macip_lens |= skb_network_header_len(skb);
5885 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
5886 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 5887 break;
897ab156
AD		 5888 case __constant_htons(ETH_P_IPV6):
5889 vlan_macip_lens |= skb_network_header_len(skb);
5890 l4_hdr = ipv6_hdr(skb)->nexthdr;
5891 break;
5892 default:
5893 if (unlikely(net_ratelimit())) {
5894 dev_warn(tx_ring->dev,
5895 "partial checksum but proto=%x!\n",
244e27ad 5896 first->protocol);
897ab156 5897 }
7ca647bd
JP		 5898 break;
5899 }
897ab156
AD		 5900
5901 switch (l4_hdr) {
7ca647bd 5902 case IPPROTO_TCP:
897ab156
AD		 5903 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5904 mss_l4len_idx = tcp_hdrlen(skb) <<
5905 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 5906 break;
5907 case IPPROTO_SCTP:
897ab156
AD		 5908 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5909 mss_l4len_idx = sizeof(struct sctphdr) <<
5910 IXGBE_ADVTXD_L4LEN_SHIFT;
5911 break;
5912 case IPPROTO_UDP:
5913 mss_l4len_idx = sizeof(struct udphdr) <<
5914 IXGBE_ADVTXD_L4LEN_SHIFT;
5915 break;
5916 default:
5917 if (unlikely(net_ratelimit())) {
5918 dev_warn(tx_ring->dev,
5919 "partial checksum but l4 proto=%x!\n",
244e27ad 5920 l4_hdr);
897ab156 5921 }
7ca647bd
JP		 5922 break;
5923 }
244e27ad
AD		 5924
5925 /* update TX checksum flag */
5926 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 5927 }
5928
244e27ad 5929 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 5930 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 5931 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 5932
897ab156
AD		 5933 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
5934 type_tucmd, mss_l4len_idx);
9a799d71
AK		 5935}
5936
d3d00239 5937static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 5938{
d3d00239
AD		 5939 /* set type for advanced descriptor with frame checksum insertion */
5940 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
5941 IXGBE_ADVTXD_DCMD_IFCS |
5942 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 5943
d3d00239 5944 /* set HW vlan bit if vlan is present */
66f32a8b 5945 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 5946 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 5947
3a6a4eda
JK		 5948#ifdef CONFIG_IXGBE_PTP
5949 if (tx_flags & IXGBE_TX_FLAGS_TSTAMP)
5950 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP);
5951#endif
5952
d3d00239
AD		 5953 /* set segmentation enable bits for TSO/FSO */
5954#ifdef IXGBE_FCOE
93f5b3c1 5955 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO))
d3d00239
AD		 5956#else
5957 if (tx_flags & IXGBE_TX_FLAGS_TSO)
5958#endif
5959 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 5960
d3d00239
AD		 5961 return cmd_type;
5962}
9a799d71 5963
729739b7
AD		 5964static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
5965 u32 tx_flags, unsigned int paylen)
d3d00239 5966{
93f5b3c1 5967 __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
9a799d71 5968
d3d00239
AD		 5969 /* enable L4 checksum for TSO and TX checksum offload */
5970 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5971 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 5972
93f5b3c1
AD		 5973 /* enble IPv4 checksum for TSO */
5974 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5975 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 5976
93f5b3c1
AD		 5977 /* use index 1 context for TSO/FSO/FCOE */
5978#ifdef IXGBE_FCOE
5979 if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE))
5980#else
5981 if (tx_flags & IXGBE_TX_FLAGS_TSO)
d3d00239 5982#endif
93f5b3c1
AD		 5983 olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT);
5984
7f9643fd
AD		 5985 /*
5986 * Check Context must be set if Tx switch is enabled, which it
5987 * always is for case where virtual functions are running
5988 */
93f5b3c1
AD		 5989#ifdef IXGBE_FCOE
5990 if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE))
5991#else
7f9643fd 5992 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
93f5b3c1 5993#endif
7f9643fd
AD		 5994 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
5995
729739b7 5996 tx_desc->read.olinfo_status = olinfo_status;
d3d00239 5997}
44df32c5 5998
d3d00239
AD		 5999#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6000 IXGBE_TXD_CMD_RS)
6001
6002static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6003 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6004 const u8 hdr_len)
6005{
729739b7 6006 dma_addr_t dma;
fd0db0ed 6007 struct sk_buff *skb = first->skb;
729739b7 6008 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6009 union ixgbe_adv_tx_desc *tx_desc;
729739b7 6010 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
d3d00239
AD		 6011 unsigned int data_len = skb->data_len;
6012 unsigned int size = skb_headlen(skb);
729739b7 6013 unsigned int paylen = skb->len - hdr_len;
244e27ad 6014 u32 tx_flags = first->tx_flags;
729739b7 6015 __le32 cmd_type;
d3d00239 6016 u16 i = tx_ring->next_to_use;
d3d00239 6017
729739b7
AD		 6018 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6019
6020 ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen);
6021 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6022
d3d00239
AD		 6023#ifdef IXGBE_FCOE
6024 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6025 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6026 size -= sizeof(struct fcoe_crc_eof) - data_len;
6027 data_len = 0;
729739b7
AD		 6028 } else {
6029 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6030 }
6031 }
44df32c5 6032
d3d00239 6033#endif
729739b7
AD		 6034 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
6035 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6036 goto dma_error;
8ad494b0 6037
729739b7
AD		 6038 /* record length, and DMA address */
6039 dma_unmap_len_set(first, len, size);
6040 dma_unmap_addr_set(first, dma, dma);
9a799d71 6041
729739b7 6042 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6043
d3d00239 6044 for (;;) {
729739b7 6045 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239
AD		 6046 tx_desc->read.cmd_type_len =
6047 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
e5a43549 6048
d3d00239 6049 i++;
729739b7 6050 tx_desc++;
d3d00239 6051 if (i == tx_ring->count) {
e4f74028 6052 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6053 i = 0;
6054 }
729739b7
AD		 6055
6056 dma += IXGBE_MAX_DATA_PER_TXD;
6057 size -= IXGBE_MAX_DATA_PER_TXD;
6058
6059 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6060 tx_desc->read.olinfo_status = 0;
d3d00239 6061 }
e5a43549 6062
729739b7
AD		 6063 if (likely(!data_len))
6064 break;
9a799d71 6065
f43f313e
BG		 6066 if (unlikely(skb->no_fcs))
6067 cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS));
d3d00239 6068 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
9a799d71 6069
729739b7
AD		 6070 i++;
6071 tx_desc++;
6072 if (i == tx_ring->count) {
6073 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6074 i = 0;
6075 }
9a799d71 6076
d3d00239 6077#ifdef IXGBE_FCOE
9e903e08 6078 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6079#else
9e903e08 6080 size = skb_frag_size(frag);
d3d00239
AD		 6081#endif
6082 data_len -= size;
9a799d71 6083
729739b7
AD		 6084 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6085 DMA_TO_DEVICE);
6086 if (dma_mapping_error(tx_ring->dev, dma))
d3d00239 6087 goto dma_error;
9a799d71 6088
729739b7
AD		 6089 tx_buffer = &tx_ring->tx_buffer_info[i];
6090 dma_unmap_len_set(tx_buffer, len, size);
6091 dma_unmap_addr_set(tx_buffer, dma, dma);
9a799d71 6092
729739b7
AD		 6093 tx_desc->read.buffer_addr = cpu_to_le64(dma);
6094 tx_desc->read.olinfo_status = 0;
9a799d71 6095
729739b7
AD		 6096 frag++;
6097 }
9a799d71 6098
729739b7
AD		 6099 /* write last descriptor with RS and EOP bits */
6100 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD);
6101 tx_desc->read.cmd_type_len = cmd_type;
eacd73f7 6102
091a6246 6103 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6104
d3d00239
AD		 6105 /* set the timestamp */
6106 first->time_stamp = jiffies;
9a799d71
AK		 6107
6108 /*
729739b7
AD		 6109 * Force memory writes to complete before letting h/w know there
6110 * are new descriptors to fetch. (Only applicable for weak-ordered
6111 * memory model archs, such as IA-64).
6112 *
6113 * We also need this memory barrier to make certain all of the
6114 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6115 */
6116 wmb();
6117
d3d00239
AD		 6118 /* set next_to_watch value indicating a packet is present */
6119 first->next_to_watch = tx_desc;
6120
729739b7
AD		 6121 i++;
6122 if (i == tx_ring->count)
6123 i = 0;
6124
6125 tx_ring->next_to_use = i;
6126
d3d00239 6127 /* notify HW of packet */
84ea2591 6128 writel(i, tx_ring->tail);
d3d00239
AD		 6129
6130 return;
6131dma_error:
729739b7 6132 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6133
6134 /* clear dma mappings for failed tx_buffer_info map */
6135 for (;;) {
729739b7
AD		 6136 tx_buffer = &tx_ring->tx_buffer_info[i];
6137 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6138 if (tx_buffer == first)
d3d00239
AD		 6139 break;
6140 if (i == 0)
6141 i = tx_ring->count;
6142 i--;
6143 }
6144
d3d00239 6145 tx_ring->next_to_use = i;
9a799d71
AK		 6146}
6147
fd0db0ed 6148static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6149 struct ixgbe_tx_buffer *first)
69830529
AD		 6150{
6151 struct ixgbe_q_vector *q_vector = ring->q_vector;
6152 union ixgbe_atr_hash_dword input = { .dword = 0 };
6153 union ixgbe_atr_hash_dword common = { .dword = 0 };
6154 union {
6155 unsigned char *network;
6156 struct iphdr *ipv4;
6157 struct ipv6hdr *ipv6;
6158 } hdr;
ee9e0f0b 6159 struct tcphdr *th;
905e4a41 6160 __be16 vlan_id;
c4cf55e5 6161
69830529
AD		 6162 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6163 if (!q_vector)
6164 return;
6165
6166 /* do nothing if sampling is disabled */
6167 if (!ring->atr_sample_rate)
d3ead241 6168 return;
c4cf55e5 6169
69830529 6170 ring->atr_count++;
c4cf55e5 6171
69830529 6172 /* snag network header to get L4 type and address */
fd0db0ed 6173 hdr.network = skb_network_header(first->skb);
69830529
AD		 6174
6175 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6176 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6177 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6178 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6179 hdr.ipv4->protocol != IPPROTO_TCP))
6180 return;
ee9e0f0b 6181
fd0db0ed 6182 th = tcp_hdr(first->skb);
c4cf55e5 6183
66f32a8b
AD		 6184 /* skip this packet since it is invalid or the socket is closing */
6185 if (!th || th->fin)
69830529
AD		 6186 return;
6187
6188 /* sample on all syn packets or once every atr sample count */
6189 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6190 return;
6191
6192 /* reset sample count */
6193 ring->atr_count = 0;
6194
244e27ad 6195 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6196
6197 /*
6198 * src and dst are inverted, think how the receiver sees them
6199 *
6200 * The input is broken into two sections, a non-compressed section
6201 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6202 * is XORed together and stored in the compressed dword.
6203 */
6204 input.formatted.vlan_id = vlan_id;
6205
6206 /*
6207 * since src port and flex bytes occupy the same word XOR them together
6208 * and write the value to source port portion of compressed dword
6209 */
244e27ad 6210 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6211 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6212 else
244e27ad 6213 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6214 common.port.dst ^= th->source;
6215
244e27ad 6216 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6217 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6218 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6219 } else {
6220 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6221 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6222 hdr.ipv6->saddr.s6_addr32[1] ^
6223 hdr.ipv6->saddr.s6_addr32[2] ^
6224 hdr.ipv6->saddr.s6_addr32[3] ^
6225 hdr.ipv6->daddr.s6_addr32[0] ^
6226 hdr.ipv6->daddr.s6_addr32[1] ^
6227 hdr.ipv6->daddr.s6_addr32[2] ^
6228 hdr.ipv6->daddr.s6_addr32[3];
6229 }
c4cf55e5
PWJ		 6230
6231 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6232 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6233 input, common, ring->queue_index);
c4cf55e5
PWJ		 6234}
6235
63544e9c 6236static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6237{
fc77dc3c 6238 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6239 /* Herbert's original patch had:
6240 * smp_mb__after_netif_stop_queue();
6241 * but since that doesn't exist yet, just open code it. */
6242 smp_mb();
6243
6244 /* We need to check again in a case another CPU has just
6245 * made room available. */
7d4987de 6246 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6247 return -EBUSY;
6248
6249 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6250 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6251 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6252 return 0;
6253}
6254
82d4e46e 6255static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6256{
7d4987de 6257 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6258 return 0;
fc77dc3c 6259 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6260}
6261
09a3b1f8
SH		 6262static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6263{
6264 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6265 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6266 smp_processor_id();
56075a98 6267#ifdef IXGBE_FCOE
6440752c 6268 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6269
e5b64635
JF		 6270 if (((protocol == htons(ETH_P_FCOE)) ||
6271 (protocol == htons(ETH_P_FIP))) &&
6272 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
c087663e
AD		 6273 struct ixgbe_ring_feature *f;
6274
6275 f = &adapter->ring_feature[RING_F_FCOE];
6276
6277 while (txq >= f->indices)
6278 txq -= f->indices;
e4b317e9 6279 txq += adapter->ring_feature[RING_F_FCOE].offset;
c087663e 6280
e5b64635 6281 return txq;
56075a98
JF		 6282 }
6283#endif
6284
fdd3d631
KK		 6285 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6286 while (unlikely(txq >= dev->real_num_tx_queues))
6287 txq -= dev->real_num_tx_queues;
5f715823 6288 return txq;
fdd3d631 6289 }
c4cf55e5 6290
09a3b1f8
SH		 6291 return skb_tx_hash(dev, skb);
6292}
6293
fc77dc3c 6294netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6295 struct ixgbe_adapter *adapter,
6296 struct ixgbe_ring *tx_ring)
9a799d71 6297{
d3d00239 6298 struct ixgbe_tx_buffer *first;
5f715823 6299 int tso;
d3d00239 6300 u32 tx_flags = 0;
a535c30e
AD		 6301#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6302 unsigned short f;
6303#endif
a535c30e 6304 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6305 __be16 protocol = skb->protocol;
63544e9c 6306 u8 hdr_len = 0;
5e09a105 6307
a535c30e
AD		 6308 /*
6309 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6310 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6311 * + 2 desc gap to keep tail from touching head,
6312 * + 1 desc for context descriptor,
6313 * otherwise try next time
6314 */
6315#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6316 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6317 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6318#else
6319 count += skb_shinfo(skb)->nr_frags;
6320#endif
6321 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6322 tx_ring->tx_stats.tx_busy++;
6323 return NETDEV_TX_BUSY;
6324 }
6325
fd0db0ed
AD		 6326 /* record the location of the first descriptor for this packet */
6327 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6328 first->skb = skb;
091a6246
AD		 6329 first->bytecount = skb->len;
6330 first->gso_segs = 1;
fd0db0ed 6331
66f32a8b 6332 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6333 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6334 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6335 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6336 /* else if it is a SW VLAN check the next protocol and store the tag */
6337 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6338 struct vlan_hdr *vhdr, _vhdr;
6339 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6340 if (!vhdr)
6341 goto out_drop;
6342
6343 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6344 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6345 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6346 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6347 }
6348
aa7bd467
JK		 6349 skb_tx_timestamp(skb);
6350
3a6a4eda
JK		 6351#ifdef CONFIG_IXGBE_PTP
6352 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6353 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6354 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
6355 }
6356#endif
6357
9e0c5648
AD		 6358#ifdef CONFIG_PCI_IOV
6359 /*
6360 * Use the l2switch_enable flag - would be false if the DMA
6361 * Tx switch had been disabled.
6362 */
6363 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6364 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6365
6366#endif
32701dc2 6367 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6368 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6369 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6370 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6371 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6372 tx_flags |= (skb->priority & 0x7) <<
6373 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6374 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6375 struct vlan_ethhdr *vhdr;
6376 if (skb_header_cloned(skb) &&
6377 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6378 goto out_drop;
6379 vhdr = (struct vlan_ethhdr *)skb->data;
6380 vhdr->h_vlan_TCI = htons(tx_flags >>
6381 IXGBE_TX_FLAGS_VLAN_SHIFT);
6382 } else {
6383 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6384 }
9a799d71 6385 }
eacd73f7 6386
244e27ad
AD		 6387 /* record initial flags and protocol */
6388 first->tx_flags = tx_flags;
6389 first->protocol = protocol;
6390
eacd73f7 6391#ifdef IXGBE_FCOE
66f32a8b
AD		 6392 /* setup tx offload for FCoE */
6393 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6394 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6395 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6396 if (tso < 0)
6397 goto out_drop;
9a799d71 6398
66f32a8b 6399 goto xmit_fcoe;
eacd73f7 6400 }
9a799d71 6401
66f32a8b 6402#endif /* IXGBE_FCOE */
244e27ad 6403 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6404 if (tso < 0)
897ab156 6405 goto out_drop;
244e27ad
AD		 6406 else if (!tso)
6407 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6408
6409 /* add the ATR filter if ATR is on */
6410 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6411 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6412
6413#ifdef IXGBE_FCOE
6414xmit_fcoe:
6415#endif /* IXGBE_FCOE */
244e27ad 6416 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6417
6418 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6419
6420 return NETDEV_TX_OK;
897ab156
AD		 6421
6422out_drop:
fd0db0ed
AD		 6423 dev_kfree_skb_any(first->skb);
6424 first->skb = NULL;
6425
897ab156 6426 return NETDEV_TX_OK;
9a799d71
AK		 6427}
6428
a50c29dd
AD		 6429static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6430 struct net_device *netdev)
84418e3b
AD		 6431{
6432 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6433 struct ixgbe_ring *tx_ring;
6434
a50c29dd
AD		 6435 /*
6436 * The minimum packet size for olinfo paylen is 17 so pad the skb
6437 * in order to meet this minimum size requirement.
6438 */
f73332fc
SH		 6439 if (unlikely(skb->len < 17)) {
6440 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6441 return NETDEV_TX_OK;
6442 skb->len = 17;
6443 }
6444
84418e3b 6445 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6446 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6447}
6448
9a799d71
AK		 6449/**
6450 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6451 * @netdev: network interface device structure
6452 * @p: pointer to an address structure
6453 *
6454 * Returns 0 on success, negative on failure
6455 **/
6456static int ixgbe_set_mac(struct net_device *netdev, void *p)
6457{
6458 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6459 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6460 struct sockaddr *addr = p;
6461
6462 if (!is_valid_ether_addr(addr->sa_data))
6463 return -EADDRNOTAVAIL;
6464
6465 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6466 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6467
1d9c0bfd 6468 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6469
6470 return 0;
6471}
6472
6b73e10d
BH		 6473static int
6474ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6475{
6476 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6477 struct ixgbe_hw *hw = &adapter->hw;
6478 u16 value;
6479 int rc;
6480
6481 if (prtad != hw->phy.mdio.prtad)
6482 return -EINVAL;
6483 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6484 if (!rc)
6485 rc = value;
6486 return rc;
6487}
6488
6489static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6490 u16 addr, u16 value)
6491{
6492 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6493 struct ixgbe_hw *hw = &adapter->hw;
6494
6495 if (prtad != hw->phy.mdio.prtad)
6496 return -EINVAL;
6497 return hw->phy.ops.write_reg(hw, addr, devad, value);
6498}
6499
6500static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6501{
6502 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6503
3a6a4eda
JK		 6504 switch (cmd) {
6505#ifdef CONFIG_IXGBE_PTP
6506 case SIOCSHWTSTAMP:
6507 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
6508#endif
6509 default:
6510 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6511 }
6b73e10d
BH		 6512}
6513
0365e6e4
PW		 6514/**
6515 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6516 * netdev->dev_addrs
0365e6e4
PW		 6517 * @netdev: network interface device structure
6518 *
6519 * Returns non-zero on failure
6520 **/
6521static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6522{
6523 int err = 0;
6524 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6525 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6526
7fa7c9dc 6527 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6528 rtnl_lock();
7fa7c9dc 6529 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6530 rtnl_unlock();
7fa7c9dc
AD		 6531
6532 /* update SAN MAC vmdq pool selection */
6533 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6534 }
6535 return err;
6536}
6537
6538/**
6539 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6540 * netdev->dev_addrs
0365e6e4
PW		 6541 * @netdev: network interface device structure
6542 *
6543 * Returns non-zero on failure
6544 **/
6545static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6546{
6547 int err = 0;
6548 struct ixgbe_adapter *adapter = netdev_priv(dev);
6549 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6550
6551 if (is_valid_ether_addr(mac->san_addr)) {
6552 rtnl_lock();
6553 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6554 rtnl_unlock();
6555 }
6556 return err;
6557}
6558
9a799d71
AK		 6559#ifdef CONFIG_NET_POLL_CONTROLLER
6560/*
6561 * Polling 'interrupt' - used by things like netconsole to send skbs
6562 * without having to re-enable interrupts. It's not called while
6563 * the interrupt routine is executing.
6564 */
6565static void ixgbe_netpoll(struct net_device *netdev)
6566{
6567 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6568 int i;
9a799d71 6569
1a647bd2
AD		 6570 /* if interface is down do nothing */
6571 if (test_bit(__IXGBE_DOWN, &adapter->state))
6572 return;
6573
9a799d71 6574 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6576 for (i = 0; i < adapter->num_q_vectors; i++)
6577 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6578 } else {
6579 ixgbe_intr(adapter->pdev->irq, netdev);
6580 }
9a799d71 6581 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6582}
9a799d71 6583
581330ba 6584#endif
de1036b1
ED		 6585static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6586 struct rtnl_link_stats64 *stats)
6587{
6588 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6589 int i;
6590
1a51502b 6591 rcu_read_lock();
de1036b1 6592 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6593 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6594 u64 bytes, packets;
6595 unsigned int start;
6596
1a51502b
ED		 6597 if (ring) {
6598 do {
6599 start = u64_stats_fetch_begin_bh(&ring->syncp);
6600 packets = ring->stats.packets;
6601 bytes = ring->stats.bytes;
6602 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6603 stats->rx_packets += packets;
6604 stats->rx_bytes += bytes;
6605 }
de1036b1 6606 }
1ac9ad13
ED		 6607
6608 for (i = 0; i < adapter->num_tx_queues; i++) {
6609 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6610 u64 bytes, packets;
6611 unsigned int start;
6612
6613 if (ring) {
6614 do {
6615 start = u64_stats_fetch_begin_bh(&ring->syncp);
6616 packets = ring->stats.packets;
6617 bytes = ring->stats.bytes;
6618 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6619 stats->tx_packets += packets;
6620 stats->tx_bytes += bytes;
6621 }
6622 }
1a51502b 6623 rcu_read_unlock();
de1036b1
ED		 6624 /* following stats updated by ixgbe_watchdog_task() */
6625 stats->multicast = netdev->stats.multicast;
6626 stats->rx_errors = netdev->stats.rx_errors;
6627 stats->rx_length_errors = netdev->stats.rx_length_errors;
6628 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6629 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6630 return stats;
6631}
6632
8af3c33f 6633#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6634/**
6635 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6636 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6637 * @tc: number of traffic classes currently enabled
6638 *
6639 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6640 * 802.1Q priority maps to a packet buffer that exists.
6641 */
6642static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6643{
6644 struct ixgbe_hw *hw = &adapter->hw;
6645 u32 reg, rsave;
6646 int i;
6647
6648 /* 82598 have a static priority to TC mapping that can not
6649 * be changed so no validation is needed.
6650 */
6651 if (hw->mac.type == ixgbe_mac_82598EB)
6652 return;
6653
6654 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6655 rsave = reg;
6656
6657 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6658 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6659
6660 /* If up2tc is out of bounds default to zero */
6661 if (up2tc > tc)
6662 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6663 }
6664
6665 if (reg != rsave)
6666 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6667
6668 return;
6669}
6670
02debdc9
AD		 6671/**
6672 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6673 * @adapter: Pointer to adapter struct
6674 *
6675 * Populate the netdev user priority to tc map
6676 */
6677static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6678{
6679 struct net_device *dev = adapter->netdev;
6680 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6681 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6682 u8 prio;
6683
6684 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
6685 u8 tc = 0;
6686
6687 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
6688 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
6689 else if (ets)
6690 tc = ets->prio_tc[prio];
6691
6692 netdev_set_prio_tc_map(dev, prio, tc);
6693 }
6694}
6695
49ce9c2c
BH		 6696/**
6697 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 6698 *
6699 * @netdev: net device to configure
6700 * @tc: number of traffic classes to enable
6701 */
6702int ixgbe_setup_tc(struct net_device *dev, u8 tc)
6703{
8b1c0b24
JF		 6704 struct ixgbe_adapter *adapter = netdev_priv(dev);
6705 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 6706
8b1c0b24 6707 /* Hardware supports up to 8 traffic classes */
4de2a022 6708 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 6709 (hw->mac.type == ixgbe_mac_82598EB &&
6710 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 6711 return -EINVAL;
6712
6713 /* Hardware has to reinitialize queues and interrupts to
52f33af8 6714 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 6715 * hardware is not flexible enough to do this dynamically.
6716 */
6717 if (netif_running(dev))
6718 ixgbe_close(dev);
6719 ixgbe_clear_interrupt_scheme(adapter);
6720
e7589eab 6721 if (tc) {
8b1c0b24 6722 netdev_set_num_tc(dev, tc);
02debdc9
AD		 6723 ixgbe_set_prio_tc_map(adapter);
6724
e7589eab 6725 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 6726
943561d3
AD		 6727 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
6728 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 6729 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 6730 }
e7589eab 6731 } else {
8b1c0b24 6732 netdev_reset_tc(dev);
02debdc9 6733
943561d3
AD		 6734 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6735 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 6736
6737 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 6738
6739 adapter->temp_dcb_cfg.pfc_mode_enable = false;
6740 adapter->dcb_cfg.pfc_mode_enable = false;
6741 }
6742
8b1c0b24
JF		 6743 ixgbe_init_interrupt_scheme(adapter);
6744 ixgbe_validate_rtr(adapter, tc);
6745 if (netif_running(dev))
6746 ixgbe_open(dev);
6747
6748 return 0;
6749}
de1036b1 6750
8af3c33f 6751#endif /* CONFIG_IXGBE_DCB */
082757af
DS		 6752void ixgbe_do_reset(struct net_device *netdev)
6753{
6754 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6755
6756 if (netif_running(netdev))
6757 ixgbe_reinit_locked(adapter);
6758 else
6759 ixgbe_reset(adapter);
6760}
6761
c8f44aff 6762static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 6763 netdev_features_t features)
082757af
DS		 6764{
6765 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6766
082757af 6767 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 6768 if (!(features & NETIF_F_RXCSUM))
6769 features &= ~NETIF_F_LRO;
082757af 6770
567d2de2
AD		 6771 /* Turn off LRO if not RSC capable */
6772 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
6773 features &= ~NETIF_F_LRO;
8e2813f5 6774
567d2de2 6775 return features;
082757af
DS		 6776}
6777
c8f44aff 6778static int ixgbe_set_features(struct net_device *netdev,
567d2de2 6779 netdev_features_t features)
082757af
DS		 6780{
6781 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 6782 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 6783 bool need_reset = false;
6784
082757af 6785 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 6786 if (!(features & NETIF_F_LRO)) {
6787 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 6788 need_reset = true;
567d2de2
AD		 6789 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
6790 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
6791 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
6792 if (adapter->rx_itr_setting == 1 ||
6793 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
6794 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
6795 need_reset = true;
6796 } else if ((changed ^ features) & NETIF_F_LRO) {
6797 e_info(probe, "rx-usecs set too low, "
6798 "disabling RSC\n");
082757af
DS		 6799 }
6800 }
6801
6802 /*
6803 * Check if Flow Director n-tuple support was enabled or disabled. If
6804 * the state changed, we need to reset.
6805 */
39cb681b
AD		 6806 switch (features & NETIF_F_NTUPLE) {
6807 case NETIF_F_NTUPLE:
567d2de2 6808 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 6809 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
6810 need_reset = true;
6811
567d2de2
AD		 6812 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
6813 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 6814 break;
6815 default:
6816 /* turn off perfect filters, enable ATR and reset */
6817 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
6818 need_reset = true;
6819
6820 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
6821
6822 /* We cannot enable ATR if SR-IOV is enabled */
6823 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6824 break;
6825
6826 /* We cannot enable ATR if we have 2 or more traffic classes */
6827 if (netdev_get_num_tc(netdev) > 1)
6828 break;
6829
6830 /* We cannot enable ATR if RSS is disabled */
6831 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
6832 break;
6833
6834 /* A sample rate of 0 indicates ATR disabled */
6835 if (!adapter->atr_sample_rate)
6836 break;
6837
6838 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
6839 break;
082757af
DS		 6840 }
6841
146d4cc9
JF		 6842 if (features & NETIF_F_HW_VLAN_RX)
6843 ixgbe_vlan_strip_enable(adapter);
6844 else
6845 ixgbe_vlan_strip_disable(adapter);
6846
3f2d1c0f
BG		 6847 if (changed & NETIF_F_RXALL)
6848 need_reset = true;
6849
567d2de2 6850 netdev->features = features;
082757af
DS		 6851 if (need_reset)
6852 ixgbe_do_reset(netdev);
6853
6854 return 0;
082757af
DS		 6855}
6856
0f4b0add
JF		 6857static int ixgbe_ndo_fdb_add(struct ndmsg *ndm,
6858 struct net_device *dev,
6859 unsigned char *addr,
6860 u16 flags)
6861{
6862 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 6863 int err;
6864
6865 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
6866 return -EOPNOTSUPP;
0f4b0add
JF		 6867
6868 if (ndm->ndm_state & NUD_PERMANENT) {
6869 pr_info("%s: FDB only supports static addresses\n",
6870 ixgbe_driver_name);
6871 return -EINVAL;
6872 }
6873
95447461
JF		 6874 if (is_unicast_ether_addr(addr)) {
6875 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
6876
6877 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 6878 err = dev_uc_add_excl(dev, addr);
0f4b0add 6879 else
95447461
JF		 6880 err = -ENOMEM;
6881 } else if (is_multicast_ether_addr(addr)) {
6882 err = dev_mc_add_excl(dev, addr);
6883 } else {
6884 err = -EINVAL;
0f4b0add
JF		 6885 }
6886
6887 /* Only return duplicate errors if NLM_F_EXCL is set */
6888 if (err == -EEXIST && !(flags & NLM_F_EXCL))
6889 err = 0;
6890
6891 return err;
6892}
6893
6894static int ixgbe_ndo_fdb_del(struct ndmsg *ndm,
6895 struct net_device *dev,
6896 unsigned char *addr)
6897{
6898 struct ixgbe_adapter *adapter = netdev_priv(dev);
6899 int err = -EOPNOTSUPP;
6900
6901 if (ndm->ndm_state & NUD_PERMANENT) {
6902 pr_info("%s: FDB only supports static addresses\n",
6903 ixgbe_driver_name);
6904 return -EINVAL;
6905 }
6906
6907 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
6908 if (is_unicast_ether_addr(addr))
6909 err = dev_uc_del(dev, addr);
6910 else if (is_multicast_ether_addr(addr))
6911 err = dev_mc_del(dev, addr);
6912 else
6913 err = -EINVAL;
6914 }
6915
6916 return err;
6917}
6918
6919static int ixgbe_ndo_fdb_dump(struct sk_buff *skb,
6920 struct netlink_callback *cb,
6921 struct net_device *dev,
6922 int idx)
6923{
6924 struct ixgbe_adapter *adapter = netdev_priv(dev);
6925
6926 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6927 idx = ndo_dflt_fdb_dump(skb, cb, dev, idx);
6928
6929 return idx;
6930}
6931
0edc3527 6932static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 6933 .ndo_open = ixgbe_open,
0edc3527 6934 .ndo_stop = ixgbe_close,
00829823 6935 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 6936 .ndo_select_queue = ixgbe_select_queue,
581330ba 6937 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 6938 .ndo_validate_addr = eth_validate_addr,
6939 .ndo_set_mac_address = ixgbe_set_mac,
6940 .ndo_change_mtu = ixgbe_change_mtu,
6941 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 6942 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6943 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 6944 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 6945 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6946 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6947 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 6948 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 6949 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 6950 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 6951#ifdef CONFIG_IXGBE_DCB
24095aa3 6952 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 6953#endif
0edc3527
SH		 6954#ifdef CONFIG_NET_POLL_CONTROLLER
6955 .ndo_poll_controller = ixgbe_netpoll,
6956#endif
332d4a7d
YZ		 6957#ifdef IXGBE_FCOE
6958 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 6959 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 6960 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 6961 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6962 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 6963 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 6964 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 6965#endif /* IXGBE_FCOE */
082757af
DS		 6966 .ndo_set_features = ixgbe_set_features,
6967 .ndo_fix_features = ixgbe_fix_features,
0f4b0add
JF		 6968 .ndo_fdb_add = ixgbe_ndo_fdb_add,
6969 .ndo_fdb_del = ixgbe_ndo_fdb_del,
6970 .ndo_fdb_dump = ixgbe_ndo_fdb_dump,
0edc3527
SH		 6971};
6972
8e2813f5
JK		 6973/**
6974 * ixgbe_wol_supported - Check whether device supports WoL
6975 * @hw: hw specific details
6976 * @device_id: the device ID
6977 * @subdev_id: the subsystem device ID
6978 *
6979 * This function is used by probe and ethtool to determine
6980 * which devices have WoL support
6981 *
6982 **/
6983int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
6984 u16 subdevice_id)
6985{
6986 struct ixgbe_hw *hw = &adapter->hw;
6987 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
6988 int is_wol_supported = 0;
6989
6990 switch (device_id) {
6991 case IXGBE_DEV_ID_82599_SFP:
6992 /* Only these subdevices could supports WOL */
6993 switch (subdevice_id) {
6994 case IXGBE_SUBDEV_ID_82599_560FLR:
6995 /* only support first port */
6996 if (hw->bus.func != 0)
6997 break;
6998 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 6999 case IXGBE_SUBDEV_ID_82599_RNDC:
8e2813f5
JK		 7000 is_wol_supported = 1;
7001 break;
7002 }
7003 break;
7004 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7005 /* All except this subdevice support WOL */
7006 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7007 is_wol_supported = 1;
7008 break;
7009 case IXGBE_DEV_ID_82599_KX4:
7010 is_wol_supported = 1;
7011 break;
7012 case IXGBE_DEV_ID_X540T:
7013 /* check eeprom to see if enabled wol */
7014 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7015 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7016 (hw->bus.func == 0))) {
7017 is_wol_supported = 1;
7018 }
7019 break;
7020 }
7021
7022 return is_wol_supported;
7023}
7024
9a799d71
AK		 7025/**
7026 * ixgbe_probe - Device Initialization Routine
7027 * @pdev: PCI device information struct
7028 * @ent: entry in ixgbe_pci_tbl
7029 *
7030 * Returns 0 on success, negative on failure
7031 *
7032 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7033 * The OS initialization, configuring of the adapter private structure,
7034 * and a hardware reset occur.
7035 **/
7036static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7037 const struct pci_device_id *ent)
9a799d71
AK		 7038{
7039 struct net_device *netdev;
7040 struct ixgbe_adapter *adapter = NULL;
7041 struct ixgbe_hw *hw;
7042 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7043 static int cards_found;
7044 int i, err, pci_using_dac;
289700db 7045 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7046 unsigned int indices = num_possible_cpus();
3f4a6f00 7047 unsigned int dcb_max = 0;
eacd73f7
YZ		 7048#ifdef IXGBE_FCOE
7049 u16 device_caps;
7050#endif
289700db 7051 u32 eec;
9a799d71 7052
bded64a7
AG		 7053 /* Catch broken hardware that put the wrong VF device ID in
7054 * the PCIe SR-IOV capability.
7055 */
7056 if (pdev->is_virtfn) {
7057 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7058 pci_name(pdev), pdev->vendor, pdev->device);
7059 return -EINVAL;
7060 }
7061
9ce77666 7062 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7063 if (err)
7064 return err;
7065
1b507730
NN		 7066 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7067 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7068 pci_using_dac = 1;
7069 } else {
1b507730 7070 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7071 if (err) {
1b507730
NN		 7072 err = dma_set_coherent_mask(&pdev->dev,
7073 DMA_BIT_MASK(32));
9a799d71 7074 if (err) {
b8bc0421
DC		 7075 dev_err(&pdev->dev,
7076 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7077 goto err_dma;
7078 }
7079 }
7080 pci_using_dac = 0;
7081 }
7082
9ce77666 7083 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7084 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7085 if (err) {
b8bc0421
DC		 7086 dev_err(&pdev->dev,
7087 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7088 goto err_pci_reg;
7089 }
7090
19d5afd4 7091 pci_enable_pcie_error_reporting(pdev);
6fabd715 7092
9a799d71 7093 pci_set_master(pdev);
fb3b27bc 7094 pci_save_state(pdev);
9a799d71 7095
e901acd6 7096#ifdef CONFIG_IXGBE_DCB
3f4a6f00
JF		 7097 if (ii->mac == ixgbe_mac_82598EB)
7098 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7099 IXGBE_MAX_RSS_INDICES);
7100 else
7101 dcb_max = min_t(unsigned int, indices * MAX_TRAFFIC_CLASS,
7102 IXGBE_MAX_FDIR_INDICES);
e901acd6
JF		 7103#endif
7104
c85a2618
JF		 7105 if (ii->mac == ixgbe_mac_82598EB)
7106 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7107 else
7108 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7109
e901acd6 7110#ifdef IXGBE_FCOE
c85a2618
JF		 7111 indices += min_t(unsigned int, num_possible_cpus(),
7112 IXGBE_MAX_FCOE_INDICES);
7113#endif
3f4a6f00 7114 indices = max_t(unsigned int, dcb_max, indices);
c85a2618 7115 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7116 if (!netdev) {
7117 err = -ENOMEM;
7118 goto err_alloc_etherdev;
7119 }
7120
9a799d71
AK		 7121 SET_NETDEV_DEV(netdev, &pdev->dev);
7122
9a799d71 7123 adapter = netdev_priv(netdev);
c60fbb00 7124 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7125
7126 adapter->netdev = netdev;
7127 adapter->pdev = pdev;
7128 hw = &adapter->hw;
7129 hw->back = adapter;
b3f4d599 7130 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7131
05857980 7132 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7133 pci_resource_len(pdev, 0));
9a799d71
AK		 7134 if (!hw->hw_addr) {
7135 err = -EIO;
7136 goto err_ioremap;
7137 }
7138
7139 for (i = 1; i <= 5; i++) {
7140 if (pci_resource_len(pdev, i) == 0)
7141 continue;
7142 }
7143
0edc3527 7144 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7145 ixgbe_set_ethtool_ops(netdev);
9a799d71 7146 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7147 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7148
9a799d71
AK		 7149 adapter->bd_number = cards_found;
7150
9a799d71
AK		 7151 /* Setup hw api */
7152 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7153 hw->mac.type = ii->mac;
9a799d71 7154
c44ade9e
JB		 7155 /* EEPROM */
7156 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7157 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7158 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7159 if (!(eec & (1 << 8)))
7160 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7161
7162 /* PHY */
7163 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7164 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7165 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7166 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7167 hw->phy.mdio.mmds = 0;
7168 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7169 hw->phy.mdio.dev = netdev;
7170 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7171 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7172
8ca783ab 7173 ii->get_invariants(hw);
9a799d71
AK		 7174
7175 /* setup the private structure */
7176 err = ixgbe_sw_init(adapter);
7177 if (err)
7178 goto err_sw_init;
7179
e86bff0e 7180 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7181 switch (adapter->hw.mac.type) {
7182 case ixgbe_mac_82599EB:
7183 case ixgbe_mac_X540:
e86bff0e 7184 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7185 break;
7186 default:
7187 break;
7188 }
e86bff0e 7189
bf069c97
DS		 7190 /*
7191 * If there is a fan on this device and it has failed log the
7192 * failure.
7193 */
7194 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7195 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7196 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7197 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7198 }
7199
8ef78adc
PWJ		 7200 if (allow_unsupported_sfp)
7201 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7202
c44ade9e 7203 /* reset_hw fills in the perm_addr as well */
119fc60a 7204 hw->phy.reset_if_overtemp = true;
c44ade9e 7205 err = hw->mac.ops.reset_hw(hw);
119fc60a 7206 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7207 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7208 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7209 err = 0;
7210 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7211 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7212 "module type was detected.\n");
7213 e_dev_err("Reload the driver after installing a supported "
7214 "module.\n");
04f165ef
PW		 7215 goto err_sw_init;
7216 } else if (err) {
849c4542 7217 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7218 goto err_sw_init;
7219 }
7220
99d74487
AD		 7221#ifdef CONFIG_PCI_IOV
7222 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8 7223
99d74487 7224#endif
396e799c 7225 netdev->features = NETIF_F_SG |
e8e9f696 7226 NETIF_F_IP_CSUM |
082757af 7227 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7228 NETIF_F_HW_VLAN_TX |
7229 NETIF_F_HW_VLAN_RX |
082757af
DS		 7230 NETIF_F_HW_VLAN_FILTER |
7231 NETIF_F_TSO |
7232 NETIF_F_TSO6 |
082757af
DS		 7233 NETIF_F_RXHASH |
7234 NETIF_F_RXCSUM;
9a799d71 7235
082757af 7236 netdev->hw_features = netdev->features;
ad31c402 7237
58be7666
DS		 7238 switch (adapter->hw.mac.type) {
7239 case ixgbe_mac_82599EB:
7240 case ixgbe_mac_X540:
45a5ead0 7241 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7242 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7243 NETIF_F_NTUPLE;
58be7666
DS		 7244 break;
7245 default:
7246 break;
7247 }
45a5ead0 7248
3f2d1c0f
BG		 7249 netdev->hw_features |= NETIF_F_RXALL;
7250
ad31c402
JK		 7251 netdev->vlan_features |= NETIF_F_TSO;
7252 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7253 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7254 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7255 netdev->vlan_features |= NETIF_F_SG;
7256
01789349 7257 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7258 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7259
7a6b6f51 7260#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7261 netdev->dcbnl_ops = &dcbnl_ops;
7262#endif
7263
eacd73f7 7264#ifdef IXGBE_FCOE
0d551589 7265 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7266 if (hw->mac.ops.get_device_caps) {
7267 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7268 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7269 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7270 }
7c8ae65a
AD		 7271
7272 adapter->ring_feature[RING_F_FCOE].limit = IXGBE_FCRETA_SIZE;
7273
a58915c7
AD		 7274 netdev->features |= NETIF_F_FSO |
7275 NETIF_F_FCOE_CRC;
7276
7c8ae65a
AD		 7277 netdev->vlan_features |= NETIF_F_FSO |
7278 NETIF_F_FCOE_CRC |
7279 NETIF_F_FCOE_MTU;
5e09d7f6 7280 }
eacd73f7 7281#endif /* IXGBE_FCOE */
7b872a55 7282 if (pci_using_dac) {
9a799d71 7283 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7284 netdev->vlan_features |= NETIF_F_HIGHDMA;
7285 }
9a799d71 7286
082757af
DS		 7287 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7288 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7289 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7290 netdev->features |= NETIF_F_LRO;
7291
9a799d71 7292 /* make sure the EEPROM is good */
c44ade9e 7293 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7294 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7295 err = -EIO;
35937c05 7296 goto err_sw_init;
9a799d71
AK		 7297 }
7298
7299 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7300 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7301
c44ade9e 7302 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7303 e_dev_err("invalid MAC address\n");
9a799d71 7304 err = -EIO;
35937c05 7305 goto err_sw_init;
9a799d71
AK		 7306 }
7307
7086400d 7308 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7309 (unsigned long) adapter);
9a799d71 7310
7086400d
AD		 7311 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7312 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7313
021230d4
AV		 7314 err = ixgbe_init_interrupt_scheme(adapter);
7315 if (err)
7316 goto err_sw_init;
9a799d71 7317
8e2813f5 7318 /* WOL not supported for all devices */
c23f5b6b 7319 adapter->wol = 0;
8e2813f5
JK		 7320 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7321 if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device))
9417c464 7322 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7323
e8e26350
PW		 7324 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7325
3a6a4eda
JK		 7326#ifdef CONFIG_IXGBE_PTP
7327 ixgbe_ptp_init(adapter);
7328#endif /* CONFIG_IXGBE_PTP*/
7329
15e5209f
ET		 7330 /* save off EEPROM version number */
7331 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7332 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7333
04f165ef
PW		 7334 /* pick up the PCI bus settings for reporting later */
7335 hw->mac.ops.get_bus_info(hw);
7336
9a799d71 7337 /* print bus type/speed/width info */
849c4542 7338 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7339 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7340 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7341 "Unknown"),
7342 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7343 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7344 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7345 "Unknown"),
7346 netdev->dev_addr);
289700db
DS		 7347
7348 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7349 if (err)
9fe93afd 7350 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7351 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7352 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7353 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7354 part_str);
e8e26350 7355 else
289700db
DS		 7356 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7357 hw->mac.type, hw->phy.type, part_str);
9a799d71 7358
e8e26350 7359 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7360 e_dev_warn("PCI-Express bandwidth available for this card is "
7361 "not sufficient for optimal performance.\n");
7362 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7363 "is required.\n");
0c254d86
AK		 7364 }
7365
9a799d71 7366 /* reset the hardware with the new settings */
794caeb2 7367 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7368 if (err == IXGBE_ERR_EEPROM_VERSION) {
7369 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7370 e_dev_warn("This device is a pre-production adapter/LOM. "
7371 "Please be aware there may be issues associated "
7372 "with your hardware. If you are experiencing "
7373 "problems please contact your Intel or hardware "
7374 "representative who provided you with this "
7375 "hardware.\n");
794caeb2 7376 }
9a799d71
AK		 7377 strcpy(netdev->name, "eth%d");
7378 err = register_netdev(netdev);
7379 if (err)
7380 goto err_register;
7381
93d3ce8f
ET		 7382 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7383 if (hw->mac.ops.disable_tx_laser &&
7384 ((hw->phy.multispeed_fiber) ||
7385 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7386 (hw->mac.type == ixgbe_mac_82599EB))))
7387 hw->mac.ops.disable_tx_laser(hw);
7388
54386467
JB		 7389 /* carrier off reporting is important to ethtool even BEFORE open */
7390 netif_carrier_off(netdev);
7391
5dd2d332 7392#ifdef CONFIG_IXGBE_DCA
652f093f 7393 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7394 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7395 ixgbe_setup_dca(adapter);
7396 }
7397#endif
1cdd1ec8 7398 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7399 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7400 for (i = 0; i < adapter->num_vfs; i++)
7401 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7402 }
7403
2466dd9c
JK		 7404 /* firmware requires driver version to be 0xFFFFFFFF
7405 * since os does not support feature
7406 */
9612de92 7407 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7408 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7409 0xFF);
9612de92 7410
0365e6e4
PW		 7411 /* add san mac addr to netdev */
7412 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7413
ea81875a 7414 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7415 cards_found++;
3ca8bc6d 7416
1210982b 7417#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7418 if (ixgbe_sysfs_init(adapter))
7419 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7420#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7421
9a799d71
AK		 7422 return 0;
7423
7424err_register:
5eba3699 7425 ixgbe_release_hw_control(adapter);
7a921c93 7426 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7427err_sw_init:
99d74487 7428 ixgbe_disable_sriov(adapter);
7086400d 7429 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7430 iounmap(hw->hw_addr);
7431err_ioremap:
7432 free_netdev(netdev);
7433err_alloc_etherdev:
e8e9f696
JP		 7434 pci_release_selected_regions(pdev,
7435 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7436err_pci_reg:
7437err_dma:
7438 pci_disable_device(pdev);
7439 return err;
7440}
7441
7442/**
7443 * ixgbe_remove - Device Removal Routine
7444 * @pdev: PCI device information struct
7445 *
7446 * ixgbe_remove is called by the PCI subsystem to alert the driver
7447 * that it should release a PCI device. The could be caused by a
7448 * Hot-Plug event, or because the driver is going to be removed from
7449 * memory.
7450 **/
7451static void __devexit ixgbe_remove(struct pci_dev *pdev)
7452{
c60fbb00
AD		 7453 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7454 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7455
7456 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7457 cancel_work_sync(&adapter->service_task);
9a799d71 7458
3a6a4eda
JK		 7459#ifdef CONFIG_IXGBE_PTP
7460 ixgbe_ptp_stop(adapter);
7461#endif
7462
5dd2d332 7463#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7464 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7465 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7466 dca_remove_requester(&pdev->dev);
7467 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7468 }
7469
7470#endif
1210982b 7471#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7472 ixgbe_sysfs_exit(adapter);
1210982b 7473#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7474
0365e6e4
PW		 7475 /* remove the added san mac */
7476 ixgbe_del_sanmac_netdev(netdev);
7477
c4900be0
DS		 7478 if (netdev->reg_state == NETREG_REGISTERED)
7479 unregister_netdev(netdev);
9a799d71 7480
9297127b 7481 ixgbe_disable_sriov(adapter);
1cdd1ec8 7482
7a921c93 7483 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7484
021230d4 7485 ixgbe_release_hw_control(adapter);
9a799d71 7486
2b1588c3
AD		 7487#ifdef CONFIG_DCB
7488 kfree(adapter->ixgbe_ieee_pfc);
7489 kfree(adapter->ixgbe_ieee_ets);
7490
7491#endif
9a799d71 7492 iounmap(adapter->hw.hw_addr);
9ce77666 7493 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7494 IORESOURCE_MEM));
9a799d71 7495
849c4542 7496 e_dev_info("complete\n");
021230d4 7497
9a799d71
AK		 7498 free_netdev(netdev);
7499
19d5afd4 7500 pci_disable_pcie_error_reporting(pdev);
6fabd715 7501
9a799d71
AK		 7502 pci_disable_device(pdev);
7503}
7504
7505/**
7506 * ixgbe_io_error_detected - called when PCI error is detected
7507 * @pdev: Pointer to PCI device
7508 * @state: The current pci connection state
7509 *
7510 * This function is called after a PCI bus error affecting
7511 * this device has been detected.
7512 */
7513static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7514 pci_channel_state_t state)
9a799d71 7515{
c60fbb00
AD		 7516 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7517 struct net_device *netdev = adapter->netdev;
9a799d71 7518
83c61fa9
GR		 7519#ifdef CONFIG_PCI_IOV
7520 struct pci_dev *bdev, *vfdev;
7521 u32 dw0, dw1, dw2, dw3;
7522 int vf, pos;
7523 u16 req_id, pf_func;
7524
7525 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7526 adapter->num_vfs == 0)
7527 goto skip_bad_vf_detection;
7528
7529 bdev = pdev->bus->self;
7530 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7531 bdev = bdev->bus->self;
7532
7533 if (!bdev)
7534 goto skip_bad_vf_detection;
7535
7536 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7537 if (!pos)
7538 goto skip_bad_vf_detection;
7539
7540 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7541 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7542 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7543 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7544
7545 req_id = dw1 >> 16;
7546 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7547 if (!(req_id & 0x0080))
7548 goto skip_bad_vf_detection;
7549
7550 pf_func = req_id & 0x01;
7551 if ((pf_func & 1) == (pdev->devfn & 1)) {
7552 unsigned int device_id;
7553
7554 vf = (req_id & 0x7F) >> 1;
7555 e_dev_err("VF %d has caused a PCIe error\n", vf);
7556 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7557 "%8.8x\tdw3: %8.8x\n",
7558 dw0, dw1, dw2, dw3);
7559 switch (adapter->hw.mac.type) {
7560 case ixgbe_mac_82599EB:
7561 device_id = IXGBE_82599_VF_DEVICE_ID;
7562 break;
7563 case ixgbe_mac_X540:
7564 device_id = IXGBE_X540_VF_DEVICE_ID;
7565 break;
7566 default:
7567 device_id = 0;
7568 break;
7569 }
7570
7571 /* Find the pci device of the offending VF */
36e90319 7572 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7573 while (vfdev) {
7574 if (vfdev->devfn == (req_id & 0xFF))
7575 break;
36e90319 7576 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7577 device_id, vfdev);
7578 }
7579 /*
7580 * There's a slim chance the VF could have been hot plugged,
7581 * so if it is no longer present we don't need to issue the
7582 * VFLR. Just clean up the AER in that case.
7583 */
7584 if (vfdev) {
7585 e_dev_err("Issuing VFLR to VF %d\n", vf);
7586 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7587 }
7588
7589 pci_cleanup_aer_uncorrect_error_status(pdev);
7590 }
7591
7592 /*
7593 * Even though the error may have occurred on the other port
7594 * we still need to increment the vf error reference count for
7595 * both ports because the I/O resume function will be called
7596 * for both of them.
7597 */
7598 adapter->vferr_refcount++;
7599
7600 return PCI_ERS_RESULT_RECOVERED;
7601
7602skip_bad_vf_detection:
7603#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7604 netif_device_detach(netdev);
7605
3044b8d1
BL		 7606 if (state == pci_channel_io_perm_failure)
7607 return PCI_ERS_RESULT_DISCONNECT;
7608
9a799d71
AK		 7609 if (netif_running(netdev))
7610 ixgbe_down(adapter);
7611 pci_disable_device(pdev);
7612
b4617240 7613 /* Request a slot reset. */
9a799d71
AK		 7614 return PCI_ERS_RESULT_NEED_RESET;
7615}
7616
7617/**
7618 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7619 * @pdev: Pointer to PCI device
7620 *
7621 * Restart the card from scratch, as if from a cold-boot.
7622 */
7623static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7624{
c60fbb00 7625 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7626 pci_ers_result_t result;
7627 int err;
9a799d71 7628
9ce77666 7629 if (pci_enable_device_mem(pdev)) {
396e799c 7630 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7631 result = PCI_ERS_RESULT_DISCONNECT;
7632 } else {
7633 pci_set_master(pdev);
7634 pci_restore_state(pdev);
c0e1f68b 7635 pci_save_state(pdev);
9a799d71 7636
dd4d8ca6 7637 pci_wake_from_d3(pdev, false);
9a799d71 7638
6fabd715 7639 ixgbe_reset(adapter);
88512539 7640 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7641 result = PCI_ERS_RESULT_RECOVERED;
7642 }
7643
7644 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7645 if (err) {
849c4542
ET		 7646 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7647 "failed 0x%0x\n", err);
6fabd715
PWJ		 7648 /* non-fatal, continue */
7649 }
9a799d71 7650
6fabd715 7651 return result;
9a799d71
AK		 7652}
7653
7654/**
7655 * ixgbe_io_resume - called when traffic can start flowing again.
7656 * @pdev: Pointer to PCI device
7657 *
7658 * This callback is called when the error recovery driver tells us that
7659 * its OK to resume normal operation.
7660 */
7661static void ixgbe_io_resume(struct pci_dev *pdev)
7662{
c60fbb00
AD		 7663 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7664 struct net_device *netdev = adapter->netdev;
9a799d71 7665
83c61fa9
GR		 7666#ifdef CONFIG_PCI_IOV
7667 if (adapter->vferr_refcount) {
7668 e_info(drv, "Resuming after VF err\n");
7669 adapter->vferr_refcount--;
7670 return;
7671 }
7672
7673#endif
c7ccde0f
AD		 7674 if (netif_running(netdev))
7675 ixgbe_up(adapter);
9a799d71
AK		 7676
7677 netif_device_attach(netdev);
9a799d71
AK		 7678}
7679
7680static struct pci_error_handlers ixgbe_err_handler = {
7681 .error_detected = ixgbe_io_error_detected,
7682 .slot_reset = ixgbe_io_slot_reset,
7683 .resume = ixgbe_io_resume,
7684};
7685
7686static struct pci_driver ixgbe_driver = {
7687 .name = ixgbe_driver_name,
7688 .id_table = ixgbe_pci_tbl,
7689 .probe = ixgbe_probe,
7690 .remove = __devexit_p(ixgbe_remove),
7691#ifdef CONFIG_PM
7692 .suspend = ixgbe_suspend,
7693 .resume = ixgbe_resume,
7694#endif
7695 .shutdown = ixgbe_shutdown,
7696 .err_handler = &ixgbe_err_handler
7697};
7698
7699/**
7700 * ixgbe_init_module - Driver Registration Routine
7701 *
7702 * ixgbe_init_module is the first routine called when the driver is
7703 * loaded. All it does is register with the PCI subsystem.
7704 **/
7705static int __init ixgbe_init_module(void)
7706{
7707 int ret;
c7689578 7708 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 7709 pr_info("%s\n", ixgbe_copyright);
9a799d71 7710
5dd2d332 7711#ifdef CONFIG_IXGBE_DCA
bd0362dd 7712 dca_register_notify(&dca_notifier);
bd0362dd 7713#endif
5dd2d332 7714
9a799d71
AK		 7715 ret = pci_register_driver(&ixgbe_driver);
7716 return ret;
7717}
b4617240 7718
9a799d71
AK		 7719module_init(ixgbe_init_module);
7720
7721/**
7722 * ixgbe_exit_module - Driver Exit Cleanup Routine
7723 *
7724 * ixgbe_exit_module is called just before the driver is removed
7725 * from memory.
7726 **/
7727static void __exit ixgbe_exit_module(void)
7728{
5dd2d332 7729#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7730 dca_unregister_notify(&dca_notifier);
7731#endif
9a799d71 7732 pci_unregister_driver(&ixgbe_driver);
1a51502b 7733 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 7734}
bd0362dd 7735
5dd2d332 7736#ifdef CONFIG_IXGBE_DCA
bd0362dd 7737static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 7738 void *p)
bd0362dd
JC		 7739{
7740 int ret_val;
7741
7742 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 7743 __ixgbe_notify_dca);
bd0362dd
JC		 7744
7745 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7746}
b453368d 7747
5dd2d332 7748#endif /* CONFIG_IXGBE_DCA */
849c4542 7749
9a799d71
AK		 7750module_exit(ixgbe_exit_module);
7751
7752/* ixgbe_main.c */
Linux kernel - Deliverables
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