projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: add support for new 82599 device id
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
a52055e0 4 Copyright(c) 1999 - 2011 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
75e3d3c6 58#define MAJ 3
19d478bb
DS		 59#define MIN 6
60#define BUILD 7
75e3d3c6 61#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 62 __stringify(BUILD) "-k"
9c8eb720 63const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0
DS		 64static const char ixgbe_copyright[] =
65 "Copyright (c) 1999-2011 Intel Corporation.";
9a799d71
AK		 66
67static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 68 [board_82598] = &ixgbe_82598_info,
e8e26350 69 [board_82599] = &ixgbe_82599_info,
fe15e8e1 70 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 71};
72
73/* ixgbe_pci_tbl - PCI Device ID Table
74 *
75 * Wildcard entries (PCI_ANY_ID) should come last
76 * Last entry must be all 0s
77 *
78 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
79 * Class, Class Mask, private data (not used) }
80 */
a3aa1884 81static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 82 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 110 /* required last entry */
111 {0, }
112};
113MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
114
5dd2d332 115#ifdef CONFIG_IXGBE_DCA
bd0362dd 116static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 117 void *p);
bd0362dd
JC		 118static struct notifier_block dca_notifier = {
119 .notifier_call = ixgbe_notify_dca,
120 .next = NULL,
121 .priority = 0
122};
123#endif
124
1cdd1ec8
GR		 125#ifdef CONFIG_PCI_IOV
126static unsigned int max_vfs;
127module_param(max_vfs, uint, 0);
e8e9f696
JP		 128MODULE_PARM_DESC(max_vfs,
129 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 130#endif /* CONFIG_PCI_IOV */
131
9a799d71
AK		 132MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
133MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
134MODULE_LICENSE("GPL");
135MODULE_VERSION(DRV_VERSION);
136
137#define DEFAULT_DEBUG_LEVEL_SHIFT 3
138
7086400d
AD		 139static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
140{
141 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
142 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
143 schedule_work(&adapter->service_task);
144}
145
146static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
147{
148 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
149
52f33af8 150 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 151 smp_mb__before_clear_bit();
152 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
153}
154
dcd79aeb
TI		 155struct ixgbe_reg_info {
156 u32 ofs;
157 char *name;
158};
159
160static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
161
162 /* General Registers */
163 {IXGBE_CTRL, "CTRL"},
164 {IXGBE_STATUS, "STATUS"},
165 {IXGBE_CTRL_EXT, "CTRL_EXT"},
166
167 /* Interrupt Registers */
168 {IXGBE_EICR, "EICR"},
169
170 /* RX Registers */
171 {IXGBE_SRRCTL(0), "SRRCTL"},
172 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
173 {IXGBE_RDLEN(0), "RDLEN"},
174 {IXGBE_RDH(0), "RDH"},
175 {IXGBE_RDT(0), "RDT"},
176 {IXGBE_RXDCTL(0), "RXDCTL"},
177 {IXGBE_RDBAL(0), "RDBAL"},
178 {IXGBE_RDBAH(0), "RDBAH"},
179
180 /* TX Registers */
181 {IXGBE_TDBAL(0), "TDBAL"},
182 {IXGBE_TDBAH(0), "TDBAH"},
183 {IXGBE_TDLEN(0), "TDLEN"},
184 {IXGBE_TDH(0), "TDH"},
185 {IXGBE_TDT(0), "TDT"},
186 {IXGBE_TXDCTL(0), "TXDCTL"},
187
188 /* List Terminator */
189 {}
190};
191
192
193/*
194 * ixgbe_regdump - register printout routine
195 */
196static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
197{
198 int i = 0, j = 0;
199 char rname[16];
200 u32 regs[64];
201
202 switch (reginfo->ofs) {
203 case IXGBE_SRRCTL(0):
204 for (i = 0; i < 64; i++)
205 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
206 break;
207 case IXGBE_DCA_RXCTRL(0):
208 for (i = 0; i < 64; i++)
209 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
210 break;
211 case IXGBE_RDLEN(0):
212 for (i = 0; i < 64; i++)
213 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
214 break;
215 case IXGBE_RDH(0):
216 for (i = 0; i < 64; i++)
217 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
218 break;
219 case IXGBE_RDT(0):
220 for (i = 0; i < 64; i++)
221 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
222 break;
223 case IXGBE_RXDCTL(0):
224 for (i = 0; i < 64; i++)
225 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
226 break;
227 case IXGBE_RDBAL(0):
228 for (i = 0; i < 64; i++)
229 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
230 break;
231 case IXGBE_RDBAH(0):
232 for (i = 0; i < 64; i++)
233 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
234 break;
235 case IXGBE_TDBAL(0):
236 for (i = 0; i < 64; i++)
237 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
238 break;
239 case IXGBE_TDBAH(0):
240 for (i = 0; i < 64; i++)
241 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
242 break;
243 case IXGBE_TDLEN(0):
244 for (i = 0; i < 64; i++)
245 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
246 break;
247 case IXGBE_TDH(0):
248 for (i = 0; i < 64; i++)
249 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
250 break;
251 case IXGBE_TDT(0):
252 for (i = 0; i < 64; i++)
253 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
254 break;
255 case IXGBE_TXDCTL(0):
256 for (i = 0; i < 64; i++)
257 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
258 break;
259 default:
c7689578 260 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 261 IXGBE_READ_REG(hw, reginfo->ofs));
262 return;
263 }
264
265 for (i = 0; i < 8; i++) {
266 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 267 pr_err("%-15s", rname);
dcd79aeb 268 for (j = 0; j < 8; j++)
c7689578
JP		 269 pr_cont(" %08x", regs[i*8+j]);
270 pr_cont("\n");
dcd79aeb
TI		 271 }
272
273}
274
275/*
276 * ixgbe_dump - Print registers, tx-rings and rx-rings
277 */
278static void ixgbe_dump(struct ixgbe_adapter *adapter)
279{
280 struct net_device *netdev = adapter->netdev;
281 struct ixgbe_hw *hw = &adapter->hw;
282 struct ixgbe_reg_info *reginfo;
283 int n = 0;
284 struct ixgbe_ring *tx_ring;
285 struct ixgbe_tx_buffer *tx_buffer_info;
286 union ixgbe_adv_tx_desc *tx_desc;
287 struct my_u0 { u64 a; u64 b; } *u0;
288 struct ixgbe_ring *rx_ring;
289 union ixgbe_adv_rx_desc *rx_desc;
290 struct ixgbe_rx_buffer *rx_buffer_info;
291 u32 staterr;
292 int i = 0;
293
294 if (!netif_msg_hw(adapter))
295 return;
296
297 /* Print netdevice Info */
298 if (netdev) {
299 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 300 pr_info("Device Name state "
dcd79aeb 301 "trans_start last_rx\n");
c7689578
JP		 302 pr_info("%-15s %016lX %016lX %016lX\n",
303 netdev->name,
304 netdev->state,
305 netdev->trans_start,
306 netdev->last_rx);
dcd79aeb
TI		 307 }
308
309 /* Print Registers */
310 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 311 pr_info(" Register Name Value\n");
dcd79aeb
TI		 312 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
313 reginfo->name; reginfo++) {
314 ixgbe_regdump(hw, reginfo);
315 }
316
317 /* Print TX Ring Summary */
318 if (!netdev || !netif_running(netdev))
319 goto exit;
320
321 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 322 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 323 for (n = 0; n < adapter->num_tx_queues; n++) {
324 tx_ring = adapter->tx_ring[n];
325 tx_buffer_info =
326 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 327 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 328 n, tx_ring->next_to_use, tx_ring->next_to_clean,
329 (u64)tx_buffer_info->dma,
330 tx_buffer_info->length,
331 tx_buffer_info->next_to_watch,
332 (u64)tx_buffer_info->time_stamp);
333 }
334
335 /* Print TX Rings */
336 if (!netif_msg_tx_done(adapter))
337 goto rx_ring_summary;
338
339 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
340
341 /* Transmit Descriptor Formats
342 *
343 * Advanced Transmit Descriptor
344 * +--------------------------------------------------------------+
345 * 0 | Buffer Address [63:0] |
346 * +--------------------------------------------------------------+
347 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
348 * +--------------------------------------------------------------+
349 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
350 */
351
352 for (n = 0; n < adapter->num_tx_queues; n++) {
353 tx_ring = adapter->tx_ring[n];
c7689578
JP		 354 pr_info("------------------------------------\n");
355 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
356 pr_info("------------------------------------\n");
357 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 358 "[PlPOIdStDDt Ln] [bi->dma ] "
359 "leng ntw timestamp bi->skb\n");
360
361 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
31f05a2d 362 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
dcd79aeb
TI		 363 tx_buffer_info = &tx_ring->tx_buffer_info[i];
364 u0 = (struct my_u0 *)tx_desc;
c7689578 365 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 366 " %04X %p %016llX %p", i,
dcd79aeb
TI		 367 le64_to_cpu(u0->a),
368 le64_to_cpu(u0->b),
369 (u64)tx_buffer_info->dma,
370 tx_buffer_info->length,
371 tx_buffer_info->next_to_watch,
372 (u64)tx_buffer_info->time_stamp,
373 tx_buffer_info->skb);
374 if (i == tx_ring->next_to_use &&
375 i == tx_ring->next_to_clean)
c7689578 376 pr_cont(" NTC/U\n");
dcd79aeb 377 else if (i == tx_ring->next_to_use)
c7689578 378 pr_cont(" NTU\n");
dcd79aeb 379 else if (i == tx_ring->next_to_clean)
c7689578 380 pr_cont(" NTC\n");
dcd79aeb 381 else
c7689578 382 pr_cont("\n");
dcd79aeb
TI		 383
384 if (netif_msg_pktdata(adapter) &&
385 tx_buffer_info->dma != 0)
386 print_hex_dump(KERN_INFO, "",
387 DUMP_PREFIX_ADDRESS, 16, 1,
388 phys_to_virt(tx_buffer_info->dma),
389 tx_buffer_info->length, true);
390 }
391 }
392
393 /* Print RX Rings Summary */
394rx_ring_summary:
395 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 396 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 397 for (n = 0; n < adapter->num_rx_queues; n++) {
398 rx_ring = adapter->rx_ring[n];
c7689578
JP		 399 pr_info("%5d %5X %5X\n",
400 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 401 }
402
403 /* Print RX Rings */
404 if (!netif_msg_rx_status(adapter))
405 goto exit;
406
407 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
408
409 /* Advanced Receive Descriptor (Read) Format
410 * 63 1 0
411 * +-----------------------------------------------------+
412 * 0 | Packet Buffer Address [63:1] |A0/NSE|
413 * +----------------------------------------------+------+
414 * 8 | Header Buffer Address [63:1] | DD |
415 * +-----------------------------------------------------+
416 *
417 *
418 * Advanced Receive Descriptor (Write-Back) Format
419 *
420 * 63 48 47 32 31 30 21 20 16 15 4 3 0
421 * +------------------------------------------------------+
422 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
423 * | Checksum Ident | | | | Type | Type |
424 * +------------------------------------------------------+
425 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
426 * +------------------------------------------------------+
427 * 63 48 47 32 31 20 19 0
428 */
429 for (n = 0; n < adapter->num_rx_queues; n++) {
430 rx_ring = adapter->rx_ring[n];
c7689578
JP		 431 pr_info("------------------------------------\n");
432 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
433 pr_info("------------------------------------\n");
434 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 435 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
436 "<-- Adv Rx Read format\n");
c7689578 437 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 438 "[vl er S cks ln] ---------------- [bi->skb] "
439 "<-- Adv Rx Write-Back format\n");
440
441 for (i = 0; i < rx_ring->count; i++) {
442 rx_buffer_info = &rx_ring->rx_buffer_info[i];
31f05a2d 443 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
dcd79aeb
TI		 444 u0 = (struct my_u0 *)rx_desc;
445 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
446 if (staterr & IXGBE_RXD_STAT_DD) {
447 /* Descriptor Done */
c7689578 448 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 449 "%016llX ---------------- %p", i,
450 le64_to_cpu(u0->a),
451 le64_to_cpu(u0->b),
452 rx_buffer_info->skb);
453 } else {
c7689578 454 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 455 "%016llX %016llX %p", i,
456 le64_to_cpu(u0->a),
457 le64_to_cpu(u0->b),
458 (u64)rx_buffer_info->dma,
459 rx_buffer_info->skb);
460
461 if (netif_msg_pktdata(adapter)) {
462 print_hex_dump(KERN_INFO, "",
463 DUMP_PREFIX_ADDRESS, 16, 1,
464 phys_to_virt(rx_buffer_info->dma),
465 rx_ring->rx_buf_len, true);
466
467 if (rx_ring->rx_buf_len
919e78a6 468 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(
472 rx_buffer_info->page_dma +
473 rx_buffer_info->page_offset
474 ),
475 PAGE_SIZE/2, true);
476 }
477 }
478
479 if (i == rx_ring->next_to_use)
c7689578 480 pr_cont(" NTU\n");
dcd79aeb 481 else if (i == rx_ring->next_to_clean)
c7689578 482 pr_cont(" NTC\n");
dcd79aeb 483 else
c7689578 484 pr_cont("\n");
dcd79aeb
TI		 485
486 }
487 }
488
489exit:
490 return;
491}
492
5eba3699
AV		 493static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
494{
495 u32 ctrl_ext;
496
497 /* Let firmware take over control of h/w */
498 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
499 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 500 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 501}
502
503static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
504{
505 u32 ctrl_ext;
506
507 /* Let firmware know the driver has taken over */
508 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
509 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 510 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 511}
9a799d71 512
e8e26350
PW		 513/*
514 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
515 * @adapter: pointer to adapter struct
516 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
517 * @queue: queue to map the corresponding interrupt to
518 * @msix_vector: the vector to map to the corresponding queue
519 *
520 */
521static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 522 u8 queue, u8 msix_vector)
9a799d71
AK		 523{
524 u32 ivar, index;
e8e26350
PW		 525 struct ixgbe_hw *hw = &adapter->hw;
526 switch (hw->mac.type) {
527 case ixgbe_mac_82598EB:
528 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
529 if (direction == -1)
530 direction = 0;
531 index = (((direction * 64) + queue) >> 2) & 0x1F;
532 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
533 ivar &= ~(0xFF << (8 * (queue & 0x3)));
534 ivar |= (msix_vector << (8 * (queue & 0x3)));
535 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
536 break;
537 case ixgbe_mac_82599EB:
b93a2226 538 case ixgbe_mac_X540:
e8e26350
PW		 539 if (direction == -1) {
540 /* other causes */
541 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
542 index = ((queue & 1) * 8);
543 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
544 ivar &= ~(0xFF << index);
545 ivar |= (msix_vector << index);
546 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
547 break;
548 } else {
549 /* tx or rx causes */
550 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
551 index = ((16 * (queue & 1)) + (8 * direction));
552 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
553 ivar &= ~(0xFF << index);
554 ivar |= (msix_vector << index);
555 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
556 break;
557 }
558 default:
559 break;
560 }
9a799d71
AK		 561}
562
fe49f04a 563static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 564 u64 qmask)
fe49f04a
AD		 565{
566 u32 mask;
567
bd508178
AD		 568 switch (adapter->hw.mac.type) {
569 case ixgbe_mac_82598EB:
fe49f04a
AD		 570 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
571 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 572 break;
573 case ixgbe_mac_82599EB:
b93a2226 574 case ixgbe_mac_X540:
fe49f04a
AD		 575 mask = (qmask & 0xFFFFFFFF);
576 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
577 mask = (qmask >> 32);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 579 break;
580 default:
581 break;
fe49f04a
AD		 582 }
583}
584
d3d00239
AD		 585static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
586 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 587{
d3d00239
AD		 588 if (tx_buffer->dma) {
589 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
590 dma_unmap_page(ring->dev,
591 tx_buffer->dma,
592 tx_buffer->length,
593 DMA_TO_DEVICE);
e5a43549 594 else
d3d00239
AD		 595 dma_unmap_single(ring->dev,
596 tx_buffer->dma,
597 tx_buffer->length,
598 DMA_TO_DEVICE);
e5a43549 599 }
d3d00239
AD		 600 tx_buffer->dma = 0;
601}
602
603void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
604 struct ixgbe_tx_buffer *tx_buffer_info)
605{
606 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
607 if (tx_buffer_info->skb)
9a799d71 608 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 609 tx_buffer_info->skb = NULL;
9a799d71
AK		 610 /* tx_buffer_info must be completely set up in the transmit path */
611}
612
c84d324c
JF		 613static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
614{
615 struct ixgbe_hw *hw = &adapter->hw;
616 struct ixgbe_hw_stats *hwstats = &adapter->stats;
617 u32 data = 0;
618 u32 xoff[8] = {0};
619 int i;
620
621 if ((hw->fc.current_mode == ixgbe_fc_full) ||
622 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
623 switch (hw->mac.type) {
624 case ixgbe_mac_82598EB:
625 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 626 break;
627 default:
c84d324c
JF		 628 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
629 }
630 hwstats->lxoffrxc += data;
631
632 /* refill credits (no tx hang) if we received xoff */
633 if (!data)
634 return;
635
636 for (i = 0; i < adapter->num_tx_queues; i++)
637 clear_bit(__IXGBE_HANG_CHECK_ARMED,
638 &adapter->tx_ring[i]->state);
639 return;
640 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
641 return;
642
643 /* update stats for each tc, only valid with PFC enabled */
644 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
645 switch (hw->mac.type) {
646 case ixgbe_mac_82598EB:
647 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 648 break;
c84d324c
JF		 649 default:
650 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 651 }
c84d324c
JF		 652 hwstats->pxoffrxc[i] += xoff[i];
653 }
654
655 /* disarm tx queues that have received xoff frames */
656 for (i = 0; i < adapter->num_tx_queues; i++) {
657 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 658 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 659
660 if (xoff[tc])
661 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 662 }
26f23d82
YZ		 663}
664
c84d324c 665static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 666{
c84d324c
JF		 667 return ring->tx_stats.completed;
668}
669
670static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
671{
672 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 673 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 674
c84d324c
JF		 675 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
676 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
677
678 if (head != tail)
679 return (head < tail) ?
680 tail - head : (tail + ring->count - head);
681
682 return 0;
683}
684
685static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
686{
687 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
688 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
689 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
690 bool ret = false;
691
7d637bcc 692 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 693
694 /*
695 * Check for a hung queue, but be thorough. This verifies
696 * that a transmit has been completed since the previous
697 * check AND there is at least one packet pending. The
698 * ARMED bit is set to indicate a potential hang. The
699 * bit is cleared if a pause frame is received to remove
700 * false hang detection due to PFC or 802.3x frames. By
701 * requiring this to fail twice we avoid races with
702 * pfc clearing the ARMED bit and conditions where we
703 * run the check_tx_hang logic with a transmit completion
704 * pending but without time to complete it yet.
705 */
706 if ((tx_done_old == tx_done) && tx_pending) {
707 /* make sure it is true for two checks in a row */
708 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
709 &tx_ring->state);
710 } else {
711 /* update completed stats and continue */
712 tx_ring->tx_stats.tx_done_old = tx_done;
713 /* reset the countdown */
714 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 715 }
716
c84d324c 717 return ret;
9a799d71
AK		 718}
719
c83c6cbd
AD		 720/**
721 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
722 * @adapter: driver private struct
723 **/
724static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
725{
726
727 /* Do the reset outside of interrupt context */
728 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
729 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
730 ixgbe_service_event_schedule(adapter);
731 }
732}
e01c31a5 733
9a799d71
AK		 734/**
735 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 736 * @q_vector: structure containing interrupt and ring information
e01c31a5 737 * @tx_ring: tx ring to clean
9a799d71 738 **/
fe49f04a 739static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 740 struct ixgbe_ring *tx_ring)
9a799d71 741{
fe49f04a 742 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 743 struct ixgbe_tx_buffer *tx_buffer;
744 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 745 unsigned int total_bytes = 0, total_packets = 0;
59224555 746 unsigned int budget = q_vector->tx.work_limit;
d3d00239 747 u16 i = tx_ring->next_to_clean;
9a799d71 748
d3d00239
AD		 749 tx_buffer = &tx_ring->tx_buffer_info[i];
750 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
12207e49 751
30065e63 752 for (; budget; budget--) {
d3d00239
AD		 753 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
754
755 /* if next_to_watch is not set then there is no work pending */
756 if (!eop_desc)
757 break;
758
759 /* if DD is not set pending work has not been completed */
760 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
761 break;
8ad494b0 762
d3d00239
AD		 763 /* count the packet as being completed */
764 tx_ring->tx_stats.completed++;
765
766 /* clear next_to_watch to prevent false hangs */
767 tx_buffer->next_to_watch = NULL;
8ad494b0 768
d3d00239
AD		 769 /* prevent any other reads prior to eop_desc being verified */
770 rmb();
771
772 do {
773 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 774 tx_desc->wb.status = 0;
d3d00239
AD		 775 if (likely(tx_desc == eop_desc)) {
776 eop_desc = NULL;
777 dev_kfree_skb_any(tx_buffer->skb);
778 tx_buffer->skb = NULL;
779
780 total_bytes += tx_buffer->bytecount;
781 total_packets += tx_buffer->gso_segs;
782 }
9a799d71 783
d3d00239
AD		 784 tx_buffer++;
785 tx_desc++;
8ad494b0 786 i++;
d3d00239 787 if (unlikely(i == tx_ring->count)) {
8ad494b0 788 i = 0;
e01c31a5 789
d3d00239
AD		 790 tx_buffer = tx_ring->tx_buffer_info;
791 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
e092be60 792 }
e01c31a5 793
d3d00239 794 } while (eop_desc);
12207e49
PWJ		 795 }
796
9a799d71 797 tx_ring->next_to_clean = i;
d3d00239 798 u64_stats_update_begin(&tx_ring->syncp);
b953799e 799 tx_ring->stats.bytes += total_bytes;
bd198058 800 tx_ring->stats.packets += total_packets;
d3d00239 801 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 802 q_vector->tx.total_bytes += total_bytes;
803 q_vector->tx.total_packets += total_packets;
b953799e 804
c84d324c
JF		 805 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
806 /* schedule immediate reset if we believe we hung */
807 struct ixgbe_hw *hw = &adapter->hw;
d3d00239 808 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
c84d324c
JF		 809 e_err(drv, "Detected Tx Unit Hang\n"
810 " Tx Queue <%d>\n"
811 " TDH, TDT <%x>, <%x>\n"
812 " next_to_use <%x>\n"
813 " next_to_clean <%x>\n"
814 "tx_buffer_info[next_to_clean]\n"
815 " time_stamp <%lx>\n"
816 " jiffies <%lx>\n",
817 tx_ring->queue_index,
818 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
819 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 820 tx_ring->next_to_use, i,
821 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 822
823 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
824
825 e_info(probe,
826 "tx hang %d detected on queue %d, resetting adapter\n",
827 adapter->tx_timeout_count + 1, tx_ring->queue_index);
828
b953799e 829 /* schedule immediate reset if we believe we hung */
c83c6cbd 830 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 831
832 /* the adapter is about to reset, no point in enabling stuff */
59224555 833 return true;
b953799e 834 }
9a799d71 835
e092be60 836#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 837 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 838 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 839 /* Make sure that anybody stopping the queue after this
840 * sees the new next_to_clean.
841 */
842 smp_mb();
fc77dc3c 843 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 844 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 845 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 846 ++tx_ring->tx_stats.restart_queue;
30eba97a 847 }
e092be60 848 }
9a799d71 849
59224555 850 return !!budget;
9a799d71
AK		 851}
852
5dd2d332 853#ifdef CONFIG_IXGBE_DCA
bd0362dd 854static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 855 struct ixgbe_ring *rx_ring,
856 int cpu)
bd0362dd 857{
33cf09c9 858 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 859 u32 rxctrl;
33cf09c9
AD		 860 u8 reg_idx = rx_ring->reg_idx;
861
862 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
863 switch (hw->mac.type) {
864 case ixgbe_mac_82598EB:
865 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 866 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 867 break;
868 case ixgbe_mac_82599EB:
b93a2226 869 case ixgbe_mac_X540:
33cf09c9 870 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 871 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 872 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
873 break;
874 default:
875 break;
bd0362dd 876 }
33cf09c9
AD		 877 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
878 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
879 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 880 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 881}
882
883static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 884 struct ixgbe_ring *tx_ring,
885 int cpu)
bd0362dd 886{
33cf09c9 887 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 888 u32 txctrl;
33cf09c9
AD		 889 u8 reg_idx = tx_ring->reg_idx;
890
891 switch (hw->mac.type) {
892 case ixgbe_mac_82598EB:
893 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
894 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 895 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 896 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 897 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
898 break;
899 case ixgbe_mac_82599EB:
b93a2226 900 case ixgbe_mac_X540:
33cf09c9
AD		 901 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
902 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 903 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 904 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
905 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 906 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
907 break;
908 default:
909 break;
910 }
911}
912
913static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
914{
915 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 916 struct ixgbe_ring *ring;
bd0362dd 917 int cpu = get_cpu();
bd0362dd 918
33cf09c9
AD		 919 if (q_vector->cpu == cpu)
920 goto out_no_update;
921
efe3d3c8
AD		 922 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
923 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 924
efe3d3c8
AD		 925 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
926 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 927
928 q_vector->cpu = cpu;
929out_no_update:
bd0362dd
JC		 930 put_cpu();
931}
932
933static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
934{
33cf09c9 935 int num_q_vectors;
bd0362dd
JC		 936 int i;
937
938 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
939 return;
940
e35ec126
AD		 941 /* always use CB2 mode, difference is masked in the CB driver */
942 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
943
33cf09c9
AD		 944 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
945 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
946 else
947 num_q_vectors = 1;
948
949 for (i = 0; i < num_q_vectors; i++) {
950 adapter->q_vector[i]->cpu = -1;
951 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 952 }
953}
954
955static int __ixgbe_notify_dca(struct device *dev, void *data)
956{
c60fbb00 957 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 958 unsigned long event = *(unsigned long *)data;
959
2a72c31e 960 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 961 return 0;
962
bd0362dd
JC		 963 switch (event) {
964 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 965 /* if we're already enabled, don't do it again */
966 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
967 break;
652f093f 968 if (dca_add_requester(dev) == 0) {
96b0e0f6 969 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 970 ixgbe_setup_dca(adapter);
971 break;
972 }
973 /* Fall Through since DCA is disabled. */
974 case DCA_PROVIDER_REMOVE:
975 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
976 dca_remove_requester(dev);
977 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
978 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
979 }
980 break;
981 }
982
652f093f 983 return 0;
bd0362dd 984}
5dd2d332 985#endif /* CONFIG_IXGBE_DCA */
67a74ee2
ET		 986
987static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
988 struct sk_buff *skb)
989{
990 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
991}
992
ff886dfc
AD		 993/**
994 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
995 * @adapter: address of board private structure
996 * @rx_desc: advanced rx descriptor
997 *
998 * Returns : true if it is FCoE pkt
999 */
1000static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1001 union ixgbe_adv_rx_desc *rx_desc)
1002{
1003 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1004
1005 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1006 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1007 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1008 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1009}
1010
9a799d71
AK		 1011/**
1012 * ixgbe_receive_skb - Send a completed packet up the stack
1013 * @adapter: board private structure
1014 * @skb: packet to send up
177db6ff
MC		 1015 * @status: hardware indication of status of receive
1016 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1017 * @rx_desc: rx descriptor
9a799d71 1018 **/
78b6f4ce 1019static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
e8e9f696
JP		 1020 struct sk_buff *skb, u8 status,
1021 struct ixgbe_ring *ring,
1022 union ixgbe_adv_rx_desc *rx_desc)
9a799d71 1023{
78b6f4ce
HX		 1024 struct ixgbe_adapter *adapter = q_vector->adapter;
1025 struct napi_struct *napi = &q_vector->napi;
177db6ff
MC		 1026 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1027 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
9a799d71 1028
f62bbb5e
JG		 1029 if (is_vlan && (tag & VLAN_VID_MASK))
1030 __vlan_hwaccel_put_tag(skb, tag);
1031
1032 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1033 napi_gro_receive(napi, skb);
1034 else
1035 netif_rx(skb);
9a799d71
AK		 1036}
1037
e59bd25d
AV		 1038/**
1039 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1040 * @adapter: address of board private structure
1041 * @status_err: hardware indication of status of receive
1042 * @skb: skb currently being received and modified
ff886dfc 1043 * @status_err: status error value of last descriptor in packet
e59bd25d 1044 **/
9a799d71 1045static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
8bae1b2b 1046 union ixgbe_adv_rx_desc *rx_desc,
ff886dfc
AD		 1047 struct sk_buff *skb,
1048 u32 status_err)
9a799d71 1049{
ff886dfc 1050 skb->ip_summed = CHECKSUM_NONE;
9a799d71 1051
712744be
JB		 1052 /* Rx csum disabled */
1053 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
9a799d71 1054 return;
e59bd25d
AV		 1055
1056 /* if IP and error */
1057 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1058 (status_err & IXGBE_RXDADV_ERR_IPE)) {
9a799d71
AK		 1059 adapter->hw_csum_rx_error++;
1060 return;
1061 }
e59bd25d
AV		 1062
1063 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1064 return;
1065
1066 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
8bae1b2b
DS		 1067 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1068
1069 /*
1070 * 82599 errata, UDP frames with a 0 checksum can be marked as
1071 * checksum errors.
1072 */
1073 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1074 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1075 return;
1076
e59bd25d
AV		 1077 adapter->hw_csum_rx_error++;
1078 return;
1079 }
1080
9a799d71 1081 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1082 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1083}
1084
84ea2591 1085static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350
PW		 1086{
1087 /*
1088 * Force memory writes to complete before letting h/w
1089 * know there are new descriptors to fetch. (Only
1090 * applicable for weak-ordered memory model archs,
1091 * such as IA-64).
1092 */
1093 wmb();
84ea2591 1094 writel(val, rx_ring->tail);
e8e26350
PW		 1095}
1096
9a799d71
AK		 1097/**
1098 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
fc77dc3c
AD		 1099 * @rx_ring: ring to place buffers on
1100 * @cleaned_count: number of buffers to replace
9a799d71 1101 **/
fc77dc3c 1102void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1103{
9a799d71 1104 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1105 struct ixgbe_rx_buffer *bi;
d5f398ed
AD		 1106 struct sk_buff *skb;
1107 u16 i = rx_ring->next_to_use;
9a799d71 1108
fc77dc3c
AD		 1109 /* do nothing if no valid netdev defined */
1110 if (!rx_ring->netdev)
1111 return;
1112
9a799d71 1113 while (cleaned_count--) {
31f05a2d 1114 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
d5f398ed
AD		 1115 bi = &rx_ring->rx_buffer_info[i];
1116 skb = bi->skb;
9a799d71 1117
d5f398ed 1118 if (!skb) {
fc77dc3c 1119 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
d5f398ed 1120 rx_ring->rx_buf_len);
9a799d71 1121 if (!skb) {
5b7da515 1122 rx_ring->rx_stats.alloc_rx_buff_failed++;
9a799d71
AK		 1123 goto no_buffers;
1124 }
d716a7d8
AD		 1125 /* initialize queue mapping */
1126 skb_record_rx_queue(skb, rx_ring->queue_index);
d5f398ed 1127 bi->skb = skb;
d716a7d8 1128 }
9a799d71 1129
d716a7d8 1130 if (!bi->dma) {
b6ec895e 1131 bi->dma = dma_map_single(rx_ring->dev,
d5f398ed 1132 skb->data,
e8e9f696 1133 rx_ring->rx_buf_len,
1b507730 1134 DMA_FROM_DEVICE);
b6ec895e 1135 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
5b7da515 1136 rx_ring->rx_stats.alloc_rx_buff_failed++;
d5f398ed
AD		 1137 bi->dma = 0;
1138 goto no_buffers;
1139 }
9a799d71 1140 }
d5f398ed 1141
7d637bcc 1142 if (ring_is_ps_enabled(rx_ring)) {
d5f398ed 1143 if (!bi->page) {
1f2149c1 1144 bi->page = alloc_page(GFP_ATOMIC | __GFP_COLD);
d5f398ed 1145 if (!bi->page) {
5b7da515 1146 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1147 goto no_buffers;
1148 }
1149 }
1150
1151 if (!bi->page_dma) {
1152 /* use a half page if we're re-using */
1153 bi->page_offset ^= PAGE_SIZE / 2;
b6ec895e 1154 bi->page_dma = dma_map_page(rx_ring->dev,
d5f398ed
AD		 1155 bi->page,
1156 bi->page_offset,
1157 PAGE_SIZE / 2,
1158 DMA_FROM_DEVICE);
b6ec895e 1159 if (dma_mapping_error(rx_ring->dev,
d5f398ed 1160 bi->page_dma)) {
5b7da515 1161 rx_ring->rx_stats.alloc_rx_page_failed++;
d5f398ed
AD		 1162 bi->page_dma = 0;
1163 goto no_buffers;
1164 }
1165 }
1166
1167 /* Refresh the desc even if buffer_addrs didn't change
1168 * because each write-back erases this info. */
3a581073
JB		 1169 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1170 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
9a799d71 1171 } else {
3a581073 1172 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
84418e3b 1173 rx_desc->read.hdr_addr = 0;
9a799d71
AK		 1174 }
1175
1176 i++;
1177 if (i == rx_ring->count)
1178 i = 0;
9a799d71 1179 }
7c6e0a43 1180
9a799d71
AK		 1181no_buffers:
1182 if (rx_ring->next_to_use != i) {
1183 rx_ring->next_to_use = i;
84ea2591 1184 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1185 }
1186}
1187
c267fc16 1188static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1189{
c267fc16
AD		 1190 /* HW will not DMA in data larger than the given buffer, even if it
1191 * parses the (NFS, of course) header to be larger. In that case, it
1192 * fills the header buffer and spills the rest into the page.
1193 */
1194 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1195 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1196 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1197 if (hlen > IXGBE_RX_HDR_SIZE)
1198 hlen = IXGBE_RX_HDR_SIZE;
1199 return hlen;
7c6e0a43
JB		 1200}
1201
f8212f97
AD		 1202/**
1203 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1204 * @skb: pointer to the last skb in the rsc queue
1205 *
1206 * This function changes a queue full of hw rsc buffers into a completed
1207 * packet. It uses the ->prev pointers to find the first packet and then
1208 * turns it into the frag list owner.
1209 **/
aa80175a 1210static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
f8212f97
AD		 1211{
1212 unsigned int frag_list_size = 0;
aa80175a 1213 unsigned int skb_cnt = 1;
f8212f97
AD		 1214
1215 while (skb->prev) {
1216 struct sk_buff *prev = skb->prev;
1217 frag_list_size += skb->len;
1218 skb->prev = NULL;
1219 skb = prev;
aa80175a 1220 skb_cnt++;
f8212f97
AD		 1221 }
1222
1223 skb_shinfo(skb)->frag_list = skb->next;
1224 skb->next = NULL;
1225 skb->len += frag_list_size;
1226 skb->data_len += frag_list_size;
1227 skb->truesize += frag_list_size;
aa80175a
AD		 1228 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1229
f8212f97
AD		 1230 return skb;
1231}
1232
aa80175a
AD		 1233static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1234{
1235 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1236 IXGBE_RXDADV_RSCCNT_MASK);
1237}
43634e82 1238
4ff7fb12 1239static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1240 struct ixgbe_ring *rx_ring,
4ff7fb12 1241 int budget)
9a799d71 1242{
78b6f4ce 1243 struct ixgbe_adapter *adapter = q_vector->adapter;
9a799d71
AK		 1244 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1245 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1246 struct sk_buff *skb;
d2f4fbe2 1247 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1248 const int current_node = numa_node_id();
3d8fd385
YZ		 1249#ifdef IXGBE_FCOE
1250 int ddp_bytes = 0;
1251#endif /* IXGBE_FCOE */
c267fc16
AD		 1252 u32 staterr;
1253 u16 i;
1254 u16 cleaned_count = 0;
aa80175a 1255 bool pkt_is_rsc = false;
9a799d71
AK		 1256
1257 i = rx_ring->next_to_clean;
31f05a2d 1258 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1259 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
9a799d71
AK		 1260
1261 while (staterr & IXGBE_RXD_STAT_DD) {
7c6e0a43 1262 u32 upper_len = 0;
9a799d71 1263
3c945e5b 1264 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1265
c267fc16
AD		 1266 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1267
9a799d71 1268 skb = rx_buffer_info->skb;
9a799d71 1269 rx_buffer_info->skb = NULL;
c267fc16 1270 prefetch(skb->data);
9a799d71 1271
c267fc16 1272 if (ring_is_rsc_enabled(rx_ring))
aa80175a 1273 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
c267fc16 1274
b811ce91
JB		 1275 /* linear means we are building an skb from multiple pages */
1276 if (!skb_is_nonlinear(skb)) {
c267fc16 1277 u16 hlen;
aa80175a 1278 if (pkt_is_rsc &&
c267fc16
AD		 1279 !(staterr & IXGBE_RXD_STAT_EOP) &&
1280 !skb->prev) {
43634e82
MC		 1281 /*
1282 * When HWRSC is enabled, delay unmapping
1283 * of the first packet. It carries the
1284 * header information, HW may still
1285 * access the header after the writeback.
1286 * Only unmap it when EOP is reached
1287 */
e8171aaa 1288 IXGBE_RSC_CB(skb)->delay_unmap = true;
43634e82 1289 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
e8171aaa 1290 } else {
b6ec895e 1291 dma_unmap_single(rx_ring->dev,
e8e9f696
JP		 1292 rx_buffer_info->dma,
1293 rx_ring->rx_buf_len,
1294 DMA_FROM_DEVICE);
e8171aaa 1295 }
4f57ca6e 1296 rx_buffer_info->dma = 0;
c267fc16
AD		 1297
1298 if (ring_is_ps_enabled(rx_ring)) {
1299 hlen = ixgbe_get_hlen(rx_desc);
1300 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1301 } else {
1302 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1303 }
1304
1305 skb_put(skb, hlen);
1306 } else {
1307 /* assume packet split since header is unmapped */
1308 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1309 }
1310
1311 if (upper_len) {
b6ec895e
AD		 1312 dma_unmap_page(rx_ring->dev,
1313 rx_buffer_info->page_dma,
1314 PAGE_SIZE / 2,
1315 DMA_FROM_DEVICE);
9a799d71
AK		 1316 rx_buffer_info->page_dma = 0;
1317 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1318 rx_buffer_info->page,
1319 rx_buffer_info->page_offset,
1320 upper_len);
762f4c57 1321
c267fc16
AD		 1322 if ((page_count(rx_buffer_info->page) == 1) &&
1323 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1324 get_page(rx_buffer_info->page);
c267fc16
AD		 1325 else
1326 rx_buffer_info->page = NULL;
9a799d71
AK		 1327
1328 skb->len += upper_len;
1329 skb->data_len += upper_len;
98130646 1330 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1331 }
1332
1333 i++;
1334 if (i == rx_ring->count)
1335 i = 0;
9a799d71 1336
31f05a2d 1337 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
9a799d71 1338 prefetch(next_rxd);
9a799d71 1339 cleaned_count++;
f8212f97 1340
aa80175a 1341 if (pkt_is_rsc) {
f8212f97
AD		 1342 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1343 IXGBE_RXDADV_NEXTP_SHIFT;
1344 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97
AD		 1345 } else {
1346 next_buffer = &rx_ring->rx_buffer_info[i];
1347 }
1348
c267fc16 1349 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
7d637bcc 1350 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1351 rx_buffer_info->skb = next_buffer->skb;
1352 rx_buffer_info->dma = next_buffer->dma;
1353 next_buffer->skb = skb;
1354 next_buffer->dma = 0;
1355 } else {
1356 skb->next = next_buffer->skb;
1357 skb->next->prev = skb;
1358 }
5b7da515 1359 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1360 goto next_desc;
1361 }
1362
aa80175a
AD		 1363 if (skb->prev) {
1364 skb = ixgbe_transform_rsc_queue(skb);
1365 /* if we got here without RSC the packet is invalid */
1366 if (!pkt_is_rsc) {
1367 __pskb_trim(skb, 0);
1368 rx_buffer_info->skb = skb;
1369 goto next_desc;
1370 }
1371 }
c267fc16
AD		 1372
1373 if (ring_is_rsc_enabled(rx_ring)) {
1374 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1375 dma_unmap_single(rx_ring->dev,
1376 IXGBE_RSC_CB(skb)->dma,
1377 rx_ring->rx_buf_len,
1378 DMA_FROM_DEVICE);
1379 IXGBE_RSC_CB(skb)->dma = 0;
1380 IXGBE_RSC_CB(skb)->delay_unmap = false;
1381 }
aa80175a
AD		 1382 }
1383 if (pkt_is_rsc) {
c267fc16
AD		 1384 if (ring_is_ps_enabled(rx_ring))
1385 rx_ring->rx_stats.rsc_count +=
aa80175a 1386 skb_shinfo(skb)->nr_frags;
c267fc16 1387 else
aa80175a
AD		 1388 rx_ring->rx_stats.rsc_count +=
1389 IXGBE_RSC_CB(skb)->skb_cnt;
c267fc16
AD		 1390 rx_ring->rx_stats.rsc_flush++;
1391 }
1392
1393 /* ERR_MASK will only have valid bits if EOP set */
ff886dfc
AD		 1394 if (unlikely(staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK)) {
1395 dev_kfree_skb_any(skb);
9a799d71
AK		 1396 goto next_desc;
1397 }
1398
ff886dfc 1399 ixgbe_rx_checksum(adapter, rx_desc, skb, staterr);
67a74ee2
ET		 1400 if (adapter->netdev->features & NETIF_F_RXHASH)
1401 ixgbe_rx_hash(rx_desc, skb);
d2f4fbe2
AV		 1402
1403 /* probably a little skewed due to removing CRC */
1404 total_rx_bytes += skb->len;
1405 total_rx_packets++;
1406
fc77dc3c 1407 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
332d4a7d
YZ		 1408#ifdef IXGBE_FCOE
1409 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc
AD		 1410 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
1411 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb,
1412 staterr);
63d635b2
AD		 1413 if (!ddp_bytes) {
1414 dev_kfree_skb_any(skb);
332d4a7d 1415 goto next_desc;
63d635b2 1416 }
3d8fd385 1417 }
332d4a7d 1418#endif /* IXGBE_FCOE */
fdaff1ce 1419 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
9a799d71 1420
4ff7fb12 1421 budget--;
9a799d71
AK		 1422next_desc:
1423 rx_desc->wb.upper.status_error = 0;
1424
4ff7fb12 1425 if (!budget)
c267fc16
AD		 1426 break;
1427
9a799d71
AK		 1428 /* return some buffers to hardware, one at a time is too slow */
1429 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1430 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1431 cleaned_count = 0;
1432 }
1433
1434 /* use prefetched values */
1435 rx_desc = next_rxd;
9a799d71 1436 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
177db6ff
MC		 1437 }
1438
9a799d71 1439 rx_ring->next_to_clean = i;
7d4987de 1440 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1441
1442 if (cleaned_count)
fc77dc3c 1443 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1444
3d8fd385
YZ		 1445#ifdef IXGBE_FCOE
1446 /* include DDPed FCoE data */
1447 if (ddp_bytes > 0) {
1448 unsigned int mss;
1449
fc77dc3c 1450 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1451 sizeof(struct fc_frame_header) -
1452 sizeof(struct fcoe_crc_eof);
1453 if (mss > 512)
1454 mss &= ~511;
1455 total_rx_bytes += ddp_bytes;
1456 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1457 }
1458#endif /* IXGBE_FCOE */
1459
c267fc16
AD		 1460 u64_stats_update_begin(&rx_ring->syncp);
1461 rx_ring->stats.packets += total_rx_packets;
1462 rx_ring->stats.bytes += total_rx_bytes;
1463 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1464 q_vector->rx.total_packets += total_rx_packets;
1465 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1466
1467 return !!budget;
9a799d71
AK		 1468}
1469
9a799d71
AK		 1470/**
1471 * ixgbe_configure_msix - Configure MSI-X hardware
1472 * @adapter: board private structure
1473 *
1474 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1475 * interrupts.
1476 **/
1477static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1478{
021230d4 1479 struct ixgbe_q_vector *q_vector;
efe3d3c8 1480 int q_vectors, v_idx;
021230d4 1481 u32 mask;
9a799d71 1482
021230d4 1483 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1484
8e34d1aa
AD		 1485 /* Populate MSIX to EITR Select */
1486 if (adapter->num_vfs > 32) {
1487 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1488 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1489 }
1490
4df10466
JB		 1491 /*
1492 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1493 * corresponding register.
1494 */
1495 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1496 struct ixgbe_ring *ring;
7a921c93 1497 q_vector = adapter->q_vector[v_idx];
021230d4 1498
efe3d3c8
AD		 1499 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1500 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1501
1502 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1503 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1504
d5bf4f67
ET		 1505 if (q_vector->tx.ring && !q_vector->rx.ring) {
1506 /* tx only vector */
1507 if (adapter->tx_itr_setting == 1)
1508 q_vector->itr = IXGBE_10K_ITR;
1509 else
1510 q_vector->itr = adapter->tx_itr_setting;
1511 } else {
1512 /* rx or rx/tx vector */
1513 if (adapter->rx_itr_setting == 1)
1514 q_vector->itr = IXGBE_20K_ITR;
1515 else
1516 q_vector->itr = adapter->rx_itr_setting;
1517 }
021230d4 1518
fe49f04a 1519 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1520 }
1521
bd508178
AD		 1522 switch (adapter->hw.mac.type) {
1523 case ixgbe_mac_82598EB:
e8e26350 1524 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1525 v_idx);
bd508178
AD		 1526 break;
1527 case ixgbe_mac_82599EB:
b93a2226 1528 case ixgbe_mac_X540:
e8e26350 1529 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1530 break;
bd508178
AD		 1531 default:
1532 break;
1533 }
021230d4
AV		 1534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1535
41fb9248 1536 /* set up to autoclear timer, and the vectors */
021230d4 1537 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1538 mask &= ~(IXGBE_EIMS_OTHER |
1539 IXGBE_EIMS_MAILBOX |
1540 IXGBE_EIMS_LSC);
1541
021230d4 1542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1543}
1544
f494e8fa
AV		 1545enum latency_range {
1546 lowest_latency = 0,
1547 low_latency = 1,
1548 bulk_latency = 2,
1549 latency_invalid = 255
1550};
1551
1552/**
1553 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1554 * @q_vector: structure containing interrupt and ring information
1555 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1556 *
1557 * Stores a new ITR value based on packets and byte
1558 * counts during the last interrupt. The advantage of per interrupt
1559 * computation is faster updates and more accurate ITR for the current
1560 * traffic pattern. Constants in this function were computed
1561 * based on theoretical maximum wire speed and thresholds were set based
1562 * on testing data as well as attempting to minimize response time
1563 * while increasing bulk throughput.
1564 * this functionality is controlled by the InterruptThrottleRate module
1565 * parameter (see ixgbe_param.c)
1566 **/
bd198058
AD		 1567static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1568 struct ixgbe_ring_container *ring_container)
f494e8fa 1569{
f494e8fa 1570 u64 bytes_perint;
bd198058
AD		 1571 struct ixgbe_adapter *adapter = q_vector->adapter;
1572 int bytes = ring_container->total_bytes;
1573 int packets = ring_container->total_packets;
1574 u32 timepassed_us;
1575 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1576
1577 if (packets == 0)
bd198058 1578 return;
f494e8fa
AV		 1579
1580 /* simple throttlerate management
1581 * 0-20MB/s lowest (100000 ints/s)
1582 * 20-100MB/s low (20000 ints/s)
1583 * 100-1249MB/s bulk (8000 ints/s)
1584 */
1585 /* what was last interrupt timeslice? */
d5bf4f67 1586 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1587 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1588
1589 switch (itr_setting) {
1590 case lowest_latency:
1591 if (bytes_perint > adapter->eitr_low)
bd198058 1592 itr_setting = low_latency;
f494e8fa
AV		 1593 break;
1594 case low_latency:
1595 if (bytes_perint > adapter->eitr_high)
bd198058 1596 itr_setting = bulk_latency;
f494e8fa 1597 else if (bytes_perint <= adapter->eitr_low)
bd198058 1598 itr_setting = lowest_latency;
f494e8fa
AV		 1599 break;
1600 case bulk_latency:
1601 if (bytes_perint <= adapter->eitr_high)
bd198058 1602 itr_setting = low_latency;
f494e8fa
AV		 1603 break;
1604 }
1605
bd198058
AD		 1606 /* clear work counters since we have the values we need */
1607 ring_container->total_bytes = 0;
1608 ring_container->total_packets = 0;
1609
1610 /* write updated itr to ring container */
1611 ring_container->itr = itr_setting;
f494e8fa
AV		 1612}
1613
509ee935
JB		 1614/**
1615 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1616 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1617 *
1618 * This function is made to be called by ethtool and by the driver
1619 * when it needs to update EITR registers at runtime. Hardware
1620 * specific quirks/differences are taken care of here.
1621 */
fe49f04a 1622void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1623{
fe49f04a 1624 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1625 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1626 int v_idx = q_vector->v_idx;
d5bf4f67 1627 u32 itr_reg = q_vector->itr;
fe49f04a 1628
bd508178
AD		 1629 switch (adapter->hw.mac.type) {
1630 case ixgbe_mac_82598EB:
509ee935
JB		 1631 /* must write high and low 16 bits to reset counter */
1632 itr_reg |= (itr_reg << 16);
bd508178
AD		 1633 break;
1634 case ixgbe_mac_82599EB:
b93a2226 1635 case ixgbe_mac_X540:
509ee935
JB		 1636 /*
1637 * set the WDIS bit to not clear the timer bits and cause an
1638 * immediate assertion of the interrupt
1639 */
1640 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1641 break;
1642 default:
1643 break;
509ee935
JB		 1644 }
1645 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1646}
1647
bd198058 1648static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1649{
d5bf4f67 1650 u32 new_itr = q_vector->itr;
bd198058 1651 u8 current_itr;
f494e8fa 1652
bd198058
AD		 1653 ixgbe_update_itr(q_vector, &q_vector->tx);
1654 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1655
08c8833b 1656 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1657
1658 switch (current_itr) {
1659 /* counts and packets in update_itr are dependent on these numbers */
1660 case lowest_latency:
d5bf4f67 1661 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1662 break;
1663 case low_latency:
d5bf4f67 1664 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1665 break;
1666 case bulk_latency:
d5bf4f67 1667 new_itr = IXGBE_8K_ITR;
f494e8fa 1668 break;
bd198058
AD		 1669 default:
1670 break;
f494e8fa
AV		 1671 }
1672
d5bf4f67 1673 if (new_itr != q_vector->itr) {
fe49f04a 1674 /* do an exponential smoothing */
d5bf4f67
ET		 1675 new_itr = (10 * new_itr * q_vector->itr) /
1676 ((9 * new_itr) + q_vector->itr);
509ee935 1677
bd198058 1678 /* save the algorithm value here */
d5bf4f67 1679 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1680
1681 ixgbe_write_eitr(q_vector);
f494e8fa 1682 }
f494e8fa
AV		 1683}
1684
119fc60a 1685/**
f0f9778d
AD		 1686 * ixgbe_check_overtemp_subtask - check for over tempurature
1687 * @adapter: pointer to adapter
119fc60a 1688 **/
f0f9778d 1689static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1690{
119fc60a
MC		 1691 struct ixgbe_hw *hw = &adapter->hw;
1692 u32 eicr = adapter->interrupt_event;
1693
f0f9778d 1694 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1695 return;
1696
f0f9778d
AD		 1697 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1698 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1699 return;
1700
1701 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1702
7ca647bd 1703 switch (hw->device_id) {
f0f9778d
AD		 1704 case IXGBE_DEV_ID_82599_T3_LOM:
1705 /*
1706 * Since the warning interrupt is for both ports
1707 * we don't have to check if:
1708 * - This interrupt wasn't for our port.
1709 * - We may have missed the interrupt so always have to
1710 * check if we got a LSC
1711 */
1712 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1713 !(eicr & IXGBE_EICR_LSC))
1714 return;
1715
1716 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1717 u32 autoneg;
1718 bool link_up = false;
7ca647bd 1719
7ca647bd
JP		 1720 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1721
f0f9778d
AD		 1722 if (link_up)
1723 return;
1724 }
1725
1726 /* Check if this is not due to overtemp */
1727 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1728 return;
1729
1730 break;
7ca647bd
JP		 1731 default:
1732 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1733 return;
7ca647bd 1734 break;
119fc60a 1735 }
7ca647bd
JP		 1736 e_crit(drv,
1737 "Network adapter has been stopped because it has over heated. "
1738 "Restart the computer. If the problem persists, "
1739 "power off the system and replace the adapter\n");
f0f9778d
AD		 1740
1741 adapter->interrupt_event = 0;
119fc60a
MC		 1742}
1743
0befdb3e
JB		 1744static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1745{
1746 struct ixgbe_hw *hw = &adapter->hw;
1747
1748 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1749 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1750 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1751 /* write to clear the interrupt */
1752 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1753 }
1754}
cf8280ee 1755
4f51bf70
JK		 1756static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1757{
1758 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1759 return;
1760
1761 switch (adapter->hw.mac.type) {
1762 case ixgbe_mac_82599EB:
1763 /*
1764 * Need to check link state so complete overtemp check
1765 * on service task
1766 */
1767 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1768 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1769 adapter->interrupt_event = eicr;
1770 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1771 ixgbe_service_event_schedule(adapter);
1772 return;
1773 }
1774 return;
1775 case ixgbe_mac_X540:
1776 if (!(eicr & IXGBE_EICR_TS))
1777 return;
1778 break;
1779 default:
1780 return;
1781 }
1782
1783 e_crit(drv,
1784 "Network adapter has been stopped because it has over heated. "
1785 "Restart the computer. If the problem persists, "
1786 "power off the system and replace the adapter\n");
1787}
1788
e8e26350
PW		 1789static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1790{
1791 struct ixgbe_hw *hw = &adapter->hw;
1792
73c4b7cd
AD		 1793 if (eicr & IXGBE_EICR_GPI_SDP2) {
1794 /* Clear the interrupt */
1795 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 1796 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1797 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1798 ixgbe_service_event_schedule(adapter);
1799 }
73c4b7cd
AD		 1800 }
1801
e8e26350
PW		 1802 if (eicr & IXGBE_EICR_GPI_SDP1) {
1803 /* Clear the interrupt */
1804 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 1805 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1806 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1807 ixgbe_service_event_schedule(adapter);
1808 }
e8e26350
PW		 1809 }
1810}
1811
cf8280ee
JB		 1812static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1813{
1814 struct ixgbe_hw *hw = &adapter->hw;
1815
1816 adapter->lsc_int++;
1817 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1818 adapter->link_check_timeout = jiffies;
1819 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1820 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 1821 IXGBE_WRITE_FLUSH(hw);
93c52dd0 1822 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 1823 }
1824}
1825
fe49f04a
AD		 1826static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1827 u64 qmask)
1828{
1829 u32 mask;
bd508178 1830 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1831
bd508178
AD		 1832 switch (hw->mac.type) {
1833 case ixgbe_mac_82598EB:
fe49f04a 1834 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1835 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1836 break;
1837 case ixgbe_mac_82599EB:
b93a2226 1838 case ixgbe_mac_X540:
fe49f04a 1839 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1840 if (mask)
1841 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 1842 mask = (qmask >> 32);
bd508178
AD		 1843 if (mask)
1844 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1845 break;
1846 default:
1847 break;
fe49f04a
AD		 1848 }
1849 /* skip the flush */
1850}
1851
1852static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 1853 u64 qmask)
fe49f04a
AD		 1854{
1855 u32 mask;
bd508178 1856 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1857
bd508178
AD		 1858 switch (hw->mac.type) {
1859 case ixgbe_mac_82598EB:
fe49f04a 1860 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 1861 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1862 break;
1863 case ixgbe_mac_82599EB:
b93a2226 1864 case ixgbe_mac_X540:
fe49f04a 1865 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 1866 if (mask)
1867 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 1868 mask = (qmask >> 32);
bd508178
AD		 1869 if (mask)
1870 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1871 break;
1872 default:
1873 break;
fe49f04a
AD		 1874 }
1875 /* skip the flush */
1876}
1877
021230d4 1878/**
2c4af694
AD		 1879 * ixgbe_irq_enable - Enable default interrupt generation settings
1880 * @adapter: board private structure
021230d4 1881 **/
2c4af694
AD		 1882static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
1883 bool flush)
9a799d71 1884{
2c4af694 1885 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 1886
2c4af694
AD		 1887 /* don't reenable LSC while waiting for link */
1888 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
1889 mask &= ~IXGBE_EIMS_LSC;
9a799d71 1890
2c4af694 1891 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 1892 switch (adapter->hw.mac.type) {
1893 case ixgbe_mac_82599EB:
1894 mask |= IXGBE_EIMS_GPI_SDP0;
1895 break;
1896 case ixgbe_mac_X540:
1897 mask |= IXGBE_EIMS_TS;
1898 break;
1899 default:
1900 break;
1901 }
2c4af694
AD		 1902 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1903 mask |= IXGBE_EIMS_GPI_SDP1;
1904 switch (adapter->hw.mac.type) {
1905 case ixgbe_mac_82599EB:
2c4af694
AD		 1906 mask |= IXGBE_EIMS_GPI_SDP1;
1907 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 1908 case ixgbe_mac_X540:
1909 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 1910 mask |= IXGBE_EIMS_MAILBOX;
1911 break;
1912 default:
1913 break;
9a799d71 1914 }
2c4af694
AD		 1915 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
1916 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
1917 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 1918
2c4af694
AD		 1919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1920 if (queues)
1921 ixgbe_irq_enable_queues(adapter, ~0);
1922 if (flush)
1923 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 1924}
1925
2c4af694 1926static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 1927{
a65151ba 1928 struct ixgbe_adapter *adapter = data;
9a799d71 1929 struct ixgbe_hw *hw = &adapter->hw;
54037505 1930 u32 eicr;
91281fd3 1931
54037505
DS		 1932 /*
1933 * Workaround for Silicon errata. Use clear-by-write instead
1934 * of clear-by-read. Reading with EICS will return the
1935 * interrupt causes without clearing, which later be done
1936 * with the write to EICR.
1937 */
1938 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1939 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 1940
cf8280ee
JB		 1941 if (eicr & IXGBE_EICR_LSC)
1942 ixgbe_check_lsc(adapter);
f0848276 1943
1cdd1ec8
GR		 1944 if (eicr & IXGBE_EICR_MAILBOX)
1945 ixgbe_msg_task(adapter);
efe3d3c8 1946
bd508178
AD		 1947 switch (hw->mac.type) {
1948 case ixgbe_mac_82599EB:
b93a2226 1949 case ixgbe_mac_X540:
2c4af694
AD		 1950 if (eicr & IXGBE_EICR_ECC)
1951 e_info(link, "Received unrecoverable ECC Err, please "
1952 "reboot\n");
c4cf55e5
PWJ		 1953 /* Handle Flow Director Full threshold interrupt */
1954 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 1955 int reinit_count = 0;
c4cf55e5 1956 int i;
c4cf55e5 1957 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 1958 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 1959 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 1960 &ring->state))
1961 reinit_count++;
1962 }
1963 if (reinit_count) {
1964 /* no more flow director interrupts until after init */
1965 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 1966 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1967 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 1968 }
1969 }
f0f9778d 1970 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 1971 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 1972 break;
1973 default:
1974 break;
c4cf55e5 1975 }
f0848276 1976
bd508178 1977 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 1978
7086400d 1979 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 1980 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 1981 ixgbe_irq_enable(adapter, false, false);
f0848276 1982
9a799d71 1983 return IRQ_HANDLED;
f0848276 1984}
91281fd3 1985
4ff7fb12 1986static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 1987{
021230d4 1988 struct ixgbe_q_vector *q_vector = data;
91281fd3 1989
9b471446 1990 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 1991
4ff7fb12
AD		 1992 if (q_vector->rx.ring || q_vector->tx.ring)
1993 napi_schedule(&q_vector->napi);
91281fd3 1994
9a799d71 1995 return IRQ_HANDLED;
91281fd3
AD		 1996}
1997
021230d4 1998static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 1999 int r_idx)
021230d4 2000{
7a921c93 2001 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2002 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2003
2274543f 2004 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2005 rx_ring->next = q_vector->rx.ring;
2006 q_vector->rx.ring = rx_ring;
2007 q_vector->rx.count++;
021230d4
AV		 2008}
2009
2010static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2011 int t_idx)
021230d4 2012{
7a921c93 2013 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2014 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2015
2274543f 2016 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2017 tx_ring->next = q_vector->tx.ring;
2018 q_vector->tx.ring = tx_ring;
2019 q_vector->tx.count++;
bd198058 2020 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2021}
2022
9a799d71 2023/**
021230d4
AV		 2024 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2025 * @adapter: board private structure to initialize
9a799d71 2026 *
021230d4
AV		 2027 * This function maps descriptor rings to the queue-specific vectors
2028 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2029 * one vector per ring/queue, but on a constrained vector budget, we
2030 * group the rings as "efficiently" as possible. You would add new
2031 * mapping configurations in here.
9a799d71 2032 **/
4cc6df29 2033static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2034{
4cc6df29
AD		 2035 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2036 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2037 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2038 int v_start = 0;
021230d4 2039
4cc6df29 2040 /* only one q_vector if MSI-X is disabled. */
021230d4 2041 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2042 q_vectors = 1;
d0759ebb 2043
021230d4 2044 /*
4cc6df29
AD		 2045 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2046 * group them so there are multiple queues per vector.
2047 *
2048 * Re-adjusting *qpv takes care of the remainder.
021230d4 2049 */
4cc6df29
AD		 2050 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2051 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2052 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2053 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2054 }
9a799d71 2055
021230d4 2056 /*
4cc6df29
AD		 2057 * If there are not enough q_vectors for each ring to have it's own
2058 * vector then we must pair up Rx/Tx on a each vector
021230d4 2059 */
4cc6df29
AD		 2060 if ((v_start + txr_remaining) > q_vectors)
2061 v_start = 0;
2062
2063 for (; v_start < q_vectors && txr_remaining; v_start++) {
2064 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2065 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2066 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2067 }
021230d4
AV		 2068}
2069
2070/**
2071 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2072 * @adapter: board private structure
2073 *
2074 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2075 * interrupts from the kernel.
2076 **/
2077static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2078{
2079 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2080 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2081 int vector, err;
e8e9f696 2082 int ri = 0, ti = 0;
021230d4 2083
021230d4 2084 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2085 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2086 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2087
4ff7fb12 2088 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2089 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2090 "%s-%s-%d", netdev->name, "TxRx", ri++);
2091 ti++;
2092 } else if (q_vector->rx.ring) {
9fe93afd 2093 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2094 "%s-%s-%d", netdev->name, "rx", ri++);
2095 } else if (q_vector->tx.ring) {
9fe93afd 2096 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2097 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2098 } else {
2099 /* skip this unused q_vector */
2100 continue;
32aa77a4 2101 }
207867f5
AD		 2102 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2103 q_vector->name, q_vector);
9a799d71 2104 if (err) {
396e799c 2105 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2106 "Error: %d\n", err);
021230d4 2107 goto free_queue_irqs;
9a799d71 2108 }
207867f5
AD		 2109 /* If Flow Director is enabled, set interrupt affinity */
2110 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2111 /* assign the mask for this irq */
2112 irq_set_affinity_hint(entry->vector,
2113 q_vector->affinity_mask);
2114 }
9a799d71
AK		 2115 }
2116
021230d4 2117 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2118 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2119 if (err) {
396e799c 2120 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2121 goto free_queue_irqs;
9a799d71
AK		 2122 }
2123
9a799d71
AK		 2124 return 0;
2125
021230d4 2126free_queue_irqs:
207867f5
AD		 2127 while (vector) {
2128 vector--;
2129 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2130 NULL);
2131 free_irq(adapter->msix_entries[vector].vector,
2132 adapter->q_vector[vector]);
2133 }
021230d4
AV		 2134 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2135 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2136 kfree(adapter->msix_entries);
2137 adapter->msix_entries = NULL;
9a799d71
AK		 2138 return err;
2139}
2140
2141/**
021230d4 2142 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2143 * @irq: interrupt number
2144 * @data: pointer to a network interface device structure
9a799d71
AK		 2145 **/
2146static irqreturn_t ixgbe_intr(int irq, void *data)
2147{
a65151ba 2148 struct ixgbe_adapter *adapter = data;
9a799d71 2149 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2150 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2151 u32 eicr;
2152
54037505 2153 /*
6af3b9eb 2154 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2155 * before the read of EICR.
2156 */
2157 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2158
021230d4 2159 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2160 * therefore no explicit interrupt disable is necessary */
021230d4 2161 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2162 if (!eicr) {
6af3b9eb
ET		 2163 /*
2164 * shared interrupt alert!
f47cf66e 2165 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2166 * have disabled interrupts due to EIAM
2167 * finish the workaround of silicon errata on 82598. Unmask
2168 * the interrupt that we masked before the EICR read.
2169 */
2170 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2171 ixgbe_irq_enable(adapter, true, true);
9a799d71 2172 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2173 }
9a799d71 2174
cf8280ee
JB		 2175 if (eicr & IXGBE_EICR_LSC)
2176 ixgbe_check_lsc(adapter);
021230d4 2177
bd508178
AD		 2178 switch (hw->mac.type) {
2179 case ixgbe_mac_82599EB:
e8e26350 2180 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2181 /* Fall through */
2182 case ixgbe_mac_X540:
2183 if (eicr & IXGBE_EICR_ECC)
2184 e_info(link, "Received unrecoverable ECC err, please "
2185 "reboot\n");
4f51bf70 2186 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2187 break;
2188 default:
2189 break;
2190 }
e8e26350 2191
0befdb3e
JB		 2192 ixgbe_check_fan_failure(adapter, eicr);
2193
7a921c93 2194 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2195 /* would disable interrupts here but EIAM disabled it */
7a921c93 2196 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2197 }
2198
6af3b9eb
ET		 2199 /*
2200 * re-enable link(maybe) and non-queue interrupts, no flush.
2201 * ixgbe_poll will re-enable the queue interrupts
2202 */
2203
2204 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2205 ixgbe_irq_enable(adapter, false, false);
2206
9a799d71
AK		 2207 return IRQ_HANDLED;
2208}
2209
021230d4
AV		 2210static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2211{
efe3d3c8
AD		 2212 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2213 int i;
2214
2215 /* legacy and MSI only use one vector */
2216 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2217 q_vectors = 1;
2218
2219 for (i = 0; i < adapter->num_rx_queues; i++) {
2220 adapter->rx_ring[i]->q_vector = NULL;
2221 adapter->rx_ring[i]->next = NULL;
2222 }
2223 for (i = 0; i < adapter->num_tx_queues; i++) {
2224 adapter->tx_ring[i]->q_vector = NULL;
2225 adapter->tx_ring[i]->next = NULL;
2226 }
021230d4
AV		 2227
2228 for (i = 0; i < q_vectors; i++) {
7a921c93 2229 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2230 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2231 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2232 }
2233}
2234
9a799d71
AK		 2235/**
2236 * ixgbe_request_irq - initialize interrupts
2237 * @adapter: board private structure
2238 *
2239 * Attempts to configure interrupts using the best available
2240 * capabilities of the hardware and kernel.
2241 **/
021230d4 2242static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2243{
2244 struct net_device *netdev = adapter->netdev;
021230d4 2245 int err;
9a799d71 2246
4cc6df29
AD		 2247 /* map all of the rings to the q_vectors */
2248 ixgbe_map_rings_to_vectors(adapter);
2249
2250 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2251 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2252 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2253 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2254 netdev->name, adapter);
4cc6df29 2255 else
a0607fd3 2256 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2257 netdev->name, adapter);
9a799d71 2258
4cc6df29 2259 if (err) {
396e799c 2260 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2261
4cc6df29
AD		 2262 /* place q_vectors and rings back into a known good state */
2263 ixgbe_reset_q_vectors(adapter);
2264 }
2265
9a799d71
AK		 2266 return err;
2267}
2268
2269static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2270{
9a799d71 2271 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2272 int i, q_vectors;
9a799d71 2273
021230d4 2274 q_vectors = adapter->num_msix_vectors;
021230d4 2275 i = q_vectors - 1;
a65151ba 2276 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2277 i--;
4cc6df29 2278
021230d4 2279 for (; i >= 0; i--) {
894ff7cf 2280 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2281 if (!adapter->q_vector[i]->rx.ring &&
2282 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2283 continue;
2284
207867f5
AD		 2285 /* clear the affinity_mask in the IRQ descriptor */
2286 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2287 NULL);
2288
021230d4 2289 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2290 adapter->q_vector[i]);
021230d4 2291 }
021230d4 2292 } else {
a65151ba 2293 free_irq(adapter->pdev->irq, adapter);
9a799d71 2294 }
207867f5
AD		 2295
2296 /* clear q_vector state information */
2297 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2298}
2299
22d5a71b
JB		 2300/**
2301 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2302 * @adapter: board private structure
2303 **/
2304static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2305{
bd508178
AD		 2306 switch (adapter->hw.mac.type) {
2307 case ixgbe_mac_82598EB:
835462fc 2308 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2309 break;
2310 case ixgbe_mac_82599EB:
b93a2226 2311 case ixgbe_mac_X540:
835462fc
NS		 2312 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2314 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2315 break;
2316 default:
2317 break;
22d5a71b
JB		 2318 }
2319 IXGBE_WRITE_FLUSH(&adapter->hw);
2320 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2321 int i;
2322 for (i = 0; i < adapter->num_msix_vectors; i++)
2323 synchronize_irq(adapter->msix_entries[i].vector);
2324 } else {
2325 synchronize_irq(adapter->pdev->irq);
2326 }
2327}
2328
9a799d71
AK		 2329/**
2330 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2331 *
2332 **/
2333static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2334{
d5bf4f67 2335 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2336
d5bf4f67
ET		 2337 /* rx/tx vector */
2338 if (adapter->rx_itr_setting == 1)
2339 q_vector->itr = IXGBE_20K_ITR;
2340 else
2341 q_vector->itr = adapter->rx_itr_setting;
2342
2343 ixgbe_write_eitr(q_vector);
9a799d71 2344
e8e26350
PW		 2345 ixgbe_set_ivar(adapter, 0, 0, 0);
2346 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2347
396e799c 2348 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2349}
2350
43e69bf0
AD		 2351/**
2352 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2353 * @adapter: board private structure
2354 * @ring: structure containing ring specific data
2355 *
2356 * Configure the Tx descriptor ring after a reset.
2357 **/
84418e3b
AD		 2358void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2359 struct ixgbe_ring *ring)
43e69bf0
AD		 2360{
2361 struct ixgbe_hw *hw = &adapter->hw;
2362 u64 tdba = ring->dma;
2f1860b8 2363 int wait_loop = 10;
b88c6de2 2364 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2365 u8 reg_idx = ring->reg_idx;
43e69bf0 2366
2f1860b8 2367 /* disable queue to avoid issues while updating state */
b88c6de2 2368 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2369 IXGBE_WRITE_FLUSH(hw);
2370
43e69bf0 2371 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2372 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2373 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2374 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2375 ring->count * sizeof(union ixgbe_adv_tx_desc));
2376 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2377 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2378 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2379
b88c6de2
AD		 2380 /*
2381 * set WTHRESH to encourage burst writeback, it should not be set
2382 * higher than 1 when ITR is 0 as it could cause false TX hangs
2383 *
2384 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2385 * to or less than the number of on chip descriptors, which is
2386 * currently 40.
2387 */
2388 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2389 txdctl |= (1 << 16); /* WTHRESH = 1 */
2390 else
2391 txdctl |= (8 << 16); /* WTHRESH = 8 */
2392
2393 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2394 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2395 32; /* PTHRESH = 32 */
2f1860b8
AD		 2396
2397 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2398 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2399 adapter->atr_sample_rate) {
2400 ring->atr_sample_rate = adapter->atr_sample_rate;
2401 ring->atr_count = 0;
2402 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2403 } else {
2404 ring->atr_sample_rate = 0;
2405 }
2f1860b8 2406
c84d324c
JF		 2407 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2408
2f1860b8 2409 /* enable queue */
2f1860b8
AD		 2410 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2411
2412 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2413 if (hw->mac.type == ixgbe_mac_82598EB &&
2414 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2415 return;
2416
2417 /* poll to verify queue is enabled */
2418 do {
032b4325 2419 usleep_range(1000, 2000);
2f1860b8
AD		 2420 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2421 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2422 if (!wait_loop)
2423 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2424}
2425
120ff942
AD		 2426static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2427{
2428 struct ixgbe_hw *hw = &adapter->hw;
2429 u32 rttdcs;
72a32f1f 2430 u32 reg;
8b1c0b24 2431 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2432
2433 if (hw->mac.type == ixgbe_mac_82598EB)
2434 return;
2435
2436 /* disable the arbiter while setting MTQC */
2437 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2438 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2439 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2440
2441 /* set transmit pool layout */
8b1c0b24 2442 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2443 case (IXGBE_FLAG_SRIOV_ENABLED):
2444 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2445 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2446 break;
8b1c0b24
JF		 2447 default:
2448 if (!tcs)
2449 reg = IXGBE_MTQC_64Q_1PB;
2450 else if (tcs <= 4)
2451 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2452 else
2453 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2454
8b1c0b24 2455 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2456
8b1c0b24
JF		 2457 /* Enable Security TX Buffer IFG for multiple pb */
2458 if (tcs) {
2459 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2460 reg |= IXGBE_SECTX_DCB;
2461 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2462 }
120ff942
AD		 2463 break;
2464 }
2465
2466 /* re-enable the arbiter */
2467 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2468 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2469}
2470
9a799d71 2471/**
3a581073 2472 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2473 * @adapter: board private structure
2474 *
2475 * Configure the Tx unit of the MAC after a reset.
2476 **/
2477static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2478{
2f1860b8
AD		 2479 struct ixgbe_hw *hw = &adapter->hw;
2480 u32 dmatxctl;
43e69bf0 2481 u32 i;
9a799d71 2482
2f1860b8
AD		 2483 ixgbe_setup_mtqc(adapter);
2484
2485 if (hw->mac.type != ixgbe_mac_82598EB) {
2486 /* DMATXCTL.EN must be before Tx queues are enabled */
2487 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2488 dmatxctl |= IXGBE_DMATXCTL_TE;
2489 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2490 }
2491
9a799d71 2492 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2493 for (i = 0; i < adapter->num_tx_queues; i++)
2494 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2495}
2496
e8e26350 2497#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2498
a6616b42 2499static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2500 struct ixgbe_ring *rx_ring)
cc41ac7c 2501{
cc41ac7c 2502 u32 srrctl;
bf29ee6c 2503 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2504
bd508178
AD		 2505 switch (adapter->hw.mac.type) {
2506 case ixgbe_mac_82598EB: {
2507 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2508 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2509 reg_idx = reg_idx & mask;
cc41ac7c 2510 }
bd508178
AD		 2511 break;
2512 case ixgbe_mac_82599EB:
b93a2226 2513 case ixgbe_mac_X540:
bd508178
AD		 2514 default:
2515 break;
2516 }
2517
bf29ee6c 2518 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2519
2520 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2521 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2522 if (adapter->num_vfs)
2523 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2524
afafd5b0
AD		 2525 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2526 IXGBE_SRRCTL_BSIZEHDR_MASK;
2527
7d637bcc 2528 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2529#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2530 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2531#else
2532 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2533#endif
cc41ac7c 2534 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2535 } else {
afafd5b0
AD		 2536 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2537 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2538 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2539 }
e8e26350 2540
bf29ee6c 2541 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2542}
9a799d71 2543
05abb126 2544static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2545{
05abb126
AD		 2546 struct ixgbe_hw *hw = &adapter->hw;
2547 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2548 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2549 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2550 u32 mrqc = 0, reta = 0;
2551 u32 rxcsum;
2552 int i, j;
8b1c0b24 2553 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2554 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2555
2556 if (tcs)
2557 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2558
05abb126
AD		 2559 /* Fill out hash function seeds */
2560 for (i = 0; i < 10; i++)
2561 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2562
2563 /* Fill out redirection table */
2564 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2565 if (j == maxq)
05abb126
AD		 2566 j = 0;
2567 /* reta = 4-byte sliding window of
2568 * 0x00..(indices-1)(indices-1)00..etc. */
2569 reta = (reta << 8) | (j * 0x11);
2570 if ((i & 3) == 3)
2571 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2572 }
0cefafad 2573
05abb126
AD		 2574 /* Disable indicating checksum in descriptor, enables RSS hash */
2575 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2576 rxcsum |= IXGBE_RXCSUM_PCSD;
2577 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2578
8b1c0b24
JF		 2579 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2580 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2581 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2582 } else {
2583 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2584 | IXGBE_FLAG_SRIOV_ENABLED);
2585
2586 switch (mask) {
2587 case (IXGBE_FLAG_RSS_ENABLED):
2588 if (!tcs)
2589 mrqc = IXGBE_MRQC_RSSEN;
2590 else if (tcs <= 4)
2591 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2592 else
2593 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2594 break;
2595 case (IXGBE_FLAG_SRIOV_ENABLED):
2596 mrqc = IXGBE_MRQC_VMDQEN;
2597 break;
2598 default:
2599 break;
2600 }
0cefafad
JB		 2601 }
2602
05abb126
AD		 2603 /* Perform hash on these packet types */
2604 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2605 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2606 | IXGBE_MRQC_RSS_FIELD_IPV6
2607 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2608
2609 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2610}
2611
bb5a9ad2
NS		 2612/**
2613 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2614 * @adapter: address of board private structure
2615 * @index: index of ring to set
bb5a9ad2 2616 **/
082757af 2617static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2618 struct ixgbe_ring *ring)
bb5a9ad2 2619{
bb5a9ad2 2620 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2621 u32 rscctrl;
edd2ea55 2622 int rx_buf_len;
bf29ee6c 2623 u8 reg_idx = ring->reg_idx;
7367096a 2624
7d637bcc 2625 if (!ring_is_rsc_enabled(ring))
7367096a 2626 return;
bb5a9ad2 2627
7367096a
AD		 2628 rx_buf_len = ring->rx_buf_len;
2629 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2630 rscctrl |= IXGBE_RSCCTL_RSCEN;
2631 /*
2632 * we must limit the number of descriptors so that the
2633 * total size of max desc * buf_len is not greater
2634 * than 65535
2635 */
7d637bcc 2636 if (ring_is_ps_enabled(ring)) {
bb5a9ad2
NS		 2637#if (MAX_SKB_FRAGS > 16)
2638 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2639#elif (MAX_SKB_FRAGS > 8)
2640 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2641#elif (MAX_SKB_FRAGS > 4)
2642 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2643#else
2644 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2645#endif
2646 } else {
919e78a6 2647 if (rx_buf_len < IXGBE_RXBUFFER_4K)
bb5a9ad2 2648 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
919e78a6 2649 else if (rx_buf_len < IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2650 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2651 else
2652 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2653 }
7367096a 2654 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2655}
2656
9e10e045
AD		 2657/**
2658 * ixgbe_set_uta - Set unicast filter table address
2659 * @adapter: board private structure
2660 *
2661 * The unicast table address is a register array of 32-bit registers.
2662 * The table is meant to be used in a way similar to how the MTA is used
2663 * however due to certain limitations in the hardware it is necessary to
2664 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2665 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2666 **/
2667static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2668{
2669 struct ixgbe_hw *hw = &adapter->hw;
2670 int i;
2671
2672 /* The UTA table only exists on 82599 hardware and newer */
2673 if (hw->mac.type < ixgbe_mac_82599EB)
2674 return;
2675
2676 /* we only need to do this if VMDq is enabled */
2677 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2678 return;
2679
2680 for (i = 0; i < 128; i++)
2681 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2682}
2683
2684#define IXGBE_MAX_RX_DESC_POLL 10
2685static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2686 struct ixgbe_ring *ring)
2687{
2688 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2689 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2690 u32 rxdctl;
bf29ee6c 2691 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2692
2693 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2694 if (hw->mac.type == ixgbe_mac_82598EB &&
2695 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2696 return;
2697
2698 do {
032b4325 2699 usleep_range(1000, 2000);
9e10e045
AD		 2700 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2701 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2702
2703 if (!wait_loop) {
2704 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2705 "the polling period\n", reg_idx);
2706 }
2707}
2708
2d39d576
YZ		 2709void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2710 struct ixgbe_ring *ring)
2711{
2712 struct ixgbe_hw *hw = &adapter->hw;
2713 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2714 u32 rxdctl;
2715 u8 reg_idx = ring->reg_idx;
2716
2717 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2718 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2719
2720 /* write value back with RXDCTL.ENABLE bit cleared */
2721 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2722
2723 if (hw->mac.type == ixgbe_mac_82598EB &&
2724 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2725 return;
2726
2727 /* the hardware may take up to 100us to really disable the rx queue */
2728 do {
2729 udelay(10);
2730 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2731 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2732
2733 if (!wait_loop) {
2734 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2735 "the polling period\n", reg_idx);
2736 }
2737}
2738
84418e3b
AD		 2739void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2740 struct ixgbe_ring *ring)
acd37177
AD		 2741{
2742 struct ixgbe_hw *hw = &adapter->hw;
2743 u64 rdba = ring->dma;
9e10e045 2744 u32 rxdctl;
bf29ee6c 2745 u8 reg_idx = ring->reg_idx;
acd37177 2746
9e10e045
AD		 2747 /* disable queue to avoid issues while updating state */
2748 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2749 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2750
acd37177
AD		 2751 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2752 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2753 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2754 ring->count * sizeof(union ixgbe_adv_rx_desc));
2755 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2756 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2757 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2758
2759 ixgbe_configure_srrctl(adapter, ring);
2760 ixgbe_configure_rscctl(adapter, ring);
2761
e9f98072
GR		 2762 /* If operating in IOV mode set RLPML for X540 */
2763 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2764 hw->mac.type == ixgbe_mac_X540) {
2765 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2766 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2767 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2768 }
2769
9e10e045
AD		 2770 if (hw->mac.type == ixgbe_mac_82598EB) {
2771 /*
2772 * enable cache line friendly hardware writes:
2773 * PTHRESH=32 descriptors (half the internal cache),
2774 * this also removes ugly rx_no_buffer_count increment
2775 * HTHRESH=4 descriptors (to minimize latency on fetch)
2776 * WTHRESH=8 burst writeback up to two cache lines
2777 */
2778 rxdctl &= ~0x3FFFFF;
2779 rxdctl |= 0x080420;
2780 }
2781
2782 /* enable receive descriptor ring */
2783 rxdctl |= IXGBE_RXDCTL_ENABLE;
2784 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2785
2786 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2787 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2788}
2789
48654521
AD		 2790static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2791{
2792 struct ixgbe_hw *hw = &adapter->hw;
2793 int p;
2794
2795 /* PSRTYPE must be initialized in non 82598 adapters */
2796 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 2797 IXGBE_PSRTYPE_UDPHDR |
2798 IXGBE_PSRTYPE_IPV4HDR |
48654521 2799 IXGBE_PSRTYPE_L2HDR |
e8e9f696 2800 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 2801
2802 if (hw->mac.type == ixgbe_mac_82598EB)
2803 return;
2804
2805 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2806 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2807
2808 for (p = 0; p < adapter->num_rx_pools; p++)
2809 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2810 psrtype);
2811}
2812
f5b4a52e
AD		 2813static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2814{
2815 struct ixgbe_hw *hw = &adapter->hw;
2816 u32 gcr_ext;
2817 u32 vt_reg_bits;
2818 u32 reg_offset, vf_shift;
2819 u32 vmdctl;
de4c7f65 2820 int i;
f5b4a52e
AD		 2821
2822 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2823 return;
2824
2825 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2826 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2827 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2828 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2829
2830 vf_shift = adapter->num_vfs % 32;
2831 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2832
2833 /* Enable only the PF's pool for Tx/Rx */
2834 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2835 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2836 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2837 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2838 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2839
2840 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2841 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2842
2843 /*
2844 * Set up VF register offsets for selected VT Mode,
2845 * i.e. 32 or 64 VFs for SR-IOV
2846 */
2847 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2848 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2849 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2850 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2851
2852 /* enable Tx loopback for VF/PF communication */
2853 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 2854 /* Enable MAC Anti-Spoofing */
a1cbb15c 2855 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 2856 (adapter->num_vfs != 0),
a985b6c3 2857 adapter->num_vfs);
de4c7f65
GR		 2858 /* For VFs that have spoof checking turned off */
2859 for (i = 0; i < adapter->num_vfs; i++) {
2860 if (!adapter->vfinfo[i].spoofchk_enabled)
2861 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
2862 }
f5b4a52e
AD		 2863}
2864
477de6ed 2865static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 2866{
9a799d71
AK		 2867 struct ixgbe_hw *hw = &adapter->hw;
2868 struct net_device *netdev = adapter->netdev;
2869 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 2870 int rx_buf_len;
477de6ed
AD		 2871 struct ixgbe_ring *rx_ring;
2872 int i;
2873 u32 mhadd, hlreg0;
48654521 2874
9a799d71 2875 /* Decide whether to use packet split mode or not */
a124339a
DS		 2876 /* On by default */
2877 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2878
1cdd1ec8 2879 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 2880 if (adapter->num_vfs)
2881 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
2882
2883 /* Disable packet split due to 82599 erratum #45 */
2884 if (hw->mac.type == ixgbe_mac_82599EB)
2885 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 2886
63f39bd1 2887#ifdef IXGBE_FCOE
477de6ed
AD		 2888 /* adjust max frame to be able to do baby jumbo for FCoE */
2889 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2890 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2891 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 2892
477de6ed
AD		 2893#endif /* IXGBE_FCOE */
2894 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2895 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2896 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2897 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2898
2899 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2900 }
2901
919e78a6
AD		 2902 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
2903 max_frame += VLAN_HLEN;
2904
2905 /* Set the RX buffer length according to the mode */
2906 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2907 rx_buf_len = IXGBE_RX_HDR_SIZE;
2908 } else {
2909 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2910 (netdev->mtu <= ETH_DATA_LEN))
2911 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2912 /*
2913 * Make best use of allocation by using all but 1K of a
2914 * power of 2 allocation that will be used for skb->head.
2915 */
2916 else if (max_frame <= IXGBE_RXBUFFER_3K)
2917 rx_buf_len = IXGBE_RXBUFFER_3K;
2918 else if (max_frame <= IXGBE_RXBUFFER_7K)
2919 rx_buf_len = IXGBE_RXBUFFER_7K;
2920 else if (max_frame <= IXGBE_RXBUFFER_15K)
2921 rx_buf_len = IXGBE_RXBUFFER_15K;
2922 else
2923 rx_buf_len = IXGBE_MAX_RXBUFFER;
2924 }
2925
477de6ed
AD		 2926 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2927 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2928 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2929 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 2930
0cefafad
JB		 2931 /*
2932 * Setup the HW Rx Head and Tail Descriptor Pointers and
2933 * the Base and Length of the Rx Descriptor Ring
2934 */
9a799d71 2935 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 2936 rx_ring = adapter->rx_ring[i];
a6616b42 2937 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 2938
6e455b89 2939 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 2940 set_ring_ps_enabled(rx_ring);
2941 else
2942 clear_ring_ps_enabled(rx_ring);
2943
2944 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
2945 set_ring_rsc_enabled(rx_ring);
1b3ff02e 2946 else
7d637bcc 2947 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 2948
63f39bd1 2949#ifdef IXGBE_FCOE
e8e9f696 2950 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 2951 struct ixgbe_ring_feature *f;
2952 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 2953 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 2954 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 2955 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2956 rx_ring->rx_buf_len =
e8e9f696 2957 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 2958 } else if (!ring_is_rsc_enabled(rx_ring) &&
2959 !ring_is_ps_enabled(rx_ring)) {
2960 rx_ring->rx_buf_len =
2961 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 2962 }
63f39bd1 2963 }
63f39bd1 2964#endif /* IXGBE_FCOE */
477de6ed 2965 }
477de6ed
AD		 2966}
2967
7367096a
AD		 2968static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2969{
2970 struct ixgbe_hw *hw = &adapter->hw;
2971 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2972
2973 switch (hw->mac.type) {
2974 case ixgbe_mac_82598EB:
2975 /*
2976 * For VMDq support of different descriptor types or
2977 * buffer sizes through the use of multiple SRRCTL
2978 * registers, RDRXCTL.MVMEN must be set to 1
2979 *
2980 * also, the manual doesn't mention it clearly but DCA hints
2981 * will only use queue 0's tags unless this bit is set. Side
2982 * effects of setting this bit are only that SRRCTL must be
2983 * fully programmed [0..15]
2984 */
2985 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2986 break;
2987 case ixgbe_mac_82599EB:
b93a2226 2988 case ixgbe_mac_X540:
7367096a
AD		 2989 /* Disable RSC for ACK packets */
2990 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2991 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2992 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2993 /* hardware requires some bits to be set by default */
2994 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
2995 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2996 break;
2997 default:
2998 /* We should do nothing since we don't know this hardware */
2999 return;
3000 }
3001
3002 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3003}
3004
477de6ed
AD		 3005/**
3006 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3007 * @adapter: board private structure
3008 *
3009 * Configure the Rx unit of the MAC after a reset.
3010 **/
3011static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3012{
3013 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3014 int i;
3015 u32 rxctrl;
477de6ed
AD		 3016
3017 /* disable receives while setting up the descriptors */
3018 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3019 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3020
3021 ixgbe_setup_psrtype(adapter);
7367096a 3022 ixgbe_setup_rdrxctl(adapter);
477de6ed 3023
9e10e045 3024 /* Program registers for the distribution of queues */
f5b4a52e 3025 ixgbe_setup_mrqc(adapter);
f5b4a52e 3026
9e10e045
AD		 3027 ixgbe_set_uta(adapter);
3028
477de6ed
AD		 3029 /* set_rx_buffer_len must be called before ring initialization */
3030 ixgbe_set_rx_buffer_len(adapter);
3031
3032 /*
3033 * Setup the HW Rx Head and Tail Descriptor Pointers and
3034 * the Base and Length of the Rx Descriptor Ring
3035 */
9e10e045
AD		 3036 for (i = 0; i < adapter->num_rx_queues; i++)
3037 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3038
9e10e045
AD		 3039 /* disable drop enable for 82598 parts */
3040 if (hw->mac.type == ixgbe_mac_82598EB)
3041 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3042
3043 /* enable all receives */
3044 rxctrl |= IXGBE_RXCTRL_RXEN;
3045 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3046}
3047
8e586137 3048static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3049{
3050 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3051 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3052 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3053
3054 /* add VID to filter table */
1ada1b1b 3055 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3056 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3057
3058 return 0;
068c89b0
DS		 3059}
3060
8e586137 3061static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3062{
3063 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3064 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3065 int pool_ndx = adapter->num_vfs;
068c89b0 3066
068c89b0 3067 /* remove VID from filter table */
1ada1b1b 3068 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3069 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3070
3071 return 0;
068c89b0
DS		 3072}
3073
5f6c0181
JB		 3074/**
3075 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3076 * @adapter: driver data
3077 */
3078static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3079{
3080 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3081 u32 vlnctrl;
3082
3083 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3084 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3085 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3086}
3087
3088/**
3089 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3090 * @adapter: driver data
3091 */
3092static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3093{
3094 struct ixgbe_hw *hw = &adapter->hw;
3095 u32 vlnctrl;
3096
3097 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3098 vlnctrl |= IXGBE_VLNCTRL_VFE;
3099 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3100 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3101}
3102
3103/**
3104 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3105 * @adapter: driver data
3106 */
3107static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3108{
3109 struct ixgbe_hw *hw = &adapter->hw;
3110 u32 vlnctrl;
5f6c0181
JB		 3111 int i, j;
3112
3113 switch (hw->mac.type) {
3114 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3115 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3116 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3117 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3118 break;
3119 case ixgbe_mac_82599EB:
b93a2226 3120 case ixgbe_mac_X540:
5f6c0181
JB		 3121 for (i = 0; i < adapter->num_rx_queues; i++) {
3122 j = adapter->rx_ring[i]->reg_idx;
3123 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3124 vlnctrl &= ~IXGBE_RXDCTL_VME;
3125 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3126 }
3127 break;
3128 default:
3129 break;
3130 }
3131}
3132
3133/**
f62bbb5e 3134 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3135 * @adapter: driver data
3136 */
f62bbb5e 3137static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3138{
3139 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3140 u32 vlnctrl;
5f6c0181
JB		 3141 int i, j;
3142
3143 switch (hw->mac.type) {
3144 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3145 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3146 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3147 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3148 break;
3149 case ixgbe_mac_82599EB:
b93a2226 3150 case ixgbe_mac_X540:
5f6c0181
JB		 3151 for (i = 0; i < adapter->num_rx_queues; i++) {
3152 j = adapter->rx_ring[i]->reg_idx;
3153 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3154 vlnctrl |= IXGBE_RXDCTL_VME;
3155 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3156 }
3157 break;
3158 default:
3159 break;
3160 }
3161}
3162
9a799d71
AK		 3163static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3164{
f62bbb5e 3165 u16 vid;
9a799d71 3166
f62bbb5e
JG		 3167 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3168
3169 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3170 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3171}
3172
2850062a
AD		 3173/**
3174 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3175 * @netdev: network interface device structure
3176 *
3177 * Writes unicast address list to the RAR table.
3178 * Returns: -ENOMEM on failure/insufficient address space
3179 * 0 on no addresses written
3180 * X on writing X addresses to the RAR table
3181 **/
3182static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3183{
3184 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3185 struct ixgbe_hw *hw = &adapter->hw;
3186 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3187 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3188 int count = 0;
3189
3190 /* return ENOMEM indicating insufficient memory for addresses */
3191 if (netdev_uc_count(netdev) > rar_entries)
3192 return -ENOMEM;
3193
3194 if (!netdev_uc_empty(netdev) && rar_entries) {
3195 struct netdev_hw_addr *ha;
3196 /* return error if we do not support writing to RAR table */
3197 if (!hw->mac.ops.set_rar)
3198 return -ENOMEM;
3199
3200 netdev_for_each_uc_addr(ha, netdev) {
3201 if (!rar_entries)
3202 break;
3203 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3204 vfn, IXGBE_RAH_AV);
3205 count++;
3206 }
3207 }
3208 /* write the addresses in reverse order to avoid write combining */
3209 for (; rar_entries > 0 ; rar_entries--)
3210 hw->mac.ops.clear_rar(hw, rar_entries);
3211
3212 return count;
3213}
3214
9a799d71 3215/**
2c5645cf 3216 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3217 * @netdev: network interface device structure
3218 *
2c5645cf
CL		 3219 * The set_rx_method entry point is called whenever the unicast/multicast
3220 * address list or the network interface flags are updated. This routine is
3221 * responsible for configuring the hardware for proper unicast, multicast and
3222 * promiscuous mode.
9a799d71 3223 **/
7f870475 3224void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3225{
3226 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3227 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3228 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3229 int count;
9a799d71
AK		 3230
3231 /* Check for Promiscuous and All Multicast modes */
3232
3233 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3234
f5dc442b
AD		 3235 /* set all bits that we expect to always be set */
3236 fctrl |= IXGBE_FCTRL_BAM;
3237 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3238 fctrl |= IXGBE_FCTRL_PMCF;
3239
2850062a
AD		 3240 /* clear the bits we are changing the status of */
3241 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3242
9a799d71 3243 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3244 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3245 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3246 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3247 /* don't hardware filter vlans in promisc mode */
3248 ixgbe_vlan_filter_disable(adapter);
9a799d71 3249 } else {
746b9f02
PM		 3250 if (netdev->flags & IFF_ALLMULTI) {
3251 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3252 vmolr |= IXGBE_VMOLR_MPE;
3253 } else {
3254 /*
3255 * Write addresses to the MTA, if the attempt fails
25985edc 3256 * then we should just turn on promiscuous mode so
2850062a
AD		 3257 * that we can at least receive multicast traffic
3258 */
3259 hw->mac.ops.update_mc_addr_list(hw, netdev);
3260 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3261 }
5f6c0181 3262 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3263 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3264 /*
3265 * Write addresses to available RAR registers, if there is not
3266 * sufficient space to store all the addresses then enable
25985edc 3267 * unicast promiscuous mode
2850062a
AD		 3268 */
3269 count = ixgbe_write_uc_addr_list(netdev);
3270 if (count < 0) {
3271 fctrl |= IXGBE_FCTRL_UPE;
3272 vmolr |= IXGBE_VMOLR_ROPE;
3273 }
9a799d71
AK		 3274 }
3275
2850062a 3276 if (adapter->num_vfs) {
1cdd1ec8 3277 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3278 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3279 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3280 IXGBE_VMOLR_ROPE);
3281 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3282 }
3283
3284 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3285
3286 if (netdev->features & NETIF_F_HW_VLAN_RX)
3287 ixgbe_vlan_strip_enable(adapter);
3288 else
3289 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3290}
3291
021230d4
AV		 3292static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3293{
3294 int q_idx;
3295 struct ixgbe_q_vector *q_vector;
3296 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3297
3298 /* legacy and MSI only use one vector */
3299 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3300 q_vectors = 1;
3301
3302 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3303 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3304 napi_enable(&q_vector->napi);
021230d4
AV		 3305 }
3306}
3307
3308static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3309{
3310 int q_idx;
3311 struct ixgbe_q_vector *q_vector;
3312 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3313
3314 /* legacy and MSI only use one vector */
3315 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3316 q_vectors = 1;
3317
3318 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3319 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3320 napi_disable(&q_vector->napi);
3321 }
3322}
3323
7a6b6f51 3324#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3325/*
3326 * ixgbe_configure_dcb - Configure DCB hardware
3327 * @adapter: ixgbe adapter struct
3328 *
3329 * This is called by the driver on open to configure the DCB hardware.
3330 * This is also called by the gennetlink interface when reconfiguring
3331 * the DCB state.
3332 */
3333static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3334{
3335 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3336 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3337
67ebd791
AD		 3338 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3339 if (hw->mac.type == ixgbe_mac_82598EB)
3340 netif_set_gso_max_size(adapter->netdev, 65536);
3341 return;
3342 }
3343
3344 if (hw->mac.type == ixgbe_mac_82598EB)
3345 netif_set_gso_max_size(adapter->netdev, 32768);
3346
2f90b865 3347
2f90b865 3348 /* Enable VLAN tag insert/strip */
f62bbb5e 3349 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3350
2f90b865 3351 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3352
971060b1 3353#ifdef IXGBE_FCOE
b120818e
JF		 3354 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3355 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3356#endif
b120818e
JF		 3357
3358 /* reconfigure the hardware */
3359 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3360 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3361 DCB_TX_CONFIG);
3362 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3363 DCB_RX_CONFIG);
3364 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3365 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3366 ixgbe_dcb_hw_ets(&adapter->hw,
3367 adapter->ixgbe_ieee_ets,
3368 max_frame);
3369 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3370 adapter->ixgbe_ieee_pfc->pfc_en,
3371 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3372 }
8187cd48
JF		 3373
3374 /* Enable RSS Hash per TC */
3375 if (hw->mac.type != ixgbe_mac_82598EB) {
3376 int i;
3377 u32 reg = 0;
3378
3379 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3380 u8 msb = 0;
3381 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3382
3383 while (cnt >>= 1)
3384 msb++;
3385
3386 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3387 }
3388 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3389 }
2f90b865 3390}
9da712d2
JF		 3391#endif
3392
3393/* Additional bittime to account for IXGBE framing */
3394#define IXGBE_ETH_FRAMING 20
3395
3396/*
3397 * ixgbe_hpbthresh - calculate high water mark for flow control
3398 *
3399 * @adapter: board private structure to calculate for
3400 * @pb - packet buffer to calculate
3401 */
3402static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3403{
3404 struct ixgbe_hw *hw = &adapter->hw;
3405 struct net_device *dev = adapter->netdev;
3406 int link, tc, kb, marker;
3407 u32 dv_id, rx_pba;
3408
3409 /* Calculate max LAN frame size */
3410 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3411
3412#ifdef IXGBE_FCOE
3413 /* FCoE traffic class uses FCOE jumbo frames */
3414 if (dev->features & NETIF_F_FCOE_MTU) {
3415 int fcoe_pb = 0;
2f90b865 3416
9da712d2
JF		 3417#ifdef CONFIG_IXGBE_DCB
3418 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3419
3420#endif
3421 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3422 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3423 }
2f90b865 3424#endif
80605c65 3425
9da712d2
JF		 3426 /* Calculate delay value for device */
3427 switch (hw->mac.type) {
3428 case ixgbe_mac_X540:
3429 dv_id = IXGBE_DV_X540(link, tc);
3430 break;
3431 default:
3432 dv_id = IXGBE_DV(link, tc);
3433 break;
3434 }
3435
3436 /* Loopback switch introduces additional latency */
3437 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3438 dv_id += IXGBE_B2BT(tc);
3439
3440 /* Delay value is calculated in bit times convert to KB */
3441 kb = IXGBE_BT2KB(dv_id);
3442 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3443
3444 marker = rx_pba - kb;
3445
3446 /* It is possible that the packet buffer is not large enough
3447 * to provide required headroom. In this case throw an error
3448 * to user and a do the best we can.
3449 */
3450 if (marker < 0) {
3451 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3452 "headroom to support flow control."
3453 "Decrease MTU or number of traffic classes\n", pb);
3454 marker = tc + 1;
3455 }
3456
3457 return marker;
3458}
3459
3460/*
3461 * ixgbe_lpbthresh - calculate low water mark for for flow control
3462 *
3463 * @adapter: board private structure to calculate for
3464 * @pb - packet buffer to calculate
3465 */
3466static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3467{
3468 struct ixgbe_hw *hw = &adapter->hw;
3469 struct net_device *dev = adapter->netdev;
3470 int tc;
3471 u32 dv_id;
3472
3473 /* Calculate max LAN frame size */
3474 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3475
3476 /* Calculate delay value for device */
3477 switch (hw->mac.type) {
3478 case ixgbe_mac_X540:
3479 dv_id = IXGBE_LOW_DV_X540(tc);
3480 break;
3481 default:
3482 dv_id = IXGBE_LOW_DV(tc);
3483 break;
3484 }
3485
3486 /* Delay value is calculated in bit times convert to KB */
3487 return IXGBE_BT2KB(dv_id);
3488}
3489
3490/*
3491 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3492 */
3493static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3494{
3495 struct ixgbe_hw *hw = &adapter->hw;
3496 int num_tc = netdev_get_num_tc(adapter->netdev);
3497 int i;
3498
3499 if (!num_tc)
3500 num_tc = 1;
3501
3502 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3503
3504 for (i = 0; i < num_tc; i++) {
3505 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3506
3507 /* Low water marks must not be larger than high water marks */
3508 if (hw->fc.low_water > hw->fc.high_water[i])
3509 hw->fc.low_water = 0;
3510 }
3511}
3512
80605c65
JF		 3513static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3514{
80605c65 3515 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3516 int hdrm;
3517 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3518
3519 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3520 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3521 hdrm = 32 << adapter->fdir_pballoc;
3522 else
3523 hdrm = 0;
80605c65 3524
f7e1027f 3525 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3526 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3527}
3528
e4911d57
AD		 3529static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3530{
3531 struct ixgbe_hw *hw = &adapter->hw;
3532 struct hlist_node *node, *node2;
3533 struct ixgbe_fdir_filter *filter;
3534
3535 spin_lock(&adapter->fdir_perfect_lock);
3536
3537 if (!hlist_empty(&adapter->fdir_filter_list))
3538 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3539
3540 hlist_for_each_entry_safe(filter, node, node2,
3541 &adapter->fdir_filter_list, fdir_node) {
3542 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3543 &filter->filter,
3544 filter->sw_idx,
3545 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3546 IXGBE_FDIR_DROP_QUEUE :
3547 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3548 }
3549
3550 spin_unlock(&adapter->fdir_perfect_lock);
3551}
3552
9a799d71
AK		 3553static void ixgbe_configure(struct ixgbe_adapter *adapter)
3554{
80605c65 3555 ixgbe_configure_pb(adapter);
7a6b6f51 3556#ifdef CONFIG_IXGBE_DCB
67ebd791 3557 ixgbe_configure_dcb(adapter);
2f90b865 3558#endif
9a799d71 3559
4c1d7b4b 3560 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3561 ixgbe_restore_vlan(adapter);
3562
eacd73f7
YZ		 3563#ifdef IXGBE_FCOE
3564 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3565 ixgbe_configure_fcoe(adapter);
3566
3567#endif /* IXGBE_FCOE */
c4cf55e5 3568 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3569 ixgbe_init_fdir_signature_82599(&adapter->hw,
3570 adapter->fdir_pballoc);
e4911d57
AD		 3571 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3572 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3573 adapter->fdir_pballoc);
3574 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3575 }
4c1d7b4b 3576
933d41f1 3577 ixgbe_configure_virtualization(adapter);
c4cf55e5 3578
9a799d71
AK		 3579 ixgbe_configure_tx(adapter);
3580 ixgbe_configure_rx(adapter);
9a799d71
AK		 3581}
3582
e8e26350
PW		 3583static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3584{
3585 switch (hw->phy.type) {
3586 case ixgbe_phy_sfp_avago:
3587 case ixgbe_phy_sfp_ftl:
3588 case ixgbe_phy_sfp_intel:
3589 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3590 case ixgbe_phy_sfp_passive_tyco:
3591 case ixgbe_phy_sfp_passive_unknown:
3592 case ixgbe_phy_sfp_active_unknown:
3593 case ixgbe_phy_sfp_ftl_active:
e8e26350 3594 return true;
8917b447
AD		 3595 case ixgbe_phy_nl:
3596 if (hw->mac.type == ixgbe_mac_82598EB)
3597 return true;
e8e26350
PW		 3598 default:
3599 return false;
3600 }
3601}
3602
0ecc061d 3603/**
e8e26350
PW		 3604 * ixgbe_sfp_link_config - set up SFP+ link
3605 * @adapter: pointer to private adapter struct
3606 **/
3607static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3608{
7086400d 3609 /*
52f33af8 3610 * We are assuming the worst case scenario here, and that
7086400d
AD		 3611 * is that an SFP was inserted/removed after the reset
3612 * but before SFP detection was enabled. As such the best
3613 * solution is to just start searching as soon as we start
3614 */
3615 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3616 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3617
7086400d 3618 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3619}
3620
3621/**
3622 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3623 * @hw: pointer to private hardware struct
3624 *
3625 * Returns 0 on success, negative on failure
3626 **/
e8e26350 3627static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3628{
3629 u32 autoneg;
8620a103 3630 bool negotiation, link_up = false;
0ecc061d
PWJ		 3631 u32 ret = IXGBE_ERR_LINK_SETUP;
3632
3633 if (hw->mac.ops.check_link)
3634 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3635
3636 if (ret)
3637 goto link_cfg_out;
3638
0b0c2b31
ET		 3639 autoneg = hw->phy.autoneg_advertised;
3640 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3641 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3642 &negotiation);
0ecc061d
PWJ		 3643 if (ret)
3644 goto link_cfg_out;
3645
8620a103
MC		 3646 if (hw->mac.ops.setup_link)
3647 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3648link_cfg_out:
3649 return ret;
3650}
3651
a34bcfff 3652static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3653{
9a799d71 3654 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3655 u32 gpie = 0;
9a799d71 3656
9b471446 3657 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3658 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3659 IXGBE_GPIE_OCD;
3660 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3661 /*
3662 * use EIAM to auto-mask when MSI-X interrupt is asserted
3663 * this saves a register write for every interrupt
3664 */
3665 switch (hw->mac.type) {
3666 case ixgbe_mac_82598EB:
3667 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3668 break;
9b471446 3669 case ixgbe_mac_82599EB:
b93a2226
DS		 3670 case ixgbe_mac_X540:
3671 default:
9b471446
JB		 3672 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3673 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3674 break;
3675 }
3676 } else {
021230d4
AV		 3677 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3678 * specifically only auto mask tx and rx interrupts */
3679 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3680 }
9a799d71 3681
a34bcfff
AD		 3682 /* XXX: to interrupt immediately for EICS writes, enable this */
3683 /* gpie |= IXGBE_GPIE_EIMEN; */
3684
3685 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3686 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3687 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3688 }
3689
5fdd31f9 3690 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3691 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3692 switch (adapter->hw.mac.type) {
3693 case ixgbe_mac_82599EB:
3694 gpie |= IXGBE_SDP0_GPIEN;
3695 break;
3696 case ixgbe_mac_X540:
3697 gpie |= IXGBE_EIMS_TS;
3698 break;
3699 default:
3700 break;
3701 }
3702 }
5fdd31f9 3703
a34bcfff
AD		 3704 /* Enable fan failure interrupt */
3705 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3706 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3707
2698b208 3708 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3709 gpie |= IXGBE_SDP1_GPIEN;
3710 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3711 }
a34bcfff
AD		 3712
3713 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3714}
3715
c7ccde0f 3716static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3717{
3718 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3719 int err;
a34bcfff
AD		 3720 u32 ctrl_ext;
3721
3722 ixgbe_get_hw_control(adapter);
3723 ixgbe_setup_gpie(adapter);
e8e26350 3724
9a799d71
AK		 3725 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3726 ixgbe_configure_msix(adapter);
3727 else
3728 ixgbe_configure_msi_and_legacy(adapter);
3729
c6ecf39a
DS		 3730 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3731 if (hw->mac.ops.enable_tx_laser &&
3732 ((hw->phy.multispeed_fiber) ||
9f911707 3733 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3734 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3735 hw->mac.ops.enable_tx_laser(hw);
3736
9a799d71 3737 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3738 ixgbe_napi_enable_all(adapter);
3739
73c4b7cd
AD		 3740 if (ixgbe_is_sfp(hw)) {
3741 ixgbe_sfp_link_config(adapter);
3742 } else {
3743 err = ixgbe_non_sfp_link_config(hw);
3744 if (err)
3745 e_err(probe, "link_config FAILED %d\n", err);
3746 }
3747
021230d4
AV		 3748 /* clear any pending interrupts, may auto mask */
3749 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3750 ixgbe_irq_enable(adapter, true, true);
9a799d71 3751
bf069c97
DS		 3752 /*
3753 * If this adapter has a fan, check to see if we had a failure
3754 * before we enabled the interrupt.
3755 */
3756 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3757 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3758 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3759 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3760 }
3761
1da100bb 3762 /* enable transmits */
477de6ed 3763 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3764
9a799d71
AK		 3765 /* bring the link up in the watchdog, this could race with our first
3766 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3767 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3768 adapter->link_check_timeout = jiffies;
7086400d 3769 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3770
3771 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3772 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3773 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3774 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3775}
3776
d4f80882
AV		 3777void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3778{
3779 WARN_ON(in_interrupt());
7086400d
AD		 3780 /* put off any impending NetWatchDogTimeout */
3781 adapter->netdev->trans_start = jiffies;
3782
d4f80882 3783 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3784 usleep_range(1000, 2000);
d4f80882 3785 ixgbe_down(adapter);
5809a1ae
GR		 3786 /*
3787 * If SR-IOV enabled then wait a bit before bringing the adapter
3788 * back up to give the VFs time to respond to the reset. The
3789 * two second wait is based upon the watchdog timer cycle in
3790 * the VF driver.
3791 */
3792 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3793 msleep(2000);
d4f80882
AV		 3794 ixgbe_up(adapter);
3795 clear_bit(__IXGBE_RESETTING, &adapter->state);
3796}
3797
c7ccde0f 3798void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 3799{
3800 /* hardware has been reset, we need to reload some things */
3801 ixgbe_configure(adapter);
3802
c7ccde0f 3803 ixgbe_up_complete(adapter);
9a799d71
AK		 3804}
3805
3806void ixgbe_reset(struct ixgbe_adapter *adapter)
3807{
c44ade9e 3808 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 3809 int err;
3810
7086400d
AD		 3811 /* lock SFP init bit to prevent race conditions with the watchdog */
3812 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3813 usleep_range(1000, 2000);
3814
3815 /* clear all SFP and link config related flags while holding SFP_INIT */
3816 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3817 IXGBE_FLAG2_SFP_NEEDS_RESET);
3818 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3819
8ca783ab 3820 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 3821 switch (err) {
3822 case 0:
3823 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 3824 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 3825 break;
3826 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 3827 e_dev_err("master disable timed out\n");
da4dd0f7 3828 break;
794caeb2
PWJ		 3829 case IXGBE_ERR_EEPROM_VERSION:
3830 /* We are running on a pre-production device, log a warning */
849c4542 3831 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 3832 "Please be aware there may be issues associated with "
849c4542
ET		 3833 "your hardware. If you are experiencing problems "
3834 "please contact your Intel or hardware "
3835 "representative who provided you with this "
3836 "hardware.\n");
794caeb2 3837 break;
da4dd0f7 3838 default:
849c4542 3839 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 3840 }
9a799d71 3841
7086400d
AD		 3842 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
3843
9a799d71 3844 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 3845 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3846 IXGBE_RAH_AV);
9a799d71
AK		 3847}
3848
9a799d71
AK		 3849/**
3850 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 3851 * @rx_ring: ring to free buffers from
3852 **/
b6ec895e 3853static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 3854{
b6ec895e 3855 struct device *dev = rx_ring->dev;
9a799d71 3856 unsigned long size;
b6ec895e 3857 u16 i;
9a799d71 3858
84418e3b
AD		 3859 /* ring already cleared, nothing to do */
3860 if (!rx_ring->rx_buffer_info)
3861 return;
9a799d71 3862
84418e3b 3863 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 3864 for (i = 0; i < rx_ring->count; i++) {
3865 struct ixgbe_rx_buffer *rx_buffer_info;
3866
3867 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3868 if (rx_buffer_info->dma) {
b6ec895e 3869 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 3870 rx_ring->rx_buf_len,
1b507730 3871 DMA_FROM_DEVICE);
9a799d71
AK		 3872 rx_buffer_info->dma = 0;
3873 }
3874 if (rx_buffer_info->skb) {
f8212f97 3875 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 3876 rx_buffer_info->skb = NULL;
f8212f97
AD		 3877 do {
3878 struct sk_buff *this = skb;
e8171aaa 3879 if (IXGBE_RSC_CB(this)->delay_unmap) {
b6ec895e 3880 dma_unmap_single(dev,
1b507730 3881 IXGBE_RSC_CB(this)->dma,
e8e9f696 3882 rx_ring->rx_buf_len,
1b507730 3883 DMA_FROM_DEVICE);
fd3686a8 3884 IXGBE_RSC_CB(this)->dma = 0;
e8171aaa 3885 IXGBE_RSC_CB(skb)->delay_unmap = false;
fd3686a8 3886 }
f8212f97
AD		 3887 skb = skb->prev;
3888 dev_kfree_skb(this);
3889 } while (skb);
9a799d71
AK		 3890 }
3891 if (!rx_buffer_info->page)
3892 continue;
4f57ca6e 3893 if (rx_buffer_info->page_dma) {
b6ec895e 3894 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 3895 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 3896 rx_buffer_info->page_dma = 0;
3897 }
9a799d71
AK		 3898 put_page(rx_buffer_info->page);
3899 rx_buffer_info->page = NULL;
762f4c57 3900 rx_buffer_info->page_offset = 0;
9a799d71
AK		 3901 }
3902
3903 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3904 memset(rx_ring->rx_buffer_info, 0, size);
3905
3906 /* Zero out the descriptor ring */
3907 memset(rx_ring->desc, 0, rx_ring->size);
3908
3909 rx_ring->next_to_clean = 0;
3910 rx_ring->next_to_use = 0;
9a799d71
AK		 3911}
3912
3913/**
3914 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 3915 * @tx_ring: ring to be cleaned
3916 **/
b6ec895e 3917static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 3918{
3919 struct ixgbe_tx_buffer *tx_buffer_info;
3920 unsigned long size;
b6ec895e 3921 u16 i;
9a799d71 3922
84418e3b
AD		 3923 /* ring already cleared, nothing to do */
3924 if (!tx_ring->tx_buffer_info)
3925 return;
9a799d71 3926
84418e3b 3927 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 3928 for (i = 0; i < tx_ring->count; i++) {
3929 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 3930 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 3931 }
3932
3933 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3934 memset(tx_ring->tx_buffer_info, 0, size);
3935
3936 /* Zero out the descriptor ring */
3937 memset(tx_ring->desc, 0, tx_ring->size);
3938
3939 tx_ring->next_to_use = 0;
3940 tx_ring->next_to_clean = 0;
9a799d71
AK		 3941}
3942
3943/**
021230d4 3944 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 3945 * @adapter: board private structure
3946 **/
021230d4 3947static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3948{
3949 int i;
3950
021230d4 3951 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 3952 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 3953}
3954
3955/**
021230d4 3956 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 3957 * @adapter: board private structure
3958 **/
021230d4 3959static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 3960{
3961 int i;
3962
021230d4 3963 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 3964 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 3965}
3966
e4911d57
AD		 3967static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
3968{
3969 struct hlist_node *node, *node2;
3970 struct ixgbe_fdir_filter *filter;
3971
3972 spin_lock(&adapter->fdir_perfect_lock);
3973
3974 hlist_for_each_entry_safe(filter, node, node2,
3975 &adapter->fdir_filter_list, fdir_node) {
3976 hlist_del(&filter->fdir_node);
3977 kfree(filter);
3978 }
3979 adapter->fdir_filter_count = 0;
3980
3981 spin_unlock(&adapter->fdir_perfect_lock);
3982}
3983
9a799d71
AK		 3984void ixgbe_down(struct ixgbe_adapter *adapter)
3985{
3986 struct net_device *netdev = adapter->netdev;
7f821875 3987 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 3988 u32 rxctrl;
bf29ee6c 3989 int i;
9a799d71
AK		 3990
3991 /* signal that we are down to the interrupt handler */
3992 set_bit(__IXGBE_DOWN, &adapter->state);
3993
3994 /* disable receives */
7f821875
JB		 3995 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3996 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 3997
2d39d576
YZ		 3998 /* disable all enabled rx queues */
3999 for (i = 0; i < adapter->num_rx_queues; i++)
4000 /* this call also flushes the previous write */
4001 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4002
032b4325 4003 usleep_range(10000, 20000);
9a799d71 4004
7f821875
JB		 4005 netif_tx_stop_all_queues(netdev);
4006
7086400d 4007 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4008 netif_carrier_off(netdev);
4009 netif_tx_disable(netdev);
4010
4011 ixgbe_irq_disable(adapter);
4012
4013 ixgbe_napi_disable_all(adapter);
4014
d034acf1
AD		 4015 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4016 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4017 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4018
4019 del_timer_sync(&adapter->service_timer);
4020
34cecbbf 4021 if (adapter->num_vfs) {
8e34d1aa
AD		 4022 /* Clear EITR Select mapping */
4023 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4024
4025 /* Mark all the VFs as inactive */
4026 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4027 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4028
34cecbbf
AD		 4029 /* ping all the active vfs to let them know we are going down */
4030 ixgbe_ping_all_vfs(adapter);
4031
4032 /* Disable all VFTE/VFRE TX/RX */
4033 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4034 }
4035
7f821875
JB		 4036 /* disable transmits in the hardware now that interrupts are off */
4037 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4038 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4039 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4040 }
34cecbbf
AD		 4041
4042 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4043 switch (hw->mac.type) {
4044 case ixgbe_mac_82599EB:
b93a2226 4045 case ixgbe_mac_X540:
88512539 4046 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4047 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4048 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4049 break;
4050 default:
4051 break;
4052 }
7f821875 4053
6f4a0e45
PL		 4054 if (!pci_channel_offline(adapter->pdev))
4055 ixgbe_reset(adapter);
c6ecf39a
DS		 4056
4057 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4058 if (hw->mac.ops.disable_tx_laser &&
4059 ((hw->phy.multispeed_fiber) ||
9f911707 4060 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4061 (hw->mac.type == ixgbe_mac_82599EB))))
4062 hw->mac.ops.disable_tx_laser(hw);
4063
9a799d71
AK		 4064 ixgbe_clean_all_tx_rings(adapter);
4065 ixgbe_clean_all_rx_rings(adapter);
4066
5dd2d332 4067#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4068 /* since we reset the hardware DCA settings were cleared */
e35ec126 4069 ixgbe_setup_dca(adapter);
96b0e0f6 4070#endif
9a799d71
AK		 4071}
4072
9a799d71 4073/**
021230d4
AV		 4074 * ixgbe_poll - NAPI Rx polling callback
4075 * @napi: structure for representing this polling device
4076 * @budget: how many packets driver is allowed to clean
4077 *
4078 * This function is used for legacy and MSI, NAPI mode
9a799d71 4079 **/
021230d4 4080static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4081{
9a1a69ad 4082 struct ixgbe_q_vector *q_vector =
e8e9f696 4083 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4084 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4085 struct ixgbe_ring *ring;
4086 int per_ring_budget;
4087 bool clean_complete = true;
9a799d71 4088
5dd2d332 4089#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4090 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4091 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4092#endif
4093
4ff7fb12
AD		 4094 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4095 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4096
4ff7fb12
AD		 4097 /* attempt to distribute budget to each queue fairly, but don't allow
4098 * the budget to go below 1 because we'll exit polling */
4099 if (q_vector->rx.count > 1)
4100 per_ring_budget = max(budget/q_vector->rx.count, 1);
4101 else
4102 per_ring_budget = budget;
d2c7ddd6 4103
4ff7fb12
AD		 4104 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4105 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4106 per_ring_budget);
4107
4108 /* If all work not completed, return budget and keep polling */
4109 if (!clean_complete)
4110 return budget;
4111
4112 /* all work done, exit the polling mode */
4113 napi_complete(napi);
4114 if (adapter->rx_itr_setting & 1)
4115 ixgbe_set_itr(q_vector);
4116 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4117 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4118
4119 return 0;
9a799d71
AK		 4120}
4121
4122/**
4123 * ixgbe_tx_timeout - Respond to a Tx Hang
4124 * @netdev: network interface device structure
4125 **/
4126static void ixgbe_tx_timeout(struct net_device *netdev)
4127{
4128 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4129
4130 /* Do the reset outside of interrupt context */
c83c6cbd 4131 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4132}
4133
4df10466
JB		 4134/**
4135 * ixgbe_set_rss_queues: Allocate queues for RSS
4136 * @adapter: board private structure to initialize
4137 *
4138 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4139 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4140 *
4141 **/
bc97114d
PWJ		 4142static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4143{
4144 bool ret = false;
0cefafad 4145 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4146
4147 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4148 f->mask = 0xF;
4149 adapter->num_rx_queues = f->indices;
4150 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4151 ret = true;
4152 } else {
bc97114d 4153 ret = false;
b9804972
JB		 4154 }
4155
bc97114d
PWJ		 4156 return ret;
4157}
4158
c4cf55e5
PWJ		 4159/**
4160 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4161 * @adapter: board private structure to initialize
4162 *
4163 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4164 * to the original CPU that initiated the Tx session. This runs in addition
4165 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4166 * Rx load across CPUs using RSS.
4167 *
4168 **/
e8e9f696 4169static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4170{
4171 bool ret = false;
4172 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4173
4174 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4175 f_fdir->mask = 0;
4176
4177 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4178 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4179 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4180 adapter->num_tx_queues = f_fdir->indices;
4181 adapter->num_rx_queues = f_fdir->indices;
4182 ret = true;
4183 } else {
4184 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4185 }
4186 return ret;
4187}
4188
0331a832
YZ		 4189#ifdef IXGBE_FCOE
4190/**
4191 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4192 * @adapter: board private structure to initialize
4193 *
4194 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4195 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4196 * rx queues out of the max number of rx queues, instead, it is used as the
4197 * index of the first rx queue used by FCoE.
4198 *
4199 **/
4200static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4201{
0331a832
YZ		 4202 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4203
e5b64635
JF		 4204 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4205 return false;
4206
e901acd6 4207 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4208
e901acd6
JF		 4209 adapter->num_rx_queues = 1;
4210 adapter->num_tx_queues = 1;
e5b64635 4211
e901acd6
JF		 4212 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4213 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4214 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4215 ixgbe_set_fdir_queues(adapter);
4216 else
4217 ixgbe_set_rss_queues(adapter);
e5b64635 4218 }
03ecf91a 4219
e901acd6
JF		 4220 /* adding FCoE rx rings to the end */
4221 f->mask = adapter->num_rx_queues;
4222 adapter->num_rx_queues += f->indices;
4223 adapter->num_tx_queues += f->indices;
0331a832 4224
e5b64635
JF		 4225 return true;
4226}
4227#endif /* IXGBE_FCOE */
4228
e901acd6
JF		 4229/* Artificial max queue cap per traffic class in DCB mode */
4230#define DCB_QUEUE_CAP 8
4231
e5b64635
JF		 4232#ifdef CONFIG_IXGBE_DCB
4233static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4234{
e901acd6
JF		 4235 int per_tc_q, q, i, offset = 0;
4236 struct net_device *dev = adapter->netdev;
4237 int tcs = netdev_get_num_tc(dev);
e5b64635 4238
e901acd6
JF		 4239 if (!tcs)
4240 return false;
e5b64635 4241
e901acd6
JF		 4242 /* Map queue offset and counts onto allocated tx queues */
4243 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4244 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4245
8b1c0b24 4246 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4247 netdev_set_tc_queue(dev, i, q, offset);
4248 offset += q;
0331a832
YZ		 4249 }
4250
e901acd6
JF		 4251 adapter->num_tx_queues = q * tcs;
4252 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4253
4254#ifdef IXGBE_FCOE
e901acd6
JF		 4255 /* FCoE enabled queues require special configuration indexed
4256 * by feature specific indices and mask. Here we map FCoE
4257 * indices onto the DCB queue pairs allowing FCoE to own
4258 * configuration later.
e5b64635 4259 */
e901acd6
JF		 4260 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4261 int tc;
4262 struct ixgbe_ring_feature *f =
4263 &adapter->ring_feature[RING_F_FCOE];
4264
4265 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4266 f->indices = dev->tc_to_txq[tc].count;
4267 f->mask = dev->tc_to_txq[tc].offset;
4268 }
e5b64635
JF		 4269#endif
4270
e901acd6 4271 return true;
0331a832 4272}
e5b64635 4273#endif
0331a832 4274
1cdd1ec8
GR		 4275/**
4276 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4277 * @adapter: board private structure to initialize
4278 *
4279 * IOV doesn't actually use anything, so just NAK the
4280 * request for now and let the other queue routines
4281 * figure out what to do.
4282 */
4283static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4284{
4285 return false;
4286}
4287
4df10466 4288/*
25985edc 4289 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4290 * @adapter: board private structure to initialize
4291 *
4292 * This is the top level queue allocation routine. The order here is very
4293 * important, starting with the "most" number of features turned on at once,
4294 * and ending with the smallest set of features. This way large combinations
4295 * can be allocated if they're turned on, and smaller combinations are the
4296 * fallthrough conditions.
4297 *
4298 **/
847f53ff 4299static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4300{
1cdd1ec8
GR		 4301 /* Start with base case */
4302 adapter->num_rx_queues = 1;
4303 adapter->num_tx_queues = 1;
4304 adapter->num_rx_pools = adapter->num_rx_queues;
4305 adapter->num_rx_queues_per_pool = 1;
4306
4307 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4308 goto done;
1cdd1ec8 4309
bc97114d
PWJ		 4310#ifdef CONFIG_IXGBE_DCB
4311 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4312 goto done;
bc97114d
PWJ		 4313
4314#endif
e5b64635
JF		 4315#ifdef IXGBE_FCOE
4316 if (ixgbe_set_fcoe_queues(adapter))
4317 goto done;
4318
4319#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4320 if (ixgbe_set_fdir_queues(adapter))
4321 goto done;
4322
bc97114d 4323 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4324 goto done;
4325
4326 /* fallback to base case */
4327 adapter->num_rx_queues = 1;
4328 adapter->num_tx_queues = 1;
4329
4330done:
847f53ff 4331 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4332 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4333 return netif_set_real_num_rx_queues(adapter->netdev,
4334 adapter->num_rx_queues);
b9804972
JB		 4335}
4336
021230d4 4337static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4338 int vectors)
021230d4
AV		 4339{
4340 int err, vector_threshold;
4341
4342 /* We'll want at least 3 (vector_threshold):
4343 * 1) TxQ[0] Cleanup
4344 * 2) RxQ[0] Cleanup
4345 * 3) Other (Link Status Change, etc.)
4346 * 4) TCP Timer (optional)
4347 */
4348 vector_threshold = MIN_MSIX_COUNT;
4349
4350 /* The more we get, the more we will assign to Tx/Rx Cleanup
4351 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4352 * Right now, we simply care about how many we'll get; we'll
4353 * set them up later while requesting irq's.
4354 */
4355 while (vectors >= vector_threshold) {
4356 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4357 vectors);
021230d4
AV		 4358 if (!err) /* Success in acquiring all requested vectors. */
4359 break;
4360 else if (err < 0)
4361 vectors = 0; /* Nasty failure, quit now */
4362 else /* err == number of vectors we should try again with */
4363 vectors = err;
4364 }
4365
4366 if (vectors < vector_threshold) {
4367 /* Can't allocate enough MSI-X interrupts? Oh well.
4368 * This just means we'll go with either a single MSI
4369 * vector or fall back to legacy interrupts.
4370 */
849c4542
ET		 4371 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4372 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4373 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4374 kfree(adapter->msix_entries);
4375 adapter->msix_entries = NULL;
021230d4
AV		 4376 } else {
4377 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4378 /*
4379 * Adjust for only the vectors we'll use, which is minimum
4380 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4381 * vectors we were allocated.
4382 */
4383 adapter->num_msix_vectors = min(vectors,
e8e9f696 4384 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4385 }
4386}
4387
021230d4 4388/**
bc97114d 4389 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4390 * @adapter: board private structure to initialize
4391 *
bc97114d
PWJ		 4392 * Cache the descriptor ring offsets for RSS to the assigned rings.
4393 *
021230d4 4394 **/
bc97114d 4395static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4396{
bc97114d 4397 int i;
bc97114d 4398
9d6b758f
AD		 4399 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4400 return false;
bc97114d 4401
9d6b758f
AD		 4402 for (i = 0; i < adapter->num_rx_queues; i++)
4403 adapter->rx_ring[i]->reg_idx = i;
4404 for (i = 0; i < adapter->num_tx_queues; i++)
4405 adapter->tx_ring[i]->reg_idx = i;
4406
4407 return true;
bc97114d
PWJ		 4408}
4409
4410#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4411
4412/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4413static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4414 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4415{
4416 struct net_device *dev = adapter->netdev;
4417 struct ixgbe_hw *hw = &adapter->hw;
4418 u8 num_tcs = netdev_get_num_tc(dev);
4419
4420 *tx = 0;
4421 *rx = 0;
4422
4423 switch (hw->mac.type) {
4424 case ixgbe_mac_82598EB:
aba70d5e
JF		 4425 *tx = tc << 2;
4426 *rx = tc << 3;
e5b64635
JF		 4427 break;
4428 case ixgbe_mac_82599EB:
4429 case ixgbe_mac_X540:
4fa2e0e1 4430 if (num_tcs > 4) {
e5b64635
JF		 4431 if (tc < 3) {
4432 *tx = tc << 5;
4433 *rx = tc << 4;
4434 } else if (tc < 5) {
4435 *tx = ((tc + 2) << 4);
4436 *rx = tc << 4;
4437 } else if (tc < num_tcs) {
4438 *tx = ((tc + 8) << 3);
4439 *rx = tc << 4;
4440 }
4fa2e0e1 4441 } else {
e5b64635
JF		 4442 *rx = tc << 5;
4443 switch (tc) {
4444 case 0:
4445 *tx = 0;
4446 break;
4447 case 1:
4448 *tx = 64;
4449 break;
4450 case 2:
4451 *tx = 96;
4452 break;
4453 case 3:
4454 *tx = 112;
4455 break;
4456 default:
4457 break;
4458 }
4459 }
4460 break;
4461 default:
4462 break;
4463 }
4464}
4465
bc97114d
PWJ		 4466/**
4467 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4468 * @adapter: board private structure to initialize
4469 *
4470 * Cache the descriptor ring offsets for DCB to the assigned rings.
4471 *
4472 **/
4473static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4474{
e5b64635
JF		 4475 struct net_device *dev = adapter->netdev;
4476 int i, j, k;
4477 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4478
8b1c0b24 4479 if (!num_tcs)
bd508178 4480 return false;
f92ef202 4481
e5b64635
JF		 4482 for (i = 0, k = 0; i < num_tcs; i++) {
4483 unsigned int tx_s, rx_s;
4484 u16 count = dev->tc_to_txq[i].count;
4485
4486 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4487 for (j = 0; j < count; j++, k++) {
4488 adapter->tx_ring[k]->reg_idx = tx_s + j;
4489 adapter->rx_ring[k]->reg_idx = rx_s + j;
4490 adapter->tx_ring[k]->dcb_tc = i;
4491 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4492 }
021230d4 4493 }
e5b64635
JF		 4494
4495 return true;
bc97114d
PWJ		 4496}
4497#endif
4498
c4cf55e5
PWJ		 4499/**
4500 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4501 * @adapter: board private structure to initialize
4502 *
4503 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4504 *
4505 **/
e8e9f696 4506static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4507{
4508 int i;
4509 bool ret = false;
4510
03ecf91a
AD		 4511 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4512 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4513 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4514 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4515 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4516 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4517 ret = true;
4518 }
4519
4520 return ret;
4521}
4522
0331a832
YZ		 4523#ifdef IXGBE_FCOE
4524/**
4525 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4526 * @adapter: board private structure to initialize
4527 *
4528 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4529 *
4530 */
4531static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4532{
0331a832 4533 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4534 int i;
4535 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4536
4537 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4538 return false;
0331a832 4539
bf29ee6c 4540 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4541 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4542 ixgbe_cache_ring_fdir(adapter);
4543 else
4544 ixgbe_cache_ring_rss(adapter);
8faa2a78 4545
bf29ee6c
AD		 4546 fcoe_rx_i = f->mask;
4547 fcoe_tx_i = f->mask;
0331a832 4548 }
bf29ee6c
AD		 4549 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4550 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4551 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4552 }
4553 return true;
0331a832
YZ		 4554}
4555
4556#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4557/**
4558 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4559 * @adapter: board private structure to initialize
4560 *
4561 * SR-IOV doesn't use any descriptor rings but changes the default if
4562 * no other mapping is used.
4563 *
4564 */
4565static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4566{
4a0b9ca0
PW		 4567 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4568 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4569 if (adapter->num_vfs)
4570 return true;
4571 else
4572 return false;
4573}
4574
bc97114d
PWJ		 4575/**
4576 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4577 * @adapter: board private structure to initialize
4578 *
4579 * Once we know the feature-set enabled for the device, we'll cache
4580 * the register offset the descriptor ring is assigned to.
4581 *
4582 * Note, the order the various feature calls is important. It must start with
4583 * the "most" features enabled at the same time, then trickle down to the
4584 * least amount of features turned on at once.
4585 **/
4586static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4587{
4588 /* start with default case */
4a0b9ca0
PW		 4589 adapter->rx_ring[0]->reg_idx = 0;
4590 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4591
1cdd1ec8
GR		 4592 if (ixgbe_cache_ring_sriov(adapter))
4593 return;
4594
e5b64635
JF		 4595#ifdef CONFIG_IXGBE_DCB
4596 if (ixgbe_cache_ring_dcb(adapter))
4597 return;
4598#endif
4599
0331a832
YZ		 4600#ifdef IXGBE_FCOE
4601 if (ixgbe_cache_ring_fcoe(adapter))
4602 return;
0331a832 4603#endif /* IXGBE_FCOE */
bc97114d 4604
c4cf55e5
PWJ		 4605 if (ixgbe_cache_ring_fdir(adapter))
4606 return;
4607
bc97114d
PWJ		 4608 if (ixgbe_cache_ring_rss(adapter))
4609 return;
021230d4
AV		 4610}
4611
9a799d71
AK		 4612/**
4613 * ixgbe_alloc_queues - Allocate memory for all rings
4614 * @adapter: board private structure to initialize
4615 *
4616 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4617 * number of queues at compile-time. The polling_netdev array is
4618 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4619 **/
2f90b865 4620static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4621{
e2ddeba9 4622 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4623
e2ddeba9
ED		 4624 if (nid < 0 || !node_online(nid))
4625 nid = first_online_node;
4626
4627 for (; tx < adapter->num_tx_queues; tx++) {
4628 struct ixgbe_ring *ring;
4629
4630 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4631 if (!ring)
e2ddeba9 4632 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4633 if (!ring)
e2ddeba9 4634 goto err_allocation;
4a0b9ca0 4635 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4636 ring->queue_index = tx;
4637 ring->numa_node = nid;
b6ec895e 4638 ring->dev = &adapter->pdev->dev;
fc77dc3c 4639 ring->netdev = adapter->netdev;
4a0b9ca0 4640
e2ddeba9 4641 adapter->tx_ring[tx] = ring;
021230d4 4642 }
b9804972 4643
e2ddeba9
ED		 4644 for (; rx < adapter->num_rx_queues; rx++) {
4645 struct ixgbe_ring *ring;
4a0b9ca0 4646
e2ddeba9 4647 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4648 if (!ring)
e2ddeba9 4649 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4650 if (!ring)
e2ddeba9
ED		 4651 goto err_allocation;
4652 ring->count = adapter->rx_ring_count;
4653 ring->queue_index = rx;
4654 ring->numa_node = nid;
b6ec895e 4655 ring->dev = &adapter->pdev->dev;
fc77dc3c 4656 ring->netdev = adapter->netdev;
4a0b9ca0 4657
e2ddeba9 4658 adapter->rx_ring[rx] = ring;
021230d4
AV		 4659 }
4660
4661 ixgbe_cache_ring_register(adapter);
4662
4663 return 0;
4664
e2ddeba9
ED		 4665err_allocation:
4666 while (tx)
4667 kfree(adapter->tx_ring[--tx]);
4668
4669 while (rx)
4670 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4671 return -ENOMEM;
4672}
4673
4674/**
4675 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4676 * @adapter: board private structure to initialize
4677 *
4678 * Attempt to configure the interrupts using the best available
4679 * capabilities of the hardware and the kernel.
4680 **/
feea6a57 4681static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4682{
8be0e467 4683 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4684 int err = 0;
4685 int vector, v_budget;
4686
4687 /*
4688 * It's easy to be greedy for MSI-X vectors, but it really
4689 * doesn't do us much good if we have a lot more vectors
4690 * than CPU's. So let's be conservative and only ask for
342bde1b 4691 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4692 */
4693 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4694 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4695
4696 /*
4697 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4698 * hw.mac->max_msix_vectors vectors. With features
4699 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4700 * descriptor queues supported by our device. Thus, we cap it off in
4701 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4702 */
8be0e467 4703 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4704
4705 /* A failure in MSI-X entry allocation isn't fatal, but it does
4706 * mean we disable MSI-X capabilities of the adapter. */
4707 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4708 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4709 if (adapter->msix_entries) {
4710 for (vector = 0; vector < v_budget; vector++)
4711 adapter->msix_entries[vector].entry = vector;
021230d4 4712
7a921c93 4713 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4714
7a921c93
AD		 4715 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4716 goto out;
4717 }
26d27844 4718
7a921c93
AD		 4719 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4720 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4721 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4722 e_err(probe,
03ecf91a 4723 "ATR is not supported while multiple "
45b9f509
AD		 4724 "queues are disabled. Disabling Flow Director\n");
4725 }
c4cf55e5 4726 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4727 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4728 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4729 ixgbe_disable_sriov(adapter);
4730
847f53ff
BH		 4731 err = ixgbe_set_num_queues(adapter);
4732 if (err)
4733 return err;
021230d4 4734
021230d4
AV		 4735 err = pci_enable_msi(adapter->pdev);
4736 if (!err) {
4737 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4738 } else {
849c4542
ET		 4739 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4740 "Unable to allocate MSI interrupt, "
4741 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4742 /* reset err */
4743 err = 0;
4744 }
4745
4746out:
021230d4
AV		 4747 return err;
4748}
4749
7a921c93
AD		 4750/**
4751 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4752 * @adapter: board private structure to initialize
4753 *
4754 * We allocate one q_vector per queue interrupt. If allocation fails we
4755 * return -ENOMEM.
4756 **/
4757static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4758{
4ff7fb12 4759 int v_idx, num_q_vectors;
7a921c93 4760 struct ixgbe_q_vector *q_vector;
7a921c93 4761
4ff7fb12 4762 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4763 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4764 else
7a921c93 4765 num_q_vectors = 1;
7a921c93 4766
4ff7fb12 4767 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4768 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4769 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4770 if (!q_vector)
4771 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4772 GFP_KERNEL);
7a921c93
AD		 4773 if (!q_vector)
4774 goto err_out;
4ff7fb12 4775
7a921c93 4776 q_vector->adapter = adapter;
4ff7fb12
AD		 4777 q_vector->v_idx = v_idx;
4778
207867f5
AD		 4779 /* Allocate the affinity_hint cpumask, configure the mask */
4780 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4781 goto err_out;
4782 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 4783 netif_napi_add(adapter->netdev, &q_vector->napi,
4784 ixgbe_poll, 64);
4785 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 4786 }
4787
4788 return 0;
4789
4790err_out:
4ff7fb12
AD		 4791 while (v_idx) {
4792 v_idx--;
4793 q_vector = adapter->q_vector[v_idx];
7a921c93 4794 netif_napi_del(&q_vector->napi);
207867f5 4795 free_cpumask_var(q_vector->affinity_mask);
7a921c93 4796 kfree(q_vector);
4ff7fb12 4797 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 4798 }
4799 return -ENOMEM;
4800}
4801
4802/**
4803 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4804 * @adapter: board private structure to initialize
4805 *
4806 * This function frees the memory allocated to the q_vectors. In addition if
4807 * NAPI is enabled it will delete any references to the NAPI struct prior
4808 * to freeing the q_vector.
4809 **/
4810static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4811{
207867f5 4812 int v_idx, num_q_vectors;
7a921c93 4813
91281fd3 4814 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4815 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 4816 else
7a921c93 4817 num_q_vectors = 1;
7a921c93 4818
207867f5
AD		 4819 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
4820 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
4821 adapter->q_vector[v_idx] = NULL;
91281fd3 4822 netif_napi_del(&q_vector->napi);
207867f5 4823 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 4824 kfree(q_vector);
4825 }
4826}
4827
7b25cdba 4828static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 4829{
4830 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4831 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4832 pci_disable_msix(adapter->pdev);
4833 kfree(adapter->msix_entries);
4834 adapter->msix_entries = NULL;
4835 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4836 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4837 pci_disable_msi(adapter->pdev);
4838 }
021230d4
AV		 4839}
4840
4841/**
4842 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4843 * @adapter: board private structure to initialize
4844 *
4845 * We determine which interrupt scheme to use based on...
4846 * - Kernel support (MSI, MSI-X)
4847 * - which can be user-defined (via MODULE_PARAM)
4848 * - Hardware queue count (num_*_queues)
4849 * - defined by miscellaneous hardware support/features (RSS, etc.)
4850 **/
2f90b865 4851int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 4852{
4853 int err;
4854
4855 /* Number of supported queues */
847f53ff
BH		 4856 err = ixgbe_set_num_queues(adapter);
4857 if (err)
4858 return err;
021230d4 4859
021230d4
AV		 4860 err = ixgbe_set_interrupt_capability(adapter);
4861 if (err) {
849c4542 4862 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 4863 goto err_set_interrupt;
9a799d71
AK		 4864 }
4865
7a921c93
AD		 4866 err = ixgbe_alloc_q_vectors(adapter);
4867 if (err) {
849c4542 4868 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 4869 goto err_alloc_q_vectors;
4870 }
4871
4872 err = ixgbe_alloc_queues(adapter);
4873 if (err) {
849c4542 4874 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 4875 goto err_alloc_queues;
4876 }
4877
849c4542 4878 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 4879 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4880 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 4881
4882 set_bit(__IXGBE_DOWN, &adapter->state);
4883
9a799d71 4884 return 0;
021230d4 4885
7a921c93
AD		 4886err_alloc_queues:
4887 ixgbe_free_q_vectors(adapter);
4888err_alloc_q_vectors:
4889 ixgbe_reset_interrupt_capability(adapter);
021230d4 4890err_set_interrupt:
7a921c93
AD		 4891 return err;
4892}
4893
4894/**
4895 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4896 * @adapter: board private structure to clear interrupt scheme on
4897 *
4898 * We go through and clear interrupt specific resources and reset the structure
4899 * to pre-load conditions
4900 **/
4901void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4902{
4a0b9ca0
PW		 4903 int i;
4904
4905 for (i = 0; i < adapter->num_tx_queues; i++) {
4906 kfree(adapter->tx_ring[i]);
4907 adapter->tx_ring[i] = NULL;
4908 }
4909 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 4910 struct ixgbe_ring *ring = adapter->rx_ring[i];
4911
4912 /* ixgbe_get_stats64() might access this ring, we must wait
4913 * a grace period before freeing it.
4914 */
bcec8b65 4915 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 4916 adapter->rx_ring[i] = NULL;
4917 }
7a921c93 4918
b8eb3a10
DS		 4919 adapter->num_tx_queues = 0;
4920 adapter->num_rx_queues = 0;
4921
7a921c93
AD		 4922 ixgbe_free_q_vectors(adapter);
4923 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 4924}
4925
4926/**
4927 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4928 * @adapter: board private structure to initialize
4929 *
4930 * ixgbe_sw_init initializes the Adapter private data structure.
4931 * Fields are initialized based on PCI device information and
4932 * OS network device settings (MTU size).
4933 **/
4934static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4935{
4936 struct ixgbe_hw *hw = &adapter->hw;
4937 struct pci_dev *pdev = adapter->pdev;
021230d4 4938 unsigned int rss;
7a6b6f51 4939#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4940 int j;
4941 struct tc_configuration *tc;
4942#endif
021230d4 4943
c44ade9e
JB		 4944 /* PCI config space info */
4945
4946 hw->vendor_id = pdev->vendor;
4947 hw->device_id = pdev->device;
4948 hw->revision_id = pdev->revision;
4949 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4950 hw->subsystem_device_id = pdev->subsystem_device;
4951
021230d4
AV		 4952 /* Set capability flags */
4953 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4954 adapter->ring_feature[RING_F_RSS].indices = rss;
4955 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 4956 switch (hw->mac.type) {
4957 case ixgbe_mac_82598EB:
bf069c97
DS		 4958 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4959 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 4960 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 4961 break;
b93a2226 4962 case ixgbe_mac_X540:
4f51bf70
JK		 4963 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4964 case ixgbe_mac_82599EB:
e8e26350 4965 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 4966 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4967 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 4968 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4969 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 4970 /* Flow Director hash filters enabled */
4971 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4972 adapter->atr_sample_rate = 20;
c4cf55e5 4973 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 4974 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 4975 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 4976#ifdef IXGBE_FCOE
0d551589
YZ		 4977 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4978 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4979 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 4980#ifdef CONFIG_IXGBE_DCB
6ee16520 4981 /* Default traffic class to use for FCoE */
56075a98 4982 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 4983#endif
eacd73f7 4984#endif /* IXGBE_FCOE */
bd508178
AD		 4985 break;
4986 default:
4987 break;
f8212f97 4988 }
2f90b865 4989
1fc5f038
AD		 4990 /* n-tuple support exists, always init our spinlock */
4991 spin_lock_init(&adapter->fdir_perfect_lock);
4992
7a6b6f51 4993#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4994 switch (hw->mac.type) {
4995 case ixgbe_mac_X540:
4996 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4997 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4998 break;
4999 default:
5000 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5001 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5002 break;
5003 }
5004
2f90b865
AD		 5005 /* Configure DCB traffic classes */
5006 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5007 tc = &adapter->dcb_cfg.tc_config[j];
5008 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5009 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5010 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5011 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5012 tc->dcb_pfc = pfc_disabled;
5013 }
4de2a022
JF		 5014
5015 /* Initialize default user to priority mapping, UPx->TC0 */
5016 tc = &adapter->dcb_cfg.tc_config[0];
5017 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5018 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5019
2f90b865
AD		 5020 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5021 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5022 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5023 adapter->dcb_set_bitmap = 0x00;
3032309b 5024 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5025 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5026 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5027
5028#endif
9a799d71
AK		 5029
5030 /* default flow control settings */
cd7664f6 5031 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5032 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5033#ifdef CONFIG_DCB
5034 adapter->last_lfc_mode = hw->fc.current_mode;
5035#endif
9da712d2 5036 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5037 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5038 hw->fc.send_xon = true;
71fd570b 5039 hw->fc.disable_fc_autoneg = false;
9a799d71 5040
30efa5a3 5041 /* enable itr by default in dynamic mode */
f7554a2b 5042 adapter->rx_itr_setting = 1;
f7554a2b 5043 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5044
5045 /* set defaults for eitr in MegaBytes */
5046 adapter->eitr_low = 10;
5047 adapter->eitr_high = 20;
5048
5049 /* set default ring sizes */
5050 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5051 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5052
bd198058 5053 /* set default work limits */
59224555 5054 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5055
9a799d71 5056 /* initialize eeprom parameters */
c44ade9e 5057 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5058 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5059 return -EIO;
5060 }
5061
021230d4 5062 /* enable rx csum by default */
9a799d71
AK		 5063 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5064
1a6c14a2
JB		 5065 /* get assigned NUMA node */
5066 adapter->node = dev_to_node(&pdev->dev);
5067
9a799d71
AK		 5068 set_bit(__IXGBE_DOWN, &adapter->state);
5069
5070 return 0;
5071}
5072
5073/**
5074 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5075 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5076 *
5077 * Return 0 on success, negative on failure
5078 **/
b6ec895e 5079int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5080{
b6ec895e 5081 struct device *dev = tx_ring->dev;
9a799d71
AK		 5082 int size;
5083
3a581073 5084 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5085 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5086 if (!tx_ring->tx_buffer_info)
89bf67f1 5087 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5088 if (!tx_ring->tx_buffer_info)
5089 goto err;
9a799d71
AK		 5090
5091 /* round up to nearest 4K */
12207e49 5092 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5093 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5094
b6ec895e 5095 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5096 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5097 if (!tx_ring->desc)
5098 goto err;
9a799d71 5099
3a581073
JB		 5100 tx_ring->next_to_use = 0;
5101 tx_ring->next_to_clean = 0;
9a799d71 5102 return 0;
e01c31a5
JB		 5103
5104err:
5105 vfree(tx_ring->tx_buffer_info);
5106 tx_ring->tx_buffer_info = NULL;
b6ec895e 5107 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5108 return -ENOMEM;
9a799d71
AK		 5109}
5110
69888674
AD		 5111/**
5112 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5113 * @adapter: board private structure
5114 *
5115 * If this function returns with an error, then it's possible one or
5116 * more of the rings is populated (while the rest are not). It is the
5117 * callers duty to clean those orphaned rings.
5118 *
5119 * Return 0 on success, negative on failure
5120 **/
5121static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5122{
5123 int i, err = 0;
5124
5125 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5126 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5127 if (!err)
5128 continue;
396e799c 5129 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5130 break;
5131 }
5132
5133 return err;
5134}
5135
9a799d71
AK		 5136/**
5137 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5138 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5139 *
5140 * Returns 0 on success, negative on failure
5141 **/
b6ec895e 5142int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5143{
b6ec895e 5144 struct device *dev = rx_ring->dev;
021230d4 5145 int size;
9a799d71 5146
3a581073 5147 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5148 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5149 if (!rx_ring->rx_buffer_info)
89bf67f1 5150 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5151 if (!rx_ring->rx_buffer_info)
5152 goto err;
9a799d71 5153
9a799d71 5154 /* Round up to nearest 4K */
3a581073
JB		 5155 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5156 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5157
b6ec895e 5158 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5159 &rx_ring->dma, GFP_KERNEL);
9a799d71 5160
b6ec895e
AD		 5161 if (!rx_ring->desc)
5162 goto err;
9a799d71 5163
3a581073
JB		 5164 rx_ring->next_to_clean = 0;
5165 rx_ring->next_to_use = 0;
9a799d71
AK		 5166
5167 return 0;
b6ec895e
AD		 5168err:
5169 vfree(rx_ring->rx_buffer_info);
5170 rx_ring->rx_buffer_info = NULL;
5171 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5172 return -ENOMEM;
9a799d71
AK		 5173}
5174
69888674
AD		 5175/**
5176 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5177 * @adapter: board private structure
5178 *
5179 * If this function returns with an error, then it's possible one or
5180 * more of the rings is populated (while the rest are not). It is the
5181 * callers duty to clean those orphaned rings.
5182 *
5183 * Return 0 on success, negative on failure
5184 **/
69888674
AD		 5185static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5186{
5187 int i, err = 0;
5188
5189 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5190 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5191 if (!err)
5192 continue;
396e799c 5193 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5194 break;
5195 }
5196
5197 return err;
5198}
5199
9a799d71
AK		 5200/**
5201 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5202 * @tx_ring: Tx descriptor ring for a specific queue
5203 *
5204 * Free all transmit software resources
5205 **/
b6ec895e 5206void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5207{
b6ec895e 5208 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5209
5210 vfree(tx_ring->tx_buffer_info);
5211 tx_ring->tx_buffer_info = NULL;
5212
b6ec895e
AD		 5213 /* if not set, then don't free */
5214 if (!tx_ring->desc)
5215 return;
5216
5217 dma_free_coherent(tx_ring->dev, tx_ring->size,
5218 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5219
5220 tx_ring->desc = NULL;
5221}
5222
5223/**
5224 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5225 * @adapter: board private structure
5226 *
5227 * Free all transmit software resources
5228 **/
5229static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5230{
5231 int i;
5232
5233 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5234 if (adapter->tx_ring[i]->desc)
b6ec895e 5235 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5236}
5237
5238/**
b4617240 5239 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5240 * @rx_ring: ring to clean the resources from
5241 *
5242 * Free all receive software resources
5243 **/
b6ec895e 5244void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5245{
b6ec895e 5246 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5247
5248 vfree(rx_ring->rx_buffer_info);
5249 rx_ring->rx_buffer_info = NULL;
5250
b6ec895e
AD		 5251 /* if not set, then don't free */
5252 if (!rx_ring->desc)
5253 return;
5254
5255 dma_free_coherent(rx_ring->dev, rx_ring->size,
5256 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5257
5258 rx_ring->desc = NULL;
5259}
5260
5261/**
5262 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5263 * @adapter: board private structure
5264 *
5265 * Free all receive software resources
5266 **/
5267static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5268{
5269 int i;
5270
5271 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5272 if (adapter->rx_ring[i]->desc)
b6ec895e 5273 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5274}
5275
9a799d71
AK		 5276/**
5277 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5278 * @netdev: network interface device structure
5279 * @new_mtu: new value for maximum frame size
5280 *
5281 * Returns 0 on success, negative on failure
5282 **/
5283static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5284{
5285 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5286 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5287 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5288
42c783c5 5289 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5290 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5291 hw->mac.type != ixgbe_mac_X540) {
5292 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5293 return -EINVAL;
5294 } else {
5295 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5296 return -EINVAL;
5297 }
9a799d71 5298
396e799c 5299 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5300 /* must set new MTU before calling down or up */
9a799d71
AK		 5301 netdev->mtu = new_mtu;
5302
d4f80882
AV		 5303 if (netif_running(netdev))
5304 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5305
5306 return 0;
5307}
5308
5309/**
5310 * ixgbe_open - Called when a network interface is made active
5311 * @netdev: network interface device structure
5312 *
5313 * Returns 0 on success, negative value on failure
5314 *
5315 * The open entry point is called when a network interface is made
5316 * active by the system (IFF_UP). At this point all resources needed
5317 * for transmit and receive operations are allocated, the interrupt
5318 * handler is registered with the OS, the watchdog timer is started,
5319 * and the stack is notified that the interface is ready.
5320 **/
5321static int ixgbe_open(struct net_device *netdev)
5322{
5323 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5324 int err;
4bebfaa5
AK		 5325
5326 /* disallow open during test */
5327 if (test_bit(__IXGBE_TESTING, &adapter->state))
5328 return -EBUSY;
9a799d71 5329
54386467
JB		 5330 netif_carrier_off(netdev);
5331
9a799d71
AK		 5332 /* allocate transmit descriptors */
5333 err = ixgbe_setup_all_tx_resources(adapter);
5334 if (err)
5335 goto err_setup_tx;
5336
9a799d71
AK		 5337 /* allocate receive descriptors */
5338 err = ixgbe_setup_all_rx_resources(adapter);
5339 if (err)
5340 goto err_setup_rx;
5341
5342 ixgbe_configure(adapter);
5343
021230d4 5344 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5345 if (err)
5346 goto err_req_irq;
5347
c7ccde0f 5348 ixgbe_up_complete(adapter);
9a799d71
AK		 5349
5350 return 0;
5351
9a799d71 5352err_req_irq:
9a799d71 5353err_setup_rx:
a20a1199 5354 ixgbe_free_all_rx_resources(adapter);
9a799d71 5355err_setup_tx:
a20a1199 5356 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5357 ixgbe_reset(adapter);
5358
5359 return err;
5360}
5361
5362/**
5363 * ixgbe_close - Disables a network interface
5364 * @netdev: network interface device structure
5365 *
5366 * Returns 0, this is not allowed to fail
5367 *
5368 * The close entry point is called when an interface is de-activated
5369 * by the OS. The hardware is still under the drivers control, but
5370 * needs to be disabled. A global MAC reset is issued to stop the
5371 * hardware, and all transmit and receive resources are freed.
5372 **/
5373static int ixgbe_close(struct net_device *netdev)
5374{
5375 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5376
5377 ixgbe_down(adapter);
5378 ixgbe_free_irq(adapter);
5379
e4911d57
AD		 5380 ixgbe_fdir_filter_exit(adapter);
5381
9a799d71
AK		 5382 ixgbe_free_all_tx_resources(adapter);
5383 ixgbe_free_all_rx_resources(adapter);
5384
5eba3699 5385 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5386
5387 return 0;
5388}
5389
b3c8b4ba
AD		 5390#ifdef CONFIG_PM
5391static int ixgbe_resume(struct pci_dev *pdev)
5392{
c60fbb00
AD		 5393 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5394 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5395 u32 err;
5396
5397 pci_set_power_state(pdev, PCI_D0);
5398 pci_restore_state(pdev);
656ab817
DS		 5399 /*
5400 * pci_restore_state clears dev->state_saved so call
5401 * pci_save_state to restore it.
5402 */
5403 pci_save_state(pdev);
9ce77666 5404
5405 err = pci_enable_device_mem(pdev);
b3c8b4ba 5406 if (err) {
849c4542 5407 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5408 return err;
5409 }
5410 pci_set_master(pdev);
5411
dd4d8ca6 5412 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5413
5414 err = ixgbe_init_interrupt_scheme(adapter);
5415 if (err) {
849c4542 5416 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5417 return err;
5418 }
5419
b3c8b4ba
AD		 5420 ixgbe_reset(adapter);
5421
495dce12
WJP		 5422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5423
b3c8b4ba 5424 if (netif_running(netdev)) {
c60fbb00 5425 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5426 if (err)
5427 return err;
5428 }
5429
5430 netif_device_attach(netdev);
5431
5432 return 0;
5433}
b3c8b4ba 5434#endif /* CONFIG_PM */
9d8d05ae
RW		 5435
5436static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5437{
c60fbb00
AD		 5438 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5439 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5440 struct ixgbe_hw *hw = &adapter->hw;
5441 u32 ctrl, fctrl;
5442 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5443#ifdef CONFIG_PM
5444 int retval = 0;
5445#endif
5446
5447 netif_device_detach(netdev);
5448
5449 if (netif_running(netdev)) {
5450 ixgbe_down(adapter);
5451 ixgbe_free_irq(adapter);
5452 ixgbe_free_all_tx_resources(adapter);
5453 ixgbe_free_all_rx_resources(adapter);
5454 }
b3c8b4ba 5455
5f5ae6fc 5456 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5457#ifdef CONFIG_DCB
5458 kfree(adapter->ixgbe_ieee_pfc);
5459 kfree(adapter->ixgbe_ieee_ets);
5460#endif
5f5ae6fc 5461
b3c8b4ba
AD		 5462#ifdef CONFIG_PM
5463 retval = pci_save_state(pdev);
5464 if (retval)
5465 return retval;
4df10466 5466
b3c8b4ba 5467#endif
e8e26350
PW		 5468 if (wufc) {
5469 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5470
e8e26350
PW		 5471 /* turn on all-multi mode if wake on multicast is enabled */
5472 if (wufc & IXGBE_WUFC_MC) {
5473 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5474 fctrl |= IXGBE_FCTRL_MPE;
5475 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5476 }
5477
5478 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5479 ctrl |= IXGBE_CTRL_GIO_DIS;
5480 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5481
5482 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5483 } else {
5484 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5485 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5486 }
5487
bd508178
AD		 5488 switch (hw->mac.type) {
5489 case ixgbe_mac_82598EB:
dd4d8ca6 5490 pci_wake_from_d3(pdev, false);
bd508178
AD		 5491 break;
5492 case ixgbe_mac_82599EB:
b93a2226 5493 case ixgbe_mac_X540:
bd508178
AD		 5494 pci_wake_from_d3(pdev, !!wufc);
5495 break;
5496 default:
5497 break;
5498 }
b3c8b4ba 5499
9d8d05ae
RW		 5500 *enable_wake = !!wufc;
5501
b3c8b4ba
AD		 5502 ixgbe_release_hw_control(adapter);
5503
5504 pci_disable_device(pdev);
5505
9d8d05ae
RW		 5506 return 0;
5507}
5508
5509#ifdef CONFIG_PM
5510static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5511{
5512 int retval;
5513 bool wake;
5514
5515 retval = __ixgbe_shutdown(pdev, &wake);
5516 if (retval)
5517 return retval;
5518
5519 if (wake) {
5520 pci_prepare_to_sleep(pdev);
5521 } else {
5522 pci_wake_from_d3(pdev, false);
5523 pci_set_power_state(pdev, PCI_D3hot);
5524 }
b3c8b4ba
AD		 5525
5526 return 0;
5527}
9d8d05ae 5528#endif /* CONFIG_PM */
b3c8b4ba
AD		 5529
5530static void ixgbe_shutdown(struct pci_dev *pdev)
5531{
9d8d05ae
RW		 5532 bool wake;
5533
5534 __ixgbe_shutdown(pdev, &wake);
5535
5536 if (system_state == SYSTEM_POWER_OFF) {
5537 pci_wake_from_d3(pdev, wake);
5538 pci_set_power_state(pdev, PCI_D3hot);
5539 }
b3c8b4ba
AD		 5540}
5541
9a799d71
AK		 5542/**
5543 * ixgbe_update_stats - Update the board statistics counters.
5544 * @adapter: board private structure
5545 **/
5546void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5547{
2d86f139 5548 struct net_device *netdev = adapter->netdev;
9a799d71 5549 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5550 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5551 u64 total_mpc = 0;
5552 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5553 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5554 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5555 u64 bytes = 0, packets = 0;
7b859ebc
AH		 5556#ifdef IXGBE_FCOE
5557 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5558 unsigned int cpu;
5559 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5560#endif /* IXGBE_FCOE */
9a799d71 5561
d08935c2
DS		 5562 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5563 test_bit(__IXGBE_RESETTING, &adapter->state))
5564 return;
5565
94b982b2 5566 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5567 u64 rsc_count = 0;
94b982b2 5568 u64 rsc_flush = 0;
d51019a4
PW		 5569 for (i = 0; i < 16; i++)
5570 adapter->hw_rx_no_dma_resources +=
7ca647bd 5571 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5572 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5573 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5574 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5575 }
5576 adapter->rsc_total_count = rsc_count;
5577 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5578 }
5579
5b7da515
AD		 5580 for (i = 0; i < adapter->num_rx_queues; i++) {
5581 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5582 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5583 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5584 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5585 bytes += rx_ring->stats.bytes;
5586 packets += rx_ring->stats.packets;
5587 }
5588 adapter->non_eop_descs = non_eop_descs;
5589 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5590 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5591 netdev->stats.rx_bytes = bytes;
5592 netdev->stats.rx_packets = packets;
5593
5594 bytes = 0;
5595 packets = 0;
7ca3bc58 5596 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5597 for (i = 0; i < adapter->num_tx_queues; i++) {
5598 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5599 restart_queue += tx_ring->tx_stats.restart_queue;
5600 tx_busy += tx_ring->tx_stats.tx_busy;
5601 bytes += tx_ring->stats.bytes;
5602 packets += tx_ring->stats.packets;
5603 }
eb985f09 5604 adapter->restart_queue = restart_queue;
5b7da515
AD		 5605 adapter->tx_busy = tx_busy;
5606 netdev->stats.tx_bytes = bytes;
5607 netdev->stats.tx_packets = packets;
7ca3bc58 5608
7ca647bd 5609 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5610
5611 /* 8 register reads */
6f11eef7
AV		 5612 for (i = 0; i < 8; i++) {
5613 /* for packet buffers not used, the register should read 0 */
5614 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5615 missed_rx += mpc;
7ca647bd
JP		 5616 hwstats->mpc[i] += mpc;
5617 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5618 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5619 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5620 switch (hw->mac.type) {
5621 case ixgbe_mac_82598EB:
1a70db4b
ET		 5622 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5623 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5624 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5625 hwstats->pxonrxc[i] +=
5626 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5627 break;
5628 case ixgbe_mac_82599EB:
b93a2226 5629 case ixgbe_mac_X540:
bd508178
AD		 5630 hwstats->pxonrxc[i] +=
5631 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5632 break;
5633 default:
5634 break;
e8e26350 5635 }
6f11eef7 5636 }
1a70db4b
ET		 5637
5638 /*16 register reads */
5639 for (i = 0; i < 16; i++) {
5640 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5641 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5642 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5643 (hw->mac.type == ixgbe_mac_X540)) {
5644 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5645 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5646 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5647 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5648 }
5649 }
5650
7ca647bd 5651 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5652 /* work around hardware counting issue */
7ca647bd 5653 hwstats->gprc -= missed_rx;
6f11eef7 5654
c84d324c
JF		 5655 ixgbe_update_xoff_received(adapter);
5656
6f11eef7 5657 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5658 switch (hw->mac.type) {
5659 case ixgbe_mac_82598EB:
5660 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5661 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5662 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5663 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5664 break;
b93a2226 5665 case ixgbe_mac_X540:
58f6bcf9
ET		 5666 /* OS2BMC stats are X540 only*/
5667 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5668 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5669 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5670 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5671 case ixgbe_mac_82599EB:
7ca647bd 5672 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5673 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5674 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5675 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5676 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5677 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5678 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5679 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5680 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5681#ifdef IXGBE_FCOE
7ca647bd
JP		 5682 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5683 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5684 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5685 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5686 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5687 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5688 /* Add up per cpu counters for total ddp aloc fail */
5689 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5690 for_each_possible_cpu(cpu) {
5691 fcoe_noddp_counts_sum +=
5692 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5693 fcoe_noddp_ext_buff_counts_sum +=
5694 *per_cpu_ptr(fcoe->
5695 pcpu_noddp_ext_buff, cpu);
5696 }
5697 }
5698 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5699 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5700#endif /* IXGBE_FCOE */
bd508178
AD		 5701 break;
5702 default:
5703 break;
e8e26350 5704 }
9a799d71 5705 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5706 hwstats->bprc += bprc;
5707 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5708 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5709 hwstats->mprc -= bprc;
5710 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5711 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5712 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5713 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5714 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5715 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5716 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5717 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5718 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5719 hwstats->lxontxc += lxon;
6f11eef7 5720 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5721 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5722 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5723 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5724 /*
5725 * 82598 errata - tx of flow control packets is included in tx counters
5726 */
5727 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5728 hwstats->gptc -= xon_off_tot;
5729 hwstats->mptc -= xon_off_tot;
5730 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5731 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5732 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5733 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5734 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5735 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5736 hwstats->ptc64 -= xon_off_tot;
5737 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5738 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5739 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5740 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5741 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5742 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5743
5744 /* Fill out the OS statistics structure */
7ca647bd 5745 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5746
5747 /* Rx Errors */
7ca647bd 5748 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5749 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5750 netdev->stats.rx_length_errors = hwstats->rlec;
5751 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5752 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5753}
5754
5755/**
d034acf1
AD		 5756 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5757 * @adapter - pointer to the device adapter structure
9a799d71 5758 **/
d034acf1 5759static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5760{
cf8280ee 5761 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5762 int i;
cf8280ee 5763
d034acf1
AD		 5764 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5765 return;
5766
5767 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5768
d034acf1 5769 /* if interface is down do nothing */
fe49f04a 5770 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5771 return;
5772
5773 /* do nothing if we are not using signature filters */
5774 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5775 return;
5776
5777 adapter->fdir_overflow++;
5778
93c52dd0
AD		 5779 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5780 for (i = 0; i < adapter->num_tx_queues; i++)
5781 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5782 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5783 /* re-enable flow director interrupts */
5784 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5785 } else {
5786 e_err(probe, "failed to finish FDIR re-initialization, "
5787 "ignored adding FDIR ATR filters\n");
5788 }
93c52dd0
AD		 5789}
5790
5791/**
5792 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5793 * @adapter - pointer to the device adapter structure
5794 *
5795 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5796 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5797 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5798 * determine if a hang has occurred.
93c52dd0
AD		 5799 */
5800static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5801{
cf8280ee 5802 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5803 u64 eics = 0;
5804 int i;
cf8280ee 5805
93c52dd0
AD		 5806 /* If we're down or resetting, just bail */
5807 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5808 test_bit(__IXGBE_RESETTING, &adapter->state))
5809 return;
22d5a71b 5810
93c52dd0
AD		 5811 /* Force detection of hung controller */
5812 if (netif_carrier_ok(adapter->netdev)) {
5813 for (i = 0; i < adapter->num_tx_queues; i++)
5814 set_check_for_tx_hang(adapter->tx_ring[i]);
5815 }
22d5a71b 5816
fe49f04a
AD		 5817 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5818 /*
5819 * for legacy and MSI interrupts don't set any bits
5820 * that are enabled for EIAM, because this operation
5821 * would set *both* EIMS and EICS for any bit in EIAM
5822 */
5823 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5824 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5825 } else {
5826 /* get one bit for every active tx/rx interrupt vector */
5827 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5828 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5829 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5830 eics |= ((u64)1 << i);
5831 }
cf8280ee 5832 }
9a799d71 5833
93c52dd0 5834 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5835 ixgbe_irq_rearm_queues(adapter, eics);
5836
cf8280ee
JB		 5837}
5838
e8e26350 5839/**
93c52dd0
AD		 5840 * ixgbe_watchdog_update_link - update the link status
5841 * @adapter - pointer to the device adapter structure
5842 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 5843 **/
93c52dd0 5844static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5845{
e8e26350 5846 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5847 u32 link_speed = adapter->link_speed;
5848 bool link_up = adapter->link_up;
c4cf55e5 5849 int i;
e8e26350 5850
93c52dd0
AD		 5851 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5852 return;
5853
5854 if (hw->mac.ops.check_link) {
5855 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5856 } else {
93c52dd0
AD		 5857 /* always assume link is up, if no check link function */
5858 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5859 link_up = true;
c4cf55e5 5860 }
93c52dd0
AD		 5861 if (link_up) {
5862 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5863 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5864 hw->mac.ops.fc_enable(hw, i);
5865 } else {
5866 hw->mac.ops.fc_enable(hw, 0);
5867 }
5868 }
5869
5870 if (link_up ||
5871 time_after(jiffies, (adapter->link_check_timeout +
5872 IXGBE_TRY_LINK_TIMEOUT))) {
5873 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5874 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5875 IXGBE_WRITE_FLUSH(hw);
5876 }
5877
5878 adapter->link_up = link_up;
5879 adapter->link_speed = link_speed;
e8e26350
PW		 5880}
5881
5882/**
93c52dd0
AD		 5883 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5884 * print link up message
5885 * @adapter - pointer to the device adapter structure
e8e26350 5886 **/
93c52dd0 5887static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5888{
93c52dd0 5889 struct net_device *netdev = adapter->netdev;
e8e26350 5890 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5891 u32 link_speed = adapter->link_speed;
5892 bool flow_rx, flow_tx;
e8e26350 5893
93c52dd0
AD		 5894 /* only continue if link was previously down */
5895 if (netif_carrier_ok(netdev))
a985b6c3 5896 return;
63d6e1d8 5897
93c52dd0 5898 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5899
93c52dd0
AD		 5900 switch (hw->mac.type) {
5901 case ixgbe_mac_82598EB: {
5902 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5903 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5904 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5905 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5906 }
5907 break;
5908 case ixgbe_mac_X540:
5909 case ixgbe_mac_82599EB: {
5910 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5911 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5912 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5913 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5914 }
5915 break;
5916 default:
5917 flow_tx = false;
5918 flow_rx = false;
5919 break;
e8e26350 5920 }
93c52dd0
AD		 5921 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5922 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5923 "10 Gbps" :
5924 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5925 "1 Gbps" :
5926 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5927 "100 Mbps" :
5928 "unknown speed"))),
5929 ((flow_rx && flow_tx) ? "RX/TX" :
5930 (flow_rx ? "RX" :
5931 (flow_tx ? "TX" : "None"))));
e8e26350 5932
93c52dd0 5933 netif_carrier_on(netdev);
93c52dd0 5934 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 5935}
5936
c4cf55e5 5937/**
93c52dd0
AD		 5938 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5939 * print link down message
5940 * @adapter - pointer to the adapter structure
c4cf55e5 5941 **/
93c52dd0 5942static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 5943{
cf8280ee 5944 struct net_device *netdev = adapter->netdev;
c4cf55e5 5945 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5946
93c52dd0
AD		 5947 adapter->link_up = false;
5948 adapter->link_speed = 0;
cf8280ee 5949
93c52dd0
AD		 5950 /* only continue if link was up previously */
5951 if (!netif_carrier_ok(netdev))
5952 return;
264857b8 5953
93c52dd0
AD		 5954 /* poll for SFP+ cable when link is down */
5955 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5956 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5957
93c52dd0
AD		 5958 e_info(drv, "NIC Link is Down\n");
5959 netif_carrier_off(netdev);
5960}
e8e26350 5961
93c52dd0
AD		 5962/**
5963 * ixgbe_watchdog_flush_tx - flush queues on link down
5964 * @adapter - pointer to the device adapter structure
5965 **/
5966static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5967{
c4cf55e5 5968 int i;
93c52dd0 5969 int some_tx_pending = 0;
c4cf55e5 5970
93c52dd0 5971 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5972 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5973 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5974 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5975 some_tx_pending = 1;
5976 break;
5977 }
5978 }
5979
5980 if (some_tx_pending) {
5981 /* We've lost link, so the controller stops DMA,
5982 * but we've got queued Tx work that's never going
5983 * to get done, so reset controller to flush Tx.
5984 * (Do the reset outside of interrupt context).
5985 */
c83c6cbd 5986 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5987 }
c4cf55e5 5988 }
c4cf55e5
PWJ		 5989}
5990
a985b6c3
GR		 5991static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5992{
5993 u32 ssvpc;
5994
5995 /* Do not perform spoof check for 82598 */
5996 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5997 return;
5998
5999 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6000
6001 /*
6002 * ssvpc register is cleared on read, if zero then no
6003 * spoofed packets in the last interval.
6004 */
6005 if (!ssvpc)
6006 return;
6007
6008 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6009}
6010
93c52dd0
AD		 6011/**
6012 * ixgbe_watchdog_subtask - check and bring link up
6013 * @adapter - pointer to the device adapter structure
6014 **/
6015static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6016{
6017 /* if interface is down do nothing */
7edebf9a
ET		 6018 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6019 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6020 return;
6021
6022 ixgbe_watchdog_update_link(adapter);
6023
6024 if (adapter->link_up)
6025 ixgbe_watchdog_link_is_up(adapter);
6026 else
6027 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6028
a985b6c3 6029 ixgbe_spoof_check(adapter);
9a799d71 6030 ixgbe_update_stats(adapter);
93c52dd0
AD		 6031
6032 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6033}
10eec955 6034
cf8280ee 6035/**
7086400d
AD		 6036 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6037 * @adapter - the ixgbe adapter structure
cf8280ee 6038 **/
7086400d 6039static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6040{
cf8280ee 6041 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6042 s32 err;
cf8280ee 6043
7086400d
AD		 6044 /* not searching for SFP so there is nothing to do here */
6045 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6046 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6047 return;
10eec955 6048
7086400d
AD		 6049 /* someone else is in init, wait until next service event */
6050 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6051 return;
cf8280ee 6052
7086400d
AD		 6053 err = hw->phy.ops.identify_sfp(hw);
6054 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6055 goto sfp_out;
264857b8 6056
7086400d
AD		 6057 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6058 /* If no cable is present, then we need to reset
6059 * the next time we find a good cable. */
6060 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6061 }
9a799d71 6062
7086400d
AD		 6063 /* exit on error */
6064 if (err)
6065 goto sfp_out;
e8e26350 6066
7086400d
AD		 6067 /* exit if reset not needed */
6068 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6069 goto sfp_out;
9a799d71 6070
7086400d 6071 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6072
7086400d
AD		 6073 /*
6074 * A module may be identified correctly, but the EEPROM may not have
6075 * support for that module. setup_sfp() will fail in that case, so
6076 * we should not allow that module to load.
6077 */
6078 if (hw->mac.type == ixgbe_mac_82598EB)
6079 err = hw->phy.ops.reset(hw);
6080 else
6081 err = hw->mac.ops.setup_sfp(hw);
6082
6083 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6084 goto sfp_out;
6085
6086 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6087 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6088
6089sfp_out:
6090 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6091
6092 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6093 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6094 e_dev_err("failed to initialize because an unsupported "
6095 "SFP+ module type was detected.\n");
6096 e_dev_err("Reload the driver after installing a "
6097 "supported module.\n");
6098 unregister_netdev(adapter->netdev);
bc59fcda 6099 }
7086400d 6100}
bc59fcda 6101
7086400d
AD		 6102/**
6103 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6104 * @adapter - the ixgbe adapter structure
6105 **/
6106static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6107{
6108 struct ixgbe_hw *hw = &adapter->hw;
6109 u32 autoneg;
6110 bool negotiation;
6111
6112 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6113 return;
6114
6115 /* someone else is in init, wait until next service event */
6116 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6117 return;
6118
6119 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6120
6121 autoneg = hw->phy.autoneg_advertised;
6122 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6123 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6124 if (hw->mac.ops.setup_link)
6125 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6126
6127 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6128 adapter->link_check_timeout = jiffies;
6129 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6130}
6131
83c61fa9
GR		 6132#ifdef CONFIG_PCI_IOV
6133static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6134{
6135 int vf;
6136 struct ixgbe_hw *hw = &adapter->hw;
6137 struct net_device *netdev = adapter->netdev;
6138 u32 gpc;
6139 u32 ciaa, ciad;
6140
6141 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6142 if (gpc) /* If incrementing then no need for the check below */
6143 return;
6144 /*
6145 * Check to see if a bad DMA write target from an errant or
6146 * malicious VF has caused a PCIe error. If so then we can
6147 * issue a VFLR to the offending VF(s) and then resume without
6148 * requesting a full slot reset.
6149 */
6150
6151 for (vf = 0; vf < adapter->num_vfs; vf++) {
6152 ciaa = (vf << 16) | 0x80000000;
6153 /* 32 bit read so align, we really want status at offset 6 */
6154 ciaa |= PCI_COMMAND;
6155 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6156 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6157 ciaa &= 0x7FFFFFFF;
6158 /* disable debug mode asap after reading data */
6159 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6160 /* Get the upper 16 bits which will be the PCI status reg */
6161 ciad >>= 16;
6162 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6163 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6164 /* Issue VFLR */
6165 ciaa = (vf << 16) | 0x80000000;
6166 ciaa |= 0xA8;
6167 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6168 ciad = 0x00008000; /* VFLR */
6169 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6170 ciaa &= 0x7FFFFFFF;
6171 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6172 }
6173 }
6174}
6175
6176#endif
7086400d
AD		 6177/**
6178 * ixgbe_service_timer - Timer Call-back
6179 * @data: pointer to adapter cast into an unsigned long
6180 **/
6181static void ixgbe_service_timer(unsigned long data)
6182{
6183 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6184 unsigned long next_event_offset;
83c61fa9 6185 bool ready = true;
7086400d 6186
83c61fa9
GR		 6187#ifdef CONFIG_PCI_IOV
6188 ready = false;
6189
6190 /*
6191 * don't bother with SR-IOV VF DMA hang check if there are
6192 * no VFs or the link is down
6193 */
6194 if (!adapter->num_vfs ||
6195 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6196 ready = true;
6197 goto normal_timer_service;
6198 }
6199
6200 /* If we have VFs allocated then we must check for DMA hangs */
6201 ixgbe_check_for_bad_vf(adapter);
6202 next_event_offset = HZ / 50;
6203 adapter->timer_event_accumulator++;
6204
6205 if (adapter->timer_event_accumulator >= 100) {
6206 ready = true;
6207 adapter->timer_event_accumulator = 0;
6208 }
6209
6210 goto schedule_event;
6211
6212normal_timer_service:
6213#endif
7086400d
AD		 6214 /* poll faster when waiting for link */
6215 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6216 next_event_offset = HZ / 10;
6217 else
6218 next_event_offset = HZ * 2;
6219
83c61fa9
GR		 6220#ifdef CONFIG_PCI_IOV
6221schedule_event:
6222#endif
7086400d
AD		 6223 /* Reset the timer */
6224 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6225
83c61fa9
GR		 6226 if (ready)
6227 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6228}
6229
c83c6cbd
AD		 6230static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6231{
6232 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6233 return;
6234
6235 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6236
6237 /* If we're already down or resetting, just bail */
6238 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6239 test_bit(__IXGBE_RESETTING, &adapter->state))
6240 return;
6241
6242 ixgbe_dump(adapter);
6243 netdev_err(adapter->netdev, "Reset adapter\n");
6244 adapter->tx_timeout_count++;
6245
6246 ixgbe_reinit_locked(adapter);
6247}
6248
7086400d
AD		 6249/**
6250 * ixgbe_service_task - manages and runs subtasks
6251 * @work: pointer to work_struct containing our data
6252 **/
6253static void ixgbe_service_task(struct work_struct *work)
6254{
6255 struct ixgbe_adapter *adapter = container_of(work,
6256 struct ixgbe_adapter,
6257 service_task);
6258
c83c6cbd 6259 ixgbe_reset_subtask(adapter);
7086400d
AD		 6260 ixgbe_sfp_detection_subtask(adapter);
6261 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6262 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6263 ixgbe_watchdog_subtask(adapter);
d034acf1 6264 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6265 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6266
6267 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6268}
6269
897ab156
AD		 6270void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6271 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6272{
6273 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6274 u16 i = tx_ring->next_to_use;
9a799d71 6275
897ab156 6276 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
9a799d71 6277
897ab156
AD		 6278 i++;
6279 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6280
897ab156
AD		 6281 /* set bits to identify this as an advanced context descriptor */
6282 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6283
897ab156
AD		 6284 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6285 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6286 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6287 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6288}
9a799d71 6289
897ab156
AD		 6290static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6291 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6292{
6293 int err;
6294 u32 vlan_macip_lens, type_tucmd;
6295 u32 mss_l4len_idx, l4len;
9a799d71 6296
897ab156
AD		 6297 if (!skb_is_gso(skb))
6298 return 0;
9a799d71 6299
897ab156
AD		 6300 if (skb_header_cloned(skb)) {
6301 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6302 if (err)
6303 return err;
9a799d71 6304 }
9a799d71 6305
897ab156
AD		 6306 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6307 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6308
6309 if (protocol == __constant_htons(ETH_P_IP)) {
6310 struct iphdr *iph = ip_hdr(skb);
6311 iph->tot_len = 0;
6312 iph->check = 0;
6313 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6314 iph->daddr, 0,
6315 IPPROTO_TCP,
6316 0);
6317 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6318 } else if (skb_is_gso_v6(skb)) {
6319 ipv6_hdr(skb)->payload_len = 0;
6320 tcp_hdr(skb)->check =
6321 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6322 &ipv6_hdr(skb)->daddr,
6323 0, IPPROTO_TCP, 0);
6324 }
6325
6326 l4len = tcp_hdrlen(skb);
6327 *hdr_len = skb_transport_offset(skb) + l4len;
6328
6329 /* mss_l4len_id: use 1 as index for TSO */
6330 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6331 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6332 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6333
6334 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6335 vlan_macip_lens = skb_network_header_len(skb);
6336 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6337 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6338
6339 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6340 mss_l4len_idx);
6341
6342 return 1;
6343}
6344
6345static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6346 struct sk_buff *skb, u32 tx_flags,
6347 __be16 protocol)
7ca647bd 6348{
897ab156
AD		 6349 u32 vlan_macip_lens = 0;
6350 u32 mss_l4len_idx = 0;
6351 u32 type_tucmd = 0;
7ca647bd 6352
897ab156 6353 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6354 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6355 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6356 return false;
6357 } else {
6358 u8 l4_hdr = 0;
6359 switch (protocol) {
6360 case __constant_htons(ETH_P_IP):
6361 vlan_macip_lens |= skb_network_header_len(skb);
6362 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6363 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6364 break;
897ab156
AD		 6365 case __constant_htons(ETH_P_IPV6):
6366 vlan_macip_lens |= skb_network_header_len(skb);
6367 l4_hdr = ipv6_hdr(skb)->nexthdr;
6368 break;
6369 default:
6370 if (unlikely(net_ratelimit())) {
6371 dev_warn(tx_ring->dev,
6372 "partial checksum but proto=%x!\n",
6373 skb->protocol);
6374 }
7ca647bd
JP		 6375 break;
6376 }
897ab156
AD		 6377
6378 switch (l4_hdr) {
7ca647bd 6379 case IPPROTO_TCP:
897ab156
AD		 6380 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6381 mss_l4len_idx = tcp_hdrlen(skb) <<
6382 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6383 break;
6384 case IPPROTO_SCTP:
897ab156
AD		 6385 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6386 mss_l4len_idx = sizeof(struct sctphdr) <<
6387 IXGBE_ADVTXD_L4LEN_SHIFT;
6388 break;
6389 case IPPROTO_UDP:
6390 mss_l4len_idx = sizeof(struct udphdr) <<
6391 IXGBE_ADVTXD_L4LEN_SHIFT;
6392 break;
6393 default:
6394 if (unlikely(net_ratelimit())) {
6395 dev_warn(tx_ring->dev,
6396 "partial checksum but l4 proto=%x!\n",
6397 skb->protocol);
6398 }
7ca647bd
JP		 6399 break;
6400 }
7ca647bd
JP		 6401 }
6402
897ab156
AD		 6403 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6404 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6405
897ab156
AD		 6406 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6407 type_tucmd, mss_l4len_idx);
9a799d71 6408
897ab156 6409 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6410}
6411
d3d00239 6412static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6413{
d3d00239
AD		 6414 /* set type for advanced descriptor with frame checksum insertion */
6415 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6416 IXGBE_ADVTXD_DCMD_IFCS |
6417 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6418
d3d00239 6419 /* set HW vlan bit if vlan is present */
66f32a8b 6420 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6421 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6422
d3d00239
AD		 6423 /* set segmentation enable bits for TSO/FSO */
6424#ifdef IXGBE_FCOE
6425 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6426#else
6427 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6428#endif
6429 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6430
d3d00239
AD		 6431 return cmd_type;
6432}
9a799d71 6433
d3d00239
AD		 6434static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6435{
6436 __le32 olinfo_status =
6437 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6438
d3d00239
AD		 6439 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6440 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6441 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6442 /* enble IPv4 checksum for TSO */
6443 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6444 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6445 }
6446
d3d00239
AD		 6447 /* enable L4 checksum for TSO and TX checksum offload */
6448 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6449 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6450
d3d00239
AD		 6451#ifdef IXGBE_FCOE
6452 /* use index 1 context for FCOE/FSO */
6453 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6454 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6455 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6456
d3d00239 6457#endif
7f9643fd
AD		 6458 /*
6459 * Check Context must be set if Tx switch is enabled, which it
6460 * always is for case where virtual functions are running
6461 */
6462 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6463 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6464
d3d00239
AD		 6465 return olinfo_status;
6466}
44df32c5 6467
d3d00239
AD		 6468#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6469 IXGBE_TXD_CMD_RS)
6470
6471static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6472 struct sk_buff *skb,
6473 struct ixgbe_tx_buffer *first,
6474 u32 tx_flags,
6475 const u8 hdr_len)
6476{
6477 struct device *dev = tx_ring->dev;
6478 struct ixgbe_tx_buffer *tx_buffer_info;
6479 union ixgbe_adv_tx_desc *tx_desc;
6480 dma_addr_t dma;
6481 __le32 cmd_type, olinfo_status;
6482 struct skb_frag_struct *frag;
6483 unsigned int f = 0;
6484 unsigned int data_len = skb->data_len;
6485 unsigned int size = skb_headlen(skb);
6486 u32 offset = 0;
6487 u32 paylen = skb->len - hdr_len;
6488 u16 i = tx_ring->next_to_use;
6489 u16 gso_segs;
6490
6491#ifdef IXGBE_FCOE
6492 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6493 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6494 data_len -= sizeof(struct fcoe_crc_eof);
6495 } else {
6496 size -= sizeof(struct fcoe_crc_eof) - data_len;
6497 data_len = 0;
9a799d71
AK		 6498 }
6499 }
44df32c5 6500
d3d00239
AD		 6501#endif
6502 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6503 if (dma_mapping_error(dev, dma))
6504 goto dma_error;
8ad494b0 6505
d3d00239
AD		 6506 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6507 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6508
d3d00239 6509 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
e5a43549 6510
d3d00239
AD		 6511 for (;;) {
6512 while (size > IXGBE_MAX_DATA_PER_TXD) {
6513 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6514 tx_desc->read.cmd_type_len =
6515 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6516 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6517
d3d00239
AD		 6518 offset += IXGBE_MAX_DATA_PER_TXD;
6519 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6520
d3d00239
AD		 6521 tx_desc++;
6522 i++;
6523 if (i == tx_ring->count) {
6524 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6525 i = 0;
6526 }
6527 }
e5a43549 6528
e5a43549 6529 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6530 tx_buffer_info->length = offset + size;
6531 tx_buffer_info->tx_flags = tx_flags;
6532 tx_buffer_info->dma = dma;
9a799d71 6533
d3d00239
AD		 6534 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6535 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6536 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6537
d3d00239
AD		 6538 if (!data_len)
6539 break;
9a799d71 6540
d3d00239
AD		 6541 frag = &skb_shinfo(skb)->frags[f];
6542#ifdef IXGBE_FCOE
9e903e08 6543 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6544#else
9e903e08 6545 size = skb_frag_size(frag);
d3d00239
AD		 6546#endif
6547 data_len -= size;
6548 f++;
9a799d71 6549
d3d00239
AD		 6550 offset = 0;
6551 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6552
877749bf 6553 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6554 if (dma_mapping_error(dev, dma))
6555 goto dma_error;
9a799d71 6556
d3d00239
AD		 6557 tx_desc++;
6558 i++;
6559 if (i == tx_ring->count) {
6560 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, 0);
6561 i = 0;
6562 }
6563 }
9a799d71 6564
d3d00239 6565 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6566
d3d00239
AD		 6567 i++;
6568 if (i == tx_ring->count)
6569 i = 0;
9a799d71 6570
d3d00239 6571 tx_ring->next_to_use = i;
eacd73f7 6572
d3d00239
AD		 6573 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6574 gso_segs = skb_shinfo(skb)->gso_segs;
6575#ifdef IXGBE_FCOE
6576 /* adjust for FCoE Sequence Offload */
6577 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6578 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6579 skb_shinfo(skb)->gso_size);
6580#endif /* IXGBE_FCOE */
6581 else
6582 gso_segs = 1;
9a799d71 6583
d3d00239
AD		 6584 /* multiply data chunks by size of headers */
6585 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6586 tx_buffer_info->gso_segs = gso_segs;
6587 tx_buffer_info->skb = skb;
9a799d71 6588
d3d00239
AD		 6589 /* set the timestamp */
6590 first->time_stamp = jiffies;
9a799d71
AK		 6591
6592 /*
6593 * Force memory writes to complete before letting h/w
6594 * know there are new descriptors to fetch. (Only
6595 * applicable for weak-ordered memory model archs,
6596 * such as IA-64).
6597 */
6598 wmb();
6599
d3d00239
AD		 6600 /* set next_to_watch value indicating a packet is present */
6601 first->next_to_watch = tx_desc;
6602
6603 /* notify HW of packet */
84ea2591 6604 writel(i, tx_ring->tail);
d3d00239
AD		 6605
6606 return;
6607dma_error:
6608 dev_err(dev, "TX DMA map failed\n");
6609
6610 /* clear dma mappings for failed tx_buffer_info map */
6611 for (;;) {
6612 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6614 if (tx_buffer_info == first)
6615 break;
6616 if (i == 0)
6617 i = tx_ring->count;
6618 i--;
6619 }
6620
6621 dev_kfree_skb_any(skb);
6622
6623 tx_ring->next_to_use = i;
9a799d71
AK		 6624}
6625
69830529
AD		 6626static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6627 u32 tx_flags, __be16 protocol)
6628{
6629 struct ixgbe_q_vector *q_vector = ring->q_vector;
6630 union ixgbe_atr_hash_dword input = { .dword = 0 };
6631 union ixgbe_atr_hash_dword common = { .dword = 0 };
6632 union {
6633 unsigned char *network;
6634 struct iphdr *ipv4;
6635 struct ipv6hdr *ipv6;
6636 } hdr;
ee9e0f0b 6637 struct tcphdr *th;
905e4a41 6638 __be16 vlan_id;
c4cf55e5 6639
69830529
AD		 6640 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6641 if (!q_vector)
6642 return;
6643
6644 /* do nothing if sampling is disabled */
6645 if (!ring->atr_sample_rate)
d3ead241 6646 return;
c4cf55e5 6647
69830529 6648 ring->atr_count++;
c4cf55e5 6649
69830529
AD		 6650 /* snag network header to get L4 type and address */
6651 hdr.network = skb_network_header(skb);
6652
6653 /* Currently only IPv4/IPv6 with TCP is supported */
6654 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6655 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6656 (protocol != __constant_htons(ETH_P_IP) ||
6657 hdr.ipv4->protocol != IPPROTO_TCP))
6658 return;
ee9e0f0b
AD		 6659
6660 th = tcp_hdr(skb);
c4cf55e5 6661
66f32a8b
AD		 6662 /* skip this packet since it is invalid or the socket is closing */
6663 if (!th || th->fin)
69830529
AD		 6664 return;
6665
6666 /* sample on all syn packets or once every atr sample count */
6667 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6668 return;
6669
6670 /* reset sample count */
6671 ring->atr_count = 0;
6672
6673 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6674
6675 /*
6676 * src and dst are inverted, think how the receiver sees them
6677 *
6678 * The input is broken into two sections, a non-compressed section
6679 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6680 * is XORed together and stored in the compressed dword.
6681 */
6682 input.formatted.vlan_id = vlan_id;
6683
6684 /*
6685 * since src port and flex bytes occupy the same word XOR them together
6686 * and write the value to source port portion of compressed dword
6687 */
66f32a8b 6688 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6689 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6690 else
6691 common.port.src ^= th->dest ^ protocol;
6692 common.port.dst ^= th->source;
6693
6694 if (protocol == __constant_htons(ETH_P_IP)) {
6695 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6696 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6697 } else {
6698 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6699 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6700 hdr.ipv6->saddr.s6_addr32[1] ^
6701 hdr.ipv6->saddr.s6_addr32[2] ^
6702 hdr.ipv6->saddr.s6_addr32[3] ^
6703 hdr.ipv6->daddr.s6_addr32[0] ^
6704 hdr.ipv6->daddr.s6_addr32[1] ^
6705 hdr.ipv6->daddr.s6_addr32[2] ^
6706 hdr.ipv6->daddr.s6_addr32[3];
6707 }
c4cf55e5
PWJ		 6708
6709 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6710 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6711 input, common, ring->queue_index);
c4cf55e5
PWJ		 6712}
6713
63544e9c 6714static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6715{
fc77dc3c 6716 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6717 /* Herbert's original patch had:
6718 * smp_mb__after_netif_stop_queue();
6719 * but since that doesn't exist yet, just open code it. */
6720 smp_mb();
6721
6722 /* We need to check again in a case another CPU has just
6723 * made room available. */
7d4987de 6724 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6725 return -EBUSY;
6726
6727 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6728 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6729 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6730 return 0;
6731}
6732
82d4e46e 6733static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6734{
7d4987de 6735 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6736 return 0;
fc77dc3c 6737 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6738}
6739
09a3b1f8
SH		 6740static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6741{
6742 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6743 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6744 smp_processor_id();
56075a98 6745#ifdef IXGBE_FCOE
6440752c 6746 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6747
e5b64635
JF		 6748 if (((protocol == htons(ETH_P_FCOE)) ||
6749 (protocol == htons(ETH_P_FIP))) &&
6750 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6751 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6752 txq += adapter->ring_feature[RING_F_FCOE].mask;
6753 return txq;
56075a98
JF		 6754 }
6755#endif
6756
fdd3d631
KK		 6757 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6758 while (unlikely(txq >= dev->real_num_tx_queues))
6759 txq -= dev->real_num_tx_queues;
5f715823 6760 return txq;
fdd3d631 6761 }
c4cf55e5 6762
09a3b1f8
SH		 6763 return skb_tx_hash(dev, skb);
6764}
6765
fc77dc3c 6766netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6767 struct ixgbe_adapter *adapter,
6768 struct ixgbe_ring *tx_ring)
9a799d71 6769{
d3d00239 6770 struct ixgbe_tx_buffer *first;
5f715823 6771 int tso;
d3d00239 6772 u32 tx_flags = 0;
a535c30e
AD		 6773#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6774 unsigned short f;
6775#endif
a535c30e 6776 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6777 __be16 protocol = skb->protocol;
63544e9c 6778 u8 hdr_len = 0;
5e09a105 6779
a535c30e
AD		 6780 /*
6781 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6782 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6783 * + 2 desc gap to keep tail from touching head,
6784 * + 1 desc for context descriptor,
6785 * otherwise try next time
6786 */
6787#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6788 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6789 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6790#else
6791 count += skb_shinfo(skb)->nr_frags;
6792#endif
6793 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6794 tx_ring->tx_stats.tx_busy++;
6795 return NETDEV_TX_BUSY;
6796 }
6797
7f9643fd
AD		 6798#ifdef CONFIG_PCI_IOV
6799 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6800 tx_flags |= IXGBE_TX_FLAGS_TXSW;
6801
6802#endif
66f32a8b 6803 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6804 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6805 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6806 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6807 /* else if it is a SW VLAN check the next protocol and store the tag */
6808 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6809 struct vlan_hdr *vhdr, _vhdr;
6810 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6811 if (!vhdr)
6812 goto out_drop;
6813
6814 protocol = vhdr->h_vlan_encapsulated_proto;
6815 tx_flags |= ntohs(vhdr->h_vlan_TCI) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6816 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6817 }
6818
32701dc2 6819 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6820 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6821 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6822 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6823 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6824 tx_flags |= (skb->priority & 0x7) <<
6825 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6826 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6827 struct vlan_ethhdr *vhdr;
6828 if (skb_header_cloned(skb) &&
6829 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6830 goto out_drop;
6831 vhdr = (struct vlan_ethhdr *)skb->data;
6832 vhdr->h_vlan_TCI = htons(tx_flags >>
6833 IXGBE_TX_FLAGS_VLAN_SHIFT);
6834 } else {
6835 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6836 }
9a799d71 6837 }
eacd73f7 6838
a535c30e 6839 /* record the location of the first descriptor for this packet */
d3d00239 6840 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 6841
eacd73f7 6842#ifdef IXGBE_FCOE
66f32a8b
AD		 6843 /* setup tx offload for FCoE */
6844 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
6845 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 6846 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6847 if (tso < 0)
6848 goto out_drop;
6849 else if (tso)
66f32a8b
AD		 6850 tx_flags |= IXGBE_TX_FLAGS_FSO |
6851 IXGBE_TX_FLAGS_FCOE;
6852 else
6853 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 6854
66f32a8b 6855 goto xmit_fcoe;
eacd73f7 6856 }
9a799d71 6857
66f32a8b
AD		 6858#endif /* IXGBE_FCOE */
6859 /* setup IPv4/IPv6 offloads */
6860 if (protocol == __constant_htons(ETH_P_IP))
6861 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 6862
66f32a8b
AD		 6863 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6864 if (tso < 0)
897ab156 6865 goto out_drop;
66f32a8b
AD		 6866 else if (tso)
6867 tx_flags |= IXGBE_TX_FLAGS_TSO;
6868 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6869 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6870
6871 /* add the ATR filter if ATR is on */
6872 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6873 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6874
6875#ifdef IXGBE_FCOE
6876xmit_fcoe:
6877#endif /* IXGBE_FCOE */
d3d00239
AD		 6878 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
6879
6880 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6881
6882 return NETDEV_TX_OK;
897ab156
AD		 6883
6884out_drop:
6885 dev_kfree_skb_any(skb);
6886 return NETDEV_TX_OK;
9a799d71
AK		 6887}
6888
84418e3b
AD		 6889static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6890{
6891 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6892 struct ixgbe_ring *tx_ring;
6893
6894 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6895 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6896}
6897
9a799d71
AK		 6898/**
6899 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6900 * @netdev: network interface device structure
6901 * @p: pointer to an address structure
6902 *
6903 * Returns 0 on success, negative on failure
6904 **/
6905static int ixgbe_set_mac(struct net_device *netdev, void *p)
6906{
6907 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6908 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6909 struct sockaddr *addr = p;
6910
6911 if (!is_valid_ether_addr(addr->sa_data))
6912 return -EADDRNOTAVAIL;
6913
6914 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6915 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6916
1cdd1ec8
GR		 6917 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6918 IXGBE_RAH_AV);
9a799d71
AK		 6919
6920 return 0;
6921}
6922
6b73e10d
BH		 6923static int
6924ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6925{
6926 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6927 struct ixgbe_hw *hw = &adapter->hw;
6928 u16 value;
6929 int rc;
6930
6931 if (prtad != hw->phy.mdio.prtad)
6932 return -EINVAL;
6933 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6934 if (!rc)
6935 rc = value;
6936 return rc;
6937}
6938
6939static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6940 u16 addr, u16 value)
6941{
6942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6943 struct ixgbe_hw *hw = &adapter->hw;
6944
6945 if (prtad != hw->phy.mdio.prtad)
6946 return -EINVAL;
6947 return hw->phy.ops.write_reg(hw, addr, devad, value);
6948}
6949
6950static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6951{
6952 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6953
6954 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6955}
6956
0365e6e4
PW		 6957/**
6958 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6959 * netdev->dev_addrs
0365e6e4
PW		 6960 * @netdev: network interface device structure
6961 *
6962 * Returns non-zero on failure
6963 **/
6964static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6965{
6966 int err = 0;
6967 struct ixgbe_adapter *adapter = netdev_priv(dev);
6968 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6969
6970 if (is_valid_ether_addr(mac->san_addr)) {
6971 rtnl_lock();
6972 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6973 rtnl_unlock();
6974 }
6975 return err;
6976}
6977
6978/**
6979 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6980 * netdev->dev_addrs
0365e6e4
PW		 6981 * @netdev: network interface device structure
6982 *
6983 * Returns non-zero on failure
6984 **/
6985static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6986{
6987 int err = 0;
6988 struct ixgbe_adapter *adapter = netdev_priv(dev);
6989 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6990
6991 if (is_valid_ether_addr(mac->san_addr)) {
6992 rtnl_lock();
6993 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6994 rtnl_unlock();
6995 }
6996 return err;
6997}
6998
9a799d71
AK		 6999#ifdef CONFIG_NET_POLL_CONTROLLER
7000/*
7001 * Polling 'interrupt' - used by things like netconsole to send skbs
7002 * without having to re-enable interrupts. It's not called while
7003 * the interrupt routine is executing.
7004 */
7005static void ixgbe_netpoll(struct net_device *netdev)
7006{
7007 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7008 int i;
9a799d71 7009
1a647bd2
AD		 7010 /* if interface is down do nothing */
7011 if (test_bit(__IXGBE_DOWN, &adapter->state))
7012 return;
7013
9a799d71 7014 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7015 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7016 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7017 for (i = 0; i < num_q_vectors; i++) {
7018 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7019 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7020 }
7021 } else {
7022 ixgbe_intr(adapter->pdev->irq, netdev);
7023 }
9a799d71 7024 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7025}
7026#endif
7027
de1036b1
ED		 7028static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7029 struct rtnl_link_stats64 *stats)
7030{
7031 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7032 int i;
7033
1a51502b 7034 rcu_read_lock();
de1036b1 7035 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7036 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7037 u64 bytes, packets;
7038 unsigned int start;
7039
1a51502b
ED		 7040 if (ring) {
7041 do {
7042 start = u64_stats_fetch_begin_bh(&ring->syncp);
7043 packets = ring->stats.packets;
7044 bytes = ring->stats.bytes;
7045 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7046 stats->rx_packets += packets;
7047 stats->rx_bytes += bytes;
7048 }
de1036b1 7049 }
1ac9ad13
ED		 7050
7051 for (i = 0; i < adapter->num_tx_queues; i++) {
7052 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7053 u64 bytes, packets;
7054 unsigned int start;
7055
7056 if (ring) {
7057 do {
7058 start = u64_stats_fetch_begin_bh(&ring->syncp);
7059 packets = ring->stats.packets;
7060 bytes = ring->stats.bytes;
7061 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7062 stats->tx_packets += packets;
7063 stats->tx_bytes += bytes;
7064 }
7065 }
1a51502b 7066 rcu_read_unlock();
de1036b1
ED		 7067 /* following stats updated by ixgbe_watchdog_task() */
7068 stats->multicast = netdev->stats.multicast;
7069 stats->rx_errors = netdev->stats.rx_errors;
7070 stats->rx_length_errors = netdev->stats.rx_length_errors;
7071 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7072 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7073 return stats;
7074}
7075
8b1c0b24
JF		 7076/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7077 * #adapter: pointer to ixgbe_adapter
7078 * @tc: number of traffic classes currently enabled
7079 *
7080 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7081 * 802.1Q priority maps to a packet buffer that exists.
7082 */
7083static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7084{
7085 struct ixgbe_hw *hw = &adapter->hw;
7086 u32 reg, rsave;
7087 int i;
7088
7089 /* 82598 have a static priority to TC mapping that can not
7090 * be changed so no validation is needed.
7091 */
7092 if (hw->mac.type == ixgbe_mac_82598EB)
7093 return;
7094
7095 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7096 rsave = reg;
7097
7098 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7099 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7100
7101 /* If up2tc is out of bounds default to zero */
7102 if (up2tc > tc)
7103 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7104 }
7105
7106 if (reg != rsave)
7107 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7108
7109 return;
7110}
7111
7112
7113/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7114 * classes.
7115 *
7116 * @netdev: net device to configure
7117 * @tc: number of traffic classes to enable
7118 */
7119int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7120{
8b1c0b24
JF		 7121 struct ixgbe_adapter *adapter = netdev_priv(dev);
7122 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7123
e7589eab
JF		 7124 /* Multiple traffic classes requires multiple queues */
7125 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7126 e_err(drv, "Enable failed, needs MSI-X\n");
7127 return -EINVAL;
7128 }
8b1c0b24
JF		 7129
7130 /* Hardware supports up to 8 traffic classes */
4de2a022 7131 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7132 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7133 return -EINVAL;
7134
7135 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7136 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7137 * hardware is not flexible enough to do this dynamically.
7138 */
7139 if (netif_running(dev))
7140 ixgbe_close(dev);
7141 ixgbe_clear_interrupt_scheme(adapter);
7142
e7589eab 7143 if (tc) {
8b1c0b24 7144 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7145 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7146
7147 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7148 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7149
7150 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7151 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7152 } else {
8b1c0b24
JF		 7153 netdev_reset_tc(dev);
7154
e7589eab
JF		 7155 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7156
7157 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7158 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7159
7160 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7161 adapter->dcb_cfg.pfc_mode_enable = false;
7162 }
7163
8b1c0b24
JF		 7164 ixgbe_init_interrupt_scheme(adapter);
7165 ixgbe_validate_rtr(adapter, tc);
7166 if (netif_running(dev))
7167 ixgbe_open(dev);
7168
7169 return 0;
7170}
de1036b1 7171
082757af
DS		 7172void ixgbe_do_reset(struct net_device *netdev)
7173{
7174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7175
7176 if (netif_running(netdev))
7177 ixgbe_reinit_locked(adapter);
7178 else
7179 ixgbe_reset(adapter);
7180}
7181
c8f44aff
MM		 7182static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7183 netdev_features_t data)
082757af
DS		 7184{
7185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7186
7187#ifdef CONFIG_DCB
7188 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7189 data &= ~NETIF_F_HW_VLAN_RX;
7190#endif
7191
7192 /* return error if RXHASH is being enabled when RSS is not supported */
7193 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7194 data &= ~NETIF_F_RXHASH;
7195
7196 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7197 if (!(data & NETIF_F_RXCSUM))
7198 data &= ~NETIF_F_LRO;
7199
7200 /* Turn off LRO if not RSC capable or invalid ITR settings */
7201 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7202 data &= ~NETIF_F_LRO;
7203 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7204 (adapter->rx_itr_setting != 1 &&
7205 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7206 data &= ~NETIF_F_LRO;
7207 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7208 }
7209
7210 return data;
7211}
7212
c8f44aff
MM		 7213static int ixgbe_set_features(struct net_device *netdev,
7214 netdev_features_t data)
082757af
DS		 7215{
7216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7217 bool need_reset = false;
7218
7219 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7220 if (!(data & NETIF_F_RXCSUM))
7221 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
7222 else
7223 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
7224
7225 /* Make sure RSC matches LRO, reset if change */
7226 if (!!(data & NETIF_F_LRO) !=
7227 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7228 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7229 switch (adapter->hw.mac.type) {
7230 case ixgbe_mac_X540:
7231 case ixgbe_mac_82599EB:
7232 need_reset = true;
7233 break;
7234 default:
7235 break;
7236 }
7237 }
7238
7239 /*
7240 * Check if Flow Director n-tuple support was enabled or disabled. If
7241 * the state changed, we need to reset.
7242 */
7243 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7244 /* turn off ATR, enable perfect filters and reset */
7245 if (data & NETIF_F_NTUPLE) {
7246 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7247 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7248 need_reset = true;
7249 }
7250 } else if (!(data & NETIF_F_NTUPLE)) {
7251 /* turn off Flow Director, set ATR and reset */
7252 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7253 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7254 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7255 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7256 need_reset = true;
7257 }
7258
7259 if (need_reset)
7260 ixgbe_do_reset(netdev);
7261
7262 return 0;
7263
7264}
7265
0edc3527 7266static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7267 .ndo_open = ixgbe_open,
0edc3527 7268 .ndo_stop = ixgbe_close,
00829823 7269 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7270 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7271 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7272 .ndo_validate_addr = eth_validate_addr,
7273 .ndo_set_mac_address = ixgbe_set_mac,
7274 .ndo_change_mtu = ixgbe_change_mtu,
7275 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7276 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7277 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7278 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7279 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7280 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7281 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7282 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7283 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7284 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7285 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7286#ifdef CONFIG_NET_POLL_CONTROLLER
7287 .ndo_poll_controller = ixgbe_netpoll,
7288#endif
332d4a7d
YZ		 7289#ifdef IXGBE_FCOE
7290 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7291 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7292 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7293 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7294 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7295 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
332d4a7d 7296#endif /* IXGBE_FCOE */
082757af
DS		 7297 .ndo_set_features = ixgbe_set_features,
7298 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7299};
7300
1cdd1ec8
GR		 7301static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7302 const struct ixgbe_info *ii)
7303{
7304#ifdef CONFIG_PCI_IOV
7305 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7306
c6bda30a 7307 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7308 return;
7309
7310 /* The 82599 supports up to 64 VFs per physical function
7311 * but this implementation limits allocation to 63 so that
7312 * basic networking resources are still available to the
7313 * physical function
7314 */
7315 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7316 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7317#endif /* CONFIG_PCI_IOV */
7318}
7319
9a799d71
AK		 7320/**
7321 * ixgbe_probe - Device Initialization Routine
7322 * @pdev: PCI device information struct
7323 * @ent: entry in ixgbe_pci_tbl
7324 *
7325 * Returns 0 on success, negative on failure
7326 *
7327 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7328 * The OS initialization, configuring of the adapter private structure,
7329 * and a hardware reset occur.
7330 **/
7331static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7332 const struct pci_device_id *ent)
9a799d71
AK		 7333{
7334 struct net_device *netdev;
7335 struct ixgbe_adapter *adapter = NULL;
7336 struct ixgbe_hw *hw;
7337 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7338 static int cards_found;
7339 int i, err, pci_using_dac;
289700db 7340 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7341 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7342#ifdef IXGBE_FCOE
7343 u16 device_caps;
7344#endif
289700db 7345 u32 eec;
c23f5b6b 7346 u16 wol_cap;
9a799d71 7347
bded64a7
AG		 7348 /* Catch broken hardware that put the wrong VF device ID in
7349 * the PCIe SR-IOV capability.
7350 */
7351 if (pdev->is_virtfn) {
7352 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7353 pci_name(pdev), pdev->vendor, pdev->device);
7354 return -EINVAL;
7355 }
7356
9ce77666 7357 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7358 if (err)
7359 return err;
7360
1b507730
NN		 7361 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7362 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7363 pci_using_dac = 1;
7364 } else {
1b507730 7365 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7366 if (err) {
1b507730
NN		 7367 err = dma_set_coherent_mask(&pdev->dev,
7368 DMA_BIT_MASK(32));
9a799d71 7369 if (err) {
b8bc0421
DC		 7370 dev_err(&pdev->dev,
7371 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7372 goto err_dma;
7373 }
7374 }
7375 pci_using_dac = 0;
7376 }
7377
9ce77666 7378 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7379 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7380 if (err) {
b8bc0421
DC		 7381 dev_err(&pdev->dev,
7382 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7383 goto err_pci_reg;
7384 }
7385
19d5afd4 7386 pci_enable_pcie_error_reporting(pdev);
6fabd715 7387
9a799d71 7388 pci_set_master(pdev);
fb3b27bc 7389 pci_save_state(pdev);
9a799d71 7390
e901acd6
JF		 7391#ifdef CONFIG_IXGBE_DCB
7392 indices *= MAX_TRAFFIC_CLASS;
7393#endif
7394
c85a2618
JF		 7395 if (ii->mac == ixgbe_mac_82598EB)
7396 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7397 else
7398 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7399
e901acd6 7400#ifdef IXGBE_FCOE
c85a2618
JF		 7401 indices += min_t(unsigned int, num_possible_cpus(),
7402 IXGBE_MAX_FCOE_INDICES);
7403#endif
c85a2618 7404 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7405 if (!netdev) {
7406 err = -ENOMEM;
7407 goto err_alloc_etherdev;
7408 }
7409
9a799d71
AK		 7410 SET_NETDEV_DEV(netdev, &pdev->dev);
7411
9a799d71 7412 adapter = netdev_priv(netdev);
c60fbb00 7413 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7414
7415 adapter->netdev = netdev;
7416 adapter->pdev = pdev;
7417 hw = &adapter->hw;
7418 hw->back = adapter;
7419 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7420
05857980 7421 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7422 pci_resource_len(pdev, 0));
9a799d71
AK		 7423 if (!hw->hw_addr) {
7424 err = -EIO;
7425 goto err_ioremap;
7426 }
7427
7428 for (i = 1; i <= 5; i++) {
7429 if (pci_resource_len(pdev, i) == 0)
7430 continue;
7431 }
7432
0edc3527 7433 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7434 ixgbe_set_ethtool_ops(netdev);
9a799d71 7435 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7436 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7437
9a799d71
AK		 7438 adapter->bd_number = cards_found;
7439
9a799d71
AK		 7440 /* Setup hw api */
7441 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7442 hw->mac.type = ii->mac;
9a799d71 7443
c44ade9e
JB		 7444 /* EEPROM */
7445 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7446 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7447 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7448 if (!(eec & (1 << 8)))
7449 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7450
7451 /* PHY */
7452 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7453 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7454 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7455 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7456 hw->phy.mdio.mmds = 0;
7457 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7458 hw->phy.mdio.dev = netdev;
7459 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7460 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7461
8ca783ab 7462 ii->get_invariants(hw);
9a799d71
AK		 7463
7464 /* setup the private structure */
7465 err = ixgbe_sw_init(adapter);
7466 if (err)
7467 goto err_sw_init;
7468
e86bff0e 7469 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7470 switch (adapter->hw.mac.type) {
7471 case ixgbe_mac_82599EB:
7472 case ixgbe_mac_X540:
e86bff0e 7473 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7474 break;
7475 default:
7476 break;
7477 }
e86bff0e 7478
bf069c97
DS		 7479 /*
7480 * If there is a fan on this device and it has failed log the
7481 * failure.
7482 */
7483 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7484 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7485 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7486 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7487 }
7488
c44ade9e 7489 /* reset_hw fills in the perm_addr as well */
119fc60a 7490 hw->phy.reset_if_overtemp = true;
c44ade9e 7491 err = hw->mac.ops.reset_hw(hw);
119fc60a 7492 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7493 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7494 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7495 err = 0;
7496 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7497 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7498 "module type was detected.\n");
7499 e_dev_err("Reload the driver after installing a supported "
7500 "module.\n");
04f165ef
PW		 7501 goto err_sw_init;
7502 } else if (err) {
849c4542 7503 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7504 goto err_sw_init;
7505 }
7506
1cdd1ec8
GR		 7507 ixgbe_probe_vf(adapter, ii);
7508
396e799c 7509 netdev->features = NETIF_F_SG |
e8e9f696 7510 NETIF_F_IP_CSUM |
082757af 7511 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7512 NETIF_F_HW_VLAN_TX |
7513 NETIF_F_HW_VLAN_RX |
082757af
DS		 7514 NETIF_F_HW_VLAN_FILTER |
7515 NETIF_F_TSO |
7516 NETIF_F_TSO6 |
082757af
DS		 7517 NETIF_F_RXHASH |
7518 NETIF_F_RXCSUM;
9a799d71 7519
082757af 7520 netdev->hw_features = netdev->features;
ad31c402 7521
58be7666
DS		 7522 switch (adapter->hw.mac.type) {
7523 case ixgbe_mac_82599EB:
7524 case ixgbe_mac_X540:
45a5ead0 7525 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7526 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7527 NETIF_F_NTUPLE;
58be7666
DS		 7528 break;
7529 default:
7530 break;
7531 }
45a5ead0 7532
ad31c402
JK		 7533 netdev->vlan_features |= NETIF_F_TSO;
7534 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7535 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7536 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7537 netdev->vlan_features |= NETIF_F_SG;
7538
01789349
JP		 7539 netdev->priv_flags |= IFF_UNICAST_FLT;
7540
1cdd1ec8
GR		 7541 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7542 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7543 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7544
7a6b6f51 7545#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7546 netdev->dcbnl_ops = &dcbnl_ops;
7547#endif
7548
eacd73f7 7549#ifdef IXGBE_FCOE
0d551589 7550 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7551 if (hw->mac.ops.get_device_caps) {
7552 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7553 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7554 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7555 }
7556 }
5e09d7f6
YZ		 7557 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7558 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7559 netdev->vlan_features |= NETIF_F_FSO;
7560 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7561 }
eacd73f7 7562#endif /* IXGBE_FCOE */
7b872a55 7563 if (pci_using_dac) {
9a799d71 7564 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7565 netdev->vlan_features |= NETIF_F_HIGHDMA;
7566 }
9a799d71 7567
082757af
DS		 7568 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7569 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7570 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7571 netdev->features |= NETIF_F_LRO;
7572
9a799d71 7573 /* make sure the EEPROM is good */
c44ade9e 7574 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7575 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7576 err = -EIO;
7577 goto err_eeprom;
7578 }
7579
7580 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7581 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7582
c44ade9e 7583 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7584 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7585 err = -EIO;
7586 goto err_eeprom;
7587 }
7588
7086400d
AD		 7589 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7590 (unsigned long) adapter);
9a799d71 7591
7086400d
AD		 7592 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7593 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7594
021230d4
AV		 7595 err = ixgbe_init_interrupt_scheme(adapter);
7596 if (err)
7597 goto err_sw_init;
9a799d71 7598
082757af
DS		 7599 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7600 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7601 netdev->features &= ~NETIF_F_RXHASH;
082757af 7602 }
67a74ee2 7603
c23f5b6b
ET		 7604 /* WOL not supported for all but the following */
7605 adapter->wol = 0;
e8e26350 7606 switch (pdev->device) {
0b077fea
DS		 7607 case IXGBE_DEV_ID_82599_SFP:
7608 /* Only this subdevice supports WOL */
7609 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
9417c464 7610 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7611 break;
50d6c681
AD		 7612 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7613 /* All except this subdevice support WOL */
0b077fea 7614 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7615 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7616 break;
e8e26350 7617 case IXGBE_DEV_ID_82599_KX4:
9417c464 7618 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7619 break;
c23f5b6b
ET		 7620 case IXGBE_DEV_ID_X540T:
7621 /* Check eeprom to see if it is enabled */
7622 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7623 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7624
7625 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7626 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7627 (hw->bus.func == 0)))
7628 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7629 break;
7630 }
e8e26350
PW		 7631 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7632
15e5209f
ET		 7633 /* save off EEPROM version number */
7634 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7635 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7636
04f165ef
PW		 7637 /* pick up the PCI bus settings for reporting later */
7638 hw->mac.ops.get_bus_info(hw);
7639
9a799d71 7640 /* print bus type/speed/width info */
849c4542 7641 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7642 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7643 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7644 "Unknown"),
7645 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7646 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7647 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7648 "Unknown"),
7649 netdev->dev_addr);
289700db
DS		 7650
7651 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7652 if (err)
9fe93afd 7653 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7654 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7655 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7656 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7657 part_str);
e8e26350 7658 else
289700db
DS		 7659 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7660 hw->mac.type, hw->phy.type, part_str);
9a799d71 7661
e8e26350 7662 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7663 e_dev_warn("PCI-Express bandwidth available for this card is "
7664 "not sufficient for optimal performance.\n");
7665 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7666 "is required.\n");
0c254d86
AK		 7667 }
7668
9a799d71 7669 /* reset the hardware with the new settings */
794caeb2 7670 err = hw->mac.ops.start_hw(hw);
c44ade9e 7671
794caeb2
PWJ		 7672 if (err == IXGBE_ERR_EEPROM_VERSION) {
7673 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7674 e_dev_warn("This device is a pre-production adapter/LOM. "
7675 "Please be aware there may be issues associated "
7676 "with your hardware. If you are experiencing "
7677 "problems please contact your Intel or hardware "
7678 "representative who provided you with this "
7679 "hardware.\n");
794caeb2 7680 }
9a799d71
AK		 7681 strcpy(netdev->name, "eth%d");
7682 err = register_netdev(netdev);
7683 if (err)
7684 goto err_register;
7685
93d3ce8f
ET		 7686 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7687 if (hw->mac.ops.disable_tx_laser &&
7688 ((hw->phy.multispeed_fiber) ||
7689 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7690 (hw->mac.type == ixgbe_mac_82599EB))))
7691 hw->mac.ops.disable_tx_laser(hw);
7692
54386467
JB		 7693 /* carrier off reporting is important to ethtool even BEFORE open */
7694 netif_carrier_off(netdev);
7695
5dd2d332 7696#ifdef CONFIG_IXGBE_DCA
652f093f 7697 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7698 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7699 ixgbe_setup_dca(adapter);
7700 }
7701#endif
1cdd1ec8 7702 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7703 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7704 for (i = 0; i < adapter->num_vfs; i++)
7705 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7706 }
7707
2466dd9c
JK		 7708 /* firmware requires driver version to be 0xFFFFFFFF
7709 * since os does not support feature
7710 */
9612de92 7711 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7712 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7713 0xFF);
9612de92 7714
0365e6e4
PW		 7715 /* add san mac addr to netdev */
7716 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7717
849c4542 7718 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
9a799d71
AK		 7719 cards_found++;
7720 return 0;
7721
7722err_register:
5eba3699 7723 ixgbe_release_hw_control(adapter);
7a921c93 7724 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7725err_sw_init:
7726err_eeprom:
1cdd1ec8
GR		 7727 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7728 ixgbe_disable_sriov(adapter);
7086400d 7729 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7730 iounmap(hw->hw_addr);
7731err_ioremap:
7732 free_netdev(netdev);
7733err_alloc_etherdev:
e8e9f696
JP		 7734 pci_release_selected_regions(pdev,
7735 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7736err_pci_reg:
7737err_dma:
7738 pci_disable_device(pdev);
7739 return err;
7740}
7741
7742/**
7743 * ixgbe_remove - Device Removal Routine
7744 * @pdev: PCI device information struct
7745 *
7746 * ixgbe_remove is called by the PCI subsystem to alert the driver
7747 * that it should release a PCI device. The could be caused by a
7748 * Hot-Plug event, or because the driver is going to be removed from
7749 * memory.
7750 **/
7751static void __devexit ixgbe_remove(struct pci_dev *pdev)
7752{
c60fbb00
AD		 7753 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7754 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7755
7756 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7757 cancel_work_sync(&adapter->service_task);
9a799d71 7758
5dd2d332 7759#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7760 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7761 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7762 dca_remove_requester(&pdev->dev);
7763 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7764 }
7765
7766#endif
332d4a7d
YZ		 7767#ifdef IXGBE_FCOE
7768 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7769 ixgbe_cleanup_fcoe(adapter);
7770
7771#endif /* IXGBE_FCOE */
0365e6e4
PW		 7772
7773 /* remove the added san mac */
7774 ixgbe_del_sanmac_netdev(netdev);
7775
c4900be0
DS		 7776 if (netdev->reg_state == NETREG_REGISTERED)
7777 unregister_netdev(netdev);
9a799d71 7778
c6bda30a
GR		 7779 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7780 if (!(ixgbe_check_vf_assignment(adapter)))
7781 ixgbe_disable_sriov(adapter);
7782 else
7783 e_dev_warn("Unloading driver while VFs are assigned "
7784 "- VFs will not be deallocated\n");
7785 }
1cdd1ec8 7786
7a921c93 7787 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7788
021230d4 7789 ixgbe_release_hw_control(adapter);
9a799d71
AK		 7790
7791 iounmap(adapter->hw.hw_addr);
9ce77666 7792 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7793 IORESOURCE_MEM));
9a799d71 7794
849c4542 7795 e_dev_info("complete\n");
021230d4 7796
9a799d71
AK		 7797 free_netdev(netdev);
7798
19d5afd4 7799 pci_disable_pcie_error_reporting(pdev);
6fabd715 7800
9a799d71
AK		 7801 pci_disable_device(pdev);
7802}
7803
7804/**
7805 * ixgbe_io_error_detected - called when PCI error is detected
7806 * @pdev: Pointer to PCI device
7807 * @state: The current pci connection state
7808 *
7809 * This function is called after a PCI bus error affecting
7810 * this device has been detected.
7811 */
7812static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7813 pci_channel_state_t state)
9a799d71 7814{
c60fbb00
AD		 7815 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7816 struct net_device *netdev = adapter->netdev;
9a799d71 7817
83c61fa9
GR		 7818#ifdef CONFIG_PCI_IOV
7819 struct pci_dev *bdev, *vfdev;
7820 u32 dw0, dw1, dw2, dw3;
7821 int vf, pos;
7822 u16 req_id, pf_func;
7823
7824 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7825 adapter->num_vfs == 0)
7826 goto skip_bad_vf_detection;
7827
7828 bdev = pdev->bus->self;
7829 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
7830 bdev = bdev->bus->self;
7831
7832 if (!bdev)
7833 goto skip_bad_vf_detection;
7834
7835 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7836 if (!pos)
7837 goto skip_bad_vf_detection;
7838
7839 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7840 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7841 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7842 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7843
7844 req_id = dw1 >> 16;
7845 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7846 if (!(req_id & 0x0080))
7847 goto skip_bad_vf_detection;
7848
7849 pf_func = req_id & 0x01;
7850 if ((pf_func & 1) == (pdev->devfn & 1)) {
7851 unsigned int device_id;
7852
7853 vf = (req_id & 0x7F) >> 1;
7854 e_dev_err("VF %d has caused a PCIe error\n", vf);
7855 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7856 "%8.8x\tdw3: %8.8x\n",
7857 dw0, dw1, dw2, dw3);
7858 switch (adapter->hw.mac.type) {
7859 case ixgbe_mac_82599EB:
7860 device_id = IXGBE_82599_VF_DEVICE_ID;
7861 break;
7862 case ixgbe_mac_X540:
7863 device_id = IXGBE_X540_VF_DEVICE_ID;
7864 break;
7865 default:
7866 device_id = 0;
7867 break;
7868 }
7869
7870 /* Find the pci device of the offending VF */
7871 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
7872 while (vfdev) {
7873 if (vfdev->devfn == (req_id & 0xFF))
7874 break;
7875 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
7876 device_id, vfdev);
7877 }
7878 /*
7879 * There's a slim chance the VF could have been hot plugged,
7880 * so if it is no longer present we don't need to issue the
7881 * VFLR. Just clean up the AER in that case.
7882 */
7883 if (vfdev) {
7884 e_dev_err("Issuing VFLR to VF %d\n", vf);
7885 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
7886 }
7887
7888 pci_cleanup_aer_uncorrect_error_status(pdev);
7889 }
7890
7891 /*
7892 * Even though the error may have occurred on the other port
7893 * we still need to increment the vf error reference count for
7894 * both ports because the I/O resume function will be called
7895 * for both of them.
7896 */
7897 adapter->vferr_refcount++;
7898
7899 return PCI_ERS_RESULT_RECOVERED;
7900
7901skip_bad_vf_detection:
7902#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 7903 netif_device_detach(netdev);
7904
3044b8d1
BL		 7905 if (state == pci_channel_io_perm_failure)
7906 return PCI_ERS_RESULT_DISCONNECT;
7907
9a799d71
AK		 7908 if (netif_running(netdev))
7909 ixgbe_down(adapter);
7910 pci_disable_device(pdev);
7911
b4617240 7912 /* Request a slot reset. */
9a799d71
AK		 7913 return PCI_ERS_RESULT_NEED_RESET;
7914}
7915
7916/**
7917 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7918 * @pdev: Pointer to PCI device
7919 *
7920 * Restart the card from scratch, as if from a cold-boot.
7921 */
7922static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7923{
c60fbb00 7924 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 7925 pci_ers_result_t result;
7926 int err;
9a799d71 7927
9ce77666 7928 if (pci_enable_device_mem(pdev)) {
396e799c 7929 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 7930 result = PCI_ERS_RESULT_DISCONNECT;
7931 } else {
7932 pci_set_master(pdev);
7933 pci_restore_state(pdev);
c0e1f68b 7934 pci_save_state(pdev);
9a799d71 7935
dd4d8ca6 7936 pci_wake_from_d3(pdev, false);
9a799d71 7937
6fabd715 7938 ixgbe_reset(adapter);
88512539 7939 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 7940 result = PCI_ERS_RESULT_RECOVERED;
7941 }
7942
7943 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7944 if (err) {
849c4542
ET		 7945 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7946 "failed 0x%0x\n", err);
6fabd715
PWJ		 7947 /* non-fatal, continue */
7948 }
9a799d71 7949
6fabd715 7950 return result;
9a799d71
AK		 7951}
7952
7953/**
7954 * ixgbe_io_resume - called when traffic can start flowing again.
7955 * @pdev: Pointer to PCI device
7956 *
7957 * This callback is called when the error recovery driver tells us that
7958 * its OK to resume normal operation.
7959 */
7960static void ixgbe_io_resume(struct pci_dev *pdev)
7961{
c60fbb00
AD		 7962 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7963 struct net_device *netdev = adapter->netdev;
9a799d71 7964
83c61fa9
GR		 7965#ifdef CONFIG_PCI_IOV
7966 if (adapter->vferr_refcount) {
7967 e_info(drv, "Resuming after VF err\n");
7968 adapter->vferr_refcount--;
7969 return;
7970 }
7971
7972#endif
c7ccde0f
AD		 7973 if (netif_running(netdev))
7974 ixgbe_up(adapter);
9a799d71
AK		 7975
7976 netif_device_attach(netdev);
9a799d71
AK		 7977}
7978
7979static struct pci_error_handlers ixgbe_err_handler = {
7980 .error_detected = ixgbe_io_error_detected,
7981 .slot_reset = ixgbe_io_slot_reset,
7982 .resume = ixgbe_io_resume,
7983};
7984
7985static struct pci_driver ixgbe_driver = {
7986 .name = ixgbe_driver_name,
7987 .id_table = ixgbe_pci_tbl,
7988 .probe = ixgbe_probe,
7989 .remove = __devexit_p(ixgbe_remove),
7990#ifdef CONFIG_PM
7991 .suspend = ixgbe_suspend,
7992 .resume = ixgbe_resume,
7993#endif
7994 .shutdown = ixgbe_shutdown,
7995 .err_handler = &ixgbe_err_handler
7996};
7997
7998/**
7999 * ixgbe_init_module - Driver Registration Routine
8000 *
8001 * ixgbe_init_module is the first routine called when the driver is
8002 * loaded. All it does is register with the PCI subsystem.
8003 **/
8004static int __init ixgbe_init_module(void)
8005{
8006 int ret;
c7689578 8007 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8008 pr_info("%s\n", ixgbe_copyright);
9a799d71 8009
5dd2d332 8010#ifdef CONFIG_IXGBE_DCA
bd0362dd 8011 dca_register_notify(&dca_notifier);
bd0362dd 8012#endif
5dd2d332 8013
9a799d71
AK		 8014 ret = pci_register_driver(&ixgbe_driver);
8015 return ret;
8016}
b4617240 8017
9a799d71
AK		 8018module_init(ixgbe_init_module);
8019
8020/**
8021 * ixgbe_exit_module - Driver Exit Cleanup Routine
8022 *
8023 * ixgbe_exit_module is called just before the driver is removed
8024 * from memory.
8025 **/
8026static void __exit ixgbe_exit_module(void)
8027{
5dd2d332 8028#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8029 dca_unregister_notify(&dca_notifier);
8030#endif
9a799d71 8031 pci_unregister_driver(&ixgbe_driver);
1a51502b 8032 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8033}
bd0362dd 8034
5dd2d332 8035#ifdef CONFIG_IXGBE_DCA
bd0362dd 8036static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8037 void *p)
bd0362dd
JC		 8038{
8039 int ret_val;
8040
8041 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8042 __ixgbe_notify_dca);
bd0362dd
JC		 8043
8044 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8045}
b453368d 8046
5dd2d332 8047#endif /* CONFIG_IXGBE_DCA */
849c4542 8048
9a799d71
AK		 8049module_exit(ixgbe_exit_module);
8050
8051/* ixgbe_main.c */
Linux kernel - Deliverables
This page took 2.572162 seconds and 5 git commands to generate.