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ixgbe: Store VXLAN port number in network order
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
b82b17d9
JF		 54#include <net/pkt_cls.h>
55#include <net/tc_act/tc_gact.h>
9a799d71 56
c762dff2
MP		 57#ifdef CONFIG_OF
58#include <linux/of_net.h>
59#endif
60
61#ifdef CONFIG_SPARC
62#include <asm/idprom.h>
63#include <asm/prom.h>
64#endif
65
9a799d71
AK		 66#include "ixgbe.h"
67#include "ixgbe_common.h"
ee5f784a 68#include "ixgbe_dcb_82599.h"
1cdd1ec8 69#include "ixgbe_sriov.h"
b82b17d9 70#include "ixgbe_model.h"
9a799d71
AK		 71
72char ixgbe_driver_name[] = "ixgbe";
9c8eb720 73static const char ixgbe_driver_string[] =
e8e9f696 74 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 75#ifdef IXGBE_FCOE
ea81875a
NP		 76char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 78#else
79static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection";
81#endif
21dd5601 82#define DRV_VERSION "4.2.1-k"
9c8eb720 83const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 84static const char ixgbe_copyright[] =
67359c3c 85 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 86
f44e751b
DS		 87static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
88
9a799d71 89static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 90 [board_82598] = &ixgbe_82598_info,
91 [board_82599] = &ixgbe_82599_info,
92 [board_X540] = &ixgbe_X540_info,
93 [board_X550] = &ixgbe_X550_info,
94 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 95};
96
97/* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
9baa3c34 105static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
018d7146 140 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
9a799d71
AK		 141 /* required last entry */
142 {0, }
143};
144MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
145
5dd2d332 146#ifdef CONFIG_IXGBE_DCA
bd0362dd 147static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 148 void *p);
bd0362dd
JC		 149static struct notifier_block dca_notifier = {
150 .notifier_call = ixgbe_notify_dca,
151 .next = NULL,
152 .priority = 0
153};
154#endif
155
1cdd1ec8
GR		 156#ifdef CONFIG_PCI_IOV
157static unsigned int max_vfs;
158module_param(max_vfs, uint, 0);
e8e9f696 159MODULE_PARM_DESC(max_vfs,
170e8543 160 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 161#endif /* CONFIG_PCI_IOV */
162
8ef78adc
PWJ		 163static unsigned int allow_unsupported_sfp;
164module_param(allow_unsupported_sfp, uint, 0);
165MODULE_PARM_DESC(allow_unsupported_sfp,
166 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
167
b3f4d599 168#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
169static int debug = -1;
170module_param(debug, int, 0);
171MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
172
9a799d71
AK		 173MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
174MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
175MODULE_LICENSE("GPL");
176MODULE_VERSION(DRV_VERSION);
177
780484d8
MR		 178static struct workqueue_struct *ixgbe_wq;
179
14438464
MR		 180static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
181
b8e82001
JK		 182static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
183 u32 reg, u16 *value)
184{
b8e82001
JK		 185 struct pci_dev *parent_dev;
186 struct pci_bus *parent_bus;
187
188 parent_bus = adapter->pdev->bus->parent;
189 if (!parent_bus)
190 return -1;
191
192 parent_dev = parent_bus->self;
193 if (!parent_dev)
194 return -1;
195
c0798edf 196 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 197 return -1;
198
c0798edf 199 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 200 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
201 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
202 return -1;
b8e82001
JK		 203 return 0;
204}
205
206static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
207{
208 struct ixgbe_hw *hw = &adapter->hw;
209 u16 link_status = 0;
210 int err;
211
212 hw->bus.type = ixgbe_bus_type_pci_express;
213
214 /* Get the negotiated link width and speed from PCI config space of the
215 * parent, as this device is behind a switch
216 */
217 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
218
219 /* assume caller will handle error case */
220 if (err)
221 return err;
222
223 hw->bus.width = ixgbe_convert_bus_width(link_status);
224 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
225
226 return 0;
227}
228
e027d1ae
JK		 229/**
230 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
231 * @hw: hw specific details
232 *
233 * This function is used by probe to determine whether a device's PCI-Express
234 * bandwidth details should be gathered from the parent bus instead of from the
235 * device. Used to ensure that various locations all have the correct device ID
236 * checks.
237 */
238static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
239{
240 switch (hw->device_id) {
241 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 242 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 243 return true;
244 default:
245 return false;
246 }
247}
248
249static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
250 int expected_gts)
251{
f9328bc6 252 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 253 int max_gts = 0;
254 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
255 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
256 struct pci_dev *pdev;
257
f9328bc6
DS		 258 /* Some devices are not connected over PCIe and thus do not negotiate
259 * speed. These devices do not have valid bus info, and thus any report
260 * we generate may not be correct.
261 */
262 if (hw->bus.type == ixgbe_bus_type_internal)
263 return;
264
56d1392f 265 /* determine whether to use the parent device */
e027d1ae
JK		 266 if (ixgbe_pcie_from_parent(&adapter->hw))
267 pdev = adapter->pdev->bus->parent->self;
268 else
269 pdev = adapter->pdev;
270
271 if (pcie_get_minimum_link(pdev, &speed, &width) ||
272 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
273 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
274 return;
275 }
276
277 switch (speed) {
278 case PCIE_SPEED_2_5GT:
279 /* 8b/10b encoding reduces max throughput by 20% */
280 max_gts = 2 * width;
281 break;
282 case PCIE_SPEED_5_0GT:
283 /* 8b/10b encoding reduces max throughput by 20% */
284 max_gts = 4 * width;
285 break;
286 case PCIE_SPEED_8_0GT:
9f0a433c 287 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 288 max_gts = 8 * width;
289 break;
290 default:
291 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
292 return;
293 }
294
295 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
296 max_gts);
297 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
298 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
299 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
300 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
301 "Unknown"),
302 width,
303 (speed == PCIE_SPEED_2_5GT ? "20%" :
304 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 305 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 306 "Unknown"));
307
308 if (max_gts < expected_gts) {
309 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
310 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
311 expected_gts);
312 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
313 }
314}
315
7086400d
AD		 316static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
317{
318 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 319 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d 320 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
780484d8 321 queue_work(ixgbe_wq, &adapter->service_task);
7086400d
AD		 322}
323
2a1a091c
MR		 324static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
325{
326 struct ixgbe_adapter *adapter = hw->back;
327
328 if (!hw->hw_addr)
329 return;
330 hw->hw_addr = NULL;
331 e_dev_err("Adapter removed\n");
58cf663f
MR		 332 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
333 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 334}
335
f8e2472f 336static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 337{
338 u32 value;
339
340 /* The following check not only optimizes a bit by not
341 * performing a read on the status register when the
342 * register just read was a status register read that
343 * returned IXGBE_FAILED_READ_REG. It also blocks any
344 * potential recursion.
345 */
346 if (reg == IXGBE_STATUS) {
347 ixgbe_remove_adapter(hw);
348 return;
349 }
350 value = ixgbe_read_reg(hw, IXGBE_STATUS);
351 if (value == IXGBE_FAILED_READ_REG)
352 ixgbe_remove_adapter(hw);
353}
354
f8e2472f
MR		 355/**
356 * ixgbe_read_reg - Read from device register
357 * @hw: hw specific details
358 * @reg: offset of register to read
359 *
360 * Returns : value read or IXGBE_FAILED_READ_REG if removed
361 *
362 * This function is used to read device registers. It checks for device
363 * removal by confirming any read that returns all ones by checking the
364 * status register value for all ones. This function avoids reading from
365 * the hardware if a removal was previously detected in which case it
366 * returns IXGBE_FAILED_READ_REG (all ones).
367 */
368u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
369{
370 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
371 u32 value;
372
373 if (ixgbe_removed(reg_addr))
374 return IXGBE_FAILED_READ_REG;
375 value = readl(reg_addr + reg);
376 if (unlikely(value == IXGBE_FAILED_READ_REG))
377 ixgbe_check_remove(hw, reg);
378 return value;
379}
380
14438464
MR		 381static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
382{
383 u16 value;
384
385 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
386 if (value == IXGBE_FAILED_READ_CFG_WORD) {
387 ixgbe_remove_adapter(hw);
388 return true;
389 }
390 return false;
391}
392
393u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
394{
395 struct ixgbe_adapter *adapter = hw->back;
396 u16 value;
397
398 if (ixgbe_removed(hw->hw_addr))
399 return IXGBE_FAILED_READ_CFG_WORD;
400 pci_read_config_word(adapter->pdev, reg, &value);
401 if (value == IXGBE_FAILED_READ_CFG_WORD &&
402 ixgbe_check_cfg_remove(hw, adapter->pdev))
403 return IXGBE_FAILED_READ_CFG_WORD;
404 return value;
405}
406
407#ifdef CONFIG_PCI_IOV
408static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
409{
410 struct ixgbe_adapter *adapter = hw->back;
411 u32 value;
412
413 if (ixgbe_removed(hw->hw_addr))
414 return IXGBE_FAILED_READ_CFG_DWORD;
415 pci_read_config_dword(adapter->pdev, reg, &value);
416 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
417 ixgbe_check_cfg_remove(hw, adapter->pdev))
418 return IXGBE_FAILED_READ_CFG_DWORD;
419 return value;
420}
421#endif /* CONFIG_PCI_IOV */
422
ed19231c
JK		 423void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
424{
425 struct ixgbe_adapter *adapter = hw->back;
426
427 if (ixgbe_removed(hw->hw_addr))
428 return;
429 pci_write_config_word(adapter->pdev, reg, value);
430}
431
7086400d
AD		 432static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
433{
434 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
435
52f33af8 436 /* flush memory to make sure state is correct before next watchdog */
4e857c58 437 smp_mb__before_atomic();
7086400d
AD		 438 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
439}
440
dcd79aeb
TI		 441struct ixgbe_reg_info {
442 u32 ofs;
443 char *name;
444};
445
446static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
447
448 /* General Registers */
449 {IXGBE_CTRL, "CTRL"},
450 {IXGBE_STATUS, "STATUS"},
451 {IXGBE_CTRL_EXT, "CTRL_EXT"},
452
453 /* Interrupt Registers */
454 {IXGBE_EICR, "EICR"},
455
456 /* RX Registers */
457 {IXGBE_SRRCTL(0), "SRRCTL"},
458 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
459 {IXGBE_RDLEN(0), "RDLEN"},
460 {IXGBE_RDH(0), "RDH"},
461 {IXGBE_RDT(0), "RDT"},
462 {IXGBE_RXDCTL(0), "RXDCTL"},
463 {IXGBE_RDBAL(0), "RDBAL"},
464 {IXGBE_RDBAH(0), "RDBAH"},
465
466 /* TX Registers */
467 {IXGBE_TDBAL(0), "TDBAL"},
468 {IXGBE_TDBAH(0), "TDBAH"},
469 {IXGBE_TDLEN(0), "TDLEN"},
470 {IXGBE_TDH(0), "TDH"},
471 {IXGBE_TDT(0), "TDT"},
472 {IXGBE_TXDCTL(0), "TXDCTL"},
473
474 /* List Terminator */
ca8dfe25 475 { .name = NULL }
dcd79aeb
TI		 476};
477
478
479/*
480 * ixgbe_regdump - register printout routine
481 */
482static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
483{
484 int i = 0, j = 0;
485 char rname[16];
486 u32 regs[64];
487
488 switch (reginfo->ofs) {
489 case IXGBE_SRRCTL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
492 break;
493 case IXGBE_DCA_RXCTRL(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
496 break;
497 case IXGBE_RDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
500 break;
501 case IXGBE_RDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
504 break;
505 case IXGBE_RDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
508 break;
509 case IXGBE_RXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
512 break;
513 case IXGBE_RDBAL(0):
514 for (i = 0; i < 64; i++)
515 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
516 break;
517 case IXGBE_RDBAH(0):
518 for (i = 0; i < 64; i++)
519 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
520 break;
521 case IXGBE_TDBAL(0):
522 for (i = 0; i < 64; i++)
523 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
524 break;
525 case IXGBE_TDBAH(0):
526 for (i = 0; i < 64; i++)
527 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
528 break;
529 case IXGBE_TDLEN(0):
530 for (i = 0; i < 64; i++)
531 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
532 break;
533 case IXGBE_TDH(0):
534 for (i = 0; i < 64; i++)
535 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
536 break;
537 case IXGBE_TDT(0):
538 for (i = 0; i < 64; i++)
539 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
540 break;
541 case IXGBE_TXDCTL(0):
542 for (i = 0; i < 64; i++)
543 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
544 break;
545 default:
c7689578 546 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 547 IXGBE_READ_REG(hw, reginfo->ofs));
548 return;
549 }
550
551 for (i = 0; i < 8; i++) {
552 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 553 pr_err("%-15s", rname);
dcd79aeb 554 for (j = 0; j < 8; j++)
c7689578
JP		 555 pr_cont(" %08x", regs[i*8+j]);
556 pr_cont("\n");
dcd79aeb
TI		 557 }
558
559}
560
561/*
562 * ixgbe_dump - Print registers, tx-rings and rx-rings
563 */
564static void ixgbe_dump(struct ixgbe_adapter *adapter)
565{
566 struct net_device *netdev = adapter->netdev;
567 struct ixgbe_hw *hw = &adapter->hw;
568 struct ixgbe_reg_info *reginfo;
569 int n = 0;
570 struct ixgbe_ring *tx_ring;
729739b7 571 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 572 union ixgbe_adv_tx_desc *tx_desc;
573 struct my_u0 { u64 a; u64 b; } *u0;
574 struct ixgbe_ring *rx_ring;
575 union ixgbe_adv_rx_desc *rx_desc;
576 struct ixgbe_rx_buffer *rx_buffer_info;
577 u32 staterr;
578 int i = 0;
579
580 if (!netif_msg_hw(adapter))
581 return;
582
583 /* Print netdevice Info */
584 if (netdev) {
585 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 586 pr_info("Device Name state "
dcd79aeb 587 "trans_start last_rx\n");
c7689578
JP		 588 pr_info("%-15s %016lX %016lX %016lX\n",
589 netdev->name,
590 netdev->state,
591 netdev->trans_start,
592 netdev->last_rx);
dcd79aeb
TI		 593 }
594
595 /* Print Registers */
596 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 597 pr_info(" Register Name Value\n");
dcd79aeb
TI		 598 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
599 reginfo->name; reginfo++) {
600 ixgbe_regdump(hw, reginfo);
601 }
602
603 /* Print TX Ring Summary */
604 if (!netdev || !netif_running(netdev))
e90dd264 605 return;
dcd79aeb
TI		 606
607 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 608 pr_info(" %s %s %s %s\n",
609 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
610 "leng", "ntw", "timestamp");
dcd79aeb
TI		 611 for (n = 0; n < adapter->num_tx_queues; n++) {
612 tx_ring = adapter->tx_ring[n];
729739b7 613 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 614 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 615 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 616 (u64)dma_unmap_addr(tx_buffer, dma),
617 dma_unmap_len(tx_buffer, len),
618 tx_buffer->next_to_watch,
619 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 620 }
621
622 /* Print TX Rings */
623 if (!netif_msg_tx_done(adapter))
624 goto rx_ring_summary;
625
626 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
627
628 /* Transmit Descriptor Formats
629 *
39ac868a 630 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 631 * +--------------------------------------------------------------+
632 * 0 | Buffer Address [63:0] |
633 * +--------------------------------------------------------------+
39ac868a 634 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 635 * +--------------------------------------------------------------+
636 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 637 *
638 * 82598 Advanced Transmit Descriptor (Write-Back Format)
639 * +--------------------------------------------------------------+
640 * 0 | RSV [63:0] |
641 * +--------------------------------------------------------------+
642 * 8 | RSV | STA | NXTSEQ |
643 * +--------------------------------------------------------------+
644 * 63 36 35 32 31 0
645 *
646 * 82599+ Advanced Transmit Descriptor
647 * +--------------------------------------------------------------+
648 * 0 | Buffer Address [63:0] |
649 * +--------------------------------------------------------------+
650 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
651 * +--------------------------------------------------------------+
652 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
653 *
654 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
655 * +--------------------------------------------------------------+
656 * 0 | RSV [63:0] |
657 * +--------------------------------------------------------------+
658 * 8 | RSV | STA | RSV |
659 * +--------------------------------------------------------------+
660 * 63 36 35 32 31 0
dcd79aeb
TI		 661 */
662
663 for (n = 0; n < adapter->num_tx_queues; n++) {
664 tx_ring = adapter->tx_ring[n];
c7689578
JP		 665 pr_info("------------------------------------\n");
666 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
667 pr_info("------------------------------------\n");
8ad88e37
JH		 668 pr_info("%s%s %s %s %s %s\n",
669 "T [desc] [address 63:0 ] ",
670 "[PlPOIdStDDt Ln] [bi->dma ] ",
671 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 672
673 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 674 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 675 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 676 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 677 if (dma_unmap_len(tx_buffer, len) > 0) {
678 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
679 i,
680 le64_to_cpu(u0->a),
681 le64_to_cpu(u0->b),
682 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 683 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 684 tx_buffer->next_to_watch,
685 (u64)tx_buffer->time_stamp,
686 tx_buffer->skb);
687 if (i == tx_ring->next_to_use &&
688 i == tx_ring->next_to_clean)
689 pr_cont(" NTC/U\n");
690 else if (i == tx_ring->next_to_use)
691 pr_cont(" NTU\n");
692 else if (i == tx_ring->next_to_clean)
693 pr_cont(" NTC\n");
694 else
695 pr_cont("\n");
696
697 if (netif_msg_pktdata(adapter) &&
698 tx_buffer->skb)
699 print_hex_dump(KERN_INFO, "",
700 DUMP_PREFIX_ADDRESS, 16, 1,
701 tx_buffer->skb->data,
702 dma_unmap_len(tx_buffer, len),
703 true);
704 }
dcd79aeb
TI		 705 }
706 }
707
708 /* Print RX Rings Summary */
709rx_ring_summary:
710 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 711 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 712 for (n = 0; n < adapter->num_rx_queues; n++) {
713 rx_ring = adapter->rx_ring[n];
c7689578
JP		 714 pr_info("%5d %5X %5X\n",
715 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 716 }
717
718 /* Print RX Rings */
719 if (!netif_msg_rx_status(adapter))
e90dd264 720 return;
dcd79aeb
TI		 721
722 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
723
39ac868a
JH		 724 /* Receive Descriptor Formats
725 *
726 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 727 * 63 1 0
728 * +-----------------------------------------------------+
729 * 0 | Packet Buffer Address [63:1] |A0/NSE|
730 * +----------------------------------------------+------+
731 * 8 | Header Buffer Address [63:1] | DD |
732 * +-----------------------------------------------------+
733 *
734 *
39ac868a 735 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 736 *
737 * 63 48 47 32 31 30 21 20 16 15 4 3 0
738 * +------------------------------------------------------+
39ac868a
JH		 739 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
740 * | Packet | IP | | | | Type | Type |
741 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 742 * +------------------------------------------------------+
743 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
744 * +------------------------------------------------------+
745 * 63 48 47 32 31 20 19 0
39ac868a
JH		 746 *
747 * 82599+ Advanced Receive Descriptor (Read) Format
748 * 63 1 0
749 * +-----------------------------------------------------+
750 * 0 | Packet Buffer Address [63:1] |A0/NSE|
751 * +----------------------------------------------+------+
752 * 8 | Header Buffer Address [63:1] | DD |
753 * +-----------------------------------------------------+
754 *
755 *
756 * 82599+ Advanced Receive Descriptor (Write-Back) Format
757 *
758 * 63 48 47 32 31 30 21 20 17 16 4 3 0
759 * +------------------------------------------------------+
760 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
761 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
762 * |/ Flow Dir Flt ID | | | | | |
763 * +------------------------------------------------------+
764 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
765 * +------------------------------------------------------+
766 * 63 48 47 32 31 20 19 0
dcd79aeb 767 */
39ac868a 768
dcd79aeb
TI		 769 for (n = 0; n < adapter->num_rx_queues; n++) {
770 rx_ring = adapter->rx_ring[n];
c7689578
JP		 771 pr_info("------------------------------------\n");
772 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
773 pr_info("------------------------------------\n");
8ad88e37
JH		 774 pr_info("%s%s%s",
775 "R [desc] [ PktBuf A0] ",
776 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 777 "<-- Adv Rx Read format\n");
8ad88e37
JH		 778 pr_info("%s%s%s",
779 "RWB[desc] [PcsmIpSHl PtRs] ",
780 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 781 "<-- Adv Rx Write-Back format\n");
782
783 for (i = 0; i < rx_ring->count; i++) {
784 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 785 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 786 u0 = (struct my_u0 *)rx_desc;
787 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
788 if (staterr & IXGBE_RXD_STAT_DD) {
789 /* Descriptor Done */
c7689578 790 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 791 "%016llX ---------------- %p", i,
792 le64_to_cpu(u0->a),
793 le64_to_cpu(u0->b),
794 rx_buffer_info->skb);
795 } else {
c7689578 796 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 797 "%016llX %016llX %p", i,
798 le64_to_cpu(u0->a),
799 le64_to_cpu(u0->b),
800 (u64)rx_buffer_info->dma,
801 rx_buffer_info->skb);
802
9c50c035
ET		 803 if (netif_msg_pktdata(adapter) &&
804 rx_buffer_info->dma) {
dcd79aeb
TI		 805 print_hex_dump(KERN_INFO, "",
806 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 807 page_address(rx_buffer_info->page) +
808 rx_buffer_info->page_offset,
f800326d 809 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 810 }
811 }
812
813 if (i == rx_ring->next_to_use)
c7689578 814 pr_cont(" NTU\n");
dcd79aeb 815 else if (i == rx_ring->next_to_clean)
c7689578 816 pr_cont(" NTC\n");
dcd79aeb 817 else
c7689578 818 pr_cont("\n");
dcd79aeb
TI		 819
820 }
821 }
dcd79aeb
TI		 822}
823
5eba3699
AV		 824static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
825{
826 u32 ctrl_ext;
827
828 /* Let firmware take over control of h/w */
829 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
830 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 831 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 832}
833
834static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
835{
836 u32 ctrl_ext;
837
838 /* Let firmware know the driver has taken over */
839 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
840 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 841 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 842}
9a799d71 843
49ce9c2c 844/**
e8e26350
PW		 845 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
846 * @adapter: pointer to adapter struct
847 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
848 * @queue: queue to map the corresponding interrupt to
849 * @msix_vector: the vector to map to the corresponding queue
850 *
851 */
852static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 853 u8 queue, u8 msix_vector)
9a799d71
AK		 854{
855 u32 ivar, index;
e8e26350
PW		 856 struct ixgbe_hw *hw = &adapter->hw;
857 switch (hw->mac.type) {
858 case ixgbe_mac_82598EB:
859 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
860 if (direction == -1)
861 direction = 0;
862 index = (((direction * 64) + queue) >> 2) & 0x1F;
863 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
864 ivar &= ~(0xFF << (8 * (queue & 0x3)));
865 ivar |= (msix_vector << (8 * (queue & 0x3)));
866 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
867 break;
868 case ixgbe_mac_82599EB:
b93a2226 869 case ixgbe_mac_X540:
9a75a1ac
DS		 870 case ixgbe_mac_X550:
871 case ixgbe_mac_X550EM_x:
e8e26350
PW		 872 if (direction == -1) {
873 /* other causes */
874 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
875 index = ((queue & 1) * 8);
876 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
877 ivar &= ~(0xFF << index);
878 ivar |= (msix_vector << index);
879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
880 break;
881 } else {
882 /* tx or rx causes */
883 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
884 index = ((16 * (queue & 1)) + (8 * direction));
885 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
886 ivar &= ~(0xFF << index);
887 ivar |= (msix_vector << index);
888 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
889 break;
890 }
891 default:
892 break;
893 }
9a799d71
AK		 894}
895
fe49f04a 896static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 897 u64 qmask)
fe49f04a
AD		 898{
899 u32 mask;
900
bd508178
AD		 901 switch (adapter->hw.mac.type) {
902 case ixgbe_mac_82598EB:
fe49f04a
AD		 903 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
904 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 905 break;
906 case ixgbe_mac_82599EB:
b93a2226 907 case ixgbe_mac_X540:
9a75a1ac
DS		 908 case ixgbe_mac_X550:
909 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 910 mask = (qmask & 0xFFFFFFFF);
911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
912 mask = (qmask >> 32);
913 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 914 break;
915 default:
916 break;
fe49f04a
AD		 917 }
918}
919
729739b7
AD		 920void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
921 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 922{
729739b7
AD		 923 if (tx_buffer->skb) {
924 dev_kfree_skb_any(tx_buffer->skb);
925 if (dma_unmap_len(tx_buffer, len))
d3d00239 926 dma_unmap_single(ring->dev,
729739b7
AD		 927 dma_unmap_addr(tx_buffer, dma),
928 dma_unmap_len(tx_buffer, len),
929 DMA_TO_DEVICE);
930 } else if (dma_unmap_len(tx_buffer, len)) {
931 dma_unmap_page(ring->dev,
932 dma_unmap_addr(tx_buffer, dma),
933 dma_unmap_len(tx_buffer, len),
934 DMA_TO_DEVICE);
e5a43549 935 }
729739b7
AD		 936 tx_buffer->next_to_watch = NULL;
937 tx_buffer->skb = NULL;
938 dma_unmap_len_set(tx_buffer, len, 0);
939 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 940}
941
943561d3 942static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 943{
944 struct ixgbe_hw *hw = &adapter->hw;
945 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 946 int i;
943561d3 947 u32 data;
c84d324c 948
943561d3
AD		 949 if ((hw->fc.current_mode != ixgbe_fc_full) &&
950 (hw->fc.current_mode != ixgbe_fc_rx_pause))
951 return;
c84d324c 952
943561d3
AD		 953 switch (hw->mac.type) {
954 case ixgbe_mac_82598EB:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
956 break;
957 default:
958 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
959 }
960 hwstats->lxoffrxc += data;
c84d324c 961
943561d3
AD		 962 /* refill credits (no tx hang) if we received xoff */
963 if (!data)
c84d324c 964 return;
943561d3
AD		 965
966 for (i = 0; i < adapter->num_tx_queues; i++)
967 clear_bit(__IXGBE_HANG_CHECK_ARMED,
968 &adapter->tx_ring[i]->state);
969}
970
971static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
972{
973 struct ixgbe_hw *hw = &adapter->hw;
974 struct ixgbe_hw_stats *hwstats = &adapter->stats;
975 u32 xoff[8] = {0};
2afaa00d 976 u8 tc;
943561d3
AD		 977 int i;
978 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
979
980 if (adapter->ixgbe_ieee_pfc)
981 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
982
983 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
984 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 985 return;
943561d3 986 }
c84d324c
JF		 987
988 /* update stats for each tc, only valid with PFC enabled */
989 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 990 u32 pxoffrxc;
991
c84d324c
JF		 992 switch (hw->mac.type) {
993 case ixgbe_mac_82598EB:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 995 break;
c84d324c 996 default:
2afaa00d 997 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 998 }
2afaa00d
PN		 999 hwstats->pxoffrxc[i] += pxoffrxc;
1000 /* Get the TC for given UP */
1001 tc = netdev_get_prio_tc_map(adapter->netdev, i);
1002 xoff[tc] += pxoffrxc;
c84d324c
JF		 1003 }
1004
1005 /* disarm tx queues that have received xoff frames */
1006 for (i = 0; i < adapter->num_tx_queues; i++) {
1007 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1008
2afaa00d 1009 tc = tx_ring->dcb_tc;
c84d324c
JF		 1010 if (xoff[tc])
1011 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1012 }
26f23d82
YZ		 1013}
1014
c84d324c 1015static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1016{
7d7ce682 1017 return ring->stats.packets;
c84d324c
JF		 1018}
1019
1020static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1021{
2a47fa45
JF		 1022 struct ixgbe_adapter *adapter;
1023 struct ixgbe_hw *hw;
1024 u32 head, tail;
1025
1026 if (ring->l2_accel_priv)
1027 adapter = ring->l2_accel_priv->real_adapter;
1028 else
1029 adapter = netdev_priv(ring->netdev);
e01c31a5 1030
2a47fa45
JF		 1031 hw = &adapter->hw;
1032 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1033 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1034
1035 if (head != tail)
1036 return (head < tail) ?
1037 tail - head : (tail + ring->count - head);
1038
1039 return 0;
1040}
1041
1042static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1043{
1044 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1045 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1046 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1047
7d637bcc 1048 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1049
1050 /*
1051 * Check for a hung queue, but be thorough. This verifies
1052 * that a transmit has been completed since the previous
1053 * check AND there is at least one packet pending. The
1054 * ARMED bit is set to indicate a potential hang. The
1055 * bit is cleared if a pause frame is received to remove
1056 * false hang detection due to PFC or 802.3x frames. By
1057 * requiring this to fail twice we avoid races with
1058 * pfc clearing the ARMED bit and conditions where we
1059 * run the check_tx_hang logic with a transmit completion
1060 * pending but without time to complete it yet.
1061 */
e90dd264 1062 if (tx_done_old == tx_done && tx_pending)
c84d324c 1063 /* make sure it is true for two checks in a row */
e90dd264
MR		 1064 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1065 &tx_ring->state);
1066 /* update completed stats and continue */
1067 tx_ring->tx_stats.tx_done_old = tx_done;
1068 /* reset the countdown */
1069 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1070
e90dd264 1071 return false;
9a799d71
AK		 1072}
1073
c83c6cbd
AD		 1074/**
1075 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1076 * @adapter: driver private struct
1077 **/
1078static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1079{
1080
1081 /* Do the reset outside of interrupt context */
1082 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1083 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1084 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1085 ixgbe_service_event_schedule(adapter);
1086 }
1087}
e01c31a5 1088
9a799d71
AK		 1089/**
1090 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1091 * @q_vector: structure containing interrupt and ring information
e01c31a5 1092 * @tx_ring: tx ring to clean
9a799d71 1093 **/
fe49f04a 1094static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
a3a8749d 1095 struct ixgbe_ring *tx_ring, int napi_budget)
9a799d71 1096{
fe49f04a 1097 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1098 struct ixgbe_tx_buffer *tx_buffer;
1099 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1100 unsigned int total_bytes = 0, total_packets = 0;
59224555 1101 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1102 unsigned int i = tx_ring->next_to_clean;
1103
1104 if (test_bit(__IXGBE_DOWN, &adapter->state))
1105 return true;
9a799d71 1106
d3d00239 1107 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1108 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1109 i -= tx_ring->count;
12207e49 1110
729739b7 1111 do {
d3d00239
AD		 1112 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1113
1114 /* if next_to_watch is not set then there is no work pending */
1115 if (!eop_desc)
1116 break;
1117
7f83a9e6 1118 /* prevent any other reads prior to eop_desc */
7e63bf49 1119 read_barrier_depends();
7f83a9e6 1120
d3d00239
AD		 1121 /* if DD is not set pending work has not been completed */
1122 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1123 break;
8ad494b0 1124
d3d00239
AD		 1125 /* clear next_to_watch to prevent false hangs */
1126 tx_buffer->next_to_watch = NULL;
8ad494b0 1127
091a6246
AD		 1128 /* update the statistics for this packet */
1129 total_bytes += tx_buffer->bytecount;
1130 total_packets += tx_buffer->gso_segs;
1131
fd0db0ed 1132 /* free the skb */
a3a8749d 1133 napi_consume_skb(tx_buffer->skb, napi_budget);
fd0db0ed 1134
729739b7
AD		 1135 /* unmap skb header data */
1136 dma_unmap_single(tx_ring->dev,
1137 dma_unmap_addr(tx_buffer, dma),
1138 dma_unmap_len(tx_buffer, len),
1139 DMA_TO_DEVICE);
1140
fd0db0ed
AD		 1141 /* clear tx_buffer data */
1142 tx_buffer->skb = NULL;
729739b7 1143 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1144
729739b7
AD		 1145 /* unmap remaining buffers */
1146 while (tx_desc != eop_desc) {
d3d00239
AD		 1147 tx_buffer++;
1148 tx_desc++;
8ad494b0 1149 i++;
729739b7
AD		 1150 if (unlikely(!i)) {
1151 i -= tx_ring->count;
d3d00239 1152 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1153 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1154 }
e01c31a5 1155
729739b7
AD		 1156 /* unmap any remaining paged data */
1157 if (dma_unmap_len(tx_buffer, len)) {
1158 dma_unmap_page(tx_ring->dev,
1159 dma_unmap_addr(tx_buffer, dma),
1160 dma_unmap_len(tx_buffer, len),
1161 DMA_TO_DEVICE);
1162 dma_unmap_len_set(tx_buffer, len, 0);
1163 }
1164 }
1165
1166 /* move us one more past the eop_desc for start of next pkt */
1167 tx_buffer++;
1168 tx_desc++;
1169 i++;
1170 if (unlikely(!i)) {
1171 i -= tx_ring->count;
1172 tx_buffer = tx_ring->tx_buffer_info;
1173 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1174 }
1175
1176 /* issue prefetch for next Tx descriptor */
1177 prefetch(tx_desc);
12207e49 1178
729739b7
AD		 1179 /* update budget accounting */
1180 budget--;
1181 } while (likely(budget));
1182
1183 i += tx_ring->count;
9a799d71 1184 tx_ring->next_to_clean = i;
d3d00239 1185 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1186 tx_ring->stats.bytes += total_bytes;
bd198058 1187 tx_ring->stats.packets += total_packets;
d3d00239 1188 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1189 q_vector->tx.total_bytes += total_bytes;
1190 q_vector->tx.total_packets += total_packets;
b953799e 1191
c84d324c
JF		 1192 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1193 /* schedule immediate reset if we believe we hung */
1194 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1195 e_err(drv, "Detected Tx Unit Hang\n"
1196 " Tx Queue <%d>\n"
1197 " TDH, TDT <%x>, <%x>\n"
1198 " next_to_use <%x>\n"
1199 " next_to_clean <%x>\n"
1200 "tx_buffer_info[next_to_clean]\n"
1201 " time_stamp <%lx>\n"
1202 " jiffies <%lx>\n",
1203 tx_ring->queue_index,
1204 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1205 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1206 tx_ring->next_to_use, i,
1207 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1208
1209 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1210
1211 e_info(probe,
1212 "tx hang %d detected on queue %d, resetting adapter\n",
1213 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1214
b953799e 1215 /* schedule immediate reset if we believe we hung */
c83c6cbd 1216 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1217
1218 /* the adapter is about to reset, no point in enabling stuff */
59224555 1219 return true;
b953799e 1220 }
9a799d71 1221
b2d96e0a
AD		 1222 netdev_tx_completed_queue(txring_txq(tx_ring),
1223 total_packets, total_bytes);
1224
e092be60 1225#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1226 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1227 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1228 /* Make sure that anybody stopping the queue after this
1229 * sees the new next_to_clean.
1230 */
1231 smp_mb();
729739b7
AD		 1232 if (__netif_subqueue_stopped(tx_ring->netdev,
1233 tx_ring->queue_index)
1234 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1235 netif_wake_subqueue(tx_ring->netdev,
1236 tx_ring->queue_index);
5b7da515 1237 ++tx_ring->tx_stats.restart_queue;
30eba97a 1238 }
e092be60 1239 }
9a799d71 1240
59224555 1241 return !!budget;
9a799d71
AK		 1242}
1243
5dd2d332 1244#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1245static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1246 struct ixgbe_ring *tx_ring,
33cf09c9 1247 int cpu)
bd0362dd 1248{
33cf09c9 1249 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1250 u32 txctrl = 0;
bdda1a61 1251 u16 reg_offset;
33cf09c9 1252
9de7605e
MR		 1253 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1254 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1255
33cf09c9
AD		 1256 switch (hw->mac.type) {
1257 case ixgbe_mac_82598EB:
bdda1a61 1258 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1259 break;
1260 case ixgbe_mac_82599EB:
b93a2226 1261 case ixgbe_mac_X540:
bdda1a61
AD		 1262 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1263 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1264 break;
1265 default:
bdda1a61
AD		 1266 /* for unknown hardware do not write register */
1267 return;
bd0362dd 1268 }
bdda1a61
AD		 1269
1270 /*
1271 * We can enable relaxed ordering for reads, but not writes when
1272 * DCA is enabled. This is due to a known issue in some chipsets
1273 * which will cause the DCA tag to be cleared.
1274 */
1275 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1276 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1277 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1278
1279 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1280}
1281
bdda1a61
AD		 1282static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1283 struct ixgbe_ring *rx_ring,
33cf09c9 1284 int cpu)
bd0362dd 1285{
33cf09c9 1286 struct ixgbe_hw *hw = &adapter->hw;
9de7605e 1287 u32 rxctrl = 0;
bdda1a61
AD		 1288 u8 reg_idx = rx_ring->reg_idx;
1289
9de7605e
MR		 1290 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1291 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 1292
1293 switch (hw->mac.type) {
33cf09c9 1294 case ixgbe_mac_82599EB:
b93a2226 1295 case ixgbe_mac_X540:
bdda1a61 1296 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1297 break;
1298 default:
1299 break;
1300 }
bdda1a61
AD		 1301
1302 /*
1303 * We can enable relaxed ordering for reads, but not writes when
1304 * DCA is enabled. This is due to a known issue in some chipsets
1305 * which will cause the DCA tag to be cleared.
1306 */
1307 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
9de7605e 1308 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
bdda1a61
AD		 1309 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1310
1311 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1312}
1313
1314static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1315{
1316 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1317 struct ixgbe_ring *ring;
bd0362dd 1318 int cpu = get_cpu();
bd0362dd 1319
33cf09c9
AD		 1320 if (q_vector->cpu == cpu)
1321 goto out_no_update;
1322
a557928e 1323 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1324 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1325
a557928e 1326 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1327 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1328
1329 q_vector->cpu = cpu;
1330out_no_update:
bd0362dd
JC		 1331 put_cpu();
1332}
1333
1334static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1335{
1336 int i;
1337
e35ec126 1338 /* always use CB2 mode, difference is masked in the CB driver */
9de7605e
MR		 1339 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1340 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1341 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1342 else
1343 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1344 IXGBE_DCA_CTRL_DCA_DISABLE);
e35ec126 1345
49c7ffbe 1346 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1347 adapter->q_vector[i]->cpu = -1;
1348 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1349 }
1350}
1351
1352static int __ixgbe_notify_dca(struct device *dev, void *data)
1353{
c60fbb00 1354 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1355 unsigned long event = *(unsigned long *)data;
1356
2a72c31e 1357 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1358 return 0;
1359
bd0362dd
JC		 1360 switch (event) {
1361 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1362 /* if we're already enabled, don't do it again */
1363 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1364 break;
652f093f 1365 if (dca_add_requester(dev) == 0) {
96b0e0f6 1366 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1368 IXGBE_DCA_CTRL_DCA_MODE_CB2);
bd0362dd
JC		 1369 break;
1370 }
1371 /* Fall Through since DCA is disabled. */
1372 case DCA_PROVIDER_REMOVE:
1373 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1374 dca_remove_requester(dev);
1375 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9de7605e
MR		 1376 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1377 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 1378 }
1379 break;
1380 }
1381
652f093f 1382 return 0;
bd0362dd 1383}
67a74ee2 1384
bdda1a61 1385#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1386
1387#define IXGBE_RSS_L4_TYPES_MASK \
1388 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1389 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1390 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1391 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1392
8a0da21b
AD		 1393static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1394 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1395 struct sk_buff *skb)
1396{
7edda4b8
FD		 1397 u16 rss_type;
1398
1399 if (!(ring->netdev->features & NETIF_F_RXHASH))
1400 return;
1401
1402 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1403 IXGBE_RXDADV_RSSTYPE_MASK;
1404
1405 if (!rss_type)
1406 return;
1407
1408 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1409 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1410 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1411}
1412
f800326d 1413#ifdef IXGBE_FCOE
ff886dfc
AD		 1414/**
1415 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1416 * @ring: structure containing ring specific data
ff886dfc
AD		 1417 * @rx_desc: advanced rx descriptor
1418 *
1419 * Returns : true if it is FCoE pkt
1420 */
57efd44c 1421static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1422 union ixgbe_adv_rx_desc *rx_desc)
1423{
1424 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1425
57efd44c 1426 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1427 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1428 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1429 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1430}
1431
f800326d 1432#endif /* IXGBE_FCOE */
e59bd25d
AV		 1433/**
1434 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1435 * @ring: structure containing ring specific data
1436 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1437 * @skb: skb currently being received and modified
1438 **/
8a0da21b 1439static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1440 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1441 struct sk_buff *skb)
9a799d71 1442{
3f207800
DS		 1443 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1444 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1445 bool encap_pkt = false;
1446
8a0da21b 1447 skb_checksum_none_assert(skb);
9a799d71 1448
712744be 1449 /* Rx csum disabled */
8a0da21b 1450 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1451 return;
e59bd25d 1452
3f207800
DS		 1453 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1454 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1455 encap_pkt = true;
1456 skb->encapsulation = 1;
3f207800
DS		 1457 }
1458
e59bd25d 1459 /* if IP and error */
f56e0cb1
AD		 1460 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1461 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1462 ring->rx_stats.csum_err++;
9a799d71
AK		 1463 return;
1464 }
e59bd25d 1465
f56e0cb1 1466 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1467 return;
1468
f56e0cb1 1469 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1470 /*
1471 * 82599 errata, UDP frames with a 0 checksum can be marked as
1472 * checksum errors.
1473 */
8a0da21b
AD		 1474 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1475 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1476 return;
1477
8a0da21b 1478 ring->rx_stats.csum_err++;
e59bd25d
AV		 1479 return;
1480 }
1481
9a799d71 1482 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1483 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1484 if (encap_pkt) {
1485 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1486 return;
1487
1488 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
d469251b 1489 skb->ip_summed = CHECKSUM_NONE;
3f207800
DS		 1490 return;
1491 }
1492 /* If we checked the outer header let the stack know */
1493 skb->csum_level = 1;
1494 }
9a799d71
AK		 1495}
1496
f990b79b
AD		 1497static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1498 struct ixgbe_rx_buffer *bi)
1499{
1500 struct page *page = bi->page;
18cb652a 1501 dma_addr_t dma;
f990b79b 1502
f800326d 1503 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1504 if (likely(page))
f990b79b
AD		 1505 return true;
1506
f800326d 1507 /* alloc new page for storage */
18cb652a
AD		 1508 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1509 if (unlikely(!page)) {
1510 rx_ring->rx_stats.alloc_rx_page_failed++;
1511 return false;
f990b79b
AD		 1512 }
1513
f800326d
AD		 1514 /* map page for use */
1515 dma = dma_map_page(rx_ring->dev, page, 0,
1516 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1517
1518 /*
1519 * if mapping failed free memory back to system since
1520 * there isn't much point in holding memory we can't use
1521 */
1522 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1523 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1524
f990b79b
AD		 1525 rx_ring->rx_stats.alloc_rx_page_failed++;
1526 return false;
1527 }
1528
f800326d 1529 bi->dma = dma;
18cb652a 1530 bi->page = page;
afaa9459 1531 bi->page_offset = 0;
f800326d 1532
f990b79b
AD		 1533 return true;
1534}
1535
9a799d71 1536/**
f990b79b 1537 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1538 * @rx_ring: ring to place buffers on
1539 * @cleaned_count: number of buffers to replace
9a799d71 1540 **/
fc77dc3c 1541void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1542{
9a799d71 1543 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1544 struct ixgbe_rx_buffer *bi;
d5f398ed 1545 u16 i = rx_ring->next_to_use;
9a799d71 1546
f800326d
AD		 1547 /* nothing to do */
1548 if (!cleaned_count)
fc77dc3c
AD		 1549 return;
1550
e4f74028 1551 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1552 bi = &rx_ring->rx_buffer_info[i];
1553 i -= rx_ring->count;
9a799d71 1554
f800326d
AD		 1555 do {
1556 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1557 break;
d5f398ed 1558
f800326d
AD		 1559 /*
1560 * Refresh the desc even if buffer_addrs didn't change
1561 * because each write-back erases this info.
1562 */
1563 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1564
f990b79b
AD		 1565 rx_desc++;
1566 bi++;
9a799d71 1567 i++;
f990b79b 1568 if (unlikely(!i)) {
e4f74028 1569 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1570 bi = rx_ring->rx_buffer_info;
1571 i -= rx_ring->count;
1572 }
1573
18cb652a
AD		 1574 /* clear the status bits for the next_to_use descriptor */
1575 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1576
1577 cleaned_count--;
1578 } while (cleaned_count);
7c6e0a43 1579
f990b79b
AD		 1580 i += rx_ring->count;
1581
ad435ec6
AD		 1582 if (rx_ring->next_to_use != i) {
1583 rx_ring->next_to_use = i;
1584
1585 /* update next to alloc since we have filled the ring */
1586 rx_ring->next_to_alloc = i;
1587
1588 /* Force memory writes to complete before letting h/w
1589 * know there are new descriptors to fetch. (Only
1590 * applicable for weak-ordered memory model archs,
1591 * such as IA-64).
1592 */
1593 wmb();
1594 writel(i, rx_ring->tail);
1595 }
9a799d71
AK		 1596}
1597
1d2024f6
AD		 1598static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1599 struct sk_buff *skb)
1600{
f800326d 1601 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1602
1603 /* set gso_size to avoid messing up TCP MSS */
1604 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1605 IXGBE_CB(skb)->append_cnt);
96be80ab 1606 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1607}
1608
1609static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1610 struct sk_buff *skb)
1611{
1612 /* if append_cnt is 0 then frame is not RSC */
1613 if (!IXGBE_CB(skb)->append_cnt)
1614 return;
1615
1616 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1617 rx_ring->rx_stats.rsc_flush++;
1618
1619 ixgbe_set_rsc_gso_size(rx_ring, skb);
1620
1621 /* gso_size is computed using append_cnt so always clear it last */
1622 IXGBE_CB(skb)->append_cnt = 0;
1623}
1624
8a0da21b
AD		 1625/**
1626 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1627 * @rx_ring: rx descriptor ring packet is being transacted on
1628 * @rx_desc: pointer to the EOP Rx descriptor
1629 * @skb: pointer to current skb being populated
f8212f97 1630 *
8a0da21b
AD		 1631 * This function checks the ring, descriptor, and packet information in
1632 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1633 * other fields within the skb.
f8212f97 1634 **/
8a0da21b
AD		 1635static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1636 union ixgbe_adv_rx_desc *rx_desc,
1637 struct sk_buff *skb)
f8212f97 1638{
43e95f11 1639 struct net_device *dev = rx_ring->netdev;
a9763f3c 1640 u32 flags = rx_ring->q_vector->adapter->flags;
43e95f11 1641
8a0da21b
AD		 1642 ixgbe_update_rsc_stats(rx_ring, skb);
1643
1644 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1645
8a0da21b
AD		 1646 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1647
a9763f3c
MR		 1648 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1649 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1650
f646968f 1651 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1652 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1653 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1654 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1655 }
1656
8a0da21b 1657 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1658
43e95f11 1659 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1660}
1661
8a0da21b
AD		 1662static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1663 struct sk_buff *skb)
aa80175a 1664{
93f93a44 1665 skb_mark_napi_id(skb, &q_vector->napi);
b4640030 1666 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1667 netif_receive_skb(skb);
8a0da21b 1668 else
856f606e 1669 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1670}
43634e82 1671
f800326d
AD		 1672/**
1673 * ixgbe_is_non_eop - process handling of non-EOP buffers
1674 * @rx_ring: Rx ring being processed
1675 * @rx_desc: Rx descriptor for current buffer
1676 * @skb: Current socket buffer containing buffer in progress
1677 *
1678 * This function updates next to clean. If the buffer is an EOP buffer
1679 * this function exits returning false, otherwise it will place the
1680 * sk_buff in the next buffer to be chained and return true indicating
1681 * that this is in fact a non-EOP buffer.
1682 **/
1683static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1684 union ixgbe_adv_rx_desc *rx_desc,
1685 struct sk_buff *skb)
1686{
1687 u32 ntc = rx_ring->next_to_clean + 1;
1688
1689 /* fetch, update, and store next to clean */
1690 ntc = (ntc < rx_ring->count) ? ntc : 0;
1691 rx_ring->next_to_clean = ntc;
1692
1693 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1694
5a02cbd1
AD		 1695 /* update RSC append count if present */
1696 if (ring_is_rsc_enabled(rx_ring)) {
1697 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1698 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1699
1700 if (unlikely(rsc_enabled)) {
1701 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1702
1703 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1704 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1705
5a02cbd1
AD		 1706 /* update ntc based on RSC value */
1707 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1708 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1709 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1710 }
f800326d
AD		 1711 }
1712
5a02cbd1
AD		 1713 /* if we are the last buffer then there is nothing else to do */
1714 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1715 return false;
1716
f800326d
AD		 1717 /* place skb in next buffer to be received */
1718 rx_ring->rx_buffer_info[ntc].skb = skb;
1719 rx_ring->rx_stats.non_eop_descs++;
1720
1721 return true;
1722}
1723
19861ce2
AD		 1724/**
1725 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1726 * @rx_ring: rx descriptor ring packet is being transacted on
1727 * @skb: pointer to current skb being adjusted
1728 *
1729 * This function is an ixgbe specific version of __pskb_pull_tail. The
1730 * main difference between this version and the original function is that
1731 * this function can make several assumptions about the state of things
1732 * that allow for significant optimizations versus the standard function.
1733 * As a result we can do things like drop a frag and maintain an accurate
1734 * truesize for the skb.
1735 */
1736static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1737 struct sk_buff *skb)
1738{
1739 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1740 unsigned char *va;
1741 unsigned int pull_len;
1742
1743 /*
1744 * it is valid to use page_address instead of kmap since we are
1745 * working with pages allocated out of the lomem pool per
1746 * alloc_page(GFP_ATOMIC)
1747 */
1748 va = skb_frag_address(frag);
1749
1750 /*
1751 * we need the header to contain the greater of either ETH_HLEN or
1752 * 60 bytes if the skb->len is less than 60 for skb_pad.
1753 */
8496e338 1754 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1755
1756 /* align pull length to size of long to optimize memcpy performance */
1757 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1758
1759 /* update all of the pointers */
1760 skb_frag_size_sub(frag, pull_len);
1761 frag->page_offset += pull_len;
1762 skb->data_len -= pull_len;
1763 skb->tail += pull_len;
19861ce2
AD		 1764}
1765
42073d91
AD		 1766/**
1767 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1768 * @rx_ring: rx descriptor ring packet is being transacted on
1769 * @skb: pointer to current skb being updated
1770 *
1771 * This function provides a basic DMA sync up for the first fragment of an
1772 * skb. The reason for doing this is that the first fragment cannot be
1773 * unmapped until we have reached the end of packet descriptor for a buffer
1774 * chain.
1775 */
1776static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1777 struct sk_buff *skb)
1778{
1779 /* if the page was released unmap it, else just sync our portion */
1780 if (unlikely(IXGBE_CB(skb)->page_released)) {
1781 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1782 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1783 IXGBE_CB(skb)->page_released = false;
1784 } else {
1785 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1786
1787 dma_sync_single_range_for_cpu(rx_ring->dev,
1788 IXGBE_CB(skb)->dma,
1789 frag->page_offset,
1790 ixgbe_rx_bufsz(rx_ring),
1791 DMA_FROM_DEVICE);
1792 }
1793 IXGBE_CB(skb)->dma = 0;
1794}
1795
f800326d
AD		 1796/**
1797 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1798 * @rx_ring: rx descriptor ring packet is being transacted on
1799 * @rx_desc: pointer to the EOP Rx descriptor
1800 * @skb: pointer to current skb being fixed
1801 *
1802 * Check for corrupted packet headers caused by senders on the local L2
1803 * embedded NIC switch not setting up their Tx Descriptors right. These
1804 * should be very rare.
1805 *
1806 * Also address the case where we are pulling data in on pages only
1807 * and as such no data is present in the skb header.
1808 *
1809 * In addition if skb is not at least 60 bytes we need to pad it so that
1810 * it is large enough to qualify as a valid Ethernet frame.
1811 *
1812 * Returns true if an error was encountered and skb was freed.
1813 **/
1814static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1815 union ixgbe_adv_rx_desc *rx_desc,
1816 struct sk_buff *skb)
1817{
f800326d 1818 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1819
1820 /* verify that the packet does not have any known errors */
1821 if (unlikely(ixgbe_test_staterr(rx_desc,
1822 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1823 !(netdev->features & NETIF_F_RXALL))) {
1824 dev_kfree_skb_any(skb);
1825 return true;
1826 }
1827
19861ce2 1828 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1829 if (skb_is_nonlinear(skb))
1830 ixgbe_pull_tail(rx_ring, skb);
f800326d 1831
57efd44c
AD		 1832#ifdef IXGBE_FCOE
1833 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1834 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1835 return false;
1836
1837#endif
a94d9e22
AD		 1838 /* if eth_skb_pad returns an error the skb was freed */
1839 if (eth_skb_pad(skb))
1840 return true;
f800326d
AD		 1841
1842 return false;
1843}
1844
f800326d
AD		 1845/**
1846 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1847 * @rx_ring: rx descriptor ring to store buffers on
1848 * @old_buff: donor buffer to have page reused
1849 *
0549ae20 1850 * Synchronizes page for reuse by the adapter
f800326d
AD		 1851 **/
1852static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1853 struct ixgbe_rx_buffer *old_buff)
1854{
1855 struct ixgbe_rx_buffer *new_buff;
1856 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1857
1858 new_buff = &rx_ring->rx_buffer_info[nta];
1859
1860 /* update, and store next to alloc */
1861 nta++;
1862 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1863
1864 /* transfer page from old buffer to new buffer */
18cb652a 1865 *new_buff = *old_buff;
f800326d
AD		 1866
1867 /* sync the buffer for use by the device */
1868 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1869 new_buff->page_offset,
1870 ixgbe_rx_bufsz(rx_ring),
f800326d 1871 DMA_FROM_DEVICE);
f800326d
AD		 1872}
1873
18cb652a
AD		 1874static inline bool ixgbe_page_is_reserved(struct page *page)
1875{
2f064f34 1876 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1877}
1878
f800326d
AD		 1879/**
1880 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1881 * @rx_ring: rx descriptor ring to transact packets on
1882 * @rx_buffer: buffer containing page to add
1883 * @rx_desc: descriptor containing length of buffer written by hardware
1884 * @skb: sk_buff to place the data into
1885 *
0549ae20
AD		 1886 * This function will add the data contained in rx_buffer->page to the skb.
1887 * This is done either through a direct copy if the data in the buffer is
1888 * less than the skb header size, otherwise it will just attach the page as
1889 * a frag to the skb.
1890 *
1891 * The function will then update the page offset if necessary and return
1892 * true if the buffer can be reused by the adapter.
f800326d 1893 **/
0549ae20 1894static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1895 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1896 union ixgbe_adv_rx_desc *rx_desc,
1897 struct sk_buff *skb)
f800326d 1898{
0549ae20
AD		 1899 struct page *page = rx_buffer->page;
1900 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1901#if (PAGE_SIZE < 8192)
0549ae20 1902 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1903#else
1904 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1905 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1906 ixgbe_rx_bufsz(rx_ring);
1907#endif
0549ae20 1908
cf3fe7ac
AD		 1909 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1910 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1911
1912 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1913
18cb652a
AD		 1914 /* page is not reserved, we can reuse buffer as-is */
1915 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1916 return true;
1917
1918 /* this page cannot be reused so discard it */
18cb652a 1919 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1920 return false;
1921 }
1922
0549ae20
AD		 1923 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1924 rx_buffer->page_offset, size, truesize);
1925
09816fbe 1926 /* avoid re-using remote pages */
18cb652a 1927 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1928 return false;
1929
1930#if (PAGE_SIZE < 8192)
1931 /* if we are only owner of page we can reuse it */
1932 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1933 return false;
1934
1935 /* flip page offset to other buffer */
1936 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1937#else
1938 /* move offset up to the next cache line */
1939 rx_buffer->page_offset += truesize;
1940
1941 if (rx_buffer->page_offset > last_offset)
1942 return false;
09816fbe 1943#endif
0549ae20 1944
18cb652a
AD		 1945 /* Even if we own the page, we are not allowed to use atomic_set()
1946 * This would break get_page_unless_zero() users.
1947 */
fe896d18 1948 page_ref_inc(page);
18cb652a 1949
0549ae20 1950 return true;
f800326d
AD		 1951}
1952
18806c9e
AD		 1953static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1954 union ixgbe_adv_rx_desc *rx_desc)
1955{
1956 struct ixgbe_rx_buffer *rx_buffer;
1957 struct sk_buff *skb;
1958 struct page *page;
1959
1960 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1961 page = rx_buffer->page;
1962 prefetchw(page);
1963
1964 skb = rx_buffer->skb;
1965
1966 if (likely(!skb)) {
1967 void *page_addr = page_address(page) +
1968 rx_buffer->page_offset;
1969
1970 /* prefetch first cache line of first page */
1971 prefetch(page_addr);
1972#if L1_CACHE_BYTES < 128
1973 prefetch(page_addr + L1_CACHE_BYTES);
1974#endif
1975
1976 /* allocate a skb to store the frags */
67fd893e
AD		 1977 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1978 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1979 if (unlikely(!skb)) {
1980 rx_ring->rx_stats.alloc_rx_buff_failed++;
1981 return NULL;
1982 }
1983
1984 /*
1985 * we will be copying header into skb->data in
1986 * pskb_may_pull so it is in our interest to prefetch
1987 * it now to avoid a possible cache miss
1988 */
1989 prefetchw(skb->data);
1990
1991 /*
1992 * Delay unmapping of the first packet. It carries the
1993 * header information, HW may still access the header
1994 * after the writeback. Only unmap it when EOP is
1995 * reached
1996 */
1997 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1998 goto dma_sync;
1999
2000 IXGBE_CB(skb)->dma = rx_buffer->dma;
2001 } else {
2002 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2003 ixgbe_dma_sync_frag(rx_ring, skb);
2004
2005dma_sync:
2006 /* we are reusing so sync this buffer for CPU use */
2007 dma_sync_single_range_for_cpu(rx_ring->dev,
2008 rx_buffer->dma,
2009 rx_buffer->page_offset,
2010 ixgbe_rx_bufsz(rx_ring),
2011 DMA_FROM_DEVICE);
18cb652a
AD		 2012
2013 rx_buffer->skb = NULL;
18806c9e
AD		 2014 }
2015
2016 /* pull page into skb */
2017 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2018 /* hand second half of page back to the ring */
2019 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2020 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2021 /* the page has been released from the ring */
2022 IXGBE_CB(skb)->page_released = true;
2023 } else {
2024 /* we are not reusing the buffer so unmap it */
2025 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2026 ixgbe_rx_pg_size(rx_ring),
2027 DMA_FROM_DEVICE);
2028 }
2029
2030 /* clear contents of buffer_info */
18806c9e
AD		 2031 rx_buffer->page = NULL;
2032
2033 return skb;
f800326d
AD		 2034}
2035
2036/**
2037 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2038 * @q_vector: structure containing interrupt and ring information
2039 * @rx_ring: rx descriptor ring to transact packets on
2040 * @budget: Total limit on number of packets to process
2041 *
2042 * This function provides a "bounce buffer" approach to Rx interrupt
2043 * processing. The advantage to this is that on systems that have
2044 * expensive overhead for IOMMU access this provides a means of avoiding
2045 * it by maintaining the mapping of the page to the syste.
2046 *
5a85e737 2047 * Returns amount of work completed
f800326d 2048 **/
5a85e737 2049static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2050 struct ixgbe_ring *rx_ring,
f4de00ed 2051 const int budget)
9a799d71 2052{
d2f4fbe2 2053 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2054#ifdef IXGBE_FCOE
f800326d 2055 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2056 int ddp_bytes;
2057 unsigned int mss = 0;
3d8fd385 2058#endif /* IXGBE_FCOE */
f800326d 2059 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2060
fdabfc8a 2061 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2062 union ixgbe_adv_rx_desc *rx_desc;
2063 struct sk_buff *skb;
f800326d
AD		 2064
2065 /* return some buffers to hardware, one at a time is too slow */
2066 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2067 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2068 cleaned_count = 0;
2069 }
2070
18806c9e 2071 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2072
124b74c1 2073 if (!rx_desc->wb.upper.status_error)
f800326d 2074 break;
9a799d71 2075
124b74c1 2076 /* This memory barrier is needed to keep us from reading
f800326d 2077 * any other fields out of the rx_desc until we know the
124b74c1 2078 * descriptor has been written back
f800326d 2079 */
124b74c1 2080 dma_rmb();
9a799d71 2081
18806c9e
AD		 2082 /* retrieve a buffer from the ring */
2083 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2084
18806c9e
AD		 2085 /* exit if we failed to retrieve a buffer */
2086 if (!skb)
2087 break;
9a799d71 2088
9a799d71 2089 cleaned_count++;
f8212f97 2090
f800326d
AD		 2091 /* place incomplete frames back on ring for completion */
2092 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2093 continue;
c267fc16 2094
f800326d
AD		 2095 /* verify the packet layout is correct */
2096 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2097 continue;
9a799d71 2098
d2f4fbe2
AV		 2099 /* probably a little skewed due to removing CRC */
2100 total_rx_bytes += skb->len;
d2f4fbe2 2101
8a0da21b
AD		 2102 /* populate checksum, timestamp, VLAN, and protocol */
2103 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2104
332d4a7d
YZ		 2105#ifdef IXGBE_FCOE
2106 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2107 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2108 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2109 /* include DDPed FCoE data */
2110 if (ddp_bytes > 0) {
2111 if (!mss) {
2112 mss = rx_ring->netdev->mtu -
2113 sizeof(struct fcoe_hdr) -
2114 sizeof(struct fc_frame_header) -
2115 sizeof(struct fcoe_crc_eof);
2116 if (mss > 512)
2117 mss &= ~511;
2118 }
2119 total_rx_bytes += ddp_bytes;
2120 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2121 mss);
2122 }
63d635b2
AD		 2123 if (!ddp_bytes) {
2124 dev_kfree_skb_any(skb);
f800326d 2125 continue;
63d635b2 2126 }
3d8fd385 2127 }
f800326d 2128
332d4a7d 2129#endif /* IXGBE_FCOE */
8a0da21b 2130 ixgbe_rx_skb(q_vector, skb);
9a799d71 2131
f800326d 2132 /* update budget accounting */
f4de00ed 2133 total_rx_packets++;
fdabfc8a 2134 }
9a799d71 2135
c267fc16
AD		 2136 u64_stats_update_begin(&rx_ring->syncp);
2137 rx_ring->stats.packets += total_rx_packets;
2138 rx_ring->stats.bytes += total_rx_bytes;
2139 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2140 q_vector->rx.total_packets += total_rx_packets;
2141 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2142
5a85e737 2143 return total_rx_packets;
9a799d71
AK		 2144}
2145
e0d1095a 2146#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2147/* must be called with local_bh_disable()d */
2148static int ixgbe_low_latency_recv(struct napi_struct *napi)
2149{
2150 struct ixgbe_q_vector *q_vector =
2151 container_of(napi, struct ixgbe_q_vector, napi);
2152 struct ixgbe_adapter *adapter = q_vector->adapter;
2153 struct ixgbe_ring *ring;
2154 int found = 0;
2155
2156 if (test_bit(__IXGBE_DOWN, &adapter->state))
2157 return LL_FLUSH_FAILED;
2158
2159 if (!ixgbe_qv_lock_poll(q_vector))
2160 return LL_FLUSH_BUSY;
2161
2162 ixgbe_for_each_ring(ring, q_vector->rx) {
2163 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2164#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2165 if (found)
2166 ring->stats.cleaned += found;
2167 else
2168 ring->stats.misses++;
2169#endif
5a85e737
ET		 2170 if (found)
2171 break;
2172 }
2173
2174 ixgbe_qv_unlock_poll(q_vector);
2175
2176 return found;
2177}
e0d1095a 2178#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2179
9a799d71
AK		 2180/**
2181 * ixgbe_configure_msix - Configure MSI-X hardware
2182 * @adapter: board private structure
2183 *
2184 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2185 * interrupts.
2186 **/
2187static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2188{
021230d4 2189 struct ixgbe_q_vector *q_vector;
49c7ffbe 2190 int v_idx;
021230d4 2191 u32 mask;
9a799d71 2192
8e34d1aa
AD		 2193 /* Populate MSIX to EITR Select */
2194 if (adapter->num_vfs > 32) {
2195 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2196 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2197 }
2198
4df10466
JB		 2199 /*
2200 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2201 * corresponding register.
2202 */
49c7ffbe 2203 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2204 struct ixgbe_ring *ring;
7a921c93 2205 q_vector = adapter->q_vector[v_idx];
021230d4 2206
a557928e 2207 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2208 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2209
a557928e 2210 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2211 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2212
fe49f04a 2213 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2214 }
2215
bd508178
AD		 2216 switch (adapter->hw.mac.type) {
2217 case ixgbe_mac_82598EB:
e8e26350 2218 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2219 v_idx);
bd508178
AD		 2220 break;
2221 case ixgbe_mac_82599EB:
b93a2226 2222 case ixgbe_mac_X540:
9a75a1ac
DS		 2223 case ixgbe_mac_X550:
2224 case ixgbe_mac_X550EM_x:
e8e26350 2225 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2226 break;
bd508178
AD		 2227 default:
2228 break;
2229 }
021230d4
AV		 2230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2231
41fb9248 2232 /* set up to autoclear timer, and the vectors */
021230d4 2233 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2234 mask &= ~(IXGBE_EIMS_OTHER |
2235 IXGBE_EIMS_MAILBOX |
2236 IXGBE_EIMS_LSC);
2237
021230d4 2238 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2239}
2240
f494e8fa
AV		 2241enum latency_range {
2242 lowest_latency = 0,
2243 low_latency = 1,
2244 bulk_latency = 2,
2245 latency_invalid = 255
2246};
2247
2248/**
2249 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2250 * @q_vector: structure containing interrupt and ring information
2251 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2252 *
2253 * Stores a new ITR value based on packets and byte
2254 * counts during the last interrupt. The advantage of per interrupt
2255 * computation is faster updates and more accurate ITR for the current
2256 * traffic pattern. Constants in this function were computed
2257 * based on theoretical maximum wire speed and thresholds were set based
2258 * on testing data as well as attempting to minimize response time
2259 * while increasing bulk throughput.
2260 * this functionality is controlled by the InterruptThrottleRate module
2261 * parameter (see ixgbe_param.c)
2262 **/
bd198058
AD		 2263static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2264 struct ixgbe_ring_container *ring_container)
f494e8fa 2265{
bd198058
AD		 2266 int bytes = ring_container->total_bytes;
2267 int packets = ring_container->total_packets;
2268 u32 timepassed_us;
621bd70e 2269 u64 bytes_perint;
bd198058 2270 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2271
2272 if (packets == 0)
bd198058 2273 return;
f494e8fa
AV		 2274
2275 /* simple throttlerate management
621bd70e
AD		 2276 * 0-10MB/s lowest (100000 ints/s)
2277 * 10-20MB/s low (20000 ints/s)
8ac34f10 2278 * 20-1249MB/s bulk (12000 ints/s)
f494e8fa
AV		 2279 */
2280 /* what was last interrupt timeslice? */
d5bf4f67 2281 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2282 if (timepassed_us == 0)
2283 return;
2284
f494e8fa
AV		 2285 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2286
2287 switch (itr_setting) {
2288 case lowest_latency:
621bd70e 2289 if (bytes_perint > 10)
bd198058 2290 itr_setting = low_latency;
f494e8fa
AV		 2291 break;
2292 case low_latency:
621bd70e 2293 if (bytes_perint > 20)
bd198058 2294 itr_setting = bulk_latency;
621bd70e 2295 else if (bytes_perint <= 10)
bd198058 2296 itr_setting = lowest_latency;
f494e8fa
AV		 2297 break;
2298 case bulk_latency:
621bd70e 2299 if (bytes_perint <= 20)
bd198058 2300 itr_setting = low_latency;
f494e8fa
AV		 2301 break;
2302 }
2303
bd198058
AD		 2304 /* clear work counters since we have the values we need */
2305 ring_container->total_bytes = 0;
2306 ring_container->total_packets = 0;
2307
2308 /* write updated itr to ring container */
2309 ring_container->itr = itr_setting;
f494e8fa
AV		 2310}
2311
509ee935
JB		 2312/**
2313 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2314 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2315 *
2316 * This function is made to be called by ethtool and by the driver
2317 * when it needs to update EITR registers at runtime. Hardware
2318 * specific quirks/differences are taken care of here.
2319 */
fe49f04a 2320void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2321{
fe49f04a 2322 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2323 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2324 int v_idx = q_vector->v_idx;
5d967eb7 2325 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2326
bd508178
AD		 2327 switch (adapter->hw.mac.type) {
2328 case ixgbe_mac_82598EB:
509ee935
JB		 2329 /* must write high and low 16 bits to reset counter */
2330 itr_reg |= (itr_reg << 16);
bd508178
AD		 2331 break;
2332 case ixgbe_mac_82599EB:
b93a2226 2333 case ixgbe_mac_X540:
9a75a1ac
DS		 2334 case ixgbe_mac_X550:
2335 case ixgbe_mac_X550EM_x:
509ee935
JB		 2336 /*
2337 * set the WDIS bit to not clear the timer bits and cause an
2338 * immediate assertion of the interrupt
2339 */
2340 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2341 break;
2342 default:
2343 break;
509ee935
JB		 2344 }
2345 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2346}
2347
bd198058 2348static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2349{
d5bf4f67 2350 u32 new_itr = q_vector->itr;
bd198058 2351 u8 current_itr;
f494e8fa 2352
bd198058
AD		 2353 ixgbe_update_itr(q_vector, &q_vector->tx);
2354 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2355
08c8833b 2356 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2357
2358 switch (current_itr) {
2359 /* counts and packets in update_itr are dependent on these numbers */
2360 case lowest_latency:
d5bf4f67 2361 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2362 break;
2363 case low_latency:
d5bf4f67 2364 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2365 break;
2366 case bulk_latency:
8ac34f10 2367 new_itr = IXGBE_12K_ITR;
f494e8fa 2368 break;
bd198058
AD		 2369 default:
2370 break;
f494e8fa
AV		 2371 }
2372
d5bf4f67 2373 if (new_itr != q_vector->itr) {
fe49f04a 2374 /* do an exponential smoothing */
d5bf4f67
ET		 2375 new_itr = (10 * new_itr * q_vector->itr) /
2376 ((9 * new_itr) + q_vector->itr);
509ee935 2377
bd198058 2378 /* save the algorithm value here */
5d967eb7 2379 q_vector->itr = new_itr;
fe49f04a
AD		 2380
2381 ixgbe_write_eitr(q_vector);
f494e8fa 2382 }
f494e8fa
AV		 2383}
2384
119fc60a 2385/**
de88eeeb 2386 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2387 * @adapter: pointer to adapter
119fc60a 2388 **/
f0f9778d 2389static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2390{
119fc60a
MC		 2391 struct ixgbe_hw *hw = &adapter->hw;
2392 u32 eicr = adapter->interrupt_event;
2393
f0f9778d 2394 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2395 return;
2396
f0f9778d
AD		 2397 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2398 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2399 return;
2400
2401 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2402
7ca647bd 2403 switch (hw->device_id) {
f0f9778d
AD		 2404 case IXGBE_DEV_ID_82599_T3_LOM:
2405 /*
2406 * Since the warning interrupt is for both ports
2407 * we don't have to check if:
2408 * - This interrupt wasn't for our port.
2409 * - We may have missed the interrupt so always have to
2410 * check if we got a LSC
2411 */
9a900eca 2412 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2413 !(eicr & IXGBE_EICR_LSC))
2414 return;
2415
2416 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2417 u32 speed;
f0f9778d 2418 bool link_up = false;
7ca647bd 2419
3d292265 2420 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2421
f0f9778d
AD		 2422 if (link_up)
2423 return;
2424 }
2425
2426 /* Check if this is not due to overtemp */
2427 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2428 return;
2429
2430 break;
7ca647bd 2431 default:
597f22d6
DS		 2432 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2433 return;
9a900eca 2434 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2435 return;
7ca647bd 2436 break;
119fc60a 2437 }
f44e751b 2438 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2439
2440 adapter->interrupt_event = 0;
119fc60a
MC		 2441}
2442
0befdb3e
JB		 2443static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2444{
2445 struct ixgbe_hw *hw = &adapter->hw;
2446
2447 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2448 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2449 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2450 /* write to clear the interrupt */
9a900eca 2451 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2452 }
2453}
cf8280ee 2454
4f51bf70
JK		 2455static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2456{
9a900eca
DS		 2457 struct ixgbe_hw *hw = &adapter->hw;
2458
4f51bf70
JK		 2459 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2460 return;
2461
2462 switch (adapter->hw.mac.type) {
2463 case ixgbe_mac_82599EB:
2464 /*
2465 * Need to check link state so complete overtemp check
2466 * on service task
2467 */
9a900eca
DS		 2468 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2469 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2470 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2471 adapter->interrupt_event = eicr;
2472 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2473 ixgbe_service_event_schedule(adapter);
2474 return;
2475 }
2476 return;
2477 case ixgbe_mac_X540:
2478 if (!(eicr & IXGBE_EICR_TS))
2479 return;
2480 break;
2481 default:
2482 return;
2483 }
2484
f44e751b 2485 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2486}
2487
45788d2a
DS		 2488static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2489{
2490 switch (hw->mac.type) {
2491 case ixgbe_mac_82598EB:
2492 if (hw->phy.type == ixgbe_phy_nl)
2493 return true;
2494 return false;
2495 case ixgbe_mac_82599EB:
2496 case ixgbe_mac_X550EM_x:
2497 switch (hw->mac.ops.get_media_type(hw)) {
2498 case ixgbe_media_type_fiber:
2499 case ixgbe_media_type_fiber_qsfp:
2500 return true;
2501 default:
2502 return false;
2503 }
2504 default:
2505 return false;
2506 }
2507}
2508
e8e26350
PW		 2509static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2510{
2511 struct ixgbe_hw *hw = &adapter->hw;
4ccc650c 2512 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
e8e26350 2513
4ccc650c
DS		 2514 if (!ixgbe_is_sfp(hw))
2515 return;
2516
2517 /* Later MAC's use different SDP */
2518 if (hw->mac.type >= ixgbe_mac_X540)
2519 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2520
2521 if (eicr & eicr_mask) {
73c4b7cd 2522 /* Clear the interrupt */
4ccc650c 2523 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
7086400d
AD		 2524 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2525 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 2526 adapter->sfp_poll_time = 0;
7086400d
AD		 2527 ixgbe_service_event_schedule(adapter);
2528 }
73c4b7cd
AD		 2529 }
2530
4ccc650c
DS		 2531 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2532 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
e8e26350 2533 /* Clear the interrupt */
9a900eca 2534 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2535 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2536 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2537 ixgbe_service_event_schedule(adapter);
2538 }
e8e26350
PW		 2539 }
2540}
2541
cf8280ee
JB		 2542static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2543{
2544 struct ixgbe_hw *hw = &adapter->hw;
2545
2546 adapter->lsc_int++;
2547 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2548 adapter->link_check_timeout = jiffies;
2549 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2550 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2551 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2552 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2553 }
2554}
2555
fe49f04a
AD		 2556static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2557 u64 qmask)
2558{
2559 u32 mask;
bd508178 2560 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2561
bd508178
AD		 2562 switch (hw->mac.type) {
2563 case ixgbe_mac_82598EB:
fe49f04a 2564 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2565 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2566 break;
2567 case ixgbe_mac_82599EB:
b93a2226 2568 case ixgbe_mac_X540:
9a75a1ac
DS		 2569 case ixgbe_mac_X550:
2570 case ixgbe_mac_X550EM_x:
fe49f04a 2571 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2572 if (mask)
2573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2574 mask = (qmask >> 32);
bd508178
AD		 2575 if (mask)
2576 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2577 break;
2578 default:
2579 break;
fe49f04a
AD		 2580 }
2581 /* skip the flush */
2582}
2583
2584static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2585 u64 qmask)
fe49f04a
AD		 2586{
2587 u32 mask;
bd508178 2588 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2589
bd508178
AD		 2590 switch (hw->mac.type) {
2591 case ixgbe_mac_82598EB:
fe49f04a 2592 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2593 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2594 break;
2595 case ixgbe_mac_82599EB:
b93a2226 2596 case ixgbe_mac_X540:
9a75a1ac
DS		 2597 case ixgbe_mac_X550:
2598 case ixgbe_mac_X550EM_x:
fe49f04a 2599 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2600 if (mask)
2601 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2602 mask = (qmask >> 32);
bd508178
AD		 2603 if (mask)
2604 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2605 break;
2606 default:
2607 break;
fe49f04a
AD		 2608 }
2609 /* skip the flush */
2610}
2611
021230d4 2612/**
2c4af694
AD		 2613 * ixgbe_irq_enable - Enable default interrupt generation settings
2614 * @adapter: board private structure
021230d4 2615 **/
2c4af694
AD		 2616static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2617 bool flush)
9a799d71 2618{
9a900eca 2619 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2620 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2621
2c4af694
AD		 2622 /* don't reenable LSC while waiting for link */
2623 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2624 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2625
2c4af694 2626 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2627 switch (adapter->hw.mac.type) {
2628 case ixgbe_mac_82599EB:
9a900eca 2629 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2630 break;
2631 case ixgbe_mac_X540:
9a75a1ac
DS		 2632 case ixgbe_mac_X550:
2633 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2634 mask |= IXGBE_EIMS_TS;
2635 break;
2636 default:
2637 break;
2638 }
2c4af694 2639 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2640 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2641 switch (adapter->hw.mac.type) {
2642 case ixgbe_mac_82599EB:
9a900eca
DS		 2643 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2644 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2645 /* fall through */
858bc081 2646 case ixgbe_mac_X540:
9a75a1ac
DS		 2647 case ixgbe_mac_X550:
2648 case ixgbe_mac_X550EM_x:
cbd45ec7
MR		 2649 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2650 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
597f22d6
DS		 2651 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2652 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2653 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2654 mask |= IXGBE_EIMS_MAILBOX;
2655 break;
2656 default:
2657 break;
9a799d71 2658 }
db0677fa 2659
2c4af694
AD		 2660 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2661 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2662 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2663
2c4af694
AD		 2664 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2665 if (queues)
2666 ixgbe_irq_enable_queues(adapter, ~0);
2667 if (flush)
2668 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2669}
2670
2c4af694 2671static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2672{
a65151ba 2673 struct ixgbe_adapter *adapter = data;
9a799d71 2674 struct ixgbe_hw *hw = &adapter->hw;
54037505 2675 u32 eicr;
91281fd3 2676
54037505
DS		 2677 /*
2678 * Workaround for Silicon errata. Use clear-by-write instead
2679 * of clear-by-read. Reading with EICS will return the
2680 * interrupt causes without clearing, which later be done
2681 * with the write to EICR.
2682 */
2683 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2684
2685 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2686 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2687 * the bits are high when ixgbe_msix_other is called. There is a race
2688 * condition otherwise which results in possible performance loss
2689 * especially if the ixgbe_msix_other interrupt is triggering
2690 * consistently (as it would when PPS is turned on for the X540 device)
2691 */
2692 eicr &= 0xFFFF0000;
2693
54037505 2694 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2695
cf8280ee
JB		 2696 if (eicr & IXGBE_EICR_LSC)
2697 ixgbe_check_lsc(adapter);
f0848276 2698
1cdd1ec8
GR		 2699 if (eicr & IXGBE_EICR_MAILBOX)
2700 ixgbe_msg_task(adapter);
efe3d3c8 2701
bd508178
AD		 2702 switch (hw->mac.type) {
2703 case ixgbe_mac_82599EB:
b93a2226 2704 case ixgbe_mac_X540:
9a75a1ac
DS		 2705 case ixgbe_mac_X550:
2706 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2707 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2708 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2709 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2710 ixgbe_service_event_schedule(adapter);
2711 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2712 IXGBE_EICR_GPI_SDP0_X540);
2713 }
d773ce2d
DS		 2714 if (eicr & IXGBE_EICR_ECC) {
2715 e_info(link, "Received ECC Err, initiating reset\n");
2716 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2717 ixgbe_service_event_schedule(adapter);
2718 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2719 }
c4cf55e5
PWJ		 2720 /* Handle Flow Director Full threshold interrupt */
2721 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2722 int reinit_count = 0;
c4cf55e5 2723 int i;
c4cf55e5 2724 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2725 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2726 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2727 &ring->state))
2728 reinit_count++;
2729 }
2730 if (reinit_count) {
2731 /* no more flow director interrupts until after init */
2732 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2733 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2734 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2735 }
2736 }
f0f9778d 2737 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2738 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2739 break;
2740 default:
2741 break;
c4cf55e5 2742 }
f0848276 2743
bd508178 2744 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2745
db0677fa 2746 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2747 ixgbe_ptp_check_pps_event(adapter);
efe3d3c8 2748
7086400d 2749 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2751 ixgbe_irq_enable(adapter, false, false);
f0848276 2752
9a799d71 2753 return IRQ_HANDLED;
f0848276 2754}
91281fd3 2755
4ff7fb12 2756static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2757{
021230d4 2758 struct ixgbe_q_vector *q_vector = data;
91281fd3 2759
9b471446 2760 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2761
4ff7fb12 2762 if (q_vector->rx.ring || q_vector->tx.ring)
ef2662b2 2763 napi_schedule_irqoff(&q_vector->napi);
91281fd3 2764
9a799d71 2765 return IRQ_HANDLED;
91281fd3
AD		 2766}
2767
eb01b975
AD		 2768/**
2769 * ixgbe_poll - NAPI Rx polling callback
2770 * @napi: structure for representing this polling device
2771 * @budget: how many packets driver is allowed to clean
2772 *
2773 * This function is used for legacy and MSI, NAPI mode
2774 **/
8af3c33f 2775int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2776{
2777 struct ixgbe_q_vector *q_vector =
2778 container_of(napi, struct ixgbe_q_vector, napi);
2779 struct ixgbe_adapter *adapter = q_vector->adapter;
2780 struct ixgbe_ring *ring;
32b3e08f 2781 int per_ring_budget, work_done = 0;
eb01b975
AD		 2782 bool clean_complete = true;
2783
2784#ifdef CONFIG_IXGBE_DCA
2785 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2786 ixgbe_update_dca(q_vector);
2787#endif
2788
2789 ixgbe_for_each_ring(ring, q_vector->tx)
a3a8749d 2790 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring, budget);
eb01b975 2791
5d6002b7
AD		 2792 /* Exit if we are called by netpoll or busy polling is active */
2793 if ((budget <= 0) || !ixgbe_qv_lock_napi(q_vector))
5a85e737
ET		 2794 return budget;
2795
eb01b975
AD		 2796 /* attempt to distribute budget to each queue fairly, but don't allow
2797 * the budget to go below 1 because we'll exit polling */
2798 if (q_vector->rx.count > 1)
2799 per_ring_budget = max(budget/q_vector->rx.count, 1);
2800 else
2801 per_ring_budget = budget;
2802
32b3e08f
JB		 2803 ixgbe_for_each_ring(ring, q_vector->rx) {
2804 int cleaned = ixgbe_clean_rx_irq(q_vector, ring,
2805 per_ring_budget);
2806
2807 work_done += cleaned;
2808 clean_complete &= (cleaned < per_ring_budget);
2809 }
eb01b975 2810
5a85e737 2811 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2812 /* If all work not completed, return budget and keep polling */
2813 if (!clean_complete)
2814 return budget;
2815
2816 /* all work done, exit the polling mode */
32b3e08f 2817 napi_complete_done(napi, work_done);
eb01b975
AD		 2818 if (adapter->rx_itr_setting & 1)
2819 ixgbe_set_itr(q_vector);
2820 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2821 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2822
2823 return 0;
2824}
2825
021230d4
AV		 2826/**
2827 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2828 * @adapter: board private structure
2829 *
2830 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2831 * interrupts from the kernel.
2832 **/
2833static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2834{
2835 struct net_device *netdev = adapter->netdev;
207867f5 2836 int vector, err;
e8e9f696 2837 int ri = 0, ti = 0;
021230d4 2838
49c7ffbe 2839 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2840 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2841 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2842
4ff7fb12 2843 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2844 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2845 "%s-%s-%d", netdev->name, "TxRx", ri++);
2846 ti++;
2847 } else if (q_vector->rx.ring) {
9fe93afd 2848 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2849 "%s-%s-%d", netdev->name, "rx", ri++);
2850 } else if (q_vector->tx.ring) {
9fe93afd 2851 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2852 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2853 } else {
2854 /* skip this unused q_vector */
2855 continue;
32aa77a4 2856 }
207867f5
AD		 2857 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2858 q_vector->name, q_vector);
9a799d71 2859 if (err) {
396e799c 2860 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2861 "Error: %d\n", err);
021230d4 2862 goto free_queue_irqs;
9a799d71 2863 }
207867f5
AD		 2864 /* If Flow Director is enabled, set interrupt affinity */
2865 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2866 /* assign the mask for this irq */
2867 irq_set_affinity_hint(entry->vector,
de88eeeb 2868 &q_vector->affinity_mask);
207867f5 2869 }
9a799d71
AK		 2870 }
2871
021230d4 2872 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2873 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2874 if (err) {
de88eeeb 2875 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2876 goto free_queue_irqs;
9a799d71
AK		 2877 }
2878
9a799d71
AK		 2879 return 0;
2880
021230d4 2881free_queue_irqs:
207867f5
AD		 2882 while (vector) {
2883 vector--;
2884 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2885 NULL);
2886 free_irq(adapter->msix_entries[vector].vector,
2887 adapter->q_vector[vector]);
2888 }
021230d4
AV		 2889 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2890 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2891 kfree(adapter->msix_entries);
2892 adapter->msix_entries = NULL;
9a799d71
AK		 2893 return err;
2894}
2895
2896/**
021230d4 2897 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2898 * @irq: interrupt number
2899 * @data: pointer to a network interface device structure
9a799d71
AK		 2900 **/
2901static irqreturn_t ixgbe_intr(int irq, void *data)
2902{
a65151ba 2903 struct ixgbe_adapter *adapter = data;
9a799d71 2904 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2905 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2906 u32 eicr;
2907
54037505 2908 /*
24ddd967 2909 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2910 * before the read of EICR.
2911 */
2912 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2913
021230d4 2914 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2915 * therefore no explicit interrupt disable is necessary */
021230d4 2916 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2917 if (!eicr) {
6af3b9eb
ET		 2918 /*
2919 * shared interrupt alert!
f47cf66e 2920 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2921 * have disabled interrupts due to EIAM
2922 * finish the workaround of silicon errata on 82598. Unmask
2923 * the interrupt that we masked before the EICR read.
2924 */
2925 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2926 ixgbe_irq_enable(adapter, true, true);
9a799d71 2927 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2928 }
9a799d71 2929
cf8280ee
JB		 2930 if (eicr & IXGBE_EICR_LSC)
2931 ixgbe_check_lsc(adapter);
021230d4 2932
bd508178
AD		 2933 switch (hw->mac.type) {
2934 case ixgbe_mac_82599EB:
e8e26350 2935 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2936 /* Fall through */
2937 case ixgbe_mac_X540:
9a75a1ac
DS		 2938 case ixgbe_mac_X550:
2939 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2940 if (eicr & IXGBE_EICR_ECC) {
2941 e_info(link, "Received ECC Err, initiating reset\n");
2942 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2943 ixgbe_service_event_schedule(adapter);
2944 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2945 }
4f51bf70 2946 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2947 break;
2948 default:
2949 break;
2950 }
e8e26350 2951
0befdb3e 2952 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2953 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
a9763f3c 2954 ixgbe_ptp_check_pps_event(adapter);
0befdb3e 2955
b9f6ed2b 2956 /* would disable interrupts here but EIAM disabled it */
ef2662b2 2957 napi_schedule_irqoff(&q_vector->napi);
9a799d71 2958
6af3b9eb
ET		 2959 /*
2960 * re-enable link(maybe) and non-queue interrupts, no flush.
2961 * ixgbe_poll will re-enable the queue interrupts
2962 */
6af3b9eb
ET		 2963 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2964 ixgbe_irq_enable(adapter, false, false);
2965
9a799d71
AK		 2966 return IRQ_HANDLED;
2967}
2968
2969/**
2970 * ixgbe_request_irq - initialize interrupts
2971 * @adapter: board private structure
2972 *
2973 * Attempts to configure interrupts using the best available
2974 * capabilities of the hardware and kernel.
2975 **/
021230d4 2976static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2977{
2978 struct net_device *netdev = adapter->netdev;
021230d4 2979 int err;
9a799d71 2980
4cc6df29 2981 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2982 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2983 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2984 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2985 netdev->name, adapter);
4cc6df29 2986 else
a0607fd3 2987 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2988 netdev->name, adapter);
9a799d71 2989
de88eeeb 2990 if (err)
396e799c 2991 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2992
9a799d71
AK		 2993 return err;
2994}
2995
2996static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2997{
49c7ffbe 2998 int vector;
9a799d71 2999
49c7ffbe
AD		 3000 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3001 free_irq(adapter->pdev->irq, adapter);
3002 return;
3003 }
4cc6df29 3004
49c7ffbe
AD		 3005 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3006 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3007 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3008
49c7ffbe
AD		 3009 /* free only the irqs that were actually requested */
3010 if (!q_vector->rx.ring && !q_vector->tx.ring)
3011 continue;
207867f5 3012
49c7ffbe
AD		 3013 /* clear the affinity_mask in the IRQ descriptor */
3014 irq_set_affinity_hint(entry->vector, NULL);
3015
3016 free_irq(entry->vector, q_vector);
9a799d71 3017 }
49c7ffbe
AD		 3018
3019 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3020}
3021
22d5a71b
JB		 3022/**
3023 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3024 * @adapter: board private structure
3025 **/
3026static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3027{
bd508178
AD		 3028 switch (adapter->hw.mac.type) {
3029 case ixgbe_mac_82598EB:
835462fc 3030 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3031 break;
3032 case ixgbe_mac_82599EB:
b93a2226 3033 case ixgbe_mac_X540:
9a75a1ac
DS		 3034 case ixgbe_mac_X550:
3035 case ixgbe_mac_X550EM_x:
835462fc
NS		 3036 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3037 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3038 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3039 break;
3040 default:
3041 break;
22d5a71b
JB		 3042 }
3043 IXGBE_WRITE_FLUSH(&adapter->hw);
3044 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3045 int vector;
3046
3047 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3048 synchronize_irq(adapter->msix_entries[vector].vector);
3049
3050 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3051 } else {
3052 synchronize_irq(adapter->pdev->irq);
3053 }
3054}
3055
9a799d71
AK		 3056/**
3057 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3058 *
3059 **/
3060static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3061{
d5bf4f67 3062 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3063
d5bf4f67 3064 ixgbe_write_eitr(q_vector);
9a799d71 3065
e8e26350
PW		 3066 ixgbe_set_ivar(adapter, 0, 0, 0);
3067 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3068
396e799c 3069 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3070}
3071
43e69bf0
AD		 3072/**
3073 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3074 * @adapter: board private structure
3075 * @ring: structure containing ring specific data
3076 *
3077 * Configure the Tx descriptor ring after a reset.
3078 **/
84418e3b
AD		 3079void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3080 struct ixgbe_ring *ring)
43e69bf0
AD		 3081{
3082 struct ixgbe_hw *hw = &adapter->hw;
3083 u64 tdba = ring->dma;
2f1860b8 3084 int wait_loop = 10;
b88c6de2 3085 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3086 u8 reg_idx = ring->reg_idx;
43e69bf0 3087
2f1860b8 3088 /* disable queue to avoid issues while updating state */
b88c6de2 3089 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3090 IXGBE_WRITE_FLUSH(hw);
3091
43e69bf0 3092 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3093 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3094 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3095 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3096 ring->count * sizeof(union ixgbe_adv_tx_desc));
3097 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3098 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3099 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3100
b88c6de2
AD		 3101 /*
3102 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3103 * higher than 1 when:
3104 * - ITR is 0 as it could cause false TX hangs
3105 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3106 *
3107 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3108 * to or less than the number of on chip descriptors, which is
3109 * currently 40.
3110 */
67da097e 3111 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3112 txdctl |= (1 << 16); /* WTHRESH = 1 */
3113 else
3114 txdctl |= (8 << 16); /* WTHRESH = 8 */
3115
e954b374
AD		 3116 /*
3117 * Setting PTHRESH to 32 both improves performance
3118 * and avoids a TX hang with DFP enabled
3119 */
b88c6de2
AD		 3120 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3121 32; /* PTHRESH = 32 */
2f1860b8
AD		 3122
3123 /* reinitialize flowdirector state */
39cb681b 3124 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3125 ring->atr_sample_rate = adapter->atr_sample_rate;
3126 ring->atr_count = 0;
3127 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3128 } else {
3129 ring->atr_sample_rate = 0;
3130 }
2f1860b8 3131
fd786b7b
AD		 3132 /* initialize XPS */
3133 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3134 struct ixgbe_q_vector *q_vector = ring->q_vector;
3135
3136 if (q_vector)
2a47fa45 3137 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3138 &q_vector->affinity_mask,
3139 ring->queue_index);
3140 }
3141
c84d324c
JF		 3142 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3143
2f1860b8 3144 /* enable queue */
2f1860b8
AD		 3145 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3146
3147 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3148 if (hw->mac.type == ixgbe_mac_82598EB &&
3149 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3150 return;
3151
3152 /* poll to verify queue is enabled */
3153 do {
032b4325 3154 usleep_range(1000, 2000);
2f1860b8
AD		 3155 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3156 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3157 if (!wait_loop)
3158 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3159}
3160
120ff942
AD		 3161static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3162{
3163 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3164 u32 rttdcs, mtqc;
8b1c0b24 3165 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3166
3167 if (hw->mac.type == ixgbe_mac_82598EB)
3168 return;
3169
3170 /* disable the arbiter while setting MTQC */
3171 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3172 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3173 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3174
3175 /* set transmit pool layout */
671c0adb
AD		 3176 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3177 mtqc = IXGBE_MTQC_VT_ENA;
3178 if (tcs > 4)
3179 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3180 else if (tcs > 1)
3181 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3182 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3183 mtqc |= IXGBE_MTQC_32VF;
3184 else
3185 mtqc |= IXGBE_MTQC_64VF;
3186 } else {
3187 if (tcs > 4)
3188 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3189 else if (tcs > 1)
3190 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3191 else
671c0adb
AD		 3192 mtqc = IXGBE_MTQC_64Q_1PB;
3193 }
120ff942 3194
671c0adb 3195 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3196
671c0adb
AD		 3197 /* Enable Security TX Buffer IFG for multiple pb */
3198 if (tcs) {
3199 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3200 sectx |= IXGBE_SECTX_DCB;
3201 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3202 }
3203
3204 /* re-enable the arbiter */
3205 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3206 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3207}
3208
9a799d71 3209/**
3a581073 3210 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3211 * @adapter: board private structure
3212 *
3213 * Configure the Tx unit of the MAC after a reset.
3214 **/
3215static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3216{
2f1860b8
AD		 3217 struct ixgbe_hw *hw = &adapter->hw;
3218 u32 dmatxctl;
43e69bf0 3219 u32 i;
9a799d71 3220
2f1860b8
AD		 3221 ixgbe_setup_mtqc(adapter);
3222
3223 if (hw->mac.type != ixgbe_mac_82598EB) {
3224 /* DMATXCTL.EN must be before Tx queues are enabled */
3225 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3226 dmatxctl |= IXGBE_DMATXCTL_TE;
3227 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3228 }
3229
9a799d71 3230 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3231 for (i = 0; i < adapter->num_tx_queues; i++)
3232 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3233}
3234
3ebe8fde
AD		 3235static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3236 struct ixgbe_ring *ring)
3237{
3238 struct ixgbe_hw *hw = &adapter->hw;
3239 u8 reg_idx = ring->reg_idx;
3240 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3241
3242 srrctl |= IXGBE_SRRCTL_DROP_EN;
3243
3244 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3245}
3246
3247static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3248 struct ixgbe_ring *ring)
3249{
3250 struct ixgbe_hw *hw = &adapter->hw;
3251 u8 reg_idx = ring->reg_idx;
3252 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3253
3254 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3255
3256 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3257}
3258
3259#ifdef CONFIG_IXGBE_DCB
3260void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3261#else
3262static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3263#endif
3264{
3265 int i;
3266 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3267
3268 if (adapter->ixgbe_ieee_pfc)
3269 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3270
3271 /*
3272 * We should set the drop enable bit if:
3273 * SR-IOV is enabled
3274 * or
3275 * Number of Rx queues > 1 and flow control is disabled
3276 *
3277 * This allows us to avoid head of line blocking for security
3278 * and performance reasons.
3279 */
3280 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3281 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3282 for (i = 0; i < adapter->num_rx_queues; i++)
3283 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3284 } else {
3285 for (i = 0; i < adapter->num_rx_queues; i++)
3286 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3287 }
3288}
3289
e8e26350 3290#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3291
a6616b42 3292static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3293 struct ixgbe_ring *rx_ring)
cc41ac7c 3294{
45e9baa5 3295 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3296 u32 srrctl;
bf29ee6c 3297 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3298
45e9baa5
AD		 3299 if (hw->mac.type == ixgbe_mac_82598EB) {
3300 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3301
45e9baa5
AD		 3302 /*
3303 * if VMDq is not active we must program one srrctl register
3304 * per RSS queue since we have enabled RDRXCTL.MVMEN
3305 */
3306 reg_idx &= mask;
3307 }
cc41ac7c 3308
45e9baa5
AD		 3309 /* configure header buffer length, needed for RSC */
3310 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3311
45e9baa5 3312 /* configure the packet buffer length */
f800326d 3313 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3314
3315 /* configure descriptor type */
f800326d 3316 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3317
45e9baa5 3318 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3319}
9a799d71 3320
dfaf891d 3321/**
a897a2ad 3322 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
dfaf891d
VZ		 3323 * @adapter: device handle
3324 *
3325 * - 82598/82599/X540: 128
3326 * - X550(non-SRIOV mode): 512
3327 * - X550(SRIOV mode): 64
3328 */
7f276efb 3329u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3330{
3331 if (adapter->hw.mac.type < ixgbe_mac_X550)
3332 return 128;
3333 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3334 return 64;
3335 else
3336 return 512;
3337}
3338
3339/**
a897a2ad 3340 * ixgbe_store_reta - Write the RETA table to HW
dfaf891d
VZ		 3341 * @adapter: device handle
3342 *
3343 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3344 */
1c7cf078 3345void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3346{
dfaf891d 3347 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3348 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3349 u32 reta = 0;
dfaf891d
VZ		 3350 u32 indices_multi;
3351 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3352
0f9b232b 3353 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3354 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3355 * indices.
3356 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3357 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3358 */
3359 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3360 indices_multi = 0x11;
3361 else
3362 indices_multi = 0x1;
3363
dfaf891d
VZ		 3364 /* Write redirection table to HW */
3365 for (i = 0; i < reta_entries; i++) {
3366 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3367 if ((i & 3) == 3) {
3368 if (i < 128)
3369 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3370 else
3371 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3372 reta);
dfaf891d 3373 reta = 0;
0f9b232b
DS		 3374 }
3375 }
3376}
3377
dfaf891d 3378/**
a897a2ad 3379 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
dfaf891d
VZ		 3380 * @adapter: device handle
3381 *
3382 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3383 */
3384static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3385{
dfaf891d 3386 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3387 struct ixgbe_hw *hw = &adapter->hw;
3388 u32 vfreta = 0;
dfaf891d
VZ		 3389 unsigned int pf_pool = adapter->num_vfs;
3390
3391 /* Write redirection table to HW */
3392 for (i = 0; i < reta_entries; i++) {
3393 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3394 if ((i & 3) == 3) {
3395 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3396 vfreta);
3397 vfreta = 0;
3398 }
3399 }
3400}
3401
3402static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3403{
3404 struct ixgbe_hw *hw = &adapter->hw;
3405 u32 i, j;
3406 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3407 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3408
3409 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3410 * make full use of any rings they may have. We will use the
3411 * PSRTYPE register to control how many rings we use within the PF.
3412 */
3413 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3414 rss_i = 2;
3415
3416 /* Fill out hash function seeds */
3417 for (i = 0; i < 10; i++)
3418 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3419
3420 /* Fill out redirection table */
3421 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3422
3423 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3424 if (j == rss_i)
3425 j = 0;
3426
3427 adapter->rss_indir_tbl[i] = j;
3428 }
3429
3430 ixgbe_store_reta(adapter);
3431}
3432
3433static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3434{
3435 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3436 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3437 unsigned int pf_pool = adapter->num_vfs;
3438 int i, j;
3439
3440 /* Fill out hash function seeds */
3441 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3442 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3443 adapter->rss_key[i]);
0f9b232b
DS		 3444
3445 /* Fill out the redirection table */
3446 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3447 if (j == rss_i)
05abb126 3448 j = 0;
dfaf891d
VZ		 3449
3450 adapter->rss_indir_tbl[i] = j;
05abb126 3451 }
dfaf891d
VZ		 3452
3453 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3454}
3455
3456static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3457{
3458 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3459 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3460 u32 rxcsum;
0cefafad 3461
05abb126
AD		 3462 /* Disable indicating checksum in descriptor, enables RSS hash */
3463 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3464 rxcsum |= IXGBE_RXCSUM_PCSD;
3465 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3466
671c0adb 3467 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3468 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3469 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3470 } else {
671c0adb
AD		 3471 u8 tcs = netdev_get_num_tc(adapter->netdev);
3472
3473 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3474 if (tcs > 4)
3475 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3476 else if (tcs > 1)
3477 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3478 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3479 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3480 else
671c0adb
AD		 3481 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3482 } else {
3483 if (tcs > 4)
8b1c0b24 3484 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3485 else if (tcs > 1)
3486 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3487 else
3488 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3489 }
0cefafad
JB		 3490 }
3491
05abb126 3492 /* Perform hash on these packet types */
d1b849b9
DS		 3493 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3494 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3495 IXGBE_MRQC_RSS_FIELD_IPV6 |
3496 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3497
ef6afc0c 3498 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3499 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3500 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3501 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3502
dfaf891d 3503 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3504 if ((hw->mac.type >= ixgbe_mac_X550) &&
3505 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3506 unsigned int pf_pool = adapter->num_vfs;
3507
3508 /* Enable VF RSS mode */
3509 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3510 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3511
3512 /* Setup RSS through the VF registers */
dfaf891d 3513 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3514 vfmrqc = IXGBE_MRQC_RSSEN;
3515 vfmrqc |= rss_field;
3516 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3517 } else {
dfaf891d 3518 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3519 mrqc |= rss_field;
3520 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3521 }
0cefafad
JB		 3522}
3523
bb5a9ad2
NS		 3524/**
3525 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3526 * @adapter: address of board private structure
3527 * @index: index of ring to set
bb5a9ad2 3528 **/
082757af 3529static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3530 struct ixgbe_ring *ring)
bb5a9ad2 3531{
bb5a9ad2 3532 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3533 u32 rscctrl;
bf29ee6c 3534 u8 reg_idx = ring->reg_idx;
7367096a 3535
7d637bcc 3536 if (!ring_is_rsc_enabled(ring))
7367096a 3537 return;
bb5a9ad2 3538
7367096a 3539 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3540 rscctrl |= IXGBE_RSCCTL_RSCEN;
3541 /*
3542 * we must limit the number of descriptors so that the
3543 * total size of max desc * buf_len is not greater
642c680e 3544 * than 65536
bb5a9ad2 3545 */
f800326d 3546 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3547 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3548}
3549
9e10e045
AD		 3550#define IXGBE_MAX_RX_DESC_POLL 10
3551static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3552 struct ixgbe_ring *ring)
3553{
3554 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3555 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3556 u32 rxdctl;
bf29ee6c 3557 u8 reg_idx = ring->reg_idx;
9e10e045 3558
b0483c8f
MR		 3559 if (ixgbe_removed(hw->hw_addr))
3560 return;
9e10e045
AD		 3561 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3562 if (hw->mac.type == ixgbe_mac_82598EB &&
3563 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3564 return;
3565
3566 do {
032b4325 3567 usleep_range(1000, 2000);
9e10e045
AD		 3568 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3569 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3570
3571 if (!wait_loop) {
3572 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3573 "the polling period\n", reg_idx);
3574 }
3575}
3576
2d39d576
YZ		 3577void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3578 struct ixgbe_ring *ring)
3579{
3580 struct ixgbe_hw *hw = &adapter->hw;
3581 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3582 u32 rxdctl;
3583 u8 reg_idx = ring->reg_idx;
3584
b0483c8f
MR		 3585 if (ixgbe_removed(hw->hw_addr))
3586 return;
2d39d576
YZ		 3587 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3588 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3589
3590 /* write value back with RXDCTL.ENABLE bit cleared */
3591 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3592
3593 if (hw->mac.type == ixgbe_mac_82598EB &&
3594 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3595 return;
3596
3597 /* the hardware may take up to 100us to really disable the rx queue */
3598 do {
3599 udelay(10);
3600 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3601 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3602
3603 if (!wait_loop) {
3604 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3605 "the polling period\n", reg_idx);
3606 }
3607}
3608
84418e3b
AD		 3609void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3610 struct ixgbe_ring *ring)
acd37177
AD		 3611{
3612 struct ixgbe_hw *hw = &adapter->hw;
3613 u64 rdba = ring->dma;
9e10e045 3614 u32 rxdctl;
bf29ee6c 3615 u8 reg_idx = ring->reg_idx;
acd37177 3616
9e10e045
AD		 3617 /* disable queue to avoid issues while updating state */
3618 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3619 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3620
acd37177
AD		 3621 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3622 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3623 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3624 ring->count * sizeof(union ixgbe_adv_rx_desc));
8b75451b
NP		 3625 /* Force flushing of IXGBE_RDLEN to prevent MDD */
3626 IXGBE_WRITE_FLUSH(hw);
3627
acd37177
AD		 3628 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3629 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3630 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3631
3632 ixgbe_configure_srrctl(adapter, ring);
3633 ixgbe_configure_rscctl(adapter, ring);
3634
3635 if (hw->mac.type == ixgbe_mac_82598EB) {
3636 /*
3637 * enable cache line friendly hardware writes:
3638 * PTHRESH=32 descriptors (half the internal cache),
3639 * this also removes ugly rx_no_buffer_count increment
3640 * HTHRESH=4 descriptors (to minimize latency on fetch)
3641 * WTHRESH=8 burst writeback up to two cache lines
3642 */
3643 rxdctl &= ~0x3FFFFF;
3644 rxdctl |= 0x080420;
3645 }
3646
3647 /* enable receive descriptor ring */
3648 rxdctl |= IXGBE_RXDCTL_ENABLE;
3649 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3650
3651 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3652 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3653}
3654
48654521
AD		 3655static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3656{
3657 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3658 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3659 u16 pool;
48654521
AD		 3660
3661 /* PSRTYPE must be initialized in non 82598 adapters */
3662 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3663 IXGBE_PSRTYPE_UDPHDR |
3664 IXGBE_PSRTYPE_IPV4HDR |
48654521 3665 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3666 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3667
3668 if (hw->mac.type == ixgbe_mac_82598EB)
3669 return;
3670
fbe7ca7f
AD		 3671 if (rss_i > 3)
3672 psrtype |= 2 << 29;
3673 else if (rss_i > 1)
3674 psrtype |= 1 << 29;
48654521 3675
2a47fa45
JF		 3676 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3677 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3678}
3679
f5b4a52e
AD		 3680static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3681{
3682 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3683 u32 reg_offset, vf_shift;
435b19f6 3684 u32 gcr_ext, vmdctl;
de4c7f65 3685 int i;
f5b4a52e
AD		 3686
3687 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3688 return;
3689
3690 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3691 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3692 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3693 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3694 vmdctl |= IXGBE_VT_CTL_REPLEN;
3695 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3696
1d9c0bfd
AD		 3697 vf_shift = VMDQ_P(0) % 32;
3698 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3699
3700 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3701 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3702 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3703 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3704 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3705 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3706 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3707
3708 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3709 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e 3710
16369564
AD		 3711 /* clear VLAN promisc flag so VFTA will be updated if necessary */
3712 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
3713
f5b4a52e
AD		 3714 /*
3715 * Set up VF register offsets for selected VT Mode,
3716 * i.e. 32 or 64 VFs for SR-IOV
3717 */
73079ea0
AD		 3718 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3719 case IXGBE_82599_VMDQ_8Q_MASK:
3720 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3721 break;
3722 case IXGBE_82599_VMDQ_4Q_MASK:
3723 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3724 break;
3725 default:
3726 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3727 break;
3728 }
3729
f5b4a52e
AD		 3730 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3731
435b19f6 3732
a985b6c3 3733 /* Enable MAC Anti-Spoofing */
435b19f6 3734 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3735 adapter->num_vfs);
5b7f000f 3736
f079fa00 3737 /* Ensure LLDP and FC is set for Ethertype Antispoofing if we will be
5b7f000f
DS		 3738 * calling set_ethertype_anti_spoofing for each VF in loop below
3739 */
f079fa00 3740 if (hw->mac.ops.set_ethertype_anti_spoofing) {
5b7f000f 3741 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
f079fa00
ET		 3742 (IXGBE_ETQF_FILTER_EN |
3743 IXGBE_ETQF_TX_ANTISPOOF |
3744 IXGBE_ETH_P_LLDP));
3745
3746 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_FC),
3747 (IXGBE_ETQF_FILTER_EN |
3748 IXGBE_ETQF_TX_ANTISPOOF |
3749 ETH_P_PAUSE));
3750 }
5b7f000f 3751
de4c7f65
GR		 3752 /* For VFs that have spoof checking turned off */
3753 for (i = 0; i < adapter->num_vfs; i++) {
3754 if (!adapter->vfinfo[i].spoofchk_enabled)
3755 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3756
3757 /* enable ethertype anti spoofing if hw supports it */
3758 if (hw->mac.ops.set_ethertype_anti_spoofing)
3759 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3760
3761 /* Enable/Disable RSS query feature */
3762 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3763 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3764 }
f5b4a52e
AD		 3765}
3766
477de6ed 3767static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3768{
9a799d71
AK		 3769 struct ixgbe_hw *hw = &adapter->hw;
3770 struct net_device *netdev = adapter->netdev;
3771 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3772 struct ixgbe_ring *rx_ring;
3773 int i;
3774 u32 mhadd, hlreg0;
48654521 3775
63f39bd1 3776#ifdef IXGBE_FCOE
477de6ed
AD		 3777 /* adjust max frame to be able to do baby jumbo for FCoE */
3778 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3779 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3780 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3781
477de6ed 3782#endif /* IXGBE_FCOE */
872844dd
AD		 3783
3784 /* adjust max frame to be at least the size of a standard frame */
3785 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3786 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3787
477de6ed
AD		 3788 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3789 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3790 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3791 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3792
3793 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3794 }
3795
3796 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3797 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3798 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3799 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3800
0cefafad
JB		 3801 /*
3802 * Setup the HW Rx Head and Tail Descriptor Pointers and
3803 * the Base and Length of the Rx Descriptor Ring
3804 */
9a799d71 3805 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3806 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3807 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3808 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3809 else
7d637bcc 3810 clear_ring_rsc_enabled(rx_ring);
477de6ed 3811 }
477de6ed
AD		 3812}
3813
7367096a
AD		 3814static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3815{
3816 struct ixgbe_hw *hw = &adapter->hw;
3817 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3818
3819 switch (hw->mac.type) {
3820 case ixgbe_mac_82598EB:
3821 /*
3822 * For VMDq support of different descriptor types or
3823 * buffer sizes through the use of multiple SRRCTL
3824 * registers, RDRXCTL.MVMEN must be set to 1
3825 *
3826 * also, the manual doesn't mention it clearly but DCA hints
3827 * will only use queue 0's tags unless this bit is set. Side
3828 * effects of setting this bit are only that SRRCTL must be
3829 * fully programmed [0..15]
3830 */
3831 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3832 break;
052a1a72
MR		 3833 case ixgbe_mac_X550:
3834 case ixgbe_mac_X550EM_x:
f961ddae
MR		 3835 if (adapter->num_vfs)
3836 rdrxctl |= IXGBE_RDRXCTL_PSP;
3837 /* fall through for older HW */
7367096a 3838 case ixgbe_mac_82599EB:
b93a2226 3839 case ixgbe_mac_X540:
7367096a
AD		 3840 /* Disable RSC for ACK packets */
3841 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3842 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3843 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3844 /* hardware requires some bits to be set by default */
3845 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3846 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3847 break;
3848 default:
3849 /* We should do nothing since we don't know this hardware */
3850 return;
3851 }
3852
3853 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3854}
3855
477de6ed
AD		 3856/**
3857 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3858 * @adapter: board private structure
3859 *
3860 * Configure the Rx unit of the MAC after a reset.
3861 **/
3862static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3863{
3864 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3865 int i;
6dcc28b9 3866 u32 rxctrl, rfctl;
477de6ed
AD		 3867
3868 /* disable receives while setting up the descriptors */
1f9ac57c 3869 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3870
3871 ixgbe_setup_psrtype(adapter);
7367096a 3872 ixgbe_setup_rdrxctl(adapter);
477de6ed 3873
6dcc28b9
JK		 3874 /* RSC Setup */
3875 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3876 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3877 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3878 rfctl |= IXGBE_RFCTL_RSC_DIS;
3879 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3880
9e10e045 3881 /* Program registers for the distribution of queues */
f5b4a52e 3882 ixgbe_setup_mrqc(adapter);
f5b4a52e 3883
477de6ed
AD		 3884 /* set_rx_buffer_len must be called before ring initialization */
3885 ixgbe_set_rx_buffer_len(adapter);
3886
3887 /*
3888 * Setup the HW Rx Head and Tail Descriptor Pointers and
3889 * the Base and Length of the Rx Descriptor Ring
3890 */
9e10e045
AD		 3891 for (i = 0; i < adapter->num_rx_queues; i++)
3892 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3893
1f9ac57c 3894 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3895 /* disable drop enable for 82598 parts */
3896 if (hw->mac.type == ixgbe_mac_82598EB)
3897 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3898
3899 /* enable all receives */
3900 rxctrl |= IXGBE_RXCTRL_RXEN;
3901 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3902}
3903
80d5c368
PM		 3904static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3905 __be16 proto, u16 vid)
068c89b0
DS		 3906{
3907 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3908 struct ixgbe_hw *hw = &adapter->hw;
3909
3910 /* add VID to filter table */
b6488b66 3911 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, true);
f62bbb5e 3912 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3913
3914 return 0;
068c89b0
DS		 3915}
3916
e1d0a2af
AD		 3917static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
3918{
3919 u32 vlvf;
3920 int idx;
3921
3922 /* short cut the special case */
3923 if (vlan == 0)
3924 return 0;
3925
3926 /* Search for the vlan id in the VLVF entries */
3927 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
3928 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
3929 if ((vlvf & VLAN_VID_MASK) == vlan)
3930 break;
3931 }
3932
3933 return idx;
3934}
3935
3936void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
3937{
3938 struct ixgbe_hw *hw = &adapter->hw;
3939 u32 bits, word;
3940 int idx;
3941
3942 idx = ixgbe_find_vlvf_entry(hw, vid);
3943 if (!idx)
3944 return;
3945
3946 /* See if any other pools are set for this VLAN filter
3947 * entry other than the PF.
3948 */
3949 word = idx * 2 + (VMDQ_P(0) / 32);
3950 bits = ~(1 << (VMDQ_P(0)) % 32);
3951 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
3952
3953 /* Disable the filter so this falls into the default pool. */
3954 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
3955 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
3956 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
3957 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
3958 }
3959}
3960
80d5c368
PM		 3961static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3962 __be16 proto, u16 vid)
068c89b0
DS		 3963{
3964 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3965 struct ixgbe_hw *hw = &adapter->hw;
3966
068c89b0 3967 /* remove VID from filter table */
e1d0a2af
AD		 3968 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
3969 ixgbe_update_pf_promisc_vlvf(adapter, vid);
3970 else
3971 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
3972
f62bbb5e 3973 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3974
3975 return 0;
068c89b0
DS		 3976}
3977
f62bbb5e
JG		 3978/**
3979 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3980 * @adapter: driver data
3981 */
3982static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3983{
3984 struct ixgbe_hw *hw = &adapter->hw;
3985 u32 vlnctrl;
5f6c0181
JB		 3986 int i, j;
3987
3988 switch (hw->mac.type) {
3989 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3990 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3991 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3992 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3993 break;
3994 case ixgbe_mac_82599EB:
b93a2226 3995 case ixgbe_mac_X540:
9a75a1ac
DS		 3996 case ixgbe_mac_X550:
3997 case ixgbe_mac_X550EM_x:
5f6c0181 3998 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3999 struct ixgbe_ring *ring = adapter->rx_ring[i];
4000
4001 if (ring->l2_accel_priv)
4002 continue;
4003 j = ring->reg_idx;
5f6c0181
JB		 4004 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4005 vlnctrl &= ~IXGBE_RXDCTL_VME;
4006 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4007 }
4008 break;
4009 default:
4010 break;
4011 }
4012}
4013
4014/**
f62bbb5e 4015 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 4016 * @adapter: driver data
4017 */
f62bbb5e 4018static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 4019{
4020 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 4021 u32 vlnctrl;
5f6c0181
JB		 4022 int i, j;
4023
4024 switch (hw->mac.type) {
4025 case ixgbe_mac_82598EB:
f62bbb5e
JG		 4026 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4027 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 4028 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4029 break;
4030 case ixgbe_mac_82599EB:
b93a2226 4031 case ixgbe_mac_X540:
9a75a1ac
DS		 4032 case ixgbe_mac_X550:
4033 case ixgbe_mac_X550EM_x:
5f6c0181 4034 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 4035 struct ixgbe_ring *ring = adapter->rx_ring[i];
4036
4037 if (ring->l2_accel_priv)
4038 continue;
4039 j = ring->reg_idx;
5f6c0181
JB		 4040 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4041 vlnctrl |= IXGBE_RXDCTL_VME;
4042 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4043 }
4044 break;
4045 default:
4046 break;
4047 }
4048}
4049
16369564
AD		 4050static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4051{
4052 struct ixgbe_hw *hw = &adapter->hw;
4053 u32 vlnctrl, i;
4054
4055 switch (hw->mac.type) {
4056 case ixgbe_mac_82599EB:
4057 case ixgbe_mac_X540:
4058 case ixgbe_mac_X550:
4059 case ixgbe_mac_X550EM_x:
4060 default:
4061 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4062 break;
4063 /* fall through */
4064 case ixgbe_mac_82598EB:
4065 /* legacy case, we can just disable VLAN filtering */
4066 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4067 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
4068 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4069 return;
4070 }
4071
4072 /* We are already in VLAN promisc, nothing to do */
4073 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4074 return;
4075
4076 /* Set flag so we don't redo unnecessary work */
4077 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4078
4079 /* Add PF to all active pools */
4080 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4081 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4082 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4083
4084 vlvfb |= 1 << (VMDQ_P(0) % 32);
4085 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4086 }
4087
4088 /* Set all bits in the VLAN filter table array */
4089 for (i = hw->mac.vft_size; i--;)
4090 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4091}
4092
4093#define VFTA_BLOCK_SIZE 8
4094static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4095{
4096 struct ixgbe_hw *hw = &adapter->hw;
4097 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4098 u32 vid_start = vfta_offset * 32;
4099 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4100 u32 i, vid, word, bits;
4101
4102 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4103 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4104
4105 /* pull VLAN ID from VLVF */
4106 vid = vlvf & VLAN_VID_MASK;
4107
4108 /* only concern outselves with a certain range */
4109 if (vid < vid_start || vid >= vid_end)
4110 continue;
4111
4112 if (vlvf) {
4113 /* record VLAN ID in VFTA */
4114 vfta[(vid - vid_start) / 32] |= 1 << (vid % 32);
4115
4116 /* if PF is part of this then continue */
4117 if (test_bit(vid, adapter->active_vlans))
4118 continue;
4119 }
4120
4121 /* remove PF from the pool */
4122 word = i * 2 + VMDQ_P(0) / 32;
4123 bits = ~(1 << (VMDQ_P(0) % 32));
4124 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4125 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4126 }
4127
4128 /* extract values from active_vlans and write back to VFTA */
4129 for (i = VFTA_BLOCK_SIZE; i--;) {
4130 vid = (vfta_offset + i) * 32;
4131 word = vid / BITS_PER_LONG;
4132 bits = vid % BITS_PER_LONG;
4133
4134 vfta[i] |= adapter->active_vlans[word] >> bits;
4135
4136 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4137 }
4138}
4139
4140static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4141{
4142 struct ixgbe_hw *hw = &adapter->hw;
4143 u32 vlnctrl, i;
4144
4145 switch (hw->mac.type) {
4146 case ixgbe_mac_82599EB:
4147 case ixgbe_mac_X540:
4148 case ixgbe_mac_X550:
4149 case ixgbe_mac_X550EM_x:
4150 default:
4151 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED)
4152 break;
4153 /* fall through */
4154 case ixgbe_mac_82598EB:
4155 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4156 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
4157 vlnctrl |= IXGBE_VLNCTRL_VFE;
4158 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4159 return;
4160 }
4161
4162 /* We are not in VLAN promisc, nothing to do */
4163 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4164 return;
4165
4166 /* Set flag so we don't redo unnecessary work */
4167 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4168
4169 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4170 ixgbe_scrub_vfta(adapter, i);
4171}
4172
9a799d71
AK		 4173static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4174{
f62bbb5e 4175 u16 vid;
9a799d71 4176
80d5c368 4177 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 4178
4179 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 4180 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 4181}
4182
b335e75b
JK		 4183/**
4184 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4185 * @netdev: network interface device structure
4186 *
4187 * Writes multicast address list to the MTA hash table.
4188 * Returns: -ENOMEM on failure
4189 * 0 on no addresses written
4190 * X on writing X addresses to MTA
4191 **/
4192static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4193{
4194 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4195 struct ixgbe_hw *hw = &adapter->hw;
4196
4197 if (!netif_running(netdev))
4198 return 0;
4199
4200 if (hw->mac.ops.update_mc_addr_list)
4201 hw->mac.ops.update_mc_addr_list(hw, netdev);
4202 else
4203 return -ENOMEM;
4204
4205#ifdef CONFIG_PCI_IOV
5d7daa35 4206 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 4207#endif
4208
4209 return netdev_mc_count(netdev);
4210}
4211
5d7daa35
JK		 4212#ifdef CONFIG_PCI_IOV
4213void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4214{
c9f53e63 4215 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4216 struct ixgbe_hw *hw = &adapter->hw;
4217 int i;
c9f53e63
AD		 4218
4219 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4220 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4221
4222 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4223 hw->mac.ops.set_rar(hw, i,
4224 mac_table->addr,
4225 mac_table->pool,
5d7daa35
JK		 4226 IXGBE_RAH_AV);
4227 else
4228 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4229 }
4230}
5d7daa35 4231
c9f53e63 4232#endif
5d7daa35
JK		 4233static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4234{
c9f53e63 4235 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4236 struct ixgbe_hw *hw = &adapter->hw;
4237 int i;
5d7daa35 4238
c9f53e63
AD		 4239 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4240 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4241 continue;
4242
4243 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4244
4245 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4246 hw->mac.ops.set_rar(hw, i,
4247 mac_table->addr,
4248 mac_table->pool,
4249 IXGBE_RAH_AV);
4250 else
4251 hw->mac.ops.clear_rar(hw, i);
5d7daa35
JK		 4252 }
4253}
4254
4255static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4256{
c9f53e63 4257 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4258 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4259 int i;
5d7daa35 4260
c9f53e63
AD		 4261 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4262 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4263 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
5d7daa35 4264 }
c9f53e63 4265
5d7daa35
JK		 4266 ixgbe_sync_mac_table(adapter);
4267}
4268
c9f53e63 4269static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
5d7daa35 4270{
c9f53e63 4271 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4272 struct ixgbe_hw *hw = &adapter->hw;
4273 int i, count = 0;
4274
c9f53e63
AD		 4275 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4276 /* do not count default RAR as available */
4277 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4278 continue;
4279
4280 /* only count unused and addresses that belong to us */
4281 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4282 if (mac_table->pool != pool)
4283 continue;
4284 }
4285
4286 count++;
5d7daa35 4287 }
c9f53e63 4288
5d7daa35
JK		 4289 return count;
4290}
4291
4292/* this function destroys the first RAR entry */
c9f53e63 4293static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
5d7daa35 4294{
c9f53e63 4295 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4296 struct ixgbe_hw *hw = &adapter->hw;
4297
c9f53e63
AD		 4298 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4299 mac_table->pool = VMDQ_P(0);
4300
4301 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4302
4303 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
5d7daa35
JK		 4304 IXGBE_RAH_AV);
4305}
4306
c9f53e63
AD		 4307int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4308 const u8 *addr, u16 pool)
5d7daa35 4309{
c9f53e63 4310 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35
JK		 4311 struct ixgbe_hw *hw = &adapter->hw;
4312 int i;
4313
4314 if (is_zero_ether_addr(addr))
4315 return -EINVAL;
4316
c9f53e63
AD		 4317 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4318 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
5d7daa35 4319 continue;
c9f53e63
AD		 4320
4321 ether_addr_copy(mac_table->addr, addr);
4322 mac_table->pool = pool;
4323
4324 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4325 IXGBE_MAC_STATE_IN_USE;
4326
5d7daa35 4327 ixgbe_sync_mac_table(adapter);
c9f53e63 4328
5d7daa35
JK		 4329 return i;
4330 }
c9f53e63 4331
5d7daa35
JK		 4332 return -ENOMEM;
4333}
4334
c9f53e63
AD		 4335int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4336 const u8 *addr, u16 pool)
5d7daa35 4337{
c9f53e63 4338 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
5d7daa35 4339 struct ixgbe_hw *hw = &adapter->hw;
c9f53e63 4340 int i;
5d7daa35
JK		 4341
4342 if (is_zero_ether_addr(addr))
4343 return -EINVAL;
4344
c9f53e63
AD		 4345 /* search table for addr, if found clear IN_USE flag and sync */
4346 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4347 /* we can only delete an entry if it is in use */
4348 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4349 continue;
4350 /* we only care about entries that belong to the given pool */
4351 if (mac_table->pool != pool)
4352 continue;
4353 /* we only care about a specific MAC address */
4354 if (!ether_addr_equal(addr, mac_table->addr))
4355 continue;
4356
4357 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4358 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4359
4360 ixgbe_sync_mac_table(adapter);
4361
4362 return 0;
5d7daa35 4363 }
c9f53e63 4364
5d7daa35
JK		 4365 return -ENOMEM;
4366}
2850062a
AD		 4367/**
4368 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4369 * @netdev: network interface device structure
4370 *
4371 * Writes unicast address list to the RAR table.
4372 * Returns: -ENOMEM on failure/insufficient address space
4373 * 0 on no addresses written
4374 * X on writing X addresses to the RAR table
4375 **/
5d7daa35 4376static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4377{
4378 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4379 int count = 0;
4380
4381 /* return ENOMEM indicating insufficient memory for addresses */
c9f53e63 4382 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter, vfn))
2850062a
AD		 4383 return -ENOMEM;
4384
95447461 4385 if (!netdev_uc_empty(netdev)) {
2850062a 4386 struct netdev_hw_addr *ha;
2850062a 4387 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4388 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4389 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4390 count++;
4391 }
4392 }
2850062a
AD		 4393 return count;
4394}
4395
0f079d22
AD		 4396static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4397{
4398 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4399 int ret;
4400
4401 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4402
4403 return min_t(int, ret, 0);
4404}
4405
4406static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4407{
4408 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4409
4410 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4411
4412 return 0;
4413}
4414
9a799d71 4415/**
2c5645cf 4416 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4417 * @netdev: network interface device structure
4418 *
2c5645cf
CL		 4419 * The set_rx_method entry point is called whenever the unicast/multicast
4420 * address list or the network interface flags are updated. This routine is
4421 * responsible for configuring the hardware for proper unicast, multicast and
4422 * promiscuous mode.
9a799d71 4423 **/
7f870475 4424void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4425{
4426 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4427 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 4428 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4429 int count;
9a799d71
AK		 4430
4431 /* Check for Promiscuous and All Multicast modes */
9a799d71
AK		 4432 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4433
f5dc442b 4434 /* set all bits that we expect to always be set */
3f2d1c0f 4435 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4436 fctrl |= IXGBE_FCTRL_BAM;
4437 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4438 fctrl |= IXGBE_FCTRL_PMCF;
4439
2850062a
AD		 4440 /* clear the bits we are changing the status of */
4441 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
9a799d71 4442 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4443 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4444 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4445 vmolr |= IXGBE_VMOLR_MPE;
16369564 4446 ixgbe_vlan_promisc_enable(adapter);
9a799d71 4447 } else {
746b9f02
PM		 4448 if (netdev->flags & IFF_ALLMULTI) {
4449 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4450 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4451 }
e433ea1f 4452 hw->addr_ctrl.user_set_promisc = false;
16369564 4453 ixgbe_vlan_promisc_disable(adapter);
9dcb373c
JF		 4454 }
4455
4456 /*
4457 * Write addresses to available RAR registers, if there is not
4458 * sufficient space to store all the addresses then enable
4459 * unicast promiscuous mode
4460 */
0f079d22 4461 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
9dcb373c
JF		 4462 fctrl |= IXGBE_FCTRL_UPE;
4463 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4464 }
4465
cf78959c
ET		 4466 /* Write addresses to the MTA, if the attempt fails
4467 * then we should just turn on promiscuous mode so
4468 * that we can at least receive multicast traffic
4469 */
b335e75b
JK		 4470 count = ixgbe_write_mc_addr_list(netdev);
4471 if (count < 0) {
4472 fctrl |= IXGBE_FCTRL_MPE;
4473 vmolr |= IXGBE_VMOLR_MPE;
4474 } else if (count) {
4475 vmolr |= IXGBE_VMOLR_ROMPE;
4476 }
1d9c0bfd
AD		 4477
4478 if (hw->mac.type != ixgbe_mac_82598EB) {
4479 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4480 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4481 IXGBE_VMOLR_ROPE);
1d9c0bfd 4482 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4483 }
4484
3f2d1c0f
BG		 4485 /* This is useful for sniffing bad packets. */
4486 if (adapter->netdev->features & NETIF_F_RXALL) {
4487 /* UPE and MPE will be handled by normal PROMISC logic
4488 * in e1000e_set_rx_mode */
4489 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4490 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4491 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4492
4493 fctrl &= ~(IXGBE_FCTRL_DPF);
4494 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4495 }
4496
2850062a 4497 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4498
f646968f 4499 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4500 ixgbe_vlan_strip_enable(adapter);
4501 else
4502 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4503}
4504
021230d4
AV		 4505static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4506{
4507 int q_idx;
021230d4 4508
5a85e737
ET		 4509 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4510 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4511 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4512 }
021230d4
AV		 4513}
4514
4515static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4516{
4517 int q_idx;
021230d4 4518
5a85e737 4519 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4520 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4521 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4522 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4523 usleep_range(1000, 20000);
5a85e737
ET		 4524 }
4525 }
021230d4
AV		 4526}
4527
67359c3c
MR		 4528static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4529{
4530 switch (adapter->hw.mac.type) {
4531 case ixgbe_mac_X550:
4532 case ixgbe_mac_X550EM_x:
4533 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
67359c3c 4534 adapter->vxlan_port = 0;
67359c3c
MR		 4535 break;
4536 default:
4537 break;
4538 }
4539}
4540
7a6b6f51 4541#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4542/**
2f90b865
AD		 4543 * ixgbe_configure_dcb - Configure DCB hardware
4544 * @adapter: ixgbe adapter struct
4545 *
4546 * This is called by the driver on open to configure the DCB hardware.
4547 * This is also called by the gennetlink interface when reconfiguring
4548 * the DCB state.
4549 */
4550static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4551{
4552 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4553 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4554
67ebd791
AD		 4555 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4556 if (hw->mac.type == ixgbe_mac_82598EB)
4557 netif_set_gso_max_size(adapter->netdev, 65536);
4558 return;
4559 }
4560
4561 if (hw->mac.type == ixgbe_mac_82598EB)
4562 netif_set_gso_max_size(adapter->netdev, 32768);
4563
971060b1 4564#ifdef IXGBE_FCOE
b120818e
JF		 4565 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4566 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4567#endif
b120818e
JF		 4568
4569 /* reconfigure the hardware */
4570 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4571 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4572 DCB_TX_CONFIG);
4573 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4574 DCB_RX_CONFIG);
4575 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4576 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4577 ixgbe_dcb_hw_ets(&adapter->hw,
4578 adapter->ixgbe_ieee_ets,
4579 max_frame);
4580 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4581 adapter->ixgbe_ieee_pfc->pfc_en,
4582 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4583 }
8187cd48
JF		 4584
4585 /* Enable RSS Hash per TC */
4586 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4587 u32 msb = 0;
4588 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4589
d411a936
AD		 4590 while (rss_i) {
4591 msb++;
4592 rss_i >>= 1;
4593 }
8187cd48 4594
4ae63730
AD		 4595 /* write msb to all 8 TCs in one write */
4596 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4597 }
2f90b865 4598}
9da712d2
JF		 4599#endif
4600
4601/* Additional bittime to account for IXGBE framing */
4602#define IXGBE_ETH_FRAMING 20
4603
49ce9c2c 4604/**
9da712d2
JF		 4605 * ixgbe_hpbthresh - calculate high water mark for flow control
4606 *
4607 * @adapter: board private structure to calculate for
49ce9c2c 4608 * @pb: packet buffer to calculate
9da712d2
JF		 4609 */
4610static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4611{
4612 struct ixgbe_hw *hw = &adapter->hw;
4613 struct net_device *dev = adapter->netdev;
4614 int link, tc, kb, marker;
4615 u32 dv_id, rx_pba;
4616
4617 /* Calculate max LAN frame size */
4618 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4619
4620#ifdef IXGBE_FCOE
4621 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4622 if ((dev->features & NETIF_F_FCOE_MTU) &&
4623 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4624 (pb == ixgbe_fcoe_get_tc(adapter)))
4625 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4626#endif
e5776620 4627
9da712d2
JF		 4628 /* Calculate delay value for device */
4629 switch (hw->mac.type) {
4630 case ixgbe_mac_X540:
9a75a1ac
DS		 4631 case ixgbe_mac_X550:
4632 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4633 dv_id = IXGBE_DV_X540(link, tc);
4634 break;
4635 default:
4636 dv_id = IXGBE_DV(link, tc);
4637 break;
4638 }
4639
4640 /* Loopback switch introduces additional latency */
4641 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4642 dv_id += IXGBE_B2BT(tc);
4643
4644 /* Delay value is calculated in bit times convert to KB */
4645 kb = IXGBE_BT2KB(dv_id);
4646 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4647
4648 marker = rx_pba - kb;
4649
4650 /* It is possible that the packet buffer is not large enough
4651 * to provide required headroom. In this case throw an error
4652 * to user and a do the best we can.
4653 */
4654 if (marker < 0) {
4655 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4656 "headroom to support flow control."
4657 "Decrease MTU or number of traffic classes\n", pb);
4658 marker = tc + 1;
4659 }
4660
4661 return marker;
4662}
4663
49ce9c2c 4664/**
9da712d2
JF		 4665 * ixgbe_lpbthresh - calculate low water mark for for flow control
4666 *
4667 * @adapter: board private structure to calculate for
49ce9c2c 4668 * @pb: packet buffer to calculate
9da712d2 4669 */
e5776620 4670static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4671{
4672 struct ixgbe_hw *hw = &adapter->hw;
4673 struct net_device *dev = adapter->netdev;
4674 int tc;
4675 u32 dv_id;
4676
4677 /* Calculate max LAN frame size */
4678 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4679
e5776620
JK		 4680#ifdef IXGBE_FCOE
4681 /* FCoE traffic class uses FCOE jumbo frames */
4682 if ((dev->features & NETIF_F_FCOE_MTU) &&
4683 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4684 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4685 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4686#endif
4687
9da712d2
JF		 4688 /* Calculate delay value for device */
4689 switch (hw->mac.type) {
4690 case ixgbe_mac_X540:
9a75a1ac
DS		 4691 case ixgbe_mac_X550:
4692 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4693 dv_id = IXGBE_LOW_DV_X540(tc);
4694 break;
4695 default:
4696 dv_id = IXGBE_LOW_DV(tc);
4697 break;
4698 }
4699
4700 /* Delay value is calculated in bit times convert to KB */
4701 return IXGBE_BT2KB(dv_id);
4702}
4703
4704/*
4705 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4706 */
4707static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4708{
4709 struct ixgbe_hw *hw = &adapter->hw;
4710 int num_tc = netdev_get_num_tc(adapter->netdev);
4711 int i;
4712
4713 if (!num_tc)
4714 num_tc = 1;
4715
9da712d2
JF		 4716 for (i = 0; i < num_tc; i++) {
4717 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4718 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4719
4720 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4721 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4722 hw->fc.low_water[i] = 0;
9da712d2 4723 }
e5776620
JK		 4724
4725 for (; i < MAX_TRAFFIC_CLASS; i++)
4726 hw->fc.high_water[i] = 0;
9da712d2
JF		 4727}
4728
80605c65
JF		 4729static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4730{
80605c65 4731 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4732 int hdrm;
4733 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4734
4735 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4736 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4737 hdrm = 32 << adapter->fdir_pballoc;
4738 else
4739 hdrm = 0;
80605c65 4740
f7e1027f 4741 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4742 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4743}
4744
e4911d57
AD		 4745static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4746{
4747 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4748 struct hlist_node *node2;
e4911d57
AD		 4749 struct ixgbe_fdir_filter *filter;
4750
4751 spin_lock(&adapter->fdir_perfect_lock);
4752
4753 if (!hlist_empty(&adapter->fdir_filter_list))
4754 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4755
b67bfe0d 4756 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4757 &adapter->fdir_filter_list, fdir_node) {
4758 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4759 &filter->filter,
4760 filter->sw_idx,
4761 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4762 IXGBE_FDIR_DROP_QUEUE :
4763 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4764 }
4765
4766 spin_unlock(&adapter->fdir_perfect_lock);
4767}
4768
2a47fa45
JF		 4769static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4770 struct ixgbe_adapter *adapter)
4771{
4772 struct ixgbe_hw *hw = &adapter->hw;
4773 u32 vmolr;
4774
4775 /* No unicast promiscuous support for VMDQ devices. */
4776 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4777 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4778
4779 /* clear the affected bit */
4780 vmolr &= ~IXGBE_VMOLR_MPE;
4781
4782 if (dev->flags & IFF_ALLMULTI) {
4783 vmolr |= IXGBE_VMOLR_MPE;
4784 } else {
4785 vmolr |= IXGBE_VMOLR_ROMPE;
4786 hw->mac.ops.update_mc_addr_list(hw, dev);
4787 }
5d7daa35 4788 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4789 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4790}
4791
2a47fa45
JF		 4792static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4793{
4794 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4795 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4796 struct ixgbe_hw *hw = &adapter->hw;
4797 u16 pool = vadapter->pool;
4798 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4799 IXGBE_PSRTYPE_UDPHDR |
4800 IXGBE_PSRTYPE_IPV4HDR |
4801 IXGBE_PSRTYPE_L2HDR |
4802 IXGBE_PSRTYPE_IPV6HDR;
4803
4804 if (hw->mac.type == ixgbe_mac_82598EB)
4805 return;
4806
4807 if (rss_i > 3)
4808 psrtype |= 2 << 29;
4809 else if (rss_i > 1)
4810 psrtype |= 1 << 29;
4811
4812 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4813}
4814
4815/**
4816 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4817 * @rx_ring: ring to free buffers from
4818 **/
4819static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4820{
4821 struct device *dev = rx_ring->dev;
4822 unsigned long size;
4823 u16 i;
4824
4825 /* ring already cleared, nothing to do */
4826 if (!rx_ring->rx_buffer_info)
4827 return;
4828
4829 /* Free all the Rx ring sk_buffs */
4830 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4831 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4832
2a47fa45
JF		 4833 if (rx_buffer->skb) {
4834 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4835 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4836 dma_unmap_page(dev,
4837 IXGBE_CB(skb)->dma,
4838 ixgbe_rx_bufsz(rx_ring),
4839 DMA_FROM_DEVICE);
2a47fa45 4840 dev_kfree_skb(skb);
4d2fcfbc 4841 rx_buffer->skb = NULL;
2a47fa45 4842 }
18cb652a
AD		 4843
4844 if (!rx_buffer->page)
4845 continue;
4846
4847 dma_unmap_page(dev, rx_buffer->dma,
4848 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4849 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4850
2a47fa45
JF		 4851 rx_buffer->page = NULL;
4852 }
4853
4854 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4855 memset(rx_ring->rx_buffer_info, 0, size);
4856
4857 /* Zero out the descriptor ring */
4858 memset(rx_ring->desc, 0, rx_ring->size);
4859
4860 rx_ring->next_to_alloc = 0;
4861 rx_ring->next_to_clean = 0;
4862 rx_ring->next_to_use = 0;
4863}
4864
4865static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4866 struct ixgbe_ring *rx_ring)
4867{
4868 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4869 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4870
4871 /* shutdown specific queue receive and wait for dma to settle */
4872 ixgbe_disable_rx_queue(adapter, rx_ring);
4873 usleep_range(10000, 20000);
4874 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4875 ixgbe_clean_rx_ring(rx_ring);
4876 rx_ring->l2_accel_priv = NULL;
4877}
4878
ae72c8d0
JF		 4879static int ixgbe_fwd_ring_down(struct net_device *vdev,
4880 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4881{
4882 struct ixgbe_adapter *adapter = accel->real_adapter;
4883 unsigned int rxbase = accel->rx_base_queue;
4884 unsigned int txbase = accel->tx_base_queue;
4885 int i;
4886
4887 netif_tx_stop_all_queues(vdev);
4888
4889 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4890 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4891 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4892 }
4893
4894 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4895 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4896 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4897 }
4898
4899
4900 return 0;
4901}
4902
4903static int ixgbe_fwd_ring_up(struct net_device *vdev,
4904 struct ixgbe_fwd_adapter *accel)
4905{
4906 struct ixgbe_adapter *adapter = accel->real_adapter;
4907 unsigned int rxbase, txbase, queues;
4908 int i, baseq, err = 0;
4909
4910 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4911 return 0;
4912
4913 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4914 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4915 accel->pool, adapter->num_rx_pools,
4916 baseq, baseq + adapter->num_rx_queues_per_pool,
4917 adapter->fwd_bitmask);
4918
4919 accel->netdev = vdev;
4920 accel->rx_base_queue = rxbase = baseq;
4921 accel->tx_base_queue = txbase = baseq;
4922
4923 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4924 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4925
4926 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4927 adapter->rx_ring[rxbase + i]->netdev = vdev;
4928 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4929 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4930 }
4931
4932 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4933 adapter->tx_ring[txbase + i]->netdev = vdev;
4934 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4935 }
4936
4937 queues = min_t(unsigned int,
4938 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4939 err = netif_set_real_num_tx_queues(vdev, queues);
4940 if (err)
4941 goto fwd_queue_err;
4942
2a47fa45
JF		 4943 err = netif_set_real_num_rx_queues(vdev, queues);
4944 if (err)
4945 goto fwd_queue_err;
4946
4947 if (is_valid_ether_addr(vdev->dev_addr))
4948 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4949
4950 ixgbe_fwd_psrtype(accel);
4951 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4952 return err;
4953fwd_queue_err:
4954 ixgbe_fwd_ring_down(vdev, accel);
4955 return err;
4956}
4957
4958static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4959{
4960 struct net_device *upper;
4961 struct list_head *iter;
4962 int err;
4963
4964 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4965 if (netif_is_macvlan(upper)) {
4966 struct macvlan_dev *dfwd = netdev_priv(upper);
4967 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4968
4969 if (dfwd->fwd_priv) {
4970 err = ixgbe_fwd_ring_up(upper, vadapter);
4971 if (err)
4972 continue;
4973 }
4974 }
4975 }
4976}
4977
9a799d71
AK		 4978static void ixgbe_configure(struct ixgbe_adapter *adapter)
4979{
d2f5e7f3
AS		 4980 struct ixgbe_hw *hw = &adapter->hw;
4981
80605c65 4982 ixgbe_configure_pb(adapter);
7a6b6f51 4983#ifdef CONFIG_IXGBE_DCB
67ebd791 4984 ixgbe_configure_dcb(adapter);
2f90b865 4985#endif
b35d4d42
AD		 4986 /*
4987 * We must restore virtualization before VLANs or else
4988 * the VLVF registers will not be populated
4989 */
4990 ixgbe_configure_virtualization(adapter);
9a799d71 4991
4c1d7b4b 4992 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4993 ixgbe_restore_vlan(adapter);
4994
d2f5e7f3
AS		 4995 switch (hw->mac.type) {
4996 case ixgbe_mac_82599EB:
4997 case ixgbe_mac_X540:
4998 hw->mac.ops.disable_rx_buff(hw);
4999 break;
5000 default:
5001 break;
5002 }
5003
c4cf55e5 5004 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 5005 ixgbe_init_fdir_signature_82599(&adapter->hw,
5006 adapter->fdir_pballoc);
e4911d57
AD		 5007 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5008 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5009 adapter->fdir_pballoc);
5010 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 5011 }
4c1d7b4b 5012
d2f5e7f3
AS		 5013 switch (hw->mac.type) {
5014 case ixgbe_mac_82599EB:
5015 case ixgbe_mac_X540:
5016 hw->mac.ops.enable_rx_buff(hw);
5017 break;
5018 default:
5019 break;
5020 }
5021
9de7605e
MR		 5022#ifdef CONFIG_IXGBE_DCA
5023 /* configure DCA */
5024 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5025 ixgbe_setup_dca(adapter);
5026#endif /* CONFIG_IXGBE_DCA */
5027
7c8ae65a
AD		 5028#ifdef IXGBE_FCOE
5029 /* configure FCoE L2 filters, redirection table, and Rx control */
5030 ixgbe_configure_fcoe(adapter);
5031
5032#endif /* IXGBE_FCOE */
9a799d71
AK		 5033 ixgbe_configure_tx(adapter);
5034 ixgbe_configure_rx(adapter);
2a47fa45 5035 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 5036}
5037
0ecc061d 5038/**
e8e26350
PW		 5039 * ixgbe_sfp_link_config - set up SFP+ link
5040 * @adapter: pointer to private adapter struct
5041 **/
5042static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5043{
7086400d 5044 /*
52f33af8 5045 * We are assuming the worst case scenario here, and that
7086400d
AD		 5046 * is that an SFP was inserted/removed after the reset
5047 * but before SFP detection was enabled. As such the best
5048 * solution is to just start searching as soon as we start
5049 */
5050 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5051 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 5052
7086400d 5053 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
58e7cd24 5054 adapter->sfp_poll_time = 0;
e8e26350
PW		 5055}
5056
5057/**
5058 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 5059 * @hw: pointer to private hardware struct
5060 *
5061 * Returns 0 on success, negative on failure
5062 **/
e8e26350 5063static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 5064{
3d292265
JH		 5065 u32 speed;
5066 bool autoneg, link_up = false;
a1e869de 5067 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 5068
5069 if (hw->mac.ops.check_link)
3d292265 5070 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 5071
5072 if (ret)
e90dd264 5073 return ret;
0ecc061d 5074
3d292265
JH		 5075 speed = hw->phy.autoneg_advertised;
5076 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5077 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5078 &autoneg);
0ecc061d 5079 if (ret)
e90dd264 5080 return ret;
0ecc061d 5081
8620a103 5082 if (hw->mac.ops.setup_link)
fd0326f2 5083 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 5084
0ecc061d
PWJ		 5085 return ret;
5086}
5087
a34bcfff 5088static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 5089{
9a799d71 5090 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5091 u32 gpie = 0;
9a799d71 5092
9b471446 5093 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 5094 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5095 IXGBE_GPIE_OCD;
5096 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 5097 /*
5098 * use EIAM to auto-mask when MSI-X interrupt is asserted
5099 * this saves a register write for every interrupt
5100 */
5101 switch (hw->mac.type) {
5102 case ixgbe_mac_82598EB:
5103 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5104 break;
9b471446 5105 case ixgbe_mac_82599EB:
b93a2226 5106 case ixgbe_mac_X540:
9a75a1ac
DS		 5107 case ixgbe_mac_X550:
5108 case ixgbe_mac_X550EM_x:
b93a2226 5109 default:
9b471446
JB		 5110 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5111 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5112 break;
5113 }
5114 } else {
021230d4
AV		 5115 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5116 * specifically only auto mask tx and rx interrupts */
5117 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5118 }
9a799d71 5119
a34bcfff
AD		 5120 /* XXX: to interrupt immediately for EICS writes, enable this */
5121 /* gpie |= IXGBE_GPIE_EIMEN; */
5122
5123 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5124 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 5125
5126 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5127 case IXGBE_82599_VMDQ_8Q_MASK:
5128 gpie |= IXGBE_GPIE_VTMODE_16;
5129 break;
5130 case IXGBE_82599_VMDQ_4Q_MASK:
5131 gpie |= IXGBE_GPIE_VTMODE_32;
5132 break;
5133 default:
5134 gpie |= IXGBE_GPIE_VTMODE_64;
5135 break;
5136 }
119fc60a
MC		 5137 }
5138
5fdd31f9 5139 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 5140 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5141 switch (adapter->hw.mac.type) {
5142 case ixgbe_mac_82599EB:
9a900eca 5143 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec 5144 break;
f3df98ec
DS		 5145 default:
5146 break;
5147 }
5148 }
5fdd31f9 5149
a34bcfff
AD		 5150 /* Enable fan failure interrupt */
5151 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 5152 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 5153
a023bbd0
DS		 5154 switch (hw->mac.type) {
5155 case ixgbe_mac_82599EB:
5156 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5157 break;
5158 case ixgbe_mac_X550EM_x:
5159 gpie |= IXGBE_SDP0_GPIEN_X540;
5160 break;
5161 default:
5162 break;
2698b208 5163 }
a34bcfff
AD		 5164
5165 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5166}
5167
c7ccde0f 5168static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 5169{
5170 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 5171 int err;
a34bcfff
AD		 5172 u32 ctrl_ext;
5173
5174 ixgbe_get_hw_control(adapter);
5175 ixgbe_setup_gpie(adapter);
e8e26350 5176
9a799d71
AK		 5177 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5178 ixgbe_configure_msix(adapter);
5179 else
5180 ixgbe_configure_msi_and_legacy(adapter);
5181
ec74a471
ET		 5182 /* enable the optics for 82599 SFP+ fiber */
5183 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 5184 hw->mac.ops.enable_tx_laser(hw);
5185
961fac88
DS		 5186 if (hw->phy.ops.set_phy_power)
5187 hw->phy.ops.set_phy_power(hw, true);
5188
4e857c58 5189 smp_mb__before_atomic();
9a799d71 5190 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 5191 ixgbe_napi_enable_all(adapter);
5192
73c4b7cd
AD		 5193 if (ixgbe_is_sfp(hw)) {
5194 ixgbe_sfp_link_config(adapter);
5195 } else {
5196 err = ixgbe_non_sfp_link_config(hw);
5197 if (err)
5198 e_err(probe, "link_config FAILED %d\n", err);
5199 }
5200
021230d4
AV		 5201 /* clear any pending interrupts, may auto mask */
5202 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 5203 ixgbe_irq_enable(adapter, true, true);
9a799d71 5204
bf069c97
DS		 5205 /*
5206 * If this adapter has a fan, check to see if we had a failure
5207 * before we enabled the interrupt.
5208 */
5209 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5210 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5211 if (esdp & IXGBE_ESDP_SDP1)
396e799c 5212 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 5213 }
5214
9a799d71
AK		 5215 /* bring the link up in the watchdog, this could race with our first
5216 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 5217 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5218 adapter->link_check_timeout = jiffies;
7086400d 5219 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 5220
5221 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5222 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5223 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5224 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 5225}
5226
d4f80882
AV		 5227void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5228{
5229 WARN_ON(in_interrupt());
7086400d
AD		 5230 /* put off any impending NetWatchDogTimeout */
5231 adapter->netdev->trans_start = jiffies;
5232
d4f80882 5233 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 5234 usleep_range(1000, 2000);
d4f80882 5235 ixgbe_down(adapter);
5809a1ae
GR		 5236 /*
5237 * If SR-IOV enabled then wait a bit before bringing the adapter
5238 * back up to give the VFs time to respond to the reset. The
5239 * two second wait is based upon the watchdog timer cycle in
5240 * the VF driver.
5241 */
5242 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5243 msleep(2000);
d4f80882
AV		 5244 ixgbe_up(adapter);
5245 clear_bit(__IXGBE_RESETTING, &adapter->state);
5246}
5247
c7ccde0f 5248void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 5249{
5250 /* hardware has been reset, we need to reload some things */
5251 ixgbe_configure(adapter);
5252
c7ccde0f 5253 ixgbe_up_complete(adapter);
9a799d71
AK		 5254}
5255
5256void ixgbe_reset(struct ixgbe_adapter *adapter)
5257{
c44ade9e 5258 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 5259 struct net_device *netdev = adapter->netdev;
8ca783ab
DS		 5260 int err;
5261
b0483c8f
MR		 5262 if (ixgbe_removed(hw->hw_addr))
5263 return;
7086400d
AD		 5264 /* lock SFP init bit to prevent race conditions with the watchdog */
5265 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5266 usleep_range(1000, 2000);
5267
5268 /* clear all SFP and link config related flags while holding SFP_INIT */
5269 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5270 IXGBE_FLAG2_SFP_NEEDS_RESET);
5271 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5272
8ca783ab 5273 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5274 switch (err) {
5275 case 0:
5276 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5277 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5278 break;
5279 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5280 e_dev_err("master disable timed out\n");
da4dd0f7 5281 break;
794caeb2
PWJ		 5282 case IXGBE_ERR_EEPROM_VERSION:
5283 /* We are running on a pre-production device, log a warning */
849c4542 5284 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5285 "Please be aware there may be issues associated with "
849c4542
ET		 5286 "your hardware. If you are experiencing problems "
5287 "please contact your Intel or hardware "
5288 "representative who provided you with this "
5289 "hardware.\n");
794caeb2 5290 break;
da4dd0f7 5291 default:
849c4542 5292 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5293 }
9a799d71 5294
7086400d 5295 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
0f079d22
AD		 5296
5297 /* flush entries out of MAC table */
5d7daa35 5298 ixgbe_flush_sw_mac_table(adapter);
0f079d22
AD		 5299 __dev_uc_unsync(netdev, NULL);
5300
5301 /* do not flush user set addresses */
c9f53e63 5302 ixgbe_mac_set_default_filter(adapter);
7fa7c9dc
AD		 5303
5304 /* update SAN MAC vmdq pool selection */
5305 if (hw->mac.san_mac_rar_index)
5306 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5307
8fecf67c 5308 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5309 ixgbe_ptp_reset(adapter);
961fac88
DS		 5310
5311 if (hw->phy.ops.set_phy_power) {
5312 if (!netif_running(adapter->netdev) && !adapter->wol)
5313 hw->phy.ops.set_phy_power(hw, false);
5314 else
5315 hw->phy.ops.set_phy_power(hw, true);
5316 }
9a799d71
AK		 5317}
5318
9a799d71
AK		 5319/**
5320 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5321 * @tx_ring: ring to be cleaned
5322 **/
b6ec895e 5323static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5324{
5325 struct ixgbe_tx_buffer *tx_buffer_info;
5326 unsigned long size;
b6ec895e 5327 u16 i;
9a799d71 5328
84418e3b
AD		 5329 /* ring already cleared, nothing to do */
5330 if (!tx_ring->tx_buffer_info)
5331 return;
9a799d71 5332
84418e3b 5333 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5334 for (i = 0; i < tx_ring->count; i++) {
5335 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5336 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5337 }
5338
dad8a3b3
JF		 5339 netdev_tx_reset_queue(txring_txq(tx_ring));
5340
9a799d71
AK		 5341 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5342 memset(tx_ring->tx_buffer_info, 0, size);
5343
5344 /* Zero out the descriptor ring */
5345 memset(tx_ring->desc, 0, tx_ring->size);
5346
5347 tx_ring->next_to_use = 0;
5348 tx_ring->next_to_clean = 0;
9a799d71
AK		 5349}
5350
5351/**
021230d4 5352 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5353 * @adapter: board private structure
5354 **/
021230d4 5355static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5356{
5357 int i;
5358
021230d4 5359 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5360 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5361}
5362
5363/**
021230d4 5364 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5365 * @adapter: board private structure
5366 **/
021230d4 5367static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5368{
5369 int i;
5370
021230d4 5371 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5372 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5373}
5374
e4911d57
AD		 5375static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5376{
b67bfe0d 5377 struct hlist_node *node2;
e4911d57
AD		 5378 struct ixgbe_fdir_filter *filter;
5379
5380 spin_lock(&adapter->fdir_perfect_lock);
5381
b67bfe0d 5382 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5383 &adapter->fdir_filter_list, fdir_node) {
5384 hlist_del(&filter->fdir_node);
5385 kfree(filter);
5386 }
5387 adapter->fdir_filter_count = 0;
5388
5389 spin_unlock(&adapter->fdir_perfect_lock);
5390}
5391
9a799d71
AK		 5392void ixgbe_down(struct ixgbe_adapter *adapter)
5393{
5394 struct net_device *netdev = adapter->netdev;
7f821875 5395 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5396 struct net_device *upper;
5397 struct list_head *iter;
bf29ee6c 5398 int i;
9a799d71
AK		 5399
5400 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5401 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5402 return; /* do nothing if already down */
9a799d71
AK		 5403
5404 /* disable receives */
1f9ac57c 5405 hw->mac.ops.disable_rx(hw);
9a799d71 5406
2d39d576
YZ		 5407 /* disable all enabled rx queues */
5408 for (i = 0; i < adapter->num_rx_queues; i++)
5409 /* this call also flushes the previous write */
5410 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5411
032b4325 5412 usleep_range(10000, 20000);
9a799d71 5413
7f821875
JB		 5414 netif_tx_stop_all_queues(netdev);
5415
7086400d 5416 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5417 netif_carrier_off(netdev);
5418 netif_tx_disable(netdev);
5419
2a47fa45
JF		 5420 /* disable any upper devices */
5421 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5422 if (netif_is_macvlan(upper)) {
5423 struct macvlan_dev *vlan = netdev_priv(upper);
5424
5425 if (vlan->fwd_priv) {
5426 netif_tx_stop_all_queues(upper);
5427 netif_carrier_off(upper);
5428 netif_tx_disable(upper);
5429 }
5430 }
5431 }
5432
c0dfb90e
JF		 5433 ixgbe_irq_disable(adapter);
5434
5435 ixgbe_napi_disable_all(adapter);
5436
d034acf1
AD		 5437 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5438 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5439 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5440
5441 del_timer_sync(&adapter->service_timer);
5442
34cecbbf 5443 if (adapter->num_vfs) {
8e34d1aa
AD		 5444 /* Clear EITR Select mapping */
5445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5446
5447 /* Mark all the VFs as inactive */
5448 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5449 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5450
34cecbbf
AD		 5451 /* ping all the active vfs to let them know we are going down */
5452 ixgbe_ping_all_vfs(adapter);
5453
5454 /* Disable all VFTE/VFRE TX/RX */
5455 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5456 }
5457
7f821875
JB		 5458 /* disable transmits in the hardware now that interrupts are off */
5459 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5460 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5461 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5462 }
34cecbbf 5463
9a75a1ac 5464 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5465 switch (hw->mac.type) {
5466 case ixgbe_mac_82599EB:
b93a2226 5467 case ixgbe_mac_X540:
9a75a1ac
DS		 5468 case ixgbe_mac_X550:
5469 case ixgbe_mac_X550EM_x:
88512539 5470 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5471 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5472 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5473 break;
5474 default:
5475 break;
5476 }
7f821875 5477
6f4a0e45
PL		 5478 if (!pci_channel_offline(adapter->pdev))
5479 ixgbe_reset(adapter);
c6ecf39a 5480
ec74a471
ET		 5481 /* power down the optics for 82599 SFP+ fiber */
5482 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5483 hw->mac.ops.disable_tx_laser(hw);
5484
9a799d71
AK		 5485 ixgbe_clean_all_tx_rings(adapter);
5486 ixgbe_clean_all_rx_rings(adapter);
9a799d71
AK		 5487}
5488
9a799d71
AK		 5489/**
5490 * ixgbe_tx_timeout - Respond to a Tx Hang
5491 * @netdev: network interface device structure
5492 **/
5493static void ixgbe_tx_timeout(struct net_device *netdev)
5494{
5495 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5496
5497 /* Do the reset outside of interrupt context */
c83c6cbd 5498 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5499}
5500
9a799d71
AK		 5501/**
5502 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5503 * @adapter: board private structure to initialize
5504 *
5505 * ixgbe_sw_init initializes the Adapter private data structure.
5506 * Fields are initialized based on PCI device information and
5507 * OS network device settings (MTU size).
5508 **/
9f9a12f8 5509static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5510{
5511 struct ixgbe_hw *hw = &adapter->hw;
5512 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5513 unsigned int rss, fdir;
cb6d0f5e 5514 u32 fwsm;
7a6b6f51 5515#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5516 int j;
5517 struct tc_configuration *tc;
5518#endif
021230d4 5519
c44ade9e
JB		 5520 /* PCI config space info */
5521
5522 hw->vendor_id = pdev->vendor;
5523 hw->device_id = pdev->device;
5524 hw->revision_id = pdev->revision;
5525 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5526 hw->subsystem_device_id = pdev->subsystem_device;
5527
8fc3bb6d 5528 /* Set common capability flags and settings */
0f9b232b 5529 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5530 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d 5531 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d
ET		 5532 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5533 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5534 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5535 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5536 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5537#ifdef CONFIG_IXGBE_DCA
5538 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5539#endif
5540#ifdef IXGBE_FCOE
5541 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5542 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5543#ifdef CONFIG_IXGBE_DCB
5544 /* Default traffic class to use for FCoE */
5545 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5546#endif /* CONFIG_IXGBE_DCB */
5547#endif /* IXGBE_FCOE */
5548
b82b17d9
JF		 5549 /* initialize static ixgbe jump table entries */
5550 adapter->jump_tables[0] = ixgbe_ipv4_fields;
5551
5d7daa35
JK		 5552 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5553 hw->mac.num_rar_entries,
5554 GFP_ATOMIC);
530fd82a
AD		 5555 if (!adapter->mac_table)
5556 return -ENOMEM;
5d7daa35 5557
8fc3bb6d 5558 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5559 switch (hw->mac.type) {
5560 case ixgbe_mac_82598EB:
8fc3bb6d 5561 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
8fc3bb6d 5562
bf069c97
DS		 5563 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5564 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5565
49c7ffbe 5566 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5567 adapter->ring_feature[RING_F_FDIR].limit = 0;
5568 adapter->atr_sample_rate = 0;
5569 adapter->fdir_pballoc = 0;
5570#ifdef IXGBE_FCOE
5571 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5572 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5573#ifdef CONFIG_IXGBE_DCB
5574 adapter->fcoe.up = 0;
5575#endif /* IXGBE_DCB */
5576#endif /* IXGBE_FCOE */
5577 break;
5578 case ixgbe_mac_82599EB:
5579 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5580 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5581 break;
b93a2226 5582 case ixgbe_mac_X540:
9a900eca 5583 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5584 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5585 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5586 break;
9a75a1ac
DS		 5587 case ixgbe_mac_X550EM_x:
5588 case ixgbe_mac_X550:
5589#ifdef CONFIG_IXGBE_DCA
5590 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5591#endif
5592#ifdef CONFIG_IXGBE_VXLAN
5593 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5594#endif
5595 break;
bd508178
AD		 5596 default:
5597 break;
f8212f97 5598 }
2f90b865 5599
7c8ae65a
AD		 5600#ifdef IXGBE_FCOE
5601 /* FCoE support exists, always init the FCoE lock */
5602 spin_lock_init(&adapter->fcoe.lock);
5603
5604#endif
1fc5f038
AD		 5605 /* n-tuple support exists, always init our spinlock */
5606 spin_lock_init(&adapter->fdir_perfect_lock);
5607
7a6b6f51 5608#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5609 switch (hw->mac.type) {
5610 case ixgbe_mac_X540:
9a75a1ac
DS		 5611 case ixgbe_mac_X550:
5612 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5613 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5614 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5615 break;
5616 default:
5617 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5618 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5619 break;
5620 }
5621
2f90b865
AD		 5622 /* Configure DCB traffic classes */
5623 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5624 tc = &adapter->dcb_cfg.tc_config[j];
5625 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5626 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5627 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5628 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5629 tc->dcb_pfc = pfc_disabled;
5630 }
4de2a022
JF		 5631
5632 /* Initialize default user to priority mapping, UPx->TC0 */
5633 tc = &adapter->dcb_cfg.tc_config[0];
5634 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5635 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5636
2f90b865
AD		 5637 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5638 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5639 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5640 adapter->dcb_set_bitmap = 0x00;
3032309b 5641 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5642 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5643 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5644
5645#endif
9a799d71
AK		 5646
5647 /* default flow control settings */
cd7664f6 5648 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5649 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5650 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5651 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5652 hw->fc.send_xon = true;
73d80953 5653 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5654
99d74487 5655#ifdef CONFIG_PCI_IOV
170e8543
JK		 5656 if (max_vfs > 0)
5657 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5658
99d74487 5659 /* assign number of SR-IOV VFs */
170e8543 5660 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5661 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5662 adapter->num_vfs = 0;
5663 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5664 } else {
5665 adapter->num_vfs = max_vfs;
5666 }
5667 }
5668#endif /* CONFIG_PCI_IOV */
99d74487 5669
30efa5a3 5670 /* enable itr by default in dynamic mode */
f7554a2b 5671 adapter->rx_itr_setting = 1;
f7554a2b 5672 adapter->tx_itr_setting = 1;
30efa5a3 5673
30efa5a3
JB		 5674 /* set default ring sizes */
5675 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5676 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5677
bd198058 5678 /* set default work limits */
59224555 5679 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5680
9a799d71 5681 /* initialize eeprom parameters */
c44ade9e 5682 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5683 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5684 return -EIO;
5685 }
5686
2a47fa45
JF		 5687 /* PF holds first pool slot */
5688 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5689 set_bit(__IXGBE_DOWN, &adapter->state);
5690
5691 return 0;
5692}
5693
5694/**
5695 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5696 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5697 *
5698 * Return 0 on success, negative on failure
5699 **/
b6ec895e 5700int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5701{
b6ec895e 5702 struct device *dev = tx_ring->dev;
de88eeeb 5703 int orig_node = dev_to_node(dev);
ca8dfe25 5704 int ring_node = -1;
9a799d71
AK		 5705 int size;
5706
3a581073 5707 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5708
5709 if (tx_ring->q_vector)
ca8dfe25 5710 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5711
ca8dfe25 5712 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5713 if (!tx_ring->tx_buffer_info)
89bf67f1 5714 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5715 if (!tx_ring->tx_buffer_info)
5716 goto err;
9a799d71 5717
827da44c
JS		 5718 u64_stats_init(&tx_ring->syncp);
5719
9a799d71 5720 /* round up to nearest 4K */
12207e49 5721 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5722 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5723
ca8dfe25 5724 set_dev_node(dev, ring_node);
de88eeeb
AD		 5725 tx_ring->desc = dma_alloc_coherent(dev,
5726 tx_ring->size,
5727 &tx_ring->dma,
5728 GFP_KERNEL);
5729 set_dev_node(dev, orig_node);
5730 if (!tx_ring->desc)
5731 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5732 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5733 if (!tx_ring->desc)
5734 goto err;
9a799d71 5735
3a581073
JB		 5736 tx_ring->next_to_use = 0;
5737 tx_ring->next_to_clean = 0;
9a799d71 5738 return 0;
e01c31a5
JB		 5739
5740err:
5741 vfree(tx_ring->tx_buffer_info);
5742 tx_ring->tx_buffer_info = NULL;
b6ec895e 5743 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5744 return -ENOMEM;
9a799d71
AK		 5745}
5746
69888674
AD		 5747/**
5748 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5749 * @adapter: board private structure
5750 *
5751 * If this function returns with an error, then it's possible one or
5752 * more of the rings is populated (while the rest are not). It is the
5753 * callers duty to clean those orphaned rings.
5754 *
5755 * Return 0 on success, negative on failure
5756 **/
5757static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5758{
5759 int i, err = 0;
5760
5761 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5762 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5763 if (!err)
5764 continue;
de3d5b94 5765
396e799c 5766 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5767 goto err_setup_tx;
69888674
AD		 5768 }
5769
de3d5b94
AD		 5770 return 0;
5771err_setup_tx:
5772 /* rewind the index freeing the rings as we go */
5773 while (i--)
5774 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5775 return err;
5776}
5777
9a799d71
AK		 5778/**
5779 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5780 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5781 *
5782 * Returns 0 on success, negative on failure
5783 **/
b6ec895e 5784int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5785{
b6ec895e 5786 struct device *dev = rx_ring->dev;
de88eeeb 5787 int orig_node = dev_to_node(dev);
ca8dfe25 5788 int ring_node = -1;
021230d4 5789 int size;
9a799d71 5790
3a581073 5791 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5792
5793 if (rx_ring->q_vector)
ca8dfe25 5794 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5795
ca8dfe25 5796 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5797 if (!rx_ring->rx_buffer_info)
89bf67f1 5798 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5799 if (!rx_ring->rx_buffer_info)
5800 goto err;
9a799d71 5801
827da44c
JS		 5802 u64_stats_init(&rx_ring->syncp);
5803
9a799d71 5804 /* Round up to nearest 4K */
3a581073
JB		 5805 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5806 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5807
ca8dfe25 5808 set_dev_node(dev, ring_node);
de88eeeb
AD		 5809 rx_ring->desc = dma_alloc_coherent(dev,
5810 rx_ring->size,
5811 &rx_ring->dma,
5812 GFP_KERNEL);
5813 set_dev_node(dev, orig_node);
5814 if (!rx_ring->desc)
5815 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5816 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5817 if (!rx_ring->desc)
5818 goto err;
9a799d71 5819
3a581073
JB		 5820 rx_ring->next_to_clean = 0;
5821 rx_ring->next_to_use = 0;
9a799d71
AK		 5822
5823 return 0;
b6ec895e
AD		 5824err:
5825 vfree(rx_ring->rx_buffer_info);
5826 rx_ring->rx_buffer_info = NULL;
5827 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5828 return -ENOMEM;
9a799d71
AK		 5829}
5830
69888674
AD		 5831/**
5832 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5833 * @adapter: board private structure
5834 *
5835 * If this function returns with an error, then it's possible one or
5836 * more of the rings is populated (while the rest are not). It is the
5837 * callers duty to clean those orphaned rings.
5838 *
5839 * Return 0 on success, negative on failure
5840 **/
69888674
AD		 5841static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5842{
5843 int i, err = 0;
5844
5845 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5846 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5847 if (!err)
5848 continue;
de3d5b94 5849
396e799c 5850 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5851 goto err_setup_rx;
69888674
AD		 5852 }
5853
7c8ae65a
AD		 5854#ifdef IXGBE_FCOE
5855 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5856 if (!err)
5857#endif
5858 return 0;
de3d5b94
AD		 5859err_setup_rx:
5860 /* rewind the index freeing the rings as we go */
5861 while (i--)
5862 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5863 return err;
5864}
5865
9a799d71
AK		 5866/**
5867 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5868 * @tx_ring: Tx descriptor ring for a specific queue
5869 *
5870 * Free all transmit software resources
5871 **/
b6ec895e 5872void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5873{
b6ec895e 5874 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5875
5876 vfree(tx_ring->tx_buffer_info);
5877 tx_ring->tx_buffer_info = NULL;
5878
b6ec895e
AD		 5879 /* if not set, then don't free */
5880 if (!tx_ring->desc)
5881 return;
5882
5883 dma_free_coherent(tx_ring->dev, tx_ring->size,
5884 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5885
5886 tx_ring->desc = NULL;
5887}
5888
5889/**
5890 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5891 * @adapter: board private structure
5892 *
5893 * Free all transmit software resources
5894 **/
5895static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5896{
5897 int i;
5898
5899 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5900 if (adapter->tx_ring[i]->desc)
b6ec895e 5901 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5902}
5903
5904/**
b4617240 5905 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5906 * @rx_ring: ring to clean the resources from
5907 *
5908 * Free all receive software resources
5909 **/
b6ec895e 5910void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5911{
b6ec895e 5912 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5913
5914 vfree(rx_ring->rx_buffer_info);
5915 rx_ring->rx_buffer_info = NULL;
5916
b6ec895e
AD		 5917 /* if not set, then don't free */
5918 if (!rx_ring->desc)
5919 return;
5920
5921 dma_free_coherent(rx_ring->dev, rx_ring->size,
5922 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5923
5924 rx_ring->desc = NULL;
5925}
5926
5927/**
5928 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5929 * @adapter: board private structure
5930 *
5931 * Free all receive software resources
5932 **/
5933static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5934{
5935 int i;
5936
7c8ae65a
AD		 5937#ifdef IXGBE_FCOE
5938 ixgbe_free_fcoe_ddp_resources(adapter);
5939
5940#endif
9a799d71 5941 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5942 if (adapter->rx_ring[i]->desc)
b6ec895e 5943 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5944}
5945
9a799d71
AK		 5946/**
5947 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5948 * @netdev: network interface device structure
5949 * @new_mtu: new value for maximum frame size
5950 *
5951 * Returns 0 on success, negative on failure
5952 **/
5953static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5954{
5955 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5956 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5957
42c783c5 5958 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5959 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5960 return -EINVAL;
5961
5962 /*
872844dd
AD		 5963 * For 82599EB we cannot allow legacy VFs to enable their receive
5964 * paths when MTU greater than 1500 is configured. So display a
5965 * warning that legacy VFs will be disabled.
655309e9
AD		 5966 */
5967 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5968 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5969 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5970 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5971
396e799c 5972 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5973
021230d4 5974 /* must set new MTU before calling down or up */
9a799d71
AK		 5975 netdev->mtu = new_mtu;
5976
d4f80882
AV		 5977 if (netif_running(netdev))
5978 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5979
5980 return 0;
5981}
5982
5983/**
5984 * ixgbe_open - Called when a network interface is made active
5985 * @netdev: network interface device structure
5986 *
5987 * Returns 0 on success, negative value on failure
5988 *
5989 * The open entry point is called when a network interface is made
5990 * active by the system (IFF_UP). At this point all resources needed
5991 * for transmit and receive operations are allocated, the interrupt
5992 * handler is registered with the OS, the watchdog timer is started,
5993 * and the stack is notified that the interface is ready.
5994 **/
5995static int ixgbe_open(struct net_device *netdev)
5996{
5997 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5998 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5999 int err, queues;
4bebfaa5
AK		 6000
6001 /* disallow open during test */
6002 if (test_bit(__IXGBE_TESTING, &adapter->state))
6003 return -EBUSY;
9a799d71 6004
54386467
JB		 6005 netif_carrier_off(netdev);
6006
9a799d71
AK		 6007 /* allocate transmit descriptors */
6008 err = ixgbe_setup_all_tx_resources(adapter);
6009 if (err)
6010 goto err_setup_tx;
6011
9a799d71
AK		 6012 /* allocate receive descriptors */
6013 err = ixgbe_setup_all_rx_resources(adapter);
6014 if (err)
6015 goto err_setup_rx;
6016
6017 ixgbe_configure(adapter);
6018
021230d4 6019 err = ixgbe_request_irq(adapter);
9a799d71
AK		 6020 if (err)
6021 goto err_req_irq;
6022
ac802f5d 6023 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 6024 if (adapter->num_rx_pools > 1)
6025 queues = adapter->num_rx_queues_per_pool;
6026 else
6027 queues = adapter->num_tx_queues;
6028
6029 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 6030 if (err)
6031 goto err_set_queues;
6032
2a47fa45
JF		 6033 if (adapter->num_rx_pools > 1 &&
6034 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
6035 queues = IXGBE_MAX_L2A_QUEUES;
6036 else
6037 queues = adapter->num_rx_queues;
6038 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 6039 if (err)
6040 goto err_set_queues;
6041
1a71ab24 6042 ixgbe_ptp_init(adapter);
1a71ab24 6043
c7ccde0f 6044 ixgbe_up_complete(adapter);
9a799d71 6045
67359c3c
MR		 6046 ixgbe_clear_vxlan_port(adapter);
6047#ifdef CONFIG_IXGBE_VXLAN
3f207800 6048 vxlan_get_rx_port(netdev);
3f207800 6049#endif
67359c3c 6050
9a799d71
AK		 6051 return 0;
6052
ac802f5d
AD		 6053err_set_queues:
6054 ixgbe_free_irq(adapter);
9a799d71 6055err_req_irq:
a20a1199 6056 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 6057 if (hw->phy.ops.set_phy_power && !adapter->wol)
6058 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 6059err_setup_rx:
a20a1199 6060 ixgbe_free_all_tx_resources(adapter);
de3d5b94 6061err_setup_tx:
9a799d71
AK		 6062 ixgbe_reset(adapter);
6063
6064 return err;
6065}
6066
a0cccce2
JK		 6067static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6068{
6069 ixgbe_ptp_suspend(adapter);
6070
6ac74394
DS		 6071 if (adapter->hw.phy.ops.enter_lplu) {
6072 adapter->hw.phy.reset_disable = true;
6073 ixgbe_down(adapter);
6074 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6075 adapter->hw.phy.reset_disable = false;
6076 } else {
6077 ixgbe_down(adapter);
6078 }
6079
a0cccce2
JK		 6080 ixgbe_free_irq(adapter);
6081
6082 ixgbe_free_all_tx_resources(adapter);
6083 ixgbe_free_all_rx_resources(adapter);
6084}
6085
9a799d71
AK		 6086/**
6087 * ixgbe_close - Disables a network interface
6088 * @netdev: network interface device structure
6089 *
6090 * Returns 0, this is not allowed to fail
6091 *
6092 * The close entry point is called when an interface is de-activated
6093 * by the OS. The hardware is still under the drivers control, but
6094 * needs to be disabled. A global MAC reset is issued to stop the
6095 * hardware, and all transmit and receive resources are freed.
6096 **/
6097static int ixgbe_close(struct net_device *netdev)
6098{
6099 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 6100
1a71ab24 6101 ixgbe_ptp_stop(adapter);
1a71ab24 6102
a0cccce2 6103 ixgbe_close_suspend(adapter);
9a799d71 6104
e4911d57
AD		 6105 ixgbe_fdir_filter_exit(adapter);
6106
5eba3699 6107 ixgbe_release_hw_control(adapter);
9a799d71
AK		 6108
6109 return 0;
6110}
6111
b3c8b4ba
AD		 6112#ifdef CONFIG_PM
6113static int ixgbe_resume(struct pci_dev *pdev)
6114{
c60fbb00
AD		 6115 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6116 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 6117 u32 err;
6118
0391bbe3 6119 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 6120 pci_set_power_state(pdev, PCI_D0);
6121 pci_restore_state(pdev);
656ab817
DS		 6122 /*
6123 * pci_restore_state clears dev->state_saved so call
6124 * pci_save_state to restore it.
6125 */
6126 pci_save_state(pdev);
9ce77666 6127
6128 err = pci_enable_device_mem(pdev);
b3c8b4ba 6129 if (err) {
849c4542 6130 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 6131 return err;
6132 }
4e857c58 6133 smp_mb__before_atomic();
41c62843 6134 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 6135 pci_set_master(pdev);
6136
dd4d8ca6 6137 pci_wake_from_d3(pdev, false);
b3c8b4ba 6138
b3c8b4ba
AD		 6139 ixgbe_reset(adapter);
6140
495dce12
WJP		 6141 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6142
ac802f5d
AD		 6143 rtnl_lock();
6144 err = ixgbe_init_interrupt_scheme(adapter);
6145 if (!err && netif_running(netdev))
c60fbb00 6146 err = ixgbe_open(netdev);
ac802f5d
AD		 6147
6148 rtnl_unlock();
6149
6150 if (err)
6151 return err;
b3c8b4ba
AD		 6152
6153 netif_device_attach(netdev);
6154
6155 return 0;
6156}
b3c8b4ba 6157#endif /* CONFIG_PM */
9d8d05ae
RW		 6158
6159static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 6160{
c60fbb00
AD		 6161 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6162 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 6163 struct ixgbe_hw *hw = &adapter->hw;
6164 u32 ctrl, fctrl;
6165 u32 wufc = adapter->wol;
b3c8b4ba
AD		 6166#ifdef CONFIG_PM
6167 int retval = 0;
6168#endif
6169
6170 netif_device_detach(netdev);
6171
499ab5cc 6172 rtnl_lock();
a0cccce2
JK		 6173 if (netif_running(netdev))
6174 ixgbe_close_suspend(adapter);
499ab5cc 6175 rtnl_unlock();
b3c8b4ba 6176
5f5ae6fc
AD		 6177 ixgbe_clear_interrupt_scheme(adapter);
6178
b3c8b4ba
AD		 6179#ifdef CONFIG_PM
6180 retval = pci_save_state(pdev);
6181 if (retval)
6182 return retval;
4df10466 6183
b3c8b4ba 6184#endif
f4f1040a
JK		 6185 if (hw->mac.ops.stop_link_on_d3)
6186 hw->mac.ops.stop_link_on_d3(hw);
6187
e8e26350
PW		 6188 if (wufc) {
6189 ixgbe_set_rx_mode(netdev);
b3c8b4ba 6190
ec74a471
ET		 6191 /* enable the optics for 82599 SFP+ fiber as we can WoL */
6192 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 6193 hw->mac.ops.enable_tx_laser(hw);
6194
e8e26350
PW		 6195 /* turn on all-multi mode if wake on multicast is enabled */
6196 if (wufc & IXGBE_WUFC_MC) {
6197 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6198 fctrl |= IXGBE_FCTRL_MPE;
6199 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
6200 }
6201
6202 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
6203 ctrl |= IXGBE_CTRL_GIO_DIS;
6204 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
6205
6206 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
6207 } else {
6208 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
6209 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
6210 }
6211
bd508178
AD		 6212 switch (hw->mac.type) {
6213 case ixgbe_mac_82598EB:
dd4d8ca6 6214 pci_wake_from_d3(pdev, false);
bd508178
AD		 6215 break;
6216 case ixgbe_mac_82599EB:
b93a2226 6217 case ixgbe_mac_X540:
9a75a1ac
DS		 6218 case ixgbe_mac_X550:
6219 case ixgbe_mac_X550EM_x:
bd508178
AD		 6220 pci_wake_from_d3(pdev, !!wufc);
6221 break;
6222 default:
6223 break;
6224 }
b3c8b4ba 6225
9d8d05ae 6226 *enable_wake = !!wufc;
961fac88
DS		 6227 if (hw->phy.ops.set_phy_power && !*enable_wake)
6228 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 6229
b3c8b4ba
AD		 6230 ixgbe_release_hw_control(adapter);
6231
41c62843
MR		 6232 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
6233 pci_disable_device(pdev);
b3c8b4ba 6234
9d8d05ae
RW		 6235 return 0;
6236}
6237
6238#ifdef CONFIG_PM
6239static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
6240{
6241 int retval;
6242 bool wake;
6243
6244 retval = __ixgbe_shutdown(pdev, &wake);
6245 if (retval)
6246 return retval;
6247
6248 if (wake) {
6249 pci_prepare_to_sleep(pdev);
6250 } else {
6251 pci_wake_from_d3(pdev, false);
6252 pci_set_power_state(pdev, PCI_D3hot);
6253 }
b3c8b4ba
AD		 6254
6255 return 0;
6256}
9d8d05ae 6257#endif /* CONFIG_PM */
b3c8b4ba
AD		 6258
6259static void ixgbe_shutdown(struct pci_dev *pdev)
6260{
9d8d05ae
RW		 6261 bool wake;
6262
6263 __ixgbe_shutdown(pdev, &wake);
6264
6265 if (system_state == SYSTEM_POWER_OFF) {
6266 pci_wake_from_d3(pdev, wake);
6267 pci_set_power_state(pdev, PCI_D3hot);
6268 }
b3c8b4ba
AD		 6269}
6270
9a799d71
AK		 6271/**
6272 * ixgbe_update_stats - Update the board statistics counters.
6273 * @adapter: board private structure
6274 **/
6275void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6276{
2d86f139 6277 struct net_device *netdev = adapter->netdev;
9a799d71 6278 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6279 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6280 u64 total_mpc = 0;
6281 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6282 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6283 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6284 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6285
d08935c2
DS		 6286 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6287 test_bit(__IXGBE_RESETTING, &adapter->state))
6288 return;
6289
94b982b2 6290 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6291 u64 rsc_count = 0;
94b982b2 6292 u64 rsc_flush = 0;
94b982b2 6293 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6294 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6295 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6296 }
6297 adapter->rsc_total_count = rsc_count;
6298 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6299 }
6300
5b7da515
AD		 6301 for (i = 0; i < adapter->num_rx_queues; i++) {
6302 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6303 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6304 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6305 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6306 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6307 bytes += rx_ring->stats.bytes;
6308 packets += rx_ring->stats.packets;
6309 }
6310 adapter->non_eop_descs = non_eop_descs;
6311 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6312 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6313 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6314 netdev->stats.rx_bytes = bytes;
6315 netdev->stats.rx_packets = packets;
6316
6317 bytes = 0;
6318 packets = 0;
7ca3bc58 6319 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6320 for (i = 0; i < adapter->num_tx_queues; i++) {
6321 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6322 restart_queue += tx_ring->tx_stats.restart_queue;
6323 tx_busy += tx_ring->tx_stats.tx_busy;
6324 bytes += tx_ring->stats.bytes;
6325 packets += tx_ring->stats.packets;
6326 }
eb985f09 6327 adapter->restart_queue = restart_queue;
5b7da515
AD		 6328 adapter->tx_busy = tx_busy;
6329 netdev->stats.tx_bytes = bytes;
6330 netdev->stats.tx_packets = packets;
7ca3bc58 6331
7ca647bd 6332 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6333
6334 /* 8 register reads */
6f11eef7
AV		 6335 for (i = 0; i < 8; i++) {
6336 /* for packet buffers not used, the register should read 0 */
6337 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6338 missed_rx += mpc;
7ca647bd
JP		 6339 hwstats->mpc[i] += mpc;
6340 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6341 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6342 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6343 switch (hw->mac.type) {
6344 case ixgbe_mac_82598EB:
1a70db4b
ET		 6345 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6346 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6347 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6348 hwstats->pxonrxc[i] +=
6349 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6350 break;
6351 case ixgbe_mac_82599EB:
b93a2226 6352 case ixgbe_mac_X540:
9a75a1ac
DS		 6353 case ixgbe_mac_X550:
6354 case ixgbe_mac_X550EM_x:
bd508178
AD		 6355 hwstats->pxonrxc[i] +=
6356 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6357 break;
6358 default:
6359 break;
e8e26350 6360 }
6f11eef7 6361 }
1a70db4b
ET		 6362
6363 /*16 register reads */
6364 for (i = 0; i < 16; i++) {
6365 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6366 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6367 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6368 (hw->mac.type == ixgbe_mac_X540) ||
6369 (hw->mac.type == ixgbe_mac_X550) ||
6370 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6371 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6372 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6373 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6374 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6375 }
6376 }
6377
7ca647bd 6378 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6379 /* work around hardware counting issue */
7ca647bd 6380 hwstats->gprc -= missed_rx;
6f11eef7 6381
c84d324c
JF		 6382 ixgbe_update_xoff_received(adapter);
6383
6f11eef7 6384 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6385 switch (hw->mac.type) {
6386 case ixgbe_mac_82598EB:
6387 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6388 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6389 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6390 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6391 break;
b93a2226 6392 case ixgbe_mac_X540:
9a75a1ac
DS		 6393 case ixgbe_mac_X550:
6394 case ixgbe_mac_X550EM_x:
6395 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6396 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6397 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6398 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6399 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6400 case ixgbe_mac_82599EB:
a4d4f629
AD		 6401 for (i = 0; i < 16; i++)
6402 adapter->hw_rx_no_dma_resources +=
6403 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6404 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6405 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6406 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6407 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6408 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6409 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6410 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6411 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6412 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6413#ifdef IXGBE_FCOE
7ca647bd
JP		 6414 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6415 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6416 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6417 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6418 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6419 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6420 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6421 if (adapter->fcoe.ddp_pool) {
6422 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6423 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6424 unsigned int cpu;
6425 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6426 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6427 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6428 noddp += ddp_pool->noddp;
6429 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6430 }
5a1ee270
AD		 6431 hwstats->fcoe_noddp = noddp;
6432 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6433 }
6d45522c 6434#endif /* IXGBE_FCOE */
bd508178
AD		 6435 break;
6436 default:
6437 break;
e8e26350 6438 }
9a799d71 6439 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6440 hwstats->bprc += bprc;
6441 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6442 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6443 hwstats->mprc -= bprc;
6444 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6445 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6446 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6447 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6448 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6449 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6450 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6451 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6452 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6453 hwstats->lxontxc += lxon;
6f11eef7 6454 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6455 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6456 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6457 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6458 /*
6459 * 82598 errata - tx of flow control packets is included in tx counters
6460 */
6461 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6462 hwstats->gptc -= xon_off_tot;
6463 hwstats->mptc -= xon_off_tot;
6464 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6465 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6466 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6467 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6468 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6469 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6470 hwstats->ptc64 -= xon_off_tot;
6471 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6472 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6473 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6474 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6475 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6476 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6477
6478 /* Fill out the OS statistics structure */
7ca647bd 6479 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6480
6481 /* Rx Errors */
7ca647bd 6482 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6483 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6484 netdev->stats.rx_length_errors = hwstats->rlec;
6485 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6486 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6487}
6488
6489/**
d034acf1 6490 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6491 * @adapter: pointer to the device adapter structure
9a799d71 6492 **/
d034acf1 6493static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6494{
cf8280ee 6495 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6496 int i;
cf8280ee 6497
d034acf1
AD		 6498 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6499 return;
6500
6501 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6502
d034acf1 6503 /* if interface is down do nothing */
fe49f04a 6504 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6505 return;
6506
6507 /* do nothing if we are not using signature filters */
6508 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6509 return;
6510
6511 adapter->fdir_overflow++;
6512
93c52dd0
AD		 6513 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6514 for (i = 0; i < adapter->num_tx_queues; i++)
6515 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6516 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6517 /* re-enable flow director interrupts */
6518 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6519 } else {
6520 e_err(probe, "failed to finish FDIR re-initialization, "
6521 "ignored adding FDIR ATR filters\n");
6522 }
93c52dd0
AD		 6523}
6524
6525/**
6526 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6527 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6528 *
6529 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6530 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6531 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6532 * determine if a hang has occurred.
93c52dd0
AD		 6533 */
6534static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6535{
cf8280ee 6536 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6537 u64 eics = 0;
6538 int i;
cf8280ee 6539
09f40aed 6540 /* If we're down, removing or resetting, just bail */
93c52dd0 6541 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6542 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6543 test_bit(__IXGBE_RESETTING, &adapter->state))
6544 return;
22d5a71b 6545
93c52dd0
AD		 6546 /* Force detection of hung controller */
6547 if (netif_carrier_ok(adapter->netdev)) {
6548 for (i = 0; i < adapter->num_tx_queues; i++)
6549 set_check_for_tx_hang(adapter->tx_ring[i]);
6550 }
22d5a71b 6551
fe49f04a
AD		 6552 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6553 /*
6554 * for legacy and MSI interrupts don't set any bits
6555 * that are enabled for EIAM, because this operation
6556 * would set *both* EIMS and EICS for any bit in EIAM
6557 */
6558 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6559 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6560 } else {
6561 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6562 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6563 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6564 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6565 eics |= ((u64)1 << i);
6566 }
cf8280ee 6567 }
9a799d71 6568
93c52dd0 6569 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6570 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6571}
6572
e8e26350 6573/**
93c52dd0 6574 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6575 * @adapter: pointer to the device adapter structure
6576 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6577 **/
93c52dd0 6578static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6579{
e8e26350 6580 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6581 u32 link_speed = adapter->link_speed;
6582 bool link_up = adapter->link_up;
041441d0 6583 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6584
93c52dd0
AD		 6585 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6586 return;
6587
6588 if (hw->mac.ops.check_link) {
6589 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6590 } else {
93c52dd0
AD		 6591 /* always assume link is up, if no check link function */
6592 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6593 link_up = true;
c4cf55e5 6594 }
041441d0
AD		 6595
6596 if (adapter->ixgbe_ieee_pfc)
6597 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6598
3ebe8fde 6599 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6600 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6601 ixgbe_set_rx_drop_en(adapter);
6602 }
93c52dd0
AD		 6603
6604 if (link_up ||
6605 time_after(jiffies, (adapter->link_check_timeout +
6606 IXGBE_TRY_LINK_TIMEOUT))) {
6607 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6608 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6609 IXGBE_WRITE_FLUSH(hw);
6610 }
6611
6612 adapter->link_up = link_up;
6613 adapter->link_speed = link_speed;
e8e26350
PW		 6614}
6615
107d3018
AD		 6616static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6617{
6618#ifdef CONFIG_IXGBE_DCB
6619 struct net_device *netdev = adapter->netdev;
6620 struct dcb_app app = {
6621 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6622 .protocol = 0,
6623 };
6624 u8 up = 0;
6625
6626 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6627 up = dcb_ieee_getapp_mask(netdev, &app);
6628
6629 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6630#endif
6631}
6632
e8e26350 6633/**
93c52dd0
AD		 6634 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6635 * print link up message
49ce9c2c 6636 * @adapter: pointer to the device adapter structure
e8e26350 6637 **/
93c52dd0 6638static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6639{
93c52dd0 6640 struct net_device *netdev = adapter->netdev;
e8e26350 6641 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6642 struct net_device *upper;
6643 struct list_head *iter;
93c52dd0 6644 u32 link_speed = adapter->link_speed;
454adb00 6645 const char *speed_str;
93c52dd0 6646 bool flow_rx, flow_tx;
e8e26350 6647
93c52dd0
AD		 6648 /* only continue if link was previously down */
6649 if (netif_carrier_ok(netdev))
a985b6c3 6650 return;
63d6e1d8 6651
93c52dd0 6652 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6653
93c52dd0
AD		 6654 switch (hw->mac.type) {
6655 case ixgbe_mac_82598EB: {
6656 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6657 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6658 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6659 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6660 }
6661 break;
6662 case ixgbe_mac_X540:
9a75a1ac
DS		 6663 case ixgbe_mac_X550:
6664 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6665 case ixgbe_mac_82599EB: {
6666 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6667 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6668 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6669 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6670 }
6671 break;
6672 default:
6673 flow_tx = false;
6674 flow_rx = false;
6675 break;
e8e26350 6676 }
3a6a4eda 6677
6cb562d6
JK		 6678 adapter->last_rx_ptp_check = jiffies;
6679
8fecf67c 6680 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6681 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6682
454adb00
MR		 6683 switch (link_speed) {
6684 case IXGBE_LINK_SPEED_10GB_FULL:
6685 speed_str = "10 Gbps";
6686 break;
6687 case IXGBE_LINK_SPEED_2_5GB_FULL:
6688 speed_str = "2.5 Gbps";
6689 break;
6690 case IXGBE_LINK_SPEED_1GB_FULL:
6691 speed_str = "1 Gbps";
6692 break;
6693 case IXGBE_LINK_SPEED_100_FULL:
6694 speed_str = "100 Mbps";
6695 break;
6696 default:
6697 speed_str = "unknown speed";
6698 break;
6699 }
6700 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
93c52dd0
AD		 6701 ((flow_rx && flow_tx) ? "RX/TX" :
6702 (flow_rx ? "RX" :
6703 (flow_tx ? "TX" : "None"))));
e8e26350 6704
93c52dd0 6705 netif_carrier_on(netdev);
93c52dd0 6706 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6707
cdc04dcc
ET		 6708 /* enable transmits */
6709 netif_tx_wake_all_queues(adapter->netdev);
6710
6711 /* enable any upper devices */
6712 rtnl_lock();
6713 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6714 if (netif_is_macvlan(upper)) {
6715 struct macvlan_dev *vlan = netdev_priv(upper);
6716
6717 if (vlan->fwd_priv)
6718 netif_tx_wake_all_queues(upper);
6719 }
6720 }
6721 rtnl_unlock();
6722
107d3018
AD		 6723 /* update the default user priority for VFs */
6724 ixgbe_update_default_up(adapter);
6725
befa2af7
AD		 6726 /* ping all the active vfs to let them know link has changed */
6727 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6728}
6729
c4cf55e5 6730/**
93c52dd0
AD		 6731 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6732 * print link down message
49ce9c2c 6733 * @adapter: pointer to the adapter structure
c4cf55e5 6734 **/
581330ba 6735static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6736{
cf8280ee 6737 struct net_device *netdev = adapter->netdev;
c4cf55e5 6738 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6739
93c52dd0
AD		 6740 adapter->link_up = false;
6741 adapter->link_speed = 0;
cf8280ee 6742
93c52dd0
AD		 6743 /* only continue if link was up previously */
6744 if (!netif_carrier_ok(netdev))
6745 return;
264857b8 6746
93c52dd0
AD		 6747 /* poll for SFP+ cable when link is down */
6748 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6749 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6750
8fecf67c 6751 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6752 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6753
93c52dd0
AD		 6754 e_info(drv, "NIC Link is Down\n");
6755 netif_carrier_off(netdev);
befa2af7
AD		 6756
6757 /* ping all the active vfs to let them know link has changed */
6758 ixgbe_ping_all_vfs(adapter);
93c52dd0 6759}
e8e26350 6760
07923c17
ET		 6761static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6762{
6763 int i;
6764
6765 for (i = 0; i < adapter->num_tx_queues; i++) {
6766 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6767
6768 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6769 return true;
6770 }
6771
6772 return false;
6773}
6774
6775static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6776{
6777 struct ixgbe_hw *hw = &adapter->hw;
6778 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6779 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6780
6781 int i, j;
6782
6783 if (!adapter->num_vfs)
6784 return false;
6785
9a75a1ac
DS		 6786 /* resetting the PF is only needed for MAC before X550 */
6787 if (hw->mac.type >= ixgbe_mac_X550)
6788 return false;
6789
07923c17
ET		 6790 for (i = 0; i < adapter->num_vfs; i++) {
6791 for (j = 0; j < q_per_pool; j++) {
6792 u32 h, t;
6793
6794 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6795 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6796
6797 if (h != t)
6798 return true;
6799 }
6800 }
6801
6802 return false;
6803}
6804
93c52dd0
AD		 6805/**
6806 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6807 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6808 **/
6809static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6810{
93c52dd0 6811 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6812 if (ixgbe_ring_tx_pending(adapter) ||
6813 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6814 /* We've lost link, so the controller stops DMA,
6815 * but we've got queued Tx work that's never going
6816 * to get done, so reset controller to flush Tx.
6817 * (Do the reset outside of interrupt context).
6818 */
12ff3f3b 6819 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6820 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6821 }
c4cf55e5 6822 }
c4cf55e5
PWJ		 6823}
6824
9079e416
ET		 6825#ifdef CONFIG_PCI_IOV
6826static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6827 struct pci_dev *vfdev)
6828{
6829 if (!pci_wait_for_pending_transaction(vfdev))
6830 e_dev_warn("Issuing VFLR with pending transactions\n");
6831
6832 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6833 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6834
6835 msleep(100);
6836}
6837
6838static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6839{
6840 struct ixgbe_hw *hw = &adapter->hw;
6841 struct pci_dev *pdev = adapter->pdev;
988d1307 6842 unsigned int vf;
9079e416 6843 u32 gpc;
9079e416
ET		 6844
6845 if (!(netif_carrier_ok(adapter->netdev)))
6846 return;
6847
6848 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6849 if (gpc) /* If incrementing then no need for the check below */
6850 return;
6851 /* Check to see if a bad DMA write target from an errant or
6852 * malicious VF has caused a PCIe error. If so then we can
6853 * issue a VFLR to the offending VF(s) and then resume without
6854 * requesting a full slot reset.
6855 */
6856
6857 if (!pdev)
6858 return;
6859
9079e416 6860 /* check status reg for all VFs owned by this PF */
988d1307
MR		 6861 for (vf = 0; vf < adapter->num_vfs; ++vf) {
6862 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
6863 u16 status_reg;
9079e416 6864
988d1307
MR		 6865 if (!vfdev)
6866 continue;
6867 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6868 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
6869 status_reg & PCI_STATUS_REC_MASTER_ABORT)
6870 ixgbe_issue_vf_flr(adapter, vfdev);
9079e416
ET		 6871 }
6872}
6873
a985b6c3
GR		 6874static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6875{
6876 u32 ssvpc;
6877
0584d999
GR		 6878 /* Do not perform spoof check for 82598 or if not in IOV mode */
6879 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6880 adapter->num_vfs == 0)
a985b6c3
GR		 6881 return;
6882
6883 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6884
6885 /*
6886 * ssvpc register is cleared on read, if zero then no
6887 * spoofed packets in the last interval.
6888 */
6889 if (!ssvpc)
6890 return;
6891
d6ea0754 6892 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6893}
9079e416
ET		 6894#else
6895static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6896{
6897}
6898
6899static void
6900ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6901{
6902}
6903#endif /* CONFIG_PCI_IOV */
6904
a985b6c3 6905
93c52dd0
AD		 6906/**
6907 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6908 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6909 **/
6910static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6911{
09f40aed 6912 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6913 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6914 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6915 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6916 return;
6917
6918 ixgbe_watchdog_update_link(adapter);
6919
6920 if (adapter->link_up)
6921 ixgbe_watchdog_link_is_up(adapter);
6922 else
6923 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6924
9079e416 6925 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6926 ixgbe_spoof_check(adapter);
9a799d71 6927 ixgbe_update_stats(adapter);
93c52dd0
AD		 6928
6929 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6930}
10eec955 6931
cf8280ee 6932/**
7086400d 6933 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6934 * @adapter: the ixgbe adapter structure
cf8280ee 6935 **/
7086400d 6936static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6937{
cf8280ee 6938 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6939 s32 err;
cf8280ee 6940
7086400d
AD		 6941 /* not searching for SFP so there is nothing to do here */
6942 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6943 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6944 return;
10eec955 6945
58e7cd24
MR		 6946 if (adapter->sfp_poll_time &&
6947 time_after(adapter->sfp_poll_time, jiffies))
6948 return; /* If not yet time to poll for SFP */
6949
7086400d
AD		 6950 /* someone else is in init, wait until next service event */
6951 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6952 return;
cf8280ee 6953
58e7cd24
MR		 6954 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
6955
7086400d
AD		 6956 err = hw->phy.ops.identify_sfp(hw);
6957 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6958 goto sfp_out;
264857b8 6959
7086400d
AD		 6960 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6961 /* If no cable is present, then we need to reset
6962 * the next time we find a good cable. */
6963 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6964 }
9a799d71 6965
7086400d
AD		 6966 /* exit on error */
6967 if (err)
6968 goto sfp_out;
e8e26350 6969
7086400d
AD		 6970 /* exit if reset not needed */
6971 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6972 goto sfp_out;
9a799d71 6973
7086400d 6974 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6975
7086400d
AD		 6976 /*
6977 * A module may be identified correctly, but the EEPROM may not have
6978 * support for that module. setup_sfp() will fail in that case, so
6979 * we should not allow that module to load.
6980 */
6981 if (hw->mac.type == ixgbe_mac_82598EB)
6982 err = hw->phy.ops.reset(hw);
6983 else
6984 err = hw->mac.ops.setup_sfp(hw);
6985
6986 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6987 goto sfp_out;
6988
6989 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6990 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6991
6992sfp_out:
6993 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6994
6995 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6996 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6997 e_dev_err("failed to initialize because an unsupported "
6998 "SFP+ module type was detected.\n");
6999 e_dev_err("Reload the driver after installing a "
7000 "supported module.\n");
7001 unregister_netdev(adapter->netdev);
bc59fcda 7002 }
7086400d 7003}
bc59fcda 7004
7086400d
AD		 7005/**
7006 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 7007 * @adapter: the ixgbe adapter structure
7086400d
AD		 7008 **/
7009static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7010{
7011 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 7012 u32 speed;
7013 bool autoneg = false;
7086400d
AD		 7014
7015 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7016 return;
7017
7018 /* someone else is in init, wait until next service event */
7019 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7020 return;
7021
7022 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7023
3d292265 7024 speed = hw->phy.autoneg_advertised;
ed33ff66 7025 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 7026 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 7027
7028 /* setup the highest link when no autoneg */
7029 if (!autoneg) {
7030 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
7031 speed = IXGBE_LINK_SPEED_10GB_FULL;
7032 }
7033 }
7034
7086400d 7035 if (hw->mac.ops.setup_link)
fd0326f2 7036 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 7037
7038 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7039 adapter->link_check_timeout = jiffies;
7040 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7041}
7042
7043/**
7044 * ixgbe_service_timer - Timer Call-back
7045 * @data: pointer to adapter cast into an unsigned long
7046 **/
7047static void ixgbe_service_timer(unsigned long data)
7048{
7049 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
7050 unsigned long next_event_offset;
7051
6bb78cfb
AD		 7052 /* poll faster when waiting for link */
7053 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7054 next_event_offset = HZ / 10;
7055 else
7056 next_event_offset = HZ * 2;
83c61fa9 7057
7086400d
AD		 7058 /* Reset the timer */
7059 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7060
9079e416 7061 ixgbe_service_event_schedule(adapter);
7086400d
AD		 7062}
7063
597f22d6
DS		 7064static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7065{
7066 struct ixgbe_hw *hw = &adapter->hw;
7067 u32 status;
7068
7069 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7070 return;
7071
7072 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7073
7074 if (!hw->phy.ops.handle_lasi)
7075 return;
7076
7077 status = hw->phy.ops.handle_lasi(&adapter->hw);
7078 if (status != IXGBE_ERR_OVERTEMP)
7079 return;
7080
7081 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7082}
7083
c83c6cbd
AD		 7084static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7085{
7086 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
7087 return;
7088
7089 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
7090
09f40aed 7091 /* If we're already down, removing or resetting, just bail */
c83c6cbd 7092 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 7093 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 7094 test_bit(__IXGBE_RESETTING, &adapter->state))
7095 return;
7096
7097 ixgbe_dump(adapter);
7098 netdev_err(adapter->netdev, "Reset adapter\n");
7099 adapter->tx_timeout_count++;
7100
8f4c5c9f 7101 rtnl_lock();
c83c6cbd 7102 ixgbe_reinit_locked(adapter);
8f4c5c9f 7103 rtnl_unlock();
c83c6cbd
AD		 7104}
7105
7086400d
AD		 7106/**
7107 * ixgbe_service_task - manages and runs subtasks
7108 * @work: pointer to work_struct containing our data
7109 **/
7110static void ixgbe_service_task(struct work_struct *work)
7111{
7112 struct ixgbe_adapter *adapter = container_of(work,
7113 struct ixgbe_adapter,
7114 service_task);
b0483c8f
MR		 7115 if (ixgbe_removed(adapter->hw.hw_addr)) {
7116 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
7117 rtnl_lock();
7118 ixgbe_down(adapter);
7119 rtnl_unlock();
7120 }
7121 ixgbe_service_event_complete(adapter);
7122 return;
7123 }
67359c3c
MR		 7124#ifdef CONFIG_IXGBE_VXLAN
7125 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
7126 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
7127 vxlan_get_rx_port(adapter->netdev);
7128 }
7129#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 7130 ixgbe_reset_subtask(adapter);
597f22d6 7131 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 7132 ixgbe_sfp_detection_subtask(adapter);
7133 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 7134 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 7135 ixgbe_watchdog_subtask(adapter);
d034acf1 7136 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 7137 ixgbe_check_hang_subtask(adapter);
891dc082 7138
8fecf67c 7139 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 7140 ixgbe_ptp_overflow_check(adapter);
7141 ixgbe_ptp_rx_hang(adapter);
7142 }
7086400d
AD		 7143
7144 ixgbe_service_event_complete(adapter);
9a799d71
AK		 7145}
7146
fd0db0ed
AD		 7147static int ixgbe_tso(struct ixgbe_ring *tx_ring,
7148 struct ixgbe_tx_buffer *first,
244e27ad 7149 u8 *hdr_len)
897ab156 7150{
fd0db0ed 7151 struct sk_buff *skb = first->skb;
897ab156
AD		 7152 u32 vlan_macip_lens, type_tucmd;
7153 u32 mss_l4len_idx, l4len;
2049e1f6 7154 int err;
9a799d71 7155
8f4fbb9b
AD		 7156 if (skb->ip_summed != CHECKSUM_PARTIAL)
7157 return 0;
7158
897ab156
AD		 7159 if (!skb_is_gso(skb))
7160 return 0;
9a799d71 7161
2049e1f6
FR		 7162 err = skb_cow_head(skb, 0);
7163 if (err < 0)
7164 return err;
9a799d71 7165
897ab156
AD		 7166 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
7167 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
7168
a1108ffd 7169 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 7170 struct iphdr *iph = ip_hdr(skb);
7171 iph->tot_len = 0;
7172 iph->check = 0;
7173 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
7174 iph->daddr, 0,
7175 IPPROTO_TCP,
7176 0);
7177 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 7178 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7179 IXGBE_TX_FLAGS_CSUM |
7180 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 7181 } else if (skb_is_gso_v6(skb)) {
7182 ipv6_hdr(skb)->payload_len = 0;
7183 tcp_hdr(skb)->check =
7184 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
7185 &ipv6_hdr(skb)->daddr,
7186 0, IPPROTO_TCP, 0);
244e27ad
AD		 7187 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
7188 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 7189 }
7190
091a6246 7191 /* compute header lengths */
897ab156
AD		 7192 l4len = tcp_hdrlen(skb);
7193 *hdr_len = skb_transport_offset(skb) + l4len;
7194
091a6246
AD		 7195 /* update gso size and bytecount with header size */
7196 first->gso_segs = skb_shinfo(skb)->gso_segs;
7197 first->bytecount += (first->gso_segs - 1) * *hdr_len;
7198
c44f5f51 7199 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 7200 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
7201 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 7202
7203 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
7204 vlan_macip_lens = skb_network_header_len(skb);
7205 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 7206 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 7207
7208 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 7209 mss_l4len_idx);
897ab156
AD		 7210
7211 return 1;
7212}
7213
244e27ad
AD		 7214static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
7215 struct ixgbe_tx_buffer *first)
7ca647bd 7216{
fd0db0ed 7217 struct sk_buff *skb = first->skb;
897ab156
AD		 7218 u32 vlan_macip_lens = 0;
7219 u32 mss_l4len_idx = 0;
7220 u32 type_tucmd = 0;
7ca647bd 7221
897ab156 7222 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 7223 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
7224 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
7225 return;
f467bc06
MR		 7226 vlan_macip_lens = skb_network_offset(skb) <<
7227 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 7228 } else {
7229 u8 l4_hdr = 0;
f467bc06
MR		 7230 union {
7231 struct iphdr *ipv4;
7232 struct ipv6hdr *ipv6;
7233 u8 *raw;
7234 } network_hdr;
7235 union {
7236 struct tcphdr *tcphdr;
7237 u8 *raw;
7238 } transport_hdr;
36a92d71 7239 __be16 frag_off;
f467bc06
MR		 7240
7241 if (skb->encapsulation) {
7242 network_hdr.raw = skb_inner_network_header(skb);
7243 transport_hdr.raw = skb_inner_transport_header(skb);
7244 vlan_macip_lens = skb_inner_network_offset(skb) <<
7245 IXGBE_ADVTXD_MACLEN_SHIFT;
7246 } else {
7247 network_hdr.raw = skb_network_header(skb);
7248 transport_hdr.raw = skb_transport_header(skb);
7249 vlan_macip_lens = skb_network_offset(skb) <<
7250 IXGBE_ADVTXD_MACLEN_SHIFT;
7251 }
7252
7253 /* use first 4 bits to determine IP version */
7254 switch (network_hdr.ipv4->version) {
7255 case IPVERSION:
7256 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 7257 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 7258 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 7259 break;
f467bc06
MR		 7260 case 6:
7261 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
7262 l4_hdr = network_hdr.ipv6->nexthdr;
36a92d71
MR		 7263 if (likely((transport_hdr.raw - network_hdr.raw) ==
7264 sizeof(struct ipv6hdr)))
7265 break;
7266 ipv6_skip_exthdr(skb, network_hdr.raw - skb->data +
7267 sizeof(struct ipv6hdr),
7268 &l4_hdr, &frag_off);
7269 if (unlikely(frag_off))
7270 l4_hdr = NEXTHDR_FRAGMENT;
897ab156
AD		 7271 break;
7272 default:
36a92d71 7273 break;
7ca647bd 7274 }
897ab156
AD		 7275
7276 switch (l4_hdr) {
7ca647bd 7277 case IPPROTO_TCP:
897ab156 7278 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7279 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7280 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7281 break;
7282 case IPPROTO_SCTP:
897ab156
AD		 7283 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7284 mss_l4len_idx = sizeof(struct sctphdr) <<
7285 IXGBE_ADVTXD_L4LEN_SHIFT;
7286 break;
7287 case IPPROTO_UDP:
7288 mss_l4len_idx = sizeof(struct udphdr) <<
7289 IXGBE_ADVTXD_L4LEN_SHIFT;
7290 break;
7291 default:
7292 if (unlikely(net_ratelimit())) {
7293 dev_warn(tx_ring->dev,
36a92d71
MR		 7294 "partial checksum, version=%d, l4 proto=%x\n",
7295 network_hdr.ipv4->version, l4_hdr);
897ab156 7296 }
36a92d71
MR		 7297 skb_checksum_help(skb);
7298 goto no_csum;
7ca647bd 7299 }
244e27ad
AD		 7300
7301 /* update TX checksum flag */
7302 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7303 }
7304
36a92d71 7305no_csum:
244e27ad 7306 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7307 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7308
897ab156
AD		 7309 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7310 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7311}
7312
472148c3
AD		 7313#define IXGBE_SET_FLAG(_input, _flag, _result) \
7314 ((_flag <= _result) ? \
7315 ((u32)(_input & _flag) * (_result / _flag)) : \
7316 ((u32)(_input & _flag) / (_flag / _result)))
7317
7318static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7319{
d3d00239 7320 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7321 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7322 IXGBE_ADVTXD_DCMD_DEXT |
7323 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7324
d3d00239 7325 /* set HW vlan bit if vlan is present */
472148c3
AD		 7326 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7327 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7328
d3d00239 7329 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7330 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7331 IXGBE_ADVTXD_DCMD_TSE);
7332
7333 /* set timestamp bit if present */
7334 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7335 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7336
62748b7b 7337 /* insert frame checksum */
472148c3 7338 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7339
d3d00239
AD		 7340 return cmd_type;
7341}
9a799d71 7342
729739b7
AD		 7343static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7344 u32 tx_flags, unsigned int paylen)
d3d00239 7345{
472148c3 7346 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7347
d3d00239 7348 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7349 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7350 IXGBE_TX_FLAGS_CSUM,
7351 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7352
93f5b3c1 7353 /* enble IPv4 checksum for TSO */
472148c3
AD		 7354 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7355 IXGBE_TX_FLAGS_IPV4,
7356 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7357
7f9643fd
AD		 7358 /*
7359 * Check Context must be set if Tx switch is enabled, which it
7360 * always is for case where virtual functions are running
7361 */
472148c3
AD		 7362 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7363 IXGBE_TX_FLAGS_CC,
7364 IXGBE_ADVTXD_CC);
7f9643fd 7365
472148c3 7366 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7367}
44df32c5 7368
2367a173
DB		 7369static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7370{
7371 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7372
7373 /* Herbert's original patch had:
7374 * smp_mb__after_netif_stop_queue();
7375 * but since that doesn't exist yet, just open code it.
7376 */
7377 smp_mb();
7378
7379 /* We need to check again in a case another CPU has just
7380 * made room available.
7381 */
7382 if (likely(ixgbe_desc_unused(tx_ring) < size))
7383 return -EBUSY;
7384
7385 /* A reprieve! - use start_queue because it doesn't call schedule */
7386 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7387 ++tx_ring->tx_stats.restart_queue;
7388 return 0;
7389}
7390
7391static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7392{
7393 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7394 return 0;
7395
7396 return __ixgbe_maybe_stop_tx(tx_ring, size);
7397}
7398
d3d00239
AD		 7399#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7400 IXGBE_TXD_CMD_RS)
7401
7402static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7403 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7404 const u8 hdr_len)
7405{
fd0db0ed 7406 struct sk_buff *skb = first->skb;
729739b7 7407 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7408 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7409 struct skb_frag_struct *frag;
7410 dma_addr_t dma;
7411 unsigned int data_len, size;
244e27ad 7412 u32 tx_flags = first->tx_flags;
472148c3 7413 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7414 u16 i = tx_ring->next_to_use;
d3d00239 7415
729739b7
AD		 7416 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7417
ec718254
AD		 7418 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7419
7420 size = skb_headlen(skb);
7421 data_len = skb->data_len;
729739b7 7422
d3d00239
AD		 7423#ifdef IXGBE_FCOE
7424 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7425 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7426 size -= sizeof(struct fcoe_crc_eof) - data_len;
7427 data_len = 0;
729739b7
AD		 7428 } else {
7429 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7430 }
7431 }
44df32c5 7432
d3d00239 7433#endif
729739b7 7434 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7435
ec718254 7436 tx_buffer = first;
9a799d71 7437
ec718254
AD		 7438 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7439 if (dma_mapping_error(tx_ring->dev, dma))
7440 goto dma_error;
7441
7442 /* record length, and DMA address */
7443 dma_unmap_len_set(tx_buffer, len, size);
7444 dma_unmap_addr_set(tx_buffer, dma, dma);
7445
7446 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7447
729739b7 7448 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7449 tx_desc->read.cmd_type_len =
472148c3 7450 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7451
d3d00239 7452 i++;
729739b7 7453 tx_desc++;
d3d00239 7454 if (i == tx_ring->count) {
e4f74028 7455 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7456 i = 0;
7457 }
ec718254 7458 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7459
7460 dma += IXGBE_MAX_DATA_PER_TXD;
7461 size -= IXGBE_MAX_DATA_PER_TXD;
7462
7463 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7464 }
e5a43549 7465
729739b7
AD		 7466 if (likely(!data_len))
7467 break;
9a799d71 7468
472148c3 7469 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7470
729739b7
AD		 7471 i++;
7472 tx_desc++;
7473 if (i == tx_ring->count) {
7474 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7475 i = 0;
7476 }
ec718254 7477 tx_desc->read.olinfo_status = 0;
9a799d71 7478
d3d00239 7479#ifdef IXGBE_FCOE
9e903e08 7480 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7481#else
9e903e08 7482 size = skb_frag_size(frag);
d3d00239
AD		 7483#endif
7484 data_len -= size;
9a799d71 7485
729739b7
AD		 7486 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7487 DMA_TO_DEVICE);
9a799d71 7488
729739b7 7489 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7490 }
9a799d71 7491
729739b7 7492 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7493 cmd_type |= size | IXGBE_TXD_CMD;
7494 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7495
091a6246 7496 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7497
d3d00239
AD		 7498 /* set the timestamp */
7499 first->time_stamp = jiffies;
9a799d71
AK		 7500
7501 /*
729739b7
AD		 7502 * Force memory writes to complete before letting h/w know there
7503 * are new descriptors to fetch. (Only applicable for weak-ordered
7504 * memory model archs, such as IA-64).
7505 *
7506 * We also need this memory barrier to make certain all of the
7507 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7508 */
7509 wmb();
7510
d3d00239
AD		 7511 /* set next_to_watch value indicating a packet is present */
7512 first->next_to_watch = tx_desc;
7513
729739b7
AD		 7514 i++;
7515 if (i == tx_ring->count)
7516 i = 0;
7517
7518 tx_ring->next_to_use = i;
7519
2367a173
DB		 7520 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7521
7522 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7523 writel(i, tx_ring->tail);
7524
7525 /* we need this if more than one processor can write to our tail
7526 * at a time, it synchronizes IO on IA64/Altix systems
7527 */
7528 mmiowb();
9c938cdd 7529 }
2367a173 7530
d3d00239
AD		 7531 return;
7532dma_error:
729739b7 7533 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7534
7535 /* clear dma mappings for failed tx_buffer_info map */
7536 for (;;) {
729739b7
AD		 7537 tx_buffer = &tx_ring->tx_buffer_info[i];
7538 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7539 if (tx_buffer == first)
d3d00239
AD		 7540 break;
7541 if (i == 0)
7542 i = tx_ring->count;
7543 i--;
7544 }
7545
d3d00239 7546 tx_ring->next_to_use = i;
9a799d71
AK		 7547}
7548
fd0db0ed 7549static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7550 struct ixgbe_tx_buffer *first)
69830529
AD		 7551{
7552 struct ixgbe_q_vector *q_vector = ring->q_vector;
7553 union ixgbe_atr_hash_dword input = { .dword = 0 };
7554 union ixgbe_atr_hash_dword common = { .dword = 0 };
7555 union {
7556 unsigned char *network;
7557 struct iphdr *ipv4;
7558 struct ipv6hdr *ipv6;
7559 } hdr;
ee9e0f0b 7560 struct tcphdr *th;
67359c3c 7561 struct sk_buff *skb;
905e4a41 7562 __be16 vlan_id;
c4cf55e5 7563
69830529
AD		 7564 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7565 if (!q_vector)
7566 return;
7567
7568 /* do nothing if sampling is disabled */
7569 if (!ring->atr_sample_rate)
d3ead241 7570 return;
c4cf55e5 7571
69830529 7572 ring->atr_count++;
c4cf55e5 7573
69830529 7574 /* snag network header to get L4 type and address */
67359c3c
MR		 7575 skb = first->skb;
7576 hdr.network = skb_network_header(skb);
9f12df90 7577 th = tcp_hdr(skb);
67359c3c 7578#ifdef CONFIG_IXGBE_VXLAN
9f12df90
AD		 7579 if (skb->encapsulation &&
7580 first->protocol == htons(ETH_P_IP) &&
7581 hdr.ipv4->protocol != IPPROTO_UDP) {
67359c3c 7582 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7583
9f12df90
AD		 7584 /* verify the port is recognized as VXLAN */
7585 if (adapter->vxlan_port &&
7586 udp_hdr(skb)->dest == adapter->vxlan_port) {
7587 hdr.network = skb_inner_network_header(skb);
7588 th = inner_tcp_hdr(skb);
67359c3c 7589 }
e19dcdeb 7590 }
9f12df90 7591#endif /* CONFIG_IXGBE_VXLAN */
e19dcdeb
MR		 7592
7593 /* Currently only IPv4/IPv6 with TCP is supported */
7594 switch (hdr.ipv4->version) {
7595 case IPVERSION:
7596 if (hdr.ipv4->protocol != IPPROTO_TCP)
67359c3c 7597 return;
e19dcdeb
MR		 7598 break;
7599 case 6:
7600 if (likely((unsigned char *)th - hdr.network ==
7601 sizeof(struct ipv6hdr))) {
7602 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
7603 return;
7604 } else {
7605 __be16 frag_off;
7606 u8 l4_hdr;
7607
7608 ipv6_skip_exthdr(skb, hdr.network - skb->data +
7609 sizeof(struct ipv6hdr),
7610 &l4_hdr, &frag_off);
7611 if (unlikely(frag_off))
7612 return;
7613 if (l4_hdr != IPPROTO_TCP)
7614 return;
7615 }
7616 break;
7617 default:
7618 return;
67359c3c 7619 }
c4cf55e5 7620
66f32a8b
AD		 7621 /* skip this packet since it is invalid or the socket is closing */
7622 if (!th || th->fin)
69830529
AD		 7623 return;
7624
7625 /* sample on all syn packets or once every atr sample count */
7626 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7627 return;
7628
7629 /* reset sample count */
7630 ring->atr_count = 0;
7631
244e27ad 7632 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7633
7634 /*
7635 * src and dst are inverted, think how the receiver sees them
7636 *
7637 * The input is broken into two sections, a non-compressed section
7638 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7639 * is XORed together and stored in the compressed dword.
7640 */
7641 input.formatted.vlan_id = vlan_id;
7642
7643 /*
7644 * since src port and flex bytes occupy the same word XOR them together
7645 * and write the value to source port portion of compressed dword
7646 */
244e27ad 7647 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7648 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7649 else
244e27ad 7650 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7651 common.port.dst ^= th->source;
7652
e19dcdeb
MR		 7653 switch (hdr.ipv4->version) {
7654 case IPVERSION:
69830529
AD		 7655 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7656 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
e19dcdeb
MR		 7657 break;
7658 case 6:
69830529
AD		 7659 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7660 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7661 hdr.ipv6->saddr.s6_addr32[1] ^
7662 hdr.ipv6->saddr.s6_addr32[2] ^
7663 hdr.ipv6->saddr.s6_addr32[3] ^
7664 hdr.ipv6->daddr.s6_addr32[0] ^
7665 hdr.ipv6->daddr.s6_addr32[1] ^
7666 hdr.ipv6->daddr.s6_addr32[2] ^
7667 hdr.ipv6->daddr.s6_addr32[3];
e19dcdeb
MR		 7668 break;
7669 default:
7670 break;
69830529 7671 }
c4cf55e5 7672
9f12df90 7673 if (hdr.network != skb_network_header(skb))
67359c3c 7674 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
67359c3c 7675
c4cf55e5 7676 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7677 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7678 input, common, ring->queue_index);
c4cf55e5
PWJ		 7679}
7680
f663dd9a 7681static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7682 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7683{
f663dd9a
JW		 7684 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7685#ifdef IXGBE_FCOE
97488bd1
AD		 7686 struct ixgbe_adapter *adapter;
7687 struct ixgbe_ring_feature *f;
7688 int txq;
f663dd9a
JW		 7689#endif
7690
7691 if (fwd_adapter)
7692 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7693
7694#ifdef IXGBE_FCOE
5e09a105 7695
97488bd1
AD		 7696 /*
7697 * only execute the code below if protocol is FCoE
7698 * or FIP and we have FCoE enabled on the adapter
7699 */
7700 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7701 case htons(ETH_P_FCOE):
7702 case htons(ETH_P_FIP):
97488bd1 7703 adapter = netdev_priv(dev);
c087663e 7704
97488bd1
AD		 7705 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7706 break;
7707 default:
99932d4f 7708 return fallback(dev, skb);
97488bd1 7709 }
c087663e 7710
97488bd1 7711 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7712
97488bd1
AD		 7713 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7714 smp_processor_id();
56075a98 7715
97488bd1
AD		 7716 while (txq >= f->indices)
7717 txq -= f->indices;
c4cf55e5 7718
97488bd1 7719 return txq + f->offset;
f663dd9a 7720#else
99932d4f 7721 return fallback(dev, skb);
f663dd9a 7722#endif
09a3b1f8
SH		 7723}
7724
fc77dc3c 7725netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7726 struct ixgbe_adapter *adapter,
7727 struct ixgbe_ring *tx_ring)
9a799d71 7728{
d3d00239 7729 struct ixgbe_tx_buffer *first;
5f715823 7730 int tso;
d3d00239 7731 u32 tx_flags = 0;
a535c30e 7732 unsigned short f;
a535c30e 7733 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7734 __be16 protocol = skb->protocol;
63544e9c 7735 u8 hdr_len = 0;
5e09a105 7736
a535c30e
AD		 7737 /*
7738 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7739 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7740 * + 2 desc gap to keep tail from touching head,
7741 * + 1 desc for context descriptor,
7742 * otherwise try next time
7743 */
a535c30e
AD		 7744 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7745 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7746
a535c30e
AD		 7747 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7748 tx_ring->tx_stats.tx_busy++;
7749 return NETDEV_TX_BUSY;
7750 }
7751
fd0db0ed
AD		 7752 /* record the location of the first descriptor for this packet */
7753 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7754 first->skb = skb;
091a6246
AD		 7755 first->bytecount = skb->len;
7756 first->gso_segs = 1;
fd0db0ed 7757
66f32a8b 7758 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7759 if (skb_vlan_tag_present(skb)) {
7760 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7761 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7762 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7763 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7764 struct vlan_hdr *vhdr, _vhdr;
7765 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7766 if (!vhdr)
7767 goto out_drop;
7768
9e0c5648
AD		 7769 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7770 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7771 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7772 }
0213668f 7773 protocol = vlan_get_protocol(skb);
66f32a8b 7774
d5234933
MR		 7775 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7776 adapter->ptp_clock &&
7777 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7778 &adapter->state)) {
3a6a4eda
JK		 7779 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7780 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7781
7782 /* schedule check for Tx timestamp */
7783 adapter->ptp_tx_skb = skb_get(skb);
7784 adapter->ptp_tx_start = jiffies;
7785 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7786 }
3a6a4eda 7787
ff29a86e
JK		 7788 skb_tx_timestamp(skb);
7789
9e0c5648
AD		 7790#ifdef CONFIG_PCI_IOV
7791 /*
7792 * Use the l2switch_enable flag - would be false if the DMA
7793 * Tx switch had been disabled.
7794 */
7795 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7796 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7797
7798#endif
32701dc2 7799 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7800 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7801 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7802 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7803 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7804 tx_flags |= (skb->priority & 0x7) <<
7805 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7806 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7807 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7808
7809 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7810 goto out_drop;
7811 vhdr = (struct vlan_ethhdr *)skb->data;
7812 vhdr->h_vlan_TCI = htons(tx_flags >>
7813 IXGBE_TX_FLAGS_VLAN_SHIFT);
7814 } else {
7815 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7816 }
9a799d71 7817 }
eacd73f7 7818
244e27ad
AD		 7819 /* record initial flags and protocol */
7820 first->tx_flags = tx_flags;
7821 first->protocol = protocol;
7822
eacd73f7 7823#ifdef IXGBE_FCOE
66f32a8b 7824 /* setup tx offload for FCoE */
a1108ffd 7825 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7826 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7827 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7828 if (tso < 0)
7829 goto out_drop;
9a799d71 7830
66f32a8b 7831 goto xmit_fcoe;
eacd73f7 7832 }
9a799d71 7833
66f32a8b 7834#endif /* IXGBE_FCOE */
244e27ad 7835 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7836 if (tso < 0)
897ab156 7837 goto out_drop;
244e27ad
AD		 7838 else if (!tso)
7839 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7840
7841 /* add the ATR filter if ATR is on */
7842 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7843 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7844
7845#ifdef IXGBE_FCOE
7846xmit_fcoe:
7847#endif /* IXGBE_FCOE */
244e27ad 7848 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7849
9a799d71 7850 return NETDEV_TX_OK;
897ab156
AD		 7851
7852out_drop:
fd0db0ed
AD		 7853 dev_kfree_skb_any(first->skb);
7854 first->skb = NULL;
7855
897ab156 7856 return NETDEV_TX_OK;
9a799d71
AK		 7857}
7858
2a47fa45
JF		 7859static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7860 struct net_device *netdev,
7861 struct ixgbe_ring *ring)
84418e3b
AD		 7862{
7863 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7864 struct ixgbe_ring *tx_ring;
7865
a50c29dd
AD		 7866 /*
7867 * The minimum packet size for olinfo paylen is 17 so pad the skb
7868 * in order to meet this minimum size requirement.
7869 */
a94d9e22
AD		 7870 if (skb_put_padto(skb, 17))
7871 return NETDEV_TX_OK;
a50c29dd 7872
2a47fa45
JF		 7873 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7874
fc77dc3c 7875 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7876}
7877
2a47fa45
JF		 7878static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7879 struct net_device *netdev)
7880{
7881 return __ixgbe_xmit_frame(skb, netdev, NULL);
7882}
7883
9a799d71
AK		 7884/**
7885 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7886 * @netdev: network interface device structure
7887 * @p: pointer to an address structure
7888 *
7889 * Returns 0 on success, negative on failure
7890 **/
7891static int ixgbe_set_mac(struct net_device *netdev, void *p)
7892{
7893 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7894 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7895 struct sockaddr *addr = p;
7896
7897 if (!is_valid_ether_addr(addr->sa_data))
7898 return -EADDRNOTAVAIL;
7899
7900 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7901 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7902
c9f53e63
AD		 7903 ixgbe_mac_set_default_filter(adapter);
7904
7905 return 0;
9a799d71
AK		 7906}
7907
6b73e10d
BH		 7908static int
7909ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7910{
7911 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7912 struct ixgbe_hw *hw = &adapter->hw;
7913 u16 value;
7914 int rc;
7915
7916 if (prtad != hw->phy.mdio.prtad)
7917 return -EINVAL;
7918 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7919 if (!rc)
7920 rc = value;
7921 return rc;
7922}
7923
7924static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7925 u16 addr, u16 value)
7926{
7927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7928 struct ixgbe_hw *hw = &adapter->hw;
7929
7930 if (prtad != hw->phy.mdio.prtad)
7931 return -EINVAL;
7932 return hw->phy.ops.write_reg(hw, addr, devad, value);
7933}
7934
7935static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7936{
7937 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7938
3a6a4eda 7939 switch (cmd) {
3a6a4eda 7940 case SIOCSHWTSTAMP:
93501d48
JK		 7941 return ixgbe_ptp_set_ts_config(adapter, req);
7942 case SIOCGHWTSTAMP:
7943 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7944 default:
7945 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7946 }
6b73e10d
BH		 7947}
7948
0365e6e4
PW		 7949/**
7950 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7951 * netdev->dev_addrs
0365e6e4
PW		 7952 * @netdev: network interface device structure
7953 *
7954 * Returns non-zero on failure
7955 **/
7956static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7957{
7958 int err = 0;
7959 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7960 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7961
7fa7c9dc 7962 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7963 rtnl_lock();
7fa7c9dc 7964 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7965 rtnl_unlock();
7fa7c9dc
AD		 7966
7967 /* update SAN MAC vmdq pool selection */
7968 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7969 }
7970 return err;
7971}
7972
7973/**
7974 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7975 * netdev->dev_addrs
0365e6e4
PW		 7976 * @netdev: network interface device structure
7977 *
7978 * Returns non-zero on failure
7979 **/
7980static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7981{
7982 int err = 0;
7983 struct ixgbe_adapter *adapter = netdev_priv(dev);
7984 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7985
7986 if (is_valid_ether_addr(mac->san_addr)) {
7987 rtnl_lock();
7988 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7989 rtnl_unlock();
7990 }
7991 return err;
7992}
7993
9a799d71
AK		 7994#ifdef CONFIG_NET_POLL_CONTROLLER
7995/*
7996 * Polling 'interrupt' - used by things like netconsole to send skbs
7997 * without having to re-enable interrupts. It's not called while
7998 * the interrupt routine is executing.
7999 */
8000static void ixgbe_netpoll(struct net_device *netdev)
8001{
8002 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 8003 int i;
9a799d71 8004
1a647bd2
AD		 8005 /* if interface is down do nothing */
8006 if (test_bit(__IXGBE_DOWN, &adapter->state))
8007 return;
8008
856f606e
AD		 8009 /* loop through and schedule all active queues */
8010 for (i = 0; i < adapter->num_q_vectors; i++)
8011 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 8012}
9a799d71 8013
581330ba 8014#endif
de1036b1
ED		 8015static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
8016 struct rtnl_link_stats64 *stats)
8017{
8018 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8019 int i;
8020
1a51502b 8021 rcu_read_lock();
de1036b1 8022 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 8023 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 8024 u64 bytes, packets;
8025 unsigned int start;
8026
1a51502b
ED		 8027 if (ring) {
8028 do {
57a7744e 8029 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 8030 packets = ring->stats.packets;
8031 bytes = ring->stats.bytes;
57a7744e 8032 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 8033 stats->rx_packets += packets;
8034 stats->rx_bytes += bytes;
8035 }
de1036b1 8036 }
1ac9ad13
ED		 8037
8038 for (i = 0; i < adapter->num_tx_queues; i++) {
8039 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
8040 u64 bytes, packets;
8041 unsigned int start;
8042
8043 if (ring) {
8044 do {
57a7744e 8045 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 8046 packets = ring->stats.packets;
8047 bytes = ring->stats.bytes;
57a7744e 8048 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 8049 stats->tx_packets += packets;
8050 stats->tx_bytes += bytes;
8051 }
8052 }
1a51502b 8053 rcu_read_unlock();
de1036b1
ED		 8054 /* following stats updated by ixgbe_watchdog_task() */
8055 stats->multicast = netdev->stats.multicast;
8056 stats->rx_errors = netdev->stats.rx_errors;
8057 stats->rx_length_errors = netdev->stats.rx_length_errors;
8058 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
8059 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
8060 return stats;
8061}
8062
8af3c33f 8063#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 8064/**
8065 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
8066 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 8067 * @tc: number of traffic classes currently enabled
8068 *
8069 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
8070 * 802.1Q priority maps to a packet buffer that exists.
8071 */
8072static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
8073{
8074 struct ixgbe_hw *hw = &adapter->hw;
8075 u32 reg, rsave;
8076 int i;
8077
8078 /* 82598 have a static priority to TC mapping that can not
8079 * be changed so no validation is needed.
8080 */
8081 if (hw->mac.type == ixgbe_mac_82598EB)
8082 return;
8083
8084 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
8085 rsave = reg;
8086
8087 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
8088 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
8089
8090 /* If up2tc is out of bounds default to zero */
8091 if (up2tc > tc)
8092 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
8093 }
8094
8095 if (reg != rsave)
8096 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
8097
8098 return;
8099}
8100
02debdc9
AD		 8101/**
8102 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
8103 * @adapter: Pointer to adapter struct
8104 *
8105 * Populate the netdev user priority to tc map
8106 */
8107static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
8108{
8109 struct net_device *dev = adapter->netdev;
8110 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
8111 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
8112 u8 prio;
8113
8114 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
8115 u8 tc = 0;
8116
8117 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
8118 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
8119 else if (ets)
8120 tc = ets->prio_tc[prio];
8121
8122 netdev_set_prio_tc_map(dev, prio, tc);
8123 }
8124}
8125
cca73c59 8126#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 8127/**
8128 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 8129 *
8130 * @netdev: net device to configure
8131 * @tc: number of traffic classes to enable
8132 */
8133int ixgbe_setup_tc(struct net_device *dev, u8 tc)
8134{
8b1c0b24
JF		 8135 struct ixgbe_adapter *adapter = netdev_priv(dev);
8136 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 8137 bool pools;
8b1c0b24 8138
8b1c0b24 8139 /* Hardware supports up to 8 traffic classes */
7e3f5c88
ET		 8140 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
8141 return -EINVAL;
8142
8143 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
8b1c0b24
JF		 8144 return -EINVAL;
8145
2a47fa45
JF		 8146 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
8147 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
8148 return -EBUSY;
8149
8b1c0b24 8150 /* Hardware has to reinitialize queues and interrupts to
52f33af8 8151 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 8152 * hardware is not flexible enough to do this dynamically.
8153 */
8154 if (netif_running(dev))
8155 ixgbe_close(dev);
bf4d67d9
AD		 8156 else
8157 ixgbe_reset(adapter);
8158
8b1c0b24
JF		 8159 ixgbe_clear_interrupt_scheme(adapter);
8160
cca73c59 8161#ifdef CONFIG_IXGBE_DCB
e7589eab 8162 if (tc) {
8b1c0b24 8163 netdev_set_num_tc(dev, tc);
02debdc9
AD		 8164 ixgbe_set_prio_tc_map(adapter);
8165
e7589eab 8166 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 8167
943561d3
AD		 8168 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
8169 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 8170 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 8171 }
e7589eab 8172 } else {
8b1c0b24 8173 netdev_reset_tc(dev);
02debdc9 8174
943561d3
AD		 8175 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8176 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 8177
8178 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 8179
8180 adapter->temp_dcb_cfg.pfc_mode_enable = false;
8181 adapter->dcb_cfg.pfc_mode_enable = false;
8182 }
8183
8b1c0b24 8184 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 8185
8186#endif /* CONFIG_IXGBE_DCB */
8187 ixgbe_init_interrupt_scheme(adapter);
8188
8b1c0b24 8189 if (netif_running(dev))
cca73c59 8190 return ixgbe_open(dev);
8b1c0b24
JF		 8191
8192 return 0;
8193}
de1036b1 8194
b82b17d9
JF		 8195static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
8196 struct tc_cls_u32_offload *cls)
8197{
8198 int err;
8199
8200 spin_lock(&adapter->fdir_perfect_lock);
8201 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, cls->knode.handle);
8202 spin_unlock(&adapter->fdir_perfect_lock);
8203 return err;
8204}
8205
db956ae8
JF		 8206static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
8207 __be16 protocol,
8208 struct tc_cls_u32_offload *cls)
8209{
8210 /* This ixgbe devices do not support hash tables at the moment
8211 * so abort when given hash tables.
8212 */
8213 if (cls->hnode.divisor > 0)
8214 return -EINVAL;
8215
8216 set_bit(TC_U32_USERHTID(cls->hnode.handle), &adapter->tables);
8217 return 0;
8218}
8219
8220static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
8221 struct tc_cls_u32_offload *cls)
8222{
8223 clear_bit(TC_U32_USERHTID(cls->hnode.handle), &adapter->tables);
8224 return 0;
8225}
8226
b82b17d9
JF		 8227static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
8228 __be16 protocol,
8229 struct tc_cls_u32_offload *cls)
8230{
8231 u32 loc = cls->knode.handle & 0xfffff;
8232 struct ixgbe_hw *hw = &adapter->hw;
8233 struct ixgbe_mat_field *field_ptr;
8234 struct ixgbe_fdir_filter *input;
8235 union ixgbe_atr_input mask;
8236#ifdef CONFIG_NET_CLS_ACT
8237 const struct tc_action *a;
8238#endif
8239 int i, err = 0;
8240 u8 queue;
8241 u32 handle;
8242
8243 memset(&mask, 0, sizeof(union ixgbe_atr_input));
8244 handle = cls->knode.handle;
8245
8246 /* At the moment cls_u32 jumps to transport layer and skips past
8247 * L2 headers. The canonical method to match L2 frames is to use
8248 * negative values. However this is error prone at best but really
8249 * just broken because there is no way to "know" what sort of hdr
8250 * is in front of the transport layer. Fix cls_u32 to support L2
8251 * headers when needed.
8252 */
8253 if (protocol != htons(ETH_P_IP))
8254 return -EINVAL;
8255
8256 if (cls->knode.link_handle ||
8257 cls->knode.link_handle >= IXGBE_MAX_LINK_HANDLE) {
8258 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
8259 u32 uhtid = TC_U32_USERHTID(cls->knode.link_handle);
8260
db956ae8
JF		 8261 if (!test_bit(uhtid, &adapter->tables))
8262 return -EINVAL;
8263
b82b17d9
JF		 8264 for (i = 0; nexthdr[i].jump; i++) {
8265 if (nexthdr->o != cls->knode.sel->offoff ||
8266 nexthdr->s != cls->knode.sel->offshift ||
8267 nexthdr->m != cls->knode.sel->offmask ||
8268 /* do not support multiple key jumps its just mad */
8269 cls->knode.sel->nkeys > 1)
8270 return -EINVAL;
8271
8272 if (nexthdr->off != cls->knode.sel->keys[0].off ||
8273 nexthdr->val != cls->knode.sel->keys[0].val ||
8274 nexthdr->mask != cls->knode.sel->keys[0].mask)
8275 return -EINVAL;
8276
8277 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
8278 return -EINVAL;
8279
8280 adapter->jump_tables[uhtid] = nexthdr->jump;
8281 }
8282 return 0;
8283 }
8284
8285 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
8286 e_err(drv, "Location out of range\n");
8287 return -EINVAL;
8288 }
8289
8290 /* cls u32 is a graph starting at root node 0x800. The driver tracks
8291 * links and also the fields used to advance the parser across each
8292 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
8293 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
8294 * To add support for new nodes update ixgbe_model.h parse structures
8295 * this function _should_ be generic try not to hardcode values here.
8296 */
8297 if (TC_U32_USERHTID(handle) == 0x800) {
8298 field_ptr = adapter->jump_tables[0];
8299 } else {
8300 if (TC_U32_USERHTID(handle) >= ARRAY_SIZE(adapter->jump_tables))
8301 return -EINVAL;
8302
8303 field_ptr = adapter->jump_tables[TC_U32_USERHTID(handle)];
8304 }
8305
8306 if (!field_ptr)
8307 return -EINVAL;
8308
8309 input = kzalloc(sizeof(*input), GFP_KERNEL);
8310 if (!input)
8311 return -ENOMEM;
8312
8313 for (i = 0; i < cls->knode.sel->nkeys; i++) {
8314 int off = cls->knode.sel->keys[i].off;
8315 __be32 val = cls->knode.sel->keys[i].val;
8316 __be32 m = cls->knode.sel->keys[i].mask;
8317 bool found_entry = false;
8318 int j;
8319
8320 for (j = 0; field_ptr[j].val; j++) {
8321 if (field_ptr[j].off == off &&
8322 field_ptr[j].mask == m) {
8323 field_ptr[j].val(input, &mask, val, m);
8324 input->filter.formatted.flow_type |=
8325 field_ptr[j].type;
8326 found_entry = true;
8327 break;
8328 }
8329 }
8330
8331 if (!found_entry)
8332 goto err_out;
8333 }
8334
8335 mask.formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
8336 IXGBE_ATR_L4TYPE_MASK;
8337
8338 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
8339 mask.formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
8340
8341#ifdef CONFIG_NET_CLS_ACT
8342 if (list_empty(&cls->knode.exts->actions))
8343 goto err_out;
8344
8345 list_for_each_entry(a, &cls->knode.exts->actions, list) {
8346 if (!is_tcf_gact_shot(a))
8347 goto err_out;
8348 }
8349#endif
8350
8351 input->action = IXGBE_FDIR_DROP_QUEUE;
8352 queue = IXGBE_FDIR_DROP_QUEUE;
8353 input->sw_idx = loc;
8354
8355 spin_lock(&adapter->fdir_perfect_lock);
8356
8357 if (hlist_empty(&adapter->fdir_filter_list)) {
8358 memcpy(&adapter->fdir_mask, &mask, sizeof(mask));
8359 err = ixgbe_fdir_set_input_mask_82599(hw, &mask);
8360 if (err)
8361 goto err_out_w_lock;
8362 } else if (memcmp(&adapter->fdir_mask, &mask, sizeof(mask))) {
8363 err = -EINVAL;
8364 goto err_out_w_lock;
8365 }
8366
8367 ixgbe_atr_compute_perfect_hash_82599(&input->filter, &mask);
8368 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
8369 input->sw_idx, queue);
8370 if (!err)
8371 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
8372 spin_unlock(&adapter->fdir_perfect_lock);
8373
8374 return err;
8375err_out_w_lock:
8376 spin_unlock(&adapter->fdir_perfect_lock);
8377err_out:
8378 kfree(input);
8379 return -EINVAL;
8380}
8381
16e5cc64
JF		 8382int __ixgbe_setup_tc(struct net_device *dev, u32 handle, __be16 proto,
8383 struct tc_to_netdev *tc)
e4c6734e 8384{
b82b17d9
JF		 8385 struct ixgbe_adapter *adapter = netdev_priv(dev);
8386
8387 if (TC_H_MAJ(handle) == TC_H_MAJ(TC_H_INGRESS) &&
8388 tc->type == TC_SETUP_CLSU32) {
b82b17d9
JF		 8389 switch (tc->cls_u32->command) {
8390 case TC_CLSU32_NEW_KNODE:
8391 case TC_CLSU32_REPLACE_KNODE:
8392 return ixgbe_configure_clsu32(adapter,
8393 proto, tc->cls_u32);
8394 case TC_CLSU32_DELETE_KNODE:
8395 return ixgbe_delete_clsu32(adapter, tc->cls_u32);
db956ae8
JF		 8396 case TC_CLSU32_NEW_HNODE:
8397 case TC_CLSU32_REPLACE_HNODE:
8398 return ixgbe_configure_clsu32_add_hnode(adapter, proto,
8399 tc->cls_u32);
8400 case TC_CLSU32_DELETE_HNODE:
8401 return ixgbe_configure_clsu32_del_hnode(adapter,
8402 tc->cls_u32);
b82b17d9
JF		 8403 default:
8404 return -EINVAL;
8405 }
8406 }
8407
5eb4dce3 8408 if (tc->type != TC_SETUP_MQPRIO)
e4c6734e
JF		 8409 return -EINVAL;
8410
16e5cc64 8411 return ixgbe_setup_tc(dev, tc->tc);
e4c6734e
JF		 8412}
8413
da36b647
GR		 8414#ifdef CONFIG_PCI_IOV
8415void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
8416{
8417 struct net_device *netdev = adapter->netdev;
8418
8419 rtnl_lock();
da36b647 8420 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 8421 rtnl_unlock();
8422}
8423
8424#endif
082757af
DS		 8425void ixgbe_do_reset(struct net_device *netdev)
8426{
8427 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8428
8429 if (netif_running(netdev))
8430 ixgbe_reinit_locked(adapter);
8431 else
8432 ixgbe_reset(adapter);
8433}
8434
c8f44aff 8435static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 8436 netdev_features_t features)
082757af
DS		 8437{
8438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8439
082757af 8440 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 8441 if (!(features & NETIF_F_RXCSUM))
8442 features &= ~NETIF_F_LRO;
082757af 8443
567d2de2
AD		 8444 /* Turn off LRO if not RSC capable */
8445 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
8446 features &= ~NETIF_F_LRO;
8e2813f5 8447
567d2de2 8448 return features;
082757af
DS		 8449}
8450
c8f44aff 8451static int ixgbe_set_features(struct net_device *netdev,
567d2de2 8452 netdev_features_t features)
082757af
DS		 8453{
8454 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 8455 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 8456 bool need_reset = false;
8457
082757af 8458 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 8459 if (!(features & NETIF_F_LRO)) {
8460 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 8461 need_reset = true;
567d2de2
AD		 8462 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
8463 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
8464 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
8465 if (adapter->rx_itr_setting == 1 ||
8466 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
8467 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8468 need_reset = true;
8469 } else if ((changed ^ features) & NETIF_F_LRO) {
8470 e_info(probe, "rx-usecs set too low, "
8471 "disabling RSC\n");
082757af
DS		 8472 }
8473 }
8474
8475 /*
b82b17d9
JF		 8476 * Check if Flow Director n-tuple support or hw_tc support was
8477 * enabled or disabled. If the state changed, we need to reset.
082757af 8478 */
b82b17d9 8479 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
567d2de2 8480 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 8481 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
8482 need_reset = true;
8483
567d2de2
AD		 8484 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
8485 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
b82b17d9 8486 } else {
39cb681b
AD		 8487 /* turn off perfect filters, enable ATR and reset */
8488 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
8489 need_reset = true;
8490
8491 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
8492
8493 /* We cannot enable ATR if SR-IOV is enabled */
b82b17d9
JF		 8494 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
8495 /* We cannot enable ATR if we have 2 or more tcs */
8496 (netdev_get_num_tc(netdev) > 1) ||
8497 /* We cannot enable ATR if RSS is disabled */
8498 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
8499 /* A sample rate of 0 indicates ATR disabled */
8500 (!adapter->atr_sample_rate))
8501 ; /* do nothing not supported */
8502 else /* otherwise supported and set the flag */
8503 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
082757af
DS		 8504 }
8505
f646968f 8506 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8507 ixgbe_vlan_strip_enable(adapter);
8508 else
8509 ixgbe_vlan_strip_disable(adapter);
8510
3f2d1c0f
BG		 8511 if (changed & NETIF_F_RXALL)
8512 need_reset = true;
8513
567d2de2 8514 netdev->features = features;
67359c3c
MR		 8515
8516#ifdef CONFIG_IXGBE_VXLAN
8517 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8518 if (features & NETIF_F_RXCSUM)
8519 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8520 else
8521 ixgbe_clear_vxlan_port(adapter);
8522 }
8523#endif /* CONFIG_IXGBE_VXLAN */
8524
082757af
DS		 8525 if (need_reset)
8526 ixgbe_do_reset(netdev);
8527
8528 return 0;
082757af
DS		 8529}
8530
67359c3c 8531#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8532/**
8533 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8534 * @dev: The port's netdev
8535 * @sa_family: Socket Family that VXLAN is notifiying us about
8536 * @port: New UDP port number that VXLAN started listening to
8537 **/
8538static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8539 __be16 port)
8540{
8541 struct ixgbe_adapter *adapter = netdev_priv(dev);
8542 struct ixgbe_hw *hw = &adapter->hw;
3f207800 8543
67359c3c
MR		 8544 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8545 return;
8546
3f207800
DS		 8547 if (sa_family == AF_INET6)
8548 return;
8549
9f12df90 8550 if (adapter->vxlan_port == port)
3f207800 8551 return;
3f207800
DS		 8552
8553 if (adapter->vxlan_port) {
8554 netdev_info(dev,
67359c3c 8555 "Hit Max num of VXLAN ports, not adding port %d\n",
9f12df90 8556 ntohs(port));
3f207800
DS		 8557 return;
8558 }
8559
9f12df90
AD		 8560 adapter->vxlan_port = port;
8561 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, ntohs(port));
3f207800
DS		 8562}
8563
8564/**
8565 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8566 * @dev: The port's netdev
8567 * @sa_family: Socket Family that VXLAN is notifying us about
8568 * @port: UDP port number that VXLAN stopped listening to
8569 **/
8570static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8571 __be16 port)
8572{
8573 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800 8574
67359c3c
MR		 8575 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8576 return;
8577
3f207800
DS		 8578 if (sa_family == AF_INET6)
8579 return;
8580
9f12df90 8581 if (adapter->vxlan_port != port) {
3f207800 8582 netdev_info(dev, "Port %d was not found, not deleting\n",
9f12df90 8583 ntohs(port));
3f207800
DS		 8584 return;
8585 }
8586
67359c3c
MR		 8587 ixgbe_clear_vxlan_port(adapter);
8588 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8589}
67359c3c 8590#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8591
edc7d573 8592static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8593 struct net_device *dev,
f6f6424b 8594 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8595 u16 flags)
8596{
bcfd3432 8597 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8598 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
2f9be166
AD		 8599 struct ixgbe_adapter *adapter = netdev_priv(dev);
8600 u16 pool = VMDQ_P(0);
8601
8602 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
bcfd3432 8603 return -ENOMEM;
0f4b0add
JF		 8604 }
8605
f6f6424b 8606 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8607}
8608
219efe97
DS		 8609/**
8610 * ixgbe_configure_bridge_mode - set various bridge modes
8611 * @adapter - the private structure
8612 * @mode - requested bridge mode
8613 *
8614 * Configure some settings require for various bridge modes.
8615 **/
8616static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8617 __u16 mode)
8618{
6d4c96ad
DS		 8619 struct ixgbe_hw *hw = &adapter->hw;
8620 unsigned int p, num_pools;
8621 u32 vmdctl;
8622
219efe97
DS		 8623 switch (mode) {
8624 case BRIDGE_MODE_VEPA:
6d4c96ad 8625 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8627
8628 /* must enable Rx switching replication to allow multicast
8629 * packet reception on all VFs, and to enable source address
8630 * pruning.
8631 */
8632 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8633 vmdctl |= IXGBE_VT_CTL_REPLEN;
8634 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8635
8636 /* enable Rx source address pruning. Note, this requires
8637 * replication to be enabled or else it does nothing.
8638 */
8639 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8640 for (p = 0; p < num_pools; p++) {
8641 if (hw->mac.ops.set_source_address_pruning)
8642 hw->mac.ops.set_source_address_pruning(hw,
8643 true,
8644 p);
8645 }
219efe97
DS		 8646 break;
8647 case BRIDGE_MODE_VEB:
6d4c96ad 8648 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8649 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8650 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8651
8652 /* disable Rx switching replication unless we have SR-IOV
8653 * virtual functions
8654 */
8655 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8656 if (!adapter->num_vfs)
8657 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8658 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8659
8660 /* disable Rx source address pruning, since we don't expect to
8661 * be receiving external loopback of our transmitted frames.
8662 */
8663 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8664 for (p = 0; p < num_pools; p++) {
8665 if (hw->mac.ops.set_source_address_pruning)
8666 hw->mac.ops.set_source_address_pruning(hw,
8667 false,
8668 p);
8669 }
219efe97
DS		 8670 break;
8671 default:
8672 return -EINVAL;
8673 }
8674
8675 adapter->bridge_mode = mode;
8676
8677 e_info(drv, "enabling bridge mode: %s\n",
8678 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8679
8680 return 0;
8681}
8682
815cccbf 8683static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8684 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8685{
8686 struct ixgbe_adapter *adapter = netdev_priv(dev);
8687 struct nlattr *attr, *br_spec;
8688 int rem;
8689
8690 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8691 return -EOPNOTSUPP;
8692
8693 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8694 if (!br_spec)
8695 return -EINVAL;
815cccbf
JF		 8696
8697 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8698 int status;
815cccbf 8699 __u16 mode;
815cccbf
JF		 8700
8701 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8702 continue;
8703
b7c1a314
TG		 8704 if (nla_len(attr) < sizeof(mode))
8705 return -EINVAL;
8706
815cccbf 8707 mode = nla_get_u16(attr);
219efe97
DS		 8708 status = ixgbe_configure_bridge_mode(adapter, mode);
8709 if (status)
8710 return status;
aa2bacb6
DS		 8711
8712 break;
815cccbf
JF		 8713 }
8714
8715 return 0;
8716}
8717
8718static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8719 struct net_device *dev,
46c264da 8720 u32 filter_mask, int nlflags)
815cccbf
JF		 8721{
8722 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8723
8724 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8725 return 0;
8726
aa2bacb6 8727 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8728 adapter->bridge_mode, 0, 0, nlflags,
8729 filter_mask, NULL);
815cccbf
JF		 8730}
8731
2a47fa45
JF		 8732static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8733{
8734 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8735 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8736 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8737 unsigned int limit;
2a47fa45
JF		 8738 int pool, err;
8739
aac2f1bf
JK		 8740 /* Hardware has a limited number of available pools. Each VF, and the
8741 * PF require a pool. Check to ensure we don't attempt to use more
8742 * then the available number of pools.
8743 */
8744 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8745 return ERR_PTR(-EINVAL);
8746
219354d4
JF		 8747#ifdef CONFIG_RPS
8748 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8749 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8750 vdev->name);
8751 return ERR_PTR(-EINVAL);
8752 }
8753#endif
2a47fa45 8754 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8755 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8756 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8757 netdev_info(pdev,
8758 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8759 pdev->name);
8760 return ERR_PTR(-EINVAL);
8761 }
8762
8763 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8764 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8765 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8766 return ERR_PTR(-EBUSY);
8767
bc52f951 8768 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8769 if (!fwd_adapter)
8770 return ERR_PTR(-ENOMEM);
8771
8772 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8773 adapter->num_rx_pools++;
8774 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8775 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8776
8777 /* Enable VMDq flag so device will be set in VM mode */
8778 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8779 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8780 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8781
8782 /* Force reinit of ring allocation with VMDQ enabled */
8783 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8784 if (err)
8785 goto fwd_add_err;
8786 fwd_adapter->pool = pool;
8787 fwd_adapter->real_adapter = adapter;
8788 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8789 if (err)
8790 goto fwd_add_err;
8791 netif_tx_start_all_queues(vdev);
8792 return fwd_adapter;
8793fwd_add_err:
8794 /* unwind counter and free adapter struct */
8795 netdev_info(pdev,
8796 "%s: dfwd hardware acceleration failed\n", vdev->name);
8797 clear_bit(pool, &adapter->fwd_bitmask);
8798 adapter->num_rx_pools--;
8799 kfree(fwd_adapter);
8800 return ERR_PTR(err);
8801}
8802
8803static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8804{
8805 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8806 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8807 unsigned int limit;
2a47fa45
JF		 8808
8809 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8810 adapter->num_rx_pools--;
8811
51f3773b
JF		 8812 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8813 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8814 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8815 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8816 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8817 fwd_adapter->pool, adapter->num_rx_pools,
8818 fwd_adapter->rx_base_queue,
8819 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8820 adapter->fwd_bitmask);
8821 kfree(fwd_adapter);
8822}
8823
f467bc06
MR		 8824#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8825static netdev_features_t
8826ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8827 netdev_features_t features)
8828{
8829 if (!skb->encapsulation)
8830 return features;
8831
8832 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8833 IXGBE_MAX_TUNNEL_HDR_LEN))
a188222b 8834 return features & ~NETIF_F_CSUM_MASK;
f467bc06
MR		 8835
8836 return features;
8837}
8838
0edc3527 8839static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8840 .ndo_open = ixgbe_open,
0edc3527 8841 .ndo_stop = ixgbe_close,
00829823 8842 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8843 .ndo_select_queue = ixgbe_select_queue,
581330ba 8844 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8845 .ndo_validate_addr = eth_validate_addr,
8846 .ndo_set_mac_address = ixgbe_set_mac,
8847 .ndo_change_mtu = ixgbe_change_mtu,
8848 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8849 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8850 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8851 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8852 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8853 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8854 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8855 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8856 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
54011e4d 8857 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
7f01648a 8858 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8859 .ndo_get_stats64 = ixgbe_get_stats64,
e4c6734e 8860 .ndo_setup_tc = __ixgbe_setup_tc,
0edc3527
SH		 8861#ifdef CONFIG_NET_POLL_CONTROLLER
8862 .ndo_poll_controller = ixgbe_netpoll,
8863#endif
e0d1095a 8864#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8865 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8866#endif
332d4a7d
YZ		 8867#ifdef IXGBE_FCOE
8868 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8869 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8870 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8871 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8872 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8873 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8874 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8875#endif /* IXGBE_FCOE */
082757af
DS		 8876 .ndo_set_features = ixgbe_set_features,
8877 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8878 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8879 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8880 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8881 .ndo_dfwd_add_station = ixgbe_fwd_add,
8882 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8883#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8884 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8885 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8886#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8887 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8888};
8889
e027d1ae
JK		 8890/**
8891 * ixgbe_enumerate_functions - Get the number of ports this device has
8892 * @adapter: adapter structure
8893 *
8894 * This function enumerates the phsyical functions co-located on a single slot,
8895 * in order to determine how many ports a device has. This is most useful in
8896 * determining the required GT/s of PCIe bandwidth necessary for optimal
8897 * performance.
8898 **/
8899static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8900{
caafb95d 8901 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8902 int physfns = 0;
8903
f1f96579
JK		 8904 /* Some cards can not use the generic count PCIe functions method,
8905 * because they are behind a parent switch, so we hardcode these with
8906 * the correct number of functions.
e027d1ae 8907 */
8818970d 8908 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8909 physfns = 4;
8818970d
JK		 8910
8911 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8912 /* don't count virtual functions */
caafb95d
JK		 8913 if (entry->is_virtfn)
8914 continue;
8915
8916 /* When the devices on the bus don't all match our device ID,
8917 * we can't reliably determine the correct number of
8918 * functions. This can occur if a function has been direct
8919 * attached to a virtual machine using VT-d, for example. In
8920 * this case, simply return -1 to indicate this.
8921 */
8922 if ((entry->vendor != pdev->vendor) ||
8923 (entry->device != pdev->device))
8924 return -1;
8925
8926 physfns++;
e027d1ae
JK		 8927 }
8928
8929 return physfns;
8930}
8931
8e2813f5
JK		 8932/**
8933 * ixgbe_wol_supported - Check whether device supports WoL
8934 * @hw: hw specific details
8935 * @device_id: the device ID
8936 * @subdev_id: the subsystem device ID
8937 *
8938 * This function is used by probe and ethtool to determine
8939 * which devices have WoL support
8940 *
8941 **/
8942int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8943 u16 subdevice_id)
8944{
8945 struct ixgbe_hw *hw = &adapter->hw;
8946 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8947 int is_wol_supported = 0;
8948
8949 switch (device_id) {
8950 case IXGBE_DEV_ID_82599_SFP:
8951 /* Only these subdevices could supports WOL */
8952 switch (subdevice_id) {
87557440 8953 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8954 case IXGBE_SUBDEV_ID_82599_560FLR:
8955 /* only support first port */
8956 if (hw->bus.func != 0)
8957 break;
5700ff26 8958 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8959 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8960 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8961 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8962 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8963 is_wol_supported = 1;
8964 break;
8965 }
8966 break;
5daebbb0
DS		 8967 case IXGBE_DEV_ID_82599EN_SFP:
8968 /* Only this subdevice supports WOL */
8969 switch (subdevice_id) {
8970 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8971 is_wol_supported = 1;
8972 break;
8973 }
8974 break;
8e2813f5
JK		 8975 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8976 /* All except this subdevice support WOL */
8977 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8978 is_wol_supported = 1;
8979 break;
8980 case IXGBE_DEV_ID_82599_KX4:
8981 is_wol_supported = 1;
8982 break;
8983 case IXGBE_DEV_ID_X540T:
df376f0d 8984 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8985 case IXGBE_DEV_ID_X550T:
8986 case IXGBE_DEV_ID_X550EM_X_KX4:
8987 case IXGBE_DEV_ID_X550EM_X_KR:
8988 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8989 /* check eeprom to see if enabled wol */
8990 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8991 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8992 (hw->bus.func == 0))) {
8993 is_wol_supported = 1;
8994 }
8995 break;
8996 }
8997
8998 return is_wol_supported;
8999}
9000
c762dff2
MP		 9001/**
9002 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
9003 * @adapter: Pointer to adapter struct
9004 */
9005static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
9006{
9007#ifdef CONFIG_OF
9008 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
9009 struct ixgbe_hw *hw = &adapter->hw;
9010 const unsigned char *addr;
9011
9012 addr = of_get_mac_address(dp);
9013 if (addr) {
9014 ether_addr_copy(hw->mac.perm_addr, addr);
9015 return;
9016 }
9017#endif /* CONFIG_OF */
9018
9019#ifdef CONFIG_SPARC
9020 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
9021#endif /* CONFIG_SPARC */
9022}
9023
9a799d71
AK		 9024/**
9025 * ixgbe_probe - Device Initialization Routine
9026 * @pdev: PCI device information struct
9027 * @ent: entry in ixgbe_pci_tbl
9028 *
9029 * Returns 0 on success, negative on failure
9030 *
9031 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
9032 * The OS initialization, configuring of the adapter private structure,
9033 * and a hardware reset occur.
9034 **/
1dd06ae8 9035static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 9036{
9037 struct net_device *netdev;
9038 struct ixgbe_adapter *adapter = NULL;
9039 struct ixgbe_hw *hw;
9040 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 9041 int i, err, pci_using_dac, expected_gts;
d3cb9869 9042 unsigned int indices = MAX_TX_QUEUES;
289700db 9043 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 9044 bool disable_dev = false;
eacd73f7
YZ		 9045#ifdef IXGBE_FCOE
9046 u16 device_caps;
9047#endif
289700db 9048 u32 eec;
9a799d71 9049
bded64a7
AG		 9050 /* Catch broken hardware that put the wrong VF device ID in
9051 * the PCIe SR-IOV capability.
9052 */
9053 if (pdev->is_virtfn) {
9054 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
9055 pci_name(pdev), pdev->vendor, pdev->device);
9056 return -EINVAL;
9057 }
9058
9ce77666 9059 err = pci_enable_device_mem(pdev);
9a799d71
AK		 9060 if (err)
9061 return err;
9062
f5f2eda8 9063 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 9064 pci_using_dac = 1;
9065 } else {
f5f2eda8 9066 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 9067 if (err) {
f5f2eda8
RK		 9068 dev_err(&pdev->dev,
9069 "No usable DMA configuration, aborting\n");
9070 goto err_dma;
9a799d71
AK		 9071 }
9072 pci_using_dac = 0;
9073 }
9074
9ce77666 9075 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9076 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 9077 if (err) {
b8bc0421
DC		 9078 dev_err(&pdev->dev,
9079 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 9080 goto err_pci_reg;
9081 }
9082
19d5afd4 9083 pci_enable_pcie_error_reporting(pdev);
6fabd715 9084
9a799d71 9085 pci_set_master(pdev);
fb3b27bc 9086 pci_save_state(pdev);
9a799d71 9087
d3cb9869 9088 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 9089#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 9090 /* 8 TC w/ 4 queues per TC */
9091 indices = 4 * MAX_TRAFFIC_CLASS;
9092#else
9093 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 9094#endif
d3cb9869 9095 }
e901acd6 9096
c85a2618 9097 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 9098 if (!netdev) {
9099 err = -ENOMEM;
9100 goto err_alloc_etherdev;
9101 }
9102
9a799d71
AK		 9103 SET_NETDEV_DEV(netdev, &pdev->dev);
9104
9a799d71
AK		 9105 adapter = netdev_priv(netdev);
9106
9107 adapter->netdev = netdev;
9108 adapter->pdev = pdev;
9109 hw = &adapter->hw;
9110 hw->back = adapter;
b3f4d599 9111 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 9112
05857980 9113 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 9114 pci_resource_len(pdev, 0));
2a1a091c 9115 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 9116 if (!hw->hw_addr) {
9117 err = -EIO;
9118 goto err_ioremap;
9119 }
9120
0edc3527 9121 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 9122 ixgbe_set_ethtool_ops(netdev);
9a799d71 9123 netdev->watchdog_timeo = 5 * HZ;
339de30f 9124 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 9125
9a799d71
AK		 9126 /* Setup hw api */
9127 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 9128 hw->mac.type = ii->mac;
9a900eca 9129 hw->mvals = ii->mvals;
9a799d71 9130
c44ade9e
JB		 9131 /* EEPROM */
9132 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 9133 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 9134 if (ixgbe_removed(hw->hw_addr)) {
9135 err = -EIO;
9136 goto err_ioremap;
9137 }
c44ade9e
JB		 9138 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
9139 if (!(eec & (1 << 8)))
9140 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
9141
9142 /* PHY */
9143 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 9144 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 9145 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
9146 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
9147 hw->phy.mdio.mmds = 0;
9148 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
9149 hw->phy.mdio.dev = netdev;
9150 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
9151 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 9152
8ca783ab 9153 ii->get_invariants(hw);
9a799d71
AK		 9154
9155 /* setup the private structure */
9156 err = ixgbe_sw_init(adapter);
9157 if (err)
9158 goto err_sw_init;
9159
e86bff0e 9160 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 9161 switch (adapter->hw.mac.type) {
9162 case ixgbe_mac_82599EB:
9163 case ixgbe_mac_X540:
9a75a1ac
DS		 9164 case ixgbe_mac_X550:
9165 case ixgbe_mac_X550EM_x:
e86bff0e 9166 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 9167 break;
9168 default:
9169 break;
9170 }
e86bff0e 9171
bf069c97
DS		 9172 /*
9173 * If there is a fan on this device and it has failed log the
9174 * failure.
9175 */
9176 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
9177 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
9178 if (esdp & IXGBE_ESDP_SDP1)
396e799c 9179 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 9180 }
9181
8ef78adc
PWJ		 9182 if (allow_unsupported_sfp)
9183 hw->allow_unsupported_sfp = allow_unsupported_sfp;
9184
c44ade9e 9185 /* reset_hw fills in the perm_addr as well */
119fc60a 9186 hw->phy.reset_if_overtemp = true;
c44ade9e 9187 err = hw->mac.ops.reset_hw(hw);
119fc60a 9188 hw->phy.reset_if_overtemp = false;
29a8dca1 9189 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
8ca783ab
DS		 9190 err = 0;
9191 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 9192 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
9193 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 9194 goto err_sw_init;
9195 } else if (err) {
849c4542 9196 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 9197 goto err_sw_init;
9198 }
9199
99d74487 9200#ifdef CONFIG_PCI_IOV
60a1a680
GR		 9201 /* SR-IOV not supported on the 82598 */
9202 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9203 goto skip_sriov;
9204 /* Mailbox */
9205 ixgbe_init_mbx_params_pf(hw);
9206 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 9207 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 9208 ixgbe_enable_sriov(adapter);
60a1a680 9209skip_sriov:
1cdd1ec8 9210
99d74487 9211#endif
396e799c 9212 netdev->features = NETIF_F_SG |
e8e9f696 9213 NETIF_F_IP_CSUM |
082757af 9214 NETIF_F_IPV6_CSUM |
f646968f
PM		 9215 NETIF_F_HW_VLAN_CTAG_TX |
9216 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 9217 NETIF_F_TSO |
9218 NETIF_F_TSO6 |
082757af 9219 NETIF_F_RXHASH |
8bf1264d 9220 NETIF_F_RXCSUM;
9a799d71 9221
8bf1264d 9222 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 9223
58be7666
DS		 9224 switch (adapter->hw.mac.type) {
9225 case ixgbe_mac_82599EB:
9226 case ixgbe_mac_X540:
9a75a1ac
DS		 9227 case ixgbe_mac_X550:
9228 case ixgbe_mac_X550EM_x:
53692b1d
TH		 9229 netdev->features |= NETIF_F_SCTP_CRC;
9230 netdev->hw_features |= NETIF_F_SCTP_CRC |
b82b17d9
JF		 9231 NETIF_F_NTUPLE |
9232 NETIF_F_HW_TC;
58be7666
DS		 9233 break;
9234 default:
9235 break;
9236 }
45a5ead0 9237
3f2d1c0f 9238 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 9239 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 9240
ad31c402
JK		 9241 netdev->vlan_features |= NETIF_F_TSO;
9242 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 9243 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 9244 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 9245 netdev->vlan_features |= NETIF_F_SG;
9246
fb8ad4a5 9247 netdev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
f467bc06 9248
01789349 9249 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 9250 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 9251
7a6b6f51 9252#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 9253 netdev->dcbnl_ops = &dcbnl_ops;
9254#endif
9255
eacd73f7 9256#ifdef IXGBE_FCOE
0d551589 9257 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 9258 unsigned int fcoe_l;
9259
eacd73f7
YZ		 9260 if (hw->mac.ops.get_device_caps) {
9261 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 9262 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
9263 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 9264 }
7c8ae65a 9265
d3cb9869
AD		 9266
9267 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
9268 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 9269
a58915c7
AD		 9270 netdev->features |= NETIF_F_FSO |
9271 NETIF_F_FCOE_CRC;
9272
7c8ae65a
AD		 9273 netdev->vlan_features |= NETIF_F_FSO |
9274 NETIF_F_FCOE_CRC |
9275 NETIF_F_FCOE_MTU;
5e09d7f6 9276 }
eacd73f7 9277#endif /* IXGBE_FCOE */
7b872a55 9278 if (pci_using_dac) {
9a799d71 9279 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 9280 netdev->vlan_features |= NETIF_F_HIGHDMA;
9281 }
9a799d71 9282
082757af
DS		 9283 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
9284 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 9285 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 9286 netdev->features |= NETIF_F_LRO;
9287
9a799d71 9288 /* make sure the EEPROM is good */
c44ade9e 9289 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 9290 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 9291 err = -EIO;
35937c05 9292 goto err_sw_init;
9a799d71
AK		 9293 }
9294
c762dff2
MP		 9295 ixgbe_get_platform_mac_addr(adapter);
9296
9a799d71 9297 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 9298
aaeb6cdf 9299 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 9300 e_dev_err("invalid MAC address\n");
9a799d71 9301 err = -EIO;
35937c05 9302 goto err_sw_init;
9a799d71
AK		 9303 }
9304
56768045
TD		 9305 /* Set hw->mac.addr to permanent MAC address */
9306 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
c9f53e63 9307 ixgbe_mac_set_default_filter(adapter);
5d7daa35 9308
7086400d 9309 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 9310 (unsigned long) adapter);
9a799d71 9311
58cf663f
MR		 9312 if (ixgbe_removed(hw->hw_addr)) {
9313 err = -EIO;
9314 goto err_sw_init;
9315 }
7086400d 9316 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 9317 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 9318 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 9319
021230d4
AV		 9320 err = ixgbe_init_interrupt_scheme(adapter);
9321 if (err)
9322 goto err_sw_init;
9a799d71 9323
8e2813f5 9324 /* WOL not supported for all devices */
c23f5b6b 9325 adapter->wol = 0;
8e2813f5 9326 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 9327 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 9328 pdev->subsystem_device);
6b92b0ba 9329 if (hw->wol_enabled)
9417c464 9330 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 9331
e8e26350
PW		 9332 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
9333
15e5209f
ET		 9334 /* save off EEPROM version number */
9335 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
9336 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
9337
04f165ef 9338 /* pick up the PCI bus settings for reporting later */
e027d1ae 9339 if (ixgbe_pcie_from_parent(hw))
b8e82001 9340 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 9341 else
9342 hw->mac.ops.get_bus_info(hw);
04f165ef 9343
e027d1ae
JK		 9344 /* calculate the expected PCIe bandwidth required for optimal
9345 * performance. Note that some older parts will never have enough
9346 * bandwidth due to being older generation PCIe parts. We clamp these
9347 * parts to ensure no warning is displayed if it can't be fixed.
9348 */
9349 switch (hw->mac.type) {
9350 case ixgbe_mac_82598EB:
9351 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
9352 break;
9353 default:
9354 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
9355 break;
0c254d86 9356 }
caafb95d
JK		 9357
9358 /* don't check link if we failed to enumerate functions */
9359 if (expected_gts > 0)
9360 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 9361
339de30f 9362 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 9363 if (err)
339de30f 9364 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 9365 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
9366 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
9367 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 9368 part_str);
6a2aae5a
JK		 9369 else
9370 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
9371 hw->mac.type, hw->phy.type, part_str);
9372
9373 e_dev_info("%pM\n", netdev->dev_addr);
9374
9a799d71 9375 /* reset the hardware with the new settings */
794caeb2 9376 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 9377 if (err == IXGBE_ERR_EEPROM_VERSION) {
9378 /* We are running on a pre-production device, log a warning */
849c4542
ET		 9379 e_dev_warn("This device is a pre-production adapter/LOM. "
9380 "Please be aware there may be issues associated "
9381 "with your hardware. If you are experiencing "
9382 "problems please contact your Intel or hardware "
9383 "representative who provided you with this "
9384 "hardware.\n");
794caeb2 9385 }
9a799d71
AK		 9386 strcpy(netdev->name, "eth%d");
9387 err = register_netdev(netdev);
9388 if (err)
9389 goto err_register;
9390
0fb6a55c
ET		 9391 pci_set_drvdata(pdev, adapter);
9392
ec74a471
ET		 9393 /* power down the optics for 82599 SFP+ fiber */
9394 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 9395 hw->mac.ops.disable_tx_laser(hw);
9396
54386467
JB		 9397 /* carrier off reporting is important to ethtool even BEFORE open */
9398 netif_carrier_off(netdev);
9399
5dd2d332 9400#ifdef CONFIG_IXGBE_DCA
652f093f 9401 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 9402 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 9403 ixgbe_setup_dca(adapter);
9404 }
9405#endif
1cdd1ec8 9406 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 9407 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 9408 for (i = 0; i < adapter->num_vfs; i++)
9409 ixgbe_vf_configuration(pdev, (i | 0x10000000));
9410 }
9411
2466dd9c
JK		 9412 /* firmware requires driver version to be 0xFFFFFFFF
9413 * since os does not support feature
9414 */
9612de92 9415 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 9416 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
9417 0xFF);
9612de92 9418
0365e6e4
PW		 9419 /* add san mac addr to netdev */
9420 ixgbe_add_sanmac_netdev(netdev);
9a799d71 9421
ea81875a 9422 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 9423
1210982b 9424#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 9425 if (ixgbe_sysfs_init(adapter))
9426 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 9427#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9428
00949167 9429 ixgbe_dbg_adapter_init(adapter);
00949167 9430
d1a35ee2
ET		 9431 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
9432 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 9433 hw->mac.ops.setup_link(hw,
9434 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
9435 true);
9436
9a799d71
AK		 9437 return 0;
9438
9439err_register:
5eba3699 9440 ixgbe_release_hw_control(adapter);
7a921c93 9441 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 9442err_sw_init:
99d74487 9443 ixgbe_disable_sriov(adapter);
7086400d 9444 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 9445 iounmap(adapter->io_addr);
5d7daa35 9446 kfree(adapter->mac_table);
9a799d71 9447err_ioremap:
b5b2ffc0 9448 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9449 free_netdev(netdev);
9450err_alloc_etherdev:
e8e9f696
JP		 9451 pci_release_selected_regions(pdev,
9452 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 9453err_pci_reg:
9454err_dma:
b5b2ffc0 9455 if (!adapter || disable_dev)
41c62843 9456 pci_disable_device(pdev);
9a799d71
AK		 9457 return err;
9458}
9459
9460/**
9461 * ixgbe_remove - Device Removal Routine
9462 * @pdev: PCI device information struct
9463 *
9464 * ixgbe_remove is called by the PCI subsystem to alert the driver
9465 * that it should release a PCI device. The could be caused by a
9466 * Hot-Plug event, or because the driver is going to be removed from
9467 * memory.
9468 **/
9f9a12f8 9469static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 9470{
c60fbb00 9471 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 9472 struct net_device *netdev;
b5b2ffc0 9473 bool disable_dev;
9a799d71 9474
0fb6a55c
ET		 9475 /* if !adapter then we already cleaned up in probe */
9476 if (!adapter)
9477 return;
9478
9479 netdev = adapter->netdev;
00949167 9480 ixgbe_dbg_adapter_exit(adapter);
00949167 9481
09f40aed 9482 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 9483 cancel_work_sync(&adapter->service_task);
9a799d71 9484
3a6a4eda 9485
5dd2d332 9486#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9487 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
9488 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
9489 dca_remove_requester(&pdev->dev);
9de7605e
MR		 9490 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
9491 IXGBE_DCA_CTRL_DCA_DISABLE);
bd0362dd
JC		 9492 }
9493
9494#endif
1210982b 9495#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9496 ixgbe_sysfs_exit(adapter);
1210982b 9497#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9498
0365e6e4
PW		 9499 /* remove the added san mac */
9500 ixgbe_del_sanmac_netdev(netdev);
9501
da36b647 9502#ifdef CONFIG_PCI_IOV
7837e286 9503 ixgbe_disable_sriov(adapter);
da36b647 9504#endif
6b010e9b
AW		 9505 if (netdev->reg_state == NETREG_REGISTERED)
9506 unregister_netdev(netdev);
9507
7a921c93 9508 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9509
021230d4 9510 ixgbe_release_hw_control(adapter);
9a799d71 9511
2b1588c3
AD		 9512#ifdef CONFIG_DCB
9513 kfree(adapter->ixgbe_ieee_pfc);
9514 kfree(adapter->ixgbe_ieee_ets);
9515
9516#endif
2a1a091c 9517 iounmap(adapter->io_addr);
9ce77666 9518 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9519 IORESOURCE_MEM));
9a799d71 9520
849c4542 9521 e_dev_info("complete\n");
021230d4 9522
5d7daa35 9523 kfree(adapter->mac_table);
b5b2ffc0 9524 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9525 free_netdev(netdev);
9526
19d5afd4 9527 pci_disable_pcie_error_reporting(pdev);
6fabd715 9528
b5b2ffc0 9529 if (disable_dev)
41c62843 9530 pci_disable_device(pdev);
9a799d71
AK		 9531}
9532
9533/**
9534 * ixgbe_io_error_detected - called when PCI error is detected
9535 * @pdev: Pointer to PCI device
9536 * @state: The current pci connection state
9537 *
9538 * This function is called after a PCI bus error affecting
9539 * this device has been detected.
9540 */
9541static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9542 pci_channel_state_t state)
9a799d71 9543{
c60fbb00
AD		 9544 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9545 struct net_device *netdev = adapter->netdev;
9a799d71 9546
83c61fa9 9547#ifdef CONFIG_PCI_IOV
14438464 9548 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9549 struct pci_dev *bdev, *vfdev;
9550 u32 dw0, dw1, dw2, dw3;
9551 int vf, pos;
9552 u16 req_id, pf_func;
9553
9554 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9555 adapter->num_vfs == 0)
9556 goto skip_bad_vf_detection;
9557
9558 bdev = pdev->bus->self;
62f87c0e 9559 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9560 bdev = bdev->bus->self;
9561
9562 if (!bdev)
9563 goto skip_bad_vf_detection;
9564
9565 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9566 if (!pos)
9567 goto skip_bad_vf_detection;
9568
14438464
MR		 9569 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9570 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9571 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9572 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9573 if (ixgbe_removed(hw->hw_addr))
9574 goto skip_bad_vf_detection;
83c61fa9
GR		 9575
9576 req_id = dw1 >> 16;
9577 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9578 if (!(req_id & 0x0080))
9579 goto skip_bad_vf_detection;
9580
9581 pf_func = req_id & 0x01;
9582 if ((pf_func & 1) == (pdev->devfn & 1)) {
9583 unsigned int device_id;
9584
9585 vf = (req_id & 0x7F) >> 1;
9586 e_dev_err("VF %d has caused a PCIe error\n", vf);
9587 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9588 "%8.8x\tdw3: %8.8x\n",
9589 dw0, dw1, dw2, dw3);
9590 switch (adapter->hw.mac.type) {
9591 case ixgbe_mac_82599EB:
9592 device_id = IXGBE_82599_VF_DEVICE_ID;
9593 break;
9594 case ixgbe_mac_X540:
9595 device_id = IXGBE_X540_VF_DEVICE_ID;
9596 break;
9a75a1ac
DS		 9597 case ixgbe_mac_X550:
9598 device_id = IXGBE_DEV_ID_X550_VF;
9599 break;
9600 case ixgbe_mac_X550EM_x:
9601 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9602 break;
83c61fa9
GR		 9603 default:
9604 device_id = 0;
9605 break;
9606 }
9607
9608 /* Find the pci device of the offending VF */
36e90319 9609 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9610 while (vfdev) {
9611 if (vfdev->devfn == (req_id & 0xFF))
9612 break;
36e90319 9613 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9614 device_id, vfdev);
9615 }
9616 /*
9617 * There's a slim chance the VF could have been hot plugged,
9618 * so if it is no longer present we don't need to issue the
9619 * VFLR. Just clean up the AER in that case.
9620 */
9621 if (vfdev) {
9079e416 9622 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9623 /* Free device reference count */
9624 pci_dev_put(vfdev);
83c61fa9
GR		 9625 }
9626
9627 pci_cleanup_aer_uncorrect_error_status(pdev);
9628 }
9629
9630 /*
9631 * Even though the error may have occurred on the other port
9632 * we still need to increment the vf error reference count for
9633 * both ports because the I/O resume function will be called
9634 * for both of them.
9635 */
9636 adapter->vferr_refcount++;
9637
9638 return PCI_ERS_RESULT_RECOVERED;
9639
9640skip_bad_vf_detection:
9641#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9642 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9643 return PCI_ERS_RESULT_DISCONNECT;
9644
41c62843 9645 rtnl_lock();
9a799d71
AK		 9646 netif_device_detach(netdev);
9647
41c62843
MR		 9648 if (state == pci_channel_io_perm_failure) {
9649 rtnl_unlock();
3044b8d1 9650 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9651 }
3044b8d1 9652
9a799d71
AK		 9653 if (netif_running(netdev))
9654 ixgbe_down(adapter);
41c62843
MR		 9655
9656 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9657 pci_disable_device(pdev);
9658 rtnl_unlock();
9a799d71 9659
b4617240 9660 /* Request a slot reset. */
9a799d71
AK		 9661 return PCI_ERS_RESULT_NEED_RESET;
9662}
9663
9664/**
9665 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9666 * @pdev: Pointer to PCI device
9667 *
9668 * Restart the card from scratch, as if from a cold-boot.
9669 */
9670static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9671{
c60fbb00 9672 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9673 pci_ers_result_t result;
9674 int err;
9a799d71 9675
9ce77666 9676 if (pci_enable_device_mem(pdev)) {
396e799c 9677 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9678 result = PCI_ERS_RESULT_DISCONNECT;
9679 } else {
4e857c58 9680 smp_mb__before_atomic();
41c62843 9681 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9682 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9683 pci_set_master(pdev);
9684 pci_restore_state(pdev);
c0e1f68b 9685 pci_save_state(pdev);
9a799d71 9686
dd4d8ca6 9687 pci_wake_from_d3(pdev, false);
9a799d71 9688
6fabd715 9689 ixgbe_reset(adapter);
88512539 9690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9691 result = PCI_ERS_RESULT_RECOVERED;
9692 }
9693
9694 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9695 if (err) {
849c4542
ET		 9696 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9697 "failed 0x%0x\n", err);
6fabd715
PWJ		 9698 /* non-fatal, continue */
9699 }
9a799d71 9700
6fabd715 9701 return result;
9a799d71
AK		 9702}
9703
9704/**
9705 * ixgbe_io_resume - called when traffic can start flowing again.
9706 * @pdev: Pointer to PCI device
9707 *
9708 * This callback is called when the error recovery driver tells us that
9709 * its OK to resume normal operation.
9710 */
9711static void ixgbe_io_resume(struct pci_dev *pdev)
9712{
c60fbb00
AD		 9713 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9714 struct net_device *netdev = adapter->netdev;
9a799d71 9715
83c61fa9
GR		 9716#ifdef CONFIG_PCI_IOV
9717 if (adapter->vferr_refcount) {
9718 e_info(drv, "Resuming after VF err\n");
9719 adapter->vferr_refcount--;
9720 return;
9721 }
9722
9723#endif
c7ccde0f
AD		 9724 if (netif_running(netdev))
9725 ixgbe_up(adapter);
9a799d71
AK		 9726
9727 netif_device_attach(netdev);
9a799d71
AK		 9728}
9729
3646f0e5 9730static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9731 .error_detected = ixgbe_io_error_detected,
9732 .slot_reset = ixgbe_io_slot_reset,
9733 .resume = ixgbe_io_resume,
9734};
9735
9736static struct pci_driver ixgbe_driver = {
9737 .name = ixgbe_driver_name,
9738 .id_table = ixgbe_pci_tbl,
9739 .probe = ixgbe_probe,
9f9a12f8 9740 .remove = ixgbe_remove,
9a799d71
AK		 9741#ifdef CONFIG_PM
9742 .suspend = ixgbe_suspend,
9743 .resume = ixgbe_resume,
9744#endif
9745 .shutdown = ixgbe_shutdown,
da36b647 9746 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9747 .err_handler = &ixgbe_err_handler
9748};
9749
9750/**
9751 * ixgbe_init_module - Driver Registration Routine
9752 *
9753 * ixgbe_init_module is the first routine called when the driver is
9754 * loaded. All it does is register with the PCI subsystem.
9755 **/
9756static int __init ixgbe_init_module(void)
9757{
9758 int ret;
c7689578 9759 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9760 pr_info("%s\n", ixgbe_copyright);
9a799d71 9761
780484d8
MR		 9762 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
9763 if (!ixgbe_wq) {
9764 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
9765 return -ENOMEM;
9766 }
9767
00949167 9768 ixgbe_dbg_init();
00949167 9769
f01fc1a8
JK		 9770 ret = pci_register_driver(&ixgbe_driver);
9771 if (ret) {
f01fc1a8 9772 ixgbe_dbg_exit();
f01fc1a8
JK		 9773 return ret;
9774 }
9775
5dd2d332 9776#ifdef CONFIG_IXGBE_DCA
bd0362dd 9777 dca_register_notify(&dca_notifier);
bd0362dd 9778#endif
5dd2d332 9779
f01fc1a8 9780 return 0;
9a799d71 9781}
b4617240 9782
9a799d71
AK		 9783module_init(ixgbe_init_module);
9784
9785/**
9786 * ixgbe_exit_module - Driver Exit Cleanup Routine
9787 *
9788 * ixgbe_exit_module is called just before the driver is removed
9789 * from memory.
9790 **/
9791static void __exit ixgbe_exit_module(void)
9792{
5dd2d332 9793#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9794 dca_unregister_notify(&dca_notifier);
9795#endif
9a799d71 9796 pci_unregister_driver(&ixgbe_driver);
00949167 9797
00949167 9798 ixgbe_dbg_exit();
780484d8
MR		 9799 if (ixgbe_wq) {
9800 destroy_workqueue(ixgbe_wq);
9801 ixgbe_wq = NULL;
9802 }
9a799d71 9803}
bd0362dd 9804
5dd2d332 9805#ifdef CONFIG_IXGBE_DCA
bd0362dd 9806static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9807 void *p)
bd0362dd
JC		 9808{
9809 int ret_val;
9810
9811 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9812 __ixgbe_notify_dca);
bd0362dd
JC		 9813
9814 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9815}
b453368d 9816
5dd2d332 9817#endif /* CONFIG_IXGBE_DCA */
849c4542 9818
9a799d71
AK		 9819module_exit(ixgbe_exit_module);
9820
9821/* ixgbe_main.c */
Linux kernel - Deliverables
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