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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
8af3c33f | 58 | #ifdef IXGBE_FCOE |
ea81875a NP |
59 | char ixgbe_default_device_descr[] = |
60 | "Intel(R) 10 Gigabit Network Connection"; | |
8af3c33f JK |
61 | #else |
62 | static char ixgbe_default_device_descr[] = | |
63 | "Intel(R) 10 Gigabit Network Connection"; | |
64 | #endif | |
75e3d3c6 | 65 | #define MAJ 3 |
eef4560f DS |
66 | #define MIN 9 |
67 | #define BUILD 15 | |
75e3d3c6 | 68 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 69 | __stringify(BUILD) "-k" |
9c8eb720 | 70 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 71 | static const char ixgbe_copyright[] = |
94971820 | 72 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
73 | |
74 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 75 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 76 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 77 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
78 | }; |
79 | ||
80 | /* ixgbe_pci_tbl - PCI Device ID Table | |
81 | * | |
82 | * Wildcard entries (PCI_ANY_ID) should come last | |
83 | * Last entry must be all 0s | |
84 | * | |
85 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
86 | * Class, Class Mask, private data (not used) } | |
87 | */ | |
a3aa1884 | 88 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
112 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
113 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
114 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 115 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 116 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
117 | /* required last entry */ |
118 | {0, } | |
119 | }; | |
120 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
121 | ||
5dd2d332 | 122 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 123 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 124 | void *p); |
bd0362dd JC |
125 | static struct notifier_block dca_notifier = { |
126 | .notifier_call = ixgbe_notify_dca, | |
127 | .next = NULL, | |
128 | .priority = 0 | |
129 | }; | |
130 | #endif | |
131 | ||
1cdd1ec8 GR |
132 | #ifdef CONFIG_PCI_IOV |
133 | static unsigned int max_vfs; | |
134 | module_param(max_vfs, uint, 0); | |
e8e9f696 | 135 | MODULE_PARM_DESC(max_vfs, |
6b42a9c5 | 136 | "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63"); |
1cdd1ec8 GR |
137 | #endif /* CONFIG_PCI_IOV */ |
138 | ||
8ef78adc PWJ |
139 | static unsigned int allow_unsupported_sfp; |
140 | module_param(allow_unsupported_sfp, uint, 0); | |
141 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
142 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
143 | ||
b3f4d599 | 144 | #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) |
145 | static int debug = -1; | |
146 | module_param(debug, int, 0); | |
147 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
148 | ||
9a799d71 AK |
149 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
150 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
151 | MODULE_LICENSE("GPL"); | |
152 | MODULE_VERSION(DRV_VERSION); | |
153 | ||
7086400d AD |
154 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
155 | { | |
156 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
157 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
158 | schedule_work(&adapter->service_task); | |
159 | } | |
160 | ||
161 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
162 | { | |
163 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
164 | ||
52f33af8 | 165 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
166 | smp_mb__before_clear_bit(); |
167 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
168 | } | |
169 | ||
dcd79aeb TI |
170 | struct ixgbe_reg_info { |
171 | u32 ofs; | |
172 | char *name; | |
173 | }; | |
174 | ||
175 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
176 | ||
177 | /* General Registers */ | |
178 | {IXGBE_CTRL, "CTRL"}, | |
179 | {IXGBE_STATUS, "STATUS"}, | |
180 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
181 | ||
182 | /* Interrupt Registers */ | |
183 | {IXGBE_EICR, "EICR"}, | |
184 | ||
185 | /* RX Registers */ | |
186 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
187 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
188 | {IXGBE_RDLEN(0), "RDLEN"}, | |
189 | {IXGBE_RDH(0), "RDH"}, | |
190 | {IXGBE_RDT(0), "RDT"}, | |
191 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
192 | {IXGBE_RDBAL(0), "RDBAL"}, | |
193 | {IXGBE_RDBAH(0), "RDBAH"}, | |
194 | ||
195 | /* TX Registers */ | |
196 | {IXGBE_TDBAL(0), "TDBAL"}, | |
197 | {IXGBE_TDBAH(0), "TDBAH"}, | |
198 | {IXGBE_TDLEN(0), "TDLEN"}, | |
199 | {IXGBE_TDH(0), "TDH"}, | |
200 | {IXGBE_TDT(0), "TDT"}, | |
201 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
202 | ||
203 | /* List Terminator */ | |
204 | {} | |
205 | }; | |
206 | ||
207 | ||
208 | /* | |
209 | * ixgbe_regdump - register printout routine | |
210 | */ | |
211 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
212 | { | |
213 | int i = 0, j = 0; | |
214 | char rname[16]; | |
215 | u32 regs[64]; | |
216 | ||
217 | switch (reginfo->ofs) { | |
218 | case IXGBE_SRRCTL(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
221 | break; | |
222 | case IXGBE_DCA_RXCTRL(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
225 | break; | |
226 | case IXGBE_RDLEN(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
229 | break; | |
230 | case IXGBE_RDH(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
233 | break; | |
234 | case IXGBE_RDT(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
237 | break; | |
238 | case IXGBE_RXDCTL(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
241 | break; | |
242 | case IXGBE_RDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
245 | break; | |
246 | case IXGBE_RDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDBAL(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
253 | break; | |
254 | case IXGBE_TDBAH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
257 | break; | |
258 | case IXGBE_TDLEN(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
261 | break; | |
262 | case IXGBE_TDH(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
265 | break; | |
266 | case IXGBE_TDT(0): | |
267 | for (i = 0; i < 64; i++) | |
268 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
269 | break; | |
270 | case IXGBE_TXDCTL(0): | |
271 | for (i = 0; i < 64; i++) | |
272 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
273 | break; | |
274 | default: | |
c7689578 | 275 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
276 | IXGBE_READ_REG(hw, reginfo->ofs)); |
277 | return; | |
278 | } | |
279 | ||
280 | for (i = 0; i < 8; i++) { | |
281 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 282 | pr_err("%-15s", rname); |
dcd79aeb | 283 | for (j = 0; j < 8; j++) |
c7689578 JP |
284 | pr_cont(" %08x", regs[i*8+j]); |
285 | pr_cont("\n"); | |
dcd79aeb TI |
286 | } |
287 | ||
288 | } | |
289 | ||
290 | /* | |
291 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
292 | */ | |
293 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
294 | { | |
295 | struct net_device *netdev = adapter->netdev; | |
296 | struct ixgbe_hw *hw = &adapter->hw; | |
297 | struct ixgbe_reg_info *reginfo; | |
298 | int n = 0; | |
299 | struct ixgbe_ring *tx_ring; | |
729739b7 | 300 | struct ixgbe_tx_buffer *tx_buffer; |
dcd79aeb TI |
301 | union ixgbe_adv_tx_desc *tx_desc; |
302 | struct my_u0 { u64 a; u64 b; } *u0; | |
303 | struct ixgbe_ring *rx_ring; | |
304 | union ixgbe_adv_rx_desc *rx_desc; | |
305 | struct ixgbe_rx_buffer *rx_buffer_info; | |
306 | u32 staterr; | |
307 | int i = 0; | |
308 | ||
309 | if (!netif_msg_hw(adapter)) | |
310 | return; | |
311 | ||
312 | /* Print netdevice Info */ | |
313 | if (netdev) { | |
314 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 315 | pr_info("Device Name state " |
dcd79aeb | 316 | "trans_start last_rx\n"); |
c7689578 JP |
317 | pr_info("%-15s %016lX %016lX %016lX\n", |
318 | netdev->name, | |
319 | netdev->state, | |
320 | netdev->trans_start, | |
321 | netdev->last_rx); | |
dcd79aeb TI |
322 | } |
323 | ||
324 | /* Print Registers */ | |
325 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 326 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
327 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
328 | reginfo->name; reginfo++) { | |
329 | ixgbe_regdump(hw, reginfo); | |
330 | } | |
331 | ||
332 | /* Print TX Ring Summary */ | |
333 | if (!netdev || !netif_running(netdev)) | |
334 | goto exit; | |
335 | ||
336 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 337 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
338 | for (n = 0; n < adapter->num_tx_queues; n++) { |
339 | tx_ring = adapter->tx_ring[n]; | |
729739b7 | 340 | tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; |
d3d00239 | 341 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb | 342 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
729739b7 AD |
343 | (u64)dma_unmap_addr(tx_buffer, dma), |
344 | dma_unmap_len(tx_buffer, len), | |
345 | tx_buffer->next_to_watch, | |
346 | (u64)tx_buffer->time_stamp); | |
dcd79aeb TI |
347 | } |
348 | ||
349 | /* Print TX Rings */ | |
350 | if (!netif_msg_tx_done(adapter)) | |
351 | goto rx_ring_summary; | |
352 | ||
353 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
354 | ||
355 | /* Transmit Descriptor Formats | |
356 | * | |
357 | * Advanced Transmit Descriptor | |
358 | * +--------------------------------------------------------------+ | |
359 | * 0 | Buffer Address [63:0] | | |
360 | * +--------------------------------------------------------------+ | |
361 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
362 | * +--------------------------------------------------------------+ | |
363 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
364 | */ | |
365 | ||
366 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
367 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
368 | pr_info("------------------------------------\n"); |
369 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
370 | pr_info("------------------------------------\n"); | |
371 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
372 | "[PlPOIdStDDt Ln] [bi->dma ] " |
373 | "leng ntw timestamp bi->skb\n"); | |
374 | ||
375 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 376 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 377 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
dcd79aeb | 378 | u0 = (struct my_u0 *)tx_desc; |
c7689578 | 379 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 380 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
381 | le64_to_cpu(u0->a), |
382 | le64_to_cpu(u0->b), | |
729739b7 AD |
383 | (u64)dma_unmap_addr(tx_buffer, dma), |
384 | dma_unmap_len(tx_buffer, len), | |
385 | tx_buffer->next_to_watch, | |
386 | (u64)tx_buffer->time_stamp, | |
387 | tx_buffer->skb); | |
dcd79aeb TI |
388 | if (i == tx_ring->next_to_use && |
389 | i == tx_ring->next_to_clean) | |
c7689578 | 390 | pr_cont(" NTC/U\n"); |
dcd79aeb | 391 | else if (i == tx_ring->next_to_use) |
c7689578 | 392 | pr_cont(" NTU\n"); |
dcd79aeb | 393 | else if (i == tx_ring->next_to_clean) |
c7689578 | 394 | pr_cont(" NTC\n"); |
dcd79aeb | 395 | else |
c7689578 | 396 | pr_cont("\n"); |
dcd79aeb TI |
397 | |
398 | if (netif_msg_pktdata(adapter) && | |
729739b7 | 399 | dma_unmap_len(tx_buffer, len) != 0) |
dcd79aeb TI |
400 | print_hex_dump(KERN_INFO, "", |
401 | DUMP_PREFIX_ADDRESS, 16, 1, | |
729739b7 AD |
402 | phys_to_virt(dma_unmap_addr(tx_buffer, |
403 | dma)), | |
404 | dma_unmap_len(tx_buffer, len), | |
405 | true); | |
dcd79aeb TI |
406 | } |
407 | } | |
408 | ||
409 | /* Print RX Rings Summary */ | |
410 | rx_ring_summary: | |
411 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 412 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
413 | for (n = 0; n < adapter->num_rx_queues; n++) { |
414 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
415 | pr_info("%5d %5X %5X\n", |
416 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
417 | } |
418 | ||
419 | /* Print RX Rings */ | |
420 | if (!netif_msg_rx_status(adapter)) | |
421 | goto exit; | |
422 | ||
423 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
424 | ||
425 | /* Advanced Receive Descriptor (Read) Format | |
426 | * 63 1 0 | |
427 | * +-----------------------------------------------------+ | |
428 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
429 | * +----------------------------------------------+------+ | |
430 | * 8 | Header Buffer Address [63:1] | DD | | |
431 | * +-----------------------------------------------------+ | |
432 | * | |
433 | * | |
434 | * Advanced Receive Descriptor (Write-Back) Format | |
435 | * | |
436 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
437 | * +------------------------------------------------------+ | |
438 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
439 | * | Checksum Ident | | | | Type | Type | | |
440 | * +------------------------------------------------------+ | |
441 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
442 | * +------------------------------------------------------+ | |
443 | * 63 48 47 32 31 20 19 0 | |
444 | */ | |
445 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
446 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
447 | pr_info("------------------------------------\n"); |
448 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
449 | pr_info("------------------------------------\n"); | |
450 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
451 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
452 | "<-- Adv Rx Read format\n"); | |
c7689578 | 453 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
454 | "[vl er S cks ln] ---------------- [bi->skb] " |
455 | "<-- Adv Rx Write-Back format\n"); | |
456 | ||
457 | for (i = 0; i < rx_ring->count; i++) { | |
458 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 459 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
460 | u0 = (struct my_u0 *)rx_desc; |
461 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
462 | if (staterr & IXGBE_RXD_STAT_DD) { | |
463 | /* Descriptor Done */ | |
c7689578 | 464 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
465 | "%016llX ---------------- %p", i, |
466 | le64_to_cpu(u0->a), | |
467 | le64_to_cpu(u0->b), | |
468 | rx_buffer_info->skb); | |
469 | } else { | |
c7689578 | 470 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
471 | "%016llX %016llX %p", i, |
472 | le64_to_cpu(u0->a), | |
473 | le64_to_cpu(u0->b), | |
474 | (u64)rx_buffer_info->dma, | |
475 | rx_buffer_info->skb); | |
476 | ||
477 | if (netif_msg_pktdata(adapter)) { | |
478 | print_hex_dump(KERN_INFO, "", | |
479 | DUMP_PREFIX_ADDRESS, 16, 1, | |
480 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 481 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
482 | } |
483 | } | |
484 | ||
485 | if (i == rx_ring->next_to_use) | |
c7689578 | 486 | pr_cont(" NTU\n"); |
dcd79aeb | 487 | else if (i == rx_ring->next_to_clean) |
c7689578 | 488 | pr_cont(" NTC\n"); |
dcd79aeb | 489 | else |
c7689578 | 490 | pr_cont("\n"); |
dcd79aeb TI |
491 | |
492 | } | |
493 | } | |
494 | ||
495 | exit: | |
496 | return; | |
497 | } | |
498 | ||
5eba3699 AV |
499 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
500 | { | |
501 | u32 ctrl_ext; | |
502 | ||
503 | /* Let firmware take over control of h/w */ | |
504 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
505 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 506 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
507 | } |
508 | ||
509 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
510 | { | |
511 | u32 ctrl_ext; | |
512 | ||
513 | /* Let firmware know the driver has taken over */ | |
514 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
515 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 516 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 517 | } |
9a799d71 | 518 | |
49ce9c2c | 519 | /** |
e8e26350 PW |
520 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors |
521 | * @adapter: pointer to adapter struct | |
522 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
523 | * @queue: queue to map the corresponding interrupt to | |
524 | * @msix_vector: the vector to map to the corresponding queue | |
525 | * | |
526 | */ | |
527 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 528 | u8 queue, u8 msix_vector) |
9a799d71 AK |
529 | { |
530 | u32 ivar, index; | |
e8e26350 PW |
531 | struct ixgbe_hw *hw = &adapter->hw; |
532 | switch (hw->mac.type) { | |
533 | case ixgbe_mac_82598EB: | |
534 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
535 | if (direction == -1) | |
536 | direction = 0; | |
537 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
538 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
539 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
540 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
541 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
542 | break; | |
543 | case ixgbe_mac_82599EB: | |
b93a2226 | 544 | case ixgbe_mac_X540: |
e8e26350 PW |
545 | if (direction == -1) { |
546 | /* other causes */ | |
547 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
548 | index = ((queue & 1) * 8); | |
549 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
550 | ivar &= ~(0xFF << index); | |
551 | ivar |= (msix_vector << index); | |
552 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
553 | break; | |
554 | } else { | |
555 | /* tx or rx causes */ | |
556 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
557 | index = ((16 * (queue & 1)) + (8 * direction)); | |
558 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
559 | ivar &= ~(0xFF << index); | |
560 | ivar |= (msix_vector << index); | |
561 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
562 | break; | |
563 | } | |
564 | default: | |
565 | break; | |
566 | } | |
9a799d71 AK |
567 | } |
568 | ||
fe49f04a | 569 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 570 | u64 qmask) |
fe49f04a AD |
571 | { |
572 | u32 mask; | |
573 | ||
bd508178 AD |
574 | switch (adapter->hw.mac.type) { |
575 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
576 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
577 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
578 | break; |
579 | case ixgbe_mac_82599EB: | |
b93a2226 | 580 | case ixgbe_mac_X540: |
fe49f04a AD |
581 | mask = (qmask & 0xFFFFFFFF); |
582 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
583 | mask = (qmask >> 32); | |
584 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
585 | break; |
586 | default: | |
587 | break; | |
fe49f04a AD |
588 | } |
589 | } | |
590 | ||
729739b7 AD |
591 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring, |
592 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 593 | { |
729739b7 AD |
594 | if (tx_buffer->skb) { |
595 | dev_kfree_skb_any(tx_buffer->skb); | |
596 | if (dma_unmap_len(tx_buffer, len)) | |
d3d00239 | 597 | dma_unmap_single(ring->dev, |
729739b7 AD |
598 | dma_unmap_addr(tx_buffer, dma), |
599 | dma_unmap_len(tx_buffer, len), | |
600 | DMA_TO_DEVICE); | |
601 | } else if (dma_unmap_len(tx_buffer, len)) { | |
602 | dma_unmap_page(ring->dev, | |
603 | dma_unmap_addr(tx_buffer, dma), | |
604 | dma_unmap_len(tx_buffer, len), | |
605 | DMA_TO_DEVICE); | |
e5a43549 | 606 | } |
729739b7 AD |
607 | tx_buffer->next_to_watch = NULL; |
608 | tx_buffer->skb = NULL; | |
609 | dma_unmap_len_set(tx_buffer, len, 0); | |
610 | /* tx_buffer must be completely set up in the transmit path */ | |
9a799d71 AK |
611 | } |
612 | ||
943561d3 | 613 | static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter) |
c84d324c JF |
614 | { |
615 | struct ixgbe_hw *hw = &adapter->hw; | |
616 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
c84d324c | 617 | int i; |
943561d3 | 618 | u32 data; |
c84d324c | 619 | |
943561d3 AD |
620 | if ((hw->fc.current_mode != ixgbe_fc_full) && |
621 | (hw->fc.current_mode != ixgbe_fc_rx_pause)) | |
622 | return; | |
c84d324c | 623 | |
943561d3 AD |
624 | switch (hw->mac.type) { |
625 | case ixgbe_mac_82598EB: | |
626 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
627 | break; | |
628 | default: | |
629 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); | |
630 | } | |
631 | hwstats->lxoffrxc += data; | |
c84d324c | 632 | |
943561d3 AD |
633 | /* refill credits (no tx hang) if we received xoff */ |
634 | if (!data) | |
c84d324c | 635 | return; |
943561d3 AD |
636 | |
637 | for (i = 0; i < adapter->num_tx_queues; i++) | |
638 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
639 | &adapter->tx_ring[i]->state); | |
640 | } | |
641 | ||
642 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) | |
643 | { | |
644 | struct ixgbe_hw *hw = &adapter->hw; | |
645 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
646 | u32 xoff[8] = {0}; | |
647 | int i; | |
648 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
649 | ||
650 | if (adapter->ixgbe_ieee_pfc) | |
651 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
652 | ||
653 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) { | |
654 | ixgbe_update_xoff_rx_lfc(adapter); | |
c84d324c | 655 | return; |
943561d3 | 656 | } |
c84d324c JF |
657 | |
658 | /* update stats for each tc, only valid with PFC enabled */ | |
659 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
660 | switch (hw->mac.type) { | |
661 | case ixgbe_mac_82598EB: | |
662 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 663 | break; |
c84d324c JF |
664 | default: |
665 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 666 | } |
c84d324c JF |
667 | hwstats->pxoffrxc[i] += xoff[i]; |
668 | } | |
669 | ||
670 | /* disarm tx queues that have received xoff frames */ | |
671 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
672 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 673 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
674 | |
675 | if (xoff[tc]) | |
676 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 677 | } |
26f23d82 YZ |
678 | } |
679 | ||
c84d324c | 680 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 681 | { |
7d7ce682 | 682 | return ring->stats.packets; |
c84d324c JF |
683 | } |
684 | ||
685 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
686 | { | |
687 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 688 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 689 | |
c84d324c JF |
690 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
691 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
692 | ||
693 | if (head != tail) | |
694 | return (head < tail) ? | |
695 | tail - head : (tail + ring->count - head); | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
701 | { | |
702 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
703 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
704 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
705 | bool ret = false; | |
706 | ||
7d637bcc | 707 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
708 | |
709 | /* | |
710 | * Check for a hung queue, but be thorough. This verifies | |
711 | * that a transmit has been completed since the previous | |
712 | * check AND there is at least one packet pending. The | |
713 | * ARMED bit is set to indicate a potential hang. The | |
714 | * bit is cleared if a pause frame is received to remove | |
715 | * false hang detection due to PFC or 802.3x frames. By | |
716 | * requiring this to fail twice we avoid races with | |
717 | * pfc clearing the ARMED bit and conditions where we | |
718 | * run the check_tx_hang logic with a transmit completion | |
719 | * pending but without time to complete it yet. | |
720 | */ | |
721 | if ((tx_done_old == tx_done) && tx_pending) { | |
722 | /* make sure it is true for two checks in a row */ | |
723 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
724 | &tx_ring->state); | |
725 | } else { | |
726 | /* update completed stats and continue */ | |
727 | tx_ring->tx_stats.tx_done_old = tx_done; | |
728 | /* reset the countdown */ | |
729 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
730 | } |
731 | ||
c84d324c | 732 | return ret; |
9a799d71 AK |
733 | } |
734 | ||
c83c6cbd AD |
735 | /** |
736 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
737 | * @adapter: driver private struct | |
738 | **/ | |
739 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
740 | { | |
741 | ||
742 | /* Do the reset outside of interrupt context */ | |
743 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
744 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
745 | ixgbe_service_event_schedule(adapter); | |
746 | } | |
747 | } | |
e01c31a5 | 748 | |
9a799d71 AK |
749 | /** |
750 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 751 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 752 | * @tx_ring: tx ring to clean |
9a799d71 | 753 | **/ |
fe49f04a | 754 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 755 | struct ixgbe_ring *tx_ring) |
9a799d71 | 756 | { |
fe49f04a | 757 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
758 | struct ixgbe_tx_buffer *tx_buffer; |
759 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 760 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 761 | unsigned int budget = q_vector->tx.work_limit; |
729739b7 AD |
762 | unsigned int i = tx_ring->next_to_clean; |
763 | ||
764 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
765 | return true; | |
9a799d71 | 766 | |
d3d00239 | 767 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 768 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
729739b7 | 769 | i -= tx_ring->count; |
12207e49 | 770 | |
729739b7 | 771 | do { |
d3d00239 AD |
772 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
773 | ||
774 | /* if next_to_watch is not set then there is no work pending */ | |
775 | if (!eop_desc) | |
776 | break; | |
777 | ||
7f83a9e6 AD |
778 | /* prevent any other reads prior to eop_desc */ |
779 | rmb(); | |
780 | ||
d3d00239 AD |
781 | /* if DD is not set pending work has not been completed */ |
782 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
783 | break; | |
8ad494b0 | 784 | |
d3d00239 AD |
785 | /* clear next_to_watch to prevent false hangs */ |
786 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 787 | |
091a6246 AD |
788 | /* update the statistics for this packet */ |
789 | total_bytes += tx_buffer->bytecount; | |
790 | total_packets += tx_buffer->gso_segs; | |
791 | ||
3a6a4eda | 792 | #ifdef CONFIG_IXGBE_PTP |
0ede4a60 JK |
793 | if (unlikely(tx_buffer->tx_flags & IXGBE_TX_FLAGS_TSTAMP)) |
794 | ixgbe_ptp_tx_hwtstamp(q_vector, tx_buffer->skb); | |
3a6a4eda | 795 | #endif |
0ede4a60 | 796 | |
fd0db0ed AD |
797 | /* free the skb */ |
798 | dev_kfree_skb_any(tx_buffer->skb); | |
799 | ||
729739b7 AD |
800 | /* unmap skb header data */ |
801 | dma_unmap_single(tx_ring->dev, | |
802 | dma_unmap_addr(tx_buffer, dma), | |
803 | dma_unmap_len(tx_buffer, len), | |
804 | DMA_TO_DEVICE); | |
805 | ||
fd0db0ed AD |
806 | /* clear tx_buffer data */ |
807 | tx_buffer->skb = NULL; | |
729739b7 | 808 | dma_unmap_len_set(tx_buffer, len, 0); |
fd0db0ed | 809 | |
729739b7 AD |
810 | /* unmap remaining buffers */ |
811 | while (tx_desc != eop_desc) { | |
d3d00239 AD |
812 | tx_buffer++; |
813 | tx_desc++; | |
8ad494b0 | 814 | i++; |
729739b7 AD |
815 | if (unlikely(!i)) { |
816 | i -= tx_ring->count; | |
d3d00239 | 817 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 818 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 819 | } |
e01c31a5 | 820 | |
729739b7 AD |
821 | /* unmap any remaining paged data */ |
822 | if (dma_unmap_len(tx_buffer, len)) { | |
823 | dma_unmap_page(tx_ring->dev, | |
824 | dma_unmap_addr(tx_buffer, dma), | |
825 | dma_unmap_len(tx_buffer, len), | |
826 | DMA_TO_DEVICE); | |
827 | dma_unmap_len_set(tx_buffer, len, 0); | |
828 | } | |
829 | } | |
830 | ||
831 | /* move us one more past the eop_desc for start of next pkt */ | |
832 | tx_buffer++; | |
833 | tx_desc++; | |
834 | i++; | |
835 | if (unlikely(!i)) { | |
836 | i -= tx_ring->count; | |
837 | tx_buffer = tx_ring->tx_buffer_info; | |
838 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
839 | } | |
840 | ||
841 | /* issue prefetch for next Tx descriptor */ | |
842 | prefetch(tx_desc); | |
12207e49 | 843 | |
729739b7 AD |
844 | /* update budget accounting */ |
845 | budget--; | |
846 | } while (likely(budget)); | |
847 | ||
848 | i += tx_ring->count; | |
9a799d71 | 849 | tx_ring->next_to_clean = i; |
d3d00239 | 850 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 851 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 852 | tx_ring->stats.packets += total_packets; |
d3d00239 | 853 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
854 | q_vector->tx.total_bytes += total_bytes; |
855 | q_vector->tx.total_packets += total_packets; | |
b953799e | 856 | |
c84d324c JF |
857 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
858 | /* schedule immediate reset if we believe we hung */ | |
859 | struct ixgbe_hw *hw = &adapter->hw; | |
c84d324c JF |
860 | e_err(drv, "Detected Tx Unit Hang\n" |
861 | " Tx Queue <%d>\n" | |
862 | " TDH, TDT <%x>, <%x>\n" | |
863 | " next_to_use <%x>\n" | |
864 | " next_to_clean <%x>\n" | |
865 | "tx_buffer_info[next_to_clean]\n" | |
866 | " time_stamp <%lx>\n" | |
867 | " jiffies <%lx>\n", | |
868 | tx_ring->queue_index, | |
869 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
870 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
871 | tx_ring->next_to_use, i, |
872 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
873 | |
874 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
875 | ||
876 | e_info(probe, | |
877 | "tx hang %d detected on queue %d, resetting adapter\n", | |
878 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
879 | ||
b953799e | 880 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 881 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
882 | |
883 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 884 | return true; |
b953799e | 885 | } |
9a799d71 | 886 | |
b2d96e0a AD |
887 | netdev_tx_completed_queue(txring_txq(tx_ring), |
888 | total_packets, total_bytes); | |
889 | ||
e092be60 | 890 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 891 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 892 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
893 | /* Make sure that anybody stopping the queue after this |
894 | * sees the new next_to_clean. | |
895 | */ | |
896 | smp_mb(); | |
729739b7 AD |
897 | if (__netif_subqueue_stopped(tx_ring->netdev, |
898 | tx_ring->queue_index) | |
899 | && !test_bit(__IXGBE_DOWN, &adapter->state)) { | |
900 | netif_wake_subqueue(tx_ring->netdev, | |
901 | tx_ring->queue_index); | |
5b7da515 | 902 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 903 | } |
e092be60 | 904 | } |
9a799d71 | 905 | |
59224555 | 906 | return !!budget; |
9a799d71 AK |
907 | } |
908 | ||
5dd2d332 | 909 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
910 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
911 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 912 | int cpu) |
bd0362dd | 913 | { |
33cf09c9 | 914 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
915 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
916 | u16 reg_offset; | |
33cf09c9 | 917 | |
33cf09c9 AD |
918 | switch (hw->mac.type) { |
919 | case ixgbe_mac_82598EB: | |
bdda1a61 | 920 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
921 | break; |
922 | case ixgbe_mac_82599EB: | |
b93a2226 | 923 | case ixgbe_mac_X540: |
bdda1a61 AD |
924 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
925 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
926 | break; |
927 | default: | |
bdda1a61 AD |
928 | /* for unknown hardware do not write register */ |
929 | return; | |
bd0362dd | 930 | } |
bdda1a61 AD |
931 | |
932 | /* | |
933 | * We can enable relaxed ordering for reads, but not writes when | |
934 | * DCA is enabled. This is due to a known issue in some chipsets | |
935 | * which will cause the DCA tag to be cleared. | |
936 | */ | |
937 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
938 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
939 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
940 | ||
941 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
942 | } |
943 | ||
bdda1a61 AD |
944 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
945 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 946 | int cpu) |
bd0362dd | 947 | { |
33cf09c9 | 948 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
949 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
950 | u8 reg_idx = rx_ring->reg_idx; | |
951 | ||
33cf09c9 AD |
952 | |
953 | switch (hw->mac.type) { | |
33cf09c9 | 954 | case ixgbe_mac_82599EB: |
b93a2226 | 955 | case ixgbe_mac_X540: |
bdda1a61 | 956 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
957 | break; |
958 | default: | |
959 | break; | |
960 | } | |
bdda1a61 AD |
961 | |
962 | /* | |
963 | * We can enable relaxed ordering for reads, but not writes when | |
964 | * DCA is enabled. This is due to a known issue in some chipsets | |
965 | * which will cause the DCA tag to be cleared. | |
966 | */ | |
967 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
968 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
969 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
970 | ||
971 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
972 | } |
973 | ||
974 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
975 | { | |
976 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 977 | struct ixgbe_ring *ring; |
bd0362dd | 978 | int cpu = get_cpu(); |
bd0362dd | 979 | |
33cf09c9 AD |
980 | if (q_vector->cpu == cpu) |
981 | goto out_no_update; | |
982 | ||
a557928e | 983 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 984 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 985 | |
a557928e | 986 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 987 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
988 | |
989 | q_vector->cpu = cpu; | |
990 | out_no_update: | |
bd0362dd JC |
991 | put_cpu(); |
992 | } | |
993 | ||
994 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
995 | { | |
996 | int i; | |
997 | ||
998 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
999 | return; | |
1000 | ||
e35ec126 AD |
1001 | /* always use CB2 mode, difference is masked in the CB driver */ |
1002 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
1003 | ||
49c7ffbe | 1004 | for (i = 0; i < adapter->num_q_vectors; i++) { |
33cf09c9 AD |
1005 | adapter->q_vector[i]->cpu = -1; |
1006 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
1007 | } |
1008 | } | |
1009 | ||
1010 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
1011 | { | |
c60fbb00 | 1012 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
1013 | unsigned long event = *(unsigned long *)data; |
1014 | ||
2a72c31e | 1015 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
1016 | return 0; |
1017 | ||
bd0362dd JC |
1018 | switch (event) { |
1019 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
1020 | /* if we're already enabled, don't do it again */ |
1021 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
1022 | break; | |
652f093f | 1023 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 1024 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
1025 | ixgbe_setup_dca(adapter); |
1026 | break; | |
1027 | } | |
1028 | /* Fall Through since DCA is disabled. */ | |
1029 | case DCA_PROVIDER_REMOVE: | |
1030 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
1031 | dca_remove_requester(dev); | |
1032 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
1033 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
1034 | } | |
1035 | break; | |
1036 | } | |
1037 | ||
652f093f | 1038 | return 0; |
bd0362dd | 1039 | } |
67a74ee2 | 1040 | |
bdda1a61 | 1041 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
1042 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
1043 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
1044 | struct sk_buff *skb) |
1045 | { | |
8a0da21b AD |
1046 | if (ring->netdev->features & NETIF_F_RXHASH) |
1047 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
1048 | } |
1049 | ||
f800326d | 1050 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1051 | /** |
1052 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
57efd44c | 1053 | * @ring: structure containing ring specific data |
ff886dfc AD |
1054 | * @rx_desc: advanced rx descriptor |
1055 | * | |
1056 | * Returns : true if it is FCoE pkt | |
1057 | */ | |
57efd44c | 1058 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring, |
ff886dfc AD |
1059 | union ixgbe_adv_rx_desc *rx_desc) |
1060 | { | |
1061 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1062 | ||
57efd44c | 1063 | return test_bit(__IXGBE_RX_FCOE, &ring->state) && |
ff886dfc AD |
1064 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == |
1065 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1066 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1067 | } | |
1068 | ||
f800326d | 1069 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1070 | /** |
1071 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1072 | * @ring: structure containing ring specific data |
1073 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1074 | * @skb: skb currently being received and modified |
1075 | **/ | |
8a0da21b | 1076 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1077 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1078 | struct sk_buff *skb) |
9a799d71 | 1079 | { |
8a0da21b | 1080 | skb_checksum_none_assert(skb); |
9a799d71 | 1081 | |
712744be | 1082 | /* Rx csum disabled */ |
8a0da21b | 1083 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1084 | return; |
e59bd25d AV |
1085 | |
1086 | /* if IP and error */ | |
f56e0cb1 AD |
1087 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1088 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1089 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1090 | return; |
1091 | } | |
e59bd25d | 1092 | |
f56e0cb1 | 1093 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1094 | return; |
1095 | ||
f56e0cb1 | 1096 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1097 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1098 | |
1099 | /* | |
1100 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1101 | * checksum errors. | |
1102 | */ | |
8a0da21b AD |
1103 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1104 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1105 | return; |
1106 | ||
8a0da21b | 1107 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1108 | return; |
1109 | } | |
1110 | ||
9a799d71 | 1111 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1112 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1113 | } |
1114 | ||
84ea2591 | 1115 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1116 | { |
f56e0cb1 | 1117 | rx_ring->next_to_use = val; |
f800326d AD |
1118 | |
1119 | /* update next to alloc since we have filled the ring */ | |
1120 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1121 | /* |
1122 | * Force memory writes to complete before letting h/w | |
1123 | * know there are new descriptors to fetch. (Only | |
1124 | * applicable for weak-ordered memory model archs, | |
1125 | * such as IA-64). | |
1126 | */ | |
1127 | wmb(); | |
84ea2591 | 1128 | writel(val, rx_ring->tail); |
e8e26350 PW |
1129 | } |
1130 | ||
f990b79b AD |
1131 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1132 | struct ixgbe_rx_buffer *bi) | |
1133 | { | |
1134 | struct page *page = bi->page; | |
f800326d | 1135 | dma_addr_t dma = bi->dma; |
f990b79b | 1136 | |
f800326d AD |
1137 | /* since we are recycling buffers we should seldom need to alloc */ |
1138 | if (likely(dma)) | |
f990b79b AD |
1139 | return true; |
1140 | ||
f800326d AD |
1141 | /* alloc new page for storage */ |
1142 | if (likely(!page)) { | |
8633c084 | 1143 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP, |
f800326d | 1144 | ixgbe_rx_pg_order(rx_ring)); |
f990b79b AD |
1145 | if (unlikely(!page)) { |
1146 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1147 | return false; | |
1148 | } | |
f800326d | 1149 | bi->page = page; |
f990b79b AD |
1150 | } |
1151 | ||
f800326d AD |
1152 | /* map page for use */ |
1153 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1154 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1155 | ||
1156 | /* | |
1157 | * if mapping failed free memory back to system since | |
1158 | * there isn't much point in holding memory we can't use | |
1159 | */ | |
1160 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
dd411ec4 | 1161 | __free_pages(page, ixgbe_rx_pg_order(rx_ring)); |
f800326d | 1162 | bi->page = NULL; |
f990b79b | 1163 | |
f990b79b AD |
1164 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1165 | return false; | |
1166 | } | |
1167 | ||
f800326d AD |
1168 | bi->dma = dma; |
1169 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1170 | ||
f990b79b AD |
1171 | return true; |
1172 | } | |
1173 | ||
9a799d71 | 1174 | /** |
f990b79b | 1175 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1176 | * @rx_ring: ring to place buffers on |
1177 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1178 | **/ |
fc77dc3c | 1179 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1180 | { |
9a799d71 | 1181 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1182 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1183 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1184 | |
f800326d AD |
1185 | /* nothing to do */ |
1186 | if (!cleaned_count) | |
fc77dc3c AD |
1187 | return; |
1188 | ||
e4f74028 | 1189 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1190 | bi = &rx_ring->rx_buffer_info[i]; |
1191 | i -= rx_ring->count; | |
9a799d71 | 1192 | |
f800326d AD |
1193 | do { |
1194 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1195 | break; |
d5f398ed | 1196 | |
f800326d AD |
1197 | /* |
1198 | * Refresh the desc even if buffer_addrs didn't change | |
1199 | * because each write-back erases this info. | |
1200 | */ | |
1201 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1202 | |
f990b79b AD |
1203 | rx_desc++; |
1204 | bi++; | |
9a799d71 | 1205 | i++; |
f990b79b | 1206 | if (unlikely(!i)) { |
e4f74028 | 1207 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1208 | bi = rx_ring->rx_buffer_info; |
1209 | i -= rx_ring->count; | |
1210 | } | |
1211 | ||
1212 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1213 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1214 | |
1215 | cleaned_count--; | |
1216 | } while (cleaned_count); | |
7c6e0a43 | 1217 | |
f990b79b AD |
1218 | i += rx_ring->count; |
1219 | ||
f56e0cb1 | 1220 | if (rx_ring->next_to_use != i) |
84ea2591 | 1221 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1222 | } |
1223 | ||
1d2024f6 AD |
1224 | /** |
1225 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1226 | * @data: pointer to the start of the headers | |
1227 | * @max_len: total length of section to find headers in | |
1228 | * | |
1229 | * This function is meant to determine the length of headers that will | |
1230 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1231 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1232 | * packets so that we can do basic things like calculating the gso_size | |
1233 | * based on the average data per packet. | |
1234 | **/ | |
1235 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1236 | unsigned int max_len) | |
1237 | { | |
1238 | union { | |
1239 | unsigned char *network; | |
1240 | /* l2 headers */ | |
1241 | struct ethhdr *eth; | |
1242 | struct vlan_hdr *vlan; | |
1243 | /* l3 headers */ | |
1244 | struct iphdr *ipv4; | |
1245 | } hdr; | |
1246 | __be16 protocol; | |
1247 | u8 nexthdr = 0; /* default to not TCP */ | |
1248 | u8 hlen; | |
1249 | ||
1250 | /* this should never happen, but better safe than sorry */ | |
1251 | if (max_len < ETH_HLEN) | |
1252 | return max_len; | |
1253 | ||
1254 | /* initialize network frame pointer */ | |
1255 | hdr.network = data; | |
1256 | ||
1257 | /* set first protocol and move network header forward */ | |
1258 | protocol = hdr.eth->h_proto; | |
1259 | hdr.network += ETH_HLEN; | |
1260 | ||
1261 | /* handle any vlan tag if present */ | |
1262 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1263 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1264 | return max_len; | |
1265 | ||
1266 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1267 | hdr.network += VLAN_HLEN; | |
1268 | } | |
1269 | ||
1270 | /* handle L3 protocols */ | |
1271 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1272 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1273 | return max_len; | |
1274 | ||
1275 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1276 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1277 | ||
1278 | /* verify hlen meets minimum size requirements */ | |
1279 | if (hlen < sizeof(struct iphdr)) | |
1280 | return hdr.network - data; | |
1281 | ||
1282 | /* record next protocol */ | |
1283 | nexthdr = hdr.ipv4->protocol; | |
1284 | hdr.network += hlen; | |
f800326d | 1285 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1286 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1287 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1288 | return max_len; | |
1289 | hdr.network += FCOE_HEADER_LEN; | |
1290 | #endif | |
1291 | } else { | |
1292 | return hdr.network - data; | |
1293 | } | |
1294 | ||
1295 | /* finally sort out TCP */ | |
1296 | if (nexthdr == IPPROTO_TCP) { | |
1297 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1298 | return max_len; | |
1299 | ||
1300 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1301 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1302 | ||
1303 | /* verify hlen meets minimum size requirements */ | |
1304 | if (hlen < sizeof(struct tcphdr)) | |
1305 | return hdr.network - data; | |
1306 | ||
1307 | hdr.network += hlen; | |
1308 | } | |
1309 | ||
1310 | /* | |
1311 | * If everything has gone correctly hdr.network should be the | |
1312 | * data section of the packet and will be the end of the header. | |
1313 | * If not then it probably represents the end of the last recognized | |
1314 | * header. | |
1315 | */ | |
1316 | if ((hdr.network - data) < max_len) | |
1317 | return hdr.network - data; | |
1318 | else | |
1319 | return max_len; | |
1320 | } | |
1321 | ||
4c1975d7 AD |
1322 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1323 | union ixgbe_adv_rx_desc *rx_desc, | |
1324 | struct sk_buff *skb) | |
aa80175a | 1325 | { |
4c1975d7 AD |
1326 | __le32 rsc_enabled; |
1327 | u32 rsc_cnt; | |
1328 | ||
1329 | if (!ring_is_rsc_enabled(rx_ring)) | |
1330 | return; | |
1331 | ||
1332 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1333 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1334 | ||
1335 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1336 | if (!rsc_enabled) | |
1337 | return; | |
1338 | ||
1339 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1340 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1341 | ||
1342 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1343 | } |
43634e82 | 1344 | |
1d2024f6 AD |
1345 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1346 | struct sk_buff *skb) | |
1347 | { | |
f800326d | 1348 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1349 | |
1350 | /* set gso_size to avoid messing up TCP MSS */ | |
1351 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1352 | IXGBE_CB(skb)->append_cnt); | |
1353 | } | |
1354 | ||
1355 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1356 | struct sk_buff *skb) | |
1357 | { | |
1358 | /* if append_cnt is 0 then frame is not RSC */ | |
1359 | if (!IXGBE_CB(skb)->append_cnt) | |
1360 | return; | |
1361 | ||
1362 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1363 | rx_ring->rx_stats.rsc_flush++; | |
1364 | ||
1365 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1366 | ||
1367 | /* gso_size is computed using append_cnt so always clear it last */ | |
1368 | IXGBE_CB(skb)->append_cnt = 0; | |
1369 | } | |
1370 | ||
8a0da21b AD |
1371 | /** |
1372 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1373 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1374 | * @rx_desc: pointer to the EOP Rx descriptor | |
1375 | * @skb: pointer to current skb being populated | |
f8212f97 | 1376 | * |
8a0da21b AD |
1377 | * This function checks the ring, descriptor, and packet information in |
1378 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1379 | * other fields within the skb. | |
f8212f97 | 1380 | **/ |
8a0da21b AD |
1381 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1382 | union ixgbe_adv_rx_desc *rx_desc, | |
1383 | struct sk_buff *skb) | |
f8212f97 | 1384 | { |
43e95f11 JF |
1385 | struct net_device *dev = rx_ring->netdev; |
1386 | ||
8a0da21b AD |
1387 | ixgbe_update_rsc_stats(rx_ring, skb); |
1388 | ||
1389 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1390 | |
8a0da21b AD |
1391 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1392 | ||
3a6a4eda | 1393 | #ifdef CONFIG_IXGBE_PTP |
1d1a79b5 | 1394 | ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); |
3a6a4eda JK |
1395 | #endif |
1396 | ||
43e95f11 JF |
1397 | if ((dev->features & NETIF_F_HW_VLAN_RX) && |
1398 | ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
8a0da21b AD |
1399 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); |
1400 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1401 | } |
1402 | ||
8a0da21b | 1403 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1404 | |
43e95f11 | 1405 | skb->protocol = eth_type_trans(skb, dev); |
f8212f97 AD |
1406 | } |
1407 | ||
8a0da21b AD |
1408 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1409 | struct sk_buff *skb) | |
aa80175a | 1410 | { |
8a0da21b AD |
1411 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1412 | ||
1413 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1414 | napi_gro_receive(&q_vector->napi, skb); | |
1415 | else | |
1416 | netif_rx(skb); | |
aa80175a | 1417 | } |
43634e82 | 1418 | |
f800326d AD |
1419 | /** |
1420 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1421 | * @rx_ring: Rx ring being processed | |
1422 | * @rx_desc: Rx descriptor for current buffer | |
1423 | * @skb: Current socket buffer containing buffer in progress | |
1424 | * | |
1425 | * This function updates next to clean. If the buffer is an EOP buffer | |
1426 | * this function exits returning false, otherwise it will place the | |
1427 | * sk_buff in the next buffer to be chained and return true indicating | |
1428 | * that this is in fact a non-EOP buffer. | |
1429 | **/ | |
1430 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1431 | union ixgbe_adv_rx_desc *rx_desc, | |
1432 | struct sk_buff *skb) | |
1433 | { | |
1434 | u32 ntc = rx_ring->next_to_clean + 1; | |
1435 | ||
1436 | /* fetch, update, and store next to clean */ | |
1437 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1438 | rx_ring->next_to_clean = ntc; | |
1439 | ||
1440 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1441 | ||
1442 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1443 | return false; | |
1444 | ||
1445 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1446 | if (IXGBE_CB(skb)->append_cnt) { | |
1447 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1448 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1449 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1450 | } | |
1451 | ||
1452 | /* place skb in next buffer to be received */ | |
1453 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1454 | rx_ring->rx_stats.non_eop_descs++; | |
1455 | ||
1456 | return true; | |
1457 | } | |
1458 | ||
1459 | /** | |
1460 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1461 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1462 | * @rx_desc: pointer to the EOP Rx descriptor | |
1463 | * @skb: pointer to current skb being fixed | |
1464 | * | |
1465 | * Check for corrupted packet headers caused by senders on the local L2 | |
1466 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1467 | * should be very rare. | |
1468 | * | |
1469 | * Also address the case where we are pulling data in on pages only | |
1470 | * and as such no data is present in the skb header. | |
1471 | * | |
1472 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1473 | * it is large enough to qualify as a valid Ethernet frame. | |
1474 | * | |
1475 | * Returns true if an error was encountered and skb was freed. | |
1476 | **/ | |
1477 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1478 | union ixgbe_adv_rx_desc *rx_desc, | |
1479 | struct sk_buff *skb) | |
1480 | { | |
1481 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1482 | struct net_device *netdev = rx_ring->netdev; | |
1483 | unsigned char *va; | |
1484 | unsigned int pull_len; | |
1485 | ||
1486 | /* if the page was released unmap it, else just sync our portion */ | |
1487 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1488 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1489 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1490 | IXGBE_CB(skb)->page_released = false; | |
1491 | } else { | |
1492 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1493 | IXGBE_CB(skb)->dma, | |
1494 | frag->page_offset, | |
1495 | ixgbe_rx_bufsz(rx_ring), | |
1496 | DMA_FROM_DEVICE); | |
1497 | } | |
1498 | IXGBE_CB(skb)->dma = 0; | |
1499 | ||
1500 | /* verify that the packet does not have any known errors */ | |
1501 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1502 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1503 | !(netdev->features & NETIF_F_RXALL))) { | |
1504 | dev_kfree_skb_any(skb); | |
1505 | return true; | |
1506 | } | |
1507 | ||
1508 | /* | |
1509 | * it is valid to use page_address instead of kmap since we are | |
1510 | * working with pages allocated out of the lomem pool per | |
1511 | * alloc_page(GFP_ATOMIC) | |
1512 | */ | |
1513 | va = skb_frag_address(frag); | |
1514 | ||
1515 | /* | |
1516 | * we need the header to contain the greater of either ETH_HLEN or | |
1517 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1518 | */ | |
1519 | pull_len = skb_frag_size(frag); | |
1520 | if (pull_len > 256) | |
1521 | pull_len = ixgbe_get_headlen(va, pull_len); | |
1522 | ||
1523 | /* align pull length to size of long to optimize memcpy performance */ | |
1524 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1525 | ||
1526 | /* update all of the pointers */ | |
1527 | skb_frag_size_sub(frag, pull_len); | |
1528 | frag->page_offset += pull_len; | |
1529 | skb->data_len -= pull_len; | |
1530 | skb->tail += pull_len; | |
1531 | ||
1532 | /* | |
1533 | * if we sucked the frag empty then we should free it, | |
1534 | * if there are other frags here something is screwed up in hardware | |
1535 | */ | |
1536 | if (skb_frag_size(frag) == 0) { | |
1537 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1538 | skb_shinfo(skb)->nr_frags = 0; | |
1539 | __skb_frag_unref(frag); | |
1540 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1541 | } | |
1542 | ||
57efd44c AD |
1543 | #ifdef IXGBE_FCOE |
1544 | /* do not attempt to pad FCoE Frames as this will disrupt DDP */ | |
1545 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) | |
1546 | return false; | |
1547 | ||
1548 | #endif | |
f800326d AD |
1549 | /* if skb_pad returns an error the skb was freed */ |
1550 | if (unlikely(skb->len < 60)) { | |
1551 | int pad_len = 60 - skb->len; | |
1552 | ||
1553 | if (skb_pad(skb, pad_len)) | |
1554 | return true; | |
1555 | __skb_put(skb, pad_len); | |
1556 | } | |
1557 | ||
1558 | return false; | |
1559 | } | |
1560 | ||
1561 | /** | |
1562 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1563 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1564 | * | |
1565 | * Returns true if page can be reused in another Rx buffer | |
1566 | **/ | |
1567 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1568 | { | |
1569 | struct page *page = rx_buffer->page; | |
1570 | ||
1571 | /* if we are only owner of page and it is local we can reuse it */ | |
1572 | return likely(page_count(page) == 1) && | |
1573 | likely(page_to_nid(page) == numa_node_id()); | |
1574 | } | |
1575 | ||
1576 | /** | |
1577 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1578 | * @rx_ring: rx descriptor ring to store buffers on | |
1579 | * @old_buff: donor buffer to have page reused | |
1580 | * | |
1581 | * Syncronizes page for reuse by the adapter | |
1582 | **/ | |
1583 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1584 | struct ixgbe_rx_buffer *old_buff) | |
1585 | { | |
1586 | struct ixgbe_rx_buffer *new_buff; | |
1587 | u16 nta = rx_ring->next_to_alloc; | |
1588 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1589 | ||
1590 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1591 | ||
1592 | /* update, and store next to alloc */ | |
1593 | nta++; | |
1594 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1595 | ||
1596 | /* transfer page from old buffer to new buffer */ | |
1597 | new_buff->page = old_buff->page; | |
1598 | new_buff->dma = old_buff->dma; | |
1599 | ||
1600 | /* flip page offset to other buffer and store to new_buff */ | |
1601 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1602 | ||
1603 | /* sync the buffer for use by the device */ | |
1604 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1605 | new_buff->page_offset, bufsz, | |
1606 | DMA_FROM_DEVICE); | |
1607 | ||
1608 | /* bump ref count on page before it is given to the stack */ | |
1609 | get_page(new_buff->page); | |
1610 | } | |
1611 | ||
1612 | /** | |
1613 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1614 | * @rx_ring: rx descriptor ring to transact packets on | |
1615 | * @rx_buffer: buffer containing page to add | |
1616 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1617 | * @skb: sk_buff to place the data into | |
1618 | * | |
1619 | * This function is based on skb_add_rx_frag. I would have used that | |
1620 | * function however it doesn't handle the truesize case correctly since we | |
1621 | * are allocating more memory than might be used for a single receive. | |
1622 | **/ | |
1623 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1624 | struct ixgbe_rx_buffer *rx_buffer, | |
1625 | struct sk_buff *skb, int size) | |
1626 | { | |
1627 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1628 | rx_buffer->page, rx_buffer->page_offset, | |
1629 | size); | |
1630 | skb->len += size; | |
1631 | skb->data_len += size; | |
1632 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1633 | } | |
1634 | ||
1635 | /** | |
1636 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1637 | * @q_vector: structure containing interrupt and ring information | |
1638 | * @rx_ring: rx descriptor ring to transact packets on | |
1639 | * @budget: Total limit on number of packets to process | |
1640 | * | |
1641 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1642 | * processing. The advantage to this is that on systems that have | |
1643 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1644 | * it by maintaining the mapping of the page to the syste. | |
1645 | * | |
1646 | * Returns true if all work is completed without reaching budget | |
1647 | **/ | |
4ff7fb12 | 1648 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1649 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1650 | int budget) |
9a799d71 | 1651 | { |
d2f4fbe2 | 1652 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1653 | #ifdef IXGBE_FCOE |
f800326d | 1654 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1655 | int ddp_bytes = 0; |
1656 | #endif /* IXGBE_FCOE */ | |
f800326d | 1657 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1658 | |
f800326d AD |
1659 | do { |
1660 | struct ixgbe_rx_buffer *rx_buffer; | |
1661 | union ixgbe_adv_rx_desc *rx_desc; | |
1662 | struct sk_buff *skb; | |
1663 | struct page *page; | |
1664 | u16 ntc; | |
1665 | ||
1666 | /* return some buffers to hardware, one at a time is too slow */ | |
1667 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1668 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1669 | cleaned_count = 0; | |
1670 | } | |
1671 | ||
1672 | ntc = rx_ring->next_to_clean; | |
1673 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1674 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1675 | ||
1676 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1677 | break; | |
9a799d71 | 1678 | |
f800326d AD |
1679 | /* |
1680 | * This memory barrier is needed to keep us from reading | |
1681 | * any other fields out of the rx_desc until we know the | |
1682 | * RXD_STAT_DD bit is set | |
1683 | */ | |
1684 | rmb(); | |
9a799d71 | 1685 | |
f800326d AD |
1686 | page = rx_buffer->page; |
1687 | prefetchw(page); | |
9a799d71 | 1688 | |
f800326d | 1689 | skb = rx_buffer->skb; |
c267fc16 | 1690 | |
f800326d AD |
1691 | if (likely(!skb)) { |
1692 | void *page_addr = page_address(page) + | |
1693 | rx_buffer->page_offset; | |
9a799d71 | 1694 | |
f800326d AD |
1695 | /* prefetch first cache line of first page */ |
1696 | prefetch(page_addr); | |
1697 | #if L1_CACHE_BYTES < 128 | |
1698 | prefetch(page_addr + L1_CACHE_BYTES); | |
1699 | #endif | |
1700 | ||
1701 | /* allocate a skb to store the frags */ | |
1702 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1703 | IXGBE_RX_HDR_SIZE); | |
1704 | if (unlikely(!skb)) { | |
1705 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1706 | break; | |
c267fc16 AD |
1707 | } |
1708 | ||
f800326d AD |
1709 | /* |
1710 | * we will be copying header into skb->data in | |
1711 | * pskb_may_pull so it is in our interest to prefetch | |
1712 | * it now to avoid a possible cache miss | |
1713 | */ | |
1714 | prefetchw(skb->data); | |
4c1975d7 AD |
1715 | |
1716 | /* | |
1717 | * Delay unmapping of the first packet. It carries the | |
1718 | * header information, HW may still access the header | |
f800326d AD |
1719 | * after the writeback. Only unmap it when EOP is |
1720 | * reached | |
4c1975d7 | 1721 | */ |
f800326d | 1722 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1723 | } else { |
f800326d AD |
1724 | /* we are reusing so sync this buffer for CPU use */ |
1725 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1726 | rx_buffer->dma, | |
1727 | rx_buffer->page_offset, | |
1728 | ixgbe_rx_bufsz(rx_ring), | |
1729 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1730 | } |
1731 | ||
f800326d AD |
1732 | /* pull page into skb */ |
1733 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1734 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1735 | |
f800326d AD |
1736 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1737 | /* hand second half of page back to the ring */ | |
1738 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1739 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1740 | /* the page has been released from the ring */ | |
1741 | IXGBE_CB(skb)->page_released = true; | |
1742 | } else { | |
1743 | /* we are not reusing the buffer so unmap it */ | |
1744 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1745 | ixgbe_rx_pg_size(rx_ring), | |
1746 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1747 | } |
1748 | ||
f800326d AD |
1749 | /* clear contents of buffer_info */ |
1750 | rx_buffer->skb = NULL; | |
1751 | rx_buffer->dma = 0; | |
1752 | rx_buffer->page = NULL; | |
4c1975d7 | 1753 | |
f800326d | 1754 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1755 | |
9a799d71 | 1756 | cleaned_count++; |
f8212f97 | 1757 | |
f800326d AD |
1758 | /* place incomplete frames back on ring for completion */ |
1759 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1760 | continue; | |
c267fc16 | 1761 | |
f800326d AD |
1762 | /* verify the packet layout is correct */ |
1763 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1764 | continue; | |
9a799d71 | 1765 | |
d2f4fbe2 AV |
1766 | /* probably a little skewed due to removing CRC */ |
1767 | total_rx_bytes += skb->len; | |
1768 | total_rx_packets++; | |
1769 | ||
8a0da21b AD |
1770 | /* populate checksum, timestamp, VLAN, and protocol */ |
1771 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1772 | ||
332d4a7d YZ |
1773 | #ifdef IXGBE_FCOE |
1774 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
57efd44c | 1775 | if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) { |
f56e0cb1 | 1776 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1777 | if (!ddp_bytes) { |
1778 | dev_kfree_skb_any(skb); | |
f800326d | 1779 | continue; |
63d635b2 | 1780 | } |
3d8fd385 | 1781 | } |
f800326d | 1782 | |
332d4a7d | 1783 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1784 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1785 | |
f800326d | 1786 | /* update budget accounting */ |
4ff7fb12 | 1787 | budget--; |
f800326d | 1788 | } while (likely(budget)); |
9a799d71 | 1789 | |
3d8fd385 YZ |
1790 | #ifdef IXGBE_FCOE |
1791 | /* include DDPed FCoE data */ | |
1792 | if (ddp_bytes > 0) { | |
1793 | unsigned int mss; | |
1794 | ||
fc77dc3c | 1795 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1796 | sizeof(struct fc_frame_header) - |
1797 | sizeof(struct fcoe_crc_eof); | |
1798 | if (mss > 512) | |
1799 | mss &= ~511; | |
1800 | total_rx_bytes += ddp_bytes; | |
1801 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1802 | } | |
3d8fd385 | 1803 | |
f800326d | 1804 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1805 | u64_stats_update_begin(&rx_ring->syncp); |
1806 | rx_ring->stats.packets += total_rx_packets; | |
1807 | rx_ring->stats.bytes += total_rx_bytes; | |
1808 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1809 | q_vector->rx.total_packets += total_rx_packets; |
1810 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1811 | |
f800326d AD |
1812 | if (cleaned_count) |
1813 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1814 | ||
4ff7fb12 | 1815 | return !!budget; |
9a799d71 AK |
1816 | } |
1817 | ||
9a799d71 AK |
1818 | /** |
1819 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1820 | * @adapter: board private structure | |
1821 | * | |
1822 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1823 | * interrupts. | |
1824 | **/ | |
1825 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1826 | { | |
021230d4 | 1827 | struct ixgbe_q_vector *q_vector; |
49c7ffbe | 1828 | int v_idx; |
021230d4 | 1829 | u32 mask; |
9a799d71 | 1830 | |
8e34d1aa AD |
1831 | /* Populate MSIX to EITR Select */ |
1832 | if (adapter->num_vfs > 32) { | |
1833 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1834 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1835 | } | |
1836 | ||
4df10466 JB |
1837 | /* |
1838 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1839 | * corresponding register. |
1840 | */ | |
49c7ffbe | 1841 | for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { |
efe3d3c8 | 1842 | struct ixgbe_ring *ring; |
7a921c93 | 1843 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1844 | |
a557928e | 1845 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1846 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1847 | ||
a557928e | 1848 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1849 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1850 | ||
d5bf4f67 ET |
1851 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1852 | /* tx only vector */ | |
1853 | if (adapter->tx_itr_setting == 1) | |
1854 | q_vector->itr = IXGBE_10K_ITR; | |
1855 | else | |
1856 | q_vector->itr = adapter->tx_itr_setting; | |
1857 | } else { | |
1858 | /* rx or rx/tx vector */ | |
1859 | if (adapter->rx_itr_setting == 1) | |
1860 | q_vector->itr = IXGBE_20K_ITR; | |
1861 | else | |
1862 | q_vector->itr = adapter->rx_itr_setting; | |
1863 | } | |
021230d4 | 1864 | |
fe49f04a | 1865 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1866 | } |
1867 | ||
bd508178 AD |
1868 | switch (adapter->hw.mac.type) { |
1869 | case ixgbe_mac_82598EB: | |
e8e26350 | 1870 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1871 | v_idx); |
bd508178 AD |
1872 | break; |
1873 | case ixgbe_mac_82599EB: | |
b93a2226 | 1874 | case ixgbe_mac_X540: |
e8e26350 | 1875 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1876 | break; |
bd508178 AD |
1877 | default: |
1878 | break; | |
1879 | } | |
021230d4 AV |
1880 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1881 | ||
41fb9248 | 1882 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1883 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1884 | mask &= ~(IXGBE_EIMS_OTHER | |
1885 | IXGBE_EIMS_MAILBOX | | |
1886 | IXGBE_EIMS_LSC); | |
1887 | ||
021230d4 | 1888 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1889 | } |
1890 | ||
f494e8fa AV |
1891 | enum latency_range { |
1892 | lowest_latency = 0, | |
1893 | low_latency = 1, | |
1894 | bulk_latency = 2, | |
1895 | latency_invalid = 255 | |
1896 | }; | |
1897 | ||
1898 | /** | |
1899 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1900 | * @q_vector: structure containing interrupt and ring information |
1901 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1902 | * |
1903 | * Stores a new ITR value based on packets and byte | |
1904 | * counts during the last interrupt. The advantage of per interrupt | |
1905 | * computation is faster updates and more accurate ITR for the current | |
1906 | * traffic pattern. Constants in this function were computed | |
1907 | * based on theoretical maximum wire speed and thresholds were set based | |
1908 | * on testing data as well as attempting to minimize response time | |
1909 | * while increasing bulk throughput. | |
1910 | * this functionality is controlled by the InterruptThrottleRate module | |
1911 | * parameter (see ixgbe_param.c) | |
1912 | **/ | |
bd198058 AD |
1913 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1914 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1915 | { |
bd198058 AD |
1916 | int bytes = ring_container->total_bytes; |
1917 | int packets = ring_container->total_packets; | |
1918 | u32 timepassed_us; | |
621bd70e | 1919 | u64 bytes_perint; |
bd198058 | 1920 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1921 | |
1922 | if (packets == 0) | |
bd198058 | 1923 | return; |
f494e8fa AV |
1924 | |
1925 | /* simple throttlerate management | |
621bd70e AD |
1926 | * 0-10MB/s lowest (100000 ints/s) |
1927 | * 10-20MB/s low (20000 ints/s) | |
1928 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1929 | */ |
1930 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1931 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1932 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1933 | ||
1934 | switch (itr_setting) { | |
1935 | case lowest_latency: | |
621bd70e | 1936 | if (bytes_perint > 10) |
bd198058 | 1937 | itr_setting = low_latency; |
f494e8fa AV |
1938 | break; |
1939 | case low_latency: | |
621bd70e | 1940 | if (bytes_perint > 20) |
bd198058 | 1941 | itr_setting = bulk_latency; |
621bd70e | 1942 | else if (bytes_perint <= 10) |
bd198058 | 1943 | itr_setting = lowest_latency; |
f494e8fa AV |
1944 | break; |
1945 | case bulk_latency: | |
621bd70e | 1946 | if (bytes_perint <= 20) |
bd198058 | 1947 | itr_setting = low_latency; |
f494e8fa AV |
1948 | break; |
1949 | } | |
1950 | ||
bd198058 AD |
1951 | /* clear work counters since we have the values we need */ |
1952 | ring_container->total_bytes = 0; | |
1953 | ring_container->total_packets = 0; | |
1954 | ||
1955 | /* write updated itr to ring container */ | |
1956 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1957 | } |
1958 | ||
509ee935 JB |
1959 | /** |
1960 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1961 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1962 | * |
1963 | * This function is made to be called by ethtool and by the driver | |
1964 | * when it needs to update EITR registers at runtime. Hardware | |
1965 | * specific quirks/differences are taken care of here. | |
1966 | */ | |
fe49f04a | 1967 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1968 | { |
fe49f04a | 1969 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1970 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1971 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1972 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1973 | |
bd508178 AD |
1974 | switch (adapter->hw.mac.type) { |
1975 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1976 | /* must write high and low 16 bits to reset counter */ |
1977 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1978 | break; |
1979 | case ixgbe_mac_82599EB: | |
b93a2226 | 1980 | case ixgbe_mac_X540: |
509ee935 JB |
1981 | /* |
1982 | * set the WDIS bit to not clear the timer bits and cause an | |
1983 | * immediate assertion of the interrupt | |
1984 | */ | |
1985 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1986 | break; |
1987 | default: | |
1988 | break; | |
509ee935 JB |
1989 | } |
1990 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1991 | } | |
1992 | ||
bd198058 | 1993 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1994 | { |
d5bf4f67 | 1995 | u32 new_itr = q_vector->itr; |
bd198058 | 1996 | u8 current_itr; |
f494e8fa | 1997 | |
bd198058 AD |
1998 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1999 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 2000 | |
08c8833b | 2001 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
2002 | |
2003 | switch (current_itr) { | |
2004 | /* counts and packets in update_itr are dependent on these numbers */ | |
2005 | case lowest_latency: | |
d5bf4f67 | 2006 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
2007 | break; |
2008 | case low_latency: | |
d5bf4f67 | 2009 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
2010 | break; |
2011 | case bulk_latency: | |
d5bf4f67 | 2012 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 2013 | break; |
bd198058 AD |
2014 | default: |
2015 | break; | |
f494e8fa AV |
2016 | } |
2017 | ||
d5bf4f67 | 2018 | if (new_itr != q_vector->itr) { |
fe49f04a | 2019 | /* do an exponential smoothing */ |
d5bf4f67 ET |
2020 | new_itr = (10 * new_itr * q_vector->itr) / |
2021 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 2022 | |
bd198058 | 2023 | /* save the algorithm value here */ |
5d967eb7 | 2024 | q_vector->itr = new_itr; |
fe49f04a AD |
2025 | |
2026 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 2027 | } |
f494e8fa AV |
2028 | } |
2029 | ||
119fc60a | 2030 | /** |
de88eeeb | 2031 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 2032 | * @adapter: pointer to adapter |
119fc60a | 2033 | **/ |
f0f9778d | 2034 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 2035 | { |
119fc60a MC |
2036 | struct ixgbe_hw *hw = &adapter->hw; |
2037 | u32 eicr = adapter->interrupt_event; | |
2038 | ||
f0f9778d | 2039 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
2040 | return; |
2041 | ||
f0f9778d AD |
2042 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
2043 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
2044 | return; | |
2045 | ||
2046 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2047 | ||
7ca647bd | 2048 | switch (hw->device_id) { |
f0f9778d AD |
2049 | case IXGBE_DEV_ID_82599_T3_LOM: |
2050 | /* | |
2051 | * Since the warning interrupt is for both ports | |
2052 | * we don't have to check if: | |
2053 | * - This interrupt wasn't for our port. | |
2054 | * - We may have missed the interrupt so always have to | |
2055 | * check if we got a LSC | |
2056 | */ | |
2057 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
2058 | !(eicr & IXGBE_EICR_LSC)) | |
2059 | return; | |
2060 | ||
2061 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2062 | u32 autoneg; | |
2063 | bool link_up = false; | |
7ca647bd | 2064 | |
7ca647bd JP |
2065 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2066 | ||
f0f9778d AD |
2067 | if (link_up) |
2068 | return; | |
2069 | } | |
2070 | ||
2071 | /* Check if this is not due to overtemp */ | |
2072 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2073 | return; | |
2074 | ||
2075 | break; | |
7ca647bd JP |
2076 | default: |
2077 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2078 | return; |
7ca647bd | 2079 | break; |
119fc60a | 2080 | } |
7ca647bd JP |
2081 | e_crit(drv, |
2082 | "Network adapter has been stopped because it has over heated. " | |
2083 | "Restart the computer. If the problem persists, " | |
2084 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2085 | |
2086 | adapter->interrupt_event = 0; | |
119fc60a MC |
2087 | } |
2088 | ||
0befdb3e JB |
2089 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2090 | { | |
2091 | struct ixgbe_hw *hw = &adapter->hw; | |
2092 | ||
2093 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2094 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2095 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2096 | /* write to clear the interrupt */ |
2097 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2098 | } | |
2099 | } | |
cf8280ee | 2100 | |
4f51bf70 JK |
2101 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2102 | { | |
2103 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2104 | return; | |
2105 | ||
2106 | switch (adapter->hw.mac.type) { | |
2107 | case ixgbe_mac_82599EB: | |
2108 | /* | |
2109 | * Need to check link state so complete overtemp check | |
2110 | * on service task | |
2111 | */ | |
2112 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2113 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2114 | adapter->interrupt_event = eicr; | |
2115 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2116 | ixgbe_service_event_schedule(adapter); | |
2117 | return; | |
2118 | } | |
2119 | return; | |
2120 | case ixgbe_mac_X540: | |
2121 | if (!(eicr & IXGBE_EICR_TS)) | |
2122 | return; | |
2123 | break; | |
2124 | default: | |
2125 | return; | |
2126 | } | |
2127 | ||
2128 | e_crit(drv, | |
2129 | "Network adapter has been stopped because it has over heated. " | |
2130 | "Restart the computer. If the problem persists, " | |
2131 | "power off the system and replace the adapter\n"); | |
2132 | } | |
2133 | ||
e8e26350 PW |
2134 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2135 | { | |
2136 | struct ixgbe_hw *hw = &adapter->hw; | |
2137 | ||
73c4b7cd AD |
2138 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2139 | /* Clear the interrupt */ | |
2140 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2141 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2142 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2143 | ixgbe_service_event_schedule(adapter); | |
2144 | } | |
73c4b7cd AD |
2145 | } |
2146 | ||
e8e26350 PW |
2147 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2148 | /* Clear the interrupt */ | |
2149 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2150 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2151 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2152 | ixgbe_service_event_schedule(adapter); | |
2153 | } | |
e8e26350 PW |
2154 | } |
2155 | } | |
2156 | ||
cf8280ee JB |
2157 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2158 | { | |
2159 | struct ixgbe_hw *hw = &adapter->hw; | |
2160 | ||
2161 | adapter->lsc_int++; | |
2162 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2163 | adapter->link_check_timeout = jiffies; | |
2164 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2165 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2166 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2167 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2168 | } |
2169 | } | |
2170 | ||
fe49f04a AD |
2171 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2172 | u64 qmask) | |
2173 | { | |
2174 | u32 mask; | |
bd508178 | 2175 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2176 | |
bd508178 AD |
2177 | switch (hw->mac.type) { |
2178 | case ixgbe_mac_82598EB: | |
fe49f04a | 2179 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2180 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2181 | break; | |
2182 | case ixgbe_mac_82599EB: | |
b93a2226 | 2183 | case ixgbe_mac_X540: |
fe49f04a | 2184 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2185 | if (mask) |
2186 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2187 | mask = (qmask >> 32); |
bd508178 AD |
2188 | if (mask) |
2189 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2190 | break; | |
2191 | default: | |
2192 | break; | |
fe49f04a AD |
2193 | } |
2194 | /* skip the flush */ | |
2195 | } | |
2196 | ||
2197 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2198 | u64 qmask) |
fe49f04a AD |
2199 | { |
2200 | u32 mask; | |
bd508178 | 2201 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2202 | |
bd508178 AD |
2203 | switch (hw->mac.type) { |
2204 | case ixgbe_mac_82598EB: | |
fe49f04a | 2205 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2206 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2207 | break; | |
2208 | case ixgbe_mac_82599EB: | |
b93a2226 | 2209 | case ixgbe_mac_X540: |
fe49f04a | 2210 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2211 | if (mask) |
2212 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2213 | mask = (qmask >> 32); |
bd508178 AD |
2214 | if (mask) |
2215 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2216 | break; | |
2217 | default: | |
2218 | break; | |
fe49f04a AD |
2219 | } |
2220 | /* skip the flush */ | |
2221 | } | |
2222 | ||
021230d4 | 2223 | /** |
2c4af694 AD |
2224 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2225 | * @adapter: board private structure | |
021230d4 | 2226 | **/ |
2c4af694 AD |
2227 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2228 | bool flush) | |
9a799d71 | 2229 | { |
2c4af694 | 2230 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2231 | |
2c4af694 AD |
2232 | /* don't reenable LSC while waiting for link */ |
2233 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2234 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2235 | |
2c4af694 | 2236 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2237 | switch (adapter->hw.mac.type) { |
2238 | case ixgbe_mac_82599EB: | |
2239 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2240 | break; | |
2241 | case ixgbe_mac_X540: | |
2242 | mask |= IXGBE_EIMS_TS; | |
2243 | break; | |
2244 | default: | |
2245 | break; | |
2246 | } | |
2c4af694 AD |
2247 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2248 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2249 | switch (adapter->hw.mac.type) { | |
2250 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2251 | mask |= IXGBE_EIMS_GPI_SDP1; |
2252 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2253 | case ixgbe_mac_X540: |
2254 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2255 | mask |= IXGBE_EIMS_MAILBOX; |
2256 | break; | |
2257 | default: | |
2258 | break; | |
9a799d71 | 2259 | } |
2c4af694 AD |
2260 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2261 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2262 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2263 | |
2c4af694 AD |
2264 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2265 | if (queues) | |
2266 | ixgbe_irq_enable_queues(adapter, ~0); | |
2267 | if (flush) | |
2268 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2269 | } |
2270 | ||
2c4af694 | 2271 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2272 | { |
a65151ba | 2273 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2274 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2275 | u32 eicr; |
91281fd3 | 2276 | |
54037505 DS |
2277 | /* |
2278 | * Workaround for Silicon errata. Use clear-by-write instead | |
2279 | * of clear-by-read. Reading with EICS will return the | |
2280 | * interrupt causes without clearing, which later be done | |
2281 | * with the write to EICR. | |
2282 | */ | |
2283 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2284 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2285 | |
cf8280ee JB |
2286 | if (eicr & IXGBE_EICR_LSC) |
2287 | ixgbe_check_lsc(adapter); | |
f0848276 | 2288 | |
1cdd1ec8 GR |
2289 | if (eicr & IXGBE_EICR_MAILBOX) |
2290 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2291 | |
bd508178 AD |
2292 | switch (hw->mac.type) { |
2293 | case ixgbe_mac_82599EB: | |
b93a2226 | 2294 | case ixgbe_mac_X540: |
2c4af694 AD |
2295 | if (eicr & IXGBE_EICR_ECC) |
2296 | e_info(link, "Received unrecoverable ECC Err, please " | |
2297 | "reboot\n"); | |
c4cf55e5 PWJ |
2298 | /* Handle Flow Director Full threshold interrupt */ |
2299 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2300 | int reinit_count = 0; |
c4cf55e5 | 2301 | int i; |
c4cf55e5 | 2302 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2303 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2304 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2305 | &ring->state)) |
2306 | reinit_count++; | |
2307 | } | |
2308 | if (reinit_count) { | |
2309 | /* no more flow director interrupts until after init */ | |
2310 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2311 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2312 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2313 | } |
2314 | } | |
f0f9778d | 2315 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2316 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2317 | break; |
2318 | default: | |
2319 | break; | |
c4cf55e5 | 2320 | } |
f0848276 | 2321 | |
bd508178 | 2322 | ixgbe_check_fan_failure(adapter, eicr); |
681ae1ad JK |
2323 | #ifdef CONFIG_IXGBE_PTP |
2324 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
2325 | #endif | |
efe3d3c8 | 2326 | |
7086400d | 2327 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2328 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2329 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2330 | |
9a799d71 | 2331 | return IRQ_HANDLED; |
f0848276 | 2332 | } |
91281fd3 | 2333 | |
4ff7fb12 | 2334 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2335 | { |
021230d4 | 2336 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2337 | |
9b471446 | 2338 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2339 | |
4ff7fb12 AD |
2340 | if (q_vector->rx.ring || q_vector->tx.ring) |
2341 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2342 | |
9a799d71 | 2343 | return IRQ_HANDLED; |
91281fd3 AD |
2344 | } |
2345 | ||
eb01b975 AD |
2346 | /** |
2347 | * ixgbe_poll - NAPI Rx polling callback | |
2348 | * @napi: structure for representing this polling device | |
2349 | * @budget: how many packets driver is allowed to clean | |
2350 | * | |
2351 | * This function is used for legacy and MSI, NAPI mode | |
2352 | **/ | |
8af3c33f | 2353 | int ixgbe_poll(struct napi_struct *napi, int budget) |
eb01b975 AD |
2354 | { |
2355 | struct ixgbe_q_vector *q_vector = | |
2356 | container_of(napi, struct ixgbe_q_vector, napi); | |
2357 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
2358 | struct ixgbe_ring *ring; | |
2359 | int per_ring_budget; | |
2360 | bool clean_complete = true; | |
2361 | ||
2362 | #ifdef CONFIG_IXGBE_DCA | |
2363 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
2364 | ixgbe_update_dca(q_vector); | |
2365 | #endif | |
2366 | ||
2367 | ixgbe_for_each_ring(ring, q_vector->tx) | |
2368 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); | |
2369 | ||
2370 | /* attempt to distribute budget to each queue fairly, but don't allow | |
2371 | * the budget to go below 1 because we'll exit polling */ | |
2372 | if (q_vector->rx.count > 1) | |
2373 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
2374 | else | |
2375 | per_ring_budget = budget; | |
2376 | ||
2377 | ixgbe_for_each_ring(ring, q_vector->rx) | |
2378 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, | |
2379 | per_ring_budget); | |
2380 | ||
2381 | /* If all work not completed, return budget and keep polling */ | |
2382 | if (!clean_complete) | |
2383 | return budget; | |
2384 | ||
2385 | /* all work done, exit the polling mode */ | |
2386 | napi_complete(napi); | |
2387 | if (adapter->rx_itr_setting & 1) | |
2388 | ixgbe_set_itr(q_vector); | |
2389 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2390 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
2391 | ||
2392 | return 0; | |
2393 | } | |
2394 | ||
021230d4 AV |
2395 | /** |
2396 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2397 | * @adapter: board private structure | |
2398 | * | |
2399 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2400 | * interrupts from the kernel. | |
2401 | **/ | |
2402 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2403 | { | |
2404 | struct net_device *netdev = adapter->netdev; | |
207867f5 | 2405 | int vector, err; |
e8e9f696 | 2406 | int ri = 0, ti = 0; |
021230d4 | 2407 | |
49c7ffbe | 2408 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
d0759ebb | 2409 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2410 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2411 | |
4ff7fb12 | 2412 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2413 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2414 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2415 | ti++; | |
2416 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2417 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2418 | "%s-%s-%d", netdev->name, "rx", ri++); |
2419 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2420 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2421 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2422 | } else { |
2423 | /* skip this unused q_vector */ | |
2424 | continue; | |
32aa77a4 | 2425 | } |
207867f5 AD |
2426 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2427 | q_vector->name, q_vector); | |
9a799d71 | 2428 | if (err) { |
396e799c | 2429 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2430 | "Error: %d\n", err); |
021230d4 | 2431 | goto free_queue_irqs; |
9a799d71 | 2432 | } |
207867f5 AD |
2433 | /* If Flow Director is enabled, set interrupt affinity */ |
2434 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2435 | /* assign the mask for this irq */ | |
2436 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2437 | &q_vector->affinity_mask); |
207867f5 | 2438 | } |
9a799d71 AK |
2439 | } |
2440 | ||
021230d4 | 2441 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2442 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2443 | if (err) { |
de88eeeb | 2444 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2445 | goto free_queue_irqs; |
9a799d71 AK |
2446 | } |
2447 | ||
9a799d71 AK |
2448 | return 0; |
2449 | ||
021230d4 | 2450 | free_queue_irqs: |
207867f5 AD |
2451 | while (vector) { |
2452 | vector--; | |
2453 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2454 | NULL); | |
2455 | free_irq(adapter->msix_entries[vector].vector, | |
2456 | adapter->q_vector[vector]); | |
2457 | } | |
021230d4 AV |
2458 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2459 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2460 | kfree(adapter->msix_entries); |
2461 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2462 | return err; |
2463 | } | |
2464 | ||
2465 | /** | |
021230d4 | 2466 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2467 | * @irq: interrupt number |
2468 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2469 | **/ |
2470 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2471 | { | |
a65151ba | 2472 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2473 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2474 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2475 | u32 eicr; |
2476 | ||
54037505 | 2477 | /* |
24ddd967 | 2478 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2479 | * before the read of EICR. |
2480 | */ | |
2481 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2482 | ||
021230d4 | 2483 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2484 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2485 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2486 | if (!eicr) { |
6af3b9eb ET |
2487 | /* |
2488 | * shared interrupt alert! | |
f47cf66e | 2489 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2490 | * have disabled interrupts due to EIAM |
2491 | * finish the workaround of silicon errata on 82598. Unmask | |
2492 | * the interrupt that we masked before the EICR read. | |
2493 | */ | |
2494 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2495 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2496 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2497 | } |
9a799d71 | 2498 | |
cf8280ee JB |
2499 | if (eicr & IXGBE_EICR_LSC) |
2500 | ixgbe_check_lsc(adapter); | |
021230d4 | 2501 | |
bd508178 AD |
2502 | switch (hw->mac.type) { |
2503 | case ixgbe_mac_82599EB: | |
e8e26350 | 2504 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2505 | /* Fall through */ |
2506 | case ixgbe_mac_X540: | |
2507 | if (eicr & IXGBE_EICR_ECC) | |
2508 | e_info(link, "Received unrecoverable ECC err, please " | |
2509 | "reboot\n"); | |
4f51bf70 | 2510 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2511 | break; |
2512 | default: | |
2513 | break; | |
2514 | } | |
e8e26350 | 2515 | |
0befdb3e | 2516 | ixgbe_check_fan_failure(adapter, eicr); |
681ae1ad JK |
2517 | #ifdef CONFIG_IXGBE_PTP |
2518 | ixgbe_ptp_check_pps_event(adapter, eicr); | |
2519 | #endif | |
0befdb3e | 2520 | |
b9f6ed2b AD |
2521 | /* would disable interrupts here but EIAM disabled it */ |
2522 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2523 | |
6af3b9eb ET |
2524 | /* |
2525 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2526 | * ixgbe_poll will re-enable the queue interrupts | |
2527 | */ | |
6af3b9eb ET |
2528 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2529 | ixgbe_irq_enable(adapter, false, false); | |
2530 | ||
9a799d71 AK |
2531 | return IRQ_HANDLED; |
2532 | } | |
2533 | ||
2534 | /** | |
2535 | * ixgbe_request_irq - initialize interrupts | |
2536 | * @adapter: board private structure | |
2537 | * | |
2538 | * Attempts to configure interrupts using the best available | |
2539 | * capabilities of the hardware and kernel. | |
2540 | **/ | |
021230d4 | 2541 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2542 | { |
2543 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2544 | int err; |
9a799d71 | 2545 | |
4cc6df29 | 2546 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2547 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2548 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2549 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2550 | netdev->name, adapter); |
4cc6df29 | 2551 | else |
a0607fd3 | 2552 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2553 | netdev->name, adapter); |
9a799d71 | 2554 | |
de88eeeb | 2555 | if (err) |
396e799c | 2556 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2557 | |
9a799d71 AK |
2558 | return err; |
2559 | } | |
2560 | ||
2561 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2562 | { | |
49c7ffbe | 2563 | int vector; |
9a799d71 | 2564 | |
49c7ffbe AD |
2565 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
2566 | free_irq(adapter->pdev->irq, adapter); | |
2567 | return; | |
2568 | } | |
4cc6df29 | 2569 | |
49c7ffbe AD |
2570 | for (vector = 0; vector < adapter->num_q_vectors; vector++) { |
2571 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; | |
2572 | struct msix_entry *entry = &adapter->msix_entries[vector]; | |
894ff7cf | 2573 | |
49c7ffbe AD |
2574 | /* free only the irqs that were actually requested */ |
2575 | if (!q_vector->rx.ring && !q_vector->tx.ring) | |
2576 | continue; | |
207867f5 | 2577 | |
49c7ffbe AD |
2578 | /* clear the affinity_mask in the IRQ descriptor */ |
2579 | irq_set_affinity_hint(entry->vector, NULL); | |
2580 | ||
2581 | free_irq(entry->vector, q_vector); | |
9a799d71 | 2582 | } |
49c7ffbe AD |
2583 | |
2584 | free_irq(adapter->msix_entries[vector++].vector, adapter); | |
9a799d71 AK |
2585 | } |
2586 | ||
22d5a71b JB |
2587 | /** |
2588 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2589 | * @adapter: board private structure | |
2590 | **/ | |
2591 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2592 | { | |
bd508178 AD |
2593 | switch (adapter->hw.mac.type) { |
2594 | case ixgbe_mac_82598EB: | |
835462fc | 2595 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2596 | break; |
2597 | case ixgbe_mac_82599EB: | |
b93a2226 | 2598 | case ixgbe_mac_X540: |
835462fc NS |
2599 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2600 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2601 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2602 | break; |
2603 | default: | |
2604 | break; | |
22d5a71b JB |
2605 | } |
2606 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2607 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
49c7ffbe AD |
2608 | int vector; |
2609 | ||
2610 | for (vector = 0; vector < adapter->num_q_vectors; vector++) | |
2611 | synchronize_irq(adapter->msix_entries[vector].vector); | |
2612 | ||
2613 | synchronize_irq(adapter->msix_entries[vector++].vector); | |
22d5a71b JB |
2614 | } else { |
2615 | synchronize_irq(adapter->pdev->irq); | |
2616 | } | |
2617 | } | |
2618 | ||
9a799d71 AK |
2619 | /** |
2620 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2621 | * | |
2622 | **/ | |
2623 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2624 | { | |
d5bf4f67 | 2625 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2626 | |
d5bf4f67 ET |
2627 | /* rx/tx vector */ |
2628 | if (adapter->rx_itr_setting == 1) | |
2629 | q_vector->itr = IXGBE_20K_ITR; | |
2630 | else | |
2631 | q_vector->itr = adapter->rx_itr_setting; | |
2632 | ||
2633 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2634 | |
e8e26350 PW |
2635 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2636 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2637 | |
396e799c | 2638 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2639 | } |
2640 | ||
43e69bf0 AD |
2641 | /** |
2642 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2643 | * @adapter: board private structure | |
2644 | * @ring: structure containing ring specific data | |
2645 | * | |
2646 | * Configure the Tx descriptor ring after a reset. | |
2647 | **/ | |
84418e3b AD |
2648 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2649 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2650 | { |
2651 | struct ixgbe_hw *hw = &adapter->hw; | |
2652 | u64 tdba = ring->dma; | |
2f1860b8 | 2653 | int wait_loop = 10; |
b88c6de2 | 2654 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2655 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2656 | |
2f1860b8 | 2657 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2658 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2659 | IXGBE_WRITE_FLUSH(hw); |
2660 | ||
43e69bf0 | 2661 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2662 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2663 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2664 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2665 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2666 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2667 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2668 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2669 | |
b88c6de2 AD |
2670 | /* |
2671 | * set WTHRESH to encourage burst writeback, it should not be set | |
2672 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2673 | * | |
2674 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2675 | * to or less than the number of on chip descriptors, which is | |
2676 | * currently 40. | |
2677 | */ | |
e954b374 | 2678 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2679 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2680 | else | |
2681 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2682 | ||
e954b374 AD |
2683 | /* |
2684 | * Setting PTHRESH to 32 both improves performance | |
2685 | * and avoids a TX hang with DFP enabled | |
2686 | */ | |
b88c6de2 AD |
2687 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2688 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2689 | |
2690 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2691 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2692 | adapter->atr_sample_rate) { | |
2693 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2694 | ring->atr_count = 0; | |
2695 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2696 | } else { | |
2697 | ring->atr_sample_rate = 0; | |
2698 | } | |
2f1860b8 | 2699 | |
c84d324c JF |
2700 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2701 | ||
2f1860b8 | 2702 | /* enable queue */ |
2f1860b8 AD |
2703 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2704 | ||
2705 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2706 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2707 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2708 | return; | |
2709 | ||
2710 | /* poll to verify queue is enabled */ | |
2711 | do { | |
032b4325 | 2712 | usleep_range(1000, 2000); |
2f1860b8 AD |
2713 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2714 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2715 | if (!wait_loop) | |
2716 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2717 | } |
2718 | ||
120ff942 AD |
2719 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2720 | { | |
2721 | struct ixgbe_hw *hw = &adapter->hw; | |
2722 | u32 rttdcs; | |
72a32f1f | 2723 | u32 reg; |
8b1c0b24 | 2724 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2725 | |
2726 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2727 | return; | |
2728 | ||
2729 | /* disable the arbiter while setting MTQC */ | |
2730 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2731 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2732 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2733 | ||
2734 | /* set transmit pool layout */ | |
8b1c0b24 | 2735 | switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
120ff942 AD |
2736 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2737 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2738 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2739 | break; | |
8b1c0b24 JF |
2740 | default: |
2741 | if (!tcs) | |
2742 | reg = IXGBE_MTQC_64Q_1PB; | |
2743 | else if (tcs <= 4) | |
2744 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2745 | else | |
2746 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
120ff942 | 2747 | |
8b1c0b24 | 2748 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
120ff942 | 2749 | |
8b1c0b24 JF |
2750 | /* Enable Security TX Buffer IFG for multiple pb */ |
2751 | if (tcs) { | |
2752 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2753 | reg |= IXGBE_SECTX_DCB; | |
2754 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2755 | } | |
120ff942 AD |
2756 | break; |
2757 | } | |
2758 | ||
2759 | /* re-enable the arbiter */ | |
2760 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2761 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2762 | } | |
2763 | ||
9a799d71 | 2764 | /** |
3a581073 | 2765 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2766 | * @adapter: board private structure |
2767 | * | |
2768 | * Configure the Tx unit of the MAC after a reset. | |
2769 | **/ | |
2770 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2771 | { | |
2f1860b8 AD |
2772 | struct ixgbe_hw *hw = &adapter->hw; |
2773 | u32 dmatxctl; | |
43e69bf0 | 2774 | u32 i; |
9a799d71 | 2775 | |
2f1860b8 AD |
2776 | ixgbe_setup_mtqc(adapter); |
2777 | ||
2778 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2779 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2780 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2781 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2782 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2783 | } | |
2784 | ||
9a799d71 | 2785 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2786 | for (i = 0; i < adapter->num_tx_queues; i++) |
2787 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2788 | } |
2789 | ||
3ebe8fde AD |
2790 | static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter, |
2791 | struct ixgbe_ring *ring) | |
2792 | { | |
2793 | struct ixgbe_hw *hw = &adapter->hw; | |
2794 | u8 reg_idx = ring->reg_idx; | |
2795 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2796 | ||
2797 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
2798 | ||
2799 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2800 | } | |
2801 | ||
2802 | static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter, | |
2803 | struct ixgbe_ring *ring) | |
2804 | { | |
2805 | struct ixgbe_hw *hw = &adapter->hw; | |
2806 | u8 reg_idx = ring->reg_idx; | |
2807 | u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx)); | |
2808 | ||
2809 | srrctl &= ~IXGBE_SRRCTL_DROP_EN; | |
2810 | ||
2811 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); | |
2812 | } | |
2813 | ||
2814 | #ifdef CONFIG_IXGBE_DCB | |
2815 | void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2816 | #else | |
2817 | static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter) | |
2818 | #endif | |
2819 | { | |
2820 | int i; | |
2821 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; | |
2822 | ||
2823 | if (adapter->ixgbe_ieee_pfc) | |
2824 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
2825 | ||
2826 | /* | |
2827 | * We should set the drop enable bit if: | |
2828 | * SR-IOV is enabled | |
2829 | * or | |
2830 | * Number of Rx queues > 1 and flow control is disabled | |
2831 | * | |
2832 | * This allows us to avoid head of line blocking for security | |
2833 | * and performance reasons. | |
2834 | */ | |
2835 | if (adapter->num_vfs || (adapter->num_rx_queues > 1 && | |
2836 | !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) { | |
2837 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2838 | ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]); | |
2839 | } else { | |
2840 | for (i = 0; i < adapter->num_rx_queues; i++) | |
2841 | ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]); | |
2842 | } | |
2843 | } | |
2844 | ||
e8e26350 | 2845 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2846 | |
a6616b42 | 2847 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2848 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2849 | { |
45e9baa5 | 2850 | struct ixgbe_hw *hw = &adapter->hw; |
cc41ac7c | 2851 | u32 srrctl; |
bf29ee6c | 2852 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2853 | |
45e9baa5 AD |
2854 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2855 | u16 mask = adapter->ring_feature[RING_F_RSS].mask; | |
cc41ac7c | 2856 | |
45e9baa5 AD |
2857 | /* |
2858 | * if VMDq is not active we must program one srrctl register | |
2859 | * per RSS queue since we have enabled RDRXCTL.MVMEN | |
2860 | */ | |
2861 | reg_idx &= mask; | |
2862 | } | |
cc41ac7c | 2863 | |
45e9baa5 AD |
2864 | /* configure header buffer length, needed for RSC */ |
2865 | srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT; | |
afafd5b0 | 2866 | |
45e9baa5 | 2867 | /* configure the packet buffer length */ |
f800326d AD |
2868 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2869 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2870 | #else |
f800326d | 2871 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2872 | #endif |
45e9baa5 AD |
2873 | |
2874 | /* configure descriptor type */ | |
f800326d | 2875 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2876 | |
45e9baa5 | 2877 | IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2878 | } |
9a799d71 | 2879 | |
05abb126 | 2880 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2881 | { |
05abb126 AD |
2882 | struct ixgbe_hw *hw = &adapter->hw; |
2883 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2884 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2885 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2886 | u32 mrqc = 0, reta = 0; |
2887 | u32 rxcsum; | |
2888 | int i, j; | |
8b1c0b24 | 2889 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
86b4db3b JF |
2890 | int maxq = adapter->ring_feature[RING_F_RSS].indices; |
2891 | ||
2892 | if (tcs) | |
2893 | maxq = min(maxq, adapter->num_tx_queues / tcs); | |
0cefafad | 2894 | |
05abb126 AD |
2895 | /* Fill out hash function seeds */ |
2896 | for (i = 0; i < 10; i++) | |
2897 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2898 | ||
2899 | /* Fill out redirection table */ | |
2900 | for (i = 0, j = 0; i < 128; i++, j++) { | |
86b4db3b | 2901 | if (j == maxq) |
05abb126 AD |
2902 | j = 0; |
2903 | /* reta = 4-byte sliding window of | |
2904 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2905 | reta = (reta << 8) | (j * 0x11); | |
2906 | if ((i & 3) == 3) | |
2907 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2908 | } | |
0cefafad | 2909 | |
05abb126 AD |
2910 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2911 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2912 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2913 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2914 | ||
8b1c0b24 JF |
2915 | if (adapter->hw.mac.type == ixgbe_mac_82598EB && |
2916 | (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { | |
0cefafad | 2917 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 JF |
2918 | } else { |
2919 | int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2920 | | IXGBE_FLAG_SRIOV_ENABLED); | |
2921 | ||
2922 | switch (mask) { | |
2923 | case (IXGBE_FLAG_RSS_ENABLED): | |
2924 | if (!tcs) | |
2925 | mrqc = IXGBE_MRQC_RSSEN; | |
2926 | else if (tcs <= 4) | |
2927 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2928 | else | |
2929 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2930 | break; | |
2931 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2932 | mrqc = IXGBE_MRQC_VMDQEN; | |
2933 | break; | |
2934 | default: | |
2935 | break; | |
2936 | } | |
0cefafad JB |
2937 | } |
2938 | ||
05abb126 AD |
2939 | /* Perform hash on these packet types */ |
2940 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2941 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2942 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2943 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2944 | ||
ef6afc0c AD |
2945 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP) |
2946 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP; | |
2947 | if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP) | |
2948 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP; | |
2949 | ||
05abb126 | 2950 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); |
0cefafad JB |
2951 | } |
2952 | ||
bb5a9ad2 NS |
2953 | /** |
2954 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2955 | * @adapter: address of board private structure | |
2956 | * @index: index of ring to set | |
bb5a9ad2 | 2957 | **/ |
082757af | 2958 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2959 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2960 | { |
bb5a9ad2 | 2961 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2962 | u32 rscctrl; |
bf29ee6c | 2963 | u8 reg_idx = ring->reg_idx; |
7367096a | 2964 | |
7d637bcc | 2965 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2966 | return; |
bb5a9ad2 | 2967 | |
7367096a | 2968 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2969 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2970 | /* | |
2971 | * we must limit the number of descriptors so that the | |
2972 | * total size of max desc * buf_len is not greater | |
642c680e | 2973 | * than 65536 |
bb5a9ad2 | 2974 | */ |
f800326d AD |
2975 | #if (PAGE_SIZE <= 8192) |
2976 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2977 | #elif (PAGE_SIZE <= 16384) | |
2978 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2979 | #else |
f800326d | 2980 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2981 | #endif |
7367096a | 2982 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2983 | } |
2984 | ||
9e10e045 AD |
2985 | #define IXGBE_MAX_RX_DESC_POLL 10 |
2986 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2987 | struct ixgbe_ring *ring) | |
2988 | { | |
2989 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2990 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2991 | u32 rxdctl; | |
bf29ee6c | 2992 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
2993 | |
2994 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2995 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2996 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2997 | return; | |
2998 | ||
2999 | do { | |
032b4325 | 3000 | usleep_range(1000, 2000); |
9e10e045 AD |
3001 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
3002 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3003 | ||
3004 | if (!wait_loop) { | |
3005 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
3006 | "the polling period\n", reg_idx); | |
3007 | } | |
3008 | } | |
3009 | ||
2d39d576 YZ |
3010 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
3011 | struct ixgbe_ring *ring) | |
3012 | { | |
3013 | struct ixgbe_hw *hw = &adapter->hw; | |
3014 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
3015 | u32 rxdctl; | |
3016 | u8 reg_idx = ring->reg_idx; | |
3017 | ||
3018 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3019 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
3020 | ||
3021 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
3022 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3023 | ||
3024 | if (hw->mac.type == ixgbe_mac_82598EB && | |
3025 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
3026 | return; | |
3027 | ||
3028 | /* the hardware may take up to 100us to really disable the rx queue */ | |
3029 | do { | |
3030 | udelay(10); | |
3031 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
3032 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
3033 | ||
3034 | if (!wait_loop) { | |
3035 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
3036 | "the polling period\n", reg_idx); | |
3037 | } | |
3038 | } | |
3039 | ||
84418e3b AD |
3040 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
3041 | struct ixgbe_ring *ring) | |
acd37177 AD |
3042 | { |
3043 | struct ixgbe_hw *hw = &adapter->hw; | |
3044 | u64 rdba = ring->dma; | |
9e10e045 | 3045 | u32 rxdctl; |
bf29ee6c | 3046 | u8 reg_idx = ring->reg_idx; |
acd37177 | 3047 | |
9e10e045 AD |
3048 | /* disable queue to avoid issues while updating state */ |
3049 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 3050 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 3051 | |
acd37177 AD |
3052 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
3053 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
3054 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
3055 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
3056 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
3057 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 3058 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
3059 | |
3060 | ixgbe_configure_srrctl(adapter, ring); | |
3061 | ixgbe_configure_rscctl(adapter, ring); | |
3062 | ||
e9f98072 GR |
3063 | /* If operating in IOV mode set RLPML for X540 */ |
3064 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
3065 | hw->mac.type == ixgbe_mac_X540) { | |
3066 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
3067 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
3068 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
3069 | } | |
3070 | ||
9e10e045 AD |
3071 | if (hw->mac.type == ixgbe_mac_82598EB) { |
3072 | /* | |
3073 | * enable cache line friendly hardware writes: | |
3074 | * PTHRESH=32 descriptors (half the internal cache), | |
3075 | * this also removes ugly rx_no_buffer_count increment | |
3076 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
3077 | * WTHRESH=8 burst writeback up to two cache lines | |
3078 | */ | |
3079 | rxdctl &= ~0x3FFFFF; | |
3080 | rxdctl |= 0x080420; | |
3081 | } | |
3082 | ||
3083 | /* enable receive descriptor ring */ | |
3084 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
3085 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
3086 | ||
3087 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 3088 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
3089 | } |
3090 | ||
48654521 AD |
3091 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
3092 | { | |
3093 | struct ixgbe_hw *hw = &adapter->hw; | |
3094 | int p; | |
3095 | ||
3096 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
3097 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
3098 | IXGBE_PSRTYPE_UDPHDR | |
3099 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 3100 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 3101 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
3102 | |
3103 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3104 | return; | |
3105 | ||
3106 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
3107 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
3108 | ||
3109 | for (p = 0; p < adapter->num_rx_pools; p++) | |
3110 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
3111 | psrtype); | |
3112 | } | |
3113 | ||
f5b4a52e AD |
3114 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
3115 | { | |
3116 | struct ixgbe_hw *hw = &adapter->hw; | |
3117 | u32 gcr_ext; | |
3118 | u32 vt_reg_bits; | |
3119 | u32 reg_offset, vf_shift; | |
3120 | u32 vmdctl; | |
de4c7f65 | 3121 | int i; |
f5b4a52e AD |
3122 | |
3123 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
3124 | return; | |
3125 | ||
3126 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
3127 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
3128 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
3129 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
3130 | ||
3131 | vf_shift = adapter->num_vfs % 32; | |
4cd6923d | 3132 | reg_offset = (adapter->num_vfs >= 32) ? 1 : 0; |
f5b4a52e AD |
3133 | |
3134 | /* Enable only the PF's pool for Tx/Rx */ | |
3135 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
3136 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
3137 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
3138 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
3139 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
3140 | ||
3141 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3142 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3143 | ||
3144 | /* | |
3145 | * Set up VF register offsets for selected VT Mode, | |
3146 | * i.e. 32 or 64 VFs for SR-IOV | |
3147 | */ | |
3148 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3149 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3150 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3151 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3152 | ||
3153 | /* enable Tx loopback for VF/PF communication */ | |
3154 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 3155 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c | 3156 | hw->mac.ops.set_mac_anti_spoofing(hw, |
de4c7f65 | 3157 | (adapter->num_vfs != 0), |
a985b6c3 | 3158 | adapter->num_vfs); |
de4c7f65 GR |
3159 | /* For VFs that have spoof checking turned off */ |
3160 | for (i = 0; i < adapter->num_vfs; i++) { | |
3161 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3162 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3163 | } | |
f5b4a52e AD |
3164 | } |
3165 | ||
477de6ed | 3166 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3167 | { |
9a799d71 AK |
3168 | struct ixgbe_hw *hw = &adapter->hw; |
3169 | struct net_device *netdev = adapter->netdev; | |
3170 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3171 | struct ixgbe_ring *rx_ring; |
3172 | int i; | |
3173 | u32 mhadd, hlreg0; | |
48654521 | 3174 | |
63f39bd1 | 3175 | #ifdef IXGBE_FCOE |
477de6ed AD |
3176 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3177 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3178 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3179 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3180 | |
477de6ed AD |
3181 | #endif /* IXGBE_FCOE */ |
3182 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3183 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3184 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3185 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3186 | ||
3187 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3188 | } | |
3189 | ||
919e78a6 AD |
3190 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3191 | max_frame += VLAN_HLEN; | |
3192 | ||
477de6ed AD |
3193 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3194 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3195 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3196 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3197 | |
0cefafad JB |
3198 | /* |
3199 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3200 | * the Base and Length of the Rx Descriptor Ring | |
3201 | */ | |
9a799d71 | 3202 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3203 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3204 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3205 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3206 | else |
7d637bcc | 3207 | clear_ring_rsc_enabled(rx_ring); |
477de6ed | 3208 | } |
477de6ed AD |
3209 | } |
3210 | ||
7367096a AD |
3211 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3212 | { | |
3213 | struct ixgbe_hw *hw = &adapter->hw; | |
3214 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3215 | ||
3216 | switch (hw->mac.type) { | |
3217 | case ixgbe_mac_82598EB: | |
3218 | /* | |
3219 | * For VMDq support of different descriptor types or | |
3220 | * buffer sizes through the use of multiple SRRCTL | |
3221 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3222 | * | |
3223 | * also, the manual doesn't mention it clearly but DCA hints | |
3224 | * will only use queue 0's tags unless this bit is set. Side | |
3225 | * effects of setting this bit are only that SRRCTL must be | |
3226 | * fully programmed [0..15] | |
3227 | */ | |
3228 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3229 | break; | |
3230 | case ixgbe_mac_82599EB: | |
b93a2226 | 3231 | case ixgbe_mac_X540: |
7367096a AD |
3232 | /* Disable RSC for ACK packets */ |
3233 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3234 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3235 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3236 | /* hardware requires some bits to be set by default */ | |
3237 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3238 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3239 | break; | |
3240 | default: | |
3241 | /* We should do nothing since we don't know this hardware */ | |
3242 | return; | |
3243 | } | |
3244 | ||
3245 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3246 | } | |
3247 | ||
477de6ed AD |
3248 | /** |
3249 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3250 | * @adapter: board private structure | |
3251 | * | |
3252 | * Configure the Rx unit of the MAC after a reset. | |
3253 | **/ | |
3254 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3255 | { | |
3256 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3257 | int i; |
3258 | u32 rxctrl; | |
477de6ed AD |
3259 | |
3260 | /* disable receives while setting up the descriptors */ | |
3261 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3262 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3263 | ||
3264 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3265 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3266 | |
9e10e045 | 3267 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3268 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3269 | |
477de6ed AD |
3270 | /* set_rx_buffer_len must be called before ring initialization */ |
3271 | ixgbe_set_rx_buffer_len(adapter); | |
3272 | ||
3273 | /* | |
3274 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3275 | * the Base and Length of the Rx Descriptor Ring | |
3276 | */ | |
9e10e045 AD |
3277 | for (i = 0; i < adapter->num_rx_queues; i++) |
3278 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3279 | |
9e10e045 AD |
3280 | /* disable drop enable for 82598 parts */ |
3281 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3282 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3283 | ||
3284 | /* enable all receives */ | |
3285 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3286 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3287 | } |
3288 | ||
8e586137 | 3289 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3290 | { |
3291 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3292 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3293 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3294 | |
3295 | /* add VID to filter table */ | |
1ada1b1b | 3296 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3297 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3298 | |
3299 | return 0; | |
068c89b0 DS |
3300 | } |
3301 | ||
8e586137 | 3302 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3303 | { |
3304 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3305 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3306 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3307 | |
068c89b0 | 3308 | /* remove VID from filter table */ |
1ada1b1b | 3309 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3310 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3311 | |
3312 | return 0; | |
068c89b0 DS |
3313 | } |
3314 | ||
5f6c0181 JB |
3315 | /** |
3316 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3317 | * @adapter: driver data | |
3318 | */ | |
3319 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3320 | { | |
3321 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3322 | u32 vlnctrl; |
3323 | ||
3324 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3325 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3326 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3327 | } | |
3328 | ||
3329 | /** | |
3330 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3331 | * @adapter: driver data | |
3332 | */ | |
3333 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3334 | { | |
3335 | struct ixgbe_hw *hw = &adapter->hw; | |
3336 | u32 vlnctrl; | |
3337 | ||
3338 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3339 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3340 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3341 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3342 | } | |
3343 | ||
3344 | /** | |
3345 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3346 | * @adapter: driver data | |
3347 | */ | |
3348 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3349 | { | |
3350 | struct ixgbe_hw *hw = &adapter->hw; | |
3351 | u32 vlnctrl; | |
5f6c0181 JB |
3352 | int i, j; |
3353 | ||
3354 | switch (hw->mac.type) { | |
3355 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3356 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3357 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3358 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3359 | break; | |
3360 | case ixgbe_mac_82599EB: | |
b93a2226 | 3361 | case ixgbe_mac_X540: |
5f6c0181 JB |
3362 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3363 | j = adapter->rx_ring[i]->reg_idx; | |
3364 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3365 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3366 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3367 | } | |
3368 | break; | |
3369 | default: | |
3370 | break; | |
3371 | } | |
3372 | } | |
3373 | ||
3374 | /** | |
f62bbb5e | 3375 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3376 | * @adapter: driver data |
3377 | */ | |
f62bbb5e | 3378 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3379 | { |
3380 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3381 | u32 vlnctrl; |
5f6c0181 JB |
3382 | int i, j; |
3383 | ||
3384 | switch (hw->mac.type) { | |
3385 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3386 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3387 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3388 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3389 | break; | |
3390 | case ixgbe_mac_82599EB: | |
b93a2226 | 3391 | case ixgbe_mac_X540: |
5f6c0181 JB |
3392 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3393 | j = adapter->rx_ring[i]->reg_idx; | |
3394 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3395 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3396 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3397 | } | |
3398 | break; | |
3399 | default: | |
3400 | break; | |
3401 | } | |
3402 | } | |
3403 | ||
9a799d71 AK |
3404 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3405 | { | |
f62bbb5e | 3406 | u16 vid; |
9a799d71 | 3407 | |
f62bbb5e JG |
3408 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3409 | ||
3410 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3411 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3412 | } |
3413 | ||
2850062a AD |
3414 | /** |
3415 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3416 | * @netdev: network interface device structure | |
3417 | * | |
3418 | * Writes unicast address list to the RAR table. | |
3419 | * Returns: -ENOMEM on failure/insufficient address space | |
3420 | * 0 on no addresses written | |
3421 | * X on writing X addresses to the RAR table | |
3422 | **/ | |
3423 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3424 | { | |
3425 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3426 | struct ixgbe_hw *hw = &adapter->hw; | |
3427 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3428 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3429 | int count = 0; |
3430 | ||
3431 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3432 | if (netdev_uc_count(netdev) > rar_entries) | |
3433 | return -ENOMEM; | |
3434 | ||
3435 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3436 | struct netdev_hw_addr *ha; | |
3437 | /* return error if we do not support writing to RAR table */ | |
3438 | if (!hw->mac.ops.set_rar) | |
3439 | return -ENOMEM; | |
3440 | ||
3441 | netdev_for_each_uc_addr(ha, netdev) { | |
3442 | if (!rar_entries) | |
3443 | break; | |
3444 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3445 | vfn, IXGBE_RAH_AV); | |
3446 | count++; | |
3447 | } | |
3448 | } | |
3449 | /* write the addresses in reverse order to avoid write combining */ | |
3450 | for (; rar_entries > 0 ; rar_entries--) | |
3451 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3452 | ||
3453 | return count; | |
3454 | } | |
3455 | ||
9a799d71 | 3456 | /** |
2c5645cf | 3457 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3458 | * @netdev: network interface device structure |
3459 | * | |
2c5645cf CL |
3460 | * The set_rx_method entry point is called whenever the unicast/multicast |
3461 | * address list or the network interface flags are updated. This routine is | |
3462 | * responsible for configuring the hardware for proper unicast, multicast and | |
3463 | * promiscuous mode. | |
9a799d71 | 3464 | **/ |
7f870475 | 3465 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3466 | { |
3467 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3468 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3469 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3470 | int count; | |
9a799d71 AK |
3471 | |
3472 | /* Check for Promiscuous and All Multicast modes */ | |
3473 | ||
3474 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3475 | ||
f5dc442b | 3476 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3477 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3478 | fctrl |= IXGBE_FCTRL_BAM; |
3479 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3480 | fctrl |= IXGBE_FCTRL_PMCF; | |
3481 | ||
2850062a AD |
3482 | /* clear the bits we are changing the status of */ |
3483 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3484 | ||
9a799d71 | 3485 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3486 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3487 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3488 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3489 | /* don't hardware filter vlans in promisc mode */ |
3490 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3491 | } else { |
746b9f02 PM |
3492 | if (netdev->flags & IFF_ALLMULTI) { |
3493 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3494 | vmolr |= IXGBE_VMOLR_MPE; |
3495 | } else { | |
3496 | /* | |
3497 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3498 | * then we should just turn on promiscuous mode so |
2850062a AD |
3499 | * that we can at least receive multicast traffic |
3500 | */ | |
3501 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3502 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3503 | } |
5f6c0181 | 3504 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3505 | hw->addr_ctrl.user_set_promisc = false; |
9dcb373c JF |
3506 | } |
3507 | ||
3508 | /* | |
3509 | * Write addresses to available RAR registers, if there is not | |
3510 | * sufficient space to store all the addresses then enable | |
3511 | * unicast promiscuous mode | |
3512 | */ | |
3513 | count = ixgbe_write_uc_addr_list(netdev); | |
3514 | if (count < 0) { | |
3515 | fctrl |= IXGBE_FCTRL_UPE; | |
3516 | vmolr |= IXGBE_VMOLR_ROPE; | |
9a799d71 AK |
3517 | } |
3518 | ||
2850062a | 3519 | if (adapter->num_vfs) { |
1cdd1ec8 | 3520 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3521 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3522 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3523 | IXGBE_VMOLR_ROPE); | |
3524 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3525 | } | |
3526 | ||
3f2d1c0f BG |
3527 | /* This is useful for sniffing bad packets. */ |
3528 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3529 | /* UPE and MPE will be handled by normal PROMISC logic | |
3530 | * in e1000e_set_rx_mode */ | |
3531 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3532 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3533 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3534 | ||
3535 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3536 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3537 | } | |
3538 | ||
2850062a | 3539 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3540 | |
3541 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3542 | ixgbe_vlan_strip_enable(adapter); | |
3543 | else | |
3544 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3545 | } |
3546 | ||
021230d4 AV |
3547 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3548 | { | |
3549 | int q_idx; | |
021230d4 | 3550 | |
49c7ffbe AD |
3551 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3552 | napi_enable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3553 | } |
3554 | ||
3555 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3556 | { | |
3557 | int q_idx; | |
021230d4 | 3558 | |
49c7ffbe AD |
3559 | for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) |
3560 | napi_disable(&adapter->q_vector[q_idx]->napi); | |
021230d4 AV |
3561 | } |
3562 | ||
7a6b6f51 | 3563 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c | 3564 | /** |
2f90b865 AD |
3565 | * ixgbe_configure_dcb - Configure DCB hardware |
3566 | * @adapter: ixgbe adapter struct | |
3567 | * | |
3568 | * This is called by the driver on open to configure the DCB hardware. | |
3569 | * This is also called by the gennetlink interface when reconfiguring | |
3570 | * the DCB state. | |
3571 | */ | |
3572 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3573 | { | |
3574 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3575 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3576 | |
67ebd791 AD |
3577 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3578 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3579 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3580 | return; | |
3581 | } | |
3582 | ||
3583 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3584 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3585 | ||
2f90b865 | 3586 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3587 | |
971060b1 | 3588 | #ifdef IXGBE_FCOE |
b120818e JF |
3589 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3590 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3591 | #endif |
b120818e JF |
3592 | |
3593 | /* reconfigure the hardware */ | |
3594 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3595 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3596 | DCB_TX_CONFIG); | |
3597 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3598 | DCB_RX_CONFIG); | |
3599 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3600 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3601 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3602 | adapter->ixgbe_ieee_ets, | |
3603 | max_frame); | |
3604 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3605 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3606 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3607 | } |
8187cd48 JF |
3608 | |
3609 | /* Enable RSS Hash per TC */ | |
3610 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3611 | int i; | |
3612 | u32 reg = 0; | |
d411a936 AD |
3613 | u8 msb = 0; |
3614 | u8 rss_i = adapter->netdev->tc_to_txq[0].count - 1; | |
8187cd48 | 3615 | |
d411a936 AD |
3616 | while (rss_i) { |
3617 | msb++; | |
3618 | rss_i >>= 1; | |
3619 | } | |
8187cd48 | 3620 | |
d411a936 | 3621 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) |
8187cd48 | 3622 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); |
d411a936 | 3623 | |
8187cd48 JF |
3624 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); |
3625 | } | |
2f90b865 | 3626 | } |
9da712d2 JF |
3627 | #endif |
3628 | ||
3629 | /* Additional bittime to account for IXGBE framing */ | |
3630 | #define IXGBE_ETH_FRAMING 20 | |
3631 | ||
49ce9c2c | 3632 | /** |
9da712d2 JF |
3633 | * ixgbe_hpbthresh - calculate high water mark for flow control |
3634 | * | |
3635 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3636 | * @pb: packet buffer to calculate |
9da712d2 JF |
3637 | */ |
3638 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3639 | { | |
3640 | struct ixgbe_hw *hw = &adapter->hw; | |
3641 | struct net_device *dev = adapter->netdev; | |
3642 | int link, tc, kb, marker; | |
3643 | u32 dv_id, rx_pba; | |
3644 | ||
3645 | /* Calculate max LAN frame size */ | |
3646 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3647 | ||
3648 | #ifdef IXGBE_FCOE | |
3649 | /* FCoE traffic class uses FCOE jumbo frames */ | |
800bd607 AD |
3650 | if ((dev->features & NETIF_F_FCOE_MTU) && |
3651 | (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) && | |
3652 | (pb == ixgbe_fcoe_get_tc(adapter))) | |
3653 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9da712d2 JF |
3654 | |
3655 | #endif | |
9da712d2 JF |
3656 | /* Calculate delay value for device */ |
3657 | switch (hw->mac.type) { | |
3658 | case ixgbe_mac_X540: | |
3659 | dv_id = IXGBE_DV_X540(link, tc); | |
3660 | break; | |
3661 | default: | |
3662 | dv_id = IXGBE_DV(link, tc); | |
3663 | break; | |
3664 | } | |
3665 | ||
3666 | /* Loopback switch introduces additional latency */ | |
3667 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3668 | dv_id += IXGBE_B2BT(tc); | |
3669 | ||
3670 | /* Delay value is calculated in bit times convert to KB */ | |
3671 | kb = IXGBE_BT2KB(dv_id); | |
3672 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3673 | ||
3674 | marker = rx_pba - kb; | |
3675 | ||
3676 | /* It is possible that the packet buffer is not large enough | |
3677 | * to provide required headroom. In this case throw an error | |
3678 | * to user and a do the best we can. | |
3679 | */ | |
3680 | if (marker < 0) { | |
3681 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3682 | "headroom to support flow control." | |
3683 | "Decrease MTU or number of traffic classes\n", pb); | |
3684 | marker = tc + 1; | |
3685 | } | |
3686 | ||
3687 | return marker; | |
3688 | } | |
3689 | ||
49ce9c2c | 3690 | /** |
9da712d2 JF |
3691 | * ixgbe_lpbthresh - calculate low water mark for for flow control |
3692 | * | |
3693 | * @adapter: board private structure to calculate for | |
49ce9c2c | 3694 | * @pb: packet buffer to calculate |
9da712d2 JF |
3695 | */ |
3696 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3697 | { | |
3698 | struct ixgbe_hw *hw = &adapter->hw; | |
3699 | struct net_device *dev = adapter->netdev; | |
3700 | int tc; | |
3701 | u32 dv_id; | |
3702 | ||
3703 | /* Calculate max LAN frame size */ | |
3704 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3705 | ||
3706 | /* Calculate delay value for device */ | |
3707 | switch (hw->mac.type) { | |
3708 | case ixgbe_mac_X540: | |
3709 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3710 | break; | |
3711 | default: | |
3712 | dv_id = IXGBE_LOW_DV(tc); | |
3713 | break; | |
3714 | } | |
3715 | ||
3716 | /* Delay value is calculated in bit times convert to KB */ | |
3717 | return IXGBE_BT2KB(dv_id); | |
3718 | } | |
3719 | ||
3720 | /* | |
3721 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3722 | */ | |
3723 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3724 | { | |
3725 | struct ixgbe_hw *hw = &adapter->hw; | |
3726 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3727 | int i; | |
3728 | ||
3729 | if (!num_tc) | |
3730 | num_tc = 1; | |
3731 | ||
3732 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3733 | ||
3734 | for (i = 0; i < num_tc; i++) { | |
3735 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3736 | ||
3737 | /* Low water marks must not be larger than high water marks */ | |
3738 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3739 | hw->fc.low_water = 0; | |
3740 | } | |
3741 | } | |
3742 | ||
80605c65 JF |
3743 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3744 | { | |
80605c65 | 3745 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3746 | int hdrm; |
3747 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3748 | |
3749 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3750 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3751 | hdrm = 32 << adapter->fdir_pballoc; |
3752 | else | |
3753 | hdrm = 0; | |
80605c65 | 3754 | |
f7e1027f | 3755 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3756 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3757 | } |
3758 | ||
e4911d57 AD |
3759 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3760 | { | |
3761 | struct ixgbe_hw *hw = &adapter->hw; | |
3762 | struct hlist_node *node, *node2; | |
3763 | struct ixgbe_fdir_filter *filter; | |
3764 | ||
3765 | spin_lock(&adapter->fdir_perfect_lock); | |
3766 | ||
3767 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3768 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3769 | ||
3770 | hlist_for_each_entry_safe(filter, node, node2, | |
3771 | &adapter->fdir_filter_list, fdir_node) { | |
3772 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3773 | &filter->filter, |
3774 | filter->sw_idx, | |
3775 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3776 | IXGBE_FDIR_DROP_QUEUE : | |
3777 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3778 | } |
3779 | ||
3780 | spin_unlock(&adapter->fdir_perfect_lock); | |
3781 | } | |
3782 | ||
9a799d71 AK |
3783 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3784 | { | |
d2f5e7f3 AS |
3785 | struct ixgbe_hw *hw = &adapter->hw; |
3786 | ||
80605c65 | 3787 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3788 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3789 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3790 | #endif |
9a799d71 | 3791 | |
4c1d7b4b | 3792 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3793 | ixgbe_restore_vlan(adapter); |
3794 | ||
eacd73f7 YZ |
3795 | #ifdef IXGBE_FCOE |
3796 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3797 | ixgbe_configure_fcoe(adapter); | |
3798 | ||
3799 | #endif /* IXGBE_FCOE */ | |
d2f5e7f3 AS |
3800 | |
3801 | switch (hw->mac.type) { | |
3802 | case ixgbe_mac_82599EB: | |
3803 | case ixgbe_mac_X540: | |
3804 | hw->mac.ops.disable_rx_buff(hw); | |
3805 | break; | |
3806 | default: | |
3807 | break; | |
3808 | } | |
3809 | ||
c4cf55e5 | 3810 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3811 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3812 | adapter->fdir_pballoc); | |
e4911d57 AD |
3813 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3814 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3815 | adapter->fdir_pballoc); | |
3816 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3817 | } |
4c1d7b4b | 3818 | |
d2f5e7f3 AS |
3819 | switch (hw->mac.type) { |
3820 | case ixgbe_mac_82599EB: | |
3821 | case ixgbe_mac_X540: | |
3822 | hw->mac.ops.enable_rx_buff(hw); | |
3823 | break; | |
3824 | default: | |
3825 | break; | |
3826 | } | |
3827 | ||
933d41f1 | 3828 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3829 | |
9a799d71 AK |
3830 | ixgbe_configure_tx(adapter); |
3831 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3832 | } |
3833 | ||
e8e26350 PW |
3834 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3835 | { | |
3836 | switch (hw->phy.type) { | |
3837 | case ixgbe_phy_sfp_avago: | |
3838 | case ixgbe_phy_sfp_ftl: | |
3839 | case ixgbe_phy_sfp_intel: | |
3840 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3841 | case ixgbe_phy_sfp_passive_tyco: |
3842 | case ixgbe_phy_sfp_passive_unknown: | |
3843 | case ixgbe_phy_sfp_active_unknown: | |
3844 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3845 | return true; |
8917b447 AD |
3846 | case ixgbe_phy_nl: |
3847 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3848 | return true; | |
e8e26350 PW |
3849 | default: |
3850 | return false; | |
3851 | } | |
3852 | } | |
3853 | ||
0ecc061d | 3854 | /** |
e8e26350 PW |
3855 | * ixgbe_sfp_link_config - set up SFP+ link |
3856 | * @adapter: pointer to private adapter struct | |
3857 | **/ | |
3858 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3859 | { | |
7086400d | 3860 | /* |
52f33af8 | 3861 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3862 | * is that an SFP was inserted/removed after the reset |
3863 | * but before SFP detection was enabled. As such the best | |
3864 | * solution is to just start searching as soon as we start | |
3865 | */ | |
3866 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3867 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3868 | |
7086400d | 3869 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3870 | } |
3871 | ||
3872 | /** | |
3873 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3874 | * @hw: pointer to private hardware struct |
3875 | * | |
3876 | * Returns 0 on success, negative on failure | |
3877 | **/ | |
e8e26350 | 3878 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3879 | { |
3880 | u32 autoneg; | |
8620a103 | 3881 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3882 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3883 | ||
3884 | if (hw->mac.ops.check_link) | |
3885 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3886 | ||
3887 | if (ret) | |
3888 | goto link_cfg_out; | |
3889 | ||
0b0c2b31 ET |
3890 | autoneg = hw->phy.autoneg_advertised; |
3891 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3892 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3893 | &negotiation); | |
0ecc061d PWJ |
3894 | if (ret) |
3895 | goto link_cfg_out; | |
3896 | ||
8620a103 MC |
3897 | if (hw->mac.ops.setup_link) |
3898 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3899 | link_cfg_out: |
3900 | return ret; | |
3901 | } | |
3902 | ||
a34bcfff | 3903 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3904 | { |
9a799d71 | 3905 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3906 | u32 gpie = 0; |
9a799d71 | 3907 | |
9b471446 | 3908 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3909 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3910 | IXGBE_GPIE_OCD; | |
3911 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3912 | /* |
3913 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3914 | * this saves a register write for every interrupt | |
3915 | */ | |
3916 | switch (hw->mac.type) { | |
3917 | case ixgbe_mac_82598EB: | |
3918 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3919 | break; | |
9b471446 | 3920 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3921 | case ixgbe_mac_X540: |
3922 | default: | |
9b471446 JB |
3923 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3924 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3925 | break; | |
3926 | } | |
3927 | } else { | |
021230d4 AV |
3928 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3929 | * specifically only auto mask tx and rx interrupts */ | |
3930 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3931 | } | |
9a799d71 | 3932 | |
a34bcfff AD |
3933 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3934 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3935 | ||
3936 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3937 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3938 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3939 | } |
3940 | ||
5fdd31f9 | 3941 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3942 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3943 | switch (adapter->hw.mac.type) { | |
3944 | case ixgbe_mac_82599EB: | |
3945 | gpie |= IXGBE_SDP0_GPIEN; | |
3946 | break; | |
3947 | case ixgbe_mac_X540: | |
3948 | gpie |= IXGBE_EIMS_TS; | |
3949 | break; | |
3950 | default: | |
3951 | break; | |
3952 | } | |
3953 | } | |
5fdd31f9 | 3954 | |
a34bcfff AD |
3955 | /* Enable fan failure interrupt */ |
3956 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3957 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3958 | |
2698b208 | 3959 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3960 | gpie |= IXGBE_SDP1_GPIEN; |
3961 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3962 | } |
a34bcfff AD |
3963 | |
3964 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3965 | } | |
3966 | ||
c7ccde0f | 3967 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3968 | { |
3969 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3970 | int err; |
a34bcfff AD |
3971 | u32 ctrl_ext; |
3972 | ||
3973 | ixgbe_get_hw_control(adapter); | |
3974 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3975 | |
9a799d71 AK |
3976 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3977 | ixgbe_configure_msix(adapter); | |
3978 | else | |
3979 | ixgbe_configure_msi_and_legacy(adapter); | |
3980 | ||
c6ecf39a DS |
3981 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3982 | if (hw->mac.ops.enable_tx_laser && | |
3983 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3984 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3985 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3986 | hw->mac.ops.enable_tx_laser(hw); |
3987 | ||
9a799d71 | 3988 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3989 | ixgbe_napi_enable_all(adapter); |
3990 | ||
73c4b7cd AD |
3991 | if (ixgbe_is_sfp(hw)) { |
3992 | ixgbe_sfp_link_config(adapter); | |
3993 | } else { | |
3994 | err = ixgbe_non_sfp_link_config(hw); | |
3995 | if (err) | |
3996 | e_err(probe, "link_config FAILED %d\n", err); | |
3997 | } | |
3998 | ||
021230d4 AV |
3999 | /* clear any pending interrupts, may auto mask */ |
4000 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 4001 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 4002 | |
bf069c97 DS |
4003 | /* |
4004 | * If this adapter has a fan, check to see if we had a failure | |
4005 | * before we enabled the interrupt. | |
4006 | */ | |
4007 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
4008 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
4009 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 4010 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
4011 | } |
4012 | ||
1da100bb | 4013 | /* enable transmits */ |
477de6ed | 4014 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 4015 | |
9a799d71 AK |
4016 | /* bring the link up in the watchdog, this could race with our first |
4017 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
4018 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
4019 | adapter->link_check_timeout = jiffies; | |
7086400d | 4020 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
4021 | |
4022 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
4023 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
4024 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
4025 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
4026 | } |
4027 | ||
d4f80882 AV |
4028 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
4029 | { | |
4030 | WARN_ON(in_interrupt()); | |
7086400d AD |
4031 | /* put off any impending NetWatchDogTimeout */ |
4032 | adapter->netdev->trans_start = jiffies; | |
4033 | ||
d4f80882 | 4034 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 4035 | usleep_range(1000, 2000); |
d4f80882 | 4036 | ixgbe_down(adapter); |
5809a1ae GR |
4037 | /* |
4038 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
4039 | * back up to give the VFs time to respond to the reset. The | |
4040 | * two second wait is based upon the watchdog timer cycle in | |
4041 | * the VF driver. | |
4042 | */ | |
4043 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
4044 | msleep(2000); | |
d4f80882 AV |
4045 | ixgbe_up(adapter); |
4046 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
4047 | } | |
4048 | ||
c7ccde0f | 4049 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4050 | { |
4051 | /* hardware has been reset, we need to reload some things */ | |
4052 | ixgbe_configure(adapter); | |
4053 | ||
c7ccde0f | 4054 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4055 | } |
4056 | ||
4057 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
4058 | { | |
c44ade9e | 4059 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
4060 | int err; |
4061 | ||
7086400d AD |
4062 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
4063 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
4064 | usleep_range(1000, 2000); | |
4065 | ||
4066 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
4067 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
4068 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
4069 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
4070 | ||
8ca783ab | 4071 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
4072 | switch (err) { |
4073 | case 0: | |
4074 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 4075 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
4076 | break; |
4077 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 4078 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 4079 | break; |
794caeb2 PWJ |
4080 | case IXGBE_ERR_EEPROM_VERSION: |
4081 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 4082 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 4083 | "Please be aware there may be issues associated with " |
849c4542 ET |
4084 | "your hardware. If you are experiencing problems " |
4085 | "please contact your Intel or hardware " | |
4086 | "representative who provided you with this " | |
4087 | "hardware.\n"); | |
794caeb2 | 4088 | break; |
da4dd0f7 | 4089 | default: |
849c4542 | 4090 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 4091 | } |
9a799d71 | 4092 | |
7086400d AD |
4093 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
4094 | ||
9a799d71 | 4095 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
4096 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
4097 | IXGBE_RAH_AV); | |
9a799d71 AK |
4098 | } |
4099 | ||
f800326d AD |
4100 | /** |
4101 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
4102 | * @rx_ring: ring to setup | |
4103 | * | |
4104 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
4105 | * results in each receive buffer starting in the same cache set. To help | |
4106 | * reduce the pressure on this cache set we can interleave the offsets so | |
4107 | * that only every other buffer will be in the same cache set. | |
4108 | **/ | |
4109 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4110 | { | |
4111 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4112 | u16 i; | |
4113 | ||
4114 | for (i = 0; i < rx_ring->count; i += 2) { | |
4115 | rx_buffer[0].page_offset = 0; | |
4116 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4117 | rx_buffer = &rx_buffer[2]; | |
4118 | } | |
4119 | } | |
4120 | ||
9a799d71 AK |
4121 | /** |
4122 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4123 | * @rx_ring: ring to free buffers from |
4124 | **/ | |
b6ec895e | 4125 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4126 | { |
b6ec895e | 4127 | struct device *dev = rx_ring->dev; |
9a799d71 | 4128 | unsigned long size; |
b6ec895e | 4129 | u16 i; |
9a799d71 | 4130 | |
84418e3b AD |
4131 | /* ring already cleared, nothing to do */ |
4132 | if (!rx_ring->rx_buffer_info) | |
4133 | return; | |
9a799d71 | 4134 | |
84418e3b | 4135 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4136 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4137 | struct ixgbe_rx_buffer *rx_buffer; |
4138 | ||
4139 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4140 | if (rx_buffer->skb) { | |
4141 | struct sk_buff *skb = rx_buffer->skb; | |
4142 | if (IXGBE_CB(skb)->page_released) { | |
4143 | dma_unmap_page(dev, | |
4144 | IXGBE_CB(skb)->dma, | |
4145 | ixgbe_rx_bufsz(rx_ring), | |
4146 | DMA_FROM_DEVICE); | |
4147 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4148 | } |
4149 | dev_kfree_skb(skb); | |
9a799d71 | 4150 | } |
f800326d AD |
4151 | rx_buffer->skb = NULL; |
4152 | if (rx_buffer->dma) | |
4153 | dma_unmap_page(dev, rx_buffer->dma, | |
4154 | ixgbe_rx_pg_size(rx_ring), | |
4155 | DMA_FROM_DEVICE); | |
4156 | rx_buffer->dma = 0; | |
4157 | if (rx_buffer->page) | |
dd411ec4 AD |
4158 | __free_pages(rx_buffer->page, |
4159 | ixgbe_rx_pg_order(rx_ring)); | |
f800326d | 4160 | rx_buffer->page = NULL; |
9a799d71 AK |
4161 | } |
4162 | ||
4163 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4164 | memset(rx_ring->rx_buffer_info, 0, size); | |
4165 | ||
f800326d AD |
4166 | ixgbe_init_rx_page_offset(rx_ring); |
4167 | ||
9a799d71 AK |
4168 | /* Zero out the descriptor ring */ |
4169 | memset(rx_ring->desc, 0, rx_ring->size); | |
4170 | ||
f800326d | 4171 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4172 | rx_ring->next_to_clean = 0; |
4173 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4174 | } |
4175 | ||
4176 | /** | |
4177 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4178 | * @tx_ring: ring to be cleaned |
4179 | **/ | |
b6ec895e | 4180 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4181 | { |
4182 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4183 | unsigned long size; | |
b6ec895e | 4184 | u16 i; |
9a799d71 | 4185 | |
84418e3b AD |
4186 | /* ring already cleared, nothing to do */ |
4187 | if (!tx_ring->tx_buffer_info) | |
4188 | return; | |
9a799d71 | 4189 | |
84418e3b | 4190 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4191 | for (i = 0; i < tx_ring->count; i++) { |
4192 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4193 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4194 | } |
4195 | ||
dad8a3b3 JF |
4196 | netdev_tx_reset_queue(txring_txq(tx_ring)); |
4197 | ||
9a799d71 AK |
4198 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
4199 | memset(tx_ring->tx_buffer_info, 0, size); | |
4200 | ||
4201 | /* Zero out the descriptor ring */ | |
4202 | memset(tx_ring->desc, 0, tx_ring->size); | |
4203 | ||
4204 | tx_ring->next_to_use = 0; | |
4205 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4206 | } |
4207 | ||
4208 | /** | |
021230d4 | 4209 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4210 | * @adapter: board private structure |
4211 | **/ | |
021230d4 | 4212 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4213 | { |
4214 | int i; | |
4215 | ||
021230d4 | 4216 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4217 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4218 | } |
4219 | ||
4220 | /** | |
021230d4 | 4221 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4222 | * @adapter: board private structure |
4223 | **/ | |
021230d4 | 4224 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4225 | { |
4226 | int i; | |
4227 | ||
021230d4 | 4228 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4229 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4230 | } |
4231 | ||
e4911d57 AD |
4232 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4233 | { | |
4234 | struct hlist_node *node, *node2; | |
4235 | struct ixgbe_fdir_filter *filter; | |
4236 | ||
4237 | spin_lock(&adapter->fdir_perfect_lock); | |
4238 | ||
4239 | hlist_for_each_entry_safe(filter, node, node2, | |
4240 | &adapter->fdir_filter_list, fdir_node) { | |
4241 | hlist_del(&filter->fdir_node); | |
4242 | kfree(filter); | |
4243 | } | |
4244 | adapter->fdir_filter_count = 0; | |
4245 | ||
4246 | spin_unlock(&adapter->fdir_perfect_lock); | |
4247 | } | |
4248 | ||
9a799d71 AK |
4249 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4250 | { | |
4251 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4252 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4253 | u32 rxctrl; |
bf29ee6c | 4254 | int i; |
9a799d71 AK |
4255 | |
4256 | /* signal that we are down to the interrupt handler */ | |
4257 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4258 | ||
4259 | /* disable receives */ | |
7f821875 JB |
4260 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4261 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4262 | |
2d39d576 YZ |
4263 | /* disable all enabled rx queues */ |
4264 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4265 | /* this call also flushes the previous write */ | |
4266 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4267 | ||
032b4325 | 4268 | usleep_range(10000, 20000); |
9a799d71 | 4269 | |
7f821875 JB |
4270 | netif_tx_stop_all_queues(netdev); |
4271 | ||
7086400d | 4272 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4273 | netif_carrier_off(netdev); |
4274 | netif_tx_disable(netdev); | |
4275 | ||
4276 | ixgbe_irq_disable(adapter); | |
4277 | ||
4278 | ixgbe_napi_disable_all(adapter); | |
4279 | ||
d034acf1 AD |
4280 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4281 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4282 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4283 | ||
4284 | del_timer_sync(&adapter->service_timer); | |
4285 | ||
34cecbbf | 4286 | if (adapter->num_vfs) { |
8e34d1aa AD |
4287 | /* Clear EITR Select mapping */ |
4288 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4289 | |
4290 | /* Mark all the VFs as inactive */ | |
4291 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4292 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4293 | |
34cecbbf AD |
4294 | /* ping all the active vfs to let them know we are going down */ |
4295 | ixgbe_ping_all_vfs(adapter); | |
4296 | ||
4297 | /* Disable all VFTE/VFRE TX/RX */ | |
4298 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4299 | } |
4300 | ||
7f821875 JB |
4301 | /* disable transmits in the hardware now that interrupts are off */ |
4302 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4303 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4304 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4305 | } |
34cecbbf AD |
4306 | |
4307 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4308 | switch (hw->mac.type) { |
4309 | case ixgbe_mac_82599EB: | |
b93a2226 | 4310 | case ixgbe_mac_X540: |
88512539 | 4311 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4312 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4313 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4314 | break; |
4315 | default: | |
4316 | break; | |
4317 | } | |
7f821875 | 4318 | |
6f4a0e45 PL |
4319 | if (!pci_channel_offline(adapter->pdev)) |
4320 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4321 | |
4322 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4323 | if (hw->mac.ops.disable_tx_laser && | |
4324 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4325 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4326 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4327 | hw->mac.ops.disable_tx_laser(hw); | |
4328 | ||
9a799d71 AK |
4329 | ixgbe_clean_all_tx_rings(adapter); |
4330 | ixgbe_clean_all_rx_rings(adapter); | |
4331 | ||
5dd2d332 | 4332 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4333 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4334 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4335 | #endif |
9a799d71 AK |
4336 | } |
4337 | ||
9a799d71 AK |
4338 | /** |
4339 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4340 | * @netdev: network interface device structure | |
4341 | **/ | |
4342 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4343 | { | |
4344 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4345 | ||
4346 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4347 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4348 | } |
4349 | ||
9a799d71 AK |
4350 | /** |
4351 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
4352 | * @adapter: board private structure to initialize | |
4353 | * | |
4354 | * ixgbe_sw_init initializes the Adapter private data structure. | |
4355 | * Fields are initialized based on PCI device information and | |
4356 | * OS network device settings (MTU size). | |
4357 | **/ | |
4358 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
4359 | { | |
4360 | struct ixgbe_hw *hw = &adapter->hw; | |
4361 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 4362 | unsigned int rss; |
7a6b6f51 | 4363 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
4364 | int j; |
4365 | struct tc_configuration *tc; | |
4366 | #endif | |
021230d4 | 4367 | |
c44ade9e JB |
4368 | /* PCI config space info */ |
4369 | ||
4370 | hw->vendor_id = pdev->vendor; | |
4371 | hw->device_id = pdev->device; | |
4372 | hw->revision_id = pdev->revision; | |
4373 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
4374 | hw->subsystem_device_id = pdev->subsystem_device; | |
4375 | ||
021230d4 | 4376 | /* Set capability flags */ |
3ed69d7e | 4377 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
c087663e | 4378 | adapter->ring_feature[RING_F_RSS].limit = rss; |
021230d4 | 4379 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; |
bd508178 AD |
4380 | switch (hw->mac.type) { |
4381 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
4382 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
4383 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
49c7ffbe | 4384 | adapter->max_q_vectors = MAX_Q_VECTORS_82598; |
bd508178 | 4385 | break; |
b93a2226 | 4386 | case ixgbe_mac_X540: |
4f51bf70 JK |
4387 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
4388 | case ixgbe_mac_82599EB: | |
49c7ffbe | 4389 | adapter->max_q_vectors = MAX_Q_VECTORS_82599; |
0c19d6af PWJ |
4390 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
4391 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
4392 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
4393 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
4394 | /* Flow Director hash filters enabled */ |
4395 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
4396 | adapter->atr_sample_rate = 20; | |
c087663e | 4397 | adapter->ring_feature[RING_F_FDIR].limit = |
e8e9f696 | 4398 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 4399 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 4400 | #ifdef IXGBE_FCOE |
0d551589 YZ |
4401 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
4402 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
61a0f421 | 4403 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 4404 | /* Default traffic class to use for FCoE */ |
56075a98 | 4405 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 4406 | #endif |
eacd73f7 | 4407 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
4408 | break; |
4409 | default: | |
4410 | break; | |
f8212f97 | 4411 | } |
2f90b865 | 4412 | |
1fc5f038 AD |
4413 | /* n-tuple support exists, always init our spinlock */ |
4414 | spin_lock_init(&adapter->fdir_perfect_lock); | |
4415 | ||
7a6b6f51 | 4416 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
4417 | switch (hw->mac.type) { |
4418 | case ixgbe_mac_X540: | |
4419 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
4420 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
4421 | break; | |
4422 | default: | |
4423 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
4424 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
4425 | break; | |
4426 | } | |
4427 | ||
2f90b865 AD |
4428 | /* Configure DCB traffic classes */ |
4429 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
4430 | tc = &adapter->dcb_cfg.tc_config[j]; | |
4431 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
4432 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
4433 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
4434 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
4435 | tc->dcb_pfc = pfc_disabled; | |
4436 | } | |
4de2a022 JF |
4437 | |
4438 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
4439 | tc = &adapter->dcb_cfg.tc_config[0]; | |
4440 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4441 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
4442 | ||
2f90b865 AD |
4443 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
4444 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 4445 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 4446 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 4447 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
f525c6d2 JF |
4448 | memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg, |
4449 | sizeof(adapter->temp_dcb_cfg)); | |
2f90b865 AD |
4450 | |
4451 | #endif | |
9a799d71 AK |
4452 | |
4453 | /* default flow control settings */ | |
cd7664f6 | 4454 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 4455 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
9da712d2 | 4456 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
4457 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
4458 | hw->fc.send_xon = true; | |
71fd570b | 4459 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 4460 | |
30efa5a3 | 4461 | /* enable itr by default in dynamic mode */ |
f7554a2b | 4462 | adapter->rx_itr_setting = 1; |
f7554a2b | 4463 | adapter->tx_itr_setting = 1; |
30efa5a3 | 4464 | |
30efa5a3 JB |
4465 | /* set default ring sizes */ |
4466 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
4467 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
4468 | ||
bd198058 | 4469 | /* set default work limits */ |
59224555 | 4470 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 4471 | |
9a799d71 | 4472 | /* initialize eeprom parameters */ |
c44ade9e | 4473 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 4474 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
4475 | return -EIO; |
4476 | } | |
4477 | ||
9a799d71 AK |
4478 | set_bit(__IXGBE_DOWN, &adapter->state); |
4479 | ||
4480 | return 0; | |
4481 | } | |
4482 | ||
4483 | /** | |
4484 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 4485 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4486 | * |
4487 | * Return 0 on success, negative on failure | |
4488 | **/ | |
b6ec895e | 4489 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4490 | { |
b6ec895e | 4491 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
4492 | int orig_node = dev_to_node(dev); |
4493 | int numa_node = -1; | |
9a799d71 AK |
4494 | int size; |
4495 | ||
3a581073 | 4496 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
4497 | |
4498 | if (tx_ring->q_vector) | |
4499 | numa_node = tx_ring->q_vector->numa_node; | |
4500 | ||
4501 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4502 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 4503 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
4504 | if (!tx_ring->tx_buffer_info) |
4505 | goto err; | |
9a799d71 AK |
4506 | |
4507 | /* round up to nearest 4K */ | |
12207e49 | 4508 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 4509 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 4510 | |
de88eeeb AD |
4511 | set_dev_node(dev, numa_node); |
4512 | tx_ring->desc = dma_alloc_coherent(dev, | |
4513 | tx_ring->size, | |
4514 | &tx_ring->dma, | |
4515 | GFP_KERNEL); | |
4516 | set_dev_node(dev, orig_node); | |
4517 | if (!tx_ring->desc) | |
4518 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
4519 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
4520 | if (!tx_ring->desc) |
4521 | goto err; | |
9a799d71 | 4522 | |
3a581073 JB |
4523 | tx_ring->next_to_use = 0; |
4524 | tx_ring->next_to_clean = 0; | |
9a799d71 | 4525 | return 0; |
e01c31a5 JB |
4526 | |
4527 | err: | |
4528 | vfree(tx_ring->tx_buffer_info); | |
4529 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 4530 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 4531 | return -ENOMEM; |
9a799d71 AK |
4532 | } |
4533 | ||
69888674 AD |
4534 | /** |
4535 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
4536 | * @adapter: board private structure | |
4537 | * | |
4538 | * If this function returns with an error, then it's possible one or | |
4539 | * more of the rings is populated (while the rest are not). It is the | |
4540 | * callers duty to clean those orphaned rings. | |
4541 | * | |
4542 | * Return 0 on success, negative on failure | |
4543 | **/ | |
4544 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
4545 | { | |
4546 | int i, err = 0; | |
4547 | ||
4548 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 4549 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
4550 | if (!err) |
4551 | continue; | |
de3d5b94 | 4552 | |
396e799c | 4553 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
de3d5b94 | 4554 | goto err_setup_tx; |
69888674 AD |
4555 | } |
4556 | ||
de3d5b94 AD |
4557 | return 0; |
4558 | err_setup_tx: | |
4559 | /* rewind the index freeing the rings as we go */ | |
4560 | while (i--) | |
4561 | ixgbe_free_tx_resources(adapter->tx_ring[i]); | |
69888674 AD |
4562 | return err; |
4563 | } | |
4564 | ||
9a799d71 AK |
4565 | /** |
4566 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 4567 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
4568 | * |
4569 | * Returns 0 on success, negative on failure | |
4570 | **/ | |
b6ec895e | 4571 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4572 | { |
b6ec895e | 4573 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
4574 | int orig_node = dev_to_node(dev); |
4575 | int numa_node = -1; | |
021230d4 | 4576 | int size; |
9a799d71 | 4577 | |
3a581073 | 4578 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
4579 | |
4580 | if (rx_ring->q_vector) | |
4581 | numa_node = rx_ring->q_vector->numa_node; | |
4582 | ||
4583 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 4584 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 4585 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
4586 | if (!rx_ring->rx_buffer_info) |
4587 | goto err; | |
9a799d71 | 4588 | |
9a799d71 | 4589 | /* Round up to nearest 4K */ |
3a581073 JB |
4590 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
4591 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 4592 | |
de88eeeb AD |
4593 | set_dev_node(dev, numa_node); |
4594 | rx_ring->desc = dma_alloc_coherent(dev, | |
4595 | rx_ring->size, | |
4596 | &rx_ring->dma, | |
4597 | GFP_KERNEL); | |
4598 | set_dev_node(dev, orig_node); | |
4599 | if (!rx_ring->desc) | |
4600 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
4601 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
4602 | if (!rx_ring->desc) |
4603 | goto err; | |
9a799d71 | 4604 | |
3a581073 JB |
4605 | rx_ring->next_to_clean = 0; |
4606 | rx_ring->next_to_use = 0; | |
9a799d71 | 4607 | |
f800326d AD |
4608 | ixgbe_init_rx_page_offset(rx_ring); |
4609 | ||
9a799d71 | 4610 | return 0; |
b6ec895e AD |
4611 | err: |
4612 | vfree(rx_ring->rx_buffer_info); | |
4613 | rx_ring->rx_buffer_info = NULL; | |
4614 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 4615 | return -ENOMEM; |
9a799d71 AK |
4616 | } |
4617 | ||
69888674 AD |
4618 | /** |
4619 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
4620 | * @adapter: board private structure | |
4621 | * | |
4622 | * If this function returns with an error, then it's possible one or | |
4623 | * more of the rings is populated (while the rest are not). It is the | |
4624 | * callers duty to clean those orphaned rings. | |
4625 | * | |
4626 | * Return 0 on success, negative on failure | |
4627 | **/ | |
69888674 AD |
4628 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
4629 | { | |
4630 | int i, err = 0; | |
4631 | ||
4632 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 4633 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
4634 | if (!err) |
4635 | continue; | |
de3d5b94 | 4636 | |
396e799c | 4637 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
de3d5b94 | 4638 | goto err_setup_rx; |
69888674 AD |
4639 | } |
4640 | ||
de3d5b94 AD |
4641 | return 0; |
4642 | err_setup_rx: | |
4643 | /* rewind the index freeing the rings as we go */ | |
4644 | while (i--) | |
4645 | ixgbe_free_rx_resources(adapter->rx_ring[i]); | |
69888674 AD |
4646 | return err; |
4647 | } | |
4648 | ||
9a799d71 AK |
4649 | /** |
4650 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
4651 | * @tx_ring: Tx descriptor ring for a specific queue |
4652 | * | |
4653 | * Free all transmit software resources | |
4654 | **/ | |
b6ec895e | 4655 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 4656 | { |
b6ec895e | 4657 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
4658 | |
4659 | vfree(tx_ring->tx_buffer_info); | |
4660 | tx_ring->tx_buffer_info = NULL; | |
4661 | ||
b6ec895e AD |
4662 | /* if not set, then don't free */ |
4663 | if (!tx_ring->desc) | |
4664 | return; | |
4665 | ||
4666 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
4667 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
4668 | |
4669 | tx_ring->desc = NULL; | |
4670 | } | |
4671 | ||
4672 | /** | |
4673 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
4674 | * @adapter: board private structure | |
4675 | * | |
4676 | * Free all transmit software resources | |
4677 | **/ | |
4678 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
4679 | { | |
4680 | int i; | |
4681 | ||
4682 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 4683 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 4684 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
4685 | } |
4686 | ||
4687 | /** | |
b4617240 | 4688 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
4689 | * @rx_ring: ring to clean the resources from |
4690 | * | |
4691 | * Free all receive software resources | |
4692 | **/ | |
b6ec895e | 4693 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 4694 | { |
b6ec895e | 4695 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
4696 | |
4697 | vfree(rx_ring->rx_buffer_info); | |
4698 | rx_ring->rx_buffer_info = NULL; | |
4699 | ||
b6ec895e AD |
4700 | /* if not set, then don't free */ |
4701 | if (!rx_ring->desc) | |
4702 | return; | |
4703 | ||
4704 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
4705 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
4706 | |
4707 | rx_ring->desc = NULL; | |
4708 | } | |
4709 | ||
4710 | /** | |
4711 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
4712 | * @adapter: board private structure | |
4713 | * | |
4714 | * Free all receive software resources | |
4715 | **/ | |
4716 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
4717 | { | |
4718 | int i; | |
4719 | ||
4720 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 4721 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 4722 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
4723 | } |
4724 | ||
9a799d71 AK |
4725 | /** |
4726 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
4727 | * @netdev: network interface device structure | |
4728 | * @new_mtu: new value for maximum frame size | |
4729 | * | |
4730 | * Returns 0 on success, negative on failure | |
4731 | **/ | |
4732 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
4733 | { | |
4734 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4735 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
4736 | ||
42c783c5 | 4737 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
4738 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
4739 | return -EINVAL; | |
4740 | ||
4741 | /* | |
4742 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
4743 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
4744 | * don't allocate and chain buffers correctly. | |
4745 | */ | |
4746 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
4747 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
4748 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 4749 | return -EINVAL; |
9a799d71 | 4750 | |
396e799c | 4751 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 4752 | |
021230d4 | 4753 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
4754 | netdev->mtu = new_mtu; |
4755 | ||
d4f80882 AV |
4756 | if (netif_running(netdev)) |
4757 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
4758 | |
4759 | return 0; | |
4760 | } | |
4761 | ||
4762 | /** | |
4763 | * ixgbe_open - Called when a network interface is made active | |
4764 | * @netdev: network interface device structure | |
4765 | * | |
4766 | * Returns 0 on success, negative value on failure | |
4767 | * | |
4768 | * The open entry point is called when a network interface is made | |
4769 | * active by the system (IFF_UP). At this point all resources needed | |
4770 | * for transmit and receive operations are allocated, the interrupt | |
4771 | * handler is registered with the OS, the watchdog timer is started, | |
4772 | * and the stack is notified that the interface is ready. | |
4773 | **/ | |
4774 | static int ixgbe_open(struct net_device *netdev) | |
4775 | { | |
4776 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4777 | int err; | |
4bebfaa5 AK |
4778 | |
4779 | /* disallow open during test */ | |
4780 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
4781 | return -EBUSY; | |
9a799d71 | 4782 | |
54386467 JB |
4783 | netif_carrier_off(netdev); |
4784 | ||
9a799d71 AK |
4785 | /* allocate transmit descriptors */ |
4786 | err = ixgbe_setup_all_tx_resources(adapter); | |
4787 | if (err) | |
4788 | goto err_setup_tx; | |
4789 | ||
9a799d71 AK |
4790 | /* allocate receive descriptors */ |
4791 | err = ixgbe_setup_all_rx_resources(adapter); | |
4792 | if (err) | |
4793 | goto err_setup_rx; | |
4794 | ||
4795 | ixgbe_configure(adapter); | |
4796 | ||
021230d4 | 4797 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
4798 | if (err) |
4799 | goto err_req_irq; | |
4800 | ||
ac802f5d AD |
4801 | /* Notify the stack of the actual queue counts. */ |
4802 | err = netif_set_real_num_tx_queues(netdev, | |
4803 | adapter->num_rx_pools > 1 ? 1 : | |
4804 | adapter->num_tx_queues); | |
4805 | if (err) | |
4806 | goto err_set_queues; | |
4807 | ||
4808 | ||
4809 | err = netif_set_real_num_rx_queues(netdev, | |
4810 | adapter->num_rx_pools > 1 ? 1 : | |
4811 | adapter->num_rx_queues); | |
4812 | if (err) | |
4813 | goto err_set_queues; | |
4814 | ||
c7ccde0f | 4815 | ixgbe_up_complete(adapter); |
9a799d71 AK |
4816 | |
4817 | return 0; | |
4818 | ||
ac802f5d AD |
4819 | err_set_queues: |
4820 | ixgbe_free_irq(adapter); | |
9a799d71 | 4821 | err_req_irq: |
a20a1199 | 4822 | ixgbe_free_all_rx_resources(adapter); |
de3d5b94 | 4823 | err_setup_rx: |
a20a1199 | 4824 | ixgbe_free_all_tx_resources(adapter); |
de3d5b94 | 4825 | err_setup_tx: |
9a799d71 AK |
4826 | ixgbe_reset(adapter); |
4827 | ||
4828 | return err; | |
4829 | } | |
4830 | ||
4831 | /** | |
4832 | * ixgbe_close - Disables a network interface | |
4833 | * @netdev: network interface device structure | |
4834 | * | |
4835 | * Returns 0, this is not allowed to fail | |
4836 | * | |
4837 | * The close entry point is called when an interface is de-activated | |
4838 | * by the OS. The hardware is still under the drivers control, but | |
4839 | * needs to be disabled. A global MAC reset is issued to stop the | |
4840 | * hardware, and all transmit and receive resources are freed. | |
4841 | **/ | |
4842 | static int ixgbe_close(struct net_device *netdev) | |
4843 | { | |
4844 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
4845 | |
4846 | ixgbe_down(adapter); | |
4847 | ixgbe_free_irq(adapter); | |
4848 | ||
e4911d57 AD |
4849 | ixgbe_fdir_filter_exit(adapter); |
4850 | ||
9a799d71 AK |
4851 | ixgbe_free_all_tx_resources(adapter); |
4852 | ixgbe_free_all_rx_resources(adapter); | |
4853 | ||
5eba3699 | 4854 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
4855 | |
4856 | return 0; | |
4857 | } | |
4858 | ||
b3c8b4ba AD |
4859 | #ifdef CONFIG_PM |
4860 | static int ixgbe_resume(struct pci_dev *pdev) | |
4861 | { | |
c60fbb00 AD |
4862 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4863 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
4864 | u32 err; |
4865 | ||
4866 | pci_set_power_state(pdev, PCI_D0); | |
4867 | pci_restore_state(pdev); | |
656ab817 DS |
4868 | /* |
4869 | * pci_restore_state clears dev->state_saved so call | |
4870 | * pci_save_state to restore it. | |
4871 | */ | |
4872 | pci_save_state(pdev); | |
9ce77666 | 4873 | |
4874 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 4875 | if (err) { |
849c4542 | 4876 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
4877 | return err; |
4878 | } | |
4879 | pci_set_master(pdev); | |
4880 | ||
dd4d8ca6 | 4881 | pci_wake_from_d3(pdev, false); |
b3c8b4ba | 4882 | |
b3c8b4ba AD |
4883 | ixgbe_reset(adapter); |
4884 | ||
495dce12 WJP |
4885 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
4886 | ||
ac802f5d AD |
4887 | rtnl_lock(); |
4888 | err = ixgbe_init_interrupt_scheme(adapter); | |
4889 | if (!err && netif_running(netdev)) | |
c60fbb00 | 4890 | err = ixgbe_open(netdev); |
ac802f5d AD |
4891 | |
4892 | rtnl_unlock(); | |
4893 | ||
4894 | if (err) | |
4895 | return err; | |
b3c8b4ba AD |
4896 | |
4897 | netif_device_attach(netdev); | |
4898 | ||
4899 | return 0; | |
4900 | } | |
b3c8b4ba | 4901 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
4902 | |
4903 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 4904 | { |
c60fbb00 AD |
4905 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
4906 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
4907 | struct ixgbe_hw *hw = &adapter->hw; |
4908 | u32 ctrl, fctrl; | |
4909 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
4910 | #ifdef CONFIG_PM |
4911 | int retval = 0; | |
4912 | #endif | |
4913 | ||
4914 | netif_device_detach(netdev); | |
4915 | ||
4916 | if (netif_running(netdev)) { | |
ab6039a7 | 4917 | rtnl_lock(); |
b3c8b4ba AD |
4918 | ixgbe_down(adapter); |
4919 | ixgbe_free_irq(adapter); | |
4920 | ixgbe_free_all_tx_resources(adapter); | |
4921 | ixgbe_free_all_rx_resources(adapter); | |
ab6039a7 | 4922 | rtnl_unlock(); |
b3c8b4ba | 4923 | } |
b3c8b4ba | 4924 | |
5f5ae6fc AD |
4925 | ixgbe_clear_interrupt_scheme(adapter); |
4926 | ||
b3c8b4ba AD |
4927 | #ifdef CONFIG_PM |
4928 | retval = pci_save_state(pdev); | |
4929 | if (retval) | |
4930 | return retval; | |
4df10466 | 4931 | |
b3c8b4ba | 4932 | #endif |
e8e26350 PW |
4933 | if (wufc) { |
4934 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 4935 | |
c509e754 DS |
4936 | /* |
4937 | * enable the optics for both mult-speed fiber and | |
4938 | * 82599 SFP+ fiber as we can WoL. | |
4939 | */ | |
4940 | if (hw->mac.ops.enable_tx_laser && | |
4941 | (hw->phy.multispeed_fiber || | |
4942 | (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber && | |
4943 | hw->mac.type == ixgbe_mac_82599EB))) | |
4944 | hw->mac.ops.enable_tx_laser(hw); | |
4945 | ||
e8e26350 PW |
4946 | /* turn on all-multi mode if wake on multicast is enabled */ |
4947 | if (wufc & IXGBE_WUFC_MC) { | |
4948 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
4949 | fctrl |= IXGBE_FCTRL_MPE; | |
4950 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
4951 | } | |
4952 | ||
4953 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
4954 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
4955 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
4956 | ||
4957 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
4958 | } else { | |
4959 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
4960 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
4961 | } | |
4962 | ||
bd508178 AD |
4963 | switch (hw->mac.type) { |
4964 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 4965 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
4966 | break; |
4967 | case ixgbe_mac_82599EB: | |
b93a2226 | 4968 | case ixgbe_mac_X540: |
bd508178 AD |
4969 | pci_wake_from_d3(pdev, !!wufc); |
4970 | break; | |
4971 | default: | |
4972 | break; | |
4973 | } | |
b3c8b4ba | 4974 | |
9d8d05ae RW |
4975 | *enable_wake = !!wufc; |
4976 | ||
b3c8b4ba AD |
4977 | ixgbe_release_hw_control(adapter); |
4978 | ||
4979 | pci_disable_device(pdev); | |
4980 | ||
9d8d05ae RW |
4981 | return 0; |
4982 | } | |
4983 | ||
4984 | #ifdef CONFIG_PM | |
4985 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
4986 | { | |
4987 | int retval; | |
4988 | bool wake; | |
4989 | ||
4990 | retval = __ixgbe_shutdown(pdev, &wake); | |
4991 | if (retval) | |
4992 | return retval; | |
4993 | ||
4994 | if (wake) { | |
4995 | pci_prepare_to_sleep(pdev); | |
4996 | } else { | |
4997 | pci_wake_from_d3(pdev, false); | |
4998 | pci_set_power_state(pdev, PCI_D3hot); | |
4999 | } | |
b3c8b4ba AD |
5000 | |
5001 | return 0; | |
5002 | } | |
9d8d05ae | 5003 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5004 | |
5005 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5006 | { | |
9d8d05ae RW |
5007 | bool wake; |
5008 | ||
5009 | __ixgbe_shutdown(pdev, &wake); | |
5010 | ||
5011 | if (system_state == SYSTEM_POWER_OFF) { | |
5012 | pci_wake_from_d3(pdev, wake); | |
5013 | pci_set_power_state(pdev, PCI_D3hot); | |
5014 | } | |
b3c8b4ba AD |
5015 | } |
5016 | ||
9a799d71 AK |
5017 | /** |
5018 | * ixgbe_update_stats - Update the board statistics counters. | |
5019 | * @adapter: board private structure | |
5020 | **/ | |
5021 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5022 | { | |
2d86f139 | 5023 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5024 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5025 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5026 | u64 total_mpc = 0; |
5027 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5028 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5029 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 5030 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
7b859ebc AH |
5031 | #ifdef IXGBE_FCOE |
5032 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
5033 | unsigned int cpu; | |
5034 | u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0; | |
5035 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 5036 | |
d08935c2 DS |
5037 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5038 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5039 | return; | |
5040 | ||
94b982b2 | 5041 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5042 | u64 rsc_count = 0; |
94b982b2 | 5043 | u64 rsc_flush = 0; |
94b982b2 | 5044 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5045 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5046 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5047 | } |
5048 | adapter->rsc_total_count = rsc_count; | |
5049 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5050 | } |
5051 | ||
5b7da515 AD |
5052 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5053 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5054 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5055 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5056 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5057 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5058 | bytes += rx_ring->stats.bytes; |
5059 | packets += rx_ring->stats.packets; | |
5060 | } | |
5061 | adapter->non_eop_descs = non_eop_descs; | |
5062 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5063 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5064 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5065 | netdev->stats.rx_bytes = bytes; |
5066 | netdev->stats.rx_packets = packets; | |
5067 | ||
5068 | bytes = 0; | |
5069 | packets = 0; | |
7ca3bc58 | 5070 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5071 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5072 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5073 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5074 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5075 | bytes += tx_ring->stats.bytes; | |
5076 | packets += tx_ring->stats.packets; | |
5077 | } | |
eb985f09 | 5078 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5079 | adapter->tx_busy = tx_busy; |
5080 | netdev->stats.tx_bytes = bytes; | |
5081 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5082 | |
7ca647bd | 5083 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5084 | |
5085 | /* 8 register reads */ | |
6f11eef7 AV |
5086 | for (i = 0; i < 8; i++) { |
5087 | /* for packet buffers not used, the register should read 0 */ | |
5088 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5089 | missed_rx += mpc; | |
7ca647bd JP |
5090 | hwstats->mpc[i] += mpc; |
5091 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5092 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5093 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5094 | switch (hw->mac.type) { |
5095 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5096 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5097 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5098 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5099 | hwstats->pxonrxc[i] += |
5100 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5101 | break; |
5102 | case ixgbe_mac_82599EB: | |
b93a2226 | 5103 | case ixgbe_mac_X540: |
bd508178 AD |
5104 | hwstats->pxonrxc[i] += |
5105 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5106 | break; |
5107 | default: | |
5108 | break; | |
e8e26350 | 5109 | } |
6f11eef7 | 5110 | } |
1a70db4b ET |
5111 | |
5112 | /*16 register reads */ | |
5113 | for (i = 0; i < 16; i++) { | |
5114 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5115 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5116 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5117 | (hw->mac.type == ixgbe_mac_X540)) { | |
5118 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5119 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5120 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5121 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5122 | } | |
5123 | } | |
5124 | ||
7ca647bd | 5125 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5126 | /* work around hardware counting issue */ |
7ca647bd | 5127 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5128 | |
c84d324c JF |
5129 | ixgbe_update_xoff_received(adapter); |
5130 | ||
6f11eef7 | 5131 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5132 | switch (hw->mac.type) { |
5133 | case ixgbe_mac_82598EB: | |
5134 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5135 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5136 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5137 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5138 | break; | |
b93a2226 | 5139 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5140 | /* OS2BMC stats are X540 only*/ |
5141 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5142 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5143 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5144 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5145 | case ixgbe_mac_82599EB: | |
a4d4f629 AD |
5146 | for (i = 0; i < 16; i++) |
5147 | adapter->hw_rx_no_dma_resources += | |
5148 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); | |
7ca647bd | 5149 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5150 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5151 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5152 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5153 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5154 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5155 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5156 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5157 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5158 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5159 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5160 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5161 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5162 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5163 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5164 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc AH |
5165 | /* Add up per cpu counters for total ddp aloc fail */ |
5166 | if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) { | |
5167 | for_each_possible_cpu(cpu) { | |
5168 | fcoe_noddp_counts_sum += | |
5169 | *per_cpu_ptr(fcoe->pcpu_noddp, cpu); | |
5170 | fcoe_noddp_ext_buff_counts_sum += | |
5171 | *per_cpu_ptr(fcoe-> | |
5172 | pcpu_noddp_ext_buff, cpu); | |
5173 | } | |
5174 | } | |
5175 | hwstats->fcoe_noddp = fcoe_noddp_counts_sum; | |
5176 | hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum; | |
6d45522c | 5177 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5178 | break; |
5179 | default: | |
5180 | break; | |
e8e26350 | 5181 | } |
9a799d71 | 5182 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5183 | hwstats->bprc += bprc; |
5184 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5185 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5186 | hwstats->mprc -= bprc; |
5187 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5188 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5189 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5190 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5191 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5192 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5193 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5194 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5195 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5196 | hwstats->lxontxc += lxon; |
6f11eef7 | 5197 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5198 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5199 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5200 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5201 | /* |
5202 | * 82598 errata - tx of flow control packets is included in tx counters | |
5203 | */ | |
5204 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5205 | hwstats->gptc -= xon_off_tot; |
5206 | hwstats->mptc -= xon_off_tot; | |
5207 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5208 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
5209 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
5210 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
5211 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
5212 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
5213 | hwstats->ptc64 -= xon_off_tot; | |
5214 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
5215 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
5216 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
5217 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
5218 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
5219 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
5220 | |
5221 | /* Fill out the OS statistics structure */ | |
7ca647bd | 5222 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
5223 | |
5224 | /* Rx Errors */ | |
7ca647bd | 5225 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 5226 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
5227 | netdev->stats.rx_length_errors = hwstats->rlec; |
5228 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 5229 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
5230 | } |
5231 | ||
5232 | /** | |
d034acf1 | 5233 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
49ce9c2c | 5234 | * @adapter: pointer to the device adapter structure |
9a799d71 | 5235 | **/ |
d034acf1 | 5236 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 5237 | { |
cf8280ee | 5238 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 5239 | int i; |
cf8280ee | 5240 | |
d034acf1 AD |
5241 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
5242 | return; | |
5243 | ||
5244 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 5245 | |
d034acf1 | 5246 | /* if interface is down do nothing */ |
fe49f04a | 5247 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
5248 | return; |
5249 | ||
5250 | /* do nothing if we are not using signature filters */ | |
5251 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
5252 | return; | |
5253 | ||
5254 | adapter->fdir_overflow++; | |
5255 | ||
93c52dd0 AD |
5256 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
5257 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5258 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 5259 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
5260 | /* re-enable flow director interrupts */ |
5261 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
5262 | } else { |
5263 | e_err(probe, "failed to finish FDIR re-initialization, " | |
5264 | "ignored adding FDIR ATR filters\n"); | |
5265 | } | |
93c52dd0 AD |
5266 | } |
5267 | ||
5268 | /** | |
5269 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
49ce9c2c | 5270 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5271 | * |
5272 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 5273 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 5274 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 5275 | * determine if a hang has occurred. |
93c52dd0 AD |
5276 | */ |
5277 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 5278 | { |
cf8280ee | 5279 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
5280 | u64 eics = 0; |
5281 | int i; | |
cf8280ee | 5282 | |
93c52dd0 AD |
5283 | /* If we're down or resetting, just bail */ |
5284 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5285 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5286 | return; | |
22d5a71b | 5287 | |
93c52dd0 AD |
5288 | /* Force detection of hung controller */ |
5289 | if (netif_carrier_ok(adapter->netdev)) { | |
5290 | for (i = 0; i < adapter->num_tx_queues; i++) | |
5291 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
5292 | } | |
22d5a71b | 5293 | |
fe49f04a AD |
5294 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
5295 | /* | |
5296 | * for legacy and MSI interrupts don't set any bits | |
5297 | * that are enabled for EIAM, because this operation | |
5298 | * would set *both* EIMS and EICS for any bit in EIAM | |
5299 | */ | |
5300 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
5301 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
5302 | } else { |
5303 | /* get one bit for every active tx/rx interrupt vector */ | |
49c7ffbe | 5304 | for (i = 0; i < adapter->num_q_vectors; i++) { |
93c52dd0 | 5305 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; |
efe3d3c8 | 5306 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
5307 | eics |= ((u64)1 << i); |
5308 | } | |
cf8280ee | 5309 | } |
9a799d71 | 5310 | |
93c52dd0 | 5311 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
5312 | ixgbe_irq_rearm_queues(adapter, eics); |
5313 | ||
cf8280ee JB |
5314 | } |
5315 | ||
e8e26350 | 5316 | /** |
93c52dd0 | 5317 | * ixgbe_watchdog_update_link - update the link status |
49ce9c2c BH |
5318 | * @adapter: pointer to the device adapter structure |
5319 | * @link_speed: pointer to a u32 to store the link_speed | |
e8e26350 | 5320 | **/ |
93c52dd0 | 5321 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 5322 | { |
e8e26350 | 5323 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5324 | u32 link_speed = adapter->link_speed; |
5325 | bool link_up = adapter->link_up; | |
041441d0 | 5326 | bool pfc_en = adapter->dcb_cfg.pfc_mode_enable; |
e8e26350 | 5327 | |
93c52dd0 AD |
5328 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
5329 | return; | |
5330 | ||
5331 | if (hw->mac.ops.check_link) { | |
5332 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 5333 | } else { |
93c52dd0 AD |
5334 | /* always assume link is up, if no check link function */ |
5335 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
5336 | link_up = true; | |
c4cf55e5 | 5337 | } |
041441d0 AD |
5338 | |
5339 | if (adapter->ixgbe_ieee_pfc) | |
5340 | pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en); | |
5341 | ||
3ebe8fde | 5342 | if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) { |
041441d0 | 5343 | hw->mac.ops.fc_enable(hw); |
3ebe8fde AD |
5344 | ixgbe_set_rx_drop_en(adapter); |
5345 | } | |
93c52dd0 AD |
5346 | |
5347 | if (link_up || | |
5348 | time_after(jiffies, (adapter->link_check_timeout + | |
5349 | IXGBE_TRY_LINK_TIMEOUT))) { | |
5350 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
5351 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
5352 | IXGBE_WRITE_FLUSH(hw); | |
5353 | } | |
5354 | ||
5355 | adapter->link_up = link_up; | |
5356 | adapter->link_speed = link_speed; | |
e8e26350 PW |
5357 | } |
5358 | ||
5359 | /** | |
93c52dd0 AD |
5360 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
5361 | * print link up message | |
49ce9c2c | 5362 | * @adapter: pointer to the device adapter structure |
e8e26350 | 5363 | **/ |
93c52dd0 | 5364 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 5365 | { |
93c52dd0 | 5366 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 5367 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
5368 | u32 link_speed = adapter->link_speed; |
5369 | bool flow_rx, flow_tx; | |
e8e26350 | 5370 | |
93c52dd0 AD |
5371 | /* only continue if link was previously down */ |
5372 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 5373 | return; |
63d6e1d8 | 5374 | |
93c52dd0 | 5375 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 5376 | |
93c52dd0 AD |
5377 | switch (hw->mac.type) { |
5378 | case ixgbe_mac_82598EB: { | |
5379 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5380 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
5381 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
5382 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
5383 | } | |
5384 | break; | |
5385 | case ixgbe_mac_X540: | |
5386 | case ixgbe_mac_82599EB: { | |
5387 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
5388 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
5389 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
5390 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
5391 | } | |
5392 | break; | |
5393 | default: | |
5394 | flow_tx = false; | |
5395 | flow_rx = false; | |
5396 | break; | |
e8e26350 | 5397 | } |
3a6a4eda JK |
5398 | |
5399 | #ifdef CONFIG_IXGBE_PTP | |
5400 | ixgbe_ptp_start_cyclecounter(adapter); | |
5401 | #endif | |
5402 | ||
93c52dd0 AD |
5403 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
5404 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
5405 | "10 Gbps" : | |
5406 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
5407 | "1 Gbps" : | |
5408 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
5409 | "100 Mbps" : | |
5410 | "unknown speed"))), | |
5411 | ((flow_rx && flow_tx) ? "RX/TX" : | |
5412 | (flow_rx ? "RX" : | |
5413 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 5414 | |
93c52dd0 | 5415 | netif_carrier_on(netdev); |
93c52dd0 | 5416 | ixgbe_check_vf_rate_limit(adapter); |
befa2af7 AD |
5417 | |
5418 | /* ping all the active vfs to let them know link has changed */ | |
5419 | ixgbe_ping_all_vfs(adapter); | |
e8e26350 PW |
5420 | } |
5421 | ||
c4cf55e5 | 5422 | /** |
93c52dd0 AD |
5423 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
5424 | * print link down message | |
49ce9c2c | 5425 | * @adapter: pointer to the adapter structure |
c4cf55e5 | 5426 | **/ |
581330ba | 5427 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter) |
c4cf55e5 | 5428 | { |
cf8280ee | 5429 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 5430 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 5431 | |
93c52dd0 AD |
5432 | adapter->link_up = false; |
5433 | adapter->link_speed = 0; | |
cf8280ee | 5434 | |
93c52dd0 AD |
5435 | /* only continue if link was up previously */ |
5436 | if (!netif_carrier_ok(netdev)) | |
5437 | return; | |
264857b8 | 5438 | |
93c52dd0 AD |
5439 | /* poll for SFP+ cable when link is down */ |
5440 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
5441 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 5442 | |
3a6a4eda JK |
5443 | #ifdef CONFIG_IXGBE_PTP |
5444 | ixgbe_ptp_start_cyclecounter(adapter); | |
5445 | #endif | |
5446 | ||
93c52dd0 AD |
5447 | e_info(drv, "NIC Link is Down\n"); |
5448 | netif_carrier_off(netdev); | |
befa2af7 AD |
5449 | |
5450 | /* ping all the active vfs to let them know link has changed */ | |
5451 | ixgbe_ping_all_vfs(adapter); | |
93c52dd0 | 5452 | } |
e8e26350 | 5453 | |
93c52dd0 AD |
5454 | /** |
5455 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
49ce9c2c | 5456 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5457 | **/ |
5458 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
5459 | { | |
c4cf55e5 | 5460 | int i; |
93c52dd0 | 5461 | int some_tx_pending = 0; |
c4cf55e5 | 5462 | |
93c52dd0 | 5463 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 5464 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 5465 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
5466 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
5467 | some_tx_pending = 1; | |
5468 | break; | |
5469 | } | |
5470 | } | |
5471 | ||
5472 | if (some_tx_pending) { | |
5473 | /* We've lost link, so the controller stops DMA, | |
5474 | * but we've got queued Tx work that's never going | |
5475 | * to get done, so reset controller to flush Tx. | |
5476 | * (Do the reset outside of interrupt context). | |
5477 | */ | |
c83c6cbd | 5478 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 5479 | } |
c4cf55e5 | 5480 | } |
c4cf55e5 PWJ |
5481 | } |
5482 | ||
a985b6c3 GR |
5483 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
5484 | { | |
5485 | u32 ssvpc; | |
5486 | ||
5487 | /* Do not perform spoof check for 82598 */ | |
5488 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
5489 | return; | |
5490 | ||
5491 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
5492 | ||
5493 | /* | |
5494 | * ssvpc register is cleared on read, if zero then no | |
5495 | * spoofed packets in the last interval. | |
5496 | */ | |
5497 | if (!ssvpc) | |
5498 | return; | |
5499 | ||
5500 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
5501 | } | |
5502 | ||
93c52dd0 AD |
5503 | /** |
5504 | * ixgbe_watchdog_subtask - check and bring link up | |
49ce9c2c | 5505 | * @adapter: pointer to the device adapter structure |
93c52dd0 AD |
5506 | **/ |
5507 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
5508 | { | |
5509 | /* if interface is down do nothing */ | |
7edebf9a ET |
5510 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5511 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
5512 | return; |
5513 | ||
5514 | ixgbe_watchdog_update_link(adapter); | |
5515 | ||
5516 | if (adapter->link_up) | |
5517 | ixgbe_watchdog_link_is_up(adapter); | |
5518 | else | |
5519 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 5520 | |
a985b6c3 | 5521 | ixgbe_spoof_check(adapter); |
9a799d71 | 5522 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
5523 | |
5524 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 5525 | } |
10eec955 | 5526 | |
cf8280ee | 5527 | /** |
7086400d | 5528 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
49ce9c2c | 5529 | * @adapter: the ixgbe adapter structure |
cf8280ee | 5530 | **/ |
7086400d | 5531 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 5532 | { |
cf8280ee | 5533 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 5534 | s32 err; |
cf8280ee | 5535 | |
7086400d AD |
5536 | /* not searching for SFP so there is nothing to do here */ |
5537 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
5538 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5539 | return; | |
10eec955 | 5540 | |
7086400d AD |
5541 | /* someone else is in init, wait until next service event */ |
5542 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5543 | return; | |
cf8280ee | 5544 | |
7086400d AD |
5545 | err = hw->phy.ops.identify_sfp(hw); |
5546 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5547 | goto sfp_out; | |
264857b8 | 5548 | |
7086400d AD |
5549 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
5550 | /* If no cable is present, then we need to reset | |
5551 | * the next time we find a good cable. */ | |
5552 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 5553 | } |
9a799d71 | 5554 | |
7086400d AD |
5555 | /* exit on error */ |
5556 | if (err) | |
5557 | goto sfp_out; | |
e8e26350 | 5558 | |
7086400d AD |
5559 | /* exit if reset not needed */ |
5560 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
5561 | goto sfp_out; | |
9a799d71 | 5562 | |
7086400d | 5563 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 5564 | |
7086400d AD |
5565 | /* |
5566 | * A module may be identified correctly, but the EEPROM may not have | |
5567 | * support for that module. setup_sfp() will fail in that case, so | |
5568 | * we should not allow that module to load. | |
5569 | */ | |
5570 | if (hw->mac.type == ixgbe_mac_82598EB) | |
5571 | err = hw->phy.ops.reset(hw); | |
5572 | else | |
5573 | err = hw->mac.ops.setup_sfp(hw); | |
5574 | ||
5575 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
5576 | goto sfp_out; | |
5577 | ||
5578 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
5579 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
5580 | ||
5581 | sfp_out: | |
5582 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5583 | ||
5584 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
5585 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
5586 | e_dev_err("failed to initialize because an unsupported " | |
5587 | "SFP+ module type was detected.\n"); | |
5588 | e_dev_err("Reload the driver after installing a " | |
5589 | "supported module.\n"); | |
5590 | unregister_netdev(adapter->netdev); | |
bc59fcda | 5591 | } |
7086400d | 5592 | } |
bc59fcda | 5593 | |
7086400d AD |
5594 | /** |
5595 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
49ce9c2c | 5596 | * @adapter: the ixgbe adapter structure |
7086400d AD |
5597 | **/ |
5598 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
5599 | { | |
5600 | struct ixgbe_hw *hw = &adapter->hw; | |
5601 | u32 autoneg; | |
5602 | bool negotiation; | |
5603 | ||
5604 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
5605 | return; | |
5606 | ||
5607 | /* someone else is in init, wait until next service event */ | |
5608 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
5609 | return; | |
5610 | ||
5611 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
5612 | ||
5613 | autoneg = hw->phy.autoneg_advertised; | |
5614 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
5615 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
5616 | if (hw->mac.ops.setup_link) |
5617 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
5618 | ||
5619 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
5620 | adapter->link_check_timeout = jiffies; | |
5621 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
5622 | } | |
5623 | ||
83c61fa9 GR |
5624 | #ifdef CONFIG_PCI_IOV |
5625 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
5626 | { | |
5627 | int vf; | |
5628 | struct ixgbe_hw *hw = &adapter->hw; | |
5629 | struct net_device *netdev = adapter->netdev; | |
5630 | u32 gpc; | |
5631 | u32 ciaa, ciad; | |
5632 | ||
5633 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
5634 | if (gpc) /* If incrementing then no need for the check below */ | |
5635 | return; | |
5636 | /* | |
5637 | * Check to see if a bad DMA write target from an errant or | |
5638 | * malicious VF has caused a PCIe error. If so then we can | |
5639 | * issue a VFLR to the offending VF(s) and then resume without | |
5640 | * requesting a full slot reset. | |
5641 | */ | |
5642 | ||
5643 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
5644 | ciaa = (vf << 16) | 0x80000000; | |
5645 | /* 32 bit read so align, we really want status at offset 6 */ | |
5646 | ciaa |= PCI_COMMAND; | |
5647 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5648 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
5649 | ciaa &= 0x7FFFFFFF; | |
5650 | /* disable debug mode asap after reading data */ | |
5651 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5652 | /* Get the upper 16 bits which will be the PCI status reg */ | |
5653 | ciad >>= 16; | |
5654 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
5655 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
5656 | /* Issue VFLR */ | |
5657 | ciaa = (vf << 16) | 0x80000000; | |
5658 | ciaa |= 0xA8; | |
5659 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5660 | ciad = 0x00008000; /* VFLR */ | |
5661 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
5662 | ciaa &= 0x7FFFFFFF; | |
5663 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
5664 | } | |
5665 | } | |
5666 | } | |
5667 | ||
5668 | #endif | |
7086400d AD |
5669 | /** |
5670 | * ixgbe_service_timer - Timer Call-back | |
5671 | * @data: pointer to adapter cast into an unsigned long | |
5672 | **/ | |
5673 | static void ixgbe_service_timer(unsigned long data) | |
5674 | { | |
5675 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
5676 | unsigned long next_event_offset; | |
83c61fa9 | 5677 | bool ready = true; |
7086400d | 5678 | |
6bb78cfb AD |
5679 | /* poll faster when waiting for link */ |
5680 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
5681 | next_event_offset = HZ / 10; | |
5682 | else | |
5683 | next_event_offset = HZ * 2; | |
83c61fa9 | 5684 | |
6bb78cfb | 5685 | #ifdef CONFIG_PCI_IOV |
83c61fa9 GR |
5686 | /* |
5687 | * don't bother with SR-IOV VF DMA hang check if there are | |
5688 | * no VFs or the link is down | |
5689 | */ | |
5690 | if (!adapter->num_vfs || | |
6bb78cfb | 5691 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
83c61fa9 | 5692 | goto normal_timer_service; |
83c61fa9 GR |
5693 | |
5694 | /* If we have VFs allocated then we must check for DMA hangs */ | |
5695 | ixgbe_check_for_bad_vf(adapter); | |
5696 | next_event_offset = HZ / 50; | |
5697 | adapter->timer_event_accumulator++; | |
5698 | ||
6bb78cfb | 5699 | if (adapter->timer_event_accumulator >= 100) |
83c61fa9 | 5700 | adapter->timer_event_accumulator = 0; |
7086400d | 5701 | else |
6bb78cfb | 5702 | ready = false; |
7086400d | 5703 | |
6bb78cfb | 5704 | normal_timer_service: |
83c61fa9 | 5705 | #endif |
7086400d AD |
5706 | /* Reset the timer */ |
5707 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
5708 | ||
83c61fa9 GR |
5709 | if (ready) |
5710 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
5711 | } |
5712 | ||
c83c6cbd AD |
5713 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
5714 | { | |
5715 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
5716 | return; | |
5717 | ||
5718 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
5719 | ||
5720 | /* If we're already down or resetting, just bail */ | |
5721 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
5722 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5723 | return; | |
5724 | ||
5725 | ixgbe_dump(adapter); | |
5726 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
5727 | adapter->tx_timeout_count++; | |
5728 | ||
5729 | ixgbe_reinit_locked(adapter); | |
5730 | } | |
5731 | ||
7086400d AD |
5732 | /** |
5733 | * ixgbe_service_task - manages and runs subtasks | |
5734 | * @work: pointer to work_struct containing our data | |
5735 | **/ | |
5736 | static void ixgbe_service_task(struct work_struct *work) | |
5737 | { | |
5738 | struct ixgbe_adapter *adapter = container_of(work, | |
5739 | struct ixgbe_adapter, | |
5740 | service_task); | |
5741 | ||
c83c6cbd | 5742 | ixgbe_reset_subtask(adapter); |
7086400d AD |
5743 | ixgbe_sfp_detection_subtask(adapter); |
5744 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 5745 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 5746 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 5747 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 5748 | ixgbe_check_hang_subtask(adapter); |
3a6a4eda JK |
5749 | #ifdef CONFIG_IXGBE_PTP |
5750 | ixgbe_ptp_overflow_check(adapter); | |
5751 | #endif | |
7086400d AD |
5752 | |
5753 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
5754 | } |
5755 | ||
fd0db0ed AD |
5756 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
5757 | struct ixgbe_tx_buffer *first, | |
244e27ad | 5758 | u8 *hdr_len) |
897ab156 | 5759 | { |
fd0db0ed | 5760 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5761 | u32 vlan_macip_lens, type_tucmd; |
5762 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 5763 | |
897ab156 AD |
5764 | if (!skb_is_gso(skb)) |
5765 | return 0; | |
9a799d71 | 5766 | |
897ab156 | 5767 | if (skb_header_cloned(skb)) { |
244e27ad | 5768 | int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); |
897ab156 AD |
5769 | if (err) |
5770 | return err; | |
9a799d71 | 5771 | } |
9a799d71 | 5772 | |
897ab156 AD |
5773 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
5774 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
5775 | ||
244e27ad | 5776 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
897ab156 AD |
5777 | struct iphdr *iph = ip_hdr(skb); |
5778 | iph->tot_len = 0; | |
5779 | iph->check = 0; | |
5780 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
5781 | iph->daddr, 0, | |
5782 | IPPROTO_TCP, | |
5783 | 0); | |
5784 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
244e27ad AD |
5785 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5786 | IXGBE_TX_FLAGS_CSUM | | |
5787 | IXGBE_TX_FLAGS_IPV4; | |
897ab156 AD |
5788 | } else if (skb_is_gso_v6(skb)) { |
5789 | ipv6_hdr(skb)->payload_len = 0; | |
5790 | tcp_hdr(skb)->check = | |
5791 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
5792 | &ipv6_hdr(skb)->daddr, | |
5793 | 0, IPPROTO_TCP, 0); | |
244e27ad AD |
5794 | first->tx_flags |= IXGBE_TX_FLAGS_TSO | |
5795 | IXGBE_TX_FLAGS_CSUM; | |
897ab156 AD |
5796 | } |
5797 | ||
091a6246 | 5798 | /* compute header lengths */ |
897ab156 AD |
5799 | l4len = tcp_hdrlen(skb); |
5800 | *hdr_len = skb_transport_offset(skb) + l4len; | |
5801 | ||
091a6246 AD |
5802 | /* update gso size and bytecount with header size */ |
5803 | first->gso_segs = skb_shinfo(skb)->gso_segs; | |
5804 | first->bytecount += (first->gso_segs - 1) * *hdr_len; | |
5805 | ||
897ab156 AD |
5806 | /* mss_l4len_id: use 1 as index for TSO */ |
5807 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
5808 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
5809 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
5810 | ||
5811 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
5812 | vlan_macip_lens = skb_network_header_len(skb); | |
5813 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
244e27ad | 5814 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
897ab156 AD |
5815 | |
5816 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
244e27ad | 5817 | mss_l4len_idx); |
897ab156 AD |
5818 | |
5819 | return 1; | |
5820 | } | |
5821 | ||
244e27ad AD |
5822 | static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring, |
5823 | struct ixgbe_tx_buffer *first) | |
7ca647bd | 5824 | { |
fd0db0ed | 5825 | struct sk_buff *skb = first->skb; |
897ab156 AD |
5826 | u32 vlan_macip_lens = 0; |
5827 | u32 mss_l4len_idx = 0; | |
5828 | u32 type_tucmd = 0; | |
7ca647bd | 5829 | |
897ab156 | 5830 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
244e27ad AD |
5831 | if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
5832 | !(first->tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
5833 | return; | |
897ab156 AD |
5834 | } else { |
5835 | u8 l4_hdr = 0; | |
244e27ad | 5836 | switch (first->protocol) { |
897ab156 AD |
5837 | case __constant_htons(ETH_P_IP): |
5838 | vlan_macip_lens |= skb_network_header_len(skb); | |
5839 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
5840 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 5841 | break; |
897ab156 AD |
5842 | case __constant_htons(ETH_P_IPV6): |
5843 | vlan_macip_lens |= skb_network_header_len(skb); | |
5844 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
5845 | break; | |
5846 | default: | |
5847 | if (unlikely(net_ratelimit())) { | |
5848 | dev_warn(tx_ring->dev, | |
5849 | "partial checksum but proto=%x!\n", | |
244e27ad | 5850 | first->protocol); |
897ab156 | 5851 | } |
7ca647bd JP |
5852 | break; |
5853 | } | |
897ab156 AD |
5854 | |
5855 | switch (l4_hdr) { | |
7ca647bd | 5856 | case IPPROTO_TCP: |
897ab156 AD |
5857 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
5858 | mss_l4len_idx = tcp_hdrlen(skb) << | |
5859 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
5860 | break; |
5861 | case IPPROTO_SCTP: | |
897ab156 AD |
5862 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
5863 | mss_l4len_idx = sizeof(struct sctphdr) << | |
5864 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5865 | break; | |
5866 | case IPPROTO_UDP: | |
5867 | mss_l4len_idx = sizeof(struct udphdr) << | |
5868 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
5869 | break; | |
5870 | default: | |
5871 | if (unlikely(net_ratelimit())) { | |
5872 | dev_warn(tx_ring->dev, | |
5873 | "partial checksum but l4 proto=%x!\n", | |
244e27ad | 5874 | l4_hdr); |
897ab156 | 5875 | } |
7ca647bd JP |
5876 | break; |
5877 | } | |
244e27ad AD |
5878 | |
5879 | /* update TX checksum flag */ | |
5880 | first->tx_flags |= IXGBE_TX_FLAGS_CSUM; | |
7ca647bd JP |
5881 | } |
5882 | ||
244e27ad | 5883 | /* vlan_macip_lens: MACLEN, VLAN tag */ |
897ab156 | 5884 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
244e27ad | 5885 | vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; |
9a799d71 | 5886 | |
897ab156 AD |
5887 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
5888 | type_tucmd, mss_l4len_idx); | |
9a799d71 AK |
5889 | } |
5890 | ||
d3d00239 | 5891 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 5892 | { |
d3d00239 AD |
5893 | /* set type for advanced descriptor with frame checksum insertion */ |
5894 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
5895 | IXGBE_ADVTXD_DCMD_IFCS | | |
5896 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 5897 | |
d3d00239 | 5898 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 5899 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 5900 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 5901 | |
3a6a4eda JK |
5902 | #ifdef CONFIG_IXGBE_PTP |
5903 | if (tx_flags & IXGBE_TX_FLAGS_TSTAMP) | |
5904 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_MAC_TSTAMP); | |
5905 | #endif | |
5906 | ||
d3d00239 AD |
5907 | /* set segmentation enable bits for TSO/FSO */ |
5908 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 5909 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
5910 | #else |
5911 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
5912 | #endif | |
5913 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 5914 | |
d3d00239 AD |
5915 | return cmd_type; |
5916 | } | |
9a799d71 | 5917 | |
729739b7 AD |
5918 | static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc, |
5919 | u32 tx_flags, unsigned int paylen) | |
d3d00239 | 5920 | { |
93f5b3c1 | 5921 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 5922 | |
d3d00239 AD |
5923 | /* enable L4 checksum for TSO and TX checksum offload */ |
5924 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
5925 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 5926 | |
93f5b3c1 AD |
5927 | /* enble IPv4 checksum for TSO */ |
5928 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
5929 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 5930 | |
93f5b3c1 AD |
5931 | /* use index 1 context for TSO/FSO/FCOE */ |
5932 | #ifdef IXGBE_FCOE | |
5933 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
5934 | #else | |
5935 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 5936 | #endif |
93f5b3c1 AD |
5937 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
5938 | ||
7f9643fd AD |
5939 | /* |
5940 | * Check Context must be set if Tx switch is enabled, which it | |
5941 | * always is for case where virtual functions are running | |
5942 | */ | |
93f5b3c1 AD |
5943 | #ifdef IXGBE_FCOE |
5944 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
5945 | #else | |
7f9643fd | 5946 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 5947 | #endif |
7f9643fd AD |
5948 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
5949 | ||
729739b7 | 5950 | tx_desc->read.olinfo_status = olinfo_status; |
d3d00239 | 5951 | } |
44df32c5 | 5952 | |
d3d00239 AD |
5953 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
5954 | IXGBE_TXD_CMD_RS) | |
5955 | ||
5956 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 | 5957 | struct ixgbe_tx_buffer *first, |
d3d00239 AD |
5958 | const u8 hdr_len) |
5959 | { | |
729739b7 | 5960 | dma_addr_t dma; |
fd0db0ed | 5961 | struct sk_buff *skb = first->skb; |
729739b7 | 5962 | struct ixgbe_tx_buffer *tx_buffer; |
d3d00239 | 5963 | union ixgbe_adv_tx_desc *tx_desc; |
729739b7 | 5964 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; |
d3d00239 AD |
5965 | unsigned int data_len = skb->data_len; |
5966 | unsigned int size = skb_headlen(skb); | |
729739b7 | 5967 | unsigned int paylen = skb->len - hdr_len; |
244e27ad | 5968 | u32 tx_flags = first->tx_flags; |
729739b7 | 5969 | __le32 cmd_type; |
d3d00239 | 5970 | u16 i = tx_ring->next_to_use; |
d3d00239 | 5971 | |
729739b7 AD |
5972 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
5973 | ||
5974 | ixgbe_tx_olinfo_status(tx_desc, tx_flags, paylen); | |
5975 | cmd_type = ixgbe_tx_cmd_type(tx_flags); | |
5976 | ||
d3d00239 AD |
5977 | #ifdef IXGBE_FCOE |
5978 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
729739b7 | 5979 | if (data_len < sizeof(struct fcoe_crc_eof)) { |
d3d00239 AD |
5980 | size -= sizeof(struct fcoe_crc_eof) - data_len; |
5981 | data_len = 0; | |
729739b7 AD |
5982 | } else { |
5983 | data_len -= sizeof(struct fcoe_crc_eof); | |
9a799d71 AK |
5984 | } |
5985 | } | |
44df32c5 | 5986 | |
d3d00239 | 5987 | #endif |
729739b7 AD |
5988 | dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); |
5989 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 5990 | goto dma_error; |
8ad494b0 | 5991 | |
729739b7 AD |
5992 | /* record length, and DMA address */ |
5993 | dma_unmap_len_set(first, len, size); | |
5994 | dma_unmap_addr_set(first, dma, dma); | |
9a799d71 | 5995 | |
729739b7 | 5996 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
e5a43549 | 5997 | |
d3d00239 | 5998 | for (;;) { |
729739b7 | 5999 | while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) { |
d3d00239 AD |
6000 | tx_desc->read.cmd_type_len = |
6001 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
e5a43549 | 6002 | |
d3d00239 | 6003 | i++; |
729739b7 | 6004 | tx_desc++; |
d3d00239 | 6005 | if (i == tx_ring->count) { |
e4f74028 | 6006 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6007 | i = 0; |
6008 | } | |
729739b7 AD |
6009 | |
6010 | dma += IXGBE_MAX_DATA_PER_TXD; | |
6011 | size -= IXGBE_MAX_DATA_PER_TXD; | |
6012 | ||
6013 | tx_desc->read.buffer_addr = cpu_to_le64(dma); | |
6014 | tx_desc->read.olinfo_status = 0; | |
d3d00239 | 6015 | } |
e5a43549 | 6016 | |
729739b7 AD |
6017 | if (likely(!data_len)) |
6018 | break; | |
9a799d71 | 6019 | |
f43f313e BG |
6020 | if (unlikely(skb->no_fcs)) |
6021 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 | 6022 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
9a799d71 | 6023 | |
729739b7 AD |
6024 | i++; |
6025 | tx_desc++; | |
6026 | if (i == tx_ring->count) { | |
6027 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); | |
6028 | i = 0; | |
6029 | } | |
9a799d71 | 6030 | |
d3d00239 | 6031 | #ifdef IXGBE_FCOE |
9e903e08 | 6032 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 6033 | #else |
9e903e08 | 6034 | size = skb_frag_size(frag); |
d3d00239 AD |
6035 | #endif |
6036 | data_len -= size; | |
9a799d71 | 6037 | |
729739b7 AD |
6038 | dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size, |
6039 | DMA_TO_DEVICE); | |
6040 | if (dma_mapping_error(tx_ring->dev, dma)) | |
d3d00239 | 6041 | goto dma_error; |
9a799d71 | 6042 | |
729739b7 AD |
6043 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6044 | dma_unmap_len_set(tx_buffer, len, size); | |
6045 | dma_unmap_addr_set(tx_buffer, dma, dma); | |
9a799d71 | 6046 | |
729739b7 AD |
6047 | tx_desc->read.buffer_addr = cpu_to_le64(dma); |
6048 | tx_desc->read.olinfo_status = 0; | |
9a799d71 | 6049 | |
729739b7 AD |
6050 | frag++; |
6051 | } | |
9a799d71 | 6052 | |
729739b7 AD |
6053 | /* write last descriptor with RS and EOP bits */ |
6054 | cmd_type |= cpu_to_le32(size) | cpu_to_le32(IXGBE_TXD_CMD); | |
6055 | tx_desc->read.cmd_type_len = cmd_type; | |
eacd73f7 | 6056 | |
091a6246 | 6057 | netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); |
b2d96e0a | 6058 | |
d3d00239 AD |
6059 | /* set the timestamp */ |
6060 | first->time_stamp = jiffies; | |
9a799d71 AK |
6061 | |
6062 | /* | |
729739b7 AD |
6063 | * Force memory writes to complete before letting h/w know there |
6064 | * are new descriptors to fetch. (Only applicable for weak-ordered | |
6065 | * memory model archs, such as IA-64). | |
6066 | * | |
6067 | * We also need this memory barrier to make certain all of the | |
6068 | * status bits have been updated before next_to_watch is written. | |
9a799d71 AK |
6069 | */ |
6070 | wmb(); | |
6071 | ||
d3d00239 AD |
6072 | /* set next_to_watch value indicating a packet is present */ |
6073 | first->next_to_watch = tx_desc; | |
6074 | ||
729739b7 AD |
6075 | i++; |
6076 | if (i == tx_ring->count) | |
6077 | i = 0; | |
6078 | ||
6079 | tx_ring->next_to_use = i; | |
6080 | ||
d3d00239 | 6081 | /* notify HW of packet */ |
84ea2591 | 6082 | writel(i, tx_ring->tail); |
d3d00239 AD |
6083 | |
6084 | return; | |
6085 | dma_error: | |
729739b7 | 6086 | dev_err(tx_ring->dev, "TX DMA map failed\n"); |
d3d00239 AD |
6087 | |
6088 | /* clear dma mappings for failed tx_buffer_info map */ | |
6089 | for (;;) { | |
729739b7 AD |
6090 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
6091 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer); | |
6092 | if (tx_buffer == first) | |
d3d00239 AD |
6093 | break; |
6094 | if (i == 0) | |
6095 | i = tx_ring->count; | |
6096 | i--; | |
6097 | } | |
6098 | ||
d3d00239 | 6099 | tx_ring->next_to_use = i; |
9a799d71 AK |
6100 | } |
6101 | ||
fd0db0ed | 6102 | static void ixgbe_atr(struct ixgbe_ring *ring, |
244e27ad | 6103 | struct ixgbe_tx_buffer *first) |
69830529 AD |
6104 | { |
6105 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6106 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6107 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6108 | union { | |
6109 | unsigned char *network; | |
6110 | struct iphdr *ipv4; | |
6111 | struct ipv6hdr *ipv6; | |
6112 | } hdr; | |
ee9e0f0b | 6113 | struct tcphdr *th; |
905e4a41 | 6114 | __be16 vlan_id; |
c4cf55e5 | 6115 | |
69830529 AD |
6116 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6117 | if (!q_vector) | |
6118 | return; | |
6119 | ||
6120 | /* do nothing if sampling is disabled */ | |
6121 | if (!ring->atr_sample_rate) | |
d3ead241 | 6122 | return; |
c4cf55e5 | 6123 | |
69830529 | 6124 | ring->atr_count++; |
c4cf55e5 | 6125 | |
69830529 | 6126 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6127 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6128 | |
6129 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
244e27ad | 6130 | if ((first->protocol != __constant_htons(ETH_P_IPV6) || |
69830529 | 6131 | hdr.ipv6->nexthdr != IPPROTO_TCP) && |
244e27ad | 6132 | (first->protocol != __constant_htons(ETH_P_IP) || |
69830529 AD |
6133 | hdr.ipv4->protocol != IPPROTO_TCP)) |
6134 | return; | |
ee9e0f0b | 6135 | |
fd0db0ed | 6136 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6137 | |
66f32a8b AD |
6138 | /* skip this packet since it is invalid or the socket is closing */ |
6139 | if (!th || th->fin) | |
69830529 AD |
6140 | return; |
6141 | ||
6142 | /* sample on all syn packets or once every atr sample count */ | |
6143 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6144 | return; | |
6145 | ||
6146 | /* reset sample count */ | |
6147 | ring->atr_count = 0; | |
6148 | ||
244e27ad | 6149 | vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); |
69830529 AD |
6150 | |
6151 | /* | |
6152 | * src and dst are inverted, think how the receiver sees them | |
6153 | * | |
6154 | * The input is broken into two sections, a non-compressed section | |
6155 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6156 | * is XORed together and stored in the compressed dword. | |
6157 | */ | |
6158 | input.formatted.vlan_id = vlan_id; | |
6159 | ||
6160 | /* | |
6161 | * since src port and flex bytes occupy the same word XOR them together | |
6162 | * and write the value to source port portion of compressed dword | |
6163 | */ | |
244e27ad | 6164 | if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6165 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6166 | else | |
244e27ad | 6167 | common.port.src ^= th->dest ^ first->protocol; |
69830529 AD |
6168 | common.port.dst ^= th->source; |
6169 | ||
244e27ad | 6170 | if (first->protocol == __constant_htons(ETH_P_IP)) { |
69830529 AD |
6171 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; |
6172 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6173 | } else { | |
6174 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6175 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6176 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6177 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6178 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6179 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6180 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6181 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6182 | hdr.ipv6->daddr.s6_addr32[3]; | |
6183 | } | |
c4cf55e5 PWJ |
6184 | |
6185 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6186 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6187 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6188 | } |
6189 | ||
63544e9c | 6190 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6191 | { |
fc77dc3c | 6192 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6193 | /* Herbert's original patch had: |
6194 | * smp_mb__after_netif_stop_queue(); | |
6195 | * but since that doesn't exist yet, just open code it. */ | |
6196 | smp_mb(); | |
6197 | ||
6198 | /* We need to check again in a case another CPU has just | |
6199 | * made room available. */ | |
7d4987de | 6200 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6201 | return -EBUSY; |
6202 | ||
6203 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 6204 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 6205 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
6206 | return 0; |
6207 | } | |
6208 | ||
82d4e46e | 6209 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6210 | { |
7d4987de | 6211 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 6212 | return 0; |
fc77dc3c | 6213 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
6214 | } |
6215 | ||
09a3b1f8 SH |
6216 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
6217 | { | |
6218 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
6219 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
6220 | smp_processor_id(); | |
56075a98 | 6221 | #ifdef IXGBE_FCOE |
6440752c | 6222 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 6223 | |
e5b64635 JF |
6224 | if (((protocol == htons(ETH_P_FCOE)) || |
6225 | (protocol == htons(ETH_P_FIP))) && | |
6226 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
c087663e AD |
6227 | struct ixgbe_ring_feature *f; |
6228 | ||
6229 | f = &adapter->ring_feature[RING_F_FCOE]; | |
6230 | ||
6231 | while (txq >= f->indices) | |
6232 | txq -= f->indices; | |
e4b317e9 | 6233 | txq += adapter->ring_feature[RING_F_FCOE].offset; |
c087663e | 6234 | |
e5b64635 | 6235 | return txq; |
56075a98 JF |
6236 | } |
6237 | #endif | |
6238 | ||
fdd3d631 KK |
6239 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
6240 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
6241 | txq -= dev->real_num_tx_queues; | |
5f715823 | 6242 | return txq; |
fdd3d631 | 6243 | } |
c4cf55e5 | 6244 | |
09a3b1f8 SH |
6245 | return skb_tx_hash(dev, skb); |
6246 | } | |
6247 | ||
fc77dc3c | 6248 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
6249 | struct ixgbe_adapter *adapter, |
6250 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 6251 | { |
d3d00239 | 6252 | struct ixgbe_tx_buffer *first; |
5f715823 | 6253 | int tso; |
d3d00239 | 6254 | u32 tx_flags = 0; |
a535c30e AD |
6255 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
6256 | unsigned short f; | |
6257 | #endif | |
a535c30e | 6258 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 6259 | __be16 protocol = skb->protocol; |
63544e9c | 6260 | u8 hdr_len = 0; |
5e09a105 | 6261 | |
a535c30e AD |
6262 | /* |
6263 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 6264 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
6265 | * + 2 desc gap to keep tail from touching head, |
6266 | * + 1 desc for context descriptor, | |
6267 | * otherwise try next time | |
6268 | */ | |
6269 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
6270 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
6271 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
6272 | #else | |
6273 | count += skb_shinfo(skb)->nr_frags; | |
6274 | #endif | |
6275 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
6276 | tx_ring->tx_stats.tx_busy++; | |
6277 | return NETDEV_TX_BUSY; | |
6278 | } | |
6279 | ||
fd0db0ed AD |
6280 | /* record the location of the first descriptor for this packet */ |
6281 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
6282 | first->skb = skb; | |
091a6246 AD |
6283 | first->bytecount = skb->len; |
6284 | first->gso_segs = 1; | |
fd0db0ed | 6285 | |
66f32a8b | 6286 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 6287 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
6288 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
6289 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
6290 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
6291 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
6292 | struct vlan_hdr *vhdr, _vhdr; | |
6293 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
6294 | if (!vhdr) | |
6295 | goto out_drop; | |
6296 | ||
6297 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
6298 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
6299 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
6300 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
6301 | } | |
6302 | ||
aa7bd467 JK |
6303 | skb_tx_timestamp(skb); |
6304 | ||
3a6a4eda JK |
6305 | #ifdef CONFIG_IXGBE_PTP |
6306 | if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { | |
6307 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
6308 | tx_flags |= IXGBE_TX_FLAGS_TSTAMP; | |
6309 | } | |
6310 | #endif | |
6311 | ||
9e0c5648 AD |
6312 | #ifdef CONFIG_PCI_IOV |
6313 | /* | |
6314 | * Use the l2switch_enable flag - would be false if the DMA | |
6315 | * Tx switch had been disabled. | |
6316 | */ | |
6317 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6318 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
6319 | ||
6320 | #endif | |
32701dc2 | 6321 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 6322 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
6323 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
6324 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 6325 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
6326 | tx_flags |= (skb->priority & 0x7) << |
6327 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
6328 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
6329 | struct vlan_ethhdr *vhdr; | |
6330 | if (skb_header_cloned(skb) && | |
6331 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
6332 | goto out_drop; | |
6333 | vhdr = (struct vlan_ethhdr *)skb->data; | |
6334 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
6335 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6336 | } else { | |
6337 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 6338 | } |
9a799d71 | 6339 | } |
eacd73f7 | 6340 | |
244e27ad AD |
6341 | /* record initial flags and protocol */ |
6342 | first->tx_flags = tx_flags; | |
6343 | first->protocol = protocol; | |
6344 | ||
eacd73f7 | 6345 | #ifdef IXGBE_FCOE |
66f32a8b AD |
6346 | /* setup tx offload for FCoE */ |
6347 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
6348 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
244e27ad | 6349 | tso = ixgbe_fso(tx_ring, first, &hdr_len); |
897ab156 AD |
6350 | if (tso < 0) |
6351 | goto out_drop; | |
9a799d71 | 6352 | |
66f32a8b | 6353 | goto xmit_fcoe; |
eacd73f7 | 6354 | } |
9a799d71 | 6355 | |
66f32a8b | 6356 | #endif /* IXGBE_FCOE */ |
244e27ad | 6357 | tso = ixgbe_tso(tx_ring, first, &hdr_len); |
66f32a8b | 6358 | if (tso < 0) |
897ab156 | 6359 | goto out_drop; |
244e27ad AD |
6360 | else if (!tso) |
6361 | ixgbe_tx_csum(tx_ring, first); | |
66f32a8b AD |
6362 | |
6363 | /* add the ATR filter if ATR is on */ | |
6364 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
244e27ad | 6365 | ixgbe_atr(tx_ring, first); |
66f32a8b AD |
6366 | |
6367 | #ifdef IXGBE_FCOE | |
6368 | xmit_fcoe: | |
6369 | #endif /* IXGBE_FCOE */ | |
244e27ad | 6370 | ixgbe_tx_map(tx_ring, first, hdr_len); |
d3d00239 AD |
6371 | |
6372 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
6373 | |
6374 | return NETDEV_TX_OK; | |
897ab156 AD |
6375 | |
6376 | out_drop: | |
fd0db0ed AD |
6377 | dev_kfree_skb_any(first->skb); |
6378 | first->skb = NULL; | |
6379 | ||
897ab156 | 6380 | return NETDEV_TX_OK; |
9a799d71 AK |
6381 | } |
6382 | ||
a50c29dd AD |
6383 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
6384 | struct net_device *netdev) | |
84418e3b AD |
6385 | { |
6386 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6387 | struct ixgbe_ring *tx_ring; | |
6388 | ||
a50c29dd AD |
6389 | /* |
6390 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
6391 | * in order to meet this minimum size requirement. | |
6392 | */ | |
f73332fc SH |
6393 | if (unlikely(skb->len < 17)) { |
6394 | if (skb_pad(skb, 17 - skb->len)) | |
a50c29dd AD |
6395 | return NETDEV_TX_OK; |
6396 | skb->len = 17; | |
6397 | } | |
6398 | ||
84418e3b | 6399 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 6400 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
6401 | } |
6402 | ||
9a799d71 AK |
6403 | /** |
6404 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
6405 | * @netdev: network interface device structure | |
6406 | * @p: pointer to an address structure | |
6407 | * | |
6408 | * Returns 0 on success, negative on failure | |
6409 | **/ | |
6410 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
6411 | { | |
6412 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 6413 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
6414 | struct sockaddr *addr = p; |
6415 | ||
6416 | if (!is_valid_ether_addr(addr->sa_data)) | |
6417 | return -EADDRNOTAVAIL; | |
6418 | ||
6419 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 6420 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 6421 | |
1cdd1ec8 GR |
6422 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
6423 | IXGBE_RAH_AV); | |
9a799d71 AK |
6424 | |
6425 | return 0; | |
6426 | } | |
6427 | ||
6b73e10d BH |
6428 | static int |
6429 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
6430 | { | |
6431 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6432 | struct ixgbe_hw *hw = &adapter->hw; | |
6433 | u16 value; | |
6434 | int rc; | |
6435 | ||
6436 | if (prtad != hw->phy.mdio.prtad) | |
6437 | return -EINVAL; | |
6438 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
6439 | if (!rc) | |
6440 | rc = value; | |
6441 | return rc; | |
6442 | } | |
6443 | ||
6444 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
6445 | u16 addr, u16 value) | |
6446 | { | |
6447 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6448 | struct ixgbe_hw *hw = &adapter->hw; | |
6449 | ||
6450 | if (prtad != hw->phy.mdio.prtad) | |
6451 | return -EINVAL; | |
6452 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
6453 | } | |
6454 | ||
6455 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
6456 | { | |
6457 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6458 | ||
3a6a4eda JK |
6459 | switch (cmd) { |
6460 | #ifdef CONFIG_IXGBE_PTP | |
6461 | case SIOCSHWTSTAMP: | |
6462 | return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd); | |
6463 | #endif | |
6464 | default: | |
6465 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
6466 | } | |
6b73e10d BH |
6467 | } |
6468 | ||
0365e6e4 PW |
6469 | /** |
6470 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 6471 | * netdev->dev_addrs |
0365e6e4 PW |
6472 | * @netdev: network interface device structure |
6473 | * | |
6474 | * Returns non-zero on failure | |
6475 | **/ | |
6476 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
6477 | { | |
6478 | int err = 0; | |
6479 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6480 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6481 | ||
6482 | if (is_valid_ether_addr(mac->san_addr)) { | |
6483 | rtnl_lock(); | |
6484 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6485 | rtnl_unlock(); | |
6486 | } | |
6487 | return err; | |
6488 | } | |
6489 | ||
6490 | /** | |
6491 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 6492 | * netdev->dev_addrs |
0365e6e4 PW |
6493 | * @netdev: network interface device structure |
6494 | * | |
6495 | * Returns non-zero on failure | |
6496 | **/ | |
6497 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
6498 | { | |
6499 | int err = 0; | |
6500 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6501 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
6502 | ||
6503 | if (is_valid_ether_addr(mac->san_addr)) { | |
6504 | rtnl_lock(); | |
6505 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
6506 | rtnl_unlock(); | |
6507 | } | |
6508 | return err; | |
6509 | } | |
6510 | ||
9a799d71 AK |
6511 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6512 | /* | |
6513 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
6514 | * without having to re-enable interrupts. It's not called while | |
6515 | * the interrupt routine is executing. | |
6516 | */ | |
6517 | static void ixgbe_netpoll(struct net_device *netdev) | |
6518 | { | |
6519 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 6520 | int i; |
9a799d71 | 6521 | |
1a647bd2 AD |
6522 | /* if interface is down do nothing */ |
6523 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
6524 | return; | |
6525 | ||
9a799d71 | 6526 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 | 6527 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
49c7ffbe AD |
6528 | for (i = 0; i < adapter->num_q_vectors; i++) |
6529 | ixgbe_msix_clean_rings(0, adapter->q_vector[i]); | |
8f9a7167 PWJ |
6530 | } else { |
6531 | ixgbe_intr(adapter->pdev->irq, netdev); | |
6532 | } | |
9a799d71 | 6533 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 | 6534 | } |
9a799d71 | 6535 | |
581330ba | 6536 | #endif |
de1036b1 ED |
6537 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
6538 | struct rtnl_link_stats64 *stats) | |
6539 | { | |
6540 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6541 | int i; | |
6542 | ||
1a51502b | 6543 | rcu_read_lock(); |
de1036b1 | 6544 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 6545 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
6546 | u64 bytes, packets; |
6547 | unsigned int start; | |
6548 | ||
1a51502b ED |
6549 | if (ring) { |
6550 | do { | |
6551 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6552 | packets = ring->stats.packets; | |
6553 | bytes = ring->stats.bytes; | |
6554 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6555 | stats->rx_packets += packets; | |
6556 | stats->rx_bytes += bytes; | |
6557 | } | |
de1036b1 | 6558 | } |
1ac9ad13 ED |
6559 | |
6560 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
6561 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
6562 | u64 bytes, packets; | |
6563 | unsigned int start; | |
6564 | ||
6565 | if (ring) { | |
6566 | do { | |
6567 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
6568 | packets = ring->stats.packets; | |
6569 | bytes = ring->stats.bytes; | |
6570 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
6571 | stats->tx_packets += packets; | |
6572 | stats->tx_bytes += bytes; | |
6573 | } | |
6574 | } | |
1a51502b | 6575 | rcu_read_unlock(); |
de1036b1 ED |
6576 | /* following stats updated by ixgbe_watchdog_task() */ |
6577 | stats->multicast = netdev->stats.multicast; | |
6578 | stats->rx_errors = netdev->stats.rx_errors; | |
6579 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
6580 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
6581 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
6582 | return stats; | |
6583 | } | |
6584 | ||
8af3c33f | 6585 | #ifdef CONFIG_IXGBE_DCB |
49ce9c2c BH |
6586 | /** |
6587 | * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. | |
6588 | * @adapter: pointer to ixgbe_adapter | |
8b1c0b24 JF |
6589 | * @tc: number of traffic classes currently enabled |
6590 | * | |
6591 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
6592 | * 802.1Q priority maps to a packet buffer that exists. | |
6593 | */ | |
6594 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
6595 | { | |
6596 | struct ixgbe_hw *hw = &adapter->hw; | |
6597 | u32 reg, rsave; | |
6598 | int i; | |
6599 | ||
6600 | /* 82598 have a static priority to TC mapping that can not | |
6601 | * be changed so no validation is needed. | |
6602 | */ | |
6603 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6604 | return; | |
6605 | ||
6606 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
6607 | rsave = reg; | |
6608 | ||
6609 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
6610 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
6611 | ||
6612 | /* If up2tc is out of bounds default to zero */ | |
6613 | if (up2tc > tc) | |
6614 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
6615 | } | |
6616 | ||
6617 | if (reg != rsave) | |
6618 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
6619 | ||
6620 | return; | |
6621 | } | |
6622 | ||
02debdc9 AD |
6623 | /** |
6624 | * ixgbe_set_prio_tc_map - Configure netdev prio tc map | |
6625 | * @adapter: Pointer to adapter struct | |
6626 | * | |
6627 | * Populate the netdev user priority to tc map | |
6628 | */ | |
6629 | static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter) | |
6630 | { | |
6631 | struct net_device *dev = adapter->netdev; | |
6632 | struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg; | |
6633 | struct ieee_ets *ets = adapter->ixgbe_ieee_ets; | |
6634 | u8 prio; | |
6635 | ||
6636 | for (prio = 0; prio < MAX_USER_PRIORITY; prio++) { | |
6637 | u8 tc = 0; | |
6638 | ||
6639 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) | |
6640 | tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio); | |
6641 | else if (ets) | |
6642 | tc = ets->prio_tc[prio]; | |
6643 | ||
6644 | netdev_set_prio_tc_map(dev, prio, tc); | |
6645 | } | |
6646 | } | |
6647 | ||
49ce9c2c BH |
6648 | /** |
6649 | * ixgbe_setup_tc - configure net_device for multiple traffic classes | |
8b1c0b24 JF |
6650 | * |
6651 | * @netdev: net device to configure | |
6652 | * @tc: number of traffic classes to enable | |
6653 | */ | |
6654 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
6655 | { | |
8b1c0b24 JF |
6656 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
6657 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 6658 | |
e7589eab JF |
6659 | /* Multiple traffic classes requires multiple queues */ |
6660 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
6661 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
6662 | return -EINVAL; | |
6663 | } | |
8b1c0b24 | 6664 | |
d4e41649 AD |
6665 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
6666 | e_err(drv, "Enable failed, SR-IOV enabled\n"); | |
6667 | return -EINVAL; | |
6668 | } | |
6669 | ||
8b1c0b24 | 6670 | /* Hardware supports up to 8 traffic classes */ |
4de2a022 | 6671 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
581330ba AD |
6672 | (hw->mac.type == ixgbe_mac_82598EB && |
6673 | tc < MAX_TRAFFIC_CLASS)) | |
8b1c0b24 JF |
6674 | return -EINVAL; |
6675 | ||
6676 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 6677 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
6678 | * hardware is not flexible enough to do this dynamically. |
6679 | */ | |
6680 | if (netif_running(dev)) | |
6681 | ixgbe_close(dev); | |
6682 | ixgbe_clear_interrupt_scheme(adapter); | |
6683 | ||
e7589eab | 6684 | if (tc) { |
8b1c0b24 | 6685 | netdev_set_num_tc(dev, tc); |
02debdc9 AD |
6686 | ixgbe_set_prio_tc_map(adapter); |
6687 | ||
e7589eab JF |
6688 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; |
6689 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6690 | ||
943561d3 AD |
6691 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) { |
6692 | adapter->last_lfc_mode = adapter->hw.fc.requested_mode; | |
e7589eab | 6693 | adapter->hw.fc.requested_mode = ixgbe_fc_none; |
943561d3 | 6694 | } |
e7589eab | 6695 | } else { |
8b1c0b24 | 6696 | netdev_reset_tc(dev); |
02debdc9 | 6697 | |
943561d3 AD |
6698 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) |
6699 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; | |
e7589eab JF |
6700 | |
6701 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
6702 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6703 | ||
6704 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
6705 | adapter->dcb_cfg.pfc_mode_enable = false; | |
6706 | } | |
6707 | ||
8b1c0b24 JF |
6708 | ixgbe_init_interrupt_scheme(adapter); |
6709 | ixgbe_validate_rtr(adapter, tc); | |
6710 | if (netif_running(dev)) | |
6711 | ixgbe_open(dev); | |
6712 | ||
6713 | return 0; | |
6714 | } | |
de1036b1 | 6715 | |
8af3c33f | 6716 | #endif /* CONFIG_IXGBE_DCB */ |
082757af DS |
6717 | void ixgbe_do_reset(struct net_device *netdev) |
6718 | { | |
6719 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6720 | ||
6721 | if (netif_running(netdev)) | |
6722 | ixgbe_reinit_locked(adapter); | |
6723 | else | |
6724 | ixgbe_reset(adapter); | |
6725 | } | |
6726 | ||
c8f44aff | 6727 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
567d2de2 | 6728 | netdev_features_t features) |
082757af DS |
6729 | { |
6730 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
6731 | ||
082757af DS |
6732 | /* return error if RXHASH is being enabled when RSS is not supported */ |
6733 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
567d2de2 | 6734 | features &= ~NETIF_F_RXHASH; |
082757af DS |
6735 | |
6736 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
567d2de2 AD |
6737 | if (!(features & NETIF_F_RXCSUM)) |
6738 | features &= ~NETIF_F_LRO; | |
082757af | 6739 | |
567d2de2 AD |
6740 | /* Turn off LRO if not RSC capable */ |
6741 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) | |
6742 | features &= ~NETIF_F_LRO; | |
8e2813f5 | 6743 | |
567d2de2 | 6744 | return features; |
082757af DS |
6745 | } |
6746 | ||
c8f44aff | 6747 | static int ixgbe_set_features(struct net_device *netdev, |
567d2de2 | 6748 | netdev_features_t features) |
082757af DS |
6749 | { |
6750 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
567d2de2 | 6751 | netdev_features_t changed = netdev->features ^ features; |
082757af DS |
6752 | bool need_reset = false; |
6753 | ||
082757af | 6754 | /* Make sure RSC matches LRO, reset if change */ |
567d2de2 AD |
6755 | if (!(features & NETIF_F_LRO)) { |
6756 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) | |
082757af | 6757 | need_reset = true; |
567d2de2 AD |
6758 | adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED; |
6759 | } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) && | |
6760 | !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
6761 | if (adapter->rx_itr_setting == 1 || | |
6762 | adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) { | |
6763 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
6764 | need_reset = true; | |
6765 | } else if ((changed ^ features) & NETIF_F_LRO) { | |
6766 | e_info(probe, "rx-usecs set too low, " | |
6767 | "disabling RSC\n"); | |
082757af DS |
6768 | } |
6769 | } | |
6770 | ||
6771 | /* | |
6772 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
6773 | * the state changed, we need to reset. | |
6774 | */ | |
567d2de2 AD |
6775 | if (!(features & NETIF_F_NTUPLE)) { |
6776 | if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { | |
6777 | /* turn off Flow Director, set ATR and reset */ | |
6778 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
6779 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
6780 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
082757af DS |
6781 | need_reset = true; |
6782 | } | |
082757af | 6783 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; |
567d2de2 AD |
6784 | } else if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { |
6785 | /* turn off ATR, enable perfect filters and reset */ | |
6786 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
6787 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
082757af DS |
6788 | need_reset = true; |
6789 | } | |
6790 | ||
146d4cc9 JF |
6791 | if (features & NETIF_F_HW_VLAN_RX) |
6792 | ixgbe_vlan_strip_enable(adapter); | |
6793 | else | |
6794 | ixgbe_vlan_strip_disable(adapter); | |
6795 | ||
3f2d1c0f BG |
6796 | if (changed & NETIF_F_RXALL) |
6797 | need_reset = true; | |
6798 | ||
567d2de2 | 6799 | netdev->features = features; |
082757af DS |
6800 | if (need_reset) |
6801 | ixgbe_do_reset(netdev); | |
6802 | ||
6803 | return 0; | |
082757af DS |
6804 | } |
6805 | ||
0f4b0add JF |
6806 | static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, |
6807 | struct net_device *dev, | |
6808 | unsigned char *addr, | |
6809 | u16 flags) | |
6810 | { | |
6811 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6812 | int err = -EOPNOTSUPP; | |
6813 | ||
6814 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6815 | pr_info("%s: FDB only supports static addresses\n", | |
6816 | ixgbe_driver_name); | |
6817 | return -EINVAL; | |
6818 | } | |
6819 | ||
6820 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6821 | if (is_unicast_ether_addr(addr)) | |
6822 | err = dev_uc_add_excl(dev, addr); | |
6823 | else if (is_multicast_ether_addr(addr)) | |
6824 | err = dev_mc_add_excl(dev, addr); | |
6825 | else | |
6826 | err = -EINVAL; | |
6827 | } | |
6828 | ||
6829 | /* Only return duplicate errors if NLM_F_EXCL is set */ | |
6830 | if (err == -EEXIST && !(flags & NLM_F_EXCL)) | |
6831 | err = 0; | |
6832 | ||
6833 | return err; | |
6834 | } | |
6835 | ||
6836 | static int ixgbe_ndo_fdb_del(struct ndmsg *ndm, | |
6837 | struct net_device *dev, | |
6838 | unsigned char *addr) | |
6839 | { | |
6840 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6841 | int err = -EOPNOTSUPP; | |
6842 | ||
6843 | if (ndm->ndm_state & NUD_PERMANENT) { | |
6844 | pr_info("%s: FDB only supports static addresses\n", | |
6845 | ixgbe_driver_name); | |
6846 | return -EINVAL; | |
6847 | } | |
6848 | ||
6849 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
6850 | if (is_unicast_ether_addr(addr)) | |
6851 | err = dev_uc_del(dev, addr); | |
6852 | else if (is_multicast_ether_addr(addr)) | |
6853 | err = dev_mc_del(dev, addr); | |
6854 | else | |
6855 | err = -EINVAL; | |
6856 | } | |
6857 | ||
6858 | return err; | |
6859 | } | |
6860 | ||
6861 | static int ixgbe_ndo_fdb_dump(struct sk_buff *skb, | |
6862 | struct netlink_callback *cb, | |
6863 | struct net_device *dev, | |
6864 | int idx) | |
6865 | { | |
6866 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6867 | ||
6868 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
6869 | idx = ndo_dflt_fdb_dump(skb, cb, dev, idx); | |
6870 | ||
6871 | return idx; | |
6872 | } | |
6873 | ||
0edc3527 | 6874 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 6875 | .ndo_open = ixgbe_open, |
0edc3527 | 6876 | .ndo_stop = ixgbe_close, |
00829823 | 6877 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 6878 | .ndo_select_queue = ixgbe_select_queue, |
581330ba | 6879 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
6880 | .ndo_validate_addr = eth_validate_addr, |
6881 | .ndo_set_mac_address = ixgbe_set_mac, | |
6882 | .ndo_change_mtu = ixgbe_change_mtu, | |
6883 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
6884 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
6885 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 6886 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
6887 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
6888 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
6889 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
581330ba | 6890 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 6891 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 6892 | .ndo_get_stats64 = ixgbe_get_stats64, |
8af3c33f | 6893 | #ifdef CONFIG_IXGBE_DCB |
24095aa3 | 6894 | .ndo_setup_tc = ixgbe_setup_tc, |
8af3c33f | 6895 | #endif |
0edc3527 SH |
6896 | #ifdef CONFIG_NET_POLL_CONTROLLER |
6897 | .ndo_poll_controller = ixgbe_netpoll, | |
6898 | #endif | |
332d4a7d YZ |
6899 | #ifdef IXGBE_FCOE |
6900 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 6901 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 6902 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
6903 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
6904 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 6905 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 6906 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 6907 | #endif /* IXGBE_FCOE */ |
082757af DS |
6908 | .ndo_set_features = ixgbe_set_features, |
6909 | .ndo_fix_features = ixgbe_fix_features, | |
0f4b0add JF |
6910 | .ndo_fdb_add = ixgbe_ndo_fdb_add, |
6911 | .ndo_fdb_del = ixgbe_ndo_fdb_del, | |
6912 | .ndo_fdb_dump = ixgbe_ndo_fdb_dump, | |
0edc3527 SH |
6913 | }; |
6914 | ||
1cdd1ec8 | 6915 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
567d2de2 | 6916 | const struct ixgbe_info *ii) |
1cdd1ec8 GR |
6917 | { |
6918 | #ifdef CONFIG_PCI_IOV | |
6919 | struct ixgbe_hw *hw = &adapter->hw; | |
1cdd1ec8 | 6920 | |
c6bda30a | 6921 | if (hw->mac.type == ixgbe_mac_82598EB) |
1cdd1ec8 GR |
6922 | return; |
6923 | ||
6924 | /* The 82599 supports up to 64 VFs per physical function | |
6925 | * but this implementation limits allocation to 63 so that | |
6926 | * basic networking resources are still available to the | |
6b42a9c5 GR |
6927 | * physical function. If the user requests greater thn |
6928 | * 63 VFs then it is an error - reset to default of zero. | |
1cdd1ec8 | 6929 | */ |
6b42a9c5 | 6930 | adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs; |
c6bda30a | 6931 | ixgbe_enable_sriov(adapter, ii); |
1cdd1ec8 GR |
6932 | #endif /* CONFIG_PCI_IOV */ |
6933 | } | |
6934 | ||
8e2813f5 JK |
6935 | /** |
6936 | * ixgbe_wol_supported - Check whether device supports WoL | |
6937 | * @hw: hw specific details | |
6938 | * @device_id: the device ID | |
6939 | * @subdev_id: the subsystem device ID | |
6940 | * | |
6941 | * This function is used by probe and ethtool to determine | |
6942 | * which devices have WoL support | |
6943 | * | |
6944 | **/ | |
6945 | int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id, | |
6946 | u16 subdevice_id) | |
6947 | { | |
6948 | struct ixgbe_hw *hw = &adapter->hw; | |
6949 | u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
6950 | int is_wol_supported = 0; | |
6951 | ||
6952 | switch (device_id) { | |
6953 | case IXGBE_DEV_ID_82599_SFP: | |
6954 | /* Only these subdevices could supports WOL */ | |
6955 | switch (subdevice_id) { | |
6956 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
6957 | /* only support first port */ | |
6958 | if (hw->bus.func != 0) | |
6959 | break; | |
6960 | case IXGBE_SUBDEV_ID_82599_SFP: | |
6961 | is_wol_supported = 1; | |
6962 | break; | |
6963 | } | |
6964 | break; | |
6965 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: | |
6966 | /* All except this subdevice support WOL */ | |
6967 | if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) | |
6968 | is_wol_supported = 1; | |
6969 | break; | |
6970 | case IXGBE_DEV_ID_82599_KX4: | |
6971 | is_wol_supported = 1; | |
6972 | break; | |
6973 | case IXGBE_DEV_ID_X540T: | |
6974 | /* check eeprom to see if enabled wol */ | |
6975 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
6976 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
6977 | (hw->bus.func == 0))) { | |
6978 | is_wol_supported = 1; | |
6979 | } | |
6980 | break; | |
6981 | } | |
6982 | ||
6983 | return is_wol_supported; | |
6984 | } | |
6985 | ||
9a799d71 AK |
6986 | /** |
6987 | * ixgbe_probe - Device Initialization Routine | |
6988 | * @pdev: PCI device information struct | |
6989 | * @ent: entry in ixgbe_pci_tbl | |
6990 | * | |
6991 | * Returns 0 on success, negative on failure | |
6992 | * | |
6993 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
6994 | * The OS initialization, configuring of the adapter private structure, | |
6995 | * and a hardware reset occur. | |
6996 | **/ | |
6997 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 6998 | const struct pci_device_id *ent) |
9a799d71 AK |
6999 | { |
7000 | struct net_device *netdev; | |
7001 | struct ixgbe_adapter *adapter = NULL; | |
7002 | struct ixgbe_hw *hw; | |
7003 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7004 | static int cards_found; |
7005 | int i, err, pci_using_dac; | |
289700db | 7006 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7007 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7008 | #ifdef IXGBE_FCOE |
7009 | u16 device_caps; | |
7010 | #endif | |
289700db | 7011 | u32 eec; |
9a799d71 | 7012 | |
bded64a7 AG |
7013 | /* Catch broken hardware that put the wrong VF device ID in |
7014 | * the PCIe SR-IOV capability. | |
7015 | */ | |
7016 | if (pdev->is_virtfn) { | |
7017 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7018 | pci_name(pdev), pdev->vendor, pdev->device); | |
7019 | return -EINVAL; | |
7020 | } | |
7021 | ||
9ce77666 | 7022 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7023 | if (err) |
7024 | return err; | |
7025 | ||
1b507730 NN |
7026 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7027 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7028 | pci_using_dac = 1; |
7029 | } else { | |
1b507730 | 7030 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7031 | if (err) { |
1b507730 NN |
7032 | err = dma_set_coherent_mask(&pdev->dev, |
7033 | DMA_BIT_MASK(32)); | |
9a799d71 | 7034 | if (err) { |
b8bc0421 DC |
7035 | dev_err(&pdev->dev, |
7036 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7037 | goto err_dma; |
7038 | } | |
7039 | } | |
7040 | pci_using_dac = 0; | |
7041 | } | |
7042 | ||
9ce77666 | 7043 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7044 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7045 | if (err) { |
b8bc0421 DC |
7046 | dev_err(&pdev->dev, |
7047 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7048 | goto err_pci_reg; |
7049 | } | |
7050 | ||
19d5afd4 | 7051 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7052 | |
9a799d71 | 7053 | pci_set_master(pdev); |
fb3b27bc | 7054 | pci_save_state(pdev); |
9a799d71 | 7055 | |
e901acd6 JF |
7056 | #ifdef CONFIG_IXGBE_DCB |
7057 | indices *= MAX_TRAFFIC_CLASS; | |
7058 | #endif | |
7059 | ||
c85a2618 | 7060 | if (ii->mac == ixgbe_mac_82598EB) |
d411a936 AD |
7061 | #ifdef CONFIG_IXGBE_DCB |
7062 | indices = min_t(unsigned int, indices, MAX_TRAFFIC_CLASS * 4); | |
7063 | #else | |
c85a2618 | 7064 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); |
d411a936 | 7065 | #endif |
c85a2618 JF |
7066 | else |
7067 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7068 | ||
e901acd6 | 7069 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7070 | indices += min_t(unsigned int, num_possible_cpus(), |
7071 | IXGBE_MAX_FCOE_INDICES); | |
7072 | #endif | |
c85a2618 | 7073 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7074 | if (!netdev) { |
7075 | err = -ENOMEM; | |
7076 | goto err_alloc_etherdev; | |
7077 | } | |
7078 | ||
9a799d71 AK |
7079 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7080 | ||
9a799d71 | 7081 | adapter = netdev_priv(netdev); |
c60fbb00 | 7082 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7083 | |
7084 | adapter->netdev = netdev; | |
7085 | adapter->pdev = pdev; | |
7086 | hw = &adapter->hw; | |
7087 | hw->back = adapter; | |
b3f4d599 | 7088 | adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); |
9a799d71 | 7089 | |
05857980 | 7090 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7091 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7092 | if (!hw->hw_addr) { |
7093 | err = -EIO; | |
7094 | goto err_ioremap; | |
7095 | } | |
7096 | ||
7097 | for (i = 1; i <= 5; i++) { | |
7098 | if (pci_resource_len(pdev, i) == 0) | |
7099 | continue; | |
7100 | } | |
7101 | ||
0edc3527 | 7102 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7103 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7104 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7105 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7106 | |
9a799d71 AK |
7107 | adapter->bd_number = cards_found; |
7108 | ||
9a799d71 AK |
7109 | /* Setup hw api */ |
7110 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7111 | hw->mac.type = ii->mac; |
9a799d71 | 7112 | |
c44ade9e JB |
7113 | /* EEPROM */ |
7114 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7115 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7116 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7117 | if (!(eec & (1 << 8))) | |
7118 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7119 | ||
7120 | /* PHY */ | |
7121 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7122 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7123 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7124 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7125 | hw->phy.mdio.mmds = 0; | |
7126 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7127 | hw->phy.mdio.dev = netdev; | |
7128 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7129 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7130 | |
8ca783ab | 7131 | ii->get_invariants(hw); |
9a799d71 AK |
7132 | |
7133 | /* setup the private structure */ | |
7134 | err = ixgbe_sw_init(adapter); | |
7135 | if (err) | |
7136 | goto err_sw_init; | |
7137 | ||
e86bff0e | 7138 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7139 | switch (adapter->hw.mac.type) { |
7140 | case ixgbe_mac_82599EB: | |
7141 | case ixgbe_mac_X540: | |
e86bff0e | 7142 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7143 | break; |
7144 | default: | |
7145 | break; | |
7146 | } | |
e86bff0e | 7147 | |
bf069c97 DS |
7148 | /* |
7149 | * If there is a fan on this device and it has failed log the | |
7150 | * failure. | |
7151 | */ | |
7152 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7153 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7154 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7155 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7156 | } |
7157 | ||
8ef78adc PWJ |
7158 | if (allow_unsupported_sfp) |
7159 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7160 | ||
c44ade9e | 7161 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7162 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7163 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7164 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7165 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7166 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7167 | err = 0; |
7168 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7169 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7170 | "module type was detected.\n"); |
7171 | e_dev_err("Reload the driver after installing a supported " | |
7172 | "module.\n"); | |
04f165ef PW |
7173 | goto err_sw_init; |
7174 | } else if (err) { | |
849c4542 | 7175 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7176 | goto err_sw_init; |
7177 | } | |
7178 | ||
1cdd1ec8 GR |
7179 | ixgbe_probe_vf(adapter, ii); |
7180 | ||
396e799c | 7181 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7182 | NETIF_F_IP_CSUM | |
082757af | 7183 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7184 | NETIF_F_HW_VLAN_TX | |
7185 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7186 | NETIF_F_HW_VLAN_FILTER | |
7187 | NETIF_F_TSO | | |
7188 | NETIF_F_TSO6 | | |
082757af DS |
7189 | NETIF_F_RXHASH | |
7190 | NETIF_F_RXCSUM; | |
9a799d71 | 7191 | |
082757af | 7192 | netdev->hw_features = netdev->features; |
ad31c402 | 7193 | |
58be7666 DS |
7194 | switch (adapter->hw.mac.type) { |
7195 | case ixgbe_mac_82599EB: | |
7196 | case ixgbe_mac_X540: | |
45a5ead0 | 7197 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7198 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7199 | NETIF_F_NTUPLE; | |
58be7666 DS |
7200 | break; |
7201 | default: | |
7202 | break; | |
7203 | } | |
45a5ead0 | 7204 | |
3f2d1c0f BG |
7205 | netdev->hw_features |= NETIF_F_RXALL; |
7206 | ||
ad31c402 JK |
7207 | netdev->vlan_features |= NETIF_F_TSO; |
7208 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7209 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7210 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7211 | netdev->vlan_features |= NETIF_F_SG; |
7212 | ||
01789349 | 7213 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7214 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7215 | |
1cdd1ec8 GR |
7216 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7217 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7218 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7219 | |
7a6b6f51 | 7220 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7221 | netdev->dcbnl_ops = &dcbnl_ops; |
7222 | #endif | |
7223 | ||
eacd73f7 | 7224 | #ifdef IXGBE_FCOE |
0d551589 | 7225 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7226 | if (hw->mac.ops.get_device_caps) { |
7227 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7228 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7229 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7230 | } |
7231 | } | |
5e09d7f6 YZ |
7232 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7233 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7234 | netdev->vlan_features |= NETIF_F_FSO; | |
7235 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7236 | } | |
eacd73f7 | 7237 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7238 | if (pci_using_dac) { |
9a799d71 | 7239 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7240 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7241 | } | |
9a799d71 | 7242 | |
082757af DS |
7243 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7244 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7245 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7246 | netdev->features |= NETIF_F_LRO; |
7247 | ||
9a799d71 | 7248 | /* make sure the EEPROM is good */ |
c44ade9e | 7249 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7250 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 | 7251 | err = -EIO; |
35937c05 | 7252 | goto err_sw_init; |
9a799d71 AK |
7253 | } |
7254 | ||
7255 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7256 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7257 | ||
c44ade9e | 7258 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7259 | e_dev_err("invalid MAC address\n"); |
9a799d71 | 7260 | err = -EIO; |
35937c05 | 7261 | goto err_sw_init; |
9a799d71 AK |
7262 | } |
7263 | ||
7086400d | 7264 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
581330ba | 7265 | (unsigned long) adapter); |
9a799d71 | 7266 | |
7086400d AD |
7267 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7268 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7269 | |
021230d4 AV |
7270 | err = ixgbe_init_interrupt_scheme(adapter); |
7271 | if (err) | |
7272 | goto err_sw_init; | |
9a799d71 | 7273 | |
082757af DS |
7274 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7275 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7276 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7277 | } |
67a74ee2 | 7278 | |
8e2813f5 | 7279 | /* WOL not supported for all devices */ |
c23f5b6b | 7280 | adapter->wol = 0; |
8e2813f5 JK |
7281 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); |
7282 | if (ixgbe_wol_supported(adapter, pdev->device, pdev->subsystem_device)) | |
9417c464 | 7283 | adapter->wol = IXGBE_WUFC_MAG; |
c23f5b6b | 7284 | |
e8e26350 PW |
7285 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7286 | ||
3a6a4eda JK |
7287 | #ifdef CONFIG_IXGBE_PTP |
7288 | ixgbe_ptp_init(adapter); | |
7289 | #endif /* CONFIG_IXGBE_PTP*/ | |
7290 | ||
15e5209f ET |
7291 | /* save off EEPROM version number */ |
7292 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7293 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7294 | ||
04f165ef PW |
7295 | /* pick up the PCI bus settings for reporting later */ |
7296 | hw->mac.ops.get_bus_info(hw); | |
7297 | ||
9a799d71 | 7298 | /* print bus type/speed/width info */ |
849c4542 | 7299 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7300 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7301 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7302 | "Unknown"), |
7303 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7304 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7305 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7306 | "Unknown"), | |
7307 | netdev->dev_addr); | |
289700db DS |
7308 | |
7309 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7310 | if (err) | |
9fe93afd | 7311 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7312 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7313 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7314 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7315 | part_str); |
e8e26350 | 7316 | else |
289700db DS |
7317 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7318 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7319 | |
e8e26350 | 7320 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7321 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7322 | "not sufficient for optimal performance.\n"); | |
7323 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7324 | "is required.\n"); | |
0c254d86 AK |
7325 | } |
7326 | ||
9a799d71 | 7327 | /* reset the hardware with the new settings */ |
794caeb2 | 7328 | err = hw->mac.ops.start_hw(hw); |
794caeb2 PWJ |
7329 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7330 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7331 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7332 | "Please be aware there may be issues associated " | |
7333 | "with your hardware. If you are experiencing " | |
7334 | "problems please contact your Intel or hardware " | |
7335 | "representative who provided you with this " | |
7336 | "hardware.\n"); | |
794caeb2 | 7337 | } |
9a799d71 AK |
7338 | strcpy(netdev->name, "eth%d"); |
7339 | err = register_netdev(netdev); | |
7340 | if (err) | |
7341 | goto err_register; | |
7342 | ||
93d3ce8f ET |
7343 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7344 | if (hw->mac.ops.disable_tx_laser && | |
7345 | ((hw->phy.multispeed_fiber) || | |
7346 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
7347 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
7348 | hw->mac.ops.disable_tx_laser(hw); | |
7349 | ||
54386467 JB |
7350 | /* carrier off reporting is important to ethtool even BEFORE open */ |
7351 | netif_carrier_off(netdev); | |
7352 | ||
5dd2d332 | 7353 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 7354 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 7355 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
7356 | ixgbe_setup_dca(adapter); |
7357 | } | |
7358 | #endif | |
1cdd1ec8 | 7359 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 7360 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
7361 | for (i = 0; i < adapter->num_vfs; i++) |
7362 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
7363 | } | |
7364 | ||
2466dd9c JK |
7365 | /* firmware requires driver version to be 0xFFFFFFFF |
7366 | * since os does not support feature | |
7367 | */ | |
9612de92 | 7368 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
7369 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
7370 | 0xFF); | |
9612de92 | 7371 | |
0365e6e4 PW |
7372 | /* add san mac addr to netdev */ |
7373 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 7374 | |
ea81875a | 7375 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 | 7376 | cards_found++; |
3ca8bc6d | 7377 | |
1210982b | 7378 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d DS |
7379 | if (ixgbe_sysfs_init(adapter)) |
7380 | e_err(probe, "failed to allocate sysfs resources\n"); | |
1210982b | 7381 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7382 | |
9a799d71 AK |
7383 | return 0; |
7384 | ||
7385 | err_register: | |
5eba3699 | 7386 | ixgbe_release_hw_control(adapter); |
7a921c93 | 7387 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 | 7388 | err_sw_init: |
1cdd1ec8 GR |
7389 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7390 | ixgbe_disable_sriov(adapter); | |
7086400d | 7391 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
7392 | iounmap(hw->hw_addr); |
7393 | err_ioremap: | |
7394 | free_netdev(netdev); | |
7395 | err_alloc_etherdev: | |
e8e9f696 JP |
7396 | pci_release_selected_regions(pdev, |
7397 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
7398 | err_pci_reg: |
7399 | err_dma: | |
7400 | pci_disable_device(pdev); | |
7401 | return err; | |
7402 | } | |
7403 | ||
7404 | /** | |
7405 | * ixgbe_remove - Device Removal Routine | |
7406 | * @pdev: PCI device information struct | |
7407 | * | |
7408 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
7409 | * that it should release a PCI device. The could be caused by a | |
7410 | * Hot-Plug event, or because the driver is going to be removed from | |
7411 | * memory. | |
7412 | **/ | |
7413 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
7414 | { | |
c60fbb00 AD |
7415 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7416 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
7417 | |
7418 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 7419 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 7420 | |
3a6a4eda JK |
7421 | #ifdef CONFIG_IXGBE_PTP |
7422 | ixgbe_ptp_stop(adapter); | |
7423 | #endif | |
7424 | ||
5dd2d332 | 7425 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7426 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
7427 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
7428 | dca_remove_requester(&pdev->dev); | |
7429 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
7430 | } | |
7431 | ||
7432 | #endif | |
1210982b | 7433 | #ifdef CONFIG_IXGBE_HWMON |
3ca8bc6d | 7434 | ixgbe_sysfs_exit(adapter); |
1210982b | 7435 | #endif /* CONFIG_IXGBE_HWMON */ |
3ca8bc6d | 7436 | |
332d4a7d YZ |
7437 | #ifdef IXGBE_FCOE |
7438 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
7439 | ixgbe_cleanup_fcoe(adapter); | |
7440 | ||
7441 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
7442 | |
7443 | /* remove the added san mac */ | |
7444 | ixgbe_del_sanmac_netdev(netdev); | |
7445 | ||
c4900be0 DS |
7446 | if (netdev->reg_state == NETREG_REGISTERED) |
7447 | unregister_netdev(netdev); | |
9a799d71 | 7448 | |
c6bda30a GR |
7449 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
7450 | if (!(ixgbe_check_vf_assignment(adapter))) | |
7451 | ixgbe_disable_sriov(adapter); | |
7452 | else | |
7453 | e_dev_warn("Unloading driver while VFs are assigned " | |
7454 | "- VFs will not be deallocated\n"); | |
7455 | } | |
1cdd1ec8 | 7456 | |
7a921c93 | 7457 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 7458 | |
021230d4 | 7459 | ixgbe_release_hw_control(adapter); |
9a799d71 | 7460 | |
2b1588c3 AD |
7461 | #ifdef CONFIG_DCB |
7462 | kfree(adapter->ixgbe_ieee_pfc); | |
7463 | kfree(adapter->ixgbe_ieee_ets); | |
7464 | ||
7465 | #endif | |
9a799d71 | 7466 | iounmap(adapter->hw.hw_addr); |
9ce77666 | 7467 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7468 | IORESOURCE_MEM)); |
9a799d71 | 7469 | |
849c4542 | 7470 | e_dev_info("complete\n"); |
021230d4 | 7471 | |
9a799d71 AK |
7472 | free_netdev(netdev); |
7473 | ||
19d5afd4 | 7474 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 7475 | |
9a799d71 AK |
7476 | pci_disable_device(pdev); |
7477 | } | |
7478 | ||
7479 | /** | |
7480 | * ixgbe_io_error_detected - called when PCI error is detected | |
7481 | * @pdev: Pointer to PCI device | |
7482 | * @state: The current pci connection state | |
7483 | * | |
7484 | * This function is called after a PCI bus error affecting | |
7485 | * this device has been detected. | |
7486 | */ | |
7487 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 7488 | pci_channel_state_t state) |
9a799d71 | 7489 | { |
c60fbb00 AD |
7490 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7491 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7492 | |
83c61fa9 GR |
7493 | #ifdef CONFIG_PCI_IOV |
7494 | struct pci_dev *bdev, *vfdev; | |
7495 | u32 dw0, dw1, dw2, dw3; | |
7496 | int vf, pos; | |
7497 | u16 req_id, pf_func; | |
7498 | ||
7499 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
7500 | adapter->num_vfs == 0) | |
7501 | goto skip_bad_vf_detection; | |
7502 | ||
7503 | bdev = pdev->bus->self; | |
7504 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
7505 | bdev = bdev->bus->self; | |
7506 | ||
7507 | if (!bdev) | |
7508 | goto skip_bad_vf_detection; | |
7509 | ||
7510 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
7511 | if (!pos) | |
7512 | goto skip_bad_vf_detection; | |
7513 | ||
7514 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
7515 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
7516 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
7517 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
7518 | ||
7519 | req_id = dw1 >> 16; | |
7520 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
7521 | if (!(req_id & 0x0080)) | |
7522 | goto skip_bad_vf_detection; | |
7523 | ||
7524 | pf_func = req_id & 0x01; | |
7525 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
7526 | unsigned int device_id; | |
7527 | ||
7528 | vf = (req_id & 0x7F) >> 1; | |
7529 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
7530 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
7531 | "%8.8x\tdw3: %8.8x\n", | |
7532 | dw0, dw1, dw2, dw3); | |
7533 | switch (adapter->hw.mac.type) { | |
7534 | case ixgbe_mac_82599EB: | |
7535 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
7536 | break; | |
7537 | case ixgbe_mac_X540: | |
7538 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
7539 | break; | |
7540 | default: | |
7541 | device_id = 0; | |
7542 | break; | |
7543 | } | |
7544 | ||
7545 | /* Find the pci device of the offending VF */ | |
7546 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL); | |
7547 | while (vfdev) { | |
7548 | if (vfdev->devfn == (req_id & 0xFF)) | |
7549 | break; | |
7550 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, | |
7551 | device_id, vfdev); | |
7552 | } | |
7553 | /* | |
7554 | * There's a slim chance the VF could have been hot plugged, | |
7555 | * so if it is no longer present we don't need to issue the | |
7556 | * VFLR. Just clean up the AER in that case. | |
7557 | */ | |
7558 | if (vfdev) { | |
7559 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
7560 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
7561 | } | |
7562 | ||
7563 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
7564 | } | |
7565 | ||
7566 | /* | |
7567 | * Even though the error may have occurred on the other port | |
7568 | * we still need to increment the vf error reference count for | |
7569 | * both ports because the I/O resume function will be called | |
7570 | * for both of them. | |
7571 | */ | |
7572 | adapter->vferr_refcount++; | |
7573 | ||
7574 | return PCI_ERS_RESULT_RECOVERED; | |
7575 | ||
7576 | skip_bad_vf_detection: | |
7577 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
7578 | netif_device_detach(netdev); |
7579 | ||
3044b8d1 BL |
7580 | if (state == pci_channel_io_perm_failure) |
7581 | return PCI_ERS_RESULT_DISCONNECT; | |
7582 | ||
9a799d71 AK |
7583 | if (netif_running(netdev)) |
7584 | ixgbe_down(adapter); | |
7585 | pci_disable_device(pdev); | |
7586 | ||
b4617240 | 7587 | /* Request a slot reset. */ |
9a799d71 AK |
7588 | return PCI_ERS_RESULT_NEED_RESET; |
7589 | } | |
7590 | ||
7591 | /** | |
7592 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
7593 | * @pdev: Pointer to PCI device | |
7594 | * | |
7595 | * Restart the card from scratch, as if from a cold-boot. | |
7596 | */ | |
7597 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
7598 | { | |
c60fbb00 | 7599 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
7600 | pci_ers_result_t result; |
7601 | int err; | |
9a799d71 | 7602 | |
9ce77666 | 7603 | if (pci_enable_device_mem(pdev)) { |
396e799c | 7604 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
7605 | result = PCI_ERS_RESULT_DISCONNECT; |
7606 | } else { | |
7607 | pci_set_master(pdev); | |
7608 | pci_restore_state(pdev); | |
c0e1f68b | 7609 | pci_save_state(pdev); |
9a799d71 | 7610 | |
dd4d8ca6 | 7611 | pci_wake_from_d3(pdev, false); |
9a799d71 | 7612 | |
6fabd715 | 7613 | ixgbe_reset(adapter); |
88512539 | 7614 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
7615 | result = PCI_ERS_RESULT_RECOVERED; |
7616 | } | |
7617 | ||
7618 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
7619 | if (err) { | |
849c4542 ET |
7620 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
7621 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
7622 | /* non-fatal, continue */ |
7623 | } | |
9a799d71 | 7624 | |
6fabd715 | 7625 | return result; |
9a799d71 AK |
7626 | } |
7627 | ||
7628 | /** | |
7629 | * ixgbe_io_resume - called when traffic can start flowing again. | |
7630 | * @pdev: Pointer to PCI device | |
7631 | * | |
7632 | * This callback is called when the error recovery driver tells us that | |
7633 | * its OK to resume normal operation. | |
7634 | */ | |
7635 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
7636 | { | |
c60fbb00 AD |
7637 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
7638 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 7639 | |
83c61fa9 GR |
7640 | #ifdef CONFIG_PCI_IOV |
7641 | if (adapter->vferr_refcount) { | |
7642 | e_info(drv, "Resuming after VF err\n"); | |
7643 | adapter->vferr_refcount--; | |
7644 | return; | |
7645 | } | |
7646 | ||
7647 | #endif | |
c7ccde0f AD |
7648 | if (netif_running(netdev)) |
7649 | ixgbe_up(adapter); | |
9a799d71 AK |
7650 | |
7651 | netif_device_attach(netdev); | |
9a799d71 AK |
7652 | } |
7653 | ||
7654 | static struct pci_error_handlers ixgbe_err_handler = { | |
7655 | .error_detected = ixgbe_io_error_detected, | |
7656 | .slot_reset = ixgbe_io_slot_reset, | |
7657 | .resume = ixgbe_io_resume, | |
7658 | }; | |
7659 | ||
7660 | static struct pci_driver ixgbe_driver = { | |
7661 | .name = ixgbe_driver_name, | |
7662 | .id_table = ixgbe_pci_tbl, | |
7663 | .probe = ixgbe_probe, | |
7664 | .remove = __devexit_p(ixgbe_remove), | |
7665 | #ifdef CONFIG_PM | |
7666 | .suspend = ixgbe_suspend, | |
7667 | .resume = ixgbe_resume, | |
7668 | #endif | |
7669 | .shutdown = ixgbe_shutdown, | |
7670 | .err_handler = &ixgbe_err_handler | |
7671 | }; | |
7672 | ||
7673 | /** | |
7674 | * ixgbe_init_module - Driver Registration Routine | |
7675 | * | |
7676 | * ixgbe_init_module is the first routine called when the driver is | |
7677 | * loaded. All it does is register with the PCI subsystem. | |
7678 | **/ | |
7679 | static int __init ixgbe_init_module(void) | |
7680 | { | |
7681 | int ret; | |
c7689578 | 7682 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 7683 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 7684 | |
5dd2d332 | 7685 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7686 | dca_register_notify(&dca_notifier); |
bd0362dd | 7687 | #endif |
5dd2d332 | 7688 | |
9a799d71 AK |
7689 | ret = pci_register_driver(&ixgbe_driver); |
7690 | return ret; | |
7691 | } | |
b4617240 | 7692 | |
9a799d71 AK |
7693 | module_init(ixgbe_init_module); |
7694 | ||
7695 | /** | |
7696 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
7697 | * | |
7698 | * ixgbe_exit_module is called just before the driver is removed | |
7699 | * from memory. | |
7700 | **/ | |
7701 | static void __exit ixgbe_exit_module(void) | |
7702 | { | |
5dd2d332 | 7703 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
7704 | dca_unregister_notify(&dca_notifier); |
7705 | #endif | |
9a799d71 | 7706 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 7707 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 7708 | } |
bd0362dd | 7709 | |
5dd2d332 | 7710 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 7711 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 7712 | void *p) |
bd0362dd JC |
7713 | { |
7714 | int ret_val; | |
7715 | ||
7716 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 7717 | __ixgbe_notify_dca); |
bd0362dd JC |
7718 | |
7719 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
7720 | } | |
b453368d | 7721 | |
5dd2d332 | 7722 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 7723 | |
9a799d71 AK |
7724 | module_exit(ixgbe_exit_module); |
7725 | ||
7726 | /* ixgbe_main.c */ |