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ixgbe: Avoid needless PHY access on copper phys
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
67359c3c 4 Copyright(c) 1999 - 2015 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
c762dff2 45#include <linux/etherdevice.h>
9a799d71 46#include <linux/ethtool.h>
01789349 47#include <linux/if.h>
9a799d71 48#include <linux/if_vlan.h>
2a47fa45 49#include <linux/if_macvlan.h>
815cccbf 50#include <linux/if_bridge.h>
70c71606 51#include <linux/prefetch.h>
eacd73f7 52#include <scsi/fc/fc_fcoe.h>
3f207800 53#include <net/vxlan.h>
9a799d71 54
c762dff2
MP		 55#ifdef CONFIG_OF
56#include <linux/of_net.h>
57#endif
58
59#ifdef CONFIG_SPARC
60#include <asm/idprom.h>
61#include <asm/prom.h>
62#endif
63
9a799d71
AK		 64#include "ixgbe.h"
65#include "ixgbe_common.h"
ee5f784a 66#include "ixgbe_dcb_82599.h"
1cdd1ec8 67#include "ixgbe_sriov.h"
67359c3c
MR		 68#ifdef CONFIG_IXGBE_VXLAN
69#include <net/vxlan.h>
70#endif
9a799d71
AK		 71
72char ixgbe_driver_name[] = "ixgbe";
9c8eb720 73static const char ixgbe_driver_string[] =
e8e9f696 74 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 75#ifdef IXGBE_FCOE
ea81875a
NP		 76char ixgbe_default_device_descr[] =
77 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 78#else
79static char ixgbe_default_device_descr[] =
80 "Intel(R) 10 Gigabit Network Connection";
81#endif
9be4a9bb 82#define DRV_VERSION "4.0.1-k"
9c8eb720 83const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 84static const char ixgbe_copyright[] =
67359c3c 85 "Copyright (c) 1999-2015 Intel Corporation.";
9a799d71 86
f44e751b
DS		 87static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
88
9a799d71 89static const struct ixgbe_info *ixgbe_info_tbl[] = {
6a14ee0c
DS		 90 [board_82598] = &ixgbe_82598_info,
91 [board_82599] = &ixgbe_82599_info,
92 [board_X540] = &ixgbe_X540_info,
93 [board_X550] = &ixgbe_X550_info,
94 [board_X550EM_x] = &ixgbe_X550EM_x_info,
9a799d71
AK		 95};
96
97/* ixgbe_pci_tbl - PCI Device ID Table
98 *
99 * Wildcard entries (PCI_ANY_ID) should come last
100 * Last entry must be all 0s
101 *
102 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
103 * Class, Class Mask, private data (not used) }
104 */
9baa3c34 105static const struct pci_device_id ixgbe_pci_tbl[] = {
54239c67
AD		 106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 134 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 135 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
6a14ee0c
DS		 136 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
137 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
138 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
deda562a 139 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
9a799d71
AK		 140 /* required last entry */
141 {0, }
142};
143MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
144
5dd2d332 145#ifdef CONFIG_IXGBE_DCA
bd0362dd 146static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 147 void *p);
bd0362dd
JC		 148static struct notifier_block dca_notifier = {
149 .notifier_call = ixgbe_notify_dca,
150 .next = NULL,
151 .priority = 0
152};
153#endif
154
1cdd1ec8
GR		 155#ifdef CONFIG_PCI_IOV
156static unsigned int max_vfs;
157module_param(max_vfs, uint, 0);
e8e9f696 158MODULE_PARM_DESC(max_vfs,
170e8543 159 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 160#endif /* CONFIG_PCI_IOV */
161
8ef78adc
PWJ		 162static unsigned int allow_unsupported_sfp;
163module_param(allow_unsupported_sfp, uint, 0);
164MODULE_PARM_DESC(allow_unsupported_sfp,
165 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
166
b3f4d599 167#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
168static int debug = -1;
169module_param(debug, int, 0);
170MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
171
9a799d71
AK		 172MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
173MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
174MODULE_LICENSE("GPL");
175MODULE_VERSION(DRV_VERSION);
176
14438464
MR		 177static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
178
b8e82001
JK		 179static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
180 u32 reg, u16 *value)
181{
b8e82001
JK		 182 struct pci_dev *parent_dev;
183 struct pci_bus *parent_bus;
184
185 parent_bus = adapter->pdev->bus->parent;
186 if (!parent_bus)
187 return -1;
188
189 parent_dev = parent_bus->self;
190 if (!parent_dev)
191 return -1;
192
c0798edf 193 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 194 return -1;
195
c0798edf 196 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 197 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
198 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
199 return -1;
b8e82001
JK		 200 return 0;
201}
202
203static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
204{
205 struct ixgbe_hw *hw = &adapter->hw;
206 u16 link_status = 0;
207 int err;
208
209 hw->bus.type = ixgbe_bus_type_pci_express;
210
211 /* Get the negotiated link width and speed from PCI config space of the
212 * parent, as this device is behind a switch
213 */
214 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
215
216 /* assume caller will handle error case */
217 if (err)
218 return err;
219
220 hw->bus.width = ixgbe_convert_bus_width(link_status);
221 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
222
223 return 0;
224}
225
e027d1ae
JK		 226/**
227 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
228 * @hw: hw specific details
229 *
230 * This function is used by probe to determine whether a device's PCI-Express
231 * bandwidth details should be gathered from the parent bus instead of from the
232 * device. Used to ensure that various locations all have the correct device ID
233 * checks.
234 */
235static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
236{
237 switch (hw->device_id) {
238 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 239 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 240 return true;
241 default:
242 return false;
243 }
244}
245
246static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
247 int expected_gts)
248{
f9328bc6 249 struct ixgbe_hw *hw = &adapter->hw;
e027d1ae
JK		 250 int max_gts = 0;
251 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
252 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
253 struct pci_dev *pdev;
254
f9328bc6
DS		 255 /* Some devices are not connected over PCIe and thus do not negotiate
256 * speed. These devices do not have valid bus info, and thus any report
257 * we generate may not be correct.
258 */
259 if (hw->bus.type == ixgbe_bus_type_internal)
260 return;
261
56d1392f 262 /* determine whether to use the parent device */
e027d1ae
JK		 263 if (ixgbe_pcie_from_parent(&adapter->hw))
264 pdev = adapter->pdev->bus->parent->self;
265 else
266 pdev = adapter->pdev;
267
268 if (pcie_get_minimum_link(pdev, &speed, &width) ||
269 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
270 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
271 return;
272 }
273
274 switch (speed) {
275 case PCIE_SPEED_2_5GT:
276 /* 8b/10b encoding reduces max throughput by 20% */
277 max_gts = 2 * width;
278 break;
279 case PCIE_SPEED_5_0GT:
280 /* 8b/10b encoding reduces max throughput by 20% */
281 max_gts = 4 * width;
282 break;
283 case PCIE_SPEED_8_0GT:
9f0a433c 284 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 285 max_gts = 8 * width;
286 break;
287 default:
288 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
289 return;
290 }
291
292 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
293 max_gts);
294 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
295 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
296 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
297 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
298 "Unknown"),
299 width,
300 (speed == PCIE_SPEED_2_5GT ? "20%" :
301 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 302 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 303 "Unknown"));
304
305 if (max_gts < expected_gts) {
306 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
307 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
308 expected_gts);
309 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
310 }
311}
312
7086400d
AD		 313static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
314{
315 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 316 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 317 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
318 schedule_work(&adapter->service_task);
319}
320
2a1a091c
MR		 321static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
322{
323 struct ixgbe_adapter *adapter = hw->back;
324
325 if (!hw->hw_addr)
326 return;
327 hw->hw_addr = NULL;
328 e_dev_err("Adapter removed\n");
58cf663f
MR		 329 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
330 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 331}
332
f8e2472f 333static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 334{
335 u32 value;
336
337 /* The following check not only optimizes a bit by not
338 * performing a read on the status register when the
339 * register just read was a status register read that
340 * returned IXGBE_FAILED_READ_REG. It also blocks any
341 * potential recursion.
342 */
343 if (reg == IXGBE_STATUS) {
344 ixgbe_remove_adapter(hw);
345 return;
346 }
347 value = ixgbe_read_reg(hw, IXGBE_STATUS);
348 if (value == IXGBE_FAILED_READ_REG)
349 ixgbe_remove_adapter(hw);
350}
351
f8e2472f
MR		 352/**
353 * ixgbe_read_reg - Read from device register
354 * @hw: hw specific details
355 * @reg: offset of register to read
356 *
357 * Returns : value read or IXGBE_FAILED_READ_REG if removed
358 *
359 * This function is used to read device registers. It checks for device
360 * removal by confirming any read that returns all ones by checking the
361 * status register value for all ones. This function avoids reading from
362 * the hardware if a removal was previously detected in which case it
363 * returns IXGBE_FAILED_READ_REG (all ones).
364 */
365u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
366{
367 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
368 u32 value;
369
370 if (ixgbe_removed(reg_addr))
371 return IXGBE_FAILED_READ_REG;
372 value = readl(reg_addr + reg);
373 if (unlikely(value == IXGBE_FAILED_READ_REG))
374 ixgbe_check_remove(hw, reg);
375 return value;
376}
377
14438464
MR		 378static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
379{
380 u16 value;
381
382 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
383 if (value == IXGBE_FAILED_READ_CFG_WORD) {
384 ixgbe_remove_adapter(hw);
385 return true;
386 }
387 return false;
388}
389
390u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
391{
392 struct ixgbe_adapter *adapter = hw->back;
393 u16 value;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return IXGBE_FAILED_READ_CFG_WORD;
397 pci_read_config_word(adapter->pdev, reg, &value);
398 if (value == IXGBE_FAILED_READ_CFG_WORD &&
399 ixgbe_check_cfg_remove(hw, adapter->pdev))
400 return IXGBE_FAILED_READ_CFG_WORD;
401 return value;
402}
403
404#ifdef CONFIG_PCI_IOV
405static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
406{
407 struct ixgbe_adapter *adapter = hw->back;
408 u32 value;
409
410 if (ixgbe_removed(hw->hw_addr))
411 return IXGBE_FAILED_READ_CFG_DWORD;
412 pci_read_config_dword(adapter->pdev, reg, &value);
413 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
414 ixgbe_check_cfg_remove(hw, adapter->pdev))
415 return IXGBE_FAILED_READ_CFG_DWORD;
416 return value;
417}
418#endif /* CONFIG_PCI_IOV */
419
ed19231c
JK		 420void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
421{
422 struct ixgbe_adapter *adapter = hw->back;
423
424 if (ixgbe_removed(hw->hw_addr))
425 return;
426 pci_write_config_word(adapter->pdev, reg, value);
427}
428
7086400d
AD		 429static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
430{
431 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
432
52f33af8 433 /* flush memory to make sure state is correct before next watchdog */
4e857c58 434 smp_mb__before_atomic();
7086400d
AD		 435 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
436}
437
dcd79aeb
TI		 438struct ixgbe_reg_info {
439 u32 ofs;
440 char *name;
441};
442
443static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
444
445 /* General Registers */
446 {IXGBE_CTRL, "CTRL"},
447 {IXGBE_STATUS, "STATUS"},
448 {IXGBE_CTRL_EXT, "CTRL_EXT"},
449
450 /* Interrupt Registers */
451 {IXGBE_EICR, "EICR"},
452
453 /* RX Registers */
454 {IXGBE_SRRCTL(0), "SRRCTL"},
455 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
456 {IXGBE_RDLEN(0), "RDLEN"},
457 {IXGBE_RDH(0), "RDH"},
458 {IXGBE_RDT(0), "RDT"},
459 {IXGBE_RXDCTL(0), "RXDCTL"},
460 {IXGBE_RDBAL(0), "RDBAL"},
461 {IXGBE_RDBAH(0), "RDBAH"},
462
463 /* TX Registers */
464 {IXGBE_TDBAL(0), "TDBAL"},
465 {IXGBE_TDBAH(0), "TDBAH"},
466 {IXGBE_TDLEN(0), "TDLEN"},
467 {IXGBE_TDH(0), "TDH"},
468 {IXGBE_TDT(0), "TDT"},
469 {IXGBE_TXDCTL(0), "TXDCTL"},
470
471 /* List Terminator */
ca8dfe25 472 { .name = NULL }
dcd79aeb
TI		 473};
474
475
476/*
477 * ixgbe_regdump - register printout routine
478 */
479static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
480{
481 int i = 0, j = 0;
482 char rname[16];
483 u32 regs[64];
484
485 switch (reginfo->ofs) {
486 case IXGBE_SRRCTL(0):
487 for (i = 0; i < 64; i++)
488 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
489 break;
490 case IXGBE_DCA_RXCTRL(0):
491 for (i = 0; i < 64; i++)
492 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
493 break;
494 case IXGBE_RDLEN(0):
495 for (i = 0; i < 64; i++)
496 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
497 break;
498 case IXGBE_RDH(0):
499 for (i = 0; i < 64; i++)
500 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
501 break;
502 case IXGBE_RDT(0):
503 for (i = 0; i < 64; i++)
504 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
505 break;
506 case IXGBE_RXDCTL(0):
507 for (i = 0; i < 64; i++)
508 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
509 break;
510 case IXGBE_RDBAL(0):
511 for (i = 0; i < 64; i++)
512 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
513 break;
514 case IXGBE_RDBAH(0):
515 for (i = 0; i < 64; i++)
516 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
517 break;
518 case IXGBE_TDBAL(0):
519 for (i = 0; i < 64; i++)
520 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
521 break;
522 case IXGBE_TDBAH(0):
523 for (i = 0; i < 64; i++)
524 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
525 break;
526 case IXGBE_TDLEN(0):
527 for (i = 0; i < 64; i++)
528 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
529 break;
530 case IXGBE_TDH(0):
531 for (i = 0; i < 64; i++)
532 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
533 break;
534 case IXGBE_TDT(0):
535 for (i = 0; i < 64; i++)
536 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
537 break;
538 case IXGBE_TXDCTL(0):
539 for (i = 0; i < 64; i++)
540 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
541 break;
542 default:
c7689578 543 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 544 IXGBE_READ_REG(hw, reginfo->ofs));
545 return;
546 }
547
548 for (i = 0; i < 8; i++) {
549 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 550 pr_err("%-15s", rname);
dcd79aeb 551 for (j = 0; j < 8; j++)
c7689578
JP		 552 pr_cont(" %08x", regs[i*8+j]);
553 pr_cont("\n");
dcd79aeb
TI		 554 }
555
556}
557
558/*
559 * ixgbe_dump - Print registers, tx-rings and rx-rings
560 */
561static void ixgbe_dump(struct ixgbe_adapter *adapter)
562{
563 struct net_device *netdev = adapter->netdev;
564 struct ixgbe_hw *hw = &adapter->hw;
565 struct ixgbe_reg_info *reginfo;
566 int n = 0;
567 struct ixgbe_ring *tx_ring;
729739b7 568 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 569 union ixgbe_adv_tx_desc *tx_desc;
570 struct my_u0 { u64 a; u64 b; } *u0;
571 struct ixgbe_ring *rx_ring;
572 union ixgbe_adv_rx_desc *rx_desc;
573 struct ixgbe_rx_buffer *rx_buffer_info;
574 u32 staterr;
575 int i = 0;
576
577 if (!netif_msg_hw(adapter))
578 return;
579
580 /* Print netdevice Info */
581 if (netdev) {
582 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 583 pr_info("Device Name state "
dcd79aeb 584 "trans_start last_rx\n");
c7689578
JP		 585 pr_info("%-15s %016lX %016lX %016lX\n",
586 netdev->name,
587 netdev->state,
588 netdev->trans_start,
589 netdev->last_rx);
dcd79aeb
TI		 590 }
591
592 /* Print Registers */
593 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 594 pr_info(" Register Name Value\n");
dcd79aeb
TI		 595 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
596 reginfo->name; reginfo++) {
597 ixgbe_regdump(hw, reginfo);
598 }
599
600 /* Print TX Ring Summary */
601 if (!netdev || !netif_running(netdev))
e90dd264 602 return;
dcd79aeb
TI		 603
604 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 605 pr_info(" %s %s %s %s\n",
606 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
607 "leng", "ntw", "timestamp");
dcd79aeb
TI		 608 for (n = 0; n < adapter->num_tx_queues; n++) {
609 tx_ring = adapter->tx_ring[n];
729739b7 610 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 611 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 612 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 613 (u64)dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 tx_buffer->next_to_watch,
616 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 617 }
618
619 /* Print TX Rings */
620 if (!netif_msg_tx_done(adapter))
621 goto rx_ring_summary;
622
623 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
624
625 /* Transmit Descriptor Formats
626 *
39ac868a 627 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 628 * +--------------------------------------------------------------+
629 * 0 | Buffer Address [63:0] |
630 * +--------------------------------------------------------------+
39ac868a 631 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 632 * +--------------------------------------------------------------+
633 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 634 *
635 * 82598 Advanced Transmit Descriptor (Write-Back Format)
636 * +--------------------------------------------------------------+
637 * 0 | RSV [63:0] |
638 * +--------------------------------------------------------------+
639 * 8 | RSV | STA | NXTSEQ |
640 * +--------------------------------------------------------------+
641 * 63 36 35 32 31 0
642 *
643 * 82599+ Advanced Transmit Descriptor
644 * +--------------------------------------------------------------+
645 * 0 | Buffer Address [63:0] |
646 * +--------------------------------------------------------------+
647 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
648 * +--------------------------------------------------------------+
649 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
650 *
651 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
652 * +--------------------------------------------------------------+
653 * 0 | RSV [63:0] |
654 * +--------------------------------------------------------------+
655 * 8 | RSV | STA | RSV |
656 * +--------------------------------------------------------------+
657 * 63 36 35 32 31 0
dcd79aeb
TI		 658 */
659
660 for (n = 0; n < adapter->num_tx_queues; n++) {
661 tx_ring = adapter->tx_ring[n];
c7689578
JP		 662 pr_info("------------------------------------\n");
663 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
664 pr_info("------------------------------------\n");
8ad88e37
JH		 665 pr_info("%s%s %s %s %s %s\n",
666 "T [desc] [address 63:0 ] ",
667 "[PlPOIdStDDt Ln] [bi->dma ] ",
668 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 669
670 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 671 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 672 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 673 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 674 if (dma_unmap_len(tx_buffer, len) > 0) {
675 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
676 i,
677 le64_to_cpu(u0->a),
678 le64_to_cpu(u0->b),
679 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 680 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 681 tx_buffer->next_to_watch,
682 (u64)tx_buffer->time_stamp,
683 tx_buffer->skb);
684 if (i == tx_ring->next_to_use &&
685 i == tx_ring->next_to_clean)
686 pr_cont(" NTC/U\n");
687 else if (i == tx_ring->next_to_use)
688 pr_cont(" NTU\n");
689 else if (i == tx_ring->next_to_clean)
690 pr_cont(" NTC\n");
691 else
692 pr_cont("\n");
693
694 if (netif_msg_pktdata(adapter) &&
695 tx_buffer->skb)
696 print_hex_dump(KERN_INFO, "",
697 DUMP_PREFIX_ADDRESS, 16, 1,
698 tx_buffer->skb->data,
699 dma_unmap_len(tx_buffer, len),
700 true);
701 }
dcd79aeb
TI		 702 }
703 }
704
705 /* Print RX Rings Summary */
706rx_ring_summary:
707 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 708 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 709 for (n = 0; n < adapter->num_rx_queues; n++) {
710 rx_ring = adapter->rx_ring[n];
c7689578
JP		 711 pr_info("%5d %5X %5X\n",
712 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 713 }
714
715 /* Print RX Rings */
716 if (!netif_msg_rx_status(adapter))
e90dd264 717 return;
dcd79aeb
TI		 718
719 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
720
39ac868a
JH		 721 /* Receive Descriptor Formats
722 *
723 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 724 * 63 1 0
725 * +-----------------------------------------------------+
726 * 0 | Packet Buffer Address [63:1] |A0/NSE|
727 * +----------------------------------------------+------+
728 * 8 | Header Buffer Address [63:1] | DD |
729 * +-----------------------------------------------------+
730 *
731 *
39ac868a 732 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 733 *
734 * 63 48 47 32 31 30 21 20 16 15 4 3 0
735 * +------------------------------------------------------+
39ac868a
JH		 736 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
737 * | Packet | IP | | | | Type | Type |
738 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 739 * +------------------------------------------------------+
740 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
741 * +------------------------------------------------------+
742 * 63 48 47 32 31 20 19 0
39ac868a
JH		 743 *
744 * 82599+ Advanced Receive Descriptor (Read) Format
745 * 63 1 0
746 * +-----------------------------------------------------+
747 * 0 | Packet Buffer Address [63:1] |A0/NSE|
748 * +----------------------------------------------+------+
749 * 8 | Header Buffer Address [63:1] | DD |
750 * +-----------------------------------------------------+
751 *
752 *
753 * 82599+ Advanced Receive Descriptor (Write-Back) Format
754 *
755 * 63 48 47 32 31 30 21 20 17 16 4 3 0
756 * +------------------------------------------------------+
757 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
758 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
759 * |/ Flow Dir Flt ID | | | | | |
760 * +------------------------------------------------------+
761 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
762 * +------------------------------------------------------+
763 * 63 48 47 32 31 20 19 0
dcd79aeb 764 */
39ac868a 765
dcd79aeb
TI		 766 for (n = 0; n < adapter->num_rx_queues; n++) {
767 rx_ring = adapter->rx_ring[n];
c7689578
JP		 768 pr_info("------------------------------------\n");
769 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
770 pr_info("------------------------------------\n");
8ad88e37
JH		 771 pr_info("%s%s%s",
772 "R [desc] [ PktBuf A0] ",
773 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 774 "<-- Adv Rx Read format\n");
8ad88e37
JH		 775 pr_info("%s%s%s",
776 "RWB[desc] [PcsmIpSHl PtRs] ",
777 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 778 "<-- Adv Rx Write-Back format\n");
779
780 for (i = 0; i < rx_ring->count; i++) {
781 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 782 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 783 u0 = (struct my_u0 *)rx_desc;
784 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
785 if (staterr & IXGBE_RXD_STAT_DD) {
786 /* Descriptor Done */
c7689578 787 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 788 "%016llX ---------------- %p", i,
789 le64_to_cpu(u0->a),
790 le64_to_cpu(u0->b),
791 rx_buffer_info->skb);
792 } else {
c7689578 793 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 794 "%016llX %016llX %p", i,
795 le64_to_cpu(u0->a),
796 le64_to_cpu(u0->b),
797 (u64)rx_buffer_info->dma,
798 rx_buffer_info->skb);
799
9c50c035
ET		 800 if (netif_msg_pktdata(adapter) &&
801 rx_buffer_info->dma) {
dcd79aeb
TI		 802 print_hex_dump(KERN_INFO, "",
803 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 804 page_address(rx_buffer_info->page) +
805 rx_buffer_info->page_offset,
f800326d 806 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 807 }
808 }
809
810 if (i == rx_ring->next_to_use)
c7689578 811 pr_cont(" NTU\n");
dcd79aeb 812 else if (i == rx_ring->next_to_clean)
c7689578 813 pr_cont(" NTC\n");
dcd79aeb 814 else
c7689578 815 pr_cont("\n");
dcd79aeb
TI		 816
817 }
818 }
dcd79aeb
TI		 819}
820
5eba3699
AV		 821static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
822{
823 u32 ctrl_ext;
824
825 /* Let firmware take over control of h/w */
826 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
827 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 828 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 829}
830
831static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
832{
833 u32 ctrl_ext;
834
835 /* Let firmware know the driver has taken over */
836 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
837 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 838 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 839}
9a799d71 840
49ce9c2c 841/**
e8e26350
PW		 842 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
843 * @adapter: pointer to adapter struct
844 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
845 * @queue: queue to map the corresponding interrupt to
846 * @msix_vector: the vector to map to the corresponding queue
847 *
848 */
849static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 850 u8 queue, u8 msix_vector)
9a799d71
AK		 851{
852 u32 ivar, index;
e8e26350
PW		 853 struct ixgbe_hw *hw = &adapter->hw;
854 switch (hw->mac.type) {
855 case ixgbe_mac_82598EB:
856 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
857 if (direction == -1)
858 direction = 0;
859 index = (((direction * 64) + queue) >> 2) & 0x1F;
860 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
861 ivar &= ~(0xFF << (8 * (queue & 0x3)));
862 ivar |= (msix_vector << (8 * (queue & 0x3)));
863 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
864 break;
865 case ixgbe_mac_82599EB:
b93a2226 866 case ixgbe_mac_X540:
9a75a1ac
DS		 867 case ixgbe_mac_X550:
868 case ixgbe_mac_X550EM_x:
e8e26350
PW		 869 if (direction == -1) {
870 /* other causes */
871 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
872 index = ((queue & 1) * 8);
873 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
874 ivar &= ~(0xFF << index);
875 ivar |= (msix_vector << index);
876 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
877 break;
878 } else {
879 /* tx or rx causes */
880 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
881 index = ((16 * (queue & 1)) + (8 * direction));
882 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
883 ivar &= ~(0xFF << index);
884 ivar |= (msix_vector << index);
885 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
886 break;
887 }
888 default:
889 break;
890 }
9a799d71
AK		 891}
892
fe49f04a 893static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 894 u64 qmask)
fe49f04a
AD		 895{
896 u32 mask;
897
bd508178
AD		 898 switch (adapter->hw.mac.type) {
899 case ixgbe_mac_82598EB:
fe49f04a
AD		 900 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 902 break;
903 case ixgbe_mac_82599EB:
b93a2226 904 case ixgbe_mac_X540:
9a75a1ac
DS		 905 case ixgbe_mac_X550:
906 case ixgbe_mac_X550EM_x:
fe49f04a
AD		 907 mask = (qmask & 0xFFFFFFFF);
908 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
909 mask = (qmask >> 32);
910 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 911 break;
912 default:
913 break;
fe49f04a
AD		 914 }
915}
916
729739b7
AD		 917void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
918 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 919{
729739b7
AD		 920 if (tx_buffer->skb) {
921 dev_kfree_skb_any(tx_buffer->skb);
922 if (dma_unmap_len(tx_buffer, len))
d3d00239 923 dma_unmap_single(ring->dev,
729739b7
AD		 924 dma_unmap_addr(tx_buffer, dma),
925 dma_unmap_len(tx_buffer, len),
926 DMA_TO_DEVICE);
927 } else if (dma_unmap_len(tx_buffer, len)) {
928 dma_unmap_page(ring->dev,
929 dma_unmap_addr(tx_buffer, dma),
930 dma_unmap_len(tx_buffer, len),
931 DMA_TO_DEVICE);
e5a43549 932 }
729739b7
AD		 933 tx_buffer->next_to_watch = NULL;
934 tx_buffer->skb = NULL;
935 dma_unmap_len_set(tx_buffer, len, 0);
936 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 937}
938
943561d3 939static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 940{
941 struct ixgbe_hw *hw = &adapter->hw;
942 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 943 int i;
943561d3 944 u32 data;
c84d324c 945
943561d3
AD		 946 if ((hw->fc.current_mode != ixgbe_fc_full) &&
947 (hw->fc.current_mode != ixgbe_fc_rx_pause))
948 return;
c84d324c 949
943561d3
AD		 950 switch (hw->mac.type) {
951 case ixgbe_mac_82598EB:
952 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
953 break;
954 default:
955 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
956 }
957 hwstats->lxoffrxc += data;
c84d324c 958
943561d3
AD		 959 /* refill credits (no tx hang) if we received xoff */
960 if (!data)
c84d324c 961 return;
943561d3
AD		 962
963 for (i = 0; i < adapter->num_tx_queues; i++)
964 clear_bit(__IXGBE_HANG_CHECK_ARMED,
965 &adapter->tx_ring[i]->state);
966}
967
968static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
969{
970 struct ixgbe_hw *hw = &adapter->hw;
971 struct ixgbe_hw_stats *hwstats = &adapter->stats;
972 u32 xoff[8] = {0};
2afaa00d 973 u8 tc;
943561d3
AD		 974 int i;
975 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
976
977 if (adapter->ixgbe_ieee_pfc)
978 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
979
980 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
981 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 982 return;
943561d3 983 }
c84d324c
JF		 984
985 /* update stats for each tc, only valid with PFC enabled */
986 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 987 u32 pxoffrxc;
988
c84d324c
JF		 989 switch (hw->mac.type) {
990 case ixgbe_mac_82598EB:
2afaa00d 991 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 992 break;
c84d324c 993 default:
2afaa00d 994 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 995 }
2afaa00d
PN		 996 hwstats->pxoffrxc[i] += pxoffrxc;
997 /* Get the TC for given UP */
998 tc = netdev_get_prio_tc_map(adapter->netdev, i);
999 xoff[tc] += pxoffrxc;
c84d324c
JF		 1000 }
1001
1002 /* disarm tx queues that have received xoff frames */
1003 for (i = 0; i < adapter->num_tx_queues; i++) {
1004 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 1005
2afaa00d 1006 tc = tx_ring->dcb_tc;
c84d324c
JF		 1007 if (xoff[tc])
1008 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 1009 }
26f23d82
YZ		 1010}
1011
c84d324c 1012static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 1013{
7d7ce682 1014 return ring->stats.packets;
c84d324c
JF		 1015}
1016
1017static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1018{
2a47fa45
JF		 1019 struct ixgbe_adapter *adapter;
1020 struct ixgbe_hw *hw;
1021 u32 head, tail;
1022
1023 if (ring->l2_accel_priv)
1024 adapter = ring->l2_accel_priv->real_adapter;
1025 else
1026 adapter = netdev_priv(ring->netdev);
e01c31a5 1027
2a47fa45
JF		 1028 hw = &adapter->hw;
1029 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1030 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1031
1032 if (head != tail)
1033 return (head < tail) ?
1034 tail - head : (tail + ring->count - head);
1035
1036 return 0;
1037}
1038
1039static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1040{
1041 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1042 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1043 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
c84d324c 1044
7d637bcc 1045 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1046
1047 /*
1048 * Check for a hung queue, but be thorough. This verifies
1049 * that a transmit has been completed since the previous
1050 * check AND there is at least one packet pending. The
1051 * ARMED bit is set to indicate a potential hang. The
1052 * bit is cleared if a pause frame is received to remove
1053 * false hang detection due to PFC or 802.3x frames. By
1054 * requiring this to fail twice we avoid races with
1055 * pfc clearing the ARMED bit and conditions where we
1056 * run the check_tx_hang logic with a transmit completion
1057 * pending but without time to complete it yet.
1058 */
e90dd264 1059 if (tx_done_old == tx_done && tx_pending)
c84d324c 1060 /* make sure it is true for two checks in a row */
e90dd264
MR		 1061 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1062 &tx_ring->state);
1063 /* update completed stats and continue */
1064 tx_ring->tx_stats.tx_done_old = tx_done;
1065 /* reset the countdown */
1066 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71 1067
e90dd264 1068 return false;
9a799d71
AK		 1069}
1070
c83c6cbd
AD		 1071/**
1072 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1073 * @adapter: driver private struct
1074 **/
1075static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1076{
1077
1078 /* Do the reset outside of interrupt context */
1079 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1080 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1081 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1082 ixgbe_service_event_schedule(adapter);
1083 }
1084}
e01c31a5 1085
9a799d71
AK		 1086/**
1087 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1088 * @q_vector: structure containing interrupt and ring information
e01c31a5 1089 * @tx_ring: tx ring to clean
9a799d71 1090 **/
fe49f04a 1091static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1092 struct ixgbe_ring *tx_ring)
9a799d71 1093{
fe49f04a 1094 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1095 struct ixgbe_tx_buffer *tx_buffer;
1096 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1097 unsigned int total_bytes = 0, total_packets = 0;
59224555 1098 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1099 unsigned int i = tx_ring->next_to_clean;
1100
1101 if (test_bit(__IXGBE_DOWN, &adapter->state))
1102 return true;
9a799d71 1103
d3d00239 1104 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1105 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1106 i -= tx_ring->count;
12207e49 1107
729739b7 1108 do {
d3d00239
AD		 1109 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1110
1111 /* if next_to_watch is not set then there is no work pending */
1112 if (!eop_desc)
1113 break;
1114
7f83a9e6 1115 /* prevent any other reads prior to eop_desc */
7e63bf49 1116 read_barrier_depends();
7f83a9e6 1117
d3d00239
AD		 1118 /* if DD is not set pending work has not been completed */
1119 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1120 break;
8ad494b0 1121
d3d00239
AD		 1122 /* clear next_to_watch to prevent false hangs */
1123 tx_buffer->next_to_watch = NULL;
8ad494b0 1124
091a6246
AD		 1125 /* update the statistics for this packet */
1126 total_bytes += tx_buffer->bytecount;
1127 total_packets += tx_buffer->gso_segs;
1128
fd0db0ed 1129 /* free the skb */
fe1f2a97 1130 dev_consume_skb_any(tx_buffer->skb);
fd0db0ed 1131
729739b7
AD		 1132 /* unmap skb header data */
1133 dma_unmap_single(tx_ring->dev,
1134 dma_unmap_addr(tx_buffer, dma),
1135 dma_unmap_len(tx_buffer, len),
1136 DMA_TO_DEVICE);
1137
fd0db0ed
AD		 1138 /* clear tx_buffer data */
1139 tx_buffer->skb = NULL;
729739b7 1140 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1141
729739b7
AD		 1142 /* unmap remaining buffers */
1143 while (tx_desc != eop_desc) {
d3d00239
AD		 1144 tx_buffer++;
1145 tx_desc++;
8ad494b0 1146 i++;
729739b7
AD		 1147 if (unlikely(!i)) {
1148 i -= tx_ring->count;
d3d00239 1149 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1150 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1151 }
e01c31a5 1152
729739b7
AD		 1153 /* unmap any remaining paged data */
1154 if (dma_unmap_len(tx_buffer, len)) {
1155 dma_unmap_page(tx_ring->dev,
1156 dma_unmap_addr(tx_buffer, dma),
1157 dma_unmap_len(tx_buffer, len),
1158 DMA_TO_DEVICE);
1159 dma_unmap_len_set(tx_buffer, len, 0);
1160 }
1161 }
1162
1163 /* move us one more past the eop_desc for start of next pkt */
1164 tx_buffer++;
1165 tx_desc++;
1166 i++;
1167 if (unlikely(!i)) {
1168 i -= tx_ring->count;
1169 tx_buffer = tx_ring->tx_buffer_info;
1170 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1171 }
1172
1173 /* issue prefetch for next Tx descriptor */
1174 prefetch(tx_desc);
12207e49 1175
729739b7
AD		 1176 /* update budget accounting */
1177 budget--;
1178 } while (likely(budget));
1179
1180 i += tx_ring->count;
9a799d71 1181 tx_ring->next_to_clean = i;
d3d00239 1182 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1183 tx_ring->stats.bytes += total_bytes;
bd198058 1184 tx_ring->stats.packets += total_packets;
d3d00239 1185 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1186 q_vector->tx.total_bytes += total_bytes;
1187 q_vector->tx.total_packets += total_packets;
b953799e 1188
c84d324c
JF		 1189 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1190 /* schedule immediate reset if we believe we hung */
1191 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1192 e_err(drv, "Detected Tx Unit Hang\n"
1193 " Tx Queue <%d>\n"
1194 " TDH, TDT <%x>, <%x>\n"
1195 " next_to_use <%x>\n"
1196 " next_to_clean <%x>\n"
1197 "tx_buffer_info[next_to_clean]\n"
1198 " time_stamp <%lx>\n"
1199 " jiffies <%lx>\n",
1200 tx_ring->queue_index,
1201 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1202 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1203 tx_ring->next_to_use, i,
1204 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1205
1206 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1207
1208 e_info(probe,
1209 "tx hang %d detected on queue %d, resetting adapter\n",
1210 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1211
b953799e 1212 /* schedule immediate reset if we believe we hung */
c83c6cbd 1213 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1214
1215 /* the adapter is about to reset, no point in enabling stuff */
59224555 1216 return true;
b953799e 1217 }
9a799d71 1218
b2d96e0a
AD		 1219 netdev_tx_completed_queue(txring_txq(tx_ring),
1220 total_packets, total_bytes);
1221
e092be60 1222#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1223 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1224 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1225 /* Make sure that anybody stopping the queue after this
1226 * sees the new next_to_clean.
1227 */
1228 smp_mb();
729739b7
AD		 1229 if (__netif_subqueue_stopped(tx_ring->netdev,
1230 tx_ring->queue_index)
1231 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1232 netif_wake_subqueue(tx_ring->netdev,
1233 tx_ring->queue_index);
5b7da515 1234 ++tx_ring->tx_stats.restart_queue;
30eba97a 1235 }
e092be60 1236 }
9a799d71 1237
59224555 1238 return !!budget;
9a799d71
AK		 1239}
1240
5dd2d332 1241#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1242static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1243 struct ixgbe_ring *tx_ring,
33cf09c9 1244 int cpu)
bd0362dd 1245{
33cf09c9 1246 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1247 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1248 u16 reg_offset;
33cf09c9 1249
33cf09c9
AD		 1250 switch (hw->mac.type) {
1251 case ixgbe_mac_82598EB:
bdda1a61 1252 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1253 break;
1254 case ixgbe_mac_82599EB:
b93a2226 1255 case ixgbe_mac_X540:
bdda1a61
AD		 1256 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1257 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1258 break;
1259 default:
bdda1a61
AD		 1260 /* for unknown hardware do not write register */
1261 return;
bd0362dd 1262 }
bdda1a61
AD		 1263
1264 /*
1265 * We can enable relaxed ordering for reads, but not writes when
1266 * DCA is enabled. This is due to a known issue in some chipsets
1267 * which will cause the DCA tag to be cleared.
1268 */
1269 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1270 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1271 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1272
1273 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1274}
1275
bdda1a61
AD		 1276static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1277 struct ixgbe_ring *rx_ring,
33cf09c9 1278 int cpu)
bd0362dd 1279{
33cf09c9 1280 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1281 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1282 u8 reg_idx = rx_ring->reg_idx;
1283
33cf09c9
AD		 1284
1285 switch (hw->mac.type) {
33cf09c9 1286 case ixgbe_mac_82599EB:
b93a2226 1287 case ixgbe_mac_X540:
bdda1a61 1288 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1289 break;
1290 default:
1291 break;
1292 }
bdda1a61
AD		 1293
1294 /*
1295 * We can enable relaxed ordering for reads, but not writes when
1296 * DCA is enabled. This is due to a known issue in some chipsets
1297 * which will cause the DCA tag to be cleared.
1298 */
1299 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1300 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1301
1302 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1303}
1304
1305static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1306{
1307 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1308 struct ixgbe_ring *ring;
bd0362dd 1309 int cpu = get_cpu();
bd0362dd 1310
33cf09c9
AD		 1311 if (q_vector->cpu == cpu)
1312 goto out_no_update;
1313
a557928e 1314 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1315 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1316
a557928e 1317 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1318 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1319
1320 q_vector->cpu = cpu;
1321out_no_update:
bd0362dd
JC		 1322 put_cpu();
1323}
1324
1325static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1326{
1327 int i;
1328
1329 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1330 return;
1331
e35ec126
AD		 1332 /* always use CB2 mode, difference is masked in the CB driver */
1333 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1334
49c7ffbe 1335 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1336 adapter->q_vector[i]->cpu = -1;
1337 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1338 }
1339}
1340
1341static int __ixgbe_notify_dca(struct device *dev, void *data)
1342{
c60fbb00 1343 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1344 unsigned long event = *(unsigned long *)data;
1345
2a72c31e 1346 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1347 return 0;
1348
bd0362dd
JC		 1349 switch (event) {
1350 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1351 /* if we're already enabled, don't do it again */
1352 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1353 break;
652f093f 1354 if (dca_add_requester(dev) == 0) {
96b0e0f6 1355 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1356 ixgbe_setup_dca(adapter);
1357 break;
1358 }
1359 /* Fall Through since DCA is disabled. */
1360 case DCA_PROVIDER_REMOVE:
1361 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1362 dca_remove_requester(dev);
1363 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1364 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1365 }
1366 break;
1367 }
1368
652f093f 1369 return 0;
bd0362dd 1370}
67a74ee2 1371
bdda1a61 1372#endif /* CONFIG_IXGBE_DCA */
7edda4b8
FD		 1373
1374#define IXGBE_RSS_L4_TYPES_MASK \
1375 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1376 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1377 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1378 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1379
8a0da21b
AD		 1380static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1381 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1382 struct sk_buff *skb)
1383{
7edda4b8
FD		 1384 u16 rss_type;
1385
1386 if (!(ring->netdev->features & NETIF_F_RXHASH))
1387 return;
1388
1389 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1390 IXGBE_RXDADV_RSSTYPE_MASK;
1391
1392 if (!rss_type)
1393 return;
1394
1395 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1396 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1397 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
67a74ee2
ET		 1398}
1399
f800326d 1400#ifdef IXGBE_FCOE
ff886dfc
AD		 1401/**
1402 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1403 * @ring: structure containing ring specific data
ff886dfc
AD		 1404 * @rx_desc: advanced rx descriptor
1405 *
1406 * Returns : true if it is FCoE pkt
1407 */
57efd44c 1408static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1409 union ixgbe_adv_rx_desc *rx_desc)
1410{
1411 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1412
57efd44c 1413 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1414 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1415 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1416 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1417}
1418
f800326d 1419#endif /* IXGBE_FCOE */
e59bd25d
AV		 1420/**
1421 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1422 * @ring: structure containing ring specific data
1423 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1424 * @skb: skb currently being received and modified
1425 **/
8a0da21b 1426static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1427 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1428 struct sk_buff *skb)
9a799d71 1429{
3f207800
DS		 1430 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1431 __le16 hdr_info = rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1432 bool encap_pkt = false;
1433
8a0da21b 1434 skb_checksum_none_assert(skb);
9a799d71 1435
712744be 1436 /* Rx csum disabled */
8a0da21b 1437 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1438 return;
e59bd25d 1439
3f207800
DS		 1440 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) &&
1441 (hdr_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_TUNNEL >> 16))) {
1442 encap_pkt = true;
1443 skb->encapsulation = 1;
3f207800
DS		 1444 }
1445
e59bd25d 1446 /* if IP and error */
f56e0cb1
AD		 1447 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1448 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1449 ring->rx_stats.csum_err++;
9a799d71
AK		 1450 return;
1451 }
e59bd25d 1452
f56e0cb1 1453 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1454 return;
1455
f56e0cb1 1456 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1457 /*
1458 * 82599 errata, UDP frames with a 0 checksum can be marked as
1459 * checksum errors.
1460 */
8a0da21b
AD		 1461 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1462 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1463 return;
1464
8a0da21b 1465 ring->rx_stats.csum_err++;
e59bd25d
AV		 1466 return;
1467 }
1468
9a799d71 1469 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1470 skb->ip_summed = CHECKSUM_UNNECESSARY;
3f207800
DS		 1471 if (encap_pkt) {
1472 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1473 return;
1474
1475 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1476 ring->rx_stats.csum_err++;
1477 return;
1478 }
1479 /* If we checked the outer header let the stack know */
1480 skb->csum_level = 1;
1481 }
9a799d71
AK		 1482}
1483
f990b79b
AD		 1484static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1485 struct ixgbe_rx_buffer *bi)
1486{
1487 struct page *page = bi->page;
18cb652a 1488 dma_addr_t dma;
f990b79b 1489
f800326d 1490 /* since we are recycling buffers we should seldom need to alloc */
18cb652a 1491 if (likely(page))
f990b79b
AD		 1492 return true;
1493
f800326d 1494 /* alloc new page for storage */
18cb652a
AD		 1495 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1496 if (unlikely(!page)) {
1497 rx_ring->rx_stats.alloc_rx_page_failed++;
1498 return false;
f990b79b
AD		 1499 }
1500
f800326d
AD		 1501 /* map page for use */
1502 dma = dma_map_page(rx_ring->dev, page, 0,
1503 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1504
1505 /*
1506 * if mapping failed free memory back to system since
1507 * there isn't much point in holding memory we can't use
1508 */
1509 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1510 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f990b79b 1511
f990b79b
AD		 1512 rx_ring->rx_stats.alloc_rx_page_failed++;
1513 return false;
1514 }
1515
f800326d 1516 bi->dma = dma;
18cb652a 1517 bi->page = page;
afaa9459 1518 bi->page_offset = 0;
f800326d 1519
f990b79b
AD		 1520 return true;
1521}
1522
9a799d71 1523/**
f990b79b 1524 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1525 * @rx_ring: ring to place buffers on
1526 * @cleaned_count: number of buffers to replace
9a799d71 1527 **/
fc77dc3c 1528void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1529{
9a799d71 1530 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1531 struct ixgbe_rx_buffer *bi;
d5f398ed 1532 u16 i = rx_ring->next_to_use;
9a799d71 1533
f800326d
AD		 1534 /* nothing to do */
1535 if (!cleaned_count)
fc77dc3c
AD		 1536 return;
1537
e4f74028 1538 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1539 bi = &rx_ring->rx_buffer_info[i];
1540 i -= rx_ring->count;
9a799d71 1541
f800326d
AD		 1542 do {
1543 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1544 break;
d5f398ed 1545
f800326d
AD		 1546 /*
1547 * Refresh the desc even if buffer_addrs didn't change
1548 * because each write-back erases this info.
1549 */
1550 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1551
f990b79b
AD		 1552 rx_desc++;
1553 bi++;
9a799d71 1554 i++;
f990b79b 1555 if (unlikely(!i)) {
e4f74028 1556 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1557 bi = rx_ring->rx_buffer_info;
1558 i -= rx_ring->count;
1559 }
1560
18cb652a
AD		 1561 /* clear the status bits for the next_to_use descriptor */
1562 rx_desc->wb.upper.status_error = 0;
f800326d
AD		 1563
1564 cleaned_count--;
1565 } while (cleaned_count);
7c6e0a43 1566
f990b79b
AD		 1567 i += rx_ring->count;
1568
ad435ec6
AD		 1569 if (rx_ring->next_to_use != i) {
1570 rx_ring->next_to_use = i;
1571
1572 /* update next to alloc since we have filled the ring */
1573 rx_ring->next_to_alloc = i;
1574
1575 /* Force memory writes to complete before letting h/w
1576 * know there are new descriptors to fetch. (Only
1577 * applicable for weak-ordered memory model archs,
1578 * such as IA-64).
1579 */
1580 wmb();
1581 writel(i, rx_ring->tail);
1582 }
9a799d71
AK		 1583}
1584
1d2024f6
AD		 1585static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1586 struct sk_buff *skb)
1587{
f800326d 1588 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1589
1590 /* set gso_size to avoid messing up TCP MSS */
1591 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1592 IXGBE_CB(skb)->append_cnt);
96be80ab 1593 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1594}
1595
1596static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1597 struct sk_buff *skb)
1598{
1599 /* if append_cnt is 0 then frame is not RSC */
1600 if (!IXGBE_CB(skb)->append_cnt)
1601 return;
1602
1603 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1604 rx_ring->rx_stats.rsc_flush++;
1605
1606 ixgbe_set_rsc_gso_size(rx_ring, skb);
1607
1608 /* gso_size is computed using append_cnt so always clear it last */
1609 IXGBE_CB(skb)->append_cnt = 0;
1610}
1611
8a0da21b
AD		 1612/**
1613 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1614 * @rx_ring: rx descriptor ring packet is being transacted on
1615 * @rx_desc: pointer to the EOP Rx descriptor
1616 * @skb: pointer to current skb being populated
f8212f97 1617 *
8a0da21b
AD		 1618 * This function checks the ring, descriptor, and packet information in
1619 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1620 * other fields within the skb.
f8212f97 1621 **/
8a0da21b
AD		 1622static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1623 union ixgbe_adv_rx_desc *rx_desc,
1624 struct sk_buff *skb)
f8212f97 1625{
43e95f11
JF		 1626 struct net_device *dev = rx_ring->netdev;
1627
8a0da21b
AD		 1628 ixgbe_update_rsc_stats(rx_ring, skb);
1629
1630 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1631
8a0da21b
AD		 1632 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1633
eda183c2
JK		 1634 if (unlikely(ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_TS)))
1635 ixgbe_ptp_rx_hwtstamp(rx_ring->q_vector->adapter, skb);
3a6a4eda 1636
f646968f 1637 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1638 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1639 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1640 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1641 }
1642
8a0da21b 1643 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1644
43e95f11 1645 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1646}
1647
8a0da21b
AD		 1648static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1649 struct sk_buff *skb)
aa80175a 1650{
b4640030 1651 if (ixgbe_qv_busy_polling(q_vector))
5a85e737 1652 netif_receive_skb(skb);
8a0da21b 1653 else
856f606e 1654 napi_gro_receive(&q_vector->napi, skb);
aa80175a 1655}
43634e82 1656
f800326d
AD		 1657/**
1658 * ixgbe_is_non_eop - process handling of non-EOP buffers
1659 * @rx_ring: Rx ring being processed
1660 * @rx_desc: Rx descriptor for current buffer
1661 * @skb: Current socket buffer containing buffer in progress
1662 *
1663 * This function updates next to clean. If the buffer is an EOP buffer
1664 * this function exits returning false, otherwise it will place the
1665 * sk_buff in the next buffer to be chained and return true indicating
1666 * that this is in fact a non-EOP buffer.
1667 **/
1668static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1669 union ixgbe_adv_rx_desc *rx_desc,
1670 struct sk_buff *skb)
1671{
1672 u32 ntc = rx_ring->next_to_clean + 1;
1673
1674 /* fetch, update, and store next to clean */
1675 ntc = (ntc < rx_ring->count) ? ntc : 0;
1676 rx_ring->next_to_clean = ntc;
1677
1678 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1679
5a02cbd1
AD		 1680 /* update RSC append count if present */
1681 if (ring_is_rsc_enabled(rx_ring)) {
1682 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1683 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1684
1685 if (unlikely(rsc_enabled)) {
1686 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1687
1688 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1689 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1690
5a02cbd1
AD		 1691 /* update ntc based on RSC value */
1692 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1693 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1694 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1695 }
f800326d
AD		 1696 }
1697
5a02cbd1
AD		 1698 /* if we are the last buffer then there is nothing else to do */
1699 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1700 return false;
1701
f800326d
AD		 1702 /* place skb in next buffer to be received */
1703 rx_ring->rx_buffer_info[ntc].skb = skb;
1704 rx_ring->rx_stats.non_eop_descs++;
1705
1706 return true;
1707}
1708
19861ce2
AD		 1709/**
1710 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1711 * @rx_ring: rx descriptor ring packet is being transacted on
1712 * @skb: pointer to current skb being adjusted
1713 *
1714 * This function is an ixgbe specific version of __pskb_pull_tail. The
1715 * main difference between this version and the original function is that
1716 * this function can make several assumptions about the state of things
1717 * that allow for significant optimizations versus the standard function.
1718 * As a result we can do things like drop a frag and maintain an accurate
1719 * truesize for the skb.
1720 */
1721static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1722 struct sk_buff *skb)
1723{
1724 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1725 unsigned char *va;
1726 unsigned int pull_len;
1727
1728 /*
1729 * it is valid to use page_address instead of kmap since we are
1730 * working with pages allocated out of the lomem pool per
1731 * alloc_page(GFP_ATOMIC)
1732 */
1733 va = skb_frag_address(frag);
1734
1735 /*
1736 * we need the header to contain the greater of either ETH_HLEN or
1737 * 60 bytes if the skb->len is less than 60 for skb_pad.
1738 */
8496e338 1739 pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1740
1741 /* align pull length to size of long to optimize memcpy performance */
1742 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1743
1744 /* update all of the pointers */
1745 skb_frag_size_sub(frag, pull_len);
1746 frag->page_offset += pull_len;
1747 skb->data_len -= pull_len;
1748 skb->tail += pull_len;
19861ce2
AD		 1749}
1750
42073d91
AD		 1751/**
1752 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1753 * @rx_ring: rx descriptor ring packet is being transacted on
1754 * @skb: pointer to current skb being updated
1755 *
1756 * This function provides a basic DMA sync up for the first fragment of an
1757 * skb. The reason for doing this is that the first fragment cannot be
1758 * unmapped until we have reached the end of packet descriptor for a buffer
1759 * chain.
1760 */
1761static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1762 struct sk_buff *skb)
1763{
1764 /* if the page was released unmap it, else just sync our portion */
1765 if (unlikely(IXGBE_CB(skb)->page_released)) {
1766 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1767 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1768 IXGBE_CB(skb)->page_released = false;
1769 } else {
1770 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1771
1772 dma_sync_single_range_for_cpu(rx_ring->dev,
1773 IXGBE_CB(skb)->dma,
1774 frag->page_offset,
1775 ixgbe_rx_bufsz(rx_ring),
1776 DMA_FROM_DEVICE);
1777 }
1778 IXGBE_CB(skb)->dma = 0;
1779}
1780
f800326d
AD		 1781/**
1782 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1783 * @rx_ring: rx descriptor ring packet is being transacted on
1784 * @rx_desc: pointer to the EOP Rx descriptor
1785 * @skb: pointer to current skb being fixed
1786 *
1787 * Check for corrupted packet headers caused by senders on the local L2
1788 * embedded NIC switch not setting up their Tx Descriptors right. These
1789 * should be very rare.
1790 *
1791 * Also address the case where we are pulling data in on pages only
1792 * and as such no data is present in the skb header.
1793 *
1794 * In addition if skb is not at least 60 bytes we need to pad it so that
1795 * it is large enough to qualify as a valid Ethernet frame.
1796 *
1797 * Returns true if an error was encountered and skb was freed.
1798 **/
1799static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1800 union ixgbe_adv_rx_desc *rx_desc,
1801 struct sk_buff *skb)
1802{
f800326d 1803 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1804
1805 /* verify that the packet does not have any known errors */
1806 if (unlikely(ixgbe_test_staterr(rx_desc,
1807 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1808 !(netdev->features & NETIF_F_RXALL))) {
1809 dev_kfree_skb_any(skb);
1810 return true;
1811 }
1812
19861ce2 1813 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1814 if (skb_is_nonlinear(skb))
1815 ixgbe_pull_tail(rx_ring, skb);
f800326d 1816
57efd44c
AD		 1817#ifdef IXGBE_FCOE
1818 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1819 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1820 return false;
1821
1822#endif
a94d9e22
AD		 1823 /* if eth_skb_pad returns an error the skb was freed */
1824 if (eth_skb_pad(skb))
1825 return true;
f800326d
AD		 1826
1827 return false;
1828}
1829
f800326d
AD		 1830/**
1831 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1832 * @rx_ring: rx descriptor ring to store buffers on
1833 * @old_buff: donor buffer to have page reused
1834 *
0549ae20 1835 * Synchronizes page for reuse by the adapter
f800326d
AD		 1836 **/
1837static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1838 struct ixgbe_rx_buffer *old_buff)
1839{
1840 struct ixgbe_rx_buffer *new_buff;
1841 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1842
1843 new_buff = &rx_ring->rx_buffer_info[nta];
1844
1845 /* update, and store next to alloc */
1846 nta++;
1847 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1848
1849 /* transfer page from old buffer to new buffer */
18cb652a 1850 *new_buff = *old_buff;
f800326d
AD		 1851
1852 /* sync the buffer for use by the device */
1853 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1854 new_buff->page_offset,
1855 ixgbe_rx_bufsz(rx_ring),
f800326d 1856 DMA_FROM_DEVICE);
f800326d
AD		 1857}
1858
18cb652a
AD		 1859static inline bool ixgbe_page_is_reserved(struct page *page)
1860{
2f064f34 1861 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
18cb652a
AD		 1862}
1863
f800326d
AD		 1864/**
1865 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1866 * @rx_ring: rx descriptor ring to transact packets on
1867 * @rx_buffer: buffer containing page to add
1868 * @rx_desc: descriptor containing length of buffer written by hardware
1869 * @skb: sk_buff to place the data into
1870 *
0549ae20
AD		 1871 * This function will add the data contained in rx_buffer->page to the skb.
1872 * This is done either through a direct copy if the data in the buffer is
1873 * less than the skb header size, otherwise it will just attach the page as
1874 * a frag to the skb.
1875 *
1876 * The function will then update the page offset if necessary and return
1877 * true if the buffer can be reused by the adapter.
f800326d 1878 **/
0549ae20 1879static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1880 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1881 union ixgbe_adv_rx_desc *rx_desc,
1882 struct sk_buff *skb)
f800326d 1883{
0549ae20
AD		 1884 struct page *page = rx_buffer->page;
1885 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1886#if (PAGE_SIZE < 8192)
0549ae20 1887 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1888#else
1889 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1890 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1891 ixgbe_rx_bufsz(rx_ring);
1892#endif
0549ae20 1893
cf3fe7ac
AD		 1894 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1895 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1896
1897 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1898
18cb652a
AD		 1899 /* page is not reserved, we can reuse buffer as-is */
1900 if (likely(!ixgbe_page_is_reserved(page)))
cf3fe7ac
AD		 1901 return true;
1902
1903 /* this page cannot be reused so discard it */
18cb652a 1904 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
cf3fe7ac
AD		 1905 return false;
1906 }
1907
0549ae20
AD		 1908 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1909 rx_buffer->page_offset, size, truesize);
1910
09816fbe 1911 /* avoid re-using remote pages */
18cb652a 1912 if (unlikely(ixgbe_page_is_reserved(page)))
09816fbe
AD		 1913 return false;
1914
1915#if (PAGE_SIZE < 8192)
1916 /* if we are only owner of page we can reuse it */
1917 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1918 return false;
1919
1920 /* flip page offset to other buffer */
1921 rx_buffer->page_offset ^= truesize;
09816fbe
AD		 1922#else
1923 /* move offset up to the next cache line */
1924 rx_buffer->page_offset += truesize;
1925
1926 if (rx_buffer->page_offset > last_offset)
1927 return false;
09816fbe 1928#endif
0549ae20 1929
18cb652a
AD		 1930 /* Even if we own the page, we are not allowed to use atomic_set()
1931 * This would break get_page_unless_zero() users.
1932 */
1933 atomic_inc(&page->_count);
1934
0549ae20 1935 return true;
f800326d
AD		 1936}
1937
18806c9e
AD		 1938static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1939 union ixgbe_adv_rx_desc *rx_desc)
1940{
1941 struct ixgbe_rx_buffer *rx_buffer;
1942 struct sk_buff *skb;
1943 struct page *page;
1944
1945 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1946 page = rx_buffer->page;
1947 prefetchw(page);
1948
1949 skb = rx_buffer->skb;
1950
1951 if (likely(!skb)) {
1952 void *page_addr = page_address(page) +
1953 rx_buffer->page_offset;
1954
1955 /* prefetch first cache line of first page */
1956 prefetch(page_addr);
1957#if L1_CACHE_BYTES < 128
1958 prefetch(page_addr + L1_CACHE_BYTES);
1959#endif
1960
1961 /* allocate a skb to store the frags */
67fd893e
AD		 1962 skb = napi_alloc_skb(&rx_ring->q_vector->napi,
1963 IXGBE_RX_HDR_SIZE);
18806c9e
AD		 1964 if (unlikely(!skb)) {
1965 rx_ring->rx_stats.alloc_rx_buff_failed++;
1966 return NULL;
1967 }
1968
1969 /*
1970 * we will be copying header into skb->data in
1971 * pskb_may_pull so it is in our interest to prefetch
1972 * it now to avoid a possible cache miss
1973 */
1974 prefetchw(skb->data);
1975
1976 /*
1977 * Delay unmapping of the first packet. It carries the
1978 * header information, HW may still access the header
1979 * after the writeback. Only unmap it when EOP is
1980 * reached
1981 */
1982 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1983 goto dma_sync;
1984
1985 IXGBE_CB(skb)->dma = rx_buffer->dma;
1986 } else {
1987 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1988 ixgbe_dma_sync_frag(rx_ring, skb);
1989
1990dma_sync:
1991 /* we are reusing so sync this buffer for CPU use */
1992 dma_sync_single_range_for_cpu(rx_ring->dev,
1993 rx_buffer->dma,
1994 rx_buffer->page_offset,
1995 ixgbe_rx_bufsz(rx_ring),
1996 DMA_FROM_DEVICE);
18cb652a
AD		 1997
1998 rx_buffer->skb = NULL;
18806c9e
AD		 1999 }
2000
2001 /* pull page into skb */
2002 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2003 /* hand second half of page back to the ring */
2004 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2005 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2006 /* the page has been released from the ring */
2007 IXGBE_CB(skb)->page_released = true;
2008 } else {
2009 /* we are not reusing the buffer so unmap it */
2010 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2011 ixgbe_rx_pg_size(rx_ring),
2012 DMA_FROM_DEVICE);
2013 }
2014
2015 /* clear contents of buffer_info */
18806c9e
AD		 2016 rx_buffer->page = NULL;
2017
2018 return skb;
f800326d
AD		 2019}
2020
2021/**
2022 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2023 * @q_vector: structure containing interrupt and ring information
2024 * @rx_ring: rx descriptor ring to transact packets on
2025 * @budget: Total limit on number of packets to process
2026 *
2027 * This function provides a "bounce buffer" approach to Rx interrupt
2028 * processing. The advantage to this is that on systems that have
2029 * expensive overhead for IOMMU access this provides a means of avoiding
2030 * it by maintaining the mapping of the page to the syste.
2031 *
5a85e737 2032 * Returns amount of work completed
f800326d 2033 **/
5a85e737 2034static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2035 struct ixgbe_ring *rx_ring,
f4de00ed 2036 const int budget)
9a799d71 2037{
d2f4fbe2 2038 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2039#ifdef IXGBE_FCOE
f800326d 2040 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2041 int ddp_bytes;
2042 unsigned int mss = 0;
3d8fd385 2043#endif /* IXGBE_FCOE */
f800326d 2044 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2045
fdabfc8a 2046 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2047 union ixgbe_adv_rx_desc *rx_desc;
2048 struct sk_buff *skb;
f800326d
AD		 2049
2050 /* return some buffers to hardware, one at a time is too slow */
2051 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2052 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2053 cleaned_count = 0;
2054 }
2055
18806c9e 2056 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d 2057
124b74c1 2058 if (!rx_desc->wb.upper.status_error)
f800326d 2059 break;
9a799d71 2060
124b74c1 2061 /* This memory barrier is needed to keep us from reading
f800326d 2062 * any other fields out of the rx_desc until we know the
124b74c1 2063 * descriptor has been written back
f800326d 2064 */
124b74c1 2065 dma_rmb();
9a799d71 2066
18806c9e
AD		 2067 /* retrieve a buffer from the ring */
2068 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2069
18806c9e
AD		 2070 /* exit if we failed to retrieve a buffer */
2071 if (!skb)
2072 break;
9a799d71 2073
9a799d71 2074 cleaned_count++;
f8212f97 2075
f800326d
AD		 2076 /* place incomplete frames back on ring for completion */
2077 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2078 continue;
c267fc16 2079
f800326d
AD		 2080 /* verify the packet layout is correct */
2081 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2082 continue;
9a799d71 2083
d2f4fbe2
AV		 2084 /* probably a little skewed due to removing CRC */
2085 total_rx_bytes += skb->len;
d2f4fbe2 2086
8a0da21b
AD		 2087 /* populate checksum, timestamp, VLAN, and protocol */
2088 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2089
332d4a7d
YZ		 2090#ifdef IXGBE_FCOE
2091 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2092 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2093 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2094 /* include DDPed FCoE data */
2095 if (ddp_bytes > 0) {
2096 if (!mss) {
2097 mss = rx_ring->netdev->mtu -
2098 sizeof(struct fcoe_hdr) -
2099 sizeof(struct fc_frame_header) -
2100 sizeof(struct fcoe_crc_eof);
2101 if (mss > 512)
2102 mss &= ~511;
2103 }
2104 total_rx_bytes += ddp_bytes;
2105 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2106 mss);
2107 }
63d635b2
AD		 2108 if (!ddp_bytes) {
2109 dev_kfree_skb_any(skb);
f800326d 2110 continue;
63d635b2 2111 }
3d8fd385 2112 }
f800326d 2113
332d4a7d 2114#endif /* IXGBE_FCOE */
8b80cda5 2115 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2116 ixgbe_rx_skb(q_vector, skb);
9a799d71 2117
f800326d 2118 /* update budget accounting */
f4de00ed 2119 total_rx_packets++;
fdabfc8a 2120 }
9a799d71 2121
c267fc16
AD		 2122 u64_stats_update_begin(&rx_ring->syncp);
2123 rx_ring->stats.packets += total_rx_packets;
2124 rx_ring->stats.bytes += total_rx_bytes;
2125 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2126 q_vector->rx.total_packets += total_rx_packets;
2127 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2128
5a85e737 2129 return total_rx_packets;
9a799d71
AK		 2130}
2131
e0d1095a 2132#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2133/* must be called with local_bh_disable()d */
2134static int ixgbe_low_latency_recv(struct napi_struct *napi)
2135{
2136 struct ixgbe_q_vector *q_vector =
2137 container_of(napi, struct ixgbe_q_vector, napi);
2138 struct ixgbe_adapter *adapter = q_vector->adapter;
2139 struct ixgbe_ring *ring;
2140 int found = 0;
2141
2142 if (test_bit(__IXGBE_DOWN, &adapter->state))
2143 return LL_FLUSH_FAILED;
2144
2145 if (!ixgbe_qv_lock_poll(q_vector))
2146 return LL_FLUSH_BUSY;
2147
2148 ixgbe_for_each_ring(ring, q_vector->rx) {
2149 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2150#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2151 if (found)
2152 ring->stats.cleaned += found;
2153 else
2154 ring->stats.misses++;
2155#endif
5a85e737
ET		 2156 if (found)
2157 break;
2158 }
2159
2160 ixgbe_qv_unlock_poll(q_vector);
2161
2162 return found;
2163}
e0d1095a 2164#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2165
9a799d71
AK		 2166/**
2167 * ixgbe_configure_msix - Configure MSI-X hardware
2168 * @adapter: board private structure
2169 *
2170 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2171 * interrupts.
2172 **/
2173static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2174{
021230d4 2175 struct ixgbe_q_vector *q_vector;
49c7ffbe 2176 int v_idx;
021230d4 2177 u32 mask;
9a799d71 2178
8e34d1aa
AD		 2179 /* Populate MSIX to EITR Select */
2180 if (adapter->num_vfs > 32) {
2181 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2182 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2183 }
2184
4df10466
JB		 2185 /*
2186 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2187 * corresponding register.
2188 */
49c7ffbe 2189 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2190 struct ixgbe_ring *ring;
7a921c93 2191 q_vector = adapter->q_vector[v_idx];
021230d4 2192
a557928e 2193 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2194 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2195
a557928e 2196 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2197 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2198
fe49f04a 2199 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2200 }
2201
bd508178
AD		 2202 switch (adapter->hw.mac.type) {
2203 case ixgbe_mac_82598EB:
e8e26350 2204 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2205 v_idx);
bd508178
AD		 2206 break;
2207 case ixgbe_mac_82599EB:
b93a2226 2208 case ixgbe_mac_X540:
9a75a1ac
DS		 2209 case ixgbe_mac_X550:
2210 case ixgbe_mac_X550EM_x:
e8e26350 2211 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2212 break;
bd508178
AD		 2213 default:
2214 break;
2215 }
021230d4
AV		 2216 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2217
41fb9248 2218 /* set up to autoclear timer, and the vectors */
021230d4 2219 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2220 mask &= ~(IXGBE_EIMS_OTHER |
2221 IXGBE_EIMS_MAILBOX |
2222 IXGBE_EIMS_LSC);
2223
021230d4 2224 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2225}
2226
f494e8fa
AV		 2227enum latency_range {
2228 lowest_latency = 0,
2229 low_latency = 1,
2230 bulk_latency = 2,
2231 latency_invalid = 255
2232};
2233
2234/**
2235 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2236 * @q_vector: structure containing interrupt and ring information
2237 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2238 *
2239 * Stores a new ITR value based on packets and byte
2240 * counts during the last interrupt. The advantage of per interrupt
2241 * computation is faster updates and more accurate ITR for the current
2242 * traffic pattern. Constants in this function were computed
2243 * based on theoretical maximum wire speed and thresholds were set based
2244 * on testing data as well as attempting to minimize response time
2245 * while increasing bulk throughput.
2246 * this functionality is controlled by the InterruptThrottleRate module
2247 * parameter (see ixgbe_param.c)
2248 **/
bd198058
AD		 2249static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2250 struct ixgbe_ring_container *ring_container)
f494e8fa 2251{
bd198058
AD		 2252 int bytes = ring_container->total_bytes;
2253 int packets = ring_container->total_packets;
2254 u32 timepassed_us;
621bd70e 2255 u64 bytes_perint;
bd198058 2256 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2257
2258 if (packets == 0)
bd198058 2259 return;
f494e8fa
AV		 2260
2261 /* simple throttlerate management
621bd70e
AD		 2262 * 0-10MB/s lowest (100000 ints/s)
2263 * 10-20MB/s low (20000 ints/s)
2264 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2265 */
2266 /* what was last interrupt timeslice? */
d5bf4f67 2267 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2268 if (timepassed_us == 0)
2269 return;
2270
f494e8fa
AV		 2271 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2272
2273 switch (itr_setting) {
2274 case lowest_latency:
621bd70e 2275 if (bytes_perint > 10)
bd198058 2276 itr_setting = low_latency;
f494e8fa
AV		 2277 break;
2278 case low_latency:
621bd70e 2279 if (bytes_perint > 20)
bd198058 2280 itr_setting = bulk_latency;
621bd70e 2281 else if (bytes_perint <= 10)
bd198058 2282 itr_setting = lowest_latency;
f494e8fa
AV		 2283 break;
2284 case bulk_latency:
621bd70e 2285 if (bytes_perint <= 20)
bd198058 2286 itr_setting = low_latency;
f494e8fa
AV		 2287 break;
2288 }
2289
bd198058
AD		 2290 /* clear work counters since we have the values we need */
2291 ring_container->total_bytes = 0;
2292 ring_container->total_packets = 0;
2293
2294 /* write updated itr to ring container */
2295 ring_container->itr = itr_setting;
f494e8fa
AV		 2296}
2297
509ee935
JB		 2298/**
2299 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2300 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2301 *
2302 * This function is made to be called by ethtool and by the driver
2303 * when it needs to update EITR registers at runtime. Hardware
2304 * specific quirks/differences are taken care of here.
2305 */
fe49f04a 2306void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2307{
fe49f04a 2308 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2309 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2310 int v_idx = q_vector->v_idx;
5d967eb7 2311 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2312
bd508178
AD		 2313 switch (adapter->hw.mac.type) {
2314 case ixgbe_mac_82598EB:
509ee935
JB		 2315 /* must write high and low 16 bits to reset counter */
2316 itr_reg |= (itr_reg << 16);
bd508178
AD		 2317 break;
2318 case ixgbe_mac_82599EB:
b93a2226 2319 case ixgbe_mac_X540:
9a75a1ac
DS		 2320 case ixgbe_mac_X550:
2321 case ixgbe_mac_X550EM_x:
509ee935
JB		 2322 /*
2323 * set the WDIS bit to not clear the timer bits and cause an
2324 * immediate assertion of the interrupt
2325 */
2326 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2327 break;
2328 default:
2329 break;
509ee935
JB		 2330 }
2331 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2332}
2333
bd198058 2334static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2335{
d5bf4f67 2336 u32 new_itr = q_vector->itr;
bd198058 2337 u8 current_itr;
f494e8fa 2338
bd198058
AD		 2339 ixgbe_update_itr(q_vector, &q_vector->tx);
2340 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2341
08c8833b 2342 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2343
2344 switch (current_itr) {
2345 /* counts and packets in update_itr are dependent on these numbers */
2346 case lowest_latency:
d5bf4f67 2347 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2348 break;
2349 case low_latency:
d5bf4f67 2350 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2351 break;
2352 case bulk_latency:
d5bf4f67 2353 new_itr = IXGBE_8K_ITR;
f494e8fa 2354 break;
bd198058
AD		 2355 default:
2356 break;
f494e8fa
AV		 2357 }
2358
d5bf4f67 2359 if (new_itr != q_vector->itr) {
fe49f04a 2360 /* do an exponential smoothing */
d5bf4f67
ET		 2361 new_itr = (10 * new_itr * q_vector->itr) /
2362 ((9 * new_itr) + q_vector->itr);
509ee935 2363
bd198058 2364 /* save the algorithm value here */
5d967eb7 2365 q_vector->itr = new_itr;
fe49f04a
AD		 2366
2367 ixgbe_write_eitr(q_vector);
f494e8fa 2368 }
f494e8fa
AV		 2369}
2370
119fc60a 2371/**
de88eeeb 2372 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2373 * @adapter: pointer to adapter
119fc60a 2374 **/
f0f9778d 2375static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2376{
119fc60a
MC		 2377 struct ixgbe_hw *hw = &adapter->hw;
2378 u32 eicr = adapter->interrupt_event;
2379
f0f9778d 2380 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2381 return;
2382
f0f9778d
AD		 2383 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2384 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2385 return;
2386
2387 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2388
7ca647bd 2389 switch (hw->device_id) {
f0f9778d
AD		 2390 case IXGBE_DEV_ID_82599_T3_LOM:
2391 /*
2392 * Since the warning interrupt is for both ports
2393 * we don't have to check if:
2394 * - This interrupt wasn't for our port.
2395 * - We may have missed the interrupt so always have to
2396 * check if we got a LSC
2397 */
9a900eca 2398 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
f0f9778d
AD		 2399 !(eicr & IXGBE_EICR_LSC))
2400 return;
2401
2402 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2403 u32 speed;
f0f9778d 2404 bool link_up = false;
7ca647bd 2405
3d292265 2406 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2407
f0f9778d
AD		 2408 if (link_up)
2409 return;
2410 }
2411
2412 /* Check if this is not due to overtemp */
2413 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2414 return;
2415
2416 break;
7ca647bd 2417 default:
597f22d6
DS		 2418 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2419 return;
9a900eca 2420 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
119fc60a 2421 return;
7ca647bd 2422 break;
119fc60a 2423 }
f44e751b 2424 e_crit(drv, "%s\n", ixgbe_overheat_msg);
f0f9778d
AD		 2425
2426 adapter->interrupt_event = 0;
119fc60a
MC		 2427}
2428
0befdb3e
JB		 2429static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2430{
2431 struct ixgbe_hw *hw = &adapter->hw;
2432
2433 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
9a900eca 2434 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
396e799c 2435 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e 2436 /* write to clear the interrupt */
9a900eca 2437 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
0befdb3e
JB		 2438 }
2439}
cf8280ee 2440
4f51bf70
JK		 2441static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2442{
9a900eca
DS		 2443 struct ixgbe_hw *hw = &adapter->hw;
2444
4f51bf70
JK		 2445 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2446 return;
2447
2448 switch (adapter->hw.mac.type) {
2449 case ixgbe_mac_82599EB:
2450 /*
2451 * Need to check link state so complete overtemp check
2452 * on service task
2453 */
9a900eca
DS		 2454 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2455 (eicr & IXGBE_EICR_LSC)) &&
4f51bf70
JK		 2456 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2457 adapter->interrupt_event = eicr;
2458 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2459 ixgbe_service_event_schedule(adapter);
2460 return;
2461 }
2462 return;
2463 case ixgbe_mac_X540:
2464 if (!(eicr & IXGBE_EICR_TS))
2465 return;
2466 break;
2467 default:
2468 return;
2469 }
2470
f44e751b 2471 e_crit(drv, "%s\n", ixgbe_overheat_msg);
4f51bf70
JK		 2472}
2473
45788d2a
DS		 2474static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2475{
2476 switch (hw->mac.type) {
2477 case ixgbe_mac_82598EB:
2478 if (hw->phy.type == ixgbe_phy_nl)
2479 return true;
2480 return false;
2481 case ixgbe_mac_82599EB:
2482 case ixgbe_mac_X550EM_x:
2483 switch (hw->mac.ops.get_media_type(hw)) {
2484 case ixgbe_media_type_fiber:
2485 case ixgbe_media_type_fiber_qsfp:
2486 return true;
2487 default:
2488 return false;
2489 }
2490 default:
2491 return false;
2492 }
2493}
2494
e8e26350
PW		 2495static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2496{
2497 struct ixgbe_hw *hw = &adapter->hw;
2498
9a900eca 2499 if (eicr & IXGBE_EICR_GPI_SDP2(hw)) {
73c4b7cd 2500 /* Clear the interrupt */
9a900eca 2501 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2(hw));
7086400d
AD		 2502 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2503 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2504 ixgbe_service_event_schedule(adapter);
2505 }
73c4b7cd
AD		 2506 }
2507
9a900eca 2508 if (eicr & IXGBE_EICR_GPI_SDP1(hw)) {
e8e26350 2509 /* Clear the interrupt */
9a900eca 2510 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
7086400d
AD		 2511 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2512 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2513 ixgbe_service_event_schedule(adapter);
2514 }
e8e26350
PW		 2515 }
2516}
2517
cf8280ee
JB		 2518static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2519{
2520 struct ixgbe_hw *hw = &adapter->hw;
2521
2522 adapter->lsc_int++;
2523 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2524 adapter->link_check_timeout = jiffies;
2525 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2526 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2527 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2528 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2529 }
2530}
2531
fe49f04a
AD		 2532static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2533 u64 qmask)
2534{
2535 u32 mask;
bd508178 2536 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2537
bd508178
AD		 2538 switch (hw->mac.type) {
2539 case ixgbe_mac_82598EB:
fe49f04a 2540 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2541 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2542 break;
2543 case ixgbe_mac_82599EB:
b93a2226 2544 case ixgbe_mac_X540:
9a75a1ac
DS		 2545 case ixgbe_mac_X550:
2546 case ixgbe_mac_X550EM_x:
fe49f04a 2547 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2548 if (mask)
2549 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2550 mask = (qmask >> 32);
bd508178
AD		 2551 if (mask)
2552 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2553 break;
2554 default:
2555 break;
fe49f04a
AD		 2556 }
2557 /* skip the flush */
2558}
2559
2560static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2561 u64 qmask)
fe49f04a
AD		 2562{
2563 u32 mask;
bd508178 2564 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2565
bd508178
AD		 2566 switch (hw->mac.type) {
2567 case ixgbe_mac_82598EB:
fe49f04a 2568 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2569 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2570 break;
2571 case ixgbe_mac_82599EB:
b93a2226 2572 case ixgbe_mac_X540:
9a75a1ac
DS		 2573 case ixgbe_mac_X550:
2574 case ixgbe_mac_X550EM_x:
fe49f04a 2575 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2576 if (mask)
2577 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2578 mask = (qmask >> 32);
bd508178
AD		 2579 if (mask)
2580 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2581 break;
2582 default:
2583 break;
fe49f04a
AD		 2584 }
2585 /* skip the flush */
2586}
2587
021230d4 2588/**
2c4af694
AD		 2589 * ixgbe_irq_enable - Enable default interrupt generation settings
2590 * @adapter: board private structure
021230d4 2591 **/
2c4af694
AD		 2592static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2593 bool flush)
9a799d71 2594{
9a900eca 2595 struct ixgbe_hw *hw = &adapter->hw;
2c4af694 2596 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2597
2c4af694
AD		 2598 /* don't reenable LSC while waiting for link */
2599 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2600 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2601
2c4af694 2602 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2603 switch (adapter->hw.mac.type) {
2604 case ixgbe_mac_82599EB:
9a900eca 2605 mask |= IXGBE_EIMS_GPI_SDP0(hw);
4f51bf70
JK		 2606 break;
2607 case ixgbe_mac_X540:
9a75a1ac
DS		 2608 case ixgbe_mac_X550:
2609 case ixgbe_mac_X550EM_x:
4f51bf70
JK		 2610 mask |= IXGBE_EIMS_TS;
2611 break;
2612 default:
2613 break;
2614 }
2c4af694 2615 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 2616 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2c4af694
AD		 2617 switch (adapter->hw.mac.type) {
2618 case ixgbe_mac_82599EB:
9a900eca
DS		 2619 mask |= IXGBE_EIMS_GPI_SDP1(hw);
2620 mask |= IXGBE_EIMS_GPI_SDP2(hw);
9a75a1ac 2621 /* fall through */
858bc081 2622 case ixgbe_mac_X540:
9a75a1ac
DS		 2623 case ixgbe_mac_X550:
2624 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2625 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
2626 mask |= IXGBE_EICR_GPI_SDP0_X540;
858bc081 2627 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2628 mask |= IXGBE_EIMS_MAILBOX;
2629 break;
2630 default:
2631 break;
9a799d71 2632 }
db0677fa 2633
2c4af694
AD		 2634 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2635 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2636 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2637
2c4af694
AD		 2638 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2639 if (queues)
2640 ixgbe_irq_enable_queues(adapter, ~0);
2641 if (flush)
2642 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2643}
2644
2c4af694 2645static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2646{
a65151ba 2647 struct ixgbe_adapter *adapter = data;
9a799d71 2648 struct ixgbe_hw *hw = &adapter->hw;
54037505 2649 u32 eicr;
91281fd3 2650
54037505
DS		 2651 /*
2652 * Workaround for Silicon errata. Use clear-by-write instead
2653 * of clear-by-read. Reading with EICS will return the
2654 * interrupt causes without clearing, which later be done
2655 * with the write to EICR.
2656 */
2657 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2658
2659 /* The lower 16bits of the EICR register are for the queue interrupts
dbedd44e 2660 * which should be masked here in order to not accidentally clear them if
d87d8307
JK		 2661 * the bits are high when ixgbe_msix_other is called. There is a race
2662 * condition otherwise which results in possible performance loss
2663 * especially if the ixgbe_msix_other interrupt is triggering
2664 * consistently (as it would when PPS is turned on for the X540 device)
2665 */
2666 eicr &= 0xFFFF0000;
2667
54037505 2668 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2669
cf8280ee
JB		 2670 if (eicr & IXGBE_EICR_LSC)
2671 ixgbe_check_lsc(adapter);
f0848276 2672
1cdd1ec8
GR		 2673 if (eicr & IXGBE_EICR_MAILBOX)
2674 ixgbe_msg_task(adapter);
efe3d3c8 2675
bd508178
AD		 2676 switch (hw->mac.type) {
2677 case ixgbe_mac_82599EB:
b93a2226 2678 case ixgbe_mac_X540:
9a75a1ac
DS		 2679 case ixgbe_mac_X550:
2680 case ixgbe_mac_X550EM_x:
597f22d6
DS		 2681 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
2682 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
2683 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
2684 ixgbe_service_event_schedule(adapter);
2685 IXGBE_WRITE_REG(hw, IXGBE_EICR,
2686 IXGBE_EICR_GPI_SDP0_X540);
2687 }
d773ce2d
DS		 2688 if (eicr & IXGBE_EICR_ECC) {
2689 e_info(link, "Received ECC Err, initiating reset\n");
2690 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2691 ixgbe_service_event_schedule(adapter);
2692 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2693 }
c4cf55e5
PWJ		 2694 /* Handle Flow Director Full threshold interrupt */
2695 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2696 int reinit_count = 0;
c4cf55e5 2697 int i;
c4cf55e5 2698 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2699 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2700 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2701 &ring->state))
2702 reinit_count++;
2703 }
2704 if (reinit_count) {
2705 /* no more flow director interrupts until after init */
2706 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2707 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2708 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2709 }
2710 }
f0f9778d 2711 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2712 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2713 break;
2714 default:
2715 break;
c4cf55e5 2716 }
f0848276 2717
bd508178 2718 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2719
db0677fa
JK		 2720 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2721 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2722
7086400d 2723 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2724 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2725 ixgbe_irq_enable(adapter, false, false);
f0848276 2726
9a799d71 2727 return IRQ_HANDLED;
f0848276 2728}
91281fd3 2729
4ff7fb12 2730static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2731{
021230d4 2732 struct ixgbe_q_vector *q_vector = data;
91281fd3 2733
9b471446 2734 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2735
4ff7fb12
AD		 2736 if (q_vector->rx.ring || q_vector->tx.ring)
2737 napi_schedule(&q_vector->napi);
91281fd3 2738
9a799d71 2739 return IRQ_HANDLED;
91281fd3
AD		 2740}
2741
eb01b975
AD		 2742/**
2743 * ixgbe_poll - NAPI Rx polling callback
2744 * @napi: structure for representing this polling device
2745 * @budget: how many packets driver is allowed to clean
2746 *
2747 * This function is used for legacy and MSI, NAPI mode
2748 **/
8af3c33f 2749int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2750{
2751 struct ixgbe_q_vector *q_vector =
2752 container_of(napi, struct ixgbe_q_vector, napi);
2753 struct ixgbe_adapter *adapter = q_vector->adapter;
2754 struct ixgbe_ring *ring;
2755 int per_ring_budget;
2756 bool clean_complete = true;
2757
2758#ifdef CONFIG_IXGBE_DCA
2759 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2760 ixgbe_update_dca(q_vector);
2761#endif
2762
2763 ixgbe_for_each_ring(ring, q_vector->tx)
2764 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2765
5a85e737
ET		 2766 if (!ixgbe_qv_lock_napi(q_vector))
2767 return budget;
2768
eb01b975
AD		 2769 /* attempt to distribute budget to each queue fairly, but don't allow
2770 * the budget to go below 1 because we'll exit polling */
2771 if (q_vector->rx.count > 1)
2772 per_ring_budget = max(budget/q_vector->rx.count, 1);
2773 else
2774 per_ring_budget = budget;
2775
2776 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2777 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2778 per_ring_budget) < per_ring_budget);
eb01b975 2779
5a85e737 2780 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2781 /* If all work not completed, return budget and keep polling */
2782 if (!clean_complete)
2783 return budget;
2784
2785 /* all work done, exit the polling mode */
2786 napi_complete(napi);
2787 if (adapter->rx_itr_setting & 1)
2788 ixgbe_set_itr(q_vector);
2789 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2790 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2791
2792 return 0;
2793}
2794
021230d4
AV		 2795/**
2796 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2797 * @adapter: board private structure
2798 *
2799 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2800 * interrupts from the kernel.
2801 **/
2802static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2803{
2804 struct net_device *netdev = adapter->netdev;
207867f5 2805 int vector, err;
e8e9f696 2806 int ri = 0, ti = 0;
021230d4 2807
49c7ffbe 2808 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2809 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2810 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2811
4ff7fb12 2812 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2813 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2814 "%s-%s-%d", netdev->name, "TxRx", ri++);
2815 ti++;
2816 } else if (q_vector->rx.ring) {
9fe93afd 2817 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2818 "%s-%s-%d", netdev->name, "rx", ri++);
2819 } else if (q_vector->tx.ring) {
9fe93afd 2820 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2821 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2822 } else {
2823 /* skip this unused q_vector */
2824 continue;
32aa77a4 2825 }
207867f5
AD		 2826 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2827 q_vector->name, q_vector);
9a799d71 2828 if (err) {
396e799c 2829 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2830 "Error: %d\n", err);
021230d4 2831 goto free_queue_irqs;
9a799d71 2832 }
207867f5
AD		 2833 /* If Flow Director is enabled, set interrupt affinity */
2834 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2835 /* assign the mask for this irq */
2836 irq_set_affinity_hint(entry->vector,
de88eeeb 2837 &q_vector->affinity_mask);
207867f5 2838 }
9a799d71
AK		 2839 }
2840
021230d4 2841 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2842 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2843 if (err) {
de88eeeb 2844 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2845 goto free_queue_irqs;
9a799d71
AK		 2846 }
2847
9a799d71
AK		 2848 return 0;
2849
021230d4 2850free_queue_irqs:
207867f5
AD		 2851 while (vector) {
2852 vector--;
2853 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2854 NULL);
2855 free_irq(adapter->msix_entries[vector].vector,
2856 adapter->q_vector[vector]);
2857 }
021230d4
AV		 2858 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2859 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2860 kfree(adapter->msix_entries);
2861 adapter->msix_entries = NULL;
9a799d71
AK		 2862 return err;
2863}
2864
2865/**
021230d4 2866 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2867 * @irq: interrupt number
2868 * @data: pointer to a network interface device structure
9a799d71
AK		 2869 **/
2870static irqreturn_t ixgbe_intr(int irq, void *data)
2871{
a65151ba 2872 struct ixgbe_adapter *adapter = data;
9a799d71 2873 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2874 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2875 u32 eicr;
2876
54037505 2877 /*
24ddd967 2878 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2879 * before the read of EICR.
2880 */
2881 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2882
021230d4 2883 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2884 * therefore no explicit interrupt disable is necessary */
021230d4 2885 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2886 if (!eicr) {
6af3b9eb
ET		 2887 /*
2888 * shared interrupt alert!
f47cf66e 2889 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2890 * have disabled interrupts due to EIAM
2891 * finish the workaround of silicon errata on 82598. Unmask
2892 * the interrupt that we masked before the EICR read.
2893 */
2894 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2895 ixgbe_irq_enable(adapter, true, true);
9a799d71 2896 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2897 }
9a799d71 2898
cf8280ee
JB		 2899 if (eicr & IXGBE_EICR_LSC)
2900 ixgbe_check_lsc(adapter);
021230d4 2901
bd508178
AD		 2902 switch (hw->mac.type) {
2903 case ixgbe_mac_82599EB:
e8e26350 2904 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2905 /* Fall through */
2906 case ixgbe_mac_X540:
9a75a1ac
DS		 2907 case ixgbe_mac_X550:
2908 case ixgbe_mac_X550EM_x:
d773ce2d
DS		 2909 if (eicr & IXGBE_EICR_ECC) {
2910 e_info(link, "Received ECC Err, initiating reset\n");
2911 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2912 ixgbe_service_event_schedule(adapter);
2913 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2914 }
4f51bf70 2915 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2916 break;
2917 default:
2918 break;
2919 }
e8e26350 2920
0befdb3e 2921 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2922 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2923 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2924
b9f6ed2b
AD		 2925 /* would disable interrupts here but EIAM disabled it */
2926 napi_schedule(&q_vector->napi);
9a799d71 2927
6af3b9eb
ET		 2928 /*
2929 * re-enable link(maybe) and non-queue interrupts, no flush.
2930 * ixgbe_poll will re-enable the queue interrupts
2931 */
6af3b9eb
ET		 2932 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2933 ixgbe_irq_enable(adapter, false, false);
2934
9a799d71
AK		 2935 return IRQ_HANDLED;
2936}
2937
2938/**
2939 * ixgbe_request_irq - initialize interrupts
2940 * @adapter: board private structure
2941 *
2942 * Attempts to configure interrupts using the best available
2943 * capabilities of the hardware and kernel.
2944 **/
021230d4 2945static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2946{
2947 struct net_device *netdev = adapter->netdev;
021230d4 2948 int err;
9a799d71 2949
4cc6df29 2950 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2951 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2952 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2953 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2954 netdev->name, adapter);
4cc6df29 2955 else
a0607fd3 2956 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2957 netdev->name, adapter);
9a799d71 2958
de88eeeb 2959 if (err)
396e799c 2960 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2961
9a799d71
AK		 2962 return err;
2963}
2964
2965static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2966{
49c7ffbe 2967 int vector;
9a799d71 2968
49c7ffbe
AD		 2969 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2970 free_irq(adapter->pdev->irq, adapter);
2971 return;
2972 }
4cc6df29 2973
49c7ffbe
AD		 2974 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2975 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2976 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2977
49c7ffbe
AD		 2978 /* free only the irqs that were actually requested */
2979 if (!q_vector->rx.ring && !q_vector->tx.ring)
2980 continue;
207867f5 2981
49c7ffbe
AD		 2982 /* clear the affinity_mask in the IRQ descriptor */
2983 irq_set_affinity_hint(entry->vector, NULL);
2984
2985 free_irq(entry->vector, q_vector);
9a799d71 2986 }
49c7ffbe
AD		 2987
2988 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2989}
2990
22d5a71b
JB		 2991/**
2992 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2993 * @adapter: board private structure
2994 **/
2995static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2996{
bd508178
AD		 2997 switch (adapter->hw.mac.type) {
2998 case ixgbe_mac_82598EB:
835462fc 2999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3000 break;
3001 case ixgbe_mac_82599EB:
b93a2226 3002 case ixgbe_mac_X540:
9a75a1ac
DS		 3003 case ixgbe_mac_X550:
3004 case ixgbe_mac_X550EM_x:
835462fc
NS		 3005 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3006 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3007 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3008 break;
3009 default:
3010 break;
22d5a71b
JB		 3011 }
3012 IXGBE_WRITE_FLUSH(&adapter->hw);
3013 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3014 int vector;
3015
3016 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3017 synchronize_irq(adapter->msix_entries[vector].vector);
3018
3019 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3020 } else {
3021 synchronize_irq(adapter->pdev->irq);
3022 }
3023}
3024
9a799d71
AK		 3025/**
3026 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3027 *
3028 **/
3029static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3030{
d5bf4f67 3031 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3032
d5bf4f67 3033 ixgbe_write_eitr(q_vector);
9a799d71 3034
e8e26350
PW		 3035 ixgbe_set_ivar(adapter, 0, 0, 0);
3036 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3037
396e799c 3038 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3039}
3040
43e69bf0
AD		 3041/**
3042 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3043 * @adapter: board private structure
3044 * @ring: structure containing ring specific data
3045 *
3046 * Configure the Tx descriptor ring after a reset.
3047 **/
84418e3b
AD		 3048void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3049 struct ixgbe_ring *ring)
43e69bf0
AD		 3050{
3051 struct ixgbe_hw *hw = &adapter->hw;
3052 u64 tdba = ring->dma;
2f1860b8 3053 int wait_loop = 10;
b88c6de2 3054 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3055 u8 reg_idx = ring->reg_idx;
43e69bf0 3056
2f1860b8 3057 /* disable queue to avoid issues while updating state */
b88c6de2 3058 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3059 IXGBE_WRITE_FLUSH(hw);
3060
43e69bf0 3061 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3062 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3063 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3064 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3065 ring->count * sizeof(union ixgbe_adv_tx_desc));
3066 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3067 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3068 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3069
b88c6de2
AD		 3070 /*
3071 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3072 * higher than 1 when:
3073 * - ITR is 0 as it could cause false TX hangs
3074 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3075 *
3076 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3077 * to or less than the number of on chip descriptors, which is
3078 * currently 40.
3079 */
67da097e 3080 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
b88c6de2
AD		 3081 txdctl |= (1 << 16); /* WTHRESH = 1 */
3082 else
3083 txdctl |= (8 << 16); /* WTHRESH = 8 */
3084
e954b374
AD		 3085 /*
3086 * Setting PTHRESH to 32 both improves performance
3087 * and avoids a TX hang with DFP enabled
3088 */
b88c6de2
AD		 3089 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3090 32; /* PTHRESH = 32 */
2f1860b8
AD		 3091
3092 /* reinitialize flowdirector state */
39cb681b 3093 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3094 ring->atr_sample_rate = adapter->atr_sample_rate;
3095 ring->atr_count = 0;
3096 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3097 } else {
3098 ring->atr_sample_rate = 0;
3099 }
2f1860b8 3100
fd786b7b
AD		 3101 /* initialize XPS */
3102 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3103 struct ixgbe_q_vector *q_vector = ring->q_vector;
3104
3105 if (q_vector)
2a47fa45 3106 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3107 &q_vector->affinity_mask,
3108 ring->queue_index);
3109 }
3110
c84d324c
JF		 3111 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3112
2f1860b8 3113 /* enable queue */
2f1860b8
AD		 3114 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3115
3116 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3117 if (hw->mac.type == ixgbe_mac_82598EB &&
3118 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3119 return;
3120
3121 /* poll to verify queue is enabled */
3122 do {
032b4325 3123 usleep_range(1000, 2000);
2f1860b8
AD		 3124 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3125 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3126 if (!wait_loop)
3127 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3128}
3129
120ff942
AD		 3130static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3131{
3132 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3133 u32 rttdcs, mtqc;
8b1c0b24 3134 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3135
3136 if (hw->mac.type == ixgbe_mac_82598EB)
3137 return;
3138
3139 /* disable the arbiter while setting MTQC */
3140 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3141 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3142 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3143
3144 /* set transmit pool layout */
671c0adb
AD		 3145 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3146 mtqc = IXGBE_MTQC_VT_ENA;
3147 if (tcs > 4)
3148 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3149 else if (tcs > 1)
3150 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3151 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3152 mtqc |= IXGBE_MTQC_32VF;
3153 else
3154 mtqc |= IXGBE_MTQC_64VF;
3155 } else {
3156 if (tcs > 4)
3157 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3158 else if (tcs > 1)
3159 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3160 else
671c0adb
AD		 3161 mtqc = IXGBE_MTQC_64Q_1PB;
3162 }
120ff942 3163
671c0adb 3164 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3165
671c0adb
AD		 3166 /* Enable Security TX Buffer IFG for multiple pb */
3167 if (tcs) {
3168 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3169 sectx |= IXGBE_SECTX_DCB;
3170 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3171 }
3172
3173 /* re-enable the arbiter */
3174 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3175 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3176}
3177
9a799d71 3178/**
3a581073 3179 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3180 * @adapter: board private structure
3181 *
3182 * Configure the Tx unit of the MAC after a reset.
3183 **/
3184static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3185{
2f1860b8
AD		 3186 struct ixgbe_hw *hw = &adapter->hw;
3187 u32 dmatxctl;
43e69bf0 3188 u32 i;
9a799d71 3189
2f1860b8
AD		 3190 ixgbe_setup_mtqc(adapter);
3191
3192 if (hw->mac.type != ixgbe_mac_82598EB) {
3193 /* DMATXCTL.EN must be before Tx queues are enabled */
3194 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3195 dmatxctl |= IXGBE_DMATXCTL_TE;
3196 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3197 }
3198
9a799d71 3199 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3200 for (i = 0; i < adapter->num_tx_queues; i++)
3201 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3202}
3203
3ebe8fde
AD		 3204static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3205 struct ixgbe_ring *ring)
3206{
3207 struct ixgbe_hw *hw = &adapter->hw;
3208 u8 reg_idx = ring->reg_idx;
3209 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3210
3211 srrctl |= IXGBE_SRRCTL_DROP_EN;
3212
3213 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3214}
3215
3216static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3217 struct ixgbe_ring *ring)
3218{
3219 struct ixgbe_hw *hw = &adapter->hw;
3220 u8 reg_idx = ring->reg_idx;
3221 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3222
3223 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3224
3225 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3226}
3227
3228#ifdef CONFIG_IXGBE_DCB
3229void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3230#else
3231static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3232#endif
3233{
3234 int i;
3235 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3236
3237 if (adapter->ixgbe_ieee_pfc)
3238 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3239
3240 /*
3241 * We should set the drop enable bit if:
3242 * SR-IOV is enabled
3243 * or
3244 * Number of Rx queues > 1 and flow control is disabled
3245 *
3246 * This allows us to avoid head of line blocking for security
3247 * and performance reasons.
3248 */
3249 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3250 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3251 for (i = 0; i < adapter->num_rx_queues; i++)
3252 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3253 } else {
3254 for (i = 0; i < adapter->num_rx_queues; i++)
3255 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3256 }
3257}
3258
e8e26350 3259#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3260
a6616b42 3261static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3262 struct ixgbe_ring *rx_ring)
cc41ac7c 3263{
45e9baa5 3264 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3265 u32 srrctl;
bf29ee6c 3266 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3267
45e9baa5
AD		 3268 if (hw->mac.type == ixgbe_mac_82598EB) {
3269 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3270
45e9baa5
AD		 3271 /*
3272 * if VMDq is not active we must program one srrctl register
3273 * per RSS queue since we have enabled RDRXCTL.MVMEN
3274 */
3275 reg_idx &= mask;
3276 }
cc41ac7c 3277
45e9baa5
AD		 3278 /* configure header buffer length, needed for RSC */
3279 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3280
45e9baa5 3281 /* configure the packet buffer length */
f800326d 3282 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3283
3284 /* configure descriptor type */
f800326d 3285 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3286
45e9baa5 3287 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3288}
9a799d71 3289
dfaf891d
VZ		 3290/**
3291 * Return a number of entries in the RSS indirection table
3292 *
3293 * @adapter: device handle
3294 *
3295 * - 82598/82599/X540: 128
3296 * - X550(non-SRIOV mode): 512
3297 * - X550(SRIOV mode): 64
3298 */
7f276efb 3299u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
dfaf891d
VZ		 3300{
3301 if (adapter->hw.mac.type < ixgbe_mac_X550)
3302 return 128;
3303 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3304 return 64;
3305 else
3306 return 512;
3307}
3308
3309/**
3310 * Write the RETA table to HW
3311 *
3312 * @adapter: device handle
3313 *
3314 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3315 */
3316static void ixgbe_store_reta(struct ixgbe_adapter *adapter)
0cefafad 3317{
dfaf891d 3318 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
05abb126 3319 struct ixgbe_hw *hw = &adapter->hw;
d1b849b9 3320 u32 reta = 0;
dfaf891d
VZ		 3321 u32 indices_multi;
3322 u8 *indir_tbl = adapter->rss_indir_tbl;
05abb126 3323
0f9b232b 3324 /* Fill out the redirection table as follows:
dfaf891d
VZ		 3325 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3326 * indices.
3327 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3328 * - X550: 8 bit wide entries containing 6 bit RSS index
0f9b232b
DS		 3329 */
3330 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3331 indices_multi = 0x11;
3332 else
3333 indices_multi = 0x1;
3334
dfaf891d
VZ		 3335 /* Write redirection table to HW */
3336 for (i = 0; i < reta_entries; i++) {
3337 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
0f9b232b
DS		 3338 if ((i & 3) == 3) {
3339 if (i < 128)
3340 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3341 else
3342 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3343 reta);
dfaf891d 3344 reta = 0;
0f9b232b
DS		 3345 }
3346 }
3347}
3348
dfaf891d
VZ		 3349/**
3350 * Write the RETA table to HW (for x550 devices in SRIOV mode)
3351 *
3352 * @adapter: device handle
3353 *
3354 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3355 */
3356static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
0f9b232b 3357{
dfaf891d 3358 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
0f9b232b
DS		 3359 struct ixgbe_hw *hw = &adapter->hw;
3360 u32 vfreta = 0;
dfaf891d
VZ		 3361 unsigned int pf_pool = adapter->num_vfs;
3362
3363 /* Write redirection table to HW */
3364 for (i = 0; i < reta_entries; i++) {
3365 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3366 if ((i & 3) == 3) {
3367 IXGBE_WRITE_REG(hw, IXGBE_PFVFRETA(i >> 2, pf_pool),
3368 vfreta);
3369 vfreta = 0;
3370 }
3371 }
3372}
3373
3374static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3375{
3376 struct ixgbe_hw *hw = &adapter->hw;
3377 u32 i, j;
3378 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3379 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3380
3381 /* Program table for at least 2 queues w/ SR-IOV so that VFs can
3382 * make full use of any rings they may have. We will use the
3383 * PSRTYPE register to control how many rings we use within the PF.
3384 */
3385 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3386 rss_i = 2;
3387
3388 /* Fill out hash function seeds */
3389 for (i = 0; i < 10; i++)
3390 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3391
3392 /* Fill out redirection table */
3393 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3394
3395 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3396 if (j == rss_i)
3397 j = 0;
3398
3399 adapter->rss_indir_tbl[i] = j;
3400 }
3401
3402 ixgbe_store_reta(adapter);
3403}
3404
3405static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3406{
3407 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b
DS		 3408 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3409 unsigned int pf_pool = adapter->num_vfs;
3410 int i, j;
3411
3412 /* Fill out hash function seeds */
3413 for (i = 0; i < 10; i++)
dfaf891d
VZ		 3414 IXGBE_WRITE_REG(hw, IXGBE_PFVFRSSRK(i, pf_pool),
3415 adapter->rss_key[i]);
0f9b232b
DS		 3416
3417 /* Fill out the redirection table */
3418 for (i = 0, j = 0; i < 64; i++, j++) {
671c0adb 3419 if (j == rss_i)
05abb126 3420 j = 0;
dfaf891d
VZ		 3421
3422 adapter->rss_indir_tbl[i] = j;
05abb126 3423 }
dfaf891d
VZ		 3424
3425 ixgbe_store_vfreta(adapter);
d1b849b9
DS		 3426}
3427
3428static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3429{
3430 struct ixgbe_hw *hw = &adapter->hw;
0f9b232b 3431 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
d1b849b9 3432 u32 rxcsum;
0cefafad 3433
05abb126
AD		 3434 /* Disable indicating checksum in descriptor, enables RSS hash */
3435 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3436 rxcsum |= IXGBE_RXCSUM_PCSD;
3437 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3438
671c0adb 3439 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3440 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3441 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3442 } else {
671c0adb
AD		 3443 u8 tcs = netdev_get_num_tc(adapter->netdev);
3444
3445 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3446 if (tcs > 4)
3447 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3448 else if (tcs > 1)
3449 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3450 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3451 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3452 else
671c0adb
AD		 3453 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3454 } else {
3455 if (tcs > 4)
8b1c0b24 3456 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3457 else if (tcs > 1)
3458 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3459 else
3460 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3461 }
0cefafad
JB		 3462 }
3463
05abb126 3464 /* Perform hash on these packet types */
d1b849b9
DS		 3465 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3466 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3467 IXGBE_MRQC_RSS_FIELD_IPV6 |
3468 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3469
ef6afc0c 3470 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
d1b849b9 3471 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
ef6afc0c 3472 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
d1b849b9 3473 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
ef6afc0c 3474
dfaf891d 3475 netdev_rss_key_fill(adapter->rss_key, sizeof(adapter->rss_key));
0f9b232b
DS		 3476 if ((hw->mac.type >= ixgbe_mac_X550) &&
3477 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
3478 unsigned int pf_pool = adapter->num_vfs;
3479
3480 /* Enable VF RSS mode */
3481 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
3482 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3483
3484 /* Setup RSS through the VF registers */
dfaf891d 3485 ixgbe_setup_vfreta(adapter);
0f9b232b
DS		 3486 vfmrqc = IXGBE_MRQC_RSSEN;
3487 vfmrqc |= rss_field;
3488 IXGBE_WRITE_REG(hw, IXGBE_PFVFMRQC(pf_pool), vfmrqc);
3489 } else {
dfaf891d 3490 ixgbe_setup_reta(adapter);
0f9b232b
DS		 3491 mrqc |= rss_field;
3492 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
3493 }
0cefafad
JB		 3494}
3495
bb5a9ad2
NS		 3496/**
3497 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3498 * @adapter: address of board private structure
3499 * @index: index of ring to set
bb5a9ad2 3500 **/
082757af 3501static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3502 struct ixgbe_ring *ring)
bb5a9ad2 3503{
bb5a9ad2 3504 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3505 u32 rscctrl;
bf29ee6c 3506 u8 reg_idx = ring->reg_idx;
7367096a 3507
7d637bcc 3508 if (!ring_is_rsc_enabled(ring))
7367096a 3509 return;
bb5a9ad2 3510
7367096a 3511 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3512 rscctrl |= IXGBE_RSCCTL_RSCEN;
3513 /*
3514 * we must limit the number of descriptors so that the
3515 * total size of max desc * buf_len is not greater
642c680e 3516 * than 65536
bb5a9ad2 3517 */
f800326d 3518 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3519 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3520}
3521
9e10e045
AD		 3522#define IXGBE_MAX_RX_DESC_POLL 10
3523static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3524 struct ixgbe_ring *ring)
3525{
3526 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3527 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3528 u32 rxdctl;
bf29ee6c 3529 u8 reg_idx = ring->reg_idx;
9e10e045 3530
b0483c8f
MR		 3531 if (ixgbe_removed(hw->hw_addr))
3532 return;
9e10e045
AD		 3533 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3534 if (hw->mac.type == ixgbe_mac_82598EB &&
3535 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3536 return;
3537
3538 do {
032b4325 3539 usleep_range(1000, 2000);
9e10e045
AD		 3540 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3541 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3542
3543 if (!wait_loop) {
3544 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3545 "the polling period\n", reg_idx);
3546 }
3547}
3548
2d39d576
YZ		 3549void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3550 struct ixgbe_ring *ring)
3551{
3552 struct ixgbe_hw *hw = &adapter->hw;
3553 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3554 u32 rxdctl;
3555 u8 reg_idx = ring->reg_idx;
3556
b0483c8f
MR		 3557 if (ixgbe_removed(hw->hw_addr))
3558 return;
2d39d576
YZ		 3559 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3560 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3561
3562 /* write value back with RXDCTL.ENABLE bit cleared */
3563 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3564
3565 if (hw->mac.type == ixgbe_mac_82598EB &&
3566 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3567 return;
3568
3569 /* the hardware may take up to 100us to really disable the rx queue */
3570 do {
3571 udelay(10);
3572 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3573 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3574
3575 if (!wait_loop) {
3576 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3577 "the polling period\n", reg_idx);
3578 }
3579}
3580
84418e3b
AD		 3581void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3582 struct ixgbe_ring *ring)
acd37177
AD		 3583{
3584 struct ixgbe_hw *hw = &adapter->hw;
3585 u64 rdba = ring->dma;
9e10e045 3586 u32 rxdctl;
bf29ee6c 3587 u8 reg_idx = ring->reg_idx;
acd37177 3588
9e10e045
AD		 3589 /* disable queue to avoid issues while updating state */
3590 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3591 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3592
acd37177
AD		 3593 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3594 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3595 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3596 ring->count * sizeof(union ixgbe_adv_rx_desc));
3597 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3598 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3599 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3600
3601 ixgbe_configure_srrctl(adapter, ring);
3602 ixgbe_configure_rscctl(adapter, ring);
3603
3604 if (hw->mac.type == ixgbe_mac_82598EB) {
3605 /*
3606 * enable cache line friendly hardware writes:
3607 * PTHRESH=32 descriptors (half the internal cache),
3608 * this also removes ugly rx_no_buffer_count increment
3609 * HTHRESH=4 descriptors (to minimize latency on fetch)
3610 * WTHRESH=8 burst writeback up to two cache lines
3611 */
3612 rxdctl &= ~0x3FFFFF;
3613 rxdctl |= 0x080420;
3614 }
3615
3616 /* enable receive descriptor ring */
3617 rxdctl |= IXGBE_RXDCTL_ENABLE;
3618 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3619
3620 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3621 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3622}
3623
48654521
AD		 3624static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3625{
3626 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3627 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3628 u16 pool;
48654521
AD		 3629
3630 /* PSRTYPE must be initialized in non 82598 adapters */
3631 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3632 IXGBE_PSRTYPE_UDPHDR |
3633 IXGBE_PSRTYPE_IPV4HDR |
48654521 3634 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3635 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3636
3637 if (hw->mac.type == ixgbe_mac_82598EB)
3638 return;
3639
fbe7ca7f
AD		 3640 if (rss_i > 3)
3641 psrtype |= 2 << 29;
3642 else if (rss_i > 1)
3643 psrtype |= 1 << 29;
48654521 3644
2a47fa45
JF		 3645 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3646 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3647}
3648
f5b4a52e
AD		 3649static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3650{
3651 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3652 u32 reg_offset, vf_shift;
435b19f6 3653 u32 gcr_ext, vmdctl;
de4c7f65 3654 int i;
f5b4a52e
AD		 3655
3656 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3657 return;
3658
3659 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3660 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3661 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3662 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3663 vmdctl |= IXGBE_VT_CTL_REPLEN;
3664 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3665
1d9c0bfd
AD		 3666 vf_shift = VMDQ_P(0) % 32;
3667 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3668
3669 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3670 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3671 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3672 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3673 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
aa2bacb6 3674 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
9b735984 3675 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3676
3677 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3678 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3679
3680 /*
3681 * Set up VF register offsets for selected VT Mode,
3682 * i.e. 32 or 64 VFs for SR-IOV
3683 */
73079ea0
AD		 3684 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3685 case IXGBE_82599_VMDQ_8Q_MASK:
3686 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3687 break;
3688 case IXGBE_82599_VMDQ_4Q_MASK:
3689 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3690 break;
3691 default:
3692 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3693 break;
3694 }
3695
f5b4a52e
AD		 3696 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3697
435b19f6 3698
a985b6c3 3699 /* Enable MAC Anti-Spoofing */
435b19f6 3700 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3701 adapter->num_vfs);
5b7f000f
DS		 3702
3703 /* Ensure LLDP is set for Ethertype Antispoofing if we will be
3704 * calling set_ethertype_anti_spoofing for each VF in loop below
3705 */
3706 if (hw->mac.ops.set_ethertype_anti_spoofing)
3707 IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_LLDP),
3708 (IXGBE_ETQF_FILTER_EN | /* enable filter */
3709 IXGBE_ETQF_TX_ANTISPOOF | /* tx antispoof */
3710 IXGBE_ETH_P_LLDP)); /* LLDP eth type */
3711
de4c7f65
GR		 3712 /* For VFs that have spoof checking turned off */
3713 for (i = 0; i < adapter->num_vfs; i++) {
3714 if (!adapter->vfinfo[i].spoofchk_enabled)
3715 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
5b7f000f
DS		 3716
3717 /* enable ethertype anti spoofing if hw supports it */
3718 if (hw->mac.ops.set_ethertype_anti_spoofing)
3719 hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
e65ce0d3
VZ		 3720
3721 /* Enable/Disable RSS query feature */
3722 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
3723 adapter->vfinfo[i].rss_query_enabled);
de4c7f65 3724 }
f5b4a52e
AD		 3725}
3726
477de6ed 3727static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3728{
9a799d71
AK		 3729 struct ixgbe_hw *hw = &adapter->hw;
3730 struct net_device *netdev = adapter->netdev;
3731 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3732 struct ixgbe_ring *rx_ring;
3733 int i;
3734 u32 mhadd, hlreg0;
48654521 3735
63f39bd1 3736#ifdef IXGBE_FCOE
477de6ed
AD		 3737 /* adjust max frame to be able to do baby jumbo for FCoE */
3738 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3739 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3740 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3741
477de6ed 3742#endif /* IXGBE_FCOE */
872844dd
AD		 3743
3744 /* adjust max frame to be at least the size of a standard frame */
3745 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3746 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3747
477de6ed
AD		 3748 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3749 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3750 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3751 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3752
3753 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3754 }
3755
3756 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3757 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3758 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3759 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3760
0cefafad
JB		 3761 /*
3762 * Setup the HW Rx Head and Tail Descriptor Pointers and
3763 * the Base and Length of the Rx Descriptor Ring
3764 */
9a799d71 3765 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3766 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3767 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3768 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3769 else
7d637bcc 3770 clear_ring_rsc_enabled(rx_ring);
477de6ed 3771 }
477de6ed
AD		 3772}
3773
7367096a
AD		 3774static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3775{
3776 struct ixgbe_hw *hw = &adapter->hw;
3777 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3778
3779 switch (hw->mac.type) {
9a75a1ac
DS		 3780 case ixgbe_mac_X550:
3781 case ixgbe_mac_X550EM_x:
7367096a
AD		 3782 case ixgbe_mac_82598EB:
3783 /*
3784 * For VMDq support of different descriptor types or
3785 * buffer sizes through the use of multiple SRRCTL
3786 * registers, RDRXCTL.MVMEN must be set to 1
3787 *
3788 * also, the manual doesn't mention it clearly but DCA hints
3789 * will only use queue 0's tags unless this bit is set. Side
3790 * effects of setting this bit are only that SRRCTL must be
3791 * fully programmed [0..15]
3792 */
3793 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3794 break;
3795 case ixgbe_mac_82599EB:
b93a2226 3796 case ixgbe_mac_X540:
7367096a
AD		 3797 /* Disable RSC for ACK packets */
3798 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3799 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3800 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3801 /* hardware requires some bits to be set by default */
3802 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3803 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3804 break;
3805 default:
3806 /* We should do nothing since we don't know this hardware */
3807 return;
3808 }
3809
3810 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3811}
3812
477de6ed
AD		 3813/**
3814 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3815 * @adapter: board private structure
3816 *
3817 * Configure the Rx unit of the MAC after a reset.
3818 **/
3819static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3820{
3821 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3822 int i;
6dcc28b9 3823 u32 rxctrl, rfctl;
477de6ed
AD		 3824
3825 /* disable receives while setting up the descriptors */
1f9ac57c 3826 hw->mac.ops.disable_rx(hw);
477de6ed
AD		 3827
3828 ixgbe_setup_psrtype(adapter);
7367096a 3829 ixgbe_setup_rdrxctl(adapter);
477de6ed 3830
6dcc28b9
JK		 3831 /* RSC Setup */
3832 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3833 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3834 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3835 rfctl |= IXGBE_RFCTL_RSC_DIS;
3836 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3837
9e10e045 3838 /* Program registers for the distribution of queues */
f5b4a52e 3839 ixgbe_setup_mrqc(adapter);
f5b4a52e 3840
477de6ed
AD		 3841 /* set_rx_buffer_len must be called before ring initialization */
3842 ixgbe_set_rx_buffer_len(adapter);
3843
3844 /*
3845 * Setup the HW Rx Head and Tail Descriptor Pointers and
3846 * the Base and Length of the Rx Descriptor Ring
3847 */
9e10e045
AD		 3848 for (i = 0; i < adapter->num_rx_queues; i++)
3849 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3850
1f9ac57c 3851 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
9e10e045
AD		 3852 /* disable drop enable for 82598 parts */
3853 if (hw->mac.type == ixgbe_mac_82598EB)
3854 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3855
3856 /* enable all receives */
3857 rxctrl |= IXGBE_RXCTRL_RXEN;
3858 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3859}
3860
80d5c368
PM		 3861static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3862 __be16 proto, u16 vid)
068c89b0
DS		 3863{
3864 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3865 struct ixgbe_hw *hw = &adapter->hw;
3866
3867 /* add VID to filter table */
1d9c0bfd 3868 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3869 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3870
3871 return 0;
068c89b0
DS		 3872}
3873
80d5c368
PM		 3874static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3875 __be16 proto, u16 vid)
068c89b0
DS		 3876{
3877 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3878 struct ixgbe_hw *hw = &adapter->hw;
3879
068c89b0 3880 /* remove VID from filter table */
1d9c0bfd 3881 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3882 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3883
3884 return 0;
068c89b0
DS		 3885}
3886
f62bbb5e
JG		 3887/**
3888 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3889 * @adapter: driver data
3890 */
3891static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3892{
3893 struct ixgbe_hw *hw = &adapter->hw;
3894 u32 vlnctrl;
5f6c0181
JB		 3895 int i, j;
3896
3897 switch (hw->mac.type) {
3898 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3899 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3900 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3901 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3902 break;
3903 case ixgbe_mac_82599EB:
b93a2226 3904 case ixgbe_mac_X540:
9a75a1ac
DS		 3905 case ixgbe_mac_X550:
3906 case ixgbe_mac_X550EM_x:
5f6c0181 3907 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3908 struct ixgbe_ring *ring = adapter->rx_ring[i];
3909
3910 if (ring->l2_accel_priv)
3911 continue;
3912 j = ring->reg_idx;
5f6c0181
JB		 3913 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3914 vlnctrl &= ~IXGBE_RXDCTL_VME;
3915 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3916 }
3917 break;
3918 default:
3919 break;
3920 }
3921}
3922
3923/**
f62bbb5e 3924 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3925 * @adapter: driver data
3926 */
f62bbb5e 3927static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3928{
3929 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3930 u32 vlnctrl;
5f6c0181
JB		 3931 int i, j;
3932
3933 switch (hw->mac.type) {
3934 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3935 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3936 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3937 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3938 break;
3939 case ixgbe_mac_82599EB:
b93a2226 3940 case ixgbe_mac_X540:
9a75a1ac
DS		 3941 case ixgbe_mac_X550:
3942 case ixgbe_mac_X550EM_x:
5f6c0181 3943 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3944 struct ixgbe_ring *ring = adapter->rx_ring[i];
3945
3946 if (ring->l2_accel_priv)
3947 continue;
3948 j = ring->reg_idx;
5f6c0181
JB		 3949 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3950 vlnctrl |= IXGBE_RXDCTL_VME;
3951 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3952 }
3953 break;
3954 default:
3955 break;
3956 }
3957}
3958
9a799d71
AK		 3959static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3960{
f62bbb5e 3961 u16 vid;
9a799d71 3962
80d5c368 3963 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3964
3965 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3966 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3967}
3968
b335e75b
JK		 3969/**
3970 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
3971 * @netdev: network interface device structure
3972 *
3973 * Writes multicast address list to the MTA hash table.
3974 * Returns: -ENOMEM on failure
3975 * 0 on no addresses written
3976 * X on writing X addresses to MTA
3977 **/
3978static int ixgbe_write_mc_addr_list(struct net_device *netdev)
3979{
3980 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3981 struct ixgbe_hw *hw = &adapter->hw;
3982
3983 if (!netif_running(netdev))
3984 return 0;
3985
3986 if (hw->mac.ops.update_mc_addr_list)
3987 hw->mac.ops.update_mc_addr_list(hw, netdev);
3988 else
3989 return -ENOMEM;
3990
3991#ifdef CONFIG_PCI_IOV
5d7daa35 3992 ixgbe_restore_vf_multicasts(adapter);
b335e75b
JK		 3993#endif
3994
3995 return netdev_mc_count(netdev);
3996}
3997
5d7daa35
JK		 3998#ifdef CONFIG_PCI_IOV
3999void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4000{
4001 struct ixgbe_hw *hw = &adapter->hw;
4002 int i;
4003 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4004 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4005 hw->mac.ops.set_rar(hw, i, adapter->mac_table[i].addr,
4006 adapter->mac_table[i].queue,
4007 IXGBE_RAH_AV);
4008 else
4009 hw->mac.ops.clear_rar(hw, i);
4010
4011 adapter->mac_table[i].state &= ~(IXGBE_MAC_STATE_MODIFIED);
4012 }
4013}
4014#endif
4015
4016static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4017{
4018 struct ixgbe_hw *hw = &adapter->hw;
4019 int i;
4020 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4021 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_MODIFIED) {
4022 if (adapter->mac_table[i].state &
4023 IXGBE_MAC_STATE_IN_USE)
4024 hw->mac.ops.set_rar(hw, i,
4025 adapter->mac_table[i].addr,
4026 adapter->mac_table[i].queue,
4027 IXGBE_RAH_AV);
4028 else
4029 hw->mac.ops.clear_rar(hw, i);
4030
4031 adapter->mac_table[i].state &=
4032 ~(IXGBE_MAC_STATE_MODIFIED);
4033 }
4034 }
4035}
4036
4037static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4038{
4039 int i;
4040 struct ixgbe_hw *hw = &adapter->hw;
4041
4042 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4043 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4044 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4045 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4046 adapter->mac_table[i].queue = 0;
4047 }
4048 ixgbe_sync_mac_table(adapter);
4049}
4050
4051static int ixgbe_available_rars(struct ixgbe_adapter *adapter)
4052{
4053 struct ixgbe_hw *hw = &adapter->hw;
4054 int i, count = 0;
4055
4056 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4057 if (adapter->mac_table[i].state == 0)
4058 count++;
4059 }
4060 return count;
4061}
4062
4063/* this function destroys the first RAR entry */
4064static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter,
4065 u8 *addr)
4066{
4067 struct ixgbe_hw *hw = &adapter->hw;
4068
4069 memcpy(&adapter->mac_table[0].addr, addr, ETH_ALEN);
4070 adapter->mac_table[0].queue = VMDQ_P(0);
4071 adapter->mac_table[0].state = (IXGBE_MAC_STATE_DEFAULT |
4072 IXGBE_MAC_STATE_IN_USE);
4073 hw->mac.ops.set_rar(hw, 0, adapter->mac_table[0].addr,
4074 adapter->mac_table[0].queue,
4075 IXGBE_RAH_AV);
4076}
4077
4078int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4079{
4080 struct ixgbe_hw *hw = &adapter->hw;
4081 int i;
4082
4083 if (is_zero_ether_addr(addr))
4084 return -EINVAL;
4085
4086 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4087 if (adapter->mac_table[i].state & IXGBE_MAC_STATE_IN_USE)
4088 continue;
4089 adapter->mac_table[i].state |= (IXGBE_MAC_STATE_MODIFIED |
4090 IXGBE_MAC_STATE_IN_USE);
4091 ether_addr_copy(adapter->mac_table[i].addr, addr);
4092 adapter->mac_table[i].queue = queue;
4093 ixgbe_sync_mac_table(adapter);
4094 return i;
4095 }
4096 return -ENOMEM;
4097}
4098
4099int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter, u8 *addr, u16 queue)
4100{
4101 /* search table for addr, if found, set to 0 and sync */
4102 int i;
4103 struct ixgbe_hw *hw = &adapter->hw;
4104
4105 if (is_zero_ether_addr(addr))
4106 return -EINVAL;
4107
4108 for (i = 0; i < hw->mac.num_rar_entries; i++) {
4109 if (ether_addr_equal(addr, adapter->mac_table[i].addr) &&
4110 adapter->mac_table[i].queue == queue) {
4111 adapter->mac_table[i].state |= IXGBE_MAC_STATE_MODIFIED;
4112 adapter->mac_table[i].state &= ~IXGBE_MAC_STATE_IN_USE;
c7bf7169 4113 eth_zero_addr(adapter->mac_table[i].addr);
5d7daa35
JK		 4114 adapter->mac_table[i].queue = 0;
4115 ixgbe_sync_mac_table(adapter);
4116 return 0;
4117 }
4118 }
4119 return -ENOMEM;
4120}
2850062a
AD		 4121/**
4122 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
4123 * @netdev: network interface device structure
4124 *
4125 * Writes unicast address list to the RAR table.
4126 * Returns: -ENOMEM on failure/insufficient address space
4127 * 0 on no addresses written
4128 * X on writing X addresses to the RAR table
4129 **/
5d7daa35 4130static int ixgbe_write_uc_addr_list(struct net_device *netdev, int vfn)
2850062a
AD		 4131{
4132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2850062a
AD		 4133 int count = 0;
4134
4135 /* return ENOMEM indicating insufficient memory for addresses */
5d7daa35 4136 if (netdev_uc_count(netdev) > ixgbe_available_rars(adapter))
2850062a
AD		 4137 return -ENOMEM;
4138
95447461 4139 if (!netdev_uc_empty(netdev)) {
2850062a 4140 struct netdev_hw_addr *ha;
2850062a 4141 netdev_for_each_uc_addr(ha, netdev) {
5d7daa35
JK		 4142 ixgbe_del_mac_filter(adapter, ha->addr, vfn);
4143 ixgbe_add_mac_filter(adapter, ha->addr, vfn);
2850062a
AD		 4144 count++;
4145 }
4146 }
2850062a
AD		 4147 return count;
4148}
4149
9a799d71 4150/**
2c5645cf 4151 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 4152 * @netdev: network interface device structure
4153 *
2c5645cf
CL		 4154 * The set_rx_method entry point is called whenever the unicast/multicast
4155 * address list or the network interface flags are updated. This routine is
4156 * responsible for configuring the hardware for proper unicast, multicast and
4157 * promiscuous mode.
9a799d71 4158 **/
7f870475 4159void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 4160{
4161 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4162 struct ixgbe_hw *hw = &adapter->hw;
2850062a 4163 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
a9b8943e 4164 u32 vlnctrl;
2850062a 4165 int count;
9a799d71
AK		 4166
4167 /* Check for Promiscuous and All Multicast modes */
9a799d71 4168 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
a9b8943e 4169 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
9a799d71 4170
f5dc442b 4171 /* set all bits that we expect to always be set */
3f2d1c0f 4172 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 4173 fctrl |= IXGBE_FCTRL_BAM;
4174 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4175 fctrl |= IXGBE_FCTRL_PMCF;
4176
2850062a
AD		 4177 /* clear the bits we are changing the status of */
4178 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
a9b8943e 4179 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4180 if (netdev->flags & IFF_PROMISC) {
e433ea1f 4181 hw->addr_ctrl.user_set_promisc = true;
9a799d71 4182 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
b335e75b 4183 vmolr |= IXGBE_VMOLR_MPE;
670224f1
GR		 4184 /* Only disable hardware filter vlans in promiscuous mode
4185 * if SR-IOV and VMDQ are disabled - otherwise ensure
4186 * that hardware VLAN filters remain enabled.
4187 */
4556dc59
VY		 4188 if (adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
4189 IXGBE_FLAG_SRIOV_ENABLED))
a9b8943e 4190 vlnctrl |= (IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
9a799d71 4191 } else {
746b9f02
PM		 4192 if (netdev->flags & IFF_ALLMULTI) {
4193 fctrl |= IXGBE_FCTRL_MPE;
2850062a 4194 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 4195 }
a9b8943e 4196 vlnctrl |= IXGBE_VLNCTRL_VFE;
e433ea1f 4197 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 4198 }
4199
4200 /*
4201 * Write addresses to available RAR registers, if there is not
4202 * sufficient space to store all the addresses then enable
4203 * unicast promiscuous mode
4204 */
5d7daa35 4205 count = ixgbe_write_uc_addr_list(netdev, VMDQ_P(0));
9dcb373c
JF		 4206 if (count < 0) {
4207 fctrl |= IXGBE_FCTRL_UPE;
4208 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 4209 }
4210
cf78959c
ET		 4211 /* Write addresses to the MTA, if the attempt fails
4212 * then we should just turn on promiscuous mode so
4213 * that we can at least receive multicast traffic
4214 */
b335e75b
JK		 4215 count = ixgbe_write_mc_addr_list(netdev);
4216 if (count < 0) {
4217 fctrl |= IXGBE_FCTRL_MPE;
4218 vmolr |= IXGBE_VMOLR_MPE;
4219 } else if (count) {
4220 vmolr |= IXGBE_VMOLR_ROMPE;
4221 }
1d9c0bfd
AD		 4222
4223 if (hw->mac.type != ixgbe_mac_82598EB) {
4224 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 4225 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4226 IXGBE_VMOLR_ROPE);
1d9c0bfd 4227 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 4228 }
4229
3f2d1c0f
BG		 4230 /* This is useful for sniffing bad packets. */
4231 if (adapter->netdev->features & NETIF_F_RXALL) {
4232 /* UPE and MPE will be handled by normal PROMISC logic
4233 * in e1000e_set_rx_mode */
4234 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4235 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4236 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4237
4238 fctrl &= ~(IXGBE_FCTRL_DPF);
4239 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4240 }
4241
a9b8943e 4242 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2850062a 4243 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4244
f646968f 4245 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4246 ixgbe_vlan_strip_enable(adapter);
4247 else
4248 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4249}
4250
021230d4
AV		 4251static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4252{
4253 int q_idx;
021230d4 4254
5a85e737
ET		 4255 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4256 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4257 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4258 }
021230d4
AV		 4259}
4260
4261static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4262{
4263 int q_idx;
021230d4 4264
5a85e737 4265 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4266 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4267 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4268 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4269 usleep_range(1000, 20000);
5a85e737
ET		 4270 }
4271 }
021230d4
AV		 4272}
4273
67359c3c
MR		 4274static void ixgbe_clear_vxlan_port(struct ixgbe_adapter *adapter)
4275{
4276 switch (adapter->hw.mac.type) {
4277 case ixgbe_mac_X550:
4278 case ixgbe_mac_X550EM_x:
4279 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VXLANCTRL, 0);
4280#ifdef CONFIG_IXGBE_VXLAN
4281 adapter->vxlan_port = 0;
4282#endif
4283 break;
4284 default:
4285 break;
4286 }
4287}
4288
7a6b6f51 4289#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4290/**
2f90b865
AD		 4291 * ixgbe_configure_dcb - Configure DCB hardware
4292 * @adapter: ixgbe adapter struct
4293 *
4294 * This is called by the driver on open to configure the DCB hardware.
4295 * This is also called by the gennetlink interface when reconfiguring
4296 * the DCB state.
4297 */
4298static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4299{
4300 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4301 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4302
67ebd791
AD		 4303 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4304 if (hw->mac.type == ixgbe_mac_82598EB)
4305 netif_set_gso_max_size(adapter->netdev, 65536);
4306 return;
4307 }
4308
4309 if (hw->mac.type == ixgbe_mac_82598EB)
4310 netif_set_gso_max_size(adapter->netdev, 32768);
4311
971060b1 4312#ifdef IXGBE_FCOE
b120818e
JF		 4313 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4314 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4315#endif
b120818e
JF		 4316
4317 /* reconfigure the hardware */
4318 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4319 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4320 DCB_TX_CONFIG);
4321 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4322 DCB_RX_CONFIG);
4323 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4324 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4325 ixgbe_dcb_hw_ets(&adapter->hw,
4326 adapter->ixgbe_ieee_ets,
4327 max_frame);
4328 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4329 adapter->ixgbe_ieee_pfc->pfc_en,
4330 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4331 }
8187cd48
JF		 4332
4333 /* Enable RSS Hash per TC */
4334 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4335 u32 msb = 0;
4336 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4337
d411a936
AD		 4338 while (rss_i) {
4339 msb++;
4340 rss_i >>= 1;
4341 }
8187cd48 4342
4ae63730
AD		 4343 /* write msb to all 8 TCs in one write */
4344 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4345 }
2f90b865 4346}
9da712d2
JF		 4347#endif
4348
4349/* Additional bittime to account for IXGBE framing */
4350#define IXGBE_ETH_FRAMING 20
4351
49ce9c2c 4352/**
9da712d2
JF		 4353 * ixgbe_hpbthresh - calculate high water mark for flow control
4354 *
4355 * @adapter: board private structure to calculate for
49ce9c2c 4356 * @pb: packet buffer to calculate
9da712d2
JF		 4357 */
4358static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4359{
4360 struct ixgbe_hw *hw = &adapter->hw;
4361 struct net_device *dev = adapter->netdev;
4362 int link, tc, kb, marker;
4363 u32 dv_id, rx_pba;
4364
4365 /* Calculate max LAN frame size */
4366 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4367
4368#ifdef IXGBE_FCOE
4369 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4370 if ((dev->features & NETIF_F_FCOE_MTU) &&
4371 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4372 (pb == ixgbe_fcoe_get_tc(adapter)))
4373 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4374#endif
e5776620 4375
9da712d2
JF		 4376 /* Calculate delay value for device */
4377 switch (hw->mac.type) {
4378 case ixgbe_mac_X540:
9a75a1ac
DS		 4379 case ixgbe_mac_X550:
4380 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4381 dv_id = IXGBE_DV_X540(link, tc);
4382 break;
4383 default:
4384 dv_id = IXGBE_DV(link, tc);
4385 break;
4386 }
4387
4388 /* Loopback switch introduces additional latency */
4389 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4390 dv_id += IXGBE_B2BT(tc);
4391
4392 /* Delay value is calculated in bit times convert to KB */
4393 kb = IXGBE_BT2KB(dv_id);
4394 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4395
4396 marker = rx_pba - kb;
4397
4398 /* It is possible that the packet buffer is not large enough
4399 * to provide required headroom. In this case throw an error
4400 * to user and a do the best we can.
4401 */
4402 if (marker < 0) {
4403 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4404 "headroom to support flow control."
4405 "Decrease MTU or number of traffic classes\n", pb);
4406 marker = tc + 1;
4407 }
4408
4409 return marker;
4410}
4411
49ce9c2c 4412/**
9da712d2
JF		 4413 * ixgbe_lpbthresh - calculate low water mark for for flow control
4414 *
4415 * @adapter: board private structure to calculate for
49ce9c2c 4416 * @pb: packet buffer to calculate
9da712d2 4417 */
e5776620 4418static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4419{
4420 struct ixgbe_hw *hw = &adapter->hw;
4421 struct net_device *dev = adapter->netdev;
4422 int tc;
4423 u32 dv_id;
4424
4425 /* Calculate max LAN frame size */
4426 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4427
e5776620
JK		 4428#ifdef IXGBE_FCOE
4429 /* FCoE traffic class uses FCOE jumbo frames */
4430 if ((dev->features & NETIF_F_FCOE_MTU) &&
4431 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4432 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4433 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4434#endif
4435
9da712d2
JF		 4436 /* Calculate delay value for device */
4437 switch (hw->mac.type) {
4438 case ixgbe_mac_X540:
9a75a1ac
DS		 4439 case ixgbe_mac_X550:
4440 case ixgbe_mac_X550EM_x:
9da712d2
JF		 4441 dv_id = IXGBE_LOW_DV_X540(tc);
4442 break;
4443 default:
4444 dv_id = IXGBE_LOW_DV(tc);
4445 break;
4446 }
4447
4448 /* Delay value is calculated in bit times convert to KB */
4449 return IXGBE_BT2KB(dv_id);
4450}
4451
4452/*
4453 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4454 */
4455static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4456{
4457 struct ixgbe_hw *hw = &adapter->hw;
4458 int num_tc = netdev_get_num_tc(adapter->netdev);
4459 int i;
4460
4461 if (!num_tc)
4462 num_tc = 1;
4463
9da712d2
JF		 4464 for (i = 0; i < num_tc; i++) {
4465 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4466 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4467
4468 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4469 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4470 hw->fc.low_water[i] = 0;
9da712d2 4471 }
e5776620
JK		 4472
4473 for (; i < MAX_TRAFFIC_CLASS; i++)
4474 hw->fc.high_water[i] = 0;
9da712d2
JF		 4475}
4476
80605c65
JF		 4477static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4478{
80605c65 4479 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4480 int hdrm;
4481 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4482
4483 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4484 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4485 hdrm = 32 << adapter->fdir_pballoc;
4486 else
4487 hdrm = 0;
80605c65 4488
f7e1027f 4489 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4490 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4491}
4492
e4911d57
AD		 4493static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4494{
4495 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4496 struct hlist_node *node2;
e4911d57
AD		 4497 struct ixgbe_fdir_filter *filter;
4498
4499 spin_lock(&adapter->fdir_perfect_lock);
4500
4501 if (!hlist_empty(&adapter->fdir_filter_list))
4502 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4503
b67bfe0d 4504 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4505 &adapter->fdir_filter_list, fdir_node) {
4506 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4507 &filter->filter,
4508 filter->sw_idx,
4509 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4510 IXGBE_FDIR_DROP_QUEUE :
4511 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4512 }
4513
4514 spin_unlock(&adapter->fdir_perfect_lock);
4515}
4516
2a47fa45
JF		 4517static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4518 struct ixgbe_adapter *adapter)
4519{
4520 struct ixgbe_hw *hw = &adapter->hw;
4521 u32 vmolr;
4522
4523 /* No unicast promiscuous support for VMDQ devices. */
4524 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4525 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4526
4527 /* clear the affected bit */
4528 vmolr &= ~IXGBE_VMOLR_MPE;
4529
4530 if (dev->flags & IFF_ALLMULTI) {
4531 vmolr |= IXGBE_VMOLR_MPE;
4532 } else {
4533 vmolr |= IXGBE_VMOLR_ROMPE;
4534 hw->mac.ops.update_mc_addr_list(hw, dev);
4535 }
5d7daa35 4536 ixgbe_write_uc_addr_list(adapter->netdev, pool);
2a47fa45
JF		 4537 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4538}
4539
2a47fa45
JF		 4540static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4541{
4542 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4543 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4544 struct ixgbe_hw *hw = &adapter->hw;
4545 u16 pool = vadapter->pool;
4546 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4547 IXGBE_PSRTYPE_UDPHDR |
4548 IXGBE_PSRTYPE_IPV4HDR |
4549 IXGBE_PSRTYPE_L2HDR |
4550 IXGBE_PSRTYPE_IPV6HDR;
4551
4552 if (hw->mac.type == ixgbe_mac_82598EB)
4553 return;
4554
4555 if (rss_i > 3)
4556 psrtype |= 2 << 29;
4557 else if (rss_i > 1)
4558 psrtype |= 1 << 29;
4559
4560 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4561}
4562
4563/**
4564 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4565 * @rx_ring: ring to free buffers from
4566 **/
4567static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4568{
4569 struct device *dev = rx_ring->dev;
4570 unsigned long size;
4571 u16 i;
4572
4573 /* ring already cleared, nothing to do */
4574 if (!rx_ring->rx_buffer_info)
4575 return;
4576
4577 /* Free all the Rx ring sk_buffs */
4578 for (i = 0; i < rx_ring->count; i++) {
18cb652a 4579 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
2a47fa45 4580
2a47fa45
JF		 4581 if (rx_buffer->skb) {
4582 struct sk_buff *skb = rx_buffer->skb;
18cb652a 4583 if (IXGBE_CB(skb)->page_released)
2a47fa45
JF		 4584 dma_unmap_page(dev,
4585 IXGBE_CB(skb)->dma,
4586 ixgbe_rx_bufsz(rx_ring),
4587 DMA_FROM_DEVICE);
2a47fa45 4588 dev_kfree_skb(skb);
4d2fcfbc 4589 rx_buffer->skb = NULL;
2a47fa45 4590 }
18cb652a
AD		 4591
4592 if (!rx_buffer->page)
4593 continue;
4594
4595 dma_unmap_page(dev, rx_buffer->dma,
4596 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
4597 __free_pages(rx_buffer->page, ixgbe_rx_pg_order(rx_ring));
4598
2a47fa45
JF		 4599 rx_buffer->page = NULL;
4600 }
4601
4602 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4603 memset(rx_ring->rx_buffer_info, 0, size);
4604
4605 /* Zero out the descriptor ring */
4606 memset(rx_ring->desc, 0, rx_ring->size);
4607
4608 rx_ring->next_to_alloc = 0;
4609 rx_ring->next_to_clean = 0;
4610 rx_ring->next_to_use = 0;
4611}
4612
4613static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4614 struct ixgbe_ring *rx_ring)
4615{
4616 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4617 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4618
4619 /* shutdown specific queue receive and wait for dma to settle */
4620 ixgbe_disable_rx_queue(adapter, rx_ring);
4621 usleep_range(10000, 20000);
4622 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4623 ixgbe_clean_rx_ring(rx_ring);
4624 rx_ring->l2_accel_priv = NULL;
4625}
4626
ae72c8d0
JF		 4627static int ixgbe_fwd_ring_down(struct net_device *vdev,
4628 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4629{
4630 struct ixgbe_adapter *adapter = accel->real_adapter;
4631 unsigned int rxbase = accel->rx_base_queue;
4632 unsigned int txbase = accel->tx_base_queue;
4633 int i;
4634
4635 netif_tx_stop_all_queues(vdev);
4636
4637 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4638 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4639 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4640 }
4641
4642 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4643 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4644 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4645 }
4646
4647
4648 return 0;
4649}
4650
4651static int ixgbe_fwd_ring_up(struct net_device *vdev,
4652 struct ixgbe_fwd_adapter *accel)
4653{
4654 struct ixgbe_adapter *adapter = accel->real_adapter;
4655 unsigned int rxbase, txbase, queues;
4656 int i, baseq, err = 0;
4657
4658 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4659 return 0;
4660
4661 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4662 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4663 accel->pool, adapter->num_rx_pools,
4664 baseq, baseq + adapter->num_rx_queues_per_pool,
4665 adapter->fwd_bitmask);
4666
4667 accel->netdev = vdev;
4668 accel->rx_base_queue = rxbase = baseq;
4669 accel->tx_base_queue = txbase = baseq;
4670
4671 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4672 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4673
4674 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4675 adapter->rx_ring[rxbase + i]->netdev = vdev;
4676 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4677 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4678 }
4679
4680 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4681 adapter->tx_ring[txbase + i]->netdev = vdev;
4682 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4683 }
4684
4685 queues = min_t(unsigned int,
4686 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4687 err = netif_set_real_num_tx_queues(vdev, queues);
4688 if (err)
4689 goto fwd_queue_err;
4690
2a47fa45
JF		 4691 err = netif_set_real_num_rx_queues(vdev, queues);
4692 if (err)
4693 goto fwd_queue_err;
4694
4695 if (is_valid_ether_addr(vdev->dev_addr))
4696 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4697
4698 ixgbe_fwd_psrtype(accel);
4699 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4700 return err;
4701fwd_queue_err:
4702 ixgbe_fwd_ring_down(vdev, accel);
4703 return err;
4704}
4705
4706static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4707{
4708 struct net_device *upper;
4709 struct list_head *iter;
4710 int err;
4711
4712 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4713 if (netif_is_macvlan(upper)) {
4714 struct macvlan_dev *dfwd = netdev_priv(upper);
4715 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4716
4717 if (dfwd->fwd_priv) {
4718 err = ixgbe_fwd_ring_up(upper, vadapter);
4719 if (err)
4720 continue;
4721 }
4722 }
4723 }
4724}
4725
9a799d71
AK		 4726static void ixgbe_configure(struct ixgbe_adapter *adapter)
4727{
d2f5e7f3
AS		 4728 struct ixgbe_hw *hw = &adapter->hw;
4729
80605c65 4730 ixgbe_configure_pb(adapter);
7a6b6f51 4731#ifdef CONFIG_IXGBE_DCB
67ebd791 4732 ixgbe_configure_dcb(adapter);
2f90b865 4733#endif
b35d4d42
AD		 4734 /*
4735 * We must restore virtualization before VLANs or else
4736 * the VLVF registers will not be populated
4737 */
4738 ixgbe_configure_virtualization(adapter);
9a799d71 4739
4c1d7b4b 4740 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4741 ixgbe_restore_vlan(adapter);
4742
d2f5e7f3
AS		 4743 switch (hw->mac.type) {
4744 case ixgbe_mac_82599EB:
4745 case ixgbe_mac_X540:
4746 hw->mac.ops.disable_rx_buff(hw);
4747 break;
4748 default:
4749 break;
4750 }
4751
c4cf55e5 4752 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4753 ixgbe_init_fdir_signature_82599(&adapter->hw,
4754 adapter->fdir_pballoc);
e4911d57
AD		 4755 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4756 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4757 adapter->fdir_pballoc);
4758 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4759 }
4c1d7b4b 4760
d2f5e7f3
AS		 4761 switch (hw->mac.type) {
4762 case ixgbe_mac_82599EB:
4763 case ixgbe_mac_X540:
4764 hw->mac.ops.enable_rx_buff(hw);
4765 break;
4766 default:
4767 break;
4768 }
4769
7c8ae65a
AD		 4770#ifdef IXGBE_FCOE
4771 /* configure FCoE L2 filters, redirection table, and Rx control */
4772 ixgbe_configure_fcoe(adapter);
4773
4774#endif /* IXGBE_FCOE */
9a799d71
AK		 4775 ixgbe_configure_tx(adapter);
4776 ixgbe_configure_rx(adapter);
2a47fa45 4777 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4778}
4779
0ecc061d 4780/**
e8e26350
PW		 4781 * ixgbe_sfp_link_config - set up SFP+ link
4782 * @adapter: pointer to private adapter struct
4783 **/
4784static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4785{
7086400d 4786 /*
52f33af8 4787 * We are assuming the worst case scenario here, and that
7086400d
AD		 4788 * is that an SFP was inserted/removed after the reset
4789 * but before SFP detection was enabled. As such the best
4790 * solution is to just start searching as soon as we start
4791 */
4792 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4793 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4794
7086400d 4795 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4796}
4797
4798/**
4799 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4800 * @hw: pointer to private hardware struct
4801 *
4802 * Returns 0 on success, negative on failure
4803 **/
e8e26350 4804static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4805{
3d292265
JH		 4806 u32 speed;
4807 bool autoneg, link_up = false;
a1e869de 4808 int ret = IXGBE_ERR_LINK_SETUP;
0ecc061d
PWJ		 4809
4810 if (hw->mac.ops.check_link)
3d292265 4811 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4812
4813 if (ret)
e90dd264 4814 return ret;
0ecc061d 4815
3d292265
JH		 4816 speed = hw->phy.autoneg_advertised;
4817 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4818 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4819 &autoneg);
0ecc061d 4820 if (ret)
e90dd264 4821 return ret;
0ecc061d 4822
8620a103 4823 if (hw->mac.ops.setup_link)
fd0326f2 4824 ret = hw->mac.ops.setup_link(hw, speed, link_up);
e90dd264 4825
0ecc061d
PWJ		 4826 return ret;
4827}
4828
a34bcfff 4829static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4830{
9a799d71 4831 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4832 u32 gpie = 0;
9a799d71 4833
9b471446 4834 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4835 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4836 IXGBE_GPIE_OCD;
4837 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4838 /*
4839 * use EIAM to auto-mask when MSI-X interrupt is asserted
4840 * this saves a register write for every interrupt
4841 */
4842 switch (hw->mac.type) {
4843 case ixgbe_mac_82598EB:
4844 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4845 break;
9b471446 4846 case ixgbe_mac_82599EB:
b93a2226 4847 case ixgbe_mac_X540:
9a75a1ac
DS		 4848 case ixgbe_mac_X550:
4849 case ixgbe_mac_X550EM_x:
b93a2226 4850 default:
9b471446
JB		 4851 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4852 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4853 break;
4854 }
4855 } else {
021230d4
AV		 4856 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4857 * specifically only auto mask tx and rx interrupts */
4858 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4859 }
9a799d71 4860
a34bcfff
AD		 4861 /* XXX: to interrupt immediately for EICS writes, enable this */
4862 /* gpie |= IXGBE_GPIE_EIMEN; */
4863
4864 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4865 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4866
4867 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4868 case IXGBE_82599_VMDQ_8Q_MASK:
4869 gpie |= IXGBE_GPIE_VTMODE_16;
4870 break;
4871 case IXGBE_82599_VMDQ_4Q_MASK:
4872 gpie |= IXGBE_GPIE_VTMODE_32;
4873 break;
4874 default:
4875 gpie |= IXGBE_GPIE_VTMODE_64;
4876 break;
4877 }
119fc60a
MC		 4878 }
4879
5fdd31f9 4880 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4881 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4882 switch (adapter->hw.mac.type) {
4883 case ixgbe_mac_82599EB:
9a900eca 4884 gpie |= IXGBE_SDP0_GPIEN_8259X;
f3df98ec
DS		 4885 break;
4886 case ixgbe_mac_X540:
4887 gpie |= IXGBE_EIMS_TS;
4888 break;
4889 default:
4890 break;
4891 }
4892 }
5fdd31f9 4893
a34bcfff
AD		 4894 /* Enable fan failure interrupt */
4895 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
9a900eca 4896 gpie |= IXGBE_SDP1_GPIEN(hw);
0befdb3e 4897
2698b208 4898 if (hw->mac.type == ixgbe_mac_82599EB) {
9a900eca
DS		 4899 gpie |= IXGBE_SDP1_GPIEN_8259X;
4900 gpie |= IXGBE_SDP2_GPIEN_8259X;
2698b208 4901 }
a34bcfff
AD		 4902
4903 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4904}
4905
c7ccde0f 4906static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4907{
4908 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4909 int err;
a34bcfff
AD		 4910 u32 ctrl_ext;
4911
4912 ixgbe_get_hw_control(adapter);
4913 ixgbe_setup_gpie(adapter);
e8e26350 4914
9a799d71
AK		 4915 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4916 ixgbe_configure_msix(adapter);
4917 else
4918 ixgbe_configure_msi_and_legacy(adapter);
4919
ec74a471
ET		 4920 /* enable the optics for 82599 SFP+ fiber */
4921 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4922 hw->mac.ops.enable_tx_laser(hw);
4923
961fac88
DS		 4924 if (hw->phy.ops.set_phy_power)
4925 hw->phy.ops.set_phy_power(hw, true);
4926
4e857c58 4927 smp_mb__before_atomic();
9a799d71 4928 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4929 ixgbe_napi_enable_all(adapter);
4930
73c4b7cd
AD		 4931 if (ixgbe_is_sfp(hw)) {
4932 ixgbe_sfp_link_config(adapter);
4933 } else {
4934 err = ixgbe_non_sfp_link_config(hw);
4935 if (err)
4936 e_err(probe, "link_config FAILED %d\n", err);
4937 }
4938
021230d4
AV		 4939 /* clear any pending interrupts, may auto mask */
4940 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4941 ixgbe_irq_enable(adapter, true, true);
9a799d71 4942
bf069c97
DS		 4943 /*
4944 * If this adapter has a fan, check to see if we had a failure
4945 * before we enabled the interrupt.
4946 */
4947 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4948 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4949 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4950 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4951 }
4952
9a799d71
AK		 4953 /* bring the link up in the watchdog, this could race with our first
4954 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4955 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4956 adapter->link_check_timeout = jiffies;
7086400d 4957 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4958
4959 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4960 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4961 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4962 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4963}
4964
d4f80882
AV		 4965void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4966{
4967 WARN_ON(in_interrupt());
7086400d
AD		 4968 /* put off any impending NetWatchDogTimeout */
4969 adapter->netdev->trans_start = jiffies;
4970
d4f80882 4971 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4972 usleep_range(1000, 2000);
d4f80882 4973 ixgbe_down(adapter);
5809a1ae
GR		 4974 /*
4975 * If SR-IOV enabled then wait a bit before bringing the adapter
4976 * back up to give the VFs time to respond to the reset. The
4977 * two second wait is based upon the watchdog timer cycle in
4978 * the VF driver.
4979 */
4980 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4981 msleep(2000);
d4f80882
AV		 4982 ixgbe_up(adapter);
4983 clear_bit(__IXGBE_RESETTING, &adapter->state);
4984}
4985
c7ccde0f 4986void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4987{
4988 /* hardware has been reset, we need to reload some things */
4989 ixgbe_configure(adapter);
4990
c7ccde0f 4991 ixgbe_up_complete(adapter);
9a799d71
AK		 4992}
4993
4994void ixgbe_reset(struct ixgbe_adapter *adapter)
4995{
c44ade9e 4996 struct ixgbe_hw *hw = &adapter->hw;
5d7daa35 4997 struct net_device *netdev = adapter->netdev;
8ca783ab 4998 int err;
5d7daa35 4999 u8 old_addr[ETH_ALEN];
8ca783ab 5000
b0483c8f
MR		 5001 if (ixgbe_removed(hw->hw_addr))
5002 return;
7086400d
AD		 5003 /* lock SFP init bit to prevent race conditions with the watchdog */
5004 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5005 usleep_range(1000, 2000);
5006
5007 /* clear all SFP and link config related flags while holding SFP_INIT */
5008 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
5009 IXGBE_FLAG2_SFP_NEEDS_RESET);
5010 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5011
8ca783ab 5012 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 5013 switch (err) {
5014 case 0:
5015 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 5016 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 5017 break;
5018 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 5019 e_dev_err("master disable timed out\n");
da4dd0f7 5020 break;
794caeb2
PWJ		 5021 case IXGBE_ERR_EEPROM_VERSION:
5022 /* We are running on a pre-production device, log a warning */
849c4542 5023 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 5024 "Please be aware there may be issues associated with "
849c4542
ET		 5025 "your hardware. If you are experiencing problems "
5026 "please contact your Intel or hardware "
5027 "representative who provided you with this "
5028 "hardware.\n");
794caeb2 5029 break;
da4dd0f7 5030 default:
849c4542 5031 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 5032 }
9a799d71 5033
7086400d 5034 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5d7daa35
JK		 5035 /* do not flush user set addresses */
5036 memcpy(old_addr, &adapter->mac_table[0].addr, netdev->addr_len);
5037 ixgbe_flush_sw_mac_table(adapter);
5038 ixgbe_mac_set_default_filter(adapter, old_addr);
7fa7c9dc
AD		 5039
5040 /* update SAN MAC vmdq pool selection */
5041 if (hw->mac.san_mac_rar_index)
5042 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 5043
8fecf67c 5044 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 5045 ixgbe_ptp_reset(adapter);
961fac88
DS		 5046
5047 if (hw->phy.ops.set_phy_power) {
5048 if (!netif_running(adapter->netdev) && !adapter->wol)
5049 hw->phy.ops.set_phy_power(hw, false);
5050 else
5051 hw->phy.ops.set_phy_power(hw, true);
5052 }
9a799d71
AK		 5053}
5054
9a799d71
AK		 5055/**
5056 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 5057 * @tx_ring: ring to be cleaned
5058 **/
b6ec895e 5059static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 5060{
5061 struct ixgbe_tx_buffer *tx_buffer_info;
5062 unsigned long size;
b6ec895e 5063 u16 i;
9a799d71 5064
84418e3b
AD		 5065 /* ring already cleared, nothing to do */
5066 if (!tx_ring->tx_buffer_info)
5067 return;
9a799d71 5068
84418e3b 5069 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 5070 for (i = 0; i < tx_ring->count; i++) {
5071 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 5072 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 5073 }
5074
dad8a3b3
JF		 5075 netdev_tx_reset_queue(txring_txq(tx_ring));
5076
9a799d71
AK		 5077 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5078 memset(tx_ring->tx_buffer_info, 0, size);
5079
5080 /* Zero out the descriptor ring */
5081 memset(tx_ring->desc, 0, tx_ring->size);
5082
5083 tx_ring->next_to_use = 0;
5084 tx_ring->next_to_clean = 0;
9a799d71
AK		 5085}
5086
5087/**
021230d4 5088 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 5089 * @adapter: board private structure
5090 **/
021230d4 5091static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5092{
5093 int i;
5094
021230d4 5095 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 5096 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 5097}
5098
5099/**
021230d4 5100 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 5101 * @adapter: board private structure
5102 **/
021230d4 5103static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 5104{
5105 int i;
5106
021230d4 5107 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 5108 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 5109}
5110
e4911d57
AD		 5111static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
5112{
b67bfe0d 5113 struct hlist_node *node2;
e4911d57
AD		 5114 struct ixgbe_fdir_filter *filter;
5115
5116 spin_lock(&adapter->fdir_perfect_lock);
5117
b67bfe0d 5118 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 5119 &adapter->fdir_filter_list, fdir_node) {
5120 hlist_del(&filter->fdir_node);
5121 kfree(filter);
5122 }
5123 adapter->fdir_filter_count = 0;
5124
5125 spin_unlock(&adapter->fdir_perfect_lock);
5126}
5127
9a799d71
AK		 5128void ixgbe_down(struct ixgbe_adapter *adapter)
5129{
5130 struct net_device *netdev = adapter->netdev;
7f821875 5131 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 5132 struct net_device *upper;
5133 struct list_head *iter;
bf29ee6c 5134 int i;
9a799d71
AK		 5135
5136 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 5137 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
5138 return; /* do nothing if already down */
9a799d71
AK		 5139
5140 /* disable receives */
1f9ac57c 5141 hw->mac.ops.disable_rx(hw);
9a799d71 5142
2d39d576
YZ		 5143 /* disable all enabled rx queues */
5144 for (i = 0; i < adapter->num_rx_queues; i++)
5145 /* this call also flushes the previous write */
5146 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
5147
032b4325 5148 usleep_range(10000, 20000);
9a799d71 5149
7f821875
JB		 5150 netif_tx_stop_all_queues(netdev);
5151
7086400d 5152 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 5153 netif_carrier_off(netdev);
5154 netif_tx_disable(netdev);
5155
2a47fa45
JF		 5156 /* disable any upper devices */
5157 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
5158 if (netif_is_macvlan(upper)) {
5159 struct macvlan_dev *vlan = netdev_priv(upper);
5160
5161 if (vlan->fwd_priv) {
5162 netif_tx_stop_all_queues(upper);
5163 netif_carrier_off(upper);
5164 netif_tx_disable(upper);
5165 }
5166 }
5167 }
5168
c0dfb90e
JF		 5169 ixgbe_irq_disable(adapter);
5170
5171 ixgbe_napi_disable_all(adapter);
5172
d034acf1
AD		 5173 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
5174 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 5175 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5176
5177 del_timer_sync(&adapter->service_timer);
5178
34cecbbf 5179 if (adapter->num_vfs) {
8e34d1aa
AD		 5180 /* Clear EITR Select mapping */
5181 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 5182
5183 /* Mark all the VFs as inactive */
5184 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 5185 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 5186
34cecbbf
AD		 5187 /* ping all the active vfs to let them know we are going down */
5188 ixgbe_ping_all_vfs(adapter);
5189
5190 /* Disable all VFTE/VFRE TX/RX */
5191 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 5192 }
5193
7f821875
JB		 5194 /* disable transmits in the hardware now that interrupts are off */
5195 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 5196 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 5197 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 5198 }
34cecbbf 5199
9a75a1ac 5200 /* Disable the Tx DMA engine on 82599 and later MAC */
bd508178
AD		 5201 switch (hw->mac.type) {
5202 case ixgbe_mac_82599EB:
b93a2226 5203 case ixgbe_mac_X540:
9a75a1ac
DS		 5204 case ixgbe_mac_X550:
5205 case ixgbe_mac_X550EM_x:
88512539 5206 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 5207 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5208 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 5209 break;
5210 default:
5211 break;
5212 }
7f821875 5213
6f4a0e45
PL		 5214 if (!pci_channel_offline(adapter->pdev))
5215 ixgbe_reset(adapter);
c6ecf39a 5216
ec74a471
ET		 5217 /* power down the optics for 82599 SFP+ fiber */
5218 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 5219 hw->mac.ops.disable_tx_laser(hw);
5220
9a799d71
AK		 5221 ixgbe_clean_all_tx_rings(adapter);
5222 ixgbe_clean_all_rx_rings(adapter);
5223
5dd2d332 5224#ifdef CONFIG_IXGBE_DCA
96b0e0f6 5225 /* since we reset the hardware DCA settings were cleared */
e35ec126 5226 ixgbe_setup_dca(adapter);
96b0e0f6 5227#endif
9a799d71
AK		 5228}
5229
9a799d71
AK		 5230/**
5231 * ixgbe_tx_timeout - Respond to a Tx Hang
5232 * @netdev: network interface device structure
5233 **/
5234static void ixgbe_tx_timeout(struct net_device *netdev)
5235{
5236 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5237
5238 /* Do the reset outside of interrupt context */
c83c6cbd 5239 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5240}
5241
9a799d71
AK		 5242/**
5243 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5244 * @adapter: board private structure to initialize
5245 *
5246 * ixgbe_sw_init initializes the Adapter private data structure.
5247 * Fields are initialized based on PCI device information and
5248 * OS network device settings (MTU size).
5249 **/
9f9a12f8 5250static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5251{
5252 struct ixgbe_hw *hw = &adapter->hw;
5253 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5254 unsigned int rss, fdir;
cb6d0f5e 5255 u32 fwsm;
7a6b6f51 5256#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5257 int j;
5258 struct tc_configuration *tc;
5259#endif
021230d4 5260
c44ade9e
JB		 5261 /* PCI config space info */
5262
5263 hw->vendor_id = pdev->vendor;
5264 hw->device_id = pdev->device;
5265 hw->revision_id = pdev->revision;
5266 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5267 hw->subsystem_device_id = pdev->subsystem_device;
5268
8fc3bb6d 5269 /* Set common capability flags and settings */
0f9b232b 5270 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
c087663e 5271 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5272 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5273 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5274 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5275 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5276 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5277 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5278 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5279#ifdef CONFIG_IXGBE_DCA
5280 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5281#endif
5282#ifdef IXGBE_FCOE
5283 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5284 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5285#ifdef CONFIG_IXGBE_DCB
5286 /* Default traffic class to use for FCoE */
5287 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5288#endif /* CONFIG_IXGBE_DCB */
5289#endif /* IXGBE_FCOE */
5290
5d7daa35
JK		 5291 adapter->mac_table = kzalloc(sizeof(struct ixgbe_mac_addr) *
5292 hw->mac.num_rar_entries,
5293 GFP_ATOMIC);
5294
8fc3bb6d 5295 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5296 switch (hw->mac.type) {
5297 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5298 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5299 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5300
bf069c97
DS		 5301 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5302 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5303
49c7ffbe 5304 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5305 adapter->ring_feature[RING_F_FDIR].limit = 0;
5306 adapter->atr_sample_rate = 0;
5307 adapter->fdir_pballoc = 0;
5308#ifdef IXGBE_FCOE
5309 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5310 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5311#ifdef CONFIG_IXGBE_DCB
5312 adapter->fcoe.up = 0;
5313#endif /* IXGBE_DCB */
5314#endif /* IXGBE_FCOE */
5315 break;
5316 case ixgbe_mac_82599EB:
5317 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5318 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5319 break;
b93a2226 5320 case ixgbe_mac_X540:
9a900eca 5321 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
cb6d0f5e
JK		 5322 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5323 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5324 break;
9a75a1ac
DS		 5325 case ixgbe_mac_X550EM_x:
5326 case ixgbe_mac_X550:
5327#ifdef CONFIG_IXGBE_DCA
5328 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
67359c3c
MR		 5329#endif
5330#ifdef CONFIG_IXGBE_VXLAN
5331 adapter->flags |= IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE;
9a75a1ac
DS		 5332#endif
5333 break;
bd508178
AD		 5334 default:
5335 break;
f8212f97 5336 }
2f90b865 5337
7c8ae65a
AD		 5338#ifdef IXGBE_FCOE
5339 /* FCoE support exists, always init the FCoE lock */
5340 spin_lock_init(&adapter->fcoe.lock);
5341
5342#endif
1fc5f038
AD		 5343 /* n-tuple support exists, always init our spinlock */
5344 spin_lock_init(&adapter->fdir_perfect_lock);
5345
7a6b6f51 5346#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5347 switch (hw->mac.type) {
5348 case ixgbe_mac_X540:
9a75a1ac
DS		 5349 case ixgbe_mac_X550:
5350 case ixgbe_mac_X550EM_x:
4de2a022
JF		 5351 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5352 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5353 break;
5354 default:
5355 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5356 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5357 break;
5358 }
5359
2f90b865
AD		 5360 /* Configure DCB traffic classes */
5361 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5362 tc = &adapter->dcb_cfg.tc_config[j];
5363 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5364 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5365 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5366 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5367 tc->dcb_pfc = pfc_disabled;
5368 }
4de2a022
JF		 5369
5370 /* Initialize default user to priority mapping, UPx->TC0 */
5371 tc = &adapter->dcb_cfg.tc_config[0];
5372 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5373 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5374
2f90b865
AD		 5375 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5376 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5377 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5378 adapter->dcb_set_bitmap = 0x00;
3032309b 5379 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5380 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5381 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5382
5383#endif
9a799d71
AK		 5384
5385 /* default flow control settings */
cd7664f6 5386 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5387 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5388 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5389 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5390 hw->fc.send_xon = true;
73d80953 5391 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5392
99d74487 5393#ifdef CONFIG_PCI_IOV
170e8543
JK		 5394 if (max_vfs > 0)
5395 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5396
99d74487 5397 /* assign number of SR-IOV VFs */
170e8543 5398 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5399 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5400 adapter->num_vfs = 0;
5401 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5402 } else {
5403 adapter->num_vfs = max_vfs;
5404 }
5405 }
5406#endif /* CONFIG_PCI_IOV */
99d74487 5407
30efa5a3 5408 /* enable itr by default in dynamic mode */
f7554a2b 5409 adapter->rx_itr_setting = 1;
f7554a2b 5410 adapter->tx_itr_setting = 1;
30efa5a3 5411
30efa5a3
JB		 5412 /* set default ring sizes */
5413 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5414 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5415
bd198058 5416 /* set default work limits */
59224555 5417 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5418
9a799d71 5419 /* initialize eeprom parameters */
c44ade9e 5420 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5421 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5422 return -EIO;
5423 }
5424
2a47fa45
JF		 5425 /* PF holds first pool slot */
5426 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5427 set_bit(__IXGBE_DOWN, &adapter->state);
5428
5429 return 0;
5430}
5431
5432/**
5433 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5434 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5435 *
5436 * Return 0 on success, negative on failure
5437 **/
b6ec895e 5438int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5439{
b6ec895e 5440 struct device *dev = tx_ring->dev;
de88eeeb 5441 int orig_node = dev_to_node(dev);
ca8dfe25 5442 int ring_node = -1;
9a799d71
AK		 5443 int size;
5444
3a581073 5445 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5446
5447 if (tx_ring->q_vector)
ca8dfe25 5448 ring_node = tx_ring->q_vector->numa_node;
de88eeeb 5449
ca8dfe25 5450 tx_ring->tx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5451 if (!tx_ring->tx_buffer_info)
89bf67f1 5452 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5453 if (!tx_ring->tx_buffer_info)
5454 goto err;
9a799d71 5455
827da44c
JS		 5456 u64_stats_init(&tx_ring->syncp);
5457
9a799d71 5458 /* round up to nearest 4K */
12207e49 5459 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5460 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5461
ca8dfe25 5462 set_dev_node(dev, ring_node);
de88eeeb
AD		 5463 tx_ring->desc = dma_alloc_coherent(dev,
5464 tx_ring->size,
5465 &tx_ring->dma,
5466 GFP_KERNEL);
5467 set_dev_node(dev, orig_node);
5468 if (!tx_ring->desc)
5469 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5470 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5471 if (!tx_ring->desc)
5472 goto err;
9a799d71 5473
3a581073
JB		 5474 tx_ring->next_to_use = 0;
5475 tx_ring->next_to_clean = 0;
9a799d71 5476 return 0;
e01c31a5
JB		 5477
5478err:
5479 vfree(tx_ring->tx_buffer_info);
5480 tx_ring->tx_buffer_info = NULL;
b6ec895e 5481 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5482 return -ENOMEM;
9a799d71
AK		 5483}
5484
69888674
AD		 5485/**
5486 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5487 * @adapter: board private structure
5488 *
5489 * If this function returns with an error, then it's possible one or
5490 * more of the rings is populated (while the rest are not). It is the
5491 * callers duty to clean those orphaned rings.
5492 *
5493 * Return 0 on success, negative on failure
5494 **/
5495static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5496{
5497 int i, err = 0;
5498
5499 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5500 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5501 if (!err)
5502 continue;
de3d5b94 5503
396e799c 5504 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5505 goto err_setup_tx;
69888674
AD		 5506 }
5507
de3d5b94
AD		 5508 return 0;
5509err_setup_tx:
5510 /* rewind the index freeing the rings as we go */
5511 while (i--)
5512 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5513 return err;
5514}
5515
9a799d71
AK		 5516/**
5517 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5518 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5519 *
5520 * Returns 0 on success, negative on failure
5521 **/
b6ec895e 5522int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5523{
b6ec895e 5524 struct device *dev = rx_ring->dev;
de88eeeb 5525 int orig_node = dev_to_node(dev);
ca8dfe25 5526 int ring_node = -1;
021230d4 5527 int size;
9a799d71 5528
3a581073 5529 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5530
5531 if (rx_ring->q_vector)
ca8dfe25 5532 ring_node = rx_ring->q_vector->numa_node;
de88eeeb 5533
ca8dfe25 5534 rx_ring->rx_buffer_info = vzalloc_node(size, ring_node);
1a6c14a2 5535 if (!rx_ring->rx_buffer_info)
89bf67f1 5536 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5537 if (!rx_ring->rx_buffer_info)
5538 goto err;
9a799d71 5539
827da44c
JS		 5540 u64_stats_init(&rx_ring->syncp);
5541
9a799d71 5542 /* Round up to nearest 4K */
3a581073
JB		 5543 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5544 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5545
ca8dfe25 5546 set_dev_node(dev, ring_node);
de88eeeb
AD		 5547 rx_ring->desc = dma_alloc_coherent(dev,
5548 rx_ring->size,
5549 &rx_ring->dma,
5550 GFP_KERNEL);
5551 set_dev_node(dev, orig_node);
5552 if (!rx_ring->desc)
5553 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5554 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5555 if (!rx_ring->desc)
5556 goto err;
9a799d71 5557
3a581073
JB		 5558 rx_ring->next_to_clean = 0;
5559 rx_ring->next_to_use = 0;
9a799d71
AK		 5560
5561 return 0;
b6ec895e
AD		 5562err:
5563 vfree(rx_ring->rx_buffer_info);
5564 rx_ring->rx_buffer_info = NULL;
5565 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5566 return -ENOMEM;
9a799d71
AK		 5567}
5568
69888674
AD		 5569/**
5570 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5571 * @adapter: board private structure
5572 *
5573 * If this function returns with an error, then it's possible one or
5574 * more of the rings is populated (while the rest are not). It is the
5575 * callers duty to clean those orphaned rings.
5576 *
5577 * Return 0 on success, negative on failure
5578 **/
69888674
AD		 5579static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5580{
5581 int i, err = 0;
5582
5583 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5584 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5585 if (!err)
5586 continue;
de3d5b94 5587
396e799c 5588 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5589 goto err_setup_rx;
69888674
AD		 5590 }
5591
7c8ae65a
AD		 5592#ifdef IXGBE_FCOE
5593 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5594 if (!err)
5595#endif
5596 return 0;
de3d5b94
AD		 5597err_setup_rx:
5598 /* rewind the index freeing the rings as we go */
5599 while (i--)
5600 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5601 return err;
5602}
5603
9a799d71
AK		 5604/**
5605 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5606 * @tx_ring: Tx descriptor ring for a specific queue
5607 *
5608 * Free all transmit software resources
5609 **/
b6ec895e 5610void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5611{
b6ec895e 5612 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5613
5614 vfree(tx_ring->tx_buffer_info);
5615 tx_ring->tx_buffer_info = NULL;
5616
b6ec895e
AD		 5617 /* if not set, then don't free */
5618 if (!tx_ring->desc)
5619 return;
5620
5621 dma_free_coherent(tx_ring->dev, tx_ring->size,
5622 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5623
5624 tx_ring->desc = NULL;
5625}
5626
5627/**
5628 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5629 * @adapter: board private structure
5630 *
5631 * Free all transmit software resources
5632 **/
5633static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5634{
5635 int i;
5636
5637 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5638 if (adapter->tx_ring[i]->desc)
b6ec895e 5639 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5640}
5641
5642/**
b4617240 5643 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5644 * @rx_ring: ring to clean the resources from
5645 *
5646 * Free all receive software resources
5647 **/
b6ec895e 5648void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5649{
b6ec895e 5650 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5651
5652 vfree(rx_ring->rx_buffer_info);
5653 rx_ring->rx_buffer_info = NULL;
5654
b6ec895e
AD		 5655 /* if not set, then don't free */
5656 if (!rx_ring->desc)
5657 return;
5658
5659 dma_free_coherent(rx_ring->dev, rx_ring->size,
5660 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5661
5662 rx_ring->desc = NULL;
5663}
5664
5665/**
5666 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5667 * @adapter: board private structure
5668 *
5669 * Free all receive software resources
5670 **/
5671static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5672{
5673 int i;
5674
7c8ae65a
AD		 5675#ifdef IXGBE_FCOE
5676 ixgbe_free_fcoe_ddp_resources(adapter);
5677
5678#endif
9a799d71 5679 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5680 if (adapter->rx_ring[i]->desc)
b6ec895e 5681 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5682}
5683
9a799d71
AK		 5684/**
5685 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5686 * @netdev: network interface device structure
5687 * @new_mtu: new value for maximum frame size
5688 *
5689 * Returns 0 on success, negative on failure
5690 **/
5691static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5692{
5693 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5694 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5695
42c783c5 5696 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5697 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5698 return -EINVAL;
5699
5700 /*
872844dd
AD		 5701 * For 82599EB we cannot allow legacy VFs to enable their receive
5702 * paths when MTU greater than 1500 is configured. So display a
5703 * warning that legacy VFs will be disabled.
655309e9
AD		 5704 */
5705 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5706 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5707 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5708 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5709
396e799c 5710 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5711
021230d4 5712 /* must set new MTU before calling down or up */
9a799d71
AK		 5713 netdev->mtu = new_mtu;
5714
d4f80882
AV		 5715 if (netif_running(netdev))
5716 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5717
5718 return 0;
5719}
5720
5721/**
5722 * ixgbe_open - Called when a network interface is made active
5723 * @netdev: network interface device structure
5724 *
5725 * Returns 0 on success, negative value on failure
5726 *
5727 * The open entry point is called when a network interface is made
5728 * active by the system (IFF_UP). At this point all resources needed
5729 * for transmit and receive operations are allocated, the interrupt
5730 * handler is registered with the OS, the watchdog timer is started,
5731 * and the stack is notified that the interface is ready.
5732 **/
5733static int ixgbe_open(struct net_device *netdev)
5734{
5735 struct ixgbe_adapter *adapter = netdev_priv(netdev);
961fac88 5736 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 5737 int err, queues;
4bebfaa5
AK		 5738
5739 /* disallow open during test */
5740 if (test_bit(__IXGBE_TESTING, &adapter->state))
5741 return -EBUSY;
9a799d71 5742
54386467
JB		 5743 netif_carrier_off(netdev);
5744
9a799d71
AK		 5745 /* allocate transmit descriptors */
5746 err = ixgbe_setup_all_tx_resources(adapter);
5747 if (err)
5748 goto err_setup_tx;
5749
9a799d71
AK		 5750 /* allocate receive descriptors */
5751 err = ixgbe_setup_all_rx_resources(adapter);
5752 if (err)
5753 goto err_setup_rx;
5754
5755 ixgbe_configure(adapter);
5756
021230d4 5757 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5758 if (err)
5759 goto err_req_irq;
5760
ac802f5d 5761 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5762 if (adapter->num_rx_pools > 1)
5763 queues = adapter->num_rx_queues_per_pool;
5764 else
5765 queues = adapter->num_tx_queues;
5766
5767 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5768 if (err)
5769 goto err_set_queues;
5770
2a47fa45
JF		 5771 if (adapter->num_rx_pools > 1 &&
5772 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5773 queues = IXGBE_MAX_L2A_QUEUES;
5774 else
5775 queues = adapter->num_rx_queues;
5776 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5777 if (err)
5778 goto err_set_queues;
5779
1a71ab24 5780 ixgbe_ptp_init(adapter);
1a71ab24 5781
c7ccde0f 5782 ixgbe_up_complete(adapter);
9a799d71 5783
67359c3c
MR		 5784 ixgbe_clear_vxlan_port(adapter);
5785#ifdef CONFIG_IXGBE_VXLAN
3f207800 5786 vxlan_get_rx_port(netdev);
3f207800 5787#endif
67359c3c 5788
9a799d71
AK		 5789 return 0;
5790
ac802f5d
AD		 5791err_set_queues:
5792 ixgbe_free_irq(adapter);
9a799d71 5793err_req_irq:
a20a1199 5794 ixgbe_free_all_rx_resources(adapter);
961fac88
DS		 5795 if (hw->phy.ops.set_phy_power && !adapter->wol)
5796 hw->phy.ops.set_phy_power(&adapter->hw, false);
de3d5b94 5797err_setup_rx:
a20a1199 5798 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5799err_setup_tx:
9a799d71
AK		 5800 ixgbe_reset(adapter);
5801
5802 return err;
5803}
5804
a0cccce2
JK		 5805static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
5806{
5807 ixgbe_ptp_suspend(adapter);
5808
6ac74394
DS		 5809 if (adapter->hw.phy.ops.enter_lplu) {
5810 adapter->hw.phy.reset_disable = true;
5811 ixgbe_down(adapter);
5812 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
5813 adapter->hw.phy.reset_disable = false;
5814 } else {
5815 ixgbe_down(adapter);
5816 }
5817
a0cccce2
JK		 5818 ixgbe_free_irq(adapter);
5819
5820 ixgbe_free_all_tx_resources(adapter);
5821 ixgbe_free_all_rx_resources(adapter);
5822}
5823
9a799d71
AK		 5824/**
5825 * ixgbe_close - Disables a network interface
5826 * @netdev: network interface device structure
5827 *
5828 * Returns 0, this is not allowed to fail
5829 *
5830 * The close entry point is called when an interface is de-activated
5831 * by the OS. The hardware is still under the drivers control, but
5832 * needs to be disabled. A global MAC reset is issued to stop the
5833 * hardware, and all transmit and receive resources are freed.
5834 **/
5835static int ixgbe_close(struct net_device *netdev)
5836{
5837 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5838
1a71ab24 5839 ixgbe_ptp_stop(adapter);
1a71ab24 5840
a0cccce2 5841 ixgbe_close_suspend(adapter);
9a799d71 5842
e4911d57
AD		 5843 ixgbe_fdir_filter_exit(adapter);
5844
5eba3699 5845 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5846
5847 return 0;
5848}
5849
b3c8b4ba
AD		 5850#ifdef CONFIG_PM
5851static int ixgbe_resume(struct pci_dev *pdev)
5852{
c60fbb00
AD		 5853 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5854 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5855 u32 err;
5856
0391bbe3 5857 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5858 pci_set_power_state(pdev, PCI_D0);
5859 pci_restore_state(pdev);
656ab817
DS		 5860 /*
5861 * pci_restore_state clears dev->state_saved so call
5862 * pci_save_state to restore it.
5863 */
5864 pci_save_state(pdev);
9ce77666 5865
5866 err = pci_enable_device_mem(pdev);
b3c8b4ba 5867 if (err) {
849c4542 5868 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5869 return err;
5870 }
4e857c58 5871 smp_mb__before_atomic();
41c62843 5872 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5873 pci_set_master(pdev);
5874
dd4d8ca6 5875 pci_wake_from_d3(pdev, false);
b3c8b4ba 5876
b3c8b4ba
AD		 5877 ixgbe_reset(adapter);
5878
495dce12
WJP		 5879 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5880
ac802f5d
AD		 5881 rtnl_lock();
5882 err = ixgbe_init_interrupt_scheme(adapter);
5883 if (!err && netif_running(netdev))
c60fbb00 5884 err = ixgbe_open(netdev);
ac802f5d
AD		 5885
5886 rtnl_unlock();
5887
5888 if (err)
5889 return err;
b3c8b4ba
AD		 5890
5891 netif_device_attach(netdev);
5892
5893 return 0;
5894}
b3c8b4ba 5895#endif /* CONFIG_PM */
9d8d05ae
RW		 5896
5897static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5898{
c60fbb00
AD		 5899 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5900 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5901 struct ixgbe_hw *hw = &adapter->hw;
5902 u32 ctrl, fctrl;
5903 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5904#ifdef CONFIG_PM
5905 int retval = 0;
5906#endif
5907
5908 netif_device_detach(netdev);
5909
499ab5cc 5910 rtnl_lock();
a0cccce2
JK		 5911 if (netif_running(netdev))
5912 ixgbe_close_suspend(adapter);
499ab5cc 5913 rtnl_unlock();
b3c8b4ba 5914
5f5ae6fc
AD		 5915 ixgbe_clear_interrupt_scheme(adapter);
5916
b3c8b4ba
AD		 5917#ifdef CONFIG_PM
5918 retval = pci_save_state(pdev);
5919 if (retval)
5920 return retval;
4df10466 5921
b3c8b4ba 5922#endif
f4f1040a
JK		 5923 if (hw->mac.ops.stop_link_on_d3)
5924 hw->mac.ops.stop_link_on_d3(hw);
5925
e8e26350
PW		 5926 if (wufc) {
5927 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5928
ec74a471
ET		 5929 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5930 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5931 hw->mac.ops.enable_tx_laser(hw);
5932
e8e26350
PW		 5933 /* turn on all-multi mode if wake on multicast is enabled */
5934 if (wufc & IXGBE_WUFC_MC) {
5935 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5936 fctrl |= IXGBE_FCTRL_MPE;
5937 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5938 }
5939
5940 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5941 ctrl |= IXGBE_CTRL_GIO_DIS;
5942 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5943
5944 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5945 } else {
5946 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5947 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5948 }
5949
bd508178
AD		 5950 switch (hw->mac.type) {
5951 case ixgbe_mac_82598EB:
dd4d8ca6 5952 pci_wake_from_d3(pdev, false);
bd508178
AD		 5953 break;
5954 case ixgbe_mac_82599EB:
b93a2226 5955 case ixgbe_mac_X540:
9a75a1ac
DS		 5956 case ixgbe_mac_X550:
5957 case ixgbe_mac_X550EM_x:
bd508178
AD		 5958 pci_wake_from_d3(pdev, !!wufc);
5959 break;
5960 default:
5961 break;
5962 }
b3c8b4ba 5963
9d8d05ae 5964 *enable_wake = !!wufc;
961fac88
DS		 5965 if (hw->phy.ops.set_phy_power && !*enable_wake)
5966 hw->phy.ops.set_phy_power(hw, false);
9d8d05ae 5967
b3c8b4ba
AD		 5968 ixgbe_release_hw_control(adapter);
5969
41c62843
MR		 5970 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5971 pci_disable_device(pdev);
b3c8b4ba 5972
9d8d05ae
RW		 5973 return 0;
5974}
5975
5976#ifdef CONFIG_PM
5977static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5978{
5979 int retval;
5980 bool wake;
5981
5982 retval = __ixgbe_shutdown(pdev, &wake);
5983 if (retval)
5984 return retval;
5985
5986 if (wake) {
5987 pci_prepare_to_sleep(pdev);
5988 } else {
5989 pci_wake_from_d3(pdev, false);
5990 pci_set_power_state(pdev, PCI_D3hot);
5991 }
b3c8b4ba
AD		 5992
5993 return 0;
5994}
9d8d05ae 5995#endif /* CONFIG_PM */
b3c8b4ba
AD		 5996
5997static void ixgbe_shutdown(struct pci_dev *pdev)
5998{
9d8d05ae
RW		 5999 bool wake;
6000
6001 __ixgbe_shutdown(pdev, &wake);
6002
6003 if (system_state == SYSTEM_POWER_OFF) {
6004 pci_wake_from_d3(pdev, wake);
6005 pci_set_power_state(pdev, PCI_D3hot);
6006 }
b3c8b4ba
AD		 6007}
6008
9a799d71
AK		 6009/**
6010 * ixgbe_update_stats - Update the board statistics counters.
6011 * @adapter: board private structure
6012 **/
6013void ixgbe_update_stats(struct ixgbe_adapter *adapter)
6014{
2d86f139 6015 struct net_device *netdev = adapter->netdev;
9a799d71 6016 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 6017 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 6018 u64 total_mpc = 0;
6019 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 6020 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
6021 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 6022 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 6023
d08935c2
DS		 6024 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6025 test_bit(__IXGBE_RESETTING, &adapter->state))
6026 return;
6027
94b982b2 6028 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 6029 u64 rsc_count = 0;
94b982b2 6030 u64 rsc_flush = 0;
94b982b2 6031 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 6032 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
6033 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 6034 }
6035 adapter->rsc_total_count = rsc_count;
6036 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 6037 }
6038
5b7da515
AD		 6039 for (i = 0; i < adapter->num_rx_queues; i++) {
6040 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
6041 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
6042 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
6043 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 6044 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 6045 bytes += rx_ring->stats.bytes;
6046 packets += rx_ring->stats.packets;
6047 }
6048 adapter->non_eop_descs = non_eop_descs;
6049 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
6050 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 6051 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 6052 netdev->stats.rx_bytes = bytes;
6053 netdev->stats.rx_packets = packets;
6054
6055 bytes = 0;
6056 packets = 0;
7ca3bc58 6057 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 6058 for (i = 0; i < adapter->num_tx_queues; i++) {
6059 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6060 restart_queue += tx_ring->tx_stats.restart_queue;
6061 tx_busy += tx_ring->tx_stats.tx_busy;
6062 bytes += tx_ring->stats.bytes;
6063 packets += tx_ring->stats.packets;
6064 }
eb985f09 6065 adapter->restart_queue = restart_queue;
5b7da515
AD		 6066 adapter->tx_busy = tx_busy;
6067 netdev->stats.tx_bytes = bytes;
6068 netdev->stats.tx_packets = packets;
7ca3bc58 6069
7ca647bd 6070 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 6071
6072 /* 8 register reads */
6f11eef7
AV		 6073 for (i = 0; i < 8; i++) {
6074 /* for packet buffers not used, the register should read 0 */
6075 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
6076 missed_rx += mpc;
7ca647bd
JP		 6077 hwstats->mpc[i] += mpc;
6078 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 6079 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
6080 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 6081 switch (hw->mac.type) {
6082 case ixgbe_mac_82598EB:
1a70db4b
ET		 6083 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
6084 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
6085 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 6086 hwstats->pxonrxc[i] +=
6087 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 6088 break;
6089 case ixgbe_mac_82599EB:
b93a2226 6090 case ixgbe_mac_X540:
9a75a1ac
DS		 6091 case ixgbe_mac_X550:
6092 case ixgbe_mac_X550EM_x:
bd508178
AD		 6093 hwstats->pxonrxc[i] +=
6094 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 6095 break;
6096 default:
6097 break;
e8e26350 6098 }
6f11eef7 6099 }
1a70db4b
ET		 6100
6101 /*16 register reads */
6102 for (i = 0; i < 16; i++) {
6103 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
6104 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
6105 if ((hw->mac.type == ixgbe_mac_82599EB) ||
9a75a1ac
DS		 6106 (hw->mac.type == ixgbe_mac_X540) ||
6107 (hw->mac.type == ixgbe_mac_X550) ||
6108 (hw->mac.type == ixgbe_mac_X550EM_x)) {
1a70db4b
ET		 6109 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
6110 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
6111 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
6112 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
6113 }
6114 }
6115
7ca647bd 6116 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 6117 /* work around hardware counting issue */
7ca647bd 6118 hwstats->gprc -= missed_rx;
6f11eef7 6119
c84d324c
JF		 6120 ixgbe_update_xoff_received(adapter);
6121
6f11eef7 6122 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 6123 switch (hw->mac.type) {
6124 case ixgbe_mac_82598EB:
6125 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 6126 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
6127 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
6128 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
6129 break;
b93a2226 6130 case ixgbe_mac_X540:
9a75a1ac
DS		 6131 case ixgbe_mac_X550:
6132 case ixgbe_mac_X550EM_x:
6133 /* OS2BMC stats are X540 and later */
58f6bcf9
ET		 6134 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
6135 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
6136 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
6137 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
6138 case ixgbe_mac_82599EB:
a4d4f629
AD		 6139 for (i = 0; i < 16; i++)
6140 adapter->hw_rx_no_dma_resources +=
6141 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 6142 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 6143 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 6144 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 6145 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 6146 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 6147 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 6148 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 6149 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
6150 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 6151#ifdef IXGBE_FCOE
7ca647bd
JP		 6152 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
6153 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
6154 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
6155 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
6156 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
6157 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 6158 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 6159 if (adapter->fcoe.ddp_pool) {
6160 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
6161 struct ixgbe_fcoe_ddp_pool *ddp_pool;
6162 unsigned int cpu;
6163 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 6164 for_each_possible_cpu(cpu) {
5a1ee270
AD		 6165 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
6166 noddp += ddp_pool->noddp;
6167 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 6168 }
5a1ee270
AD		 6169 hwstats->fcoe_noddp = noddp;
6170 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 6171 }
6d45522c 6172#endif /* IXGBE_FCOE */
bd508178
AD		 6173 break;
6174 default:
6175 break;
e8e26350 6176 }
9a799d71 6177 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 6178 hwstats->bprc += bprc;
6179 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 6180 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 6181 hwstats->mprc -= bprc;
6182 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
6183 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
6184 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
6185 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
6186 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
6187 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
6188 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
6189 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 6190 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 6191 hwstats->lxontxc += lxon;
6f11eef7 6192 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 6193 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 6194 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
6195 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 6196 /*
6197 * 82598 errata - tx of flow control packets is included in tx counters
6198 */
6199 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 6200 hwstats->gptc -= xon_off_tot;
6201 hwstats->mptc -= xon_off_tot;
6202 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
6203 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
6204 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
6205 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
6206 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
6207 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
6208 hwstats->ptc64 -= xon_off_tot;
6209 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
6210 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
6211 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
6212 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
6213 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
6214 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 6215
6216 /* Fill out the OS statistics structure */
7ca647bd 6217 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 6218
6219 /* Rx Errors */
7ca647bd 6220 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 6221 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 6222 netdev->stats.rx_length_errors = hwstats->rlec;
6223 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 6224 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 6225}
6226
6227/**
d034acf1 6228 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 6229 * @adapter: pointer to the device adapter structure
9a799d71 6230 **/
d034acf1 6231static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 6232{
cf8280ee 6233 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 6234 int i;
cf8280ee 6235
d034acf1
AD		 6236 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
6237 return;
6238
6239 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 6240
d034acf1 6241 /* if interface is down do nothing */
fe49f04a 6242 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 6243 return;
6244
6245 /* do nothing if we are not using signature filters */
6246 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
6247 return;
6248
6249 adapter->fdir_overflow++;
6250
93c52dd0
AD		 6251 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
6252 for (i = 0; i < adapter->num_tx_queues; i++)
6253 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
e7cf745b 6254 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6255 /* re-enable flow director interrupts */
6256 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6257 } else {
6258 e_err(probe, "failed to finish FDIR re-initialization, "
6259 "ignored adding FDIR ATR filters\n");
6260 }
93c52dd0
AD		 6261}
6262
6263/**
6264 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 6265 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6266 *
6267 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6268 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6269 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6270 * determine if a hang has occurred.
93c52dd0
AD		 6271 */
6272static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6273{
cf8280ee 6274 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6275 u64 eics = 0;
6276 int i;
cf8280ee 6277
09f40aed 6278 /* If we're down, removing or resetting, just bail */
93c52dd0 6279 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6280 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6281 test_bit(__IXGBE_RESETTING, &adapter->state))
6282 return;
22d5a71b 6283
93c52dd0
AD		 6284 /* Force detection of hung controller */
6285 if (netif_carrier_ok(adapter->netdev)) {
6286 for (i = 0; i < adapter->num_tx_queues; i++)
6287 set_check_for_tx_hang(adapter->tx_ring[i]);
6288 }
22d5a71b 6289
fe49f04a
AD		 6290 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6291 /*
6292 * for legacy and MSI interrupts don't set any bits
6293 * that are enabled for EIAM, because this operation
6294 * would set *both* EIMS and EICS for any bit in EIAM
6295 */
6296 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6297 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6298 } else {
6299 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6300 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6301 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6302 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6303 eics |= ((u64)1 << i);
6304 }
cf8280ee 6305 }
9a799d71 6306
93c52dd0 6307 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a 6308 ixgbe_irq_rearm_queues(adapter, eics);
cf8280ee
JB		 6309}
6310
e8e26350 6311/**
93c52dd0 6312 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6313 * @adapter: pointer to the device adapter structure
6314 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6315 **/
93c52dd0 6316static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6317{
e8e26350 6318 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6319 u32 link_speed = adapter->link_speed;
6320 bool link_up = adapter->link_up;
041441d0 6321 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6322
93c52dd0
AD		 6323 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6324 return;
6325
6326 if (hw->mac.ops.check_link) {
6327 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6328 } else {
93c52dd0
AD		 6329 /* always assume link is up, if no check link function */
6330 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6331 link_up = true;
c4cf55e5 6332 }
041441d0
AD		 6333
6334 if (adapter->ixgbe_ieee_pfc)
6335 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6336
3ebe8fde 6337 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6338 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6339 ixgbe_set_rx_drop_en(adapter);
6340 }
93c52dd0
AD		 6341
6342 if (link_up ||
6343 time_after(jiffies, (adapter->link_check_timeout +
6344 IXGBE_TRY_LINK_TIMEOUT))) {
6345 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6346 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6347 IXGBE_WRITE_FLUSH(hw);
6348 }
6349
6350 adapter->link_up = link_up;
6351 adapter->link_speed = link_speed;
e8e26350
PW		 6352}
6353
107d3018
AD		 6354static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6355{
6356#ifdef CONFIG_IXGBE_DCB
6357 struct net_device *netdev = adapter->netdev;
6358 struct dcb_app app = {
6359 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6360 .protocol = 0,
6361 };
6362 u8 up = 0;
6363
6364 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6365 up = dcb_ieee_getapp_mask(netdev, &app);
6366
6367 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6368#endif
6369}
6370
e8e26350 6371/**
93c52dd0
AD		 6372 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6373 * print link up message
49ce9c2c 6374 * @adapter: pointer to the device adapter structure
e8e26350 6375 **/
93c52dd0 6376static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6377{
93c52dd0 6378 struct net_device *netdev = adapter->netdev;
e8e26350 6379 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6380 struct net_device *upper;
6381 struct list_head *iter;
93c52dd0
AD		 6382 u32 link_speed = adapter->link_speed;
6383 bool flow_rx, flow_tx;
e8e26350 6384
93c52dd0
AD		 6385 /* only continue if link was previously down */
6386 if (netif_carrier_ok(netdev))
a985b6c3 6387 return;
63d6e1d8 6388
93c52dd0 6389 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6390
93c52dd0
AD		 6391 switch (hw->mac.type) {
6392 case ixgbe_mac_82598EB: {
6393 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6394 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6395 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6396 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6397 }
6398 break;
6399 case ixgbe_mac_X540:
9a75a1ac
DS		 6400 case ixgbe_mac_X550:
6401 case ixgbe_mac_X550EM_x:
93c52dd0
AD		 6402 case ixgbe_mac_82599EB: {
6403 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6404 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6405 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6406 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6407 }
6408 break;
6409 default:
6410 flow_tx = false;
6411 flow_rx = false;
6412 break;
e8e26350 6413 }
3a6a4eda 6414
6cb562d6
JK		 6415 adapter->last_rx_ptp_check = jiffies;
6416
8fecf67c 6417 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6418 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6419
93c52dd0
AD		 6420 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6421 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6422 "10 Gbps" :
6423 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6424 "1 Gbps" :
6425 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6426 "100 Mbps" :
6427 "unknown speed"))),
6428 ((flow_rx && flow_tx) ? "RX/TX" :
6429 (flow_rx ? "RX" :
6430 (flow_tx ? "TX" : "None"))));
e8e26350 6431
93c52dd0 6432 netif_carrier_on(netdev);
93c52dd0 6433 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6434
cdc04dcc
ET		 6435 /* enable transmits */
6436 netif_tx_wake_all_queues(adapter->netdev);
6437
6438 /* enable any upper devices */
6439 rtnl_lock();
6440 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6441 if (netif_is_macvlan(upper)) {
6442 struct macvlan_dev *vlan = netdev_priv(upper);
6443
6444 if (vlan->fwd_priv)
6445 netif_tx_wake_all_queues(upper);
6446 }
6447 }
6448 rtnl_unlock();
6449
107d3018
AD		 6450 /* update the default user priority for VFs */
6451 ixgbe_update_default_up(adapter);
6452
befa2af7
AD		 6453 /* ping all the active vfs to let them know link has changed */
6454 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6455}
6456
c4cf55e5 6457/**
93c52dd0
AD		 6458 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6459 * print link down message
49ce9c2c 6460 * @adapter: pointer to the adapter structure
c4cf55e5 6461 **/
581330ba 6462static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6463{
cf8280ee 6464 struct net_device *netdev = adapter->netdev;
c4cf55e5 6465 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6466
93c52dd0
AD		 6467 adapter->link_up = false;
6468 adapter->link_speed = 0;
cf8280ee 6469
93c52dd0
AD		 6470 /* only continue if link was up previously */
6471 if (!netif_carrier_ok(netdev))
6472 return;
264857b8 6473
93c52dd0
AD		 6474 /* poll for SFP+ cable when link is down */
6475 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6476 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6477
8fecf67c 6478 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6479 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6480
93c52dd0
AD		 6481 e_info(drv, "NIC Link is Down\n");
6482 netif_carrier_off(netdev);
befa2af7
AD		 6483
6484 /* ping all the active vfs to let them know link has changed */
6485 ixgbe_ping_all_vfs(adapter);
93c52dd0 6486}
e8e26350 6487
07923c17
ET		 6488static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
6489{
6490 int i;
6491
6492 for (i = 0; i < adapter->num_tx_queues; i++) {
6493 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6494
6495 if (tx_ring->next_to_use != tx_ring->next_to_clean)
6496 return true;
6497 }
6498
6499 return false;
6500}
6501
6502static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
6503{
6504 struct ixgbe_hw *hw = &adapter->hw;
6505 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
6506 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
6507
6508 int i, j;
6509
6510 if (!adapter->num_vfs)
6511 return false;
6512
9a75a1ac
DS		 6513 /* resetting the PF is only needed for MAC before X550 */
6514 if (hw->mac.type >= ixgbe_mac_X550)
6515 return false;
6516
07923c17
ET		 6517 for (i = 0; i < adapter->num_vfs; i++) {
6518 for (j = 0; j < q_per_pool; j++) {
6519 u32 h, t;
6520
6521 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
6522 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
6523
6524 if (h != t)
6525 return true;
6526 }
6527 }
6528
6529 return false;
6530}
6531
93c52dd0
AD		 6532/**
6533 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6534 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6535 **/
6536static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6537{
93c52dd0 6538 if (!netif_carrier_ok(adapter->netdev)) {
07923c17
ET		 6539 if (ixgbe_ring_tx_pending(adapter) ||
6540 ixgbe_vf_tx_pending(adapter)) {
bc59fcda
NS		 6541 /* We've lost link, so the controller stops DMA,
6542 * but we've got queued Tx work that's never going
6543 * to get done, so reset controller to flush Tx.
6544 * (Do the reset outside of interrupt context).
6545 */
12ff3f3b 6546 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6547 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6548 }
c4cf55e5 6549 }
c4cf55e5
PWJ		 6550}
6551
9079e416
ET		 6552#ifdef CONFIG_PCI_IOV
6553static inline void ixgbe_issue_vf_flr(struct ixgbe_adapter *adapter,
6554 struct pci_dev *vfdev)
6555{
6556 if (!pci_wait_for_pending_transaction(vfdev))
6557 e_dev_warn("Issuing VFLR with pending transactions\n");
6558
6559 e_dev_err("Issuing VFLR for VF %s\n", pci_name(vfdev));
6560 pcie_capability_set_word(vfdev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
6561
6562 msleep(100);
6563}
6564
6565static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6566{
6567 struct ixgbe_hw *hw = &adapter->hw;
6568 struct pci_dev *pdev = adapter->pdev;
6569 struct pci_dev *vfdev;
6570 u32 gpc;
6571 int pos;
6572 unsigned short vf_id;
6573
6574 if (!(netif_carrier_ok(adapter->netdev)))
6575 return;
6576
6577 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6578 if (gpc) /* If incrementing then no need for the check below */
6579 return;
6580 /* Check to see if a bad DMA write target from an errant or
6581 * malicious VF has caused a PCIe error. If so then we can
6582 * issue a VFLR to the offending VF(s) and then resume without
6583 * requesting a full slot reset.
6584 */
6585
6586 if (!pdev)
6587 return;
6588
6589 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6590 if (!pos)
6591 return;
6592
6593 /* get the device ID for the VF */
6594 pci_read_config_word(pdev, pos + PCI_SRIOV_VF_DID, &vf_id);
6595
6596 /* check status reg for all VFs owned by this PF */
6597 vfdev = pci_get_device(pdev->vendor, vf_id, NULL);
6598 while (vfdev) {
6599 if (vfdev->is_virtfn && (vfdev->physfn == pdev)) {
6600 u16 status_reg;
6601
6602 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
6603 if (status_reg & PCI_STATUS_REC_MASTER_ABORT)
6604 /* issue VFLR */
6605 ixgbe_issue_vf_flr(adapter, vfdev);
6606 }
6607
6608 vfdev = pci_get_device(pdev->vendor, vf_id, vfdev);
6609 }
6610}
6611
a985b6c3
GR		 6612static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6613{
6614 u32 ssvpc;
6615
0584d999
GR		 6616 /* Do not perform spoof check for 82598 or if not in IOV mode */
6617 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6618 adapter->num_vfs == 0)
a985b6c3
GR		 6619 return;
6620
6621 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6622
6623 /*
6624 * ssvpc register is cleared on read, if zero then no
6625 * spoofed packets in the last interval.
6626 */
6627 if (!ssvpc)
6628 return;
6629
d6ea0754 6630 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3 6631}
9079e416
ET		 6632#else
6633static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
6634{
6635}
6636
6637static void
6638ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
6639{
6640}
6641#endif /* CONFIG_PCI_IOV */
6642
a985b6c3 6643
93c52dd0
AD		 6644/**
6645 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6646 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6647 **/
6648static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6649{
09f40aed 6650 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6651 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6652 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6653 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6654 return;
6655
6656 ixgbe_watchdog_update_link(adapter);
6657
6658 if (adapter->link_up)
6659 ixgbe_watchdog_link_is_up(adapter);
6660 else
6661 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6662
9079e416 6663 ixgbe_check_for_bad_vf(adapter);
a985b6c3 6664 ixgbe_spoof_check(adapter);
9a799d71 6665 ixgbe_update_stats(adapter);
93c52dd0
AD		 6666
6667 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6668}
10eec955 6669
cf8280ee 6670/**
7086400d 6671 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6672 * @adapter: the ixgbe adapter structure
cf8280ee 6673 **/
7086400d 6674static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6675{
cf8280ee 6676 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6677 s32 err;
cf8280ee 6678
7086400d
AD		 6679 /* not searching for SFP so there is nothing to do here */
6680 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6681 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6682 return;
10eec955 6683
7086400d
AD		 6684 /* someone else is in init, wait until next service event */
6685 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6686 return;
cf8280ee 6687
7086400d
AD		 6688 err = hw->phy.ops.identify_sfp(hw);
6689 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6690 goto sfp_out;
264857b8 6691
7086400d
AD		 6692 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6693 /* If no cable is present, then we need to reset
6694 * the next time we find a good cable. */
6695 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6696 }
9a799d71 6697
7086400d
AD		 6698 /* exit on error */
6699 if (err)
6700 goto sfp_out;
e8e26350 6701
7086400d
AD		 6702 /* exit if reset not needed */
6703 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6704 goto sfp_out;
9a799d71 6705
7086400d 6706 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6707
7086400d
AD		 6708 /*
6709 * A module may be identified correctly, but the EEPROM may not have
6710 * support for that module. setup_sfp() will fail in that case, so
6711 * we should not allow that module to load.
6712 */
6713 if (hw->mac.type == ixgbe_mac_82598EB)
6714 err = hw->phy.ops.reset(hw);
6715 else
6716 err = hw->mac.ops.setup_sfp(hw);
6717
6718 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6719 goto sfp_out;
6720
6721 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6722 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6723
6724sfp_out:
6725 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6726
6727 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6728 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6729 e_dev_err("failed to initialize because an unsupported "
6730 "SFP+ module type was detected.\n");
6731 e_dev_err("Reload the driver after installing a "
6732 "supported module.\n");
6733 unregister_netdev(adapter->netdev);
bc59fcda 6734 }
7086400d 6735}
bc59fcda 6736
7086400d
AD		 6737/**
6738 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6739 * @adapter: the ixgbe adapter structure
7086400d
AD		 6740 **/
6741static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6742{
6743 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6744 u32 speed;
6745 bool autoneg = false;
7086400d
AD		 6746
6747 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6748 return;
6749
6750 /* someone else is in init, wait until next service event */
6751 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6752 return;
6753
6754 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6755
3d292265 6756 speed = hw->phy.autoneg_advertised;
ed33ff66 6757 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6758 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6759
6760 /* setup the highest link when no autoneg */
6761 if (!autoneg) {
6762 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6763 speed = IXGBE_LINK_SPEED_10GB_FULL;
6764 }
6765 }
6766
7086400d 6767 if (hw->mac.ops.setup_link)
fd0326f2 6768 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6769
6770 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6771 adapter->link_check_timeout = jiffies;
6772 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6773}
6774
6775/**
6776 * ixgbe_service_timer - Timer Call-back
6777 * @data: pointer to adapter cast into an unsigned long
6778 **/
6779static void ixgbe_service_timer(unsigned long data)
6780{
6781 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6782 unsigned long next_event_offset;
6783
6bb78cfb
AD		 6784 /* poll faster when waiting for link */
6785 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6786 next_event_offset = HZ / 10;
6787 else
6788 next_event_offset = HZ * 2;
83c61fa9 6789
7086400d
AD		 6790 /* Reset the timer */
6791 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6792
9079e416 6793 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6794}
6795
597f22d6
DS		 6796static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
6797{
6798 struct ixgbe_hw *hw = &adapter->hw;
6799 u32 status;
6800
6801 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
6802 return;
6803
6804 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
6805
6806 if (!hw->phy.ops.handle_lasi)
6807 return;
6808
6809 status = hw->phy.ops.handle_lasi(&adapter->hw);
6810 if (status != IXGBE_ERR_OVERTEMP)
6811 return;
6812
6813 e_crit(drv, "%s\n", ixgbe_overheat_msg);
6814}
6815
c83c6cbd
AD		 6816static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6817{
6818 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6819 return;
6820
6821 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6822
09f40aed 6823 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6824 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6825 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6826 test_bit(__IXGBE_RESETTING, &adapter->state))
6827 return;
6828
6829 ixgbe_dump(adapter);
6830 netdev_err(adapter->netdev, "Reset adapter\n");
6831 adapter->tx_timeout_count++;
6832
8f4c5c9f 6833 rtnl_lock();
c83c6cbd 6834 ixgbe_reinit_locked(adapter);
8f4c5c9f 6835 rtnl_unlock();
c83c6cbd
AD		 6836}
6837
7086400d
AD		 6838/**
6839 * ixgbe_service_task - manages and runs subtasks
6840 * @work: pointer to work_struct containing our data
6841 **/
6842static void ixgbe_service_task(struct work_struct *work)
6843{
6844 struct ixgbe_adapter *adapter = container_of(work,
6845 struct ixgbe_adapter,
6846 service_task);
b0483c8f
MR		 6847 if (ixgbe_removed(adapter->hw.hw_addr)) {
6848 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6849 rtnl_lock();
6850 ixgbe_down(adapter);
6851 rtnl_unlock();
6852 }
6853 ixgbe_service_event_complete(adapter);
6854 return;
6855 }
67359c3c
MR		 6856#ifdef CONFIG_IXGBE_VXLAN
6857 if (adapter->flags2 & IXGBE_FLAG2_VXLAN_REREG_NEEDED) {
6858 adapter->flags2 &= ~IXGBE_FLAG2_VXLAN_REREG_NEEDED;
6859 vxlan_get_rx_port(adapter->netdev);
6860 }
6861#endif /* CONFIG_IXGBE_VXLAN */
c83c6cbd 6862 ixgbe_reset_subtask(adapter);
597f22d6 6863 ixgbe_phy_interrupt_subtask(adapter);
7086400d
AD		 6864 ixgbe_sfp_detection_subtask(adapter);
6865 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6866 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6867 ixgbe_watchdog_subtask(adapter);
d034acf1 6868 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6869 ixgbe_check_hang_subtask(adapter);
891dc082 6870
8fecf67c 6871 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6872 ixgbe_ptp_overflow_check(adapter);
6873 ixgbe_ptp_rx_hang(adapter);
6874 }
7086400d
AD		 6875
6876 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6877}
6878
fd0db0ed
AD		 6879static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6880 struct ixgbe_tx_buffer *first,
244e27ad 6881 u8 *hdr_len)
897ab156 6882{
fd0db0ed 6883 struct sk_buff *skb = first->skb;
897ab156
AD		 6884 u32 vlan_macip_lens, type_tucmd;
6885 u32 mss_l4len_idx, l4len;
2049e1f6 6886 int err;
9a799d71 6887
8f4fbb9b
AD		 6888 if (skb->ip_summed != CHECKSUM_PARTIAL)
6889 return 0;
6890
897ab156
AD		 6891 if (!skb_is_gso(skb))
6892 return 0;
9a799d71 6893
2049e1f6
FR		 6894 err = skb_cow_head(skb, 0);
6895 if (err < 0)
6896 return err;
9a799d71 6897
897ab156
AD		 6898 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6899 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6900
a1108ffd 6901 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6902 struct iphdr *iph = ip_hdr(skb);
6903 iph->tot_len = 0;
6904 iph->check = 0;
6905 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6906 iph->daddr, 0,
6907 IPPROTO_TCP,
6908 0);
6909 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6910 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6911 IXGBE_TX_FLAGS_CSUM |
6912 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6913 } else if (skb_is_gso_v6(skb)) {
6914 ipv6_hdr(skb)->payload_len = 0;
6915 tcp_hdr(skb)->check =
6916 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6917 &ipv6_hdr(skb)->daddr,
6918 0, IPPROTO_TCP, 0);
244e27ad
AD		 6919 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6920 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6921 }
6922
091a6246 6923 /* compute header lengths */
897ab156
AD		 6924 l4len = tcp_hdrlen(skb);
6925 *hdr_len = skb_transport_offset(skb) + l4len;
6926
091a6246
AD		 6927 /* update gso size and bytecount with header size */
6928 first->gso_segs = skb_shinfo(skb)->gso_segs;
6929 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6930
c44f5f51 6931 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6932 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6933 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6934
6935 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6936 vlan_macip_lens = skb_network_header_len(skb);
6937 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6938 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6939
6940 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6941 mss_l4len_idx);
897ab156
AD		 6942
6943 return 1;
6944}
6945
244e27ad
AD		 6946static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6947 struct ixgbe_tx_buffer *first)
7ca647bd 6948{
fd0db0ed 6949 struct sk_buff *skb = first->skb;
897ab156
AD		 6950 u32 vlan_macip_lens = 0;
6951 u32 mss_l4len_idx = 0;
6952 u32 type_tucmd = 0;
7ca647bd 6953
897ab156 6954 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6955 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6956 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6957 return;
f467bc06
MR		 6958 vlan_macip_lens = skb_network_offset(skb) <<
6959 IXGBE_ADVTXD_MACLEN_SHIFT;
897ab156
AD		 6960 } else {
6961 u8 l4_hdr = 0;
f467bc06
MR		 6962 union {
6963 struct iphdr *ipv4;
6964 struct ipv6hdr *ipv6;
6965 u8 *raw;
6966 } network_hdr;
6967 union {
6968 struct tcphdr *tcphdr;
6969 u8 *raw;
6970 } transport_hdr;
6971
6972 if (skb->encapsulation) {
6973 network_hdr.raw = skb_inner_network_header(skb);
6974 transport_hdr.raw = skb_inner_transport_header(skb);
6975 vlan_macip_lens = skb_inner_network_offset(skb) <<
6976 IXGBE_ADVTXD_MACLEN_SHIFT;
6977 } else {
6978 network_hdr.raw = skb_network_header(skb);
6979 transport_hdr.raw = skb_transport_header(skb);
6980 vlan_macip_lens = skb_network_offset(skb) <<
6981 IXGBE_ADVTXD_MACLEN_SHIFT;
6982 }
6983
6984 /* use first 4 bits to determine IP version */
6985 switch (network_hdr.ipv4->version) {
6986 case IPVERSION:
6987 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
897ab156 6988 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
f467bc06 6989 l4_hdr = network_hdr.ipv4->protocol;
7ca647bd 6990 break;
f467bc06
MR		 6991 case 6:
6992 vlan_macip_lens |= transport_hdr.raw - network_hdr.raw;
6993 l4_hdr = network_hdr.ipv6->nexthdr;
897ab156
AD		 6994 break;
6995 default:
6996 if (unlikely(net_ratelimit())) {
6997 dev_warn(tx_ring->dev,
f467bc06
MR		 6998 "partial checksum but version=%d\n",
6999 network_hdr.ipv4->version);
897ab156 7000 }
7ca647bd 7001 }
897ab156
AD		 7002
7003 switch (l4_hdr) {
7ca647bd 7004 case IPPROTO_TCP:
897ab156 7005 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
f467bc06 7006 mss_l4len_idx = (transport_hdr.tcphdr->doff * 4) <<
897ab156 7007 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 7008 break;
7009 case IPPROTO_SCTP:
897ab156
AD		 7010 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
7011 mss_l4len_idx = sizeof(struct sctphdr) <<
7012 IXGBE_ADVTXD_L4LEN_SHIFT;
7013 break;
7014 case IPPROTO_UDP:
7015 mss_l4len_idx = sizeof(struct udphdr) <<
7016 IXGBE_ADVTXD_L4LEN_SHIFT;
7017 break;
7018 default:
7019 if (unlikely(net_ratelimit())) {
7020 dev_warn(tx_ring->dev,
7021 "partial checksum but l4 proto=%x!\n",
244e27ad 7022 l4_hdr);
897ab156 7023 }
7ca647bd
JP		 7024 break;
7025 }
244e27ad
AD		 7026
7027 /* update TX checksum flag */
7028 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 7029 }
7030
244e27ad 7031 /* vlan_macip_lens: MACLEN, VLAN tag */
244e27ad 7032 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 7033
897ab156
AD		 7034 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
7035 type_tucmd, mss_l4len_idx);
9a799d71
AK		 7036}
7037
472148c3
AD		 7038#define IXGBE_SET_FLAG(_input, _flag, _result) \
7039 ((_flag <= _result) ? \
7040 ((u32)(_input & _flag) * (_result / _flag)) : \
7041 ((u32)(_input & _flag) / (_flag / _result)))
7042
7043static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 7044{
d3d00239 7045 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 7046 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
7047 IXGBE_ADVTXD_DCMD_DEXT |
7048 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 7049
d3d00239 7050 /* set HW vlan bit if vlan is present */
472148c3
AD		 7051 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
7052 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 7053
d3d00239 7054 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 7055 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
7056 IXGBE_ADVTXD_DCMD_TSE);
7057
7058 /* set timestamp bit if present */
7059 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
7060 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 7061
62748b7b 7062 /* insert frame checksum */
472148c3 7063 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 7064
d3d00239
AD		 7065 return cmd_type;
7066}
9a799d71 7067
729739b7
AD		 7068static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
7069 u32 tx_flags, unsigned int paylen)
d3d00239 7070{
472148c3 7071 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 7072
d3d00239 7073 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 7074 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7075 IXGBE_TX_FLAGS_CSUM,
7076 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 7077
93f5b3c1 7078 /* enble IPv4 checksum for TSO */
472148c3
AD		 7079 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7080 IXGBE_TX_FLAGS_IPV4,
7081 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 7082
7f9643fd
AD		 7083 /*
7084 * Check Context must be set if Tx switch is enabled, which it
7085 * always is for case where virtual functions are running
7086 */
472148c3
AD		 7087 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
7088 IXGBE_TX_FLAGS_CC,
7089 IXGBE_ADVTXD_CC);
7f9643fd 7090
472148c3 7091 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 7092}
44df32c5 7093
2367a173
DB		 7094static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7095{
7096 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
7097
7098 /* Herbert's original patch had:
7099 * smp_mb__after_netif_stop_queue();
7100 * but since that doesn't exist yet, just open code it.
7101 */
7102 smp_mb();
7103
7104 /* We need to check again in a case another CPU has just
7105 * made room available.
7106 */
7107 if (likely(ixgbe_desc_unused(tx_ring) < size))
7108 return -EBUSY;
7109
7110 /* A reprieve! - use start_queue because it doesn't call schedule */
7111 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
7112 ++tx_ring->tx_stats.restart_queue;
7113 return 0;
7114}
7115
7116static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
7117{
7118 if (likely(ixgbe_desc_unused(tx_ring) >= size))
7119 return 0;
7120
7121 return __ixgbe_maybe_stop_tx(tx_ring, size);
7122}
7123
d3d00239
AD		 7124#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
7125 IXGBE_TXD_CMD_RS)
7126
7127static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 7128 struct ixgbe_tx_buffer *first,
d3d00239
AD		 7129 const u8 hdr_len)
7130{
fd0db0ed 7131 struct sk_buff *skb = first->skb;
729739b7 7132 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 7133 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 7134 struct skb_frag_struct *frag;
7135 dma_addr_t dma;
7136 unsigned int data_len, size;
244e27ad 7137 u32 tx_flags = first->tx_flags;
472148c3 7138 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 7139 u16 i = tx_ring->next_to_use;
d3d00239 7140
729739b7
AD		 7141 tx_desc = IXGBE_TX_DESC(tx_ring, i);
7142
ec718254
AD		 7143 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
7144
7145 size = skb_headlen(skb);
7146 data_len = skb->data_len;
729739b7 7147
d3d00239
AD		 7148#ifdef IXGBE_FCOE
7149 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 7150 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 7151 size -= sizeof(struct fcoe_crc_eof) - data_len;
7152 data_len = 0;
729739b7
AD		 7153 } else {
7154 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 7155 }
7156 }
44df32c5 7157
d3d00239 7158#endif
729739b7 7159 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 7160
ec718254 7161 tx_buffer = first;
9a799d71 7162
ec718254
AD		 7163 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
7164 if (dma_mapping_error(tx_ring->dev, dma))
7165 goto dma_error;
7166
7167 /* record length, and DMA address */
7168 dma_unmap_len_set(tx_buffer, len, size);
7169 dma_unmap_addr_set(tx_buffer, dma, dma);
7170
7171 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 7172
729739b7 7173 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 7174 tx_desc->read.cmd_type_len =
472148c3 7175 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 7176
d3d00239 7177 i++;
729739b7 7178 tx_desc++;
d3d00239 7179 if (i == tx_ring->count) {
e4f74028 7180 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 7181 i = 0;
7182 }
ec718254 7183 tx_desc->read.olinfo_status = 0;
729739b7
AD		 7184
7185 dma += IXGBE_MAX_DATA_PER_TXD;
7186 size -= IXGBE_MAX_DATA_PER_TXD;
7187
7188 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 7189 }
e5a43549 7190
729739b7
AD		 7191 if (likely(!data_len))
7192 break;
9a799d71 7193
472148c3 7194 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 7195
729739b7
AD		 7196 i++;
7197 tx_desc++;
7198 if (i == tx_ring->count) {
7199 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
7200 i = 0;
7201 }
ec718254 7202 tx_desc->read.olinfo_status = 0;
9a799d71 7203
d3d00239 7204#ifdef IXGBE_FCOE
9e903e08 7205 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 7206#else
9e903e08 7207 size = skb_frag_size(frag);
d3d00239
AD		 7208#endif
7209 data_len -= size;
9a799d71 7210
729739b7
AD		 7211 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
7212 DMA_TO_DEVICE);
9a799d71 7213
729739b7 7214 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 7215 }
9a799d71 7216
729739b7 7217 /* write last descriptor with RS and EOP bits */
472148c3
AD		 7218 cmd_type |= size | IXGBE_TXD_CMD;
7219 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 7220
091a6246 7221 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 7222
d3d00239
AD		 7223 /* set the timestamp */
7224 first->time_stamp = jiffies;
9a799d71
AK		 7225
7226 /*
729739b7
AD		 7227 * Force memory writes to complete before letting h/w know there
7228 * are new descriptors to fetch. (Only applicable for weak-ordered
7229 * memory model archs, such as IA-64).
7230 *
7231 * We also need this memory barrier to make certain all of the
7232 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 7233 */
7234 wmb();
7235
d3d00239
AD		 7236 /* set next_to_watch value indicating a packet is present */
7237 first->next_to_watch = tx_desc;
7238
729739b7
AD		 7239 i++;
7240 if (i == tx_ring->count)
7241 i = 0;
7242
7243 tx_ring->next_to_use = i;
7244
2367a173
DB		 7245 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
7246
7247 if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
ad435ec6
AD		 7248 writel(i, tx_ring->tail);
7249
7250 /* we need this if more than one processor can write to our tail
7251 * at a time, it synchronizes IO on IA64/Altix systems
7252 */
7253 mmiowb();
9c938cdd 7254 }
2367a173 7255
d3d00239
AD		 7256 return;
7257dma_error:
729739b7 7258 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 7259
7260 /* clear dma mappings for failed tx_buffer_info map */
7261 for (;;) {
729739b7
AD		 7262 tx_buffer = &tx_ring->tx_buffer_info[i];
7263 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
7264 if (tx_buffer == first)
d3d00239
AD		 7265 break;
7266 if (i == 0)
7267 i = tx_ring->count;
7268 i--;
7269 }
7270
d3d00239 7271 tx_ring->next_to_use = i;
9a799d71
AK		 7272}
7273
fd0db0ed 7274static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 7275 struct ixgbe_tx_buffer *first)
69830529
AD		 7276{
7277 struct ixgbe_q_vector *q_vector = ring->q_vector;
7278 union ixgbe_atr_hash_dword input = { .dword = 0 };
7279 union ixgbe_atr_hash_dword common = { .dword = 0 };
7280 union {
7281 unsigned char *network;
7282 struct iphdr *ipv4;
7283 struct ipv6hdr *ipv6;
7284 } hdr;
ee9e0f0b 7285 struct tcphdr *th;
67359c3c
MR		 7286 struct sk_buff *skb;
7287#ifdef CONFIG_IXGBE_VXLAN
7288 u8 encap = false;
7289#endif /* CONFIG_IXGBE_VXLAN */
905e4a41 7290 __be16 vlan_id;
c4cf55e5 7291
69830529
AD		 7292 /* if ring doesn't have a interrupt vector, cannot perform ATR */
7293 if (!q_vector)
7294 return;
7295
7296 /* do nothing if sampling is disabled */
7297 if (!ring->atr_sample_rate)
d3ead241 7298 return;
c4cf55e5 7299
69830529 7300 ring->atr_count++;
c4cf55e5 7301
69830529 7302 /* snag network header to get L4 type and address */
67359c3c
MR		 7303 skb = first->skb;
7304 hdr.network = skb_network_header(skb);
7305 if (skb->encapsulation) {
7306#ifdef CONFIG_IXGBE_VXLAN
7307 struct ixgbe_adapter *adapter = q_vector->adapter;
69830529 7308
67359c3c
MR		 7309 if (!adapter->vxlan_port)
7310 return;
7311 if (first->protocol != htons(ETH_P_IP) ||
7312 hdr.ipv4->version != IPVERSION ||
7313 hdr.ipv4->protocol != IPPROTO_UDP) {
7314 return;
7315 }
7316 if (ntohs(udp_hdr(skb)->dest) != adapter->vxlan_port)
7317 return;
7318 encap = true;
7319 hdr.network = skb_inner_network_header(skb);
7320 th = inner_tcp_hdr(skb);
7321#else
69830529 7322 return;
67359c3c
MR		 7323#endif /* CONFIG_IXGBE_VXLAN */
7324 } else {
7325 /* Currently only IPv4/IPv6 with TCP is supported */
7326 if ((first->protocol != htons(ETH_P_IPV6) ||
7327 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
7328 (first->protocol != htons(ETH_P_IP) ||
7329 hdr.ipv4->protocol != IPPROTO_TCP))
7330 return;
7331 th = tcp_hdr(skb);
7332 }
c4cf55e5 7333
66f32a8b
AD		 7334 /* skip this packet since it is invalid or the socket is closing */
7335 if (!th || th->fin)
69830529
AD		 7336 return;
7337
7338 /* sample on all syn packets or once every atr sample count */
7339 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
7340 return;
7341
7342 /* reset sample count */
7343 ring->atr_count = 0;
7344
244e27ad 7345 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 7346
7347 /*
7348 * src and dst are inverted, think how the receiver sees them
7349 *
7350 * The input is broken into two sections, a non-compressed section
7351 * containing vm_pool, vlan_id, and flow_type. The rest of the data
7352 * is XORed together and stored in the compressed dword.
7353 */
7354 input.formatted.vlan_id = vlan_id;
7355
7356 /*
7357 * since src port and flex bytes occupy the same word XOR them together
7358 * and write the value to source port portion of compressed dword
7359 */
244e27ad 7360 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 7361 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 7362 else
244e27ad 7363 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 7364 common.port.dst ^= th->source;
7365
a1108ffd 7366 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 7367 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
7368 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
7369 } else {
7370 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
7371 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
7372 hdr.ipv6->saddr.s6_addr32[1] ^
7373 hdr.ipv6->saddr.s6_addr32[2] ^
7374 hdr.ipv6->saddr.s6_addr32[3] ^
7375 hdr.ipv6->daddr.s6_addr32[0] ^
7376 hdr.ipv6->daddr.s6_addr32[1] ^
7377 hdr.ipv6->daddr.s6_addr32[2] ^
7378 hdr.ipv6->daddr.s6_addr32[3];
7379 }
c4cf55e5 7380
67359c3c
MR		 7381#ifdef CONFIG_IXGBE_VXLAN
7382 if (encap)
7383 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
7384#endif /* CONFIG_IXGBE_VXLAN */
7385
c4cf55e5 7386 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 7387 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
7388 input, common, ring->queue_index);
c4cf55e5
PWJ		 7389}
7390
f663dd9a 7391static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 7392 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 7393{
f663dd9a
JW		 7394 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
7395#ifdef IXGBE_FCOE
97488bd1
AD		 7396 struct ixgbe_adapter *adapter;
7397 struct ixgbe_ring_feature *f;
7398 int txq;
f663dd9a
JW		 7399#endif
7400
7401 if (fwd_adapter)
7402 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7403
7404#ifdef IXGBE_FCOE
5e09a105 7405
97488bd1
AD		 7406 /*
7407 * only execute the code below if protocol is FCoE
7408 * or FIP and we have FCoE enabled on the adapter
7409 */
7410 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7411 case htons(ETH_P_FCOE):
7412 case htons(ETH_P_FIP):
97488bd1 7413 adapter = netdev_priv(dev);
c087663e 7414
97488bd1
AD		 7415 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7416 break;
7417 default:
99932d4f 7418 return fallback(dev, skb);
97488bd1 7419 }
c087663e 7420
97488bd1 7421 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7422
97488bd1
AD		 7423 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7424 smp_processor_id();
56075a98 7425
97488bd1
AD		 7426 while (txq >= f->indices)
7427 txq -= f->indices;
c4cf55e5 7428
97488bd1 7429 return txq + f->offset;
f663dd9a 7430#else
99932d4f 7431 return fallback(dev, skb);
f663dd9a 7432#endif
09a3b1f8
SH		 7433}
7434
fc77dc3c 7435netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7436 struct ixgbe_adapter *adapter,
7437 struct ixgbe_ring *tx_ring)
9a799d71 7438{
d3d00239 7439 struct ixgbe_tx_buffer *first;
5f715823 7440 int tso;
d3d00239 7441 u32 tx_flags = 0;
a535c30e 7442 unsigned short f;
a535c30e 7443 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7444 __be16 protocol = skb->protocol;
63544e9c 7445 u8 hdr_len = 0;
5e09a105 7446
a535c30e
AD		 7447 /*
7448 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7449 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7450 * + 2 desc gap to keep tail from touching head,
7451 * + 1 desc for context descriptor,
7452 * otherwise try next time
7453 */
a535c30e
AD		 7454 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7455 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7456
a535c30e
AD		 7457 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7458 tx_ring->tx_stats.tx_busy++;
7459 return NETDEV_TX_BUSY;
7460 }
7461
fd0db0ed
AD		 7462 /* record the location of the first descriptor for this packet */
7463 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7464 first->skb = skb;
091a6246
AD		 7465 first->bytecount = skb->len;
7466 first->gso_segs = 1;
fd0db0ed 7467
66f32a8b 7468 /* if we have a HW VLAN tag being added default to the HW one */
df8a39de
JP		 7469 if (skb_vlan_tag_present(skb)) {
7470 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7471 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7472 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7473 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7474 struct vlan_hdr *vhdr, _vhdr;
7475 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7476 if (!vhdr)
7477 goto out_drop;
7478
9e0c5648
AD		 7479 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7480 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7481 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7482 }
0213668f 7483 protocol = vlan_get_protocol(skb);
66f32a8b 7484
d5234933
MR		 7485 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
7486 adapter->ptp_clock &&
7487 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7488 &adapter->state)) {
3a6a4eda
JK		 7489 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7490 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7491
7492 /* schedule check for Tx timestamp */
7493 adapter->ptp_tx_skb = skb_get(skb);
7494 adapter->ptp_tx_start = jiffies;
7495 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7496 }
3a6a4eda 7497
ff29a86e
JK		 7498 skb_tx_timestamp(skb);
7499
9e0c5648
AD		 7500#ifdef CONFIG_PCI_IOV
7501 /*
7502 * Use the l2switch_enable flag - would be false if the DMA
7503 * Tx switch had been disabled.
7504 */
7505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7506 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7507
7508#endif
32701dc2 7509 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7510 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7511 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7512 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7513 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7514 tx_flags |= (skb->priority & 0x7) <<
7515 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7516 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7517 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7518
7519 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7520 goto out_drop;
7521 vhdr = (struct vlan_ethhdr *)skb->data;
7522 vhdr->h_vlan_TCI = htons(tx_flags >>
7523 IXGBE_TX_FLAGS_VLAN_SHIFT);
7524 } else {
7525 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7526 }
9a799d71 7527 }
eacd73f7 7528
244e27ad
AD		 7529 /* record initial flags and protocol */
7530 first->tx_flags = tx_flags;
7531 first->protocol = protocol;
7532
eacd73f7 7533#ifdef IXGBE_FCOE
66f32a8b 7534 /* setup tx offload for FCoE */
a1108ffd 7535 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7536 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7537 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7538 if (tso < 0)
7539 goto out_drop;
9a799d71 7540
66f32a8b 7541 goto xmit_fcoe;
eacd73f7 7542 }
9a799d71 7543
66f32a8b 7544#endif /* IXGBE_FCOE */
244e27ad 7545 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7546 if (tso < 0)
897ab156 7547 goto out_drop;
244e27ad
AD		 7548 else if (!tso)
7549 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7550
7551 /* add the ATR filter if ATR is on */
7552 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7553 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7554
7555#ifdef IXGBE_FCOE
7556xmit_fcoe:
7557#endif /* IXGBE_FCOE */
244e27ad 7558 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239 7559
9a799d71 7560 return NETDEV_TX_OK;
897ab156
AD		 7561
7562out_drop:
fd0db0ed
AD		 7563 dev_kfree_skb_any(first->skb);
7564 first->skb = NULL;
7565
897ab156 7566 return NETDEV_TX_OK;
9a799d71
AK		 7567}
7568
2a47fa45
JF		 7569static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7570 struct net_device *netdev,
7571 struct ixgbe_ring *ring)
84418e3b
AD		 7572{
7573 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7574 struct ixgbe_ring *tx_ring;
7575
a50c29dd
AD		 7576 /*
7577 * The minimum packet size for olinfo paylen is 17 so pad the skb
7578 * in order to meet this minimum size requirement.
7579 */
a94d9e22
AD		 7580 if (skb_put_padto(skb, 17))
7581 return NETDEV_TX_OK;
a50c29dd 7582
2a47fa45
JF		 7583 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7584
fc77dc3c 7585 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7586}
7587
2a47fa45
JF		 7588static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7589 struct net_device *netdev)
7590{
7591 return __ixgbe_xmit_frame(skb, netdev, NULL);
7592}
7593
9a799d71
AK		 7594/**
7595 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7596 * @netdev: network interface device structure
7597 * @p: pointer to an address structure
7598 *
7599 * Returns 0 on success, negative on failure
7600 **/
7601static int ixgbe_set_mac(struct net_device *netdev, void *p)
7602{
7603 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7604 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 7605 struct sockaddr *addr = p;
5d7daa35 7606 int ret;
9a799d71
AK		 7607
7608 if (!is_valid_ether_addr(addr->sa_data))
7609 return -EADDRNOTAVAIL;
7610
5d7daa35 7611 ixgbe_del_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
9a799d71 7612 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7613 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7614
5d7daa35
JK		 7615 ret = ixgbe_add_mac_filter(adapter, hw->mac.addr, VMDQ_P(0));
7616 return ret > 0 ? 0 : ret;
9a799d71
AK		 7617}
7618
6b73e10d
BH		 7619static int
7620ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7621{
7622 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7623 struct ixgbe_hw *hw = &adapter->hw;
7624 u16 value;
7625 int rc;
7626
7627 if (prtad != hw->phy.mdio.prtad)
7628 return -EINVAL;
7629 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7630 if (!rc)
7631 rc = value;
7632 return rc;
7633}
7634
7635static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7636 u16 addr, u16 value)
7637{
7638 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7639 struct ixgbe_hw *hw = &adapter->hw;
7640
7641 if (prtad != hw->phy.mdio.prtad)
7642 return -EINVAL;
7643 return hw->phy.ops.write_reg(hw, addr, devad, value);
7644}
7645
7646static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7647{
7648 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7649
3a6a4eda 7650 switch (cmd) {
3a6a4eda 7651 case SIOCSHWTSTAMP:
93501d48
JK		 7652 return ixgbe_ptp_set_ts_config(adapter, req);
7653 case SIOCGHWTSTAMP:
7654 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7655 default:
7656 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7657 }
6b73e10d
BH		 7658}
7659
0365e6e4
PW		 7660/**
7661 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7662 * netdev->dev_addrs
0365e6e4
PW		 7663 * @netdev: network interface device structure
7664 *
7665 * Returns non-zero on failure
7666 **/
7667static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7668{
7669 int err = 0;
7670 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7671 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7672
7fa7c9dc 7673 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7674 rtnl_lock();
7fa7c9dc 7675 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7676 rtnl_unlock();
7fa7c9dc
AD		 7677
7678 /* update SAN MAC vmdq pool selection */
7679 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7680 }
7681 return err;
7682}
7683
7684/**
7685 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7686 * netdev->dev_addrs
0365e6e4
PW		 7687 * @netdev: network interface device structure
7688 *
7689 * Returns non-zero on failure
7690 **/
7691static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7692{
7693 int err = 0;
7694 struct ixgbe_adapter *adapter = netdev_priv(dev);
7695 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7696
7697 if (is_valid_ether_addr(mac->san_addr)) {
7698 rtnl_lock();
7699 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7700 rtnl_unlock();
7701 }
7702 return err;
7703}
7704
9a799d71
AK		 7705#ifdef CONFIG_NET_POLL_CONTROLLER
7706/*
7707 * Polling 'interrupt' - used by things like netconsole to send skbs
7708 * without having to re-enable interrupts. It's not called while
7709 * the interrupt routine is executing.
7710 */
7711static void ixgbe_netpoll(struct net_device *netdev)
7712{
7713 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7714 int i;
9a799d71 7715
1a647bd2
AD		 7716 /* if interface is down do nothing */
7717 if (test_bit(__IXGBE_DOWN, &adapter->state))
7718 return;
7719
856f606e
AD		 7720 /* loop through and schedule all active queues */
7721 for (i = 0; i < adapter->num_q_vectors; i++)
7722 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
9a799d71 7723}
9a799d71 7724
581330ba 7725#endif
de1036b1
ED		 7726static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7727 struct rtnl_link_stats64 *stats)
7728{
7729 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7730 int i;
7731
1a51502b 7732 rcu_read_lock();
de1036b1 7733 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7734 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7735 u64 bytes, packets;
7736 unsigned int start;
7737
1a51502b
ED		 7738 if (ring) {
7739 do {
57a7744e 7740 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7741 packets = ring->stats.packets;
7742 bytes = ring->stats.bytes;
57a7744e 7743 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7744 stats->rx_packets += packets;
7745 stats->rx_bytes += bytes;
7746 }
de1036b1 7747 }
1ac9ad13
ED		 7748
7749 for (i = 0; i < adapter->num_tx_queues; i++) {
7750 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7751 u64 bytes, packets;
7752 unsigned int start;
7753
7754 if (ring) {
7755 do {
57a7744e 7756 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7757 packets = ring->stats.packets;
7758 bytes = ring->stats.bytes;
57a7744e 7759 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7760 stats->tx_packets += packets;
7761 stats->tx_bytes += bytes;
7762 }
7763 }
1a51502b 7764 rcu_read_unlock();
de1036b1
ED		 7765 /* following stats updated by ixgbe_watchdog_task() */
7766 stats->multicast = netdev->stats.multicast;
7767 stats->rx_errors = netdev->stats.rx_errors;
7768 stats->rx_length_errors = netdev->stats.rx_length_errors;
7769 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7770 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7771 return stats;
7772}
7773
8af3c33f 7774#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7775/**
7776 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7777 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7778 * @tc: number of traffic classes currently enabled
7779 *
7780 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7781 * 802.1Q priority maps to a packet buffer that exists.
7782 */
7783static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7784{
7785 struct ixgbe_hw *hw = &adapter->hw;
7786 u32 reg, rsave;
7787 int i;
7788
7789 /* 82598 have a static priority to TC mapping that can not
7790 * be changed so no validation is needed.
7791 */
7792 if (hw->mac.type == ixgbe_mac_82598EB)
7793 return;
7794
7795 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7796 rsave = reg;
7797
7798 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7799 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7800
7801 /* If up2tc is out of bounds default to zero */
7802 if (up2tc > tc)
7803 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7804 }
7805
7806 if (reg != rsave)
7807 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7808
7809 return;
7810}
7811
02debdc9
AD		 7812/**
7813 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7814 * @adapter: Pointer to adapter struct
7815 *
7816 * Populate the netdev user priority to tc map
7817 */
7818static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7819{
7820 struct net_device *dev = adapter->netdev;
7821 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7822 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7823 u8 prio;
7824
7825 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7826 u8 tc = 0;
7827
7828 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7829 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7830 else if (ets)
7831 tc = ets->prio_tc[prio];
7832
7833 netdev_set_prio_tc_map(dev, prio, tc);
7834 }
7835}
7836
cca73c59 7837#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7838/**
7839 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7840 *
7841 * @netdev: net device to configure
7842 * @tc: number of traffic classes to enable
7843 */
7844int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7845{
8b1c0b24
JF		 7846 struct ixgbe_adapter *adapter = netdev_priv(dev);
7847 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7848 bool pools;
8b1c0b24 7849
8b1c0b24 7850 /* Hardware supports up to 8 traffic classes */
4de2a022 7851 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7852 (hw->mac.type == ixgbe_mac_82598EB &&
7853 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7854 return -EINVAL;
7855
2a47fa45
JF		 7856 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7857 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7858 return -EBUSY;
7859
8b1c0b24 7860 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7861 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7862 * hardware is not flexible enough to do this dynamically.
7863 */
7864 if (netif_running(dev))
7865 ixgbe_close(dev);
7866 ixgbe_clear_interrupt_scheme(adapter);
7867
cca73c59 7868#ifdef CONFIG_IXGBE_DCB
e7589eab 7869 if (tc) {
8b1c0b24 7870 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7871 ixgbe_set_prio_tc_map(adapter);
7872
e7589eab 7873 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7874
943561d3
AD		 7875 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7876 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7877 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7878 }
e7589eab 7879 } else {
8b1c0b24 7880 netdev_reset_tc(dev);
02debdc9 7881
943561d3
AD		 7882 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7883 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7884
7885 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7886
7887 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7888 adapter->dcb_cfg.pfc_mode_enable = false;
7889 }
7890
8b1c0b24 7891 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7892
7893#endif /* CONFIG_IXGBE_DCB */
7894 ixgbe_init_interrupt_scheme(adapter);
7895
8b1c0b24 7896 if (netif_running(dev))
cca73c59 7897 return ixgbe_open(dev);
8b1c0b24
JF		 7898
7899 return 0;
7900}
de1036b1 7901
da36b647
GR		 7902#ifdef CONFIG_PCI_IOV
7903void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7904{
7905 struct net_device *netdev = adapter->netdev;
7906
7907 rtnl_lock();
da36b647 7908 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7909 rtnl_unlock();
7910}
7911
7912#endif
082757af
DS		 7913void ixgbe_do_reset(struct net_device *netdev)
7914{
7915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7916
7917 if (netif_running(netdev))
7918 ixgbe_reinit_locked(adapter);
7919 else
7920 ixgbe_reset(adapter);
7921}
7922
c8f44aff 7923static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7924 netdev_features_t features)
082757af
DS		 7925{
7926 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7927
082757af 7928 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7929 if (!(features & NETIF_F_RXCSUM))
7930 features &= ~NETIF_F_LRO;
082757af 7931
567d2de2
AD		 7932 /* Turn off LRO if not RSC capable */
7933 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7934 features &= ~NETIF_F_LRO;
8e2813f5 7935
567d2de2 7936 return features;
082757af
DS		 7937}
7938
c8f44aff 7939static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7940 netdev_features_t features)
082757af
DS		 7941{
7942 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7943 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7944 bool need_reset = false;
7945
082757af 7946 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7947 if (!(features & NETIF_F_LRO)) {
7948 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7949 need_reset = true;
567d2de2
AD		 7950 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7951 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7952 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7953 if (adapter->rx_itr_setting == 1 ||
7954 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7955 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7956 need_reset = true;
7957 } else if ((changed ^ features) & NETIF_F_LRO) {
7958 e_info(probe, "rx-usecs set too low, "
7959 "disabling RSC\n");
082757af
DS		 7960 }
7961 }
7962
7963 /*
7964 * Check if Flow Director n-tuple support was enabled or disabled. If
7965 * the state changed, we need to reset.
7966 */
39cb681b
AD		 7967 switch (features & NETIF_F_NTUPLE) {
7968 case NETIF_F_NTUPLE:
567d2de2 7969 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7970 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7971 need_reset = true;
7972
567d2de2
AD		 7973 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7974 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7975 break;
7976 default:
7977 /* turn off perfect filters, enable ATR and reset */
7978 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7979 need_reset = true;
7980
7981 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7982
7983 /* We cannot enable ATR if SR-IOV is enabled */
7984 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7985 break;
7986
7987 /* We cannot enable ATR if we have 2 or more traffic classes */
7988 if (netdev_get_num_tc(netdev) > 1)
7989 break;
7990
7991 /* We cannot enable ATR if RSS is disabled */
7992 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7993 break;
7994
7995 /* A sample rate of 0 indicates ATR disabled */
7996 if (!adapter->atr_sample_rate)
7997 break;
7998
7999 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
8000 break;
082757af
DS		 8001 }
8002
f646968f 8003 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 8004 ixgbe_vlan_strip_enable(adapter);
8005 else
8006 ixgbe_vlan_strip_disable(adapter);
8007
3f2d1c0f
BG		 8008 if (changed & NETIF_F_RXALL)
8009 need_reset = true;
8010
567d2de2 8011 netdev->features = features;
67359c3c
MR		 8012
8013#ifdef CONFIG_IXGBE_VXLAN
8014 if ((adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE)) {
8015 if (features & NETIF_F_RXCSUM)
8016 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
8017 else
8018 ixgbe_clear_vxlan_port(adapter);
8019 }
8020#endif /* CONFIG_IXGBE_VXLAN */
8021
082757af
DS		 8022 if (need_reset)
8023 ixgbe_do_reset(netdev);
8024
8025 return 0;
082757af
DS		 8026}
8027
67359c3c 8028#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8029/**
8030 * ixgbe_add_vxlan_port - Get notifications about VXLAN ports that come up
8031 * @dev: The port's netdev
8032 * @sa_family: Socket Family that VXLAN is notifiying us about
8033 * @port: New UDP port number that VXLAN started listening to
8034 **/
8035static void ixgbe_add_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8036 __be16 port)
8037{
8038 struct ixgbe_adapter *adapter = netdev_priv(dev);
8039 struct ixgbe_hw *hw = &adapter->hw;
8040 u16 new_port = ntohs(port);
8041
67359c3c
MR		 8042 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8043 return;
8044
3f207800
DS		 8045 if (sa_family == AF_INET6)
8046 return;
8047
67359c3c 8048 if (adapter->vxlan_port == new_port)
3f207800 8049 return;
3f207800
DS		 8050
8051 if (adapter->vxlan_port) {
8052 netdev_info(dev,
67359c3c 8053 "Hit Max num of VXLAN ports, not adding port %d\n",
3f207800
DS		 8054 new_port);
8055 return;
8056 }
8057
8058 adapter->vxlan_port = new_port;
8059 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL, new_port);
8060}
8061
8062/**
8063 * ixgbe_del_vxlan_port - Get notifications about VXLAN ports that go away
8064 * @dev: The port's netdev
8065 * @sa_family: Socket Family that VXLAN is notifying us about
8066 * @port: UDP port number that VXLAN stopped listening to
8067 **/
8068static void ixgbe_del_vxlan_port(struct net_device *dev, sa_family_t sa_family,
8069 __be16 port)
8070{
8071 struct ixgbe_adapter *adapter = netdev_priv(dev);
3f207800
DS		 8072 u16 new_port = ntohs(port);
8073
67359c3c
MR		 8074 if (!(adapter->flags & IXGBE_FLAG_VXLAN_OFFLOAD_CAPABLE))
8075 return;
8076
3f207800
DS		 8077 if (sa_family == AF_INET6)
8078 return;
8079
8080 if (adapter->vxlan_port != new_port) {
8081 netdev_info(dev, "Port %d was not found, not deleting\n",
8082 new_port);
8083 return;
8084 }
8085
67359c3c
MR		 8086 ixgbe_clear_vxlan_port(adapter);
8087 adapter->flags2 |= IXGBE_FLAG2_VXLAN_REREG_NEEDED;
3f207800 8088}
67359c3c 8089#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8090
edc7d573 8091static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 8092 struct net_device *dev,
f6f6424b 8093 const unsigned char *addr, u16 vid,
0f4b0add
JF		 8094 u16 flags)
8095{
bcfd3432 8096 /* guarantee we can provide a unique filter for the unicast address */
46acc460 8097 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
bcfd3432
AD		 8098 if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
8099 return -ENOMEM;
0f4b0add
JF		 8100 }
8101
f6f6424b 8102 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
0f4b0add
JF		 8103}
8104
219efe97
DS		 8105/**
8106 * ixgbe_configure_bridge_mode - set various bridge modes
8107 * @adapter - the private structure
8108 * @mode - requested bridge mode
8109 *
8110 * Configure some settings require for various bridge modes.
8111 **/
8112static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
8113 __u16 mode)
8114{
6d4c96ad
DS		 8115 struct ixgbe_hw *hw = &adapter->hw;
8116 unsigned int p, num_pools;
8117 u32 vmdctl;
8118
219efe97
DS		 8119 switch (mode) {
8120 case BRIDGE_MODE_VEPA:
6d4c96ad 8121 /* disable Tx loopback, rely on switch hairpin mode */
219efe97 8122 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
6d4c96ad
DS		 8123
8124 /* must enable Rx switching replication to allow multicast
8125 * packet reception on all VFs, and to enable source address
8126 * pruning.
8127 */
8128 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8129 vmdctl |= IXGBE_VT_CTL_REPLEN;
8130 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8131
8132 /* enable Rx source address pruning. Note, this requires
8133 * replication to be enabled or else it does nothing.
8134 */
8135 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8136 for (p = 0; p < num_pools; p++) {
8137 if (hw->mac.ops.set_source_address_pruning)
8138 hw->mac.ops.set_source_address_pruning(hw,
8139 true,
8140 p);
8141 }
219efe97
DS		 8142 break;
8143 case BRIDGE_MODE_VEB:
6d4c96ad 8144 /* enable Tx loopback for internal VF/PF communication */
219efe97
DS		 8145 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
8146 IXGBE_PFDTXGSWC_VT_LBEN);
6d4c96ad
DS		 8147
8148 /* disable Rx switching replication unless we have SR-IOV
8149 * virtual functions
8150 */
8151 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
8152 if (!adapter->num_vfs)
8153 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
8154 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
8155
8156 /* disable Rx source address pruning, since we don't expect to
8157 * be receiving external loopback of our transmitted frames.
8158 */
8159 num_pools = adapter->num_vfs + adapter->num_rx_pools;
8160 for (p = 0; p < num_pools; p++) {
8161 if (hw->mac.ops.set_source_address_pruning)
8162 hw->mac.ops.set_source_address_pruning(hw,
8163 false,
8164 p);
8165 }
219efe97
DS		 8166 break;
8167 default:
8168 return -EINVAL;
8169 }
8170
8171 adapter->bridge_mode = mode;
8172
8173 e_info(drv, "enabling bridge mode: %s\n",
8174 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8175
8176 return 0;
8177}
8178
815cccbf 8179static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
add511b3 8180 struct nlmsghdr *nlh, u16 flags)
815cccbf
JF		 8181{
8182 struct ixgbe_adapter *adapter = netdev_priv(dev);
8183 struct nlattr *attr, *br_spec;
8184 int rem;
8185
8186 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8187 return -EOPNOTSUPP;
8188
8189 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
4ea85e83
TG		 8190 if (!br_spec)
8191 return -EINVAL;
815cccbf
JF		 8192
8193 nla_for_each_nested(attr, br_spec, rem) {
a1e869de 8194 int status;
815cccbf 8195 __u16 mode;
815cccbf
JF		 8196
8197 if (nla_type(attr) != IFLA_BRIDGE_MODE)
8198 continue;
8199
b7c1a314
TG		 8200 if (nla_len(attr) < sizeof(mode))
8201 return -EINVAL;
8202
815cccbf 8203 mode = nla_get_u16(attr);
219efe97
DS		 8204 status = ixgbe_configure_bridge_mode(adapter, mode);
8205 if (status)
8206 return status;
aa2bacb6
DS		 8207
8208 break;
815cccbf
JF		 8209 }
8210
8211 return 0;
8212}
8213
8214static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb 8215 struct net_device *dev,
46c264da 8216 u32 filter_mask, int nlflags)
815cccbf
JF		 8217{
8218 struct ixgbe_adapter *adapter = netdev_priv(dev);
815cccbf
JF		 8219
8220 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
8221 return 0;
8222
aa2bacb6 8223 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
7d4f8d87
SF		 8224 adapter->bridge_mode, 0, 0, nlflags,
8225 filter_mask, NULL);
815cccbf
JF		 8226}
8227
2a47fa45
JF		 8228static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
8229{
8230 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
8231 struct ixgbe_adapter *adapter = netdev_priv(pdev);
aac2f1bf 8232 int used_pools = adapter->num_vfs + adapter->num_rx_pools;
51f3773b 8233 unsigned int limit;
2a47fa45
JF		 8234 int pool, err;
8235
aac2f1bf
JK		 8236 /* Hardware has a limited number of available pools. Each VF, and the
8237 * PF require a pool. Check to ensure we don't attempt to use more
8238 * then the available number of pools.
8239 */
8240 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
8241 return ERR_PTR(-EINVAL);
8242
219354d4
JF		 8243#ifdef CONFIG_RPS
8244 if (vdev->num_rx_queues != vdev->num_tx_queues) {
8245 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
8246 vdev->name);
8247 return ERR_PTR(-EINVAL);
8248 }
8249#endif
2a47fa45 8250 /* Check for hardware restriction on number of rx/tx queues */
219354d4 8251 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 8252 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
8253 netdev_info(pdev,
8254 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
8255 pdev->name);
8256 return ERR_PTR(-EINVAL);
8257 }
8258
8259 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8260 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
8261 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
8262 return ERR_PTR(-EBUSY);
8263
bc52f951 8264 fwd_adapter = kzalloc(sizeof(*fwd_adapter), GFP_KERNEL);
2a47fa45
JF		 8265 if (!fwd_adapter)
8266 return ERR_PTR(-ENOMEM);
8267
8268 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
8269 adapter->num_rx_pools++;
8270 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 8271 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 8272
8273 /* Enable VMDq flag so device will be set in VM mode */
8274 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 8275 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 8276 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 8277
8278 /* Force reinit of ring allocation with VMDQ enabled */
8279 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8280 if (err)
8281 goto fwd_add_err;
8282 fwd_adapter->pool = pool;
8283 fwd_adapter->real_adapter = adapter;
8284 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
8285 if (err)
8286 goto fwd_add_err;
8287 netif_tx_start_all_queues(vdev);
8288 return fwd_adapter;
8289fwd_add_err:
8290 /* unwind counter and free adapter struct */
8291 netdev_info(pdev,
8292 "%s: dfwd hardware acceleration failed\n", vdev->name);
8293 clear_bit(pool, &adapter->fwd_bitmask);
8294 adapter->num_rx_pools--;
8295 kfree(fwd_adapter);
8296 return ERR_PTR(err);
8297}
8298
8299static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
8300{
8301 struct ixgbe_fwd_adapter *fwd_adapter = priv;
8302 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 8303 unsigned int limit;
2a47fa45
JF		 8304
8305 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
8306 adapter->num_rx_pools--;
8307
51f3773b
JF		 8308 limit = find_last_bit(&adapter->fwd_bitmask, 32);
8309 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 8310 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
8311 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
8312 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
8313 fwd_adapter->pool, adapter->num_rx_pools,
8314 fwd_adapter->rx_base_queue,
8315 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
8316 adapter->fwd_bitmask);
8317 kfree(fwd_adapter);
8318}
8319
f467bc06
MR		 8320#define IXGBE_MAX_TUNNEL_HDR_LEN 80
8321static netdev_features_t
8322ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
8323 netdev_features_t features)
8324{
8325 if (!skb->encapsulation)
8326 return features;
8327
8328 if (unlikely(skb_inner_mac_header(skb) - skb_transport_header(skb) >
8329 IXGBE_MAX_TUNNEL_HDR_LEN))
8330 return features & ~NETIF_F_ALL_CSUM;
8331
8332 return features;
8333}
8334
0edc3527 8335static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 8336 .ndo_open = ixgbe_open,
0edc3527 8337 .ndo_stop = ixgbe_close,
00829823 8338 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 8339 .ndo_select_queue = ixgbe_select_queue,
581330ba 8340 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 8341 .ndo_validate_addr = eth_validate_addr,
8342 .ndo_set_mac_address = ixgbe_set_mac,
8343 .ndo_change_mtu = ixgbe_change_mtu,
8344 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 8345 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
8346 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 8347 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 8348 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
8349 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
ed616689 8350 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
581330ba 8351 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
e65ce0d3 8352 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
7f01648a 8353 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 8354 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 8355#ifdef CONFIG_IXGBE_DCB
24095aa3 8356 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 8357#endif
0edc3527
SH		 8358#ifdef CONFIG_NET_POLL_CONTROLLER
8359 .ndo_poll_controller = ixgbe_netpoll,
8360#endif
e0d1095a 8361#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 8362 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 8363#endif
332d4a7d
YZ		 8364#ifdef IXGBE_FCOE
8365 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 8366 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 8367 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 8368 .ndo_fcoe_enable = ixgbe_fcoe_enable,
8369 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 8370 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 8371 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 8372#endif /* IXGBE_FCOE */
082757af
DS		 8373 .ndo_set_features = ixgbe_set_features,
8374 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 8375 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 8376 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
8377 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 8378 .ndo_dfwd_add_station = ixgbe_fwd_add,
8379 .ndo_dfwd_del_station = ixgbe_fwd_del,
67359c3c 8380#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8381 .ndo_add_vxlan_port = ixgbe_add_vxlan_port,
8382 .ndo_del_vxlan_port = ixgbe_del_vxlan_port,
67359c3c 8383#endif /* CONFIG_IXGBE_VXLAN */
f467bc06 8384 .ndo_features_check = ixgbe_features_check,
0edc3527
SH		 8385};
8386
e027d1ae
JK		 8387/**
8388 * ixgbe_enumerate_functions - Get the number of ports this device has
8389 * @adapter: adapter structure
8390 *
8391 * This function enumerates the phsyical functions co-located on a single slot,
8392 * in order to determine how many ports a device has. This is most useful in
8393 * determining the required GT/s of PCIe bandwidth necessary for optimal
8394 * performance.
8395 **/
8396static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
8397{
caafb95d 8398 struct pci_dev *entry, *pdev = adapter->pdev;
e027d1ae
JK		 8399 int physfns = 0;
8400
f1f96579
JK		 8401 /* Some cards can not use the generic count PCIe functions method,
8402 * because they are behind a parent switch, so we hardcode these with
8403 * the correct number of functions.
e027d1ae 8404 */
8818970d 8405 if (ixgbe_pcie_from_parent(&adapter->hw))
e027d1ae 8406 physfns = 4;
8818970d
JK		 8407
8408 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
8409 /* don't count virtual functions */
caafb95d
JK		 8410 if (entry->is_virtfn)
8411 continue;
8412
8413 /* When the devices on the bus don't all match our device ID,
8414 * we can't reliably determine the correct number of
8415 * functions. This can occur if a function has been direct
8416 * attached to a virtual machine using VT-d, for example. In
8417 * this case, simply return -1 to indicate this.
8418 */
8419 if ((entry->vendor != pdev->vendor) ||
8420 (entry->device != pdev->device))
8421 return -1;
8422
8423 physfns++;
e027d1ae
JK		 8424 }
8425
8426 return physfns;
8427}
8428
8e2813f5
JK		 8429/**
8430 * ixgbe_wol_supported - Check whether device supports WoL
8431 * @hw: hw specific details
8432 * @device_id: the device ID
8433 * @subdev_id: the subsystem device ID
8434 *
8435 * This function is used by probe and ethtool to determine
8436 * which devices have WoL support
8437 *
8438 **/
8439int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
8440 u16 subdevice_id)
8441{
8442 struct ixgbe_hw *hw = &adapter->hw;
8443 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
8444 int is_wol_supported = 0;
8445
8446 switch (device_id) {
8447 case IXGBE_DEV_ID_82599_SFP:
8448 /* Only these subdevices could supports WOL */
8449 switch (subdevice_id) {
87557440 8450 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 8451 case IXGBE_SUBDEV_ID_82599_560FLR:
8452 /* only support first port */
8453 if (hw->bus.func != 0)
8454 break;
5700ff26 8455 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 8456 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 8457 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 8458 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 8459 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 8460 is_wol_supported = 1;
8461 break;
8462 }
8463 break;
5daebbb0
DS		 8464 case IXGBE_DEV_ID_82599EN_SFP:
8465 /* Only this subdevice supports WOL */
8466 switch (subdevice_id) {
8467 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
8468 is_wol_supported = 1;
8469 break;
8470 }
8471 break;
8e2813f5
JK		 8472 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
8473 /* All except this subdevice support WOL */
8474 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
8475 is_wol_supported = 1;
8476 break;
8477 case IXGBE_DEV_ID_82599_KX4:
8478 is_wol_supported = 1;
8479 break;
8480 case IXGBE_DEV_ID_X540T:
df376f0d 8481 case IXGBE_DEV_ID_X540T1:
df8c26fd
DS		 8482 case IXGBE_DEV_ID_X550T:
8483 case IXGBE_DEV_ID_X550EM_X_KX4:
8484 case IXGBE_DEV_ID_X550EM_X_KR:
8485 case IXGBE_DEV_ID_X550EM_X_10G_T:
8e2813f5
JK		 8486 /* check eeprom to see if enabled wol */
8487 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
8488 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
8489 (hw->bus.func == 0))) {
8490 is_wol_supported = 1;
8491 }
8492 break;
8493 }
8494
8495 return is_wol_supported;
8496}
8497
c762dff2
MP		 8498/**
8499 * ixgbe_get_platform_mac_addr - Look up MAC address in Open Firmware / IDPROM
8500 * @adapter: Pointer to adapter struct
8501 */
8502static void ixgbe_get_platform_mac_addr(struct ixgbe_adapter *adapter)
8503{
8504#ifdef CONFIG_OF
8505 struct device_node *dp = pci_device_to_OF_node(adapter->pdev);
8506 struct ixgbe_hw *hw = &adapter->hw;
8507 const unsigned char *addr;
8508
8509 addr = of_get_mac_address(dp);
8510 if (addr) {
8511 ether_addr_copy(hw->mac.perm_addr, addr);
8512 return;
8513 }
8514#endif /* CONFIG_OF */
8515
8516#ifdef CONFIG_SPARC
8517 ether_addr_copy(hw->mac.perm_addr, idprom->id_ethaddr);
8518#endif /* CONFIG_SPARC */
8519}
8520
9a799d71
AK		 8521/**
8522 * ixgbe_probe - Device Initialization Routine
8523 * @pdev: PCI device information struct
8524 * @ent: entry in ixgbe_pci_tbl
8525 *
8526 * Returns 0 on success, negative on failure
8527 *
8528 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
8529 * The OS initialization, configuring of the adapter private structure,
8530 * and a hardware reset occur.
8531 **/
1dd06ae8 8532static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 8533{
8534 struct net_device *netdev;
8535 struct ixgbe_adapter *adapter = NULL;
8536 struct ixgbe_hw *hw;
8537 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
e027d1ae 8538 int i, err, pci_using_dac, expected_gts;
d3cb9869 8539 unsigned int indices = MAX_TX_QUEUES;
289700db 8540 u8 part_str[IXGBE_PBANUM_LENGTH];
b5b2ffc0 8541 bool disable_dev = false;
eacd73f7
YZ		 8542#ifdef IXGBE_FCOE
8543 u16 device_caps;
8544#endif
289700db 8545 u32 eec;
9a799d71 8546
bded64a7
AG		 8547 /* Catch broken hardware that put the wrong VF device ID in
8548 * the PCIe SR-IOV capability.
8549 */
8550 if (pdev->is_virtfn) {
8551 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
8552 pci_name(pdev), pdev->vendor, pdev->device);
8553 return -EINVAL;
8554 }
8555
9ce77666 8556 err = pci_enable_device_mem(pdev);
9a799d71
AK		 8557 if (err)
8558 return err;
8559
f5f2eda8 8560 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 8561 pci_using_dac = 1;
8562 } else {
f5f2eda8 8563 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 8564 if (err) {
f5f2eda8
RK		 8565 dev_err(&pdev->dev,
8566 "No usable DMA configuration, aborting\n");
8567 goto err_dma;
9a799d71
AK		 8568 }
8569 pci_using_dac = 0;
8570 }
8571
9ce77666 8572 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8573 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8574 if (err) {
b8bc0421
DC		 8575 dev_err(&pdev->dev,
8576 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8577 goto err_pci_reg;
8578 }
8579
19d5afd4 8580 pci_enable_pcie_error_reporting(pdev);
6fabd715 8581
9a799d71 8582 pci_set_master(pdev);
fb3b27bc 8583 pci_save_state(pdev);
9a799d71 8584
d3cb9869 8585 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8586#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8587 /* 8 TC w/ 4 queues per TC */
8588 indices = 4 * MAX_TRAFFIC_CLASS;
8589#else
8590 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8591#endif
d3cb9869 8592 }
e901acd6 8593
c85a2618 8594 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8595 if (!netdev) {
8596 err = -ENOMEM;
8597 goto err_alloc_etherdev;
8598 }
8599
9a799d71
AK		 8600 SET_NETDEV_DEV(netdev, &pdev->dev);
8601
9a799d71
AK		 8602 adapter = netdev_priv(netdev);
8603
8604 adapter->netdev = netdev;
8605 adapter->pdev = pdev;
8606 hw = &adapter->hw;
8607 hw->back = adapter;
b3f4d599 8608 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8609
05857980 8610 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8611 pci_resource_len(pdev, 0));
2a1a091c 8612 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8613 if (!hw->hw_addr) {
8614 err = -EIO;
8615 goto err_ioremap;
8616 }
8617
0edc3527 8618 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8619 ixgbe_set_ethtool_ops(netdev);
9a799d71 8620 netdev->watchdog_timeo = 5 * HZ;
339de30f 8621 strlcpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
9a799d71 8622
9a799d71
AK		 8623 /* Setup hw api */
8624 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8625 hw->mac.type = ii->mac;
9a900eca 8626 hw->mvals = ii->mvals;
9a799d71 8627
c44ade9e
JB		 8628 /* EEPROM */
8629 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
9a900eca 8630 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
58cf663f
MR		 8631 if (ixgbe_removed(hw->hw_addr)) {
8632 err = -EIO;
8633 goto err_ioremap;
8634 }
c44ade9e
JB		 8635 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8636 if (!(eec & (1 << 8)))
8637 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8638
8639 /* PHY */
8640 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8641 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8642 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8643 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8644 hw->phy.mdio.mmds = 0;
8645 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8646 hw->phy.mdio.dev = netdev;
8647 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8648 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8649
8ca783ab 8650 ii->get_invariants(hw);
9a799d71
AK		 8651
8652 /* setup the private structure */
8653 err = ixgbe_sw_init(adapter);
8654 if (err)
8655 goto err_sw_init;
8656
e86bff0e 8657 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8658 switch (adapter->hw.mac.type) {
8659 case ixgbe_mac_82599EB:
8660 case ixgbe_mac_X540:
9a75a1ac
DS		 8661 case ixgbe_mac_X550:
8662 case ixgbe_mac_X550EM_x:
e86bff0e 8663 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8664 break;
8665 default:
8666 break;
8667 }
e86bff0e 8668
bf069c97
DS		 8669 /*
8670 * If there is a fan on this device and it has failed log the
8671 * failure.
8672 */
8673 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8674 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8675 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8676 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8677 }
8678
8ef78adc
PWJ		 8679 if (allow_unsupported_sfp)
8680 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8681
c44ade9e 8682 /* reset_hw fills in the perm_addr as well */
119fc60a 8683 hw->phy.reset_if_overtemp = true;
c44ade9e 8684 err = hw->mac.ops.reset_hw(hw);
119fc60a 8685 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8686 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8687 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8688 err = 0;
8689 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8690 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8691 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8692 goto err_sw_init;
8693 } else if (err) {
849c4542 8694 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8695 goto err_sw_init;
8696 }
8697
99d74487 8698#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8699 /* SR-IOV not supported on the 82598 */
8700 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8701 goto skip_sriov;
8702 /* Mailbox */
8703 ixgbe_init_mbx_params_pf(hw);
8704 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8705 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8706 ixgbe_enable_sriov(adapter);
60a1a680 8707skip_sriov:
1cdd1ec8 8708
99d74487 8709#endif
396e799c 8710 netdev->features = NETIF_F_SG |
e8e9f696 8711 NETIF_F_IP_CSUM |
082757af 8712 NETIF_F_IPV6_CSUM |
f646968f
PM		 8713 NETIF_F_HW_VLAN_CTAG_TX |
8714 NETIF_F_HW_VLAN_CTAG_RX |
082757af
DS		 8715 NETIF_F_TSO |
8716 NETIF_F_TSO6 |
082757af 8717 NETIF_F_RXHASH |
8bf1264d 8718 NETIF_F_RXCSUM;
9a799d71 8719
8bf1264d 8720 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8721
58be7666
DS		 8722 switch (adapter->hw.mac.type) {
8723 case ixgbe_mac_82599EB:
8724 case ixgbe_mac_X540:
9a75a1ac
DS		 8725 case ixgbe_mac_X550:
8726 case ixgbe_mac_X550EM_x:
45a5ead0 8727 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8728 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8729 NETIF_F_NTUPLE;
58be7666
DS		 8730 break;
8731 default:
8732 break;
8733 }
45a5ead0 8734
3f2d1c0f 8735 netdev->hw_features |= NETIF_F_RXALL;
87031c0d 8736 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3f2d1c0f 8737
ad31c402
JK		 8738 netdev->vlan_features |= NETIF_F_TSO;
8739 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8740 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8741 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8742 netdev->vlan_features |= NETIF_F_SG;
8743
f467bc06
MR		 8744 netdev->hw_enc_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
8745 NETIF_F_IPV6_CSUM;
8746
01789349 8747 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8748 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8749
67359c3c 8750#ifdef CONFIG_IXGBE_VXLAN
3f207800
DS		 8751 switch (adapter->hw.mac.type) {
8752 case ixgbe_mac_X550:
8753 case ixgbe_mac_X550EM_x:
67359c3c
MR		 8754 netdev->hw_enc_features |= NETIF_F_RXCSUM |
8755 NETIF_F_IP_CSUM |
8756 NETIF_F_IPV6_CSUM;
3f207800
DS		 8757 break;
8758 default:
8759 break;
8760 }
67359c3c 8761#endif /* CONFIG_IXGBE_VXLAN */
3f207800 8762
7a6b6f51 8763#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8764 netdev->dcbnl_ops = &dcbnl_ops;
8765#endif
8766
eacd73f7 8767#ifdef IXGBE_FCOE
0d551589 8768 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8769 unsigned int fcoe_l;
8770
eacd73f7
YZ		 8771 if (hw->mac.ops.get_device_caps) {
8772 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8773 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8774 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8775 }
7c8ae65a 8776
d3cb9869
AD		 8777
8778 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8779 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8780
a58915c7
AD		 8781 netdev->features |= NETIF_F_FSO |
8782 NETIF_F_FCOE_CRC;
8783
7c8ae65a
AD		 8784 netdev->vlan_features |= NETIF_F_FSO |
8785 NETIF_F_FCOE_CRC |
8786 NETIF_F_FCOE_MTU;
5e09d7f6 8787 }
eacd73f7 8788#endif /* IXGBE_FCOE */
7b872a55 8789 if (pci_using_dac) {
9a799d71 8790 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8791 netdev->vlan_features |= NETIF_F_HIGHDMA;
8792 }
9a799d71 8793
082757af
DS		 8794 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8795 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8796 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8797 netdev->features |= NETIF_F_LRO;
8798
9a799d71 8799 /* make sure the EEPROM is good */
c44ade9e 8800 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8801 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8802 err = -EIO;
35937c05 8803 goto err_sw_init;
9a799d71
AK		 8804 }
8805
c762dff2
MP		 8806 ixgbe_get_platform_mac_addr(adapter);
8807
9a799d71 8808 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8809
aaeb6cdf 8810 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8811 e_dev_err("invalid MAC address\n");
9a799d71 8812 err = -EIO;
35937c05 8813 goto err_sw_init;
9a799d71
AK		 8814 }
8815
5d7daa35
JK		 8816 ixgbe_mac_set_default_filter(adapter, hw->mac.perm_addr);
8817
7086400d 8818 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8819 (unsigned long) adapter);
9a799d71 8820
58cf663f
MR		 8821 if (ixgbe_removed(hw->hw_addr)) {
8822 err = -EIO;
8823 goto err_sw_init;
8824 }
7086400d 8825 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8826 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8827 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8828
021230d4
AV		 8829 err = ixgbe_init_interrupt_scheme(adapter);
8830 if (err)
8831 goto err_sw_init;
9a799d71 8832
8e2813f5 8833 /* WOL not supported for all devices */
c23f5b6b 8834 adapter->wol = 0;
8e2813f5 8835 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8836 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8837 pdev->subsystem_device);
6b92b0ba 8838 if (hw->wol_enabled)
9417c464 8839 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8840
e8e26350
PW		 8841 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8842
15e5209f
ET		 8843 /* save off EEPROM version number */
8844 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8845 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8846
04f165ef 8847 /* pick up the PCI bus settings for reporting later */
e027d1ae 8848 if (ixgbe_pcie_from_parent(hw))
b8e82001 8849 ixgbe_get_parent_bus_info(adapter);
f9328bc6
DS		 8850 else
8851 hw->mac.ops.get_bus_info(hw);
04f165ef 8852
e027d1ae
JK		 8853 /* calculate the expected PCIe bandwidth required for optimal
8854 * performance. Note that some older parts will never have enough
8855 * bandwidth due to being older generation PCIe parts. We clamp these
8856 * parts to ensure no warning is displayed if it can't be fixed.
8857 */
8858 switch (hw->mac.type) {
8859 case ixgbe_mac_82598EB:
8860 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8861 break;
8862 default:
8863 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8864 break;
0c254d86 8865 }
caafb95d
JK		 8866
8867 /* don't check link if we failed to enumerate functions */
8868 if (expected_gts > 0)
8869 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8870
339de30f 8871 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
6a2aae5a 8872 if (err)
339de30f 8873 strlcpy(part_str, "Unknown", sizeof(part_str));
6a2aae5a
JK		 8874 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8875 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8876 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
e7cf745b 8877 part_str);
6a2aae5a
JK		 8878 else
8879 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8880 hw->mac.type, hw->phy.type, part_str);
8881
8882 e_dev_info("%pM\n", netdev->dev_addr);
8883
9a799d71 8884 /* reset the hardware with the new settings */
794caeb2 8885 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8886 if (err == IXGBE_ERR_EEPROM_VERSION) {
8887 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8888 e_dev_warn("This device is a pre-production adapter/LOM. "
8889 "Please be aware there may be issues associated "
8890 "with your hardware. If you are experiencing "
8891 "problems please contact your Intel or hardware "
8892 "representative who provided you with this "
8893 "hardware.\n");
794caeb2 8894 }
9a799d71
AK		 8895 strcpy(netdev->name, "eth%d");
8896 err = register_netdev(netdev);
8897 if (err)
8898 goto err_register;
8899
0fb6a55c
ET		 8900 pci_set_drvdata(pdev, adapter);
8901
ec74a471
ET		 8902 /* power down the optics for 82599 SFP+ fiber */
8903 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8904 hw->mac.ops.disable_tx_laser(hw);
8905
54386467
JB		 8906 /* carrier off reporting is important to ethtool even BEFORE open */
8907 netif_carrier_off(netdev);
8908
5dd2d332 8909#ifdef CONFIG_IXGBE_DCA
652f093f 8910 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8911 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8912 ixgbe_setup_dca(adapter);
8913 }
8914#endif
1cdd1ec8 8915 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8916 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8917 for (i = 0; i < adapter->num_vfs; i++)
8918 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8919 }
8920
2466dd9c
JK		 8921 /* firmware requires driver version to be 0xFFFFFFFF
8922 * since os does not support feature
8923 */
9612de92 8924 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8925 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8926 0xFF);
9612de92 8927
0365e6e4
PW		 8928 /* add san mac addr to netdev */
8929 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8930
ea81875a 8931 e_dev_info("%s\n", ixgbe_default_device_descr);
3ca8bc6d 8932
1210982b 8933#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8934 if (ixgbe_sysfs_init(adapter))
8935 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8936#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8937
00949167 8938 ixgbe_dbg_adapter_init(adapter);
00949167 8939
d1a35ee2
ET		 8940 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
8941 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8942 hw->mac.ops.setup_link(hw,
8943 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8944 true);
8945
9a799d71
AK		 8946 return 0;
8947
8948err_register:
5eba3699 8949 ixgbe_release_hw_control(adapter);
7a921c93 8950 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8951err_sw_init:
99d74487 8952 ixgbe_disable_sriov(adapter);
7086400d 8953 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8954 iounmap(adapter->io_addr);
5d7daa35 8955 kfree(adapter->mac_table);
9a799d71 8956err_ioremap:
b5b2ffc0 8957 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 8958 free_netdev(netdev);
8959err_alloc_etherdev:
e8e9f696
JP		 8960 pci_release_selected_regions(pdev,
8961 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8962err_pci_reg:
8963err_dma:
b5b2ffc0 8964 if (!adapter || disable_dev)
41c62843 8965 pci_disable_device(pdev);
9a799d71
AK		 8966 return err;
8967}
8968
8969/**
8970 * ixgbe_remove - Device Removal Routine
8971 * @pdev: PCI device information struct
8972 *
8973 * ixgbe_remove is called by the PCI subsystem to alert the driver
8974 * that it should release a PCI device. The could be caused by a
8975 * Hot-Plug event, or because the driver is going to be removed from
8976 * memory.
8977 **/
9f9a12f8 8978static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8979{
c60fbb00 8980 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
0fb6a55c 8981 struct net_device *netdev;
b5b2ffc0 8982 bool disable_dev;
9a799d71 8983
0fb6a55c
ET		 8984 /* if !adapter then we already cleaned up in probe */
8985 if (!adapter)
8986 return;
8987
8988 netdev = adapter->netdev;
00949167 8989 ixgbe_dbg_adapter_exit(adapter);
00949167 8990
09f40aed 8991 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8992 cancel_work_sync(&adapter->service_task);
9a799d71 8993
3a6a4eda 8994
5dd2d332 8995#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8996 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8997 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8998 dca_remove_requester(&pdev->dev);
8999 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
9000 }
9001
9002#endif
1210982b 9003#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 9004 ixgbe_sysfs_exit(adapter);
1210982b 9005#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 9006
0365e6e4
PW		 9007 /* remove the added san mac */
9008 ixgbe_del_sanmac_netdev(netdev);
9009
c4900be0
DS		 9010 if (netdev->reg_state == NETREG_REGISTERED)
9011 unregister_netdev(netdev);
9a799d71 9012
da36b647
GR		 9013#ifdef CONFIG_PCI_IOV
9014 /*
9015 * Only disable SR-IOV on unload if the user specified the now
9016 * deprecated max_vfs module parameter.
9017 */
9018 if (max_vfs)
9019 ixgbe_disable_sriov(adapter);
9020#endif
7a921c93 9021 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 9022
021230d4 9023 ixgbe_release_hw_control(adapter);
9a799d71 9024
2b1588c3
AD		 9025#ifdef CONFIG_DCB
9026 kfree(adapter->ixgbe_ieee_pfc);
9027 kfree(adapter->ixgbe_ieee_ets);
9028
9029#endif
2a1a091c 9030 iounmap(adapter->io_addr);
9ce77666 9031 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 9032 IORESOURCE_MEM));
9a799d71 9033
849c4542 9034 e_dev_info("complete\n");
021230d4 9035
5d7daa35 9036 kfree(adapter->mac_table);
b5b2ffc0 9037 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
9a799d71
AK		 9038 free_netdev(netdev);
9039
19d5afd4 9040 pci_disable_pcie_error_reporting(pdev);
6fabd715 9041
b5b2ffc0 9042 if (disable_dev)
41c62843 9043 pci_disable_device(pdev);
9a799d71
AK		 9044}
9045
9046/**
9047 * ixgbe_io_error_detected - called when PCI error is detected
9048 * @pdev: Pointer to PCI device
9049 * @state: The current pci connection state
9050 *
9051 * This function is called after a PCI bus error affecting
9052 * this device has been detected.
9053 */
9054static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 9055 pci_channel_state_t state)
9a799d71 9056{
c60fbb00
AD		 9057 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9058 struct net_device *netdev = adapter->netdev;
9a799d71 9059
83c61fa9 9060#ifdef CONFIG_PCI_IOV
14438464 9061 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 9062 struct pci_dev *bdev, *vfdev;
9063 u32 dw0, dw1, dw2, dw3;
9064 int vf, pos;
9065 u16 req_id, pf_func;
9066
9067 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
9068 adapter->num_vfs == 0)
9069 goto skip_bad_vf_detection;
9070
9071 bdev = pdev->bus->self;
62f87c0e 9072 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 9073 bdev = bdev->bus->self;
9074
9075 if (!bdev)
9076 goto skip_bad_vf_detection;
9077
9078 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
9079 if (!pos)
9080 goto skip_bad_vf_detection;
9081
14438464
MR		 9082 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
9083 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
9084 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
9085 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
9086 if (ixgbe_removed(hw->hw_addr))
9087 goto skip_bad_vf_detection;
83c61fa9
GR		 9088
9089 req_id = dw1 >> 16;
9090 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
9091 if (!(req_id & 0x0080))
9092 goto skip_bad_vf_detection;
9093
9094 pf_func = req_id & 0x01;
9095 if ((pf_func & 1) == (pdev->devfn & 1)) {
9096 unsigned int device_id;
9097
9098 vf = (req_id & 0x7F) >> 1;
9099 e_dev_err("VF %d has caused a PCIe error\n", vf);
9100 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
9101 "%8.8x\tdw3: %8.8x\n",
9102 dw0, dw1, dw2, dw3);
9103 switch (adapter->hw.mac.type) {
9104 case ixgbe_mac_82599EB:
9105 device_id = IXGBE_82599_VF_DEVICE_ID;
9106 break;
9107 case ixgbe_mac_X540:
9108 device_id = IXGBE_X540_VF_DEVICE_ID;
9109 break;
9a75a1ac
DS		 9110 case ixgbe_mac_X550:
9111 device_id = IXGBE_DEV_ID_X550_VF;
9112 break;
9113 case ixgbe_mac_X550EM_x:
9114 device_id = IXGBE_DEV_ID_X550EM_X_VF;
9115 break;
83c61fa9
GR		 9116 default:
9117 device_id = 0;
9118 break;
9119 }
9120
9121 /* Find the pci device of the offending VF */
36e90319 9122 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 9123 while (vfdev) {
9124 if (vfdev->devfn == (req_id & 0xFF))
9125 break;
36e90319 9126 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 9127 device_id, vfdev);
9128 }
9129 /*
9130 * There's a slim chance the VF could have been hot plugged,
9131 * so if it is no longer present we don't need to issue the
9132 * VFLR. Just clean up the AER in that case.
9133 */
9134 if (vfdev) {
9079e416 9135 ixgbe_issue_vf_flr(adapter, vfdev);
b4fafbe9
GR		 9136 /* Free device reference count */
9137 pci_dev_put(vfdev);
83c61fa9
GR		 9138 }
9139
9140 pci_cleanup_aer_uncorrect_error_status(pdev);
9141 }
9142
9143 /*
9144 * Even though the error may have occurred on the other port
9145 * we still need to increment the vf error reference count for
9146 * both ports because the I/O resume function will be called
9147 * for both of them.
9148 */
9149 adapter->vferr_refcount++;
9150
9151 return PCI_ERS_RESULT_RECOVERED;
9152
9153skip_bad_vf_detection:
9154#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 9155 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
9156 return PCI_ERS_RESULT_DISCONNECT;
9157
41c62843 9158 rtnl_lock();
9a799d71
AK		 9159 netif_device_detach(netdev);
9160
41c62843
MR		 9161 if (state == pci_channel_io_perm_failure) {
9162 rtnl_unlock();
3044b8d1 9163 return PCI_ERS_RESULT_DISCONNECT;
41c62843 9164 }
3044b8d1 9165
9a799d71
AK		 9166 if (netif_running(netdev))
9167 ixgbe_down(adapter);
41c62843
MR		 9168
9169 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
9170 pci_disable_device(pdev);
9171 rtnl_unlock();
9a799d71 9172
b4617240 9173 /* Request a slot reset. */
9a799d71
AK		 9174 return PCI_ERS_RESULT_NEED_RESET;
9175}
9176
9177/**
9178 * ixgbe_io_slot_reset - called after the pci bus has been reset.
9179 * @pdev: Pointer to PCI device
9180 *
9181 * Restart the card from scratch, as if from a cold-boot.
9182 */
9183static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
9184{
c60fbb00 9185 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 9186 pci_ers_result_t result;
9187 int err;
9a799d71 9188
9ce77666 9189 if (pci_enable_device_mem(pdev)) {
396e799c 9190 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 9191 result = PCI_ERS_RESULT_DISCONNECT;
9192 } else {
4e857c58 9193 smp_mb__before_atomic();
41c62843 9194 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 9195 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 9196 pci_set_master(pdev);
9197 pci_restore_state(pdev);
c0e1f68b 9198 pci_save_state(pdev);
9a799d71 9199
dd4d8ca6 9200 pci_wake_from_d3(pdev, false);
9a799d71 9201
6fabd715 9202 ixgbe_reset(adapter);
88512539 9203 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 9204 result = PCI_ERS_RESULT_RECOVERED;
9205 }
9206
9207 err = pci_cleanup_aer_uncorrect_error_status(pdev);
9208 if (err) {
849c4542
ET		 9209 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
9210 "failed 0x%0x\n", err);
6fabd715
PWJ		 9211 /* non-fatal, continue */
9212 }
9a799d71 9213
6fabd715 9214 return result;
9a799d71
AK		 9215}
9216
9217/**
9218 * ixgbe_io_resume - called when traffic can start flowing again.
9219 * @pdev: Pointer to PCI device
9220 *
9221 * This callback is called when the error recovery driver tells us that
9222 * its OK to resume normal operation.
9223 */
9224static void ixgbe_io_resume(struct pci_dev *pdev)
9225{
c60fbb00
AD		 9226 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
9227 struct net_device *netdev = adapter->netdev;
9a799d71 9228
83c61fa9
GR		 9229#ifdef CONFIG_PCI_IOV
9230 if (adapter->vferr_refcount) {
9231 e_info(drv, "Resuming after VF err\n");
9232 adapter->vferr_refcount--;
9233 return;
9234 }
9235
9236#endif
c7ccde0f
AD		 9237 if (netif_running(netdev))
9238 ixgbe_up(adapter);
9a799d71
AK		 9239
9240 netif_device_attach(netdev);
9a799d71
AK		 9241}
9242
3646f0e5 9243static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 9244 .error_detected = ixgbe_io_error_detected,
9245 .slot_reset = ixgbe_io_slot_reset,
9246 .resume = ixgbe_io_resume,
9247};
9248
9249static struct pci_driver ixgbe_driver = {
9250 .name = ixgbe_driver_name,
9251 .id_table = ixgbe_pci_tbl,
9252 .probe = ixgbe_probe,
9f9a12f8 9253 .remove = ixgbe_remove,
9a799d71
AK		 9254#ifdef CONFIG_PM
9255 .suspend = ixgbe_suspend,
9256 .resume = ixgbe_resume,
9257#endif
9258 .shutdown = ixgbe_shutdown,
da36b647 9259 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 9260 .err_handler = &ixgbe_err_handler
9261};
9262
9263/**
9264 * ixgbe_init_module - Driver Registration Routine
9265 *
9266 * ixgbe_init_module is the first routine called when the driver is
9267 * loaded. All it does is register with the PCI subsystem.
9268 **/
9269static int __init ixgbe_init_module(void)
9270{
9271 int ret;
c7689578 9272 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 9273 pr_info("%s\n", ixgbe_copyright);
9a799d71 9274
00949167 9275 ixgbe_dbg_init();
00949167 9276
f01fc1a8
JK		 9277 ret = pci_register_driver(&ixgbe_driver);
9278 if (ret) {
f01fc1a8 9279 ixgbe_dbg_exit();
f01fc1a8
JK		 9280 return ret;
9281 }
9282
5dd2d332 9283#ifdef CONFIG_IXGBE_DCA
bd0362dd 9284 dca_register_notify(&dca_notifier);
bd0362dd 9285#endif
5dd2d332 9286
f01fc1a8 9287 return 0;
9a799d71 9288}
b4617240 9289
9a799d71
AK		 9290module_init(ixgbe_init_module);
9291
9292/**
9293 * ixgbe_exit_module - Driver Exit Cleanup Routine
9294 *
9295 * ixgbe_exit_module is called just before the driver is removed
9296 * from memory.
9297 **/
9298static void __exit ixgbe_exit_module(void)
9299{
5dd2d332 9300#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 9301 dca_unregister_notify(&dca_notifier);
9302#endif
9a799d71 9303 pci_unregister_driver(&ixgbe_driver);
00949167 9304
00949167 9305 ixgbe_dbg_exit();
9a799d71 9306}
bd0362dd 9307
5dd2d332 9308#ifdef CONFIG_IXGBE_DCA
bd0362dd 9309static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 9310 void *p)
bd0362dd
JC		 9311{
9312 int ret_val;
9313
9314 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 9315 __ixgbe_notify_dca);
bd0362dd
JC		 9316
9317 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
9318}
b453368d 9319
5dd2d332 9320#endif /* CONFIG_IXGBE_DCA */
849c4542 9321
9a799d71
AK		 9322module_exit(ixgbe_exit_module);
9323
9324/* ixgbe_main.c */
Linux kernel - Deliverables
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