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ixgbe: fix spelling errors
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
70c71606 47#include <linux/prefetch.h>
eacd73f7 48#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 49
50#include "ixgbe.h"
51#include "ixgbe_common.h"
ee5f784a 52#include "ixgbe_dcb_82599.h"
1cdd1ec8 53#include "ixgbe_sriov.h"
9a799d71
AK		 54
55char ixgbe_driver_name[] = "ixgbe";
9c8eb720 56static const char ixgbe_driver_string[] =
e8e9f696 57 "Intel(R) 10 Gigabit PCI Express Network Driver";
ea81875a
NP		 58char ixgbe_default_device_descr[] =
59 "Intel(R) 10 Gigabit Network Connection";
75e3d3c6 60#define MAJ 3
19d478bb
DS		 61#define MIN 6
62#define BUILD 7
75e3d3c6 63#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
a38a104d 64 __stringify(BUILD) "-k"
9c8eb720 65const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 66static const char ixgbe_copyright[] =
94971820 67 "Copyright (c) 1999-2012 Intel Corporation.";
9a799d71
AK		 68
69static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 70 [board_82598] = &ixgbe_82598_info,
e8e26350 71 [board_82599] = &ixgbe_82599_info,
fe15e8e1 72 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 73};
74
75/* ixgbe_pci_tbl - PCI Device ID Table
76 *
77 * Wildcard entries (PCI_ANY_ID) should come last
78 * Last entry must be all 0s
79 *
80 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
81 * Class, Class Mask, private data (not used) }
82 */
a3aa1884 83static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 84 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
9a799d71
AK		 112 /* required last entry */
113 {0, }
114};
115MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
116
5dd2d332 117#ifdef CONFIG_IXGBE_DCA
bd0362dd 118static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 119 void *p);
bd0362dd
JC		 120static struct notifier_block dca_notifier = {
121 .notifier_call = ixgbe_notify_dca,
122 .next = NULL,
123 .priority = 0
124};
125#endif
126
1cdd1ec8
GR		 127#ifdef CONFIG_PCI_IOV
128static unsigned int max_vfs;
129module_param(max_vfs, uint, 0);
e8e9f696
JP		 130MODULE_PARM_DESC(max_vfs,
131 "Maximum number of virtual functions to allocate per physical function");
1cdd1ec8
GR		 132#endif /* CONFIG_PCI_IOV */
133
8ef78adc
PWJ		 134static unsigned int allow_unsupported_sfp;
135module_param(allow_unsupported_sfp, uint, 0);
136MODULE_PARM_DESC(allow_unsupported_sfp,
137 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
138
9a799d71
AK		 139MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
140MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
141MODULE_LICENSE("GPL");
142MODULE_VERSION(DRV_VERSION);
143
144#define DEFAULT_DEBUG_LEVEL_SHIFT 3
145
7086400d
AD		 146static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
147{
148 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
149 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
150 schedule_work(&adapter->service_task);
151}
152
153static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
154{
155 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
156
52f33af8 157 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 158 smp_mb__before_clear_bit();
159 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
160}
161
dcd79aeb
TI		 162struct ixgbe_reg_info {
163 u32 ofs;
164 char *name;
165};
166
167static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
168
169 /* General Registers */
170 {IXGBE_CTRL, "CTRL"},
171 {IXGBE_STATUS, "STATUS"},
172 {IXGBE_CTRL_EXT, "CTRL_EXT"},
173
174 /* Interrupt Registers */
175 {IXGBE_EICR, "EICR"},
176
177 /* RX Registers */
178 {IXGBE_SRRCTL(0), "SRRCTL"},
179 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
180 {IXGBE_RDLEN(0), "RDLEN"},
181 {IXGBE_RDH(0), "RDH"},
182 {IXGBE_RDT(0), "RDT"},
183 {IXGBE_RXDCTL(0), "RXDCTL"},
184 {IXGBE_RDBAL(0), "RDBAL"},
185 {IXGBE_RDBAH(0), "RDBAH"},
186
187 /* TX Registers */
188 {IXGBE_TDBAL(0), "TDBAL"},
189 {IXGBE_TDBAH(0), "TDBAH"},
190 {IXGBE_TDLEN(0), "TDLEN"},
191 {IXGBE_TDH(0), "TDH"},
192 {IXGBE_TDT(0), "TDT"},
193 {IXGBE_TXDCTL(0), "TXDCTL"},
194
195 /* List Terminator */
196 {}
197};
198
199
200/*
201 * ixgbe_regdump - register printout routine
202 */
203static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
204{
205 int i = 0, j = 0;
206 char rname[16];
207 u32 regs[64];
208
209 switch (reginfo->ofs) {
210 case IXGBE_SRRCTL(0):
211 for (i = 0; i < 64; i++)
212 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
213 break;
214 case IXGBE_DCA_RXCTRL(0):
215 for (i = 0; i < 64; i++)
216 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
217 break;
218 case IXGBE_RDLEN(0):
219 for (i = 0; i < 64; i++)
220 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
221 break;
222 case IXGBE_RDH(0):
223 for (i = 0; i < 64; i++)
224 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
225 break;
226 case IXGBE_RDT(0):
227 for (i = 0; i < 64; i++)
228 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
229 break;
230 case IXGBE_RXDCTL(0):
231 for (i = 0; i < 64; i++)
232 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
233 break;
234 case IXGBE_RDBAL(0):
235 for (i = 0; i < 64; i++)
236 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
237 break;
238 case IXGBE_RDBAH(0):
239 for (i = 0; i < 64; i++)
240 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
241 break;
242 case IXGBE_TDBAL(0):
243 for (i = 0; i < 64; i++)
244 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
245 break;
246 case IXGBE_TDBAH(0):
247 for (i = 0; i < 64; i++)
248 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
249 break;
250 case IXGBE_TDLEN(0):
251 for (i = 0; i < 64; i++)
252 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
253 break;
254 case IXGBE_TDH(0):
255 for (i = 0; i < 64; i++)
256 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
257 break;
258 case IXGBE_TDT(0):
259 for (i = 0; i < 64; i++)
260 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
261 break;
262 case IXGBE_TXDCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
265 break;
266 default:
c7689578 267 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 268 IXGBE_READ_REG(hw, reginfo->ofs));
269 return;
270 }
271
272 for (i = 0; i < 8; i++) {
273 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 274 pr_err("%-15s", rname);
dcd79aeb 275 for (j = 0; j < 8; j++)
c7689578
JP		 276 pr_cont(" %08x", regs[i*8+j]);
277 pr_cont("\n");
dcd79aeb
TI		 278 }
279
280}
281
282/*
283 * ixgbe_dump - Print registers, tx-rings and rx-rings
284 */
285static void ixgbe_dump(struct ixgbe_adapter *adapter)
286{
287 struct net_device *netdev = adapter->netdev;
288 struct ixgbe_hw *hw = &adapter->hw;
289 struct ixgbe_reg_info *reginfo;
290 int n = 0;
291 struct ixgbe_ring *tx_ring;
292 struct ixgbe_tx_buffer *tx_buffer_info;
293 union ixgbe_adv_tx_desc *tx_desc;
294 struct my_u0 { u64 a; u64 b; } *u0;
295 struct ixgbe_ring *rx_ring;
296 union ixgbe_adv_rx_desc *rx_desc;
297 struct ixgbe_rx_buffer *rx_buffer_info;
298 u32 staterr;
299 int i = 0;
300
301 if (!netif_msg_hw(adapter))
302 return;
303
304 /* Print netdevice Info */
305 if (netdev) {
306 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 307 pr_info("Device Name state "
dcd79aeb 308 "trans_start last_rx\n");
c7689578
JP		 309 pr_info("%-15s %016lX %016lX %016lX\n",
310 netdev->name,
311 netdev->state,
312 netdev->trans_start,
313 netdev->last_rx);
dcd79aeb
TI		 314 }
315
316 /* Print Registers */
317 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 318 pr_info(" Register Name Value\n");
dcd79aeb
TI		 319 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
320 reginfo->name; reginfo++) {
321 ixgbe_regdump(hw, reginfo);
322 }
323
324 /* Print TX Ring Summary */
325 if (!netdev || !netif_running(netdev))
326 goto exit;
327
328 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
c7689578 329 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
dcd79aeb
TI		 330 for (n = 0; n < adapter->num_tx_queues; n++) {
331 tx_ring = adapter->tx_ring[n];
332 tx_buffer_info =
333 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
d3d00239 334 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n",
dcd79aeb
TI		 335 n, tx_ring->next_to_use, tx_ring->next_to_clean,
336 (u64)tx_buffer_info->dma,
337 tx_buffer_info->length,
338 tx_buffer_info->next_to_watch,
339 (u64)tx_buffer_info->time_stamp);
340 }
341
342 /* Print TX Rings */
343 if (!netif_msg_tx_done(adapter))
344 goto rx_ring_summary;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
347
348 /* Transmit Descriptor Formats
349 *
350 * Advanced Transmit Descriptor
351 * +--------------------------------------------------------------+
352 * 0 | Buffer Address [63:0] |
353 * +--------------------------------------------------------------+
354 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
355 * +--------------------------------------------------------------+
356 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
357 */
358
359 for (n = 0; n < adapter->num_tx_queues; n++) {
360 tx_ring = adapter->tx_ring[n];
c7689578
JP		 361 pr_info("------------------------------------\n");
362 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
363 pr_info("------------------------------------\n");
364 pr_info("T [desc] [address 63:0 ] "
dcd79aeb
TI		 365 "[PlPOIdStDDt Ln] [bi->dma ] "
366 "leng ntw timestamp bi->skb\n");
367
368 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 369 tx_desc = IXGBE_TX_DESC(tx_ring, i);
dcd79aeb
TI		 370 tx_buffer_info = &tx_ring->tx_buffer_info[i];
371 u0 = (struct my_u0 *)tx_desc;
c7689578 372 pr_info("T [0x%03X] %016llX %016llX %016llX"
d3d00239 373 " %04X %p %016llX %p", i,
dcd79aeb
TI		 374 le64_to_cpu(u0->a),
375 le64_to_cpu(u0->b),
376 (u64)tx_buffer_info->dma,
377 tx_buffer_info->length,
378 tx_buffer_info->next_to_watch,
379 (u64)tx_buffer_info->time_stamp,
380 tx_buffer_info->skb);
381 if (i == tx_ring->next_to_use &&
382 i == tx_ring->next_to_clean)
c7689578 383 pr_cont(" NTC/U\n");
dcd79aeb 384 else if (i == tx_ring->next_to_use)
c7689578 385 pr_cont(" NTU\n");
dcd79aeb 386 else if (i == tx_ring->next_to_clean)
c7689578 387 pr_cont(" NTC\n");
dcd79aeb 388 else
c7689578 389 pr_cont("\n");
dcd79aeb
TI		 390
391 if (netif_msg_pktdata(adapter) &&
392 tx_buffer_info->dma != 0)
393 print_hex_dump(KERN_INFO, "",
394 DUMP_PREFIX_ADDRESS, 16, 1,
395 phys_to_virt(tx_buffer_info->dma),
396 tx_buffer_info->length, true);
397 }
398 }
399
400 /* Print RX Rings Summary */
401rx_ring_summary:
402 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 403 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 404 for (n = 0; n < adapter->num_rx_queues; n++) {
405 rx_ring = adapter->rx_ring[n];
c7689578
JP		 406 pr_info("%5d %5X %5X\n",
407 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 408 }
409
410 /* Print RX Rings */
411 if (!netif_msg_rx_status(adapter))
412 goto exit;
413
414 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
415
416 /* Advanced Receive Descriptor (Read) Format
417 * 63 1 0
418 * +-----------------------------------------------------+
419 * 0 | Packet Buffer Address [63:1] |A0/NSE|
420 * +----------------------------------------------+------+
421 * 8 | Header Buffer Address [63:1] | DD |
422 * +-----------------------------------------------------+
423 *
424 *
425 * Advanced Receive Descriptor (Write-Back) Format
426 *
427 * 63 48 47 32 31 30 21 20 16 15 4 3 0
428 * +------------------------------------------------------+
429 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
430 * | Checksum Ident | | | | Type | Type |
431 * +------------------------------------------------------+
432 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
433 * +------------------------------------------------------+
434 * 63 48 47 32 31 20 19 0
435 */
436 for (n = 0; n < adapter->num_rx_queues; n++) {
437 rx_ring = adapter->rx_ring[n];
c7689578
JP		 438 pr_info("------------------------------------\n");
439 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
440 pr_info("------------------------------------\n");
441 pr_info("R [desc] [ PktBuf A0] "
dcd79aeb
TI		 442 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
443 "<-- Adv Rx Read format\n");
c7689578 444 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
dcd79aeb
TI		 445 "[vl er S cks ln] ---------------- [bi->skb] "
446 "<-- Adv Rx Write-Back format\n");
447
448 for (i = 0; i < rx_ring->count; i++) {
449 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 450 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 451 u0 = (struct my_u0 *)rx_desc;
452 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
453 if (staterr & IXGBE_RXD_STAT_DD) {
454 /* Descriptor Done */
c7689578 455 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 456 "%016llX ---------------- %p", i,
457 le64_to_cpu(u0->a),
458 le64_to_cpu(u0->b),
459 rx_buffer_info->skb);
460 } else {
c7689578 461 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 462 "%016llX %016llX %p", i,
463 le64_to_cpu(u0->a),
464 le64_to_cpu(u0->b),
465 (u64)rx_buffer_info->dma,
466 rx_buffer_info->skb);
467
468 if (netif_msg_pktdata(adapter)) {
469 print_hex_dump(KERN_INFO, "",
470 DUMP_PREFIX_ADDRESS, 16, 1,
471 phys_to_virt(rx_buffer_info->dma),
472 rx_ring->rx_buf_len, true);
473
474 if (rx_ring->rx_buf_len
919e78a6 475 < IXGBE_RXBUFFER_2K)
dcd79aeb
TI		 476 print_hex_dump(KERN_INFO, "",
477 DUMP_PREFIX_ADDRESS, 16, 1,
478 phys_to_virt(
479 rx_buffer_info->page_dma +
480 rx_buffer_info->page_offset
481 ),
482 PAGE_SIZE/2, true);
483 }
484 }
485
486 if (i == rx_ring->next_to_use)
c7689578 487 pr_cont(" NTU\n");
dcd79aeb 488 else if (i == rx_ring->next_to_clean)
c7689578 489 pr_cont(" NTC\n");
dcd79aeb 490 else
c7689578 491 pr_cont("\n");
dcd79aeb
TI		 492
493 }
494 }
495
496exit:
497 return;
498}
499
5eba3699
AV		 500static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
501{
502 u32 ctrl_ext;
503
504 /* Let firmware take over control of h/w */
505 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
506 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 507 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 508}
509
510static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
511{
512 u32 ctrl_ext;
513
514 /* Let firmware know the driver has taken over */
515 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 517 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 518}
9a799d71 519
e8e26350
PW		 520/*
521 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
522 * @adapter: pointer to adapter struct
523 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
524 * @queue: queue to map the corresponding interrupt to
525 * @msix_vector: the vector to map to the corresponding queue
526 *
527 */
528static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 529 u8 queue, u8 msix_vector)
9a799d71
AK		 530{
531 u32 ivar, index;
e8e26350
PW		 532 struct ixgbe_hw *hw = &adapter->hw;
533 switch (hw->mac.type) {
534 case ixgbe_mac_82598EB:
535 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
536 if (direction == -1)
537 direction = 0;
538 index = (((direction * 64) + queue) >> 2) & 0x1F;
539 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
540 ivar &= ~(0xFF << (8 * (queue & 0x3)));
541 ivar |= (msix_vector << (8 * (queue & 0x3)));
542 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
543 break;
544 case ixgbe_mac_82599EB:
b93a2226 545 case ixgbe_mac_X540:
e8e26350
PW		 546 if (direction == -1) {
547 /* other causes */
548 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
549 index = ((queue & 1) * 8);
550 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
551 ivar &= ~(0xFF << index);
552 ivar |= (msix_vector << index);
553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
554 break;
555 } else {
556 /* tx or rx causes */
557 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
558 index = ((16 * (queue & 1)) + (8 * direction));
559 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
560 ivar &= ~(0xFF << index);
561 ivar |= (msix_vector << index);
562 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
563 break;
564 }
565 default:
566 break;
567 }
9a799d71
AK		 568}
569
fe49f04a 570static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 571 u64 qmask)
fe49f04a
AD		 572{
573 u32 mask;
574
bd508178
AD		 575 switch (adapter->hw.mac.type) {
576 case ixgbe_mac_82598EB:
fe49f04a
AD		 577 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 579 break;
580 case ixgbe_mac_82599EB:
b93a2226 581 case ixgbe_mac_X540:
fe49f04a
AD		 582 mask = (qmask & 0xFFFFFFFF);
583 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
584 mask = (qmask >> 32);
585 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 586 break;
587 default:
588 break;
fe49f04a
AD		 589 }
590}
591
d3d00239
AD		 592static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring,
593 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 594{
d3d00239
AD		 595 if (tx_buffer->dma) {
596 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE)
597 dma_unmap_page(ring->dev,
598 tx_buffer->dma,
599 tx_buffer->length,
600 DMA_TO_DEVICE);
e5a43549 601 else
d3d00239
AD		 602 dma_unmap_single(ring->dev,
603 tx_buffer->dma,
604 tx_buffer->length,
605 DMA_TO_DEVICE);
e5a43549 606 }
d3d00239
AD		 607 tx_buffer->dma = 0;
608}
609
610void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
611 struct ixgbe_tx_buffer *tx_buffer_info)
612{
613 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
614 if (tx_buffer_info->skb)
9a799d71 615 dev_kfree_skb_any(tx_buffer_info->skb);
d3d00239 616 tx_buffer_info->skb = NULL;
9a799d71
AK		 617 /* tx_buffer_info must be completely set up in the transmit path */
618}
619
c84d324c
JF		 620static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
621{
622 struct ixgbe_hw *hw = &adapter->hw;
623 struct ixgbe_hw_stats *hwstats = &adapter->stats;
624 u32 data = 0;
625 u32 xoff[8] = {0};
626 int i;
627
628 if ((hw->fc.current_mode == ixgbe_fc_full) ||
629 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
630 switch (hw->mac.type) {
631 case ixgbe_mac_82598EB:
632 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
6837e895
PW		 633 break;
634 default:
c84d324c
JF		 635 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
636 }
637 hwstats->lxoffrxc += data;
638
639 /* refill credits (no tx hang) if we received xoff */
640 if (!data)
641 return;
642
643 for (i = 0; i < adapter->num_tx_queues; i++)
644 clear_bit(__IXGBE_HANG_CHECK_ARMED,
645 &adapter->tx_ring[i]->state);
646 return;
647 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
648 return;
649
650 /* update stats for each tc, only valid with PFC enabled */
651 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
652 switch (hw->mac.type) {
653 case ixgbe_mac_82598EB:
654 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 655 break;
c84d324c
JF		 656 default:
657 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 658 }
c84d324c
JF		 659 hwstats->pxoffrxc[i] += xoff[i];
660 }
661
662 /* disarm tx queues that have received xoff frames */
663 for (i = 0; i < adapter->num_tx_queues; i++) {
664 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
fb5475ff 665 u8 tc = tx_ring->dcb_tc;
c84d324c
JF		 666
667 if (xoff[tc])
668 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 669 }
26f23d82
YZ		 670}
671
c84d324c 672static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 673{
c84d324c
JF		 674 return ring->tx_stats.completed;
675}
676
677static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
678{
679 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 680 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 681
c84d324c
JF		 682 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
683 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
684
685 if (head != tail)
686 return (head < tail) ?
687 tail - head : (tail + ring->count - head);
688
689 return 0;
690}
691
692static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
693{
694 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
695 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
696 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
697 bool ret = false;
698
7d637bcc 699 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 700
701 /*
702 * Check for a hung queue, but be thorough. This verifies
703 * that a transmit has been completed since the previous
704 * check AND there is at least one packet pending. The
705 * ARMED bit is set to indicate a potential hang. The
706 * bit is cleared if a pause frame is received to remove
707 * false hang detection due to PFC or 802.3x frames. By
708 * requiring this to fail twice we avoid races with
709 * pfc clearing the ARMED bit and conditions where we
710 * run the check_tx_hang logic with a transmit completion
711 * pending but without time to complete it yet.
712 */
713 if ((tx_done_old == tx_done) && tx_pending) {
714 /* make sure it is true for two checks in a row */
715 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
716 &tx_ring->state);
717 } else {
718 /* update completed stats and continue */
719 tx_ring->tx_stats.tx_done_old = tx_done;
720 /* reset the countdown */
721 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 722 }
723
c84d324c 724 return ret;
9a799d71
AK		 725}
726
c83c6cbd
AD		 727/**
728 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
729 * @adapter: driver private struct
730 **/
731static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
732{
733
734 /* Do the reset outside of interrupt context */
735 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
736 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
737 ixgbe_service_event_schedule(adapter);
738 }
739}
e01c31a5 740
9a799d71
AK		 741/**
742 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 743 * @q_vector: structure containing interrupt and ring information
e01c31a5 744 * @tx_ring: tx ring to clean
9a799d71 745 **/
fe49f04a 746static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 747 struct ixgbe_ring *tx_ring)
9a799d71 748{
fe49f04a 749 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 750 struct ixgbe_tx_buffer *tx_buffer;
751 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 752 unsigned int total_bytes = 0, total_packets = 0;
59224555 753 unsigned int budget = q_vector->tx.work_limit;
d3d00239 754 u16 i = tx_ring->next_to_clean;
9a799d71 755
d3d00239 756 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 757 tx_desc = IXGBE_TX_DESC(tx_ring, i);
12207e49 758
30065e63 759 for (; budget; budget--) {
d3d00239
AD		 760 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
761
762 /* if next_to_watch is not set then there is no work pending */
763 if (!eop_desc)
764 break;
765
766 /* if DD is not set pending work has not been completed */
767 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
768 break;
8ad494b0 769
d3d00239
AD		 770 /* count the packet as being completed */
771 tx_ring->tx_stats.completed++;
772
773 /* clear next_to_watch to prevent false hangs */
774 tx_buffer->next_to_watch = NULL;
8ad494b0 775
d3d00239
AD		 776 /* prevent any other reads prior to eop_desc being verified */
777 rmb();
778
779 do {
780 ixgbe_unmap_tx_resource(tx_ring, tx_buffer);
8ad494b0 781 tx_desc->wb.status = 0;
d3d00239
AD		 782 if (likely(tx_desc == eop_desc)) {
783 eop_desc = NULL;
784 dev_kfree_skb_any(tx_buffer->skb);
785 tx_buffer->skb = NULL;
786
787 total_bytes += tx_buffer->bytecount;
788 total_packets += tx_buffer->gso_segs;
789 }
9a799d71 790
d3d00239
AD		 791 tx_buffer++;
792 tx_desc++;
8ad494b0 793 i++;
d3d00239 794 if (unlikely(i == tx_ring->count)) {
8ad494b0 795 i = 0;
e01c31a5 796
d3d00239 797 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 798 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 799 }
e01c31a5 800
d3d00239 801 } while (eop_desc);
12207e49
PWJ		 802 }
803
9a799d71 804 tx_ring->next_to_clean = i;
d3d00239 805 u64_stats_update_begin(&tx_ring->syncp);
b953799e 806 tx_ring->stats.bytes += total_bytes;
bd198058 807 tx_ring->stats.packets += total_packets;
d3d00239 808 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 809 q_vector->tx.total_bytes += total_bytes;
810 q_vector->tx.total_packets += total_packets;
b953799e 811
c84d324c
JF		 812 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
813 /* schedule immediate reset if we believe we hung */
814 struct ixgbe_hw *hw = &adapter->hw;
e4f74028 815 tx_desc = IXGBE_TX_DESC(tx_ring, i);
c84d324c
JF		 816 e_err(drv, "Detected Tx Unit Hang\n"
817 " Tx Queue <%d>\n"
818 " TDH, TDT <%x>, <%x>\n"
819 " next_to_use <%x>\n"
820 " next_to_clean <%x>\n"
821 "tx_buffer_info[next_to_clean]\n"
822 " time_stamp <%lx>\n"
823 " jiffies <%lx>\n",
824 tx_ring->queue_index,
825 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
826 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 827 tx_ring->next_to_use, i,
828 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 829
830 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
831
832 e_info(probe,
833 "tx hang %d detected on queue %d, resetting adapter\n",
834 adapter->tx_timeout_count + 1, tx_ring->queue_index);
835
b953799e 836 /* schedule immediate reset if we believe we hung */
c83c6cbd 837 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 838
839 /* the adapter is about to reset, no point in enabling stuff */
59224555 840 return true;
b953799e 841 }
9a799d71 842
e092be60 843#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 844 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 845 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 846 /* Make sure that anybody stopping the queue after this
847 * sees the new next_to_clean.
848 */
849 smp_mb();
fc77dc3c 850 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
30eba97a 851 !test_bit(__IXGBE_DOWN, &adapter->state)) {
fc77dc3c 852 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 853 ++tx_ring->tx_stats.restart_queue;
30eba97a 854 }
e092be60 855 }
9a799d71 856
59224555 857 return !!budget;
9a799d71
AK		 858}
859
5dd2d332 860#ifdef CONFIG_IXGBE_DCA
bd0362dd 861static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 862 struct ixgbe_ring *rx_ring,
863 int cpu)
bd0362dd 864{
33cf09c9 865 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 866 u32 rxctrl;
33cf09c9
AD		 867 u8 reg_idx = rx_ring->reg_idx;
868
869 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
870 switch (hw->mac.type) {
871 case ixgbe_mac_82598EB:
872 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
263a84e7 873 rxctrl |= dca3_get_tag(rx_ring->dev, cpu);
33cf09c9
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
33cf09c9 877 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
263a84e7 878 rxctrl |= (dca3_get_tag(rx_ring->dev, cpu) <<
33cf09c9
AD		 879 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
880 break;
881 default:
882 break;
bd0362dd 883 }
33cf09c9
AD		 884 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
885 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
886 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
33cf09c9 887 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
bd0362dd
JC		 888}
889
890static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
33cf09c9
AD		 891 struct ixgbe_ring *tx_ring,
892 int cpu)
bd0362dd 893{
33cf09c9 894 struct ixgbe_hw *hw = &adapter->hw;
bd0362dd 895 u32 txctrl;
33cf09c9
AD		 896 u8 reg_idx = tx_ring->reg_idx;
897
898 switch (hw->mac.type) {
899 case ixgbe_mac_82598EB:
900 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
901 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
263a84e7 902 txctrl |= dca3_get_tag(tx_ring->dev, cpu);
33cf09c9 903 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 904 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
905 break;
906 case ixgbe_mac_82599EB:
b93a2226 907 case ixgbe_mac_X540:
33cf09c9
AD		 908 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
909 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
263a84e7 910 txctrl |= (dca3_get_tag(tx_ring->dev, cpu) <<
33cf09c9
AD		 911 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
912 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
33cf09c9
AD		 913 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
914 break;
915 default:
916 break;
917 }
918}
919
920static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
921{
922 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 923 struct ixgbe_ring *ring;
bd0362dd 924 int cpu = get_cpu();
bd0362dd 925
33cf09c9
AD		 926 if (q_vector->cpu == cpu)
927 goto out_no_update;
928
efe3d3c8
AD		 929 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
930 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 931
efe3d3c8
AD		 932 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
933 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 934
935 q_vector->cpu = cpu;
936out_no_update:
bd0362dd
JC		 937 put_cpu();
938}
939
940static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
941{
33cf09c9 942 int num_q_vectors;
bd0362dd
JC		 943 int i;
944
945 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
946 return;
947
e35ec126
AD		 948 /* always use CB2 mode, difference is masked in the CB driver */
949 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
950
33cf09c9
AD		 951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
953 else
954 num_q_vectors = 1;
955
956 for (i = 0; i < num_q_vectors; i++) {
957 adapter->q_vector[i]->cpu = -1;
958 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 959 }
960}
961
962static int __ixgbe_notify_dca(struct device *dev, void *data)
963{
c60fbb00 964 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 965 unsigned long event = *(unsigned long *)data;
966
2a72c31e 967 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 968 return 0;
969
bd0362dd
JC		 970 switch (event) {
971 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 972 /* if we're already enabled, don't do it again */
973 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
974 break;
652f093f 975 if (dca_add_requester(dev) == 0) {
96b0e0f6 976 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 977 ixgbe_setup_dca(adapter);
978 break;
979 }
980 /* Fall Through since DCA is disabled. */
981 case DCA_PROVIDER_REMOVE:
982 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
983 dca_remove_requester(dev);
984 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
985 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
986 }
987 break;
988 }
989
652f093f 990 return 0;
bd0362dd 991}
5dd2d332 992#endif /* CONFIG_IXGBE_DCA */
67a74ee2 993
8a0da21b
AD		 994static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
995 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 996 struct sk_buff *skb)
997{
8a0da21b
AD		 998 if (ring->netdev->features & NETIF_F_RXHASH)
999 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1000}
1001
ff886dfc
AD		 1002/**
1003 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1004 * @adapter: address of board private structure
1005 * @rx_desc: advanced rx descriptor
1006 *
1007 * Returns : true if it is FCoE pkt
1008 */
1009static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter,
1010 union ixgbe_adv_rx_desc *rx_desc)
1011{
1012 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1013
1014 return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
1015 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1016 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1017 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1018}
1019
e59bd25d
AV		 1020/**
1021 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1022 * @ring: structure containing ring specific data
1023 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1024 * @skb: skb currently being received and modified
1025 **/
8a0da21b 1026static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1027 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1028 struct sk_buff *skb)
9a799d71 1029{
8a0da21b 1030 skb_checksum_none_assert(skb);
9a799d71 1031
712744be 1032 /* Rx csum disabled */
8a0da21b 1033 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1034 return;
e59bd25d
AV		 1035
1036 /* if IP and error */
f56e0cb1
AD		 1037 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1038 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1039 ring->rx_stats.csum_err++;
9a799d71
AK		 1040 return;
1041 }
e59bd25d 1042
f56e0cb1 1043 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1044 return;
1045
f56e0cb1 1046 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
8bae1b2b
DS		 1047 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1048
1049 /*
1050 * 82599 errata, UDP frames with a 0 checksum can be marked as
1051 * checksum errors.
1052 */
8a0da21b
AD		 1053 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1054 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1055 return;
1056
8a0da21b 1057 ring->rx_stats.csum_err++;
e59bd25d
AV		 1058 return;
1059 }
1060
9a799d71 1061 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1062 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1063}
1064
84ea2591 1065static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1066{
f56e0cb1 1067 rx_ring->next_to_use = val;
e8e26350
PW		 1068 /*
1069 * Force memory writes to complete before letting h/w
1070 * know there are new descriptors to fetch. (Only
1071 * applicable for weak-ordered memory model archs,
1072 * such as IA-64).
1073 */
1074 wmb();
84ea2591 1075 writel(val, rx_ring->tail);
e8e26350
PW		 1076}
1077
f990b79b
AD		 1078static bool ixgbe_alloc_mapped_skb(struct ixgbe_ring *rx_ring,
1079 struct ixgbe_rx_buffer *bi)
1080{
1081 struct sk_buff *skb = bi->skb;
1082 dma_addr_t dma = bi->dma;
1083
1084 if (dma)
1085 return true;
1086
1087 if (likely(!skb)) {
1088 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1089 rx_ring->rx_buf_len);
1090 bi->skb = skb;
1091 if (!skb) {
1092 rx_ring->rx_stats.alloc_rx_buff_failed++;
1093 return false;
1094 }
f990b79b
AD		 1095 }
1096
1097 dma = dma_map_single(rx_ring->dev, skb->data,
1098 rx_ring->rx_buf_len, DMA_FROM_DEVICE);
1099
1100 if (dma_mapping_error(rx_ring->dev, dma)) {
1101 rx_ring->rx_stats.alloc_rx_buff_failed++;
1102 return false;
1103 }
1104
1105 bi->dma = dma;
1106 return true;
1107}
1108
1109static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1110 struct ixgbe_rx_buffer *bi)
1111{
1112 struct page *page = bi->page;
1113 dma_addr_t page_dma = bi->page_dma;
1114 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);
1115
1116 if (page_dma)
1117 return true;
1118
1119 if (!page) {
1120 page = alloc_page(GFP_ATOMIC | __GFP_COLD);
1121 bi->page = page;
1122 if (unlikely(!page)) {
1123 rx_ring->rx_stats.alloc_rx_page_failed++;
1124 return false;
1125 }
1126 }
1127
1128 page_dma = dma_map_page(rx_ring->dev, page,
1129 page_offset, PAGE_SIZE / 2,
1130 DMA_FROM_DEVICE);
1131
1132 if (dma_mapping_error(rx_ring->dev, page_dma)) {
1133 rx_ring->rx_stats.alloc_rx_page_failed++;
1134 return false;
1135 }
1136
1137 bi->page_dma = page_dma;
1138 bi->page_offset = page_offset;
1139 return true;
1140}
1141
9a799d71 1142/**
f990b79b 1143 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1144 * @rx_ring: ring to place buffers on
1145 * @cleaned_count: number of buffers to replace
9a799d71 1146 **/
fc77dc3c 1147void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1148{
9a799d71 1149 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1150 struct ixgbe_rx_buffer *bi;
d5f398ed 1151 u16 i = rx_ring->next_to_use;
9a799d71 1152
f990b79b
AD		 1153 /* nothing to do or no valid netdev defined */
1154 if (!cleaned_count || !rx_ring->netdev)
fc77dc3c
AD		 1155 return;
1156
e4f74028 1157 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1158 bi = &rx_ring->rx_buffer_info[i];
1159 i -= rx_ring->count;
9a799d71 1160
f990b79b
AD		 1161 while (cleaned_count--) {
1162 if (!ixgbe_alloc_mapped_skb(rx_ring, bi))
1163 break;
d5f398ed 1164
f990b79b
AD		 1165 /* Refresh the desc even if buffer_addrs didn't change
1166 * because each write-back erases this info. */
7d637bcc 1167 if (ring_is_ps_enabled(rx_ring)) {
f990b79b 1168 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
d5f398ed 1169
f990b79b
AD		 1170 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1171 break;
d5f398ed 1172
3a581073 1173 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
9a799d71 1174 } else {
3a581073 1175 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
9a799d71
AK		 1176 }
1177
f990b79b
AD		 1178 rx_desc++;
1179 bi++;
9a799d71 1180 i++;
f990b79b 1181 if (unlikely(!i)) {
e4f74028 1182 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1183 bi = rx_ring->rx_buffer_info;
1184 i -= rx_ring->count;
1185 }
1186
1187 /* clear the hdr_addr for the next_to_use descriptor */
1188 rx_desc->read.hdr_addr = 0;
9a799d71 1189 }
7c6e0a43 1190
f990b79b
AD		 1191 i += rx_ring->count;
1192
f56e0cb1 1193 if (rx_ring->next_to_use != i)
84ea2591 1194 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1195}
1196
c267fc16 1197static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
7c6e0a43 1198{
c267fc16
AD		 1199 /* HW will not DMA in data larger than the given buffer, even if it
1200 * parses the (NFS, of course) header to be larger. In that case, it
1201 * fills the header buffer and spills the rest into the page.
1202 */
1203 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1204 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1205 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1206 if (hlen > IXGBE_RX_HDR_SIZE)
1207 hlen = IXGBE_RX_HDR_SIZE;
1208 return hlen;
7c6e0a43
JB		 1209}
1210
f8212f97 1211/**
4c1975d7
AD		 1212 * ixgbe_merge_active_tail - merge active tail into lro skb
1213 * @tail: pointer to active tail in frag_list
f8212f97 1214 *
4c1975d7
AD		 1215 * This function merges the length and data of an active tail into the
1216 * skb containing the frag_list. It resets the tail's pointer to the head,
1217 * but it leaves the heads pointer to tail intact.
f8212f97 1218 **/
4c1975d7 1219static inline struct sk_buff *ixgbe_merge_active_tail(struct sk_buff *tail)
f8212f97 1220{
4c1975d7 1221 struct sk_buff *head = IXGBE_CB(tail)->head;
f8212f97 1222
4c1975d7
AD		 1223 if (!head)
1224 return tail;
1225
1226 head->len += tail->len;
1227 head->data_len += tail->len;
1228 head->truesize += tail->len;
1229
1230 IXGBE_CB(tail)->head = NULL;
1231
1232 return head;
1233}
1234
1235/**
1236 * ixgbe_add_active_tail - adds an active tail into the skb frag_list
1237 * @head: pointer to the start of the skb
1238 * @tail: pointer to active tail to add to frag_list
1239 *
1240 * This function adds an active tail to the end of the frag list. This tail
1241 * will still be receiving data so we cannot yet ad it's stats to the main
1242 * skb. That is done via ixgbe_merge_active_tail.
1243 **/
1244static inline void ixgbe_add_active_tail(struct sk_buff *head,
1245 struct sk_buff *tail)
1246{
1247 struct sk_buff *old_tail = IXGBE_CB(head)->tail;
1248
1249 if (old_tail) {
1250 ixgbe_merge_active_tail(old_tail);
1251 old_tail->next = tail;
1252 } else {
1253 skb_shinfo(head)->frag_list = tail;
f8212f97
AD		 1254 }
1255
4c1975d7
AD		 1256 IXGBE_CB(tail)->head = head;
1257 IXGBE_CB(head)->tail = tail;
1258}
1259
1260/**
1261 * ixgbe_close_active_frag_list - cleanup pointers on a frag_list skb
1262 * @head: pointer to head of an active frag list
1263 *
1264 * This function will clear the frag_tail_tracker pointer on an active
1265 * frag_list and returns true if the pointer was actually set
1266 **/
1267static inline bool ixgbe_close_active_frag_list(struct sk_buff *head)
1268{
1269 struct sk_buff *tail = IXGBE_CB(head)->tail;
1270
1271 if (!tail)
1272 return false;
1273
1274 ixgbe_merge_active_tail(tail);
1275
1276 IXGBE_CB(head)->tail = NULL;
aa80175a 1277
4c1975d7 1278 return true;
f8212f97
AD		 1279}
1280
1d2024f6
AD		 1281/**
1282 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1283 * @data: pointer to the start of the headers
1284 * @max_len: total length of section to find headers in
1285 *
1286 * This function is meant to determine the length of headers that will
1287 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1288 * motivation of doing this is to only perform one pull for IPv4 TCP
1289 * packets so that we can do basic things like calculating the gso_size
1290 * based on the average data per packet.
1291 **/
1292static unsigned int ixgbe_get_headlen(unsigned char *data,
1293 unsigned int max_len)
1294{
1295 union {
1296 unsigned char *network;
1297 /* l2 headers */
1298 struct ethhdr *eth;
1299 struct vlan_hdr *vlan;
1300 /* l3 headers */
1301 struct iphdr *ipv4;
1302 } hdr;
1303 __be16 protocol;
1304 u8 nexthdr = 0; /* default to not TCP */
1305 u8 hlen;
1306
1307 /* this should never happen, but better safe than sorry */
1308 if (max_len < ETH_HLEN)
1309 return max_len;
1310
1311 /* initialize network frame pointer */
1312 hdr.network = data;
1313
1314 /* set first protocol and move network header forward */
1315 protocol = hdr.eth->h_proto;
1316 hdr.network += ETH_HLEN;
1317
1318 /* handle any vlan tag if present */
1319 if (protocol == __constant_htons(ETH_P_8021Q)) {
1320 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1321 return max_len;
1322
1323 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1324 hdr.network += VLAN_HLEN;
1325 }
1326
1327 /* handle L3 protocols */
1328 if (protocol == __constant_htons(ETH_P_IP)) {
1329 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1330 return max_len;
1331
1332 /* access ihl as a u8 to avoid unaligned access on ia64 */
1333 hlen = (hdr.network[0] & 0x0F) << 2;
1334
1335 /* verify hlen meets minimum size requirements */
1336 if (hlen < sizeof(struct iphdr))
1337 return hdr.network - data;
1338
1339 /* record next protocol */
1340 nexthdr = hdr.ipv4->protocol;
1341 hdr.network += hlen;
1342#ifdef CONFIG_FCOE
1343 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1344 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1345 return max_len;
1346 hdr.network += FCOE_HEADER_LEN;
1347#endif
1348 } else {
1349 return hdr.network - data;
1350 }
1351
1352 /* finally sort out TCP */
1353 if (nexthdr == IPPROTO_TCP) {
1354 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1355 return max_len;
1356
1357 /* access doff as a u8 to avoid unaligned access on ia64 */
1358 hlen = (hdr.network[12] & 0xF0) >> 2;
1359
1360 /* verify hlen meets minimum size requirements */
1361 if (hlen < sizeof(struct tcphdr))
1362 return hdr.network - data;
1363
1364 hdr.network += hlen;
1365 }
1366
1367 /*
1368 * If everything has gone correctly hdr.network should be the
1369 * data section of the packet and will be the end of the header.
1370 * If not then it probably represents the end of the last recognized
1371 * header.
1372 */
1373 if ((hdr.network - data) < max_len)
1374 return hdr.network - data;
1375 else
1376 return max_len;
1377}
1378
4c1975d7
AD		 1379static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring,
1380 union ixgbe_adv_rx_desc *rx_desc,
1381 struct sk_buff *skb)
aa80175a 1382{
4c1975d7
AD		 1383 __le32 rsc_enabled;
1384 u32 rsc_cnt;
1385
1386 if (!ring_is_rsc_enabled(rx_ring))
1387 return;
1388
1389 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1390 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1391
1392 /* If this is an RSC frame rsc_cnt should be non-zero */
1393 if (!rsc_enabled)
1394 return;
1395
1396 rsc_cnt = le32_to_cpu(rsc_enabled);
1397 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1398
1399 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
aa80175a 1400}
43634e82 1401
1d2024f6
AD		 1402static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1403 struct sk_buff *skb)
1404{
1405 u16 hdr_len = ixgbe_get_headlen(skb->data, skb_headlen(skb));
1406
1407 /* set gso_size to avoid messing up TCP MSS */
1408 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1409 IXGBE_CB(skb)->append_cnt);
1410}
1411
1412static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1413 struct sk_buff *skb)
1414{
1415 /* if append_cnt is 0 then frame is not RSC */
1416 if (!IXGBE_CB(skb)->append_cnt)
1417 return;
1418
1419 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1420 rx_ring->rx_stats.rsc_flush++;
1421
1422 ixgbe_set_rsc_gso_size(rx_ring, skb);
1423
1424 /* gso_size is computed using append_cnt so always clear it last */
1425 IXGBE_CB(skb)->append_cnt = 0;
1426}
1427
8a0da21b
AD		 1428/**
1429 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1430 * @rx_ring: rx descriptor ring packet is being transacted on
1431 * @rx_desc: pointer to the EOP Rx descriptor
1432 * @skb: pointer to current skb being populated
f8212f97 1433 *
8a0da21b
AD		 1434 * This function checks the ring, descriptor, and packet information in
1435 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1436 * other fields within the skb.
f8212f97 1437 **/
8a0da21b
AD		 1438static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1439 union ixgbe_adv_rx_desc *rx_desc,
1440 struct sk_buff *skb)
f8212f97 1441{
8a0da21b
AD		 1442 ixgbe_update_rsc_stats(rx_ring, skb);
1443
1444 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1445
8a0da21b
AD		 1446 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1447
1448 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1449 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1450 __vlan_hwaccel_put_tag(skb, vid);
f8212f97
AD		 1451 }
1452
8a0da21b 1453 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1454
8a0da21b 1455 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
f8212f97
AD		 1456}
1457
8a0da21b
AD		 1458static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1459 struct sk_buff *skb)
aa80175a 1460{
8a0da21b
AD		 1461 struct ixgbe_adapter *adapter = q_vector->adapter;
1462
1463 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1464 napi_gro_receive(&q_vector->napi, skb);
1465 else
1466 netif_rx(skb);
aa80175a 1467}
43634e82 1468
4ff7fb12 1469static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1470 struct ixgbe_ring *rx_ring,
4ff7fb12 1471 int budget)
9a799d71 1472{
9a799d71 1473 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
4c1975d7 1474 struct ixgbe_rx_buffer *rx_buffer_info;
9a799d71 1475 struct sk_buff *skb;
d2f4fbe2 1476 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
c267fc16 1477 const int current_node = numa_node_id();
3d8fd385 1478#ifdef IXGBE_FCOE
8a0da21b 1479 struct ixgbe_adapter *adapter = q_vector->adapter;
3d8fd385
YZ		 1480 int ddp_bytes = 0;
1481#endif /* IXGBE_FCOE */
c267fc16
AD		 1482 u16 i;
1483 u16 cleaned_count = 0;
9a799d71
AK		 1484
1485 i = rx_ring->next_to_clean;
e4f74028 1486 rx_desc = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1487
f56e0cb1 1488 while (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) {
7c6e0a43 1489 u32 upper_len = 0;
9a799d71 1490
3c945e5b 1491 rmb(); /* read descriptor and rx_buffer_info after status DD */
9a799d71 1492
c267fc16
AD		 1493 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1494
9a799d71 1495 skb = rx_buffer_info->skb;
9a799d71 1496 rx_buffer_info->skb = NULL;
c267fc16 1497 prefetch(skb->data);
9a799d71 1498
b811ce91
JB		 1499 /* linear means we are building an skb from multiple pages */
1500 if (!skb_is_nonlinear(skb)) {
c267fc16 1501 u16 hlen;
c267fc16
AD		 1502 if (ring_is_ps_enabled(rx_ring)) {
1503 hlen = ixgbe_get_hlen(rx_desc);
1504 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1505 } else {
1506 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1507 }
1508
1509 skb_put(skb, hlen);
4c1975d7
AD		 1510
1511 /*
1512 * Delay unmapping of the first packet. It carries the
1513 * header information, HW may still access the header
1514 * after writeback. Only unmap it when EOP is reached
1515 */
1516 if (!IXGBE_CB(skb)->head) {
1517 IXGBE_CB(skb)->delay_unmap = true;
1518 IXGBE_CB(skb)->dma = rx_buffer_info->dma;
1519 } else {
1520 skb = ixgbe_merge_active_tail(skb);
1521 dma_unmap_single(rx_ring->dev,
1522 rx_buffer_info->dma,
1523 rx_ring->rx_buf_len,
1524 DMA_FROM_DEVICE);
1525 }
1526 rx_buffer_info->dma = 0;
c267fc16
AD		 1527 } else {
1528 /* assume packet split since header is unmapped */
1529 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
9a799d71
AK		 1530 }
1531
1532 if (upper_len) {
b6ec895e
AD		 1533 dma_unmap_page(rx_ring->dev,
1534 rx_buffer_info->page_dma,
1535 PAGE_SIZE / 2,
1536 DMA_FROM_DEVICE);
9a799d71
AK		 1537 rx_buffer_info->page_dma = 0;
1538 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
e8e9f696
JP		 1539 rx_buffer_info->page,
1540 rx_buffer_info->page_offset,
1541 upper_len);
762f4c57 1542
c267fc16
AD		 1543 if ((page_count(rx_buffer_info->page) == 1) &&
1544 (page_to_nid(rx_buffer_info->page) == current_node))
762f4c57 1545 get_page(rx_buffer_info->page);
c267fc16
AD		 1546 else
1547 rx_buffer_info->page = NULL;
9a799d71
AK		 1548
1549 skb->len += upper_len;
1550 skb->data_len += upper_len;
98130646 1551 skb->truesize += PAGE_SIZE / 2;
9a799d71
AK		 1552 }
1553
4c1975d7
AD		 1554 ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb);
1555
9a799d71
AK		 1556 i++;
1557 if (i == rx_ring->count)
1558 i = 0;
9a799d71 1559
e4f74028 1560 next_rxd = IXGBE_RX_DESC(rx_ring, i);
9a799d71 1561 prefetch(next_rxd);
9a799d71 1562 cleaned_count++;
f8212f97 1563
f56e0cb1 1564 if ((!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) {
4c1975d7
AD		 1565 struct ixgbe_rx_buffer *next_buffer;
1566 u32 nextp;
1567
1568 if (IXGBE_CB(skb)->append_cnt) {
f56e0cb1
AD		 1569 nextp = le32_to_cpu(
1570 rx_desc->wb.upper.status_error);
4c1975d7
AD		 1571 nextp >>= IXGBE_RXDADV_NEXTP_SHIFT;
1572 } else {
1573 nextp = i;
1574 }
1575
f8212f97 1576 next_buffer = &rx_ring->rx_buffer_info[nextp];
f8212f97 1577
7d637bcc 1578 if (ring_is_ps_enabled(rx_ring)) {
f8212f97
AD		 1579 rx_buffer_info->skb = next_buffer->skb;
1580 rx_buffer_info->dma = next_buffer->dma;
1581 next_buffer->skb = skb;
1582 next_buffer->dma = 0;
1583 } else {
4c1975d7
AD		 1584 struct sk_buff *next_skb = next_buffer->skb;
1585 ixgbe_add_active_tail(skb, next_skb);
1586 IXGBE_CB(next_skb)->head = skb;
f8212f97 1587 }
5b7da515 1588 rx_ring->rx_stats.non_eop_descs++;
9a799d71
AK		 1589 goto next_desc;
1590 }
1591
4c1975d7
AD		 1592 dma_unmap_single(rx_ring->dev,
1593 IXGBE_CB(skb)->dma,
1594 rx_ring->rx_buf_len,
1595 DMA_FROM_DEVICE);
1596 IXGBE_CB(skb)->dma = 0;
1597 IXGBE_CB(skb)->delay_unmap = false;
c267fc16 1598
4c1975d7
AD		 1599 if (ixgbe_close_active_frag_list(skb) &&
1600 !IXGBE_CB(skb)->append_cnt) {
aa80175a 1601 /* if we got here without RSC the packet is invalid */
4c1975d7
AD		 1602 dev_kfree_skb_any(skb);
1603 goto next_desc;
c267fc16
AD		 1604 }
1605
1606 /* ERR_MASK will only have valid bits if EOP set */
f56e0cb1
AD		 1607 if (unlikely(ixgbe_test_staterr(rx_desc,
1608 IXGBE_RXDADV_ERR_FRAME_ERR_MASK))) {
ff886dfc 1609 dev_kfree_skb_any(skb);
9a799d71
AK		 1610 goto next_desc;
1611 }
1612
d2f4fbe2
AV		 1613 /* probably a little skewed due to removing CRC */
1614 total_rx_bytes += skb->len;
1615 total_rx_packets++;
1616
8a0da21b
AD		 1617 /* populate checksum, timestamp, VLAN, and protocol */
1618 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
1619
332d4a7d
YZ		 1620#ifdef IXGBE_FCOE
1621 /* if ddp, not passing to ULD unless for FCP_RSP or error */
ff886dfc 1622 if (ixgbe_rx_is_fcoe(adapter, rx_desc)) {
f56e0cb1 1623 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
63d635b2
AD		 1624 if (!ddp_bytes) {
1625 dev_kfree_skb_any(skb);
332d4a7d 1626 goto next_desc;
63d635b2 1627 }
3d8fd385 1628 }
332d4a7d 1629#endif /* IXGBE_FCOE */
8a0da21b 1630 ixgbe_rx_skb(q_vector, skb);
9a799d71 1631
4ff7fb12 1632 budget--;
9a799d71 1633next_desc:
4ff7fb12 1634 if (!budget)
c267fc16
AD		 1635 break;
1636
9a799d71
AK		 1637 /* return some buffers to hardware, one at a time is too slow */
1638 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
fc77dc3c 1639 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71
AK		 1640 cleaned_count = 0;
1641 }
1642
1643 /* use prefetched values */
1644 rx_desc = next_rxd;
177db6ff
MC		 1645 }
1646
9a799d71 1647 rx_ring->next_to_clean = i;
7d4987de 1648 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71
AK		 1649
1650 if (cleaned_count)
fc77dc3c 1651 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
9a799d71 1652
3d8fd385
YZ		 1653#ifdef IXGBE_FCOE
1654 /* include DDPed FCoE data */
1655 if (ddp_bytes > 0) {
1656 unsigned int mss;
1657
fc77dc3c 1658 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
3d8fd385
YZ		 1659 sizeof(struct fc_frame_header) -
1660 sizeof(struct fcoe_crc_eof);
1661 if (mss > 512)
1662 mss &= ~511;
1663 total_rx_bytes += ddp_bytes;
1664 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1665 }
1666#endif /* IXGBE_FCOE */
1667
c267fc16
AD		 1668 u64_stats_update_begin(&rx_ring->syncp);
1669 rx_ring->stats.packets += total_rx_packets;
1670 rx_ring->stats.bytes += total_rx_bytes;
1671 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 1672 q_vector->rx.total_packets += total_rx_packets;
1673 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12
AD		 1674
1675 return !!budget;
9a799d71
AK		 1676}
1677
9a799d71
AK		 1678/**
1679 * ixgbe_configure_msix - Configure MSI-X hardware
1680 * @adapter: board private structure
1681 *
1682 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1683 * interrupts.
1684 **/
1685static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1686{
021230d4 1687 struct ixgbe_q_vector *q_vector;
efe3d3c8 1688 int q_vectors, v_idx;
021230d4 1689 u32 mask;
9a799d71 1690
021230d4 1691 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
9a799d71 1692
8e34d1aa
AD		 1693 /* Populate MSIX to EITR Select */
1694 if (adapter->num_vfs > 32) {
1695 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
1696 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
1697 }
1698
4df10466
JB		 1699 /*
1700 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 1701 * corresponding register.
1702 */
1703 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
efe3d3c8 1704 struct ixgbe_ring *ring;
7a921c93 1705 q_vector = adapter->q_vector[v_idx];
021230d4 1706
efe3d3c8
AD		 1707 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
1708 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
1709
1710 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
1711 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
1712
d5bf4f67
ET		 1713 if (q_vector->tx.ring && !q_vector->rx.ring) {
1714 /* tx only vector */
1715 if (adapter->tx_itr_setting == 1)
1716 q_vector->itr = IXGBE_10K_ITR;
1717 else
1718 q_vector->itr = adapter->tx_itr_setting;
1719 } else {
1720 /* rx or rx/tx vector */
1721 if (adapter->rx_itr_setting == 1)
1722 q_vector->itr = IXGBE_20K_ITR;
1723 else
1724 q_vector->itr = adapter->rx_itr_setting;
1725 }
021230d4 1726
fe49f04a 1727 ixgbe_write_eitr(q_vector);
9a799d71
AK		 1728 }
1729
bd508178
AD		 1730 switch (adapter->hw.mac.type) {
1731 case ixgbe_mac_82598EB:
e8e26350 1732 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 1733 v_idx);
bd508178
AD		 1734 break;
1735 case ixgbe_mac_82599EB:
b93a2226 1736 case ixgbe_mac_X540:
e8e26350 1737 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 1738 break;
bd508178
AD		 1739 default:
1740 break;
1741 }
021230d4
AV		 1742 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1743
41fb9248 1744 /* set up to autoclear timer, and the vectors */
021230d4 1745 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 1746 mask &= ~(IXGBE_EIMS_OTHER |
1747 IXGBE_EIMS_MAILBOX |
1748 IXGBE_EIMS_LSC);
1749
021230d4 1750 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 1751}
1752
f494e8fa
AV		 1753enum latency_range {
1754 lowest_latency = 0,
1755 low_latency = 1,
1756 bulk_latency = 2,
1757 latency_invalid = 255
1758};
1759
1760/**
1761 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 1762 * @q_vector: structure containing interrupt and ring information
1763 * @ring_container: structure containing ring performance data
f494e8fa
AV		 1764 *
1765 * Stores a new ITR value based on packets and byte
1766 * counts during the last interrupt. The advantage of per interrupt
1767 * computation is faster updates and more accurate ITR for the current
1768 * traffic pattern. Constants in this function were computed
1769 * based on theoretical maximum wire speed and thresholds were set based
1770 * on testing data as well as attempting to minimize response time
1771 * while increasing bulk throughput.
1772 * this functionality is controlled by the InterruptThrottleRate module
1773 * parameter (see ixgbe_param.c)
1774 **/
bd198058
AD		 1775static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
1776 struct ixgbe_ring_container *ring_container)
f494e8fa 1777{
f494e8fa 1778 u64 bytes_perint;
bd198058
AD		 1779 struct ixgbe_adapter *adapter = q_vector->adapter;
1780 int bytes = ring_container->total_bytes;
1781 int packets = ring_container->total_packets;
1782 u32 timepassed_us;
1783 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 1784
1785 if (packets == 0)
bd198058 1786 return;
f494e8fa
AV		 1787
1788 /* simple throttlerate management
1789 * 0-20MB/s lowest (100000 ints/s)
1790 * 20-100MB/s low (20000 ints/s)
1791 * 100-1249MB/s bulk (8000 ints/s)
1792 */
1793 /* what was last interrupt timeslice? */
d5bf4f67 1794 timepassed_us = q_vector->itr >> 2;
f494e8fa
AV		 1795 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1796
1797 switch (itr_setting) {
1798 case lowest_latency:
1799 if (bytes_perint > adapter->eitr_low)
bd198058 1800 itr_setting = low_latency;
f494e8fa
AV		 1801 break;
1802 case low_latency:
1803 if (bytes_perint > adapter->eitr_high)
bd198058 1804 itr_setting = bulk_latency;
f494e8fa 1805 else if (bytes_perint <= adapter->eitr_low)
bd198058 1806 itr_setting = lowest_latency;
f494e8fa
AV		 1807 break;
1808 case bulk_latency:
1809 if (bytes_perint <= adapter->eitr_high)
bd198058 1810 itr_setting = low_latency;
f494e8fa
AV		 1811 break;
1812 }
1813
bd198058
AD		 1814 /* clear work counters since we have the values we need */
1815 ring_container->total_bytes = 0;
1816 ring_container->total_packets = 0;
1817
1818 /* write updated itr to ring container */
1819 ring_container->itr = itr_setting;
f494e8fa
AV		 1820}
1821
509ee935
JB		 1822/**
1823 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 1824 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 1825 *
1826 * This function is made to be called by ethtool and by the driver
1827 * when it needs to update EITR registers at runtime. Hardware
1828 * specific quirks/differences are taken care of here.
1829 */
fe49f04a 1830void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 1831{
fe49f04a 1832 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 1833 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 1834 int v_idx = q_vector->v_idx;
d5bf4f67 1835 u32 itr_reg = q_vector->itr;
fe49f04a 1836
bd508178
AD		 1837 switch (adapter->hw.mac.type) {
1838 case ixgbe_mac_82598EB:
509ee935
JB		 1839 /* must write high and low 16 bits to reset counter */
1840 itr_reg |= (itr_reg << 16);
bd508178
AD		 1841 break;
1842 case ixgbe_mac_82599EB:
b93a2226 1843 case ixgbe_mac_X540:
509ee935
JB		 1844 /*
1845 * set the WDIS bit to not clear the timer bits and cause an
1846 * immediate assertion of the interrupt
1847 */
1848 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 1849 break;
1850 default:
1851 break;
509ee935
JB		 1852 }
1853 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1854}
1855
bd198058 1856static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 1857{
d5bf4f67 1858 u32 new_itr = q_vector->itr;
bd198058 1859 u8 current_itr;
f494e8fa 1860
bd198058
AD		 1861 ixgbe_update_itr(q_vector, &q_vector->tx);
1862 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 1863
08c8833b 1864 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 1865
1866 switch (current_itr) {
1867 /* counts and packets in update_itr are dependent on these numbers */
1868 case lowest_latency:
d5bf4f67 1869 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 1870 break;
1871 case low_latency:
d5bf4f67 1872 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 1873 break;
1874 case bulk_latency:
d5bf4f67 1875 new_itr = IXGBE_8K_ITR;
f494e8fa 1876 break;
bd198058
AD		 1877 default:
1878 break;
f494e8fa
AV		 1879 }
1880
d5bf4f67 1881 if (new_itr != q_vector->itr) {
fe49f04a 1882 /* do an exponential smoothing */
d5bf4f67
ET		 1883 new_itr = (10 * new_itr * q_vector->itr) /
1884 ((9 * new_itr) + q_vector->itr);
509ee935 1885
bd198058 1886 /* save the algorithm value here */
d5bf4f67 1887 q_vector->itr = new_itr & IXGBE_MAX_EITR;
fe49f04a
AD		 1888
1889 ixgbe_write_eitr(q_vector);
f494e8fa 1890 }
f494e8fa
AV		 1891}
1892
119fc60a 1893/**
f0f9778d
AD		 1894 * ixgbe_check_overtemp_subtask - check for over tempurature
1895 * @adapter: pointer to adapter
119fc60a 1896 **/
f0f9778d 1897static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 1898{
119fc60a
MC		 1899 struct ixgbe_hw *hw = &adapter->hw;
1900 u32 eicr = adapter->interrupt_event;
1901
f0f9778d 1902 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 1903 return;
1904
f0f9778d
AD		 1905 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1906 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1907 return;
1908
1909 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1910
7ca647bd 1911 switch (hw->device_id) {
f0f9778d
AD		 1912 case IXGBE_DEV_ID_82599_T3_LOM:
1913 /*
1914 * Since the warning interrupt is for both ports
1915 * we don't have to check if:
1916 * - This interrupt wasn't for our port.
1917 * - We may have missed the interrupt so always have to
1918 * check if we got a LSC
1919 */
1920 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1921 !(eicr & IXGBE_EICR_LSC))
1922 return;
1923
1924 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1925 u32 autoneg;
1926 bool link_up = false;
7ca647bd 1927
7ca647bd
JP		 1928 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1929
f0f9778d
AD		 1930 if (link_up)
1931 return;
1932 }
1933
1934 /* Check if this is not due to overtemp */
1935 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1936 return;
1937
1938 break;
7ca647bd
JP		 1939 default:
1940 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 1941 return;
7ca647bd 1942 break;
119fc60a 1943 }
7ca647bd
JP		 1944 e_crit(drv,
1945 "Network adapter has been stopped because it has over heated. "
1946 "Restart the computer. If the problem persists, "
1947 "power off the system and replace the adapter\n");
f0f9778d
AD		 1948
1949 adapter->interrupt_event = 0;
119fc60a
MC		 1950}
1951
0befdb3e
JB		 1952static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1953{
1954 struct ixgbe_hw *hw = &adapter->hw;
1955
1956 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1957 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 1958 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 1959 /* write to clear the interrupt */
1960 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1961 }
1962}
cf8280ee 1963
4f51bf70
JK		 1964static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
1965{
1966 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1967 return;
1968
1969 switch (adapter->hw.mac.type) {
1970 case ixgbe_mac_82599EB:
1971 /*
1972 * Need to check link state so complete overtemp check
1973 * on service task
1974 */
1975 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
1976 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
1977 adapter->interrupt_event = eicr;
1978 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1979 ixgbe_service_event_schedule(adapter);
1980 return;
1981 }
1982 return;
1983 case ixgbe_mac_X540:
1984 if (!(eicr & IXGBE_EICR_TS))
1985 return;
1986 break;
1987 default:
1988 return;
1989 }
1990
1991 e_crit(drv,
1992 "Network adapter has been stopped because it has over heated. "
1993 "Restart the computer. If the problem persists, "
1994 "power off the system and replace the adapter\n");
1995}
1996
e8e26350
PW		 1997static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1998{
1999 struct ixgbe_hw *hw = &adapter->hw;
2000
73c4b7cd
AD		 2001 if (eicr & IXGBE_EICR_GPI_SDP2) {
2002 /* Clear the interrupt */
2003 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2004 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2005 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2006 ixgbe_service_event_schedule(adapter);
2007 }
73c4b7cd
AD		 2008 }
2009
e8e26350
PW		 2010 if (eicr & IXGBE_EICR_GPI_SDP1) {
2011 /* Clear the interrupt */
2012 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2013 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2014 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2015 ixgbe_service_event_schedule(adapter);
2016 }
e8e26350
PW		 2017 }
2018}
2019
cf8280ee
JB		 2020static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2021{
2022 struct ixgbe_hw *hw = &adapter->hw;
2023
2024 adapter->lsc_int++;
2025 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2026 adapter->link_check_timeout = jiffies;
2027 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2028 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2029 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2030 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2031 }
2032}
2033
fe49f04a
AD		 2034static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2035 u64 qmask)
2036{
2037 u32 mask;
bd508178 2038 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2039
bd508178
AD		 2040 switch (hw->mac.type) {
2041 case ixgbe_mac_82598EB:
fe49f04a 2042 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2043 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2044 break;
2045 case ixgbe_mac_82599EB:
b93a2226 2046 case ixgbe_mac_X540:
fe49f04a 2047 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2048 if (mask)
2049 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2050 mask = (qmask >> 32);
bd508178
AD		 2051 if (mask)
2052 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2053 break;
2054 default:
2055 break;
fe49f04a
AD		 2056 }
2057 /* skip the flush */
2058}
2059
2060static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2061 u64 qmask)
fe49f04a
AD		 2062{
2063 u32 mask;
bd508178 2064 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2065
bd508178
AD		 2066 switch (hw->mac.type) {
2067 case ixgbe_mac_82598EB:
fe49f04a 2068 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2069 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2070 break;
2071 case ixgbe_mac_82599EB:
b93a2226 2072 case ixgbe_mac_X540:
fe49f04a 2073 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2074 if (mask)
2075 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2076 mask = (qmask >> 32);
bd508178
AD		 2077 if (mask)
2078 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2079 break;
2080 default:
2081 break;
fe49f04a
AD		 2082 }
2083 /* skip the flush */
2084}
2085
021230d4 2086/**
2c4af694
AD		 2087 * ixgbe_irq_enable - Enable default interrupt generation settings
2088 * @adapter: board private structure
021230d4 2089 **/
2c4af694
AD		 2090static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2091 bool flush)
9a799d71 2092{
2c4af694 2093 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2094
2c4af694
AD		 2095 /* don't reenable LSC while waiting for link */
2096 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2097 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2098
2c4af694 2099 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2100 switch (adapter->hw.mac.type) {
2101 case ixgbe_mac_82599EB:
2102 mask |= IXGBE_EIMS_GPI_SDP0;
2103 break;
2104 case ixgbe_mac_X540:
2105 mask |= IXGBE_EIMS_TS;
2106 break;
2107 default:
2108 break;
2109 }
2c4af694
AD		 2110 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2111 mask |= IXGBE_EIMS_GPI_SDP1;
2112 switch (adapter->hw.mac.type) {
2113 case ixgbe_mac_82599EB:
2c4af694
AD		 2114 mask |= IXGBE_EIMS_GPI_SDP1;
2115 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2116 case ixgbe_mac_X540:
2117 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2118 mask |= IXGBE_EIMS_MAILBOX;
2119 break;
2120 default:
2121 break;
9a799d71 2122 }
2c4af694
AD		 2123 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2124 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2125 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2126
2c4af694
AD		 2127 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2128 if (queues)
2129 ixgbe_irq_enable_queues(adapter, ~0);
2130 if (flush)
2131 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2132}
2133
2c4af694 2134static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2135{
a65151ba 2136 struct ixgbe_adapter *adapter = data;
9a799d71 2137 struct ixgbe_hw *hw = &adapter->hw;
54037505 2138 u32 eicr;
91281fd3 2139
54037505
DS		 2140 /*
2141 * Workaround for Silicon errata. Use clear-by-write instead
2142 * of clear-by-read. Reading with EICS will return the
2143 * interrupt causes without clearing, which later be done
2144 * with the write to EICR.
2145 */
2146 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
2147 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2148
cf8280ee
JB		 2149 if (eicr & IXGBE_EICR_LSC)
2150 ixgbe_check_lsc(adapter);
f0848276 2151
1cdd1ec8
GR		 2152 if (eicr & IXGBE_EICR_MAILBOX)
2153 ixgbe_msg_task(adapter);
efe3d3c8 2154
bd508178
AD		 2155 switch (hw->mac.type) {
2156 case ixgbe_mac_82599EB:
b93a2226 2157 case ixgbe_mac_X540:
2c4af694
AD		 2158 if (eicr & IXGBE_EICR_ECC)
2159 e_info(link, "Received unrecoverable ECC Err, please "
2160 "reboot\n");
c4cf55e5
PWJ		 2161 /* Handle Flow Director Full threshold interrupt */
2162 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2163 int reinit_count = 0;
c4cf55e5 2164 int i;
c4cf55e5 2165 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2166 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2167 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2168 &ring->state))
2169 reinit_count++;
2170 }
2171 if (reinit_count) {
2172 /* no more flow director interrupts until after init */
2173 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2174 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2175 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2176 }
2177 }
f0f9778d 2178 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2179 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2180 break;
2181 default:
2182 break;
c4cf55e5 2183 }
f0848276 2184
bd508178 2185 ixgbe_check_fan_failure(adapter, eicr);
efe3d3c8 2186
7086400d 2187 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2188 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2189 ixgbe_irq_enable(adapter, false, false);
f0848276 2190
9a799d71 2191 return IRQ_HANDLED;
f0848276 2192}
91281fd3 2193
4ff7fb12 2194static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2195{
021230d4 2196 struct ixgbe_q_vector *q_vector = data;
91281fd3 2197
9b471446 2198 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2199
4ff7fb12
AD		 2200 if (q_vector->rx.ring || q_vector->tx.ring)
2201 napi_schedule(&q_vector->napi);
91281fd3 2202
9a799d71 2203 return IRQ_HANDLED;
91281fd3
AD		 2204}
2205
021230d4 2206static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2207 int r_idx)
021230d4 2208{
7a921c93 2209 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2210 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
7a921c93 2211
2274543f 2212 rx_ring->q_vector = q_vector;
efe3d3c8
AD		 2213 rx_ring->next = q_vector->rx.ring;
2214 q_vector->rx.ring = rx_ring;
2215 q_vector->rx.count++;
021230d4
AV		 2216}
2217
2218static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
e8e9f696 2219 int t_idx)
021230d4 2220{
7a921c93 2221 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2274543f 2222 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
7a921c93 2223
2274543f 2224 tx_ring->q_vector = q_vector;
efe3d3c8
AD		 2225 tx_ring->next = q_vector->tx.ring;
2226 q_vector->tx.ring = tx_ring;
2227 q_vector->tx.count++;
bd198058 2228 q_vector->tx.work_limit = a->tx_work_limit;
021230d4
AV		 2229}
2230
9a799d71 2231/**
021230d4
AV		 2232 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2233 * @adapter: board private structure to initialize
9a799d71 2234 *
021230d4
AV		 2235 * This function maps descriptor rings to the queue-specific vectors
2236 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2237 * one vector per ring/queue, but on a constrained vector budget, we
2238 * group the rings as "efficiently" as possible. You would add new
2239 * mapping configurations in here.
9a799d71 2240 **/
4cc6df29 2241static void ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
021230d4 2242{
4cc6df29
AD		 2243 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2244 int rxr_remaining = adapter->num_rx_queues, rxr_idx = 0;
2245 int txr_remaining = adapter->num_tx_queues, txr_idx = 0;
021230d4 2246 int v_start = 0;
021230d4 2247
4cc6df29 2248 /* only one q_vector if MSI-X is disabled. */
021230d4 2249 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
4cc6df29 2250 q_vectors = 1;
d0759ebb 2251
021230d4 2252 /*
4cc6df29
AD		 2253 * If we don't have enough vectors for a 1-to-1 mapping, we'll have to
2254 * group them so there are multiple queues per vector.
2255 *
2256 * Re-adjusting *qpv takes care of the remainder.
021230d4 2257 */
4cc6df29
AD		 2258 for (; v_start < q_vectors && rxr_remaining; v_start++) {
2259 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_start);
2260 for (; rqpv; rqpv--, rxr_idx++, rxr_remaining--)
021230d4 2261 map_vector_to_rxq(adapter, v_start, rxr_idx);
021230d4 2262 }
9a799d71 2263
021230d4 2264 /*
4cc6df29
AD		 2265 * If there are not enough q_vectors for each ring to have it's own
2266 * vector then we must pair up Rx/Tx on a each vector
021230d4 2267 */
4cc6df29
AD		 2268 if ((v_start + txr_remaining) > q_vectors)
2269 v_start = 0;
2270
2271 for (; v_start < q_vectors && txr_remaining; v_start++) {
2272 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_start);
2273 for (; tqpv; tqpv--, txr_idx++, txr_remaining--)
2274 map_vector_to_txq(adapter, v_start, txr_idx);
9a799d71 2275 }
021230d4
AV		 2276}
2277
2278/**
2279 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2280 * @adapter: board private structure
2281 *
2282 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2283 * interrupts from the kernel.
2284 **/
2285static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2286{
2287 struct net_device *netdev = adapter->netdev;
207867f5
AD		 2288 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2289 int vector, err;
e8e9f696 2290 int ri = 0, ti = 0;
021230d4 2291
021230d4 2292 for (vector = 0; vector < q_vectors; vector++) {
d0759ebb 2293 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2294 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2295
4ff7fb12 2296 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2297 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2298 "%s-%s-%d", netdev->name, "TxRx", ri++);
2299 ti++;
2300 } else if (q_vector->rx.ring) {
9fe93afd 2301 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2302 "%s-%s-%d", netdev->name, "rx", ri++);
2303 } else if (q_vector->tx.ring) {
9fe93afd 2304 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2305 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2306 } else {
2307 /* skip this unused q_vector */
2308 continue;
32aa77a4 2309 }
207867f5
AD		 2310 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2311 q_vector->name, q_vector);
9a799d71 2312 if (err) {
396e799c 2313 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2314 "Error: %d\n", err);
021230d4 2315 goto free_queue_irqs;
9a799d71 2316 }
207867f5
AD		 2317 /* If Flow Director is enabled, set interrupt affinity */
2318 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2319 /* assign the mask for this irq */
2320 irq_set_affinity_hint(entry->vector,
2321 q_vector->affinity_mask);
2322 }
9a799d71
AK		 2323 }
2324
021230d4 2325 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2326 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2327 if (err) {
396e799c 2328 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
021230d4 2329 goto free_queue_irqs;
9a799d71
AK		 2330 }
2331
9a799d71
AK		 2332 return 0;
2333
021230d4 2334free_queue_irqs:
207867f5
AD		 2335 while (vector) {
2336 vector--;
2337 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2338 NULL);
2339 free_irq(adapter->msix_entries[vector].vector,
2340 adapter->q_vector[vector]);
2341 }
021230d4
AV		 2342 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2343 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2344 kfree(adapter->msix_entries);
2345 adapter->msix_entries = NULL;
9a799d71
AK		 2346 return err;
2347}
2348
2349/**
021230d4 2350 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2351 * @irq: interrupt number
2352 * @data: pointer to a network interface device structure
9a799d71
AK		 2353 **/
2354static irqreturn_t ixgbe_intr(int irq, void *data)
2355{
a65151ba 2356 struct ixgbe_adapter *adapter = data;
9a799d71 2357 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2358 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2359 u32 eicr;
2360
54037505 2361 /*
6af3b9eb 2362 * Workaround for silicon errata on 82598. Mask the interrupts
54037505
DS		 2363 * before the read of EICR.
2364 */
2365 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2366
021230d4 2367 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2368 * therefore no explicit interrupt disable is necessary */
021230d4 2369 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2370 if (!eicr) {
6af3b9eb
ET		 2371 /*
2372 * shared interrupt alert!
f47cf66e 2373 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2374 * have disabled interrupts due to EIAM
2375 * finish the workaround of silicon errata on 82598. Unmask
2376 * the interrupt that we masked before the EICR read.
2377 */
2378 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2379 ixgbe_irq_enable(adapter, true, true);
9a799d71 2380 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2381 }
9a799d71 2382
cf8280ee
JB		 2383 if (eicr & IXGBE_EICR_LSC)
2384 ixgbe_check_lsc(adapter);
021230d4 2385
bd508178
AD		 2386 switch (hw->mac.type) {
2387 case ixgbe_mac_82599EB:
e8e26350 2388 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2389 /* Fall through */
2390 case ixgbe_mac_X540:
2391 if (eicr & IXGBE_EICR_ECC)
2392 e_info(link, "Received unrecoverable ECC err, please "
2393 "reboot\n");
4f51bf70 2394 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2395 break;
2396 default:
2397 break;
2398 }
e8e26350 2399
0befdb3e
JB		 2400 ixgbe_check_fan_failure(adapter, eicr);
2401
7a921c93 2402 if (napi_schedule_prep(&(q_vector->napi))) {
021230d4 2403 /* would disable interrupts here but EIAM disabled it */
7a921c93 2404 __napi_schedule(&(q_vector->napi));
9a799d71
AK		 2405 }
2406
6af3b9eb
ET		 2407 /*
2408 * re-enable link(maybe) and non-queue interrupts, no flush.
2409 * ixgbe_poll will re-enable the queue interrupts
2410 */
2411
2412 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2413 ixgbe_irq_enable(adapter, false, false);
2414
9a799d71
AK		 2415 return IRQ_HANDLED;
2416}
2417
021230d4
AV		 2418static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2419{
efe3d3c8
AD		 2420 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2421 int i;
2422
2423 /* legacy and MSI only use one vector */
2424 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2425 q_vectors = 1;
2426
2427 for (i = 0; i < adapter->num_rx_queues; i++) {
2428 adapter->rx_ring[i]->q_vector = NULL;
2429 adapter->rx_ring[i]->next = NULL;
2430 }
2431 for (i = 0; i < adapter->num_tx_queues; i++) {
2432 adapter->tx_ring[i]->q_vector = NULL;
2433 adapter->tx_ring[i]->next = NULL;
2434 }
021230d4
AV		 2435
2436 for (i = 0; i < q_vectors; i++) {
7a921c93 2437 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
efe3d3c8
AD		 2438 memset(&q_vector->rx, 0, sizeof(struct ixgbe_ring_container));
2439 memset(&q_vector->tx, 0, sizeof(struct ixgbe_ring_container));
021230d4
AV		 2440 }
2441}
2442
9a799d71
AK		 2443/**
2444 * ixgbe_request_irq - initialize interrupts
2445 * @adapter: board private structure
2446 *
2447 * Attempts to configure interrupts using the best available
2448 * capabilities of the hardware and kernel.
2449 **/
021230d4 2450static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2451{
2452 struct net_device *netdev = adapter->netdev;
021230d4 2453 int err;
9a799d71 2454
4cc6df29
AD		 2455 /* map all of the rings to the q_vectors */
2456 ixgbe_map_rings_to_vectors(adapter);
2457
2458 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2459 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2460 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2461 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2462 netdev->name, adapter);
4cc6df29 2463 else
a0607fd3 2464 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2465 netdev->name, adapter);
9a799d71 2466
4cc6df29 2467 if (err) {
396e799c 2468 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2469
4cc6df29
AD		 2470 /* place q_vectors and rings back into a known good state */
2471 ixgbe_reset_q_vectors(adapter);
2472 }
2473
9a799d71
AK		 2474 return err;
2475}
2476
2477static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2478{
9a799d71 2479 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
021230d4 2480 int i, q_vectors;
9a799d71 2481
021230d4 2482 q_vectors = adapter->num_msix_vectors;
021230d4 2483 i = q_vectors - 1;
a65151ba 2484 free_irq(adapter->msix_entries[i].vector, adapter);
021230d4 2485 i--;
4cc6df29 2486
021230d4 2487 for (; i >= 0; i--) {
894ff7cf 2488 /* free only the irqs that were actually requested */
4ff7fb12
AD		 2489 if (!adapter->q_vector[i]->rx.ring &&
2490 !adapter->q_vector[i]->tx.ring)
894ff7cf
AD		 2491 continue;
2492
207867f5
AD		 2493 /* clear the affinity_mask in the IRQ descriptor */
2494 irq_set_affinity_hint(adapter->msix_entries[i].vector,
2495 NULL);
2496
021230d4 2497 free_irq(adapter->msix_entries[i].vector,
e8e9f696 2498 adapter->q_vector[i]);
021230d4 2499 }
021230d4 2500 } else {
a65151ba 2501 free_irq(adapter->pdev->irq, adapter);
9a799d71 2502 }
207867f5
AD		 2503
2504 /* clear q_vector state information */
2505 ixgbe_reset_q_vectors(adapter);
9a799d71
AK		 2506}
2507
22d5a71b
JB		 2508/**
2509 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2510 * @adapter: board private structure
2511 **/
2512static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2513{
bd508178
AD		 2514 switch (adapter->hw.mac.type) {
2515 case ixgbe_mac_82598EB:
835462fc 2516 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2517 break;
2518 case ixgbe_mac_82599EB:
b93a2226 2519 case ixgbe_mac_X540:
835462fc
NS		 2520 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2521 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2522 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2523 break;
2524 default:
2525 break;
22d5a71b
JB		 2526 }
2527 IXGBE_WRITE_FLUSH(&adapter->hw);
2528 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2529 int i;
2530 for (i = 0; i < adapter->num_msix_vectors; i++)
2531 synchronize_irq(adapter->msix_entries[i].vector);
2532 } else {
2533 synchronize_irq(adapter->pdev->irq);
2534 }
2535}
2536
9a799d71
AK		 2537/**
2538 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2539 *
2540 **/
2541static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2542{
d5bf4f67 2543 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2544
d5bf4f67
ET		 2545 /* rx/tx vector */
2546 if (adapter->rx_itr_setting == 1)
2547 q_vector->itr = IXGBE_20K_ITR;
2548 else
2549 q_vector->itr = adapter->rx_itr_setting;
2550
2551 ixgbe_write_eitr(q_vector);
9a799d71 2552
e8e26350
PW		 2553 ixgbe_set_ivar(adapter, 0, 0, 0);
2554 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2555
396e799c 2556 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2557}
2558
43e69bf0
AD		 2559/**
2560 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2561 * @adapter: board private structure
2562 * @ring: structure containing ring specific data
2563 *
2564 * Configure the Tx descriptor ring after a reset.
2565 **/
84418e3b
AD		 2566void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2567 struct ixgbe_ring *ring)
43e69bf0
AD		 2568{
2569 struct ixgbe_hw *hw = &adapter->hw;
2570 u64 tdba = ring->dma;
2f1860b8 2571 int wait_loop = 10;
b88c6de2 2572 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2573 u8 reg_idx = ring->reg_idx;
43e69bf0 2574
2f1860b8 2575 /* disable queue to avoid issues while updating state */
b88c6de2 2576 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2577 IXGBE_WRITE_FLUSH(hw);
2578
43e69bf0 2579 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2580 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2581 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2582 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2583 ring->count * sizeof(union ixgbe_adv_tx_desc));
2584 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2585 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2586 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2587
b88c6de2
AD		 2588 /*
2589 * set WTHRESH to encourage burst writeback, it should not be set
2590 * higher than 1 when ITR is 0 as it could cause false TX hangs
2591 *
2592 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2593 * to or less than the number of on chip descriptors, which is
2594 * currently 40.
2595 */
2596 if (!adapter->tx_itr_setting || !adapter->rx_itr_setting)
2597 txdctl |= (1 << 16); /* WTHRESH = 1 */
2598 else
2599 txdctl |= (8 << 16); /* WTHRESH = 8 */
2600
2601 /* PTHRESH=32 is needed to avoid a Tx hang with DFP enabled. */
2602 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2603 32; /* PTHRESH = 32 */
2f1860b8
AD		 2604
2605 /* reinitialize flowdirector state */
ee9e0f0b
AD		 2606 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2607 adapter->atr_sample_rate) {
2608 ring->atr_sample_rate = adapter->atr_sample_rate;
2609 ring->atr_count = 0;
2610 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2611 } else {
2612 ring->atr_sample_rate = 0;
2613 }
2f1860b8 2614
c84d324c
JF		 2615 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2616
2f1860b8 2617 /* enable queue */
2f1860b8
AD		 2618 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2619
2620 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2621 if (hw->mac.type == ixgbe_mac_82598EB &&
2622 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2623 return;
2624
2625 /* poll to verify queue is enabled */
2626 do {
032b4325 2627 usleep_range(1000, 2000);
2f1860b8
AD		 2628 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2629 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2630 if (!wait_loop)
2631 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 2632}
2633
120ff942
AD		 2634static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2635{
2636 struct ixgbe_hw *hw = &adapter->hw;
2637 u32 rttdcs;
72a32f1f 2638 u32 reg;
8b1c0b24 2639 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 2640
2641 if (hw->mac.type == ixgbe_mac_82598EB)
2642 return;
2643
2644 /* disable the arbiter while setting MTQC */
2645 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2646 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2647 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2648
2649 /* set transmit pool layout */
8b1c0b24 2650 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
120ff942
AD		 2651 case (IXGBE_FLAG_SRIOV_ENABLED):
2652 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2653 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2654 break;
8b1c0b24
JF		 2655 default:
2656 if (!tcs)
2657 reg = IXGBE_MTQC_64Q_1PB;
2658 else if (tcs <= 4)
2659 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2660 else
2661 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
120ff942 2662
8b1c0b24 2663 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
120ff942 2664
8b1c0b24
JF		 2665 /* Enable Security TX Buffer IFG for multiple pb */
2666 if (tcs) {
2667 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2668 reg |= IXGBE_SECTX_DCB;
2669 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2670 }
120ff942
AD		 2671 break;
2672 }
2673
2674 /* re-enable the arbiter */
2675 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2676 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2677}
2678
9a799d71 2679/**
3a581073 2680 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 2681 * @adapter: board private structure
2682 *
2683 * Configure the Tx unit of the MAC after a reset.
2684 **/
2685static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2686{
2f1860b8
AD		 2687 struct ixgbe_hw *hw = &adapter->hw;
2688 u32 dmatxctl;
43e69bf0 2689 u32 i;
9a799d71 2690
2f1860b8
AD		 2691 ixgbe_setup_mtqc(adapter);
2692
2693 if (hw->mac.type != ixgbe_mac_82598EB) {
2694 /* DMATXCTL.EN must be before Tx queues are enabled */
2695 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2696 dmatxctl |= IXGBE_DMATXCTL_TE;
2697 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2698 }
2699
9a799d71 2700 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 2701 for (i = 0; i < adapter->num_tx_queues; i++)
2702 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 2703}
2704
e8e26350 2705#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 2706
a6616b42 2707static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 2708 struct ixgbe_ring *rx_ring)
cc41ac7c 2709{
cc41ac7c 2710 u32 srrctl;
bf29ee6c 2711 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 2712
bd508178
AD		 2713 switch (adapter->hw.mac.type) {
2714 case ixgbe_mac_82598EB: {
2715 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2716 const int mask = feature[RING_F_RSS].mask;
bf29ee6c 2717 reg_idx = reg_idx & mask;
cc41ac7c 2718 }
bd508178
AD		 2719 break;
2720 case ixgbe_mac_82599EB:
b93a2226 2721 case ixgbe_mac_X540:
bd508178
AD		 2722 default:
2723 break;
2724 }
2725
bf29ee6c 2726 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
cc41ac7c
JB		 2727
2728 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2729 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
9e10e045
AD		 2730 if (adapter->num_vfs)
2731 srrctl |= IXGBE_SRRCTL_DROP_EN;
cc41ac7c 2732
afafd5b0
AD		 2733 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2734 IXGBE_SRRCTL_BSIZEHDR_MASK;
2735
7d637bcc 2736 if (ring_is_ps_enabled(rx_ring)) {
afafd5b0
AD		 2737#if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2738 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2739#else
2740 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2741#endif
cc41ac7c 2742 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
cc41ac7c 2743 } else {
afafd5b0
AD		 2744 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2745 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
cc41ac7c 2746 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
cc41ac7c 2747 }
e8e26350 2748
bf29ee6c 2749 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 2750}
9a799d71 2751
05abb126 2752static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 2753{
05abb126
AD		 2754 struct ixgbe_hw *hw = &adapter->hw;
2755 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 2756 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2757 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 2758 u32 mrqc = 0, reta = 0;
2759 u32 rxcsum;
2760 int i, j;
8b1c0b24 2761 u8 tcs = netdev_get_num_tc(adapter->netdev);
86b4db3b
JF		 2762 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2763
2764 if (tcs)
2765 maxq = min(maxq, adapter->num_tx_queues / tcs);
0cefafad 2766
05abb126
AD		 2767 /* Fill out hash function seeds */
2768 for (i = 0; i < 10; i++)
2769 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2770
2771 /* Fill out redirection table */
2772 for (i = 0, j = 0; i < 128; i++, j++) {
86b4db3b 2773 if (j == maxq)
05abb126
AD		 2774 j = 0;
2775 /* reta = 4-byte sliding window of
2776 * 0x00..(indices-1)(indices-1)00..etc. */
2777 reta = (reta << 8) | (j * 0x11);
2778 if ((i & 3) == 3)
2779 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2780 }
0cefafad 2781
05abb126
AD		 2782 /* Disable indicating checksum in descriptor, enables RSS hash */
2783 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2784 rxcsum |= IXGBE_RXCSUM_PCSD;
2785 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2786
8b1c0b24
JF		 2787 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2788 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
0cefafad 2789 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24
JF		 2790 } else {
2791 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2792 | IXGBE_FLAG_SRIOV_ENABLED);
2793
2794 switch (mask) {
2795 case (IXGBE_FLAG_RSS_ENABLED):
2796 if (!tcs)
2797 mrqc = IXGBE_MRQC_RSSEN;
2798 else if (tcs <= 4)
2799 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2800 else
2801 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2802 break;
2803 case (IXGBE_FLAG_SRIOV_ENABLED):
2804 mrqc = IXGBE_MRQC_VMDQEN;
2805 break;
2806 default:
2807 break;
2808 }
0cefafad
JB		 2809 }
2810
05abb126
AD		 2811 /* Perform hash on these packet types */
2812 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2813 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2814 | IXGBE_MRQC_RSS_FIELD_IPV6
2815 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2816
2817 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 2818}
2819
bb5a9ad2
NS		 2820/**
2821 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2822 * @adapter: address of board private structure
2823 * @index: index of ring to set
bb5a9ad2 2824 **/
082757af 2825static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 2826 struct ixgbe_ring *ring)
bb5a9ad2 2827{
bb5a9ad2 2828 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 2829 u32 rscctrl;
edd2ea55 2830 int rx_buf_len;
bf29ee6c 2831 u8 reg_idx = ring->reg_idx;
7367096a 2832
7d637bcc 2833 if (!ring_is_rsc_enabled(ring))
7367096a 2834 return;
bb5a9ad2 2835
7367096a
AD		 2836 rx_buf_len = ring->rx_buf_len;
2837 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 2838 rscctrl |= IXGBE_RSCCTL_RSCEN;
2839 /*
2840 * we must limit the number of descriptors so that the
2841 * total size of max desc * buf_len is not greater
642c680e 2842 * than 65536
bb5a9ad2 2843 */
7d637bcc 2844 if (ring_is_ps_enabled(ring)) {
642c680e 2845#if (PAGE_SIZE < 8192)
bb5a9ad2 2846 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2847#elif (PAGE_SIZE < 16384)
bb5a9ad2 2848 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
642c680e 2849#elif (PAGE_SIZE < 32768)
bb5a9ad2
NS		 2850 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2851#else
2852 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2853#endif
2854 } else {
642c680e 2855 if (rx_buf_len <= IXGBE_RXBUFFER_4K)
bb5a9ad2 2856 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
642c680e 2857 else if (rx_buf_len <= IXGBE_RXBUFFER_8K)
bb5a9ad2
NS		 2858 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2859 else
2860 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2861 }
7367096a 2862 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 2863}
2864
9e10e045
AD		 2865/**
2866 * ixgbe_set_uta - Set unicast filter table address
2867 * @adapter: board private structure
2868 *
2869 * The unicast table address is a register array of 32-bit registers.
2870 * The table is meant to be used in a way similar to how the MTA is used
2871 * however due to certain limitations in the hardware it is necessary to
2872 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2873 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2874 **/
2875static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2876{
2877 struct ixgbe_hw *hw = &adapter->hw;
2878 int i;
2879
2880 /* The UTA table only exists on 82599 hardware and newer */
2881 if (hw->mac.type < ixgbe_mac_82599EB)
2882 return;
2883
2884 /* we only need to do this if VMDq is enabled */
2885 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2886 return;
2887
2888 for (i = 0; i < 128; i++)
2889 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2890}
2891
2892#define IXGBE_MAX_RX_DESC_POLL 10
2893static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2894 struct ixgbe_ring *ring)
2895{
2896 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 2897 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2898 u32 rxdctl;
bf29ee6c 2899 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 2900
2901 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2902 if (hw->mac.type == ixgbe_mac_82598EB &&
2903 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2904 return;
2905
2906 do {
032b4325 2907 usleep_range(1000, 2000);
9e10e045
AD		 2908 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2909 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2910
2911 if (!wait_loop) {
2912 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2913 "the polling period\n", reg_idx);
2914 }
2915}
2916
2d39d576
YZ		 2917void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
2918 struct ixgbe_ring *ring)
2919{
2920 struct ixgbe_hw *hw = &adapter->hw;
2921 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2922 u32 rxdctl;
2923 u8 reg_idx = ring->reg_idx;
2924
2925 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2926 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
2927
2928 /* write value back with RXDCTL.ENABLE bit cleared */
2929 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2930
2931 if (hw->mac.type == ixgbe_mac_82598EB &&
2932 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2933 return;
2934
2935 /* the hardware may take up to 100us to really disable the rx queue */
2936 do {
2937 udelay(10);
2938 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2939 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
2940
2941 if (!wait_loop) {
2942 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
2943 "the polling period\n", reg_idx);
2944 }
2945}
2946
84418e3b
AD		 2947void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2948 struct ixgbe_ring *ring)
acd37177
AD		 2949{
2950 struct ixgbe_hw *hw = &adapter->hw;
2951 u64 rdba = ring->dma;
9e10e045 2952 u32 rxdctl;
bf29ee6c 2953 u8 reg_idx = ring->reg_idx;
acd37177 2954
9e10e045
AD		 2955 /* disable queue to avoid issues while updating state */
2956 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 2957 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 2958
acd37177
AD		 2959 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2960 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2961 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2962 ring->count * sizeof(union ixgbe_adv_rx_desc));
2963 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2964 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 2965 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 2966
2967 ixgbe_configure_srrctl(adapter, ring);
2968 ixgbe_configure_rscctl(adapter, ring);
2969
e9f98072
GR		 2970 /* If operating in IOV mode set RLPML for X540 */
2971 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
2972 hw->mac.type == ixgbe_mac_X540) {
2973 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
2974 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
2975 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
2976 }
2977
9e10e045
AD		 2978 if (hw->mac.type == ixgbe_mac_82598EB) {
2979 /*
2980 * enable cache line friendly hardware writes:
2981 * PTHRESH=32 descriptors (half the internal cache),
2982 * this also removes ugly rx_no_buffer_count increment
2983 * HTHRESH=4 descriptors (to minimize latency on fetch)
2984 * WTHRESH=8 burst writeback up to two cache lines
2985 */
2986 rxdctl &= ~0x3FFFFF;
2987 rxdctl |= 0x080420;
2988 }
2989
2990 /* enable receive descriptor ring */
2991 rxdctl |= IXGBE_RXDCTL_ENABLE;
2992 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2993
2994 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 2995 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 2996}
2997
48654521
AD		 2998static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2999{
3000 struct ixgbe_hw *hw = &adapter->hw;
3001 int p;
3002
3003 /* PSRTYPE must be initialized in non 82598 adapters */
3004 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3005 IXGBE_PSRTYPE_UDPHDR |
3006 IXGBE_PSRTYPE_IPV4HDR |
48654521 3007 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3008 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3009
3010 if (hw->mac.type == ixgbe_mac_82598EB)
3011 return;
3012
3013 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3014 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3015
3016 for (p = 0; p < adapter->num_rx_pools; p++)
3017 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3018 psrtype);
3019}
3020
f5b4a52e
AD		 3021static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3022{
3023 struct ixgbe_hw *hw = &adapter->hw;
3024 u32 gcr_ext;
3025 u32 vt_reg_bits;
3026 u32 reg_offset, vf_shift;
3027 u32 vmdctl;
de4c7f65 3028 int i;
f5b4a52e
AD		 3029
3030 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3031 return;
3032
3033 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3034 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3035 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3036 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3037
3038 vf_shift = adapter->num_vfs % 32;
4cd6923d 3039 reg_offset = (adapter->num_vfs >= 32) ? 1 : 0;
f5b4a52e
AD		 3040
3041 /* Enable only the PF's pool for Tx/Rx */
3042 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3043 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3044 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3045 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3046 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3047
3048 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3049 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3050
3051 /*
3052 * Set up VF register offsets for selected VT Mode,
3053 * i.e. 32 or 64 VFs for SR-IOV
3054 */
3055 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3056 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3057 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3058 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3059
3060 /* enable Tx loopback for VF/PF communication */
3061 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
a985b6c3 3062 /* Enable MAC Anti-Spoofing */
a1cbb15c 3063 hw->mac.ops.set_mac_anti_spoofing(hw,
de4c7f65 3064 (adapter->num_vfs != 0),
a985b6c3 3065 adapter->num_vfs);
de4c7f65
GR		 3066 /* For VFs that have spoof checking turned off */
3067 for (i = 0; i < adapter->num_vfs; i++) {
3068 if (!adapter->vfinfo[i].spoofchk_enabled)
3069 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3070 }
f5b4a52e
AD		 3071}
3072
477de6ed 3073static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3074{
9a799d71
AK		 3075 struct ixgbe_hw *hw = &adapter->hw;
3076 struct net_device *netdev = adapter->netdev;
3077 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
7c6e0a43 3078 int rx_buf_len;
477de6ed
AD		 3079 struct ixgbe_ring *rx_ring;
3080 int i;
3081 u32 mhadd, hlreg0;
48654521 3082
9a799d71 3083 /* Decide whether to use packet split mode or not */
a124339a
DS		 3084 /* On by default */
3085 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3086
1cdd1ec8 3087 /* Do not use packet split if we're in SR-IOV Mode */
a124339a
DS		 3088 if (adapter->num_vfs)
3089 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3090
3091 /* Disable packet split due to 82599 erratum #45 */
3092 if (hw->mac.type == ixgbe_mac_82599EB)
3093 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
9a799d71 3094
63f39bd1 3095#ifdef IXGBE_FCOE
477de6ed
AD		 3096 /* adjust max frame to be able to do baby jumbo for FCoE */
3097 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3098 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3099 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3100
477de6ed
AD		 3101#endif /* IXGBE_FCOE */
3102 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3103 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3104 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3105 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3106
3107 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3108 }
3109
919e78a6
AD		 3110 /* MHADD will allow an extra 4 bytes past for vlan tagged frames */
3111 max_frame += VLAN_HLEN;
3112
3113 /* Set the RX buffer length according to the mode */
3114 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3115 rx_buf_len = IXGBE_RX_HDR_SIZE;
3116 } else {
3117 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3118 (netdev->mtu <= ETH_DATA_LEN))
3119 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3120 /*
3121 * Make best use of allocation by using all but 1K of a
3122 * power of 2 allocation that will be used for skb->head.
3123 */
3124 else if (max_frame <= IXGBE_RXBUFFER_3K)
3125 rx_buf_len = IXGBE_RXBUFFER_3K;
3126 else if (max_frame <= IXGBE_RXBUFFER_7K)
3127 rx_buf_len = IXGBE_RXBUFFER_7K;
3128 else if (max_frame <= IXGBE_RXBUFFER_15K)
3129 rx_buf_len = IXGBE_RXBUFFER_15K;
3130 else
3131 rx_buf_len = IXGBE_MAX_RXBUFFER;
3132 }
3133
477de6ed
AD		 3134 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3135 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3136 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3137 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3138
0cefafad
JB		 3139 /*
3140 * Setup the HW Rx Head and Tail Descriptor Pointers and
3141 * the Base and Length of the Rx Descriptor Ring
3142 */
9a799d71 3143 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3144 rx_ring = adapter->rx_ring[i];
a6616b42 3145 rx_ring->rx_buf_len = rx_buf_len;
cc41ac7c 3146
6e455b89 3147 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
7d637bcc
AD		 3148 set_ring_ps_enabled(rx_ring);
3149 else
3150 clear_ring_ps_enabled(rx_ring);
3151
3152 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3153 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3154 else
7d637bcc 3155 clear_ring_rsc_enabled(rx_ring);
cc41ac7c 3156
63f39bd1 3157#ifdef IXGBE_FCOE
e8e9f696 3158 if (netdev->features & NETIF_F_FCOE_MTU) {
63f39bd1
YZ		 3159 struct ixgbe_ring_feature *f;
3160 f = &adapter->ring_feature[RING_F_FCOE];
6e455b89 3161 if ((i >= f->mask) && (i < f->mask + f->indices)) {
7d637bcc 3162 clear_ring_ps_enabled(rx_ring);
6e455b89
YZ		 3163 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3164 rx_ring->rx_buf_len =
e8e9f696 3165 IXGBE_FCOE_JUMBO_FRAME_SIZE;
7d637bcc
AD		 3166 } else if (!ring_is_rsc_enabled(rx_ring) &&
3167 !ring_is_ps_enabled(rx_ring)) {
3168 rx_ring->rx_buf_len =
3169 IXGBE_FCOE_JUMBO_FRAME_SIZE;
6e455b89 3170 }
63f39bd1 3171 }
63f39bd1 3172#endif /* IXGBE_FCOE */
477de6ed 3173 }
477de6ed
AD		 3174}
3175
7367096a
AD		 3176static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3177{
3178 struct ixgbe_hw *hw = &adapter->hw;
3179 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3180
3181 switch (hw->mac.type) {
3182 case ixgbe_mac_82598EB:
3183 /*
3184 * For VMDq support of different descriptor types or
3185 * buffer sizes through the use of multiple SRRCTL
3186 * registers, RDRXCTL.MVMEN must be set to 1
3187 *
3188 * also, the manual doesn't mention it clearly but DCA hints
3189 * will only use queue 0's tags unless this bit is set. Side
3190 * effects of setting this bit are only that SRRCTL must be
3191 * fully programmed [0..15]
3192 */
3193 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3194 break;
3195 case ixgbe_mac_82599EB:
b93a2226 3196 case ixgbe_mac_X540:
7367096a
AD		 3197 /* Disable RSC for ACK packets */
3198 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3199 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3200 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3201 /* hardware requires some bits to be set by default */
3202 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3203 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3204 break;
3205 default:
3206 /* We should do nothing since we don't know this hardware */
3207 return;
3208 }
3209
3210 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3211}
3212
477de6ed
AD		 3213/**
3214 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3215 * @adapter: board private structure
3216 *
3217 * Configure the Rx unit of the MAC after a reset.
3218 **/
3219static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3220{
3221 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3222 int i;
3223 u32 rxctrl;
477de6ed
AD		 3224
3225 /* disable receives while setting up the descriptors */
3226 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3227 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3228
3229 ixgbe_setup_psrtype(adapter);
7367096a 3230 ixgbe_setup_rdrxctl(adapter);
477de6ed 3231
9e10e045 3232 /* Program registers for the distribution of queues */
f5b4a52e 3233 ixgbe_setup_mrqc(adapter);
f5b4a52e 3234
9e10e045
AD		 3235 ixgbe_set_uta(adapter);
3236
477de6ed
AD		 3237 /* set_rx_buffer_len must be called before ring initialization */
3238 ixgbe_set_rx_buffer_len(adapter);
3239
3240 /*
3241 * Setup the HW Rx Head and Tail Descriptor Pointers and
3242 * the Base and Length of the Rx Descriptor Ring
3243 */
9e10e045
AD		 3244 for (i = 0; i < adapter->num_rx_queues; i++)
3245 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3246
9e10e045
AD		 3247 /* disable drop enable for 82598 parts */
3248 if (hw->mac.type == ixgbe_mac_82598EB)
3249 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3250
3251 /* enable all receives */
3252 rxctrl |= IXGBE_RXCTRL_RXEN;
3253 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3254}
3255
8e586137 3256static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3257{
3258 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3259 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3260 int pool_ndx = adapter->num_vfs;
068c89b0
DS		 3261
3262 /* add VID to filter table */
1ada1b1b 3263 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
f62bbb5e 3264 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3265
3266 return 0;
068c89b0
DS		 3267}
3268
8e586137 3269static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
068c89b0
DS		 3270{
3271 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3272 struct ixgbe_hw *hw = &adapter->hw;
1ada1b1b 3273 int pool_ndx = adapter->num_vfs;
068c89b0 3274
068c89b0 3275 /* remove VID from filter table */
1ada1b1b 3276 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
f62bbb5e 3277 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3278
3279 return 0;
068c89b0
DS		 3280}
3281
5f6c0181
JB		 3282/**
3283 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3284 * @adapter: driver data
3285 */
3286static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3287{
3288 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3289 u32 vlnctrl;
3290
3291 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3292 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3293 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3294}
3295
3296/**
3297 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3298 * @adapter: driver data
3299 */
3300static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3301{
3302 struct ixgbe_hw *hw = &adapter->hw;
3303 u32 vlnctrl;
3304
3305 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3306 vlnctrl |= IXGBE_VLNCTRL_VFE;
3307 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3308 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3309}
3310
3311/**
3312 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3313 * @adapter: driver data
3314 */
3315static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3316{
3317 struct ixgbe_hw *hw = &adapter->hw;
3318 u32 vlnctrl;
5f6c0181
JB		 3319 int i, j;
3320
3321 switch (hw->mac.type) {
3322 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3323 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3324 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3325 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3326 break;
3327 case ixgbe_mac_82599EB:
b93a2226 3328 case ixgbe_mac_X540:
5f6c0181
JB		 3329 for (i = 0; i < adapter->num_rx_queues; i++) {
3330 j = adapter->rx_ring[i]->reg_idx;
3331 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3332 vlnctrl &= ~IXGBE_RXDCTL_VME;
3333 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3334 }
3335 break;
3336 default:
3337 break;
3338 }
3339}
3340
3341/**
f62bbb5e 3342 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3343 * @adapter: driver data
3344 */
f62bbb5e 3345static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3346{
3347 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3348 u32 vlnctrl;
5f6c0181
JB		 3349 int i, j;
3350
3351 switch (hw->mac.type) {
3352 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3353 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3354 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3355 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3356 break;
3357 case ixgbe_mac_82599EB:
b93a2226 3358 case ixgbe_mac_X540:
5f6c0181
JB		 3359 for (i = 0; i < adapter->num_rx_queues; i++) {
3360 j = adapter->rx_ring[i]->reg_idx;
3361 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3362 vlnctrl |= IXGBE_RXDCTL_VME;
3363 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3364 }
3365 break;
3366 default:
3367 break;
3368 }
3369}
3370
9a799d71
AK		 3371static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3372{
f62bbb5e 3373 u16 vid;
9a799d71 3374
f62bbb5e
JG		 3375 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3376
3377 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3378 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
9a799d71
AK		 3379}
3380
2850062a
AD		 3381/**
3382 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3383 * @netdev: network interface device structure
3384 *
3385 * Writes unicast address list to the RAR table.
3386 * Returns: -ENOMEM on failure/insufficient address space
3387 * 0 on no addresses written
3388 * X on writing X addresses to the RAR table
3389 **/
3390static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3391{
3392 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3393 struct ixgbe_hw *hw = &adapter->hw;
3394 unsigned int vfn = adapter->num_vfs;
a1cbb15c 3395 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
2850062a
AD		 3396 int count = 0;
3397
3398 /* return ENOMEM indicating insufficient memory for addresses */
3399 if (netdev_uc_count(netdev) > rar_entries)
3400 return -ENOMEM;
3401
3402 if (!netdev_uc_empty(netdev) && rar_entries) {
3403 struct netdev_hw_addr *ha;
3404 /* return error if we do not support writing to RAR table */
3405 if (!hw->mac.ops.set_rar)
3406 return -ENOMEM;
3407
3408 netdev_for_each_uc_addr(ha, netdev) {
3409 if (!rar_entries)
3410 break;
3411 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3412 vfn, IXGBE_RAH_AV);
3413 count++;
3414 }
3415 }
3416 /* write the addresses in reverse order to avoid write combining */
3417 for (; rar_entries > 0 ; rar_entries--)
3418 hw->mac.ops.clear_rar(hw, rar_entries);
3419
3420 return count;
3421}
3422
9a799d71 3423/**
2c5645cf 3424 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3425 * @netdev: network interface device structure
3426 *
2c5645cf
CL		 3427 * The set_rx_method entry point is called whenever the unicast/multicast
3428 * address list or the network interface flags are updated. This routine is
3429 * responsible for configuring the hardware for proper unicast, multicast and
3430 * promiscuous mode.
9a799d71 3431 **/
7f870475 3432void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3433{
3434 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3435 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3436 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3437 int count;
9a799d71
AK		 3438
3439 /* Check for Promiscuous and All Multicast modes */
3440
3441 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3442
f5dc442b
AD		 3443 /* set all bits that we expect to always be set */
3444 fctrl |= IXGBE_FCTRL_BAM;
3445 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3446 fctrl |= IXGBE_FCTRL_PMCF;
3447
2850062a
AD		 3448 /* clear the bits we are changing the status of */
3449 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3450
9a799d71 3451 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3452 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3453 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3454 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
5f6c0181
JB		 3455 /* don't hardware filter vlans in promisc mode */
3456 ixgbe_vlan_filter_disable(adapter);
9a799d71 3457 } else {
746b9f02
PM		 3458 if (netdev->flags & IFF_ALLMULTI) {
3459 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3460 vmolr |= IXGBE_VMOLR_MPE;
3461 } else {
3462 /*
3463 * Write addresses to the MTA, if the attempt fails
25985edc 3464 * then we should just turn on promiscuous mode so
2850062a
AD		 3465 * that we can at least receive multicast traffic
3466 */
3467 hw->mac.ops.update_mc_addr_list(hw, netdev);
3468 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3469 }
5f6c0181 3470 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3471 hw->addr_ctrl.user_set_promisc = false;
2850062a
AD		 3472 /*
3473 * Write addresses to available RAR registers, if there is not
3474 * sufficient space to store all the addresses then enable
25985edc 3475 * unicast promiscuous mode
2850062a
AD		 3476 */
3477 count = ixgbe_write_uc_addr_list(netdev);
3478 if (count < 0) {
3479 fctrl |= IXGBE_FCTRL_UPE;
3480 vmolr |= IXGBE_VMOLR_ROPE;
3481 }
9a799d71
AK		 3482 }
3483
2850062a 3484 if (adapter->num_vfs) {
1cdd1ec8 3485 ixgbe_restore_vf_multicasts(adapter);
2850062a
AD		 3486 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3487 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3488 IXGBE_VMOLR_ROPE);
3489 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3490 }
3491
3492 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e
JG		 3493
3494 if (netdev->features & NETIF_F_HW_VLAN_RX)
3495 ixgbe_vlan_strip_enable(adapter);
3496 else
3497 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3498}
3499
021230d4
AV		 3500static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3501{
3502 int q_idx;
3503 struct ixgbe_q_vector *q_vector;
3504 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3505
3506 /* legacy and MSI only use one vector */
3507 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3508 q_vectors = 1;
3509
3510 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3511 q_vector = adapter->q_vector[q_idx];
4ff7fb12 3512 napi_enable(&q_vector->napi);
021230d4
AV		 3513 }
3514}
3515
3516static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3517{
3518 int q_idx;
3519 struct ixgbe_q_vector *q_vector;
3520 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3521
3522 /* legacy and MSI only use one vector */
3523 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3524 q_vectors = 1;
3525
3526 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
7a921c93 3527 q_vector = adapter->q_vector[q_idx];
021230d4
AV		 3528 napi_disable(&q_vector->napi);
3529 }
3530}
3531
7a6b6f51 3532#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 3533/*
3534 * ixgbe_configure_dcb - Configure DCB hardware
3535 * @adapter: ixgbe adapter struct
3536 *
3537 * This is called by the driver on open to configure the DCB hardware.
3538 * This is also called by the gennetlink interface when reconfiguring
3539 * the DCB state.
3540 */
3541static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3542{
3543 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3544 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3545
67ebd791
AD		 3546 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3547 if (hw->mac.type == ixgbe_mac_82598EB)
3548 netif_set_gso_max_size(adapter->netdev, 65536);
3549 return;
3550 }
3551
3552 if (hw->mac.type == ixgbe_mac_82598EB)
3553 netif_set_gso_max_size(adapter->netdev, 32768);
3554
2f90b865 3555
2f90b865 3556 /* Enable VLAN tag insert/strip */
f62bbb5e 3557 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
5f6c0181 3558
2f90b865 3559 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
01fa7d90 3560
971060b1 3561#ifdef IXGBE_FCOE
b120818e
JF		 3562 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3563 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3564#endif
b120818e
JF		 3565
3566 /* reconfigure the hardware */
3567 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3568 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3569 DCB_TX_CONFIG);
3570 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3571 DCB_RX_CONFIG);
3572 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3573 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3574 ixgbe_dcb_hw_ets(&adapter->hw,
3575 adapter->ixgbe_ieee_ets,
3576 max_frame);
3577 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3578 adapter->ixgbe_ieee_pfc->pfc_en,
3579 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3580 }
8187cd48
JF		 3581
3582 /* Enable RSS Hash per TC */
3583 if (hw->mac.type != ixgbe_mac_82598EB) {
3584 int i;
3585 u32 reg = 0;
3586
3587 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3588 u8 msb = 0;
3589 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3590
3591 while (cnt >>= 1)
3592 msb++;
3593
3594 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3595 }
3596 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3597 }
2f90b865 3598}
9da712d2
JF		 3599#endif
3600
3601/* Additional bittime to account for IXGBE framing */
3602#define IXGBE_ETH_FRAMING 20
3603
3604/*
3605 * ixgbe_hpbthresh - calculate high water mark for flow control
3606 *
3607 * @adapter: board private structure to calculate for
3608 * @pb - packet buffer to calculate
3609 */
3610static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3611{
3612 struct ixgbe_hw *hw = &adapter->hw;
3613 struct net_device *dev = adapter->netdev;
3614 int link, tc, kb, marker;
3615 u32 dv_id, rx_pba;
3616
3617 /* Calculate max LAN frame size */
3618 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3619
3620#ifdef IXGBE_FCOE
3621 /* FCoE traffic class uses FCOE jumbo frames */
3622 if (dev->features & NETIF_F_FCOE_MTU) {
3623 int fcoe_pb = 0;
2f90b865 3624
9da712d2
JF		 3625#ifdef CONFIG_IXGBE_DCB
3626 fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
3627
3628#endif
3629 if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3630 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3631 }
2f90b865 3632#endif
80605c65 3633
9da712d2
JF		 3634 /* Calculate delay value for device */
3635 switch (hw->mac.type) {
3636 case ixgbe_mac_X540:
3637 dv_id = IXGBE_DV_X540(link, tc);
3638 break;
3639 default:
3640 dv_id = IXGBE_DV(link, tc);
3641 break;
3642 }
3643
3644 /* Loopback switch introduces additional latency */
3645 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3646 dv_id += IXGBE_B2BT(tc);
3647
3648 /* Delay value is calculated in bit times convert to KB */
3649 kb = IXGBE_BT2KB(dv_id);
3650 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
3651
3652 marker = rx_pba - kb;
3653
3654 /* It is possible that the packet buffer is not large enough
3655 * to provide required headroom. In this case throw an error
3656 * to user and a do the best we can.
3657 */
3658 if (marker < 0) {
3659 e_warn(drv, "Packet Buffer(%i) can not provide enough"
3660 "headroom to support flow control."
3661 "Decrease MTU or number of traffic classes\n", pb);
3662 marker = tc + 1;
3663 }
3664
3665 return marker;
3666}
3667
3668/*
3669 * ixgbe_lpbthresh - calculate low water mark for for flow control
3670 *
3671 * @adapter: board private structure to calculate for
3672 * @pb - packet buffer to calculate
3673 */
3674static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
3675{
3676 struct ixgbe_hw *hw = &adapter->hw;
3677 struct net_device *dev = adapter->netdev;
3678 int tc;
3679 u32 dv_id;
3680
3681 /* Calculate max LAN frame size */
3682 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
3683
3684 /* Calculate delay value for device */
3685 switch (hw->mac.type) {
3686 case ixgbe_mac_X540:
3687 dv_id = IXGBE_LOW_DV_X540(tc);
3688 break;
3689 default:
3690 dv_id = IXGBE_LOW_DV(tc);
3691 break;
3692 }
3693
3694 /* Delay value is calculated in bit times convert to KB */
3695 return IXGBE_BT2KB(dv_id);
3696}
3697
3698/*
3699 * ixgbe_pbthresh_setup - calculate and setup high low water marks
3700 */
3701static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
3702{
3703 struct ixgbe_hw *hw = &adapter->hw;
3704 int num_tc = netdev_get_num_tc(adapter->netdev);
3705 int i;
3706
3707 if (!num_tc)
3708 num_tc = 1;
3709
3710 hw->fc.low_water = ixgbe_lpbthresh(adapter);
3711
3712 for (i = 0; i < num_tc; i++) {
3713 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
3714
3715 /* Low water marks must not be larger than high water marks */
3716 if (hw->fc.low_water > hw->fc.high_water[i])
3717 hw->fc.low_water = 0;
3718 }
3719}
3720
80605c65
JF		 3721static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3722{
80605c65 3723 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 3724 int hdrm;
3725 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 3726
3727 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3728 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 3729 hdrm = 32 << adapter->fdir_pballoc;
3730 else
3731 hdrm = 0;
80605c65 3732
f7e1027f 3733 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 3734 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 3735}
3736
e4911d57
AD		 3737static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3738{
3739 struct ixgbe_hw *hw = &adapter->hw;
3740 struct hlist_node *node, *node2;
3741 struct ixgbe_fdir_filter *filter;
3742
3743 spin_lock(&adapter->fdir_perfect_lock);
3744
3745 if (!hlist_empty(&adapter->fdir_filter_list))
3746 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3747
3748 hlist_for_each_entry_safe(filter, node, node2,
3749 &adapter->fdir_filter_list, fdir_node) {
3750 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 3751 &filter->filter,
3752 filter->sw_idx,
3753 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3754 IXGBE_FDIR_DROP_QUEUE :
3755 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 3756 }
3757
3758 spin_unlock(&adapter->fdir_perfect_lock);
3759}
3760
9a799d71
AK		 3761static void ixgbe_configure(struct ixgbe_adapter *adapter)
3762{
80605c65 3763 ixgbe_configure_pb(adapter);
7a6b6f51 3764#ifdef CONFIG_IXGBE_DCB
67ebd791 3765 ixgbe_configure_dcb(adapter);
2f90b865 3766#endif
9a799d71 3767
4c1d7b4b 3768 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 3769 ixgbe_restore_vlan(adapter);
3770
eacd73f7
YZ		 3771#ifdef IXGBE_FCOE
3772 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3773 ixgbe_configure_fcoe(adapter);
3774
3775#endif /* IXGBE_FCOE */
c4cf55e5 3776 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 3777 ixgbe_init_fdir_signature_82599(&adapter->hw,
3778 adapter->fdir_pballoc);
e4911d57
AD		 3779 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3780 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3781 adapter->fdir_pballoc);
3782 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 3783 }
4c1d7b4b 3784
933d41f1 3785 ixgbe_configure_virtualization(adapter);
c4cf55e5 3786
9a799d71
AK		 3787 ixgbe_configure_tx(adapter);
3788 ixgbe_configure_rx(adapter);
9a799d71
AK		 3789}
3790
e8e26350
PW		 3791static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3792{
3793 switch (hw->phy.type) {
3794 case ixgbe_phy_sfp_avago:
3795 case ixgbe_phy_sfp_ftl:
3796 case ixgbe_phy_sfp_intel:
3797 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 3798 case ixgbe_phy_sfp_passive_tyco:
3799 case ixgbe_phy_sfp_passive_unknown:
3800 case ixgbe_phy_sfp_active_unknown:
3801 case ixgbe_phy_sfp_ftl_active:
e8e26350 3802 return true;
8917b447
AD		 3803 case ixgbe_phy_nl:
3804 if (hw->mac.type == ixgbe_mac_82598EB)
3805 return true;
e8e26350
PW		 3806 default:
3807 return false;
3808 }
3809}
3810
0ecc061d 3811/**
e8e26350
PW		 3812 * ixgbe_sfp_link_config - set up SFP+ link
3813 * @adapter: pointer to private adapter struct
3814 **/
3815static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3816{
7086400d 3817 /*
52f33af8 3818 * We are assuming the worst case scenario here, and that
7086400d
AD		 3819 * is that an SFP was inserted/removed after the reset
3820 * but before SFP detection was enabled. As such the best
3821 * solution is to just start searching as soon as we start
3822 */
3823 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3824 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 3825
7086400d 3826 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 3827}
3828
3829/**
3830 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 3831 * @hw: pointer to private hardware struct
3832 *
3833 * Returns 0 on success, negative on failure
3834 **/
e8e26350 3835static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d
PWJ		 3836{
3837 u32 autoneg;
8620a103 3838 bool negotiation, link_up = false;
0ecc061d
PWJ		 3839 u32 ret = IXGBE_ERR_LINK_SETUP;
3840
3841 if (hw->mac.ops.check_link)
3842 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3843
3844 if (ret)
3845 goto link_cfg_out;
3846
0b0c2b31
ET		 3847 autoneg = hw->phy.autoneg_advertised;
3848 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
e8e9f696
JP		 3849 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3850 &negotiation);
0ecc061d
PWJ		 3851 if (ret)
3852 goto link_cfg_out;
3853
8620a103
MC		 3854 if (hw->mac.ops.setup_link)
3855 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
0ecc061d
PWJ		 3856link_cfg_out:
3857 return ret;
3858}
3859
a34bcfff 3860static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 3861{
9a799d71 3862 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3863 u32 gpie = 0;
9a799d71 3864
9b471446 3865 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 3866 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3867 IXGBE_GPIE_OCD;
3868 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 3869 /*
3870 * use EIAM to auto-mask when MSI-X interrupt is asserted
3871 * this saves a register write for every interrupt
3872 */
3873 switch (hw->mac.type) {
3874 case ixgbe_mac_82598EB:
3875 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3876 break;
9b471446 3877 case ixgbe_mac_82599EB:
b93a2226
DS		 3878 case ixgbe_mac_X540:
3879 default:
9b471446
JB		 3880 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3881 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3882 break;
3883 }
3884 } else {
021230d4
AV		 3885 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3886 * specifically only auto mask tx and rx interrupts */
3887 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3888 }
9a799d71 3889
a34bcfff
AD		 3890 /* XXX: to interrupt immediately for EICS writes, enable this */
3891 /* gpie |= IXGBE_GPIE_EIMEN; */
3892
3893 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3894 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3895 gpie |= IXGBE_GPIE_VTMODE_64;
119fc60a
MC		 3896 }
3897
5fdd31f9 3898 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 3899 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
3900 switch (adapter->hw.mac.type) {
3901 case ixgbe_mac_82599EB:
3902 gpie |= IXGBE_SDP0_GPIEN;
3903 break;
3904 case ixgbe_mac_X540:
3905 gpie |= IXGBE_EIMS_TS;
3906 break;
3907 default:
3908 break;
3909 }
3910 }
5fdd31f9 3911
a34bcfff
AD		 3912 /* Enable fan failure interrupt */
3913 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 3914 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 3915
2698b208 3916 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 3917 gpie |= IXGBE_SDP1_GPIEN;
3918 gpie |= IXGBE_SDP2_GPIEN;
2698b208 3919 }
a34bcfff
AD		 3920
3921 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3922}
3923
c7ccde0f 3924static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 3925{
3926 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 3927 int err;
a34bcfff
AD		 3928 u32 ctrl_ext;
3929
3930 ixgbe_get_hw_control(adapter);
3931 ixgbe_setup_gpie(adapter);
e8e26350 3932
9a799d71
AK		 3933 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3934 ixgbe_configure_msix(adapter);
3935 else
3936 ixgbe_configure_msi_and_legacy(adapter);
3937
c6ecf39a
DS		 3938 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3939 if (hw->mac.ops.enable_tx_laser &&
3940 ((hw->phy.multispeed_fiber) ||
9f911707 3941 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a 3942 (hw->mac.type == ixgbe_mac_82599EB))))
61fac744
PW		 3943 hw->mac.ops.enable_tx_laser(hw);
3944
9a799d71 3945 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 3946 ixgbe_napi_enable_all(adapter);
3947
73c4b7cd
AD		 3948 if (ixgbe_is_sfp(hw)) {
3949 ixgbe_sfp_link_config(adapter);
3950 } else {
3951 err = ixgbe_non_sfp_link_config(hw);
3952 if (err)
3953 e_err(probe, "link_config FAILED %d\n", err);
3954 }
3955
021230d4
AV		 3956 /* clear any pending interrupts, may auto mask */
3957 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 3958 ixgbe_irq_enable(adapter, true, true);
9a799d71 3959
bf069c97
DS		 3960 /*
3961 * If this adapter has a fan, check to see if we had a failure
3962 * before we enabled the interrupt.
3963 */
3964 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3965 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3966 if (esdp & IXGBE_ESDP_SDP1)
396e799c 3967 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 3968 }
3969
1da100bb 3970 /* enable transmits */
477de6ed 3971 netif_tx_start_all_queues(adapter->netdev);
1da100bb 3972
9a799d71
AK		 3973 /* bring the link up in the watchdog, this could race with our first
3974 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 3975 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3976 adapter->link_check_timeout = jiffies;
7086400d 3977 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 3978
3979 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3980 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3981 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3982 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 3983}
3984
d4f80882
AV		 3985void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3986{
3987 WARN_ON(in_interrupt());
7086400d
AD		 3988 /* put off any impending NetWatchDogTimeout */
3989 adapter->netdev->trans_start = jiffies;
3990
d4f80882 3991 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 3992 usleep_range(1000, 2000);
d4f80882 3993 ixgbe_down(adapter);
5809a1ae
GR		 3994 /*
3995 * If SR-IOV enabled then wait a bit before bringing the adapter
3996 * back up to give the VFs time to respond to the reset. The
3997 * two second wait is based upon the watchdog timer cycle in
3998 * the VF driver.
3999 */
4000 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4001 msleep(2000);
d4f80882
AV		 4002 ixgbe_up(adapter);
4003 clear_bit(__IXGBE_RESETTING, &adapter->state);
4004}
4005
c7ccde0f 4006void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4007{
4008 /* hardware has been reset, we need to reload some things */
4009 ixgbe_configure(adapter);
4010
c7ccde0f 4011 ixgbe_up_complete(adapter);
9a799d71
AK		 4012}
4013
4014void ixgbe_reset(struct ixgbe_adapter *adapter)
4015{
c44ade9e 4016 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4017 int err;
4018
7086400d
AD		 4019 /* lock SFP init bit to prevent race conditions with the watchdog */
4020 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4021 usleep_range(1000, 2000);
4022
4023 /* clear all SFP and link config related flags while holding SFP_INIT */
4024 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4025 IXGBE_FLAG2_SFP_NEEDS_RESET);
4026 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4027
8ca783ab 4028 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4029 switch (err) {
4030 case 0:
4031 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4032 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4033 break;
4034 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4035 e_dev_err("master disable timed out\n");
da4dd0f7 4036 break;
794caeb2
PWJ		 4037 case IXGBE_ERR_EEPROM_VERSION:
4038 /* We are running on a pre-production device, log a warning */
849c4542 4039 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4040 "Please be aware there may be issues associated with "
849c4542
ET		 4041 "your hardware. If you are experiencing problems "
4042 "please contact your Intel or hardware "
4043 "representative who provided you with this "
4044 "hardware.\n");
794caeb2 4045 break;
da4dd0f7 4046 default:
849c4542 4047 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4048 }
9a799d71 4049
7086400d
AD		 4050 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4051
9a799d71 4052 /* reprogram the RAR[0] in case user changed it. */
1cdd1ec8
GR		 4053 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4054 IXGBE_RAH_AV);
9a799d71
AK		 4055}
4056
9a799d71
AK		 4057/**
4058 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4059 * @rx_ring: ring to free buffers from
4060 **/
b6ec895e 4061static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4062{
b6ec895e 4063 struct device *dev = rx_ring->dev;
9a799d71 4064 unsigned long size;
b6ec895e 4065 u16 i;
9a799d71 4066
84418e3b
AD		 4067 /* ring already cleared, nothing to do */
4068 if (!rx_ring->rx_buffer_info)
4069 return;
9a799d71 4070
84418e3b 4071 /* Free all the Rx ring sk_buffs */
9a799d71
AK		 4072 for (i = 0; i < rx_ring->count; i++) {
4073 struct ixgbe_rx_buffer *rx_buffer_info;
4074
4075 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4076 if (rx_buffer_info->dma) {
b6ec895e 4077 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
e8e9f696 4078 rx_ring->rx_buf_len,
1b507730 4079 DMA_FROM_DEVICE);
9a799d71
AK		 4080 rx_buffer_info->dma = 0;
4081 }
4082 if (rx_buffer_info->skb) {
f8212f97 4083 struct sk_buff *skb = rx_buffer_info->skb;
9a799d71 4084 rx_buffer_info->skb = NULL;
4c1975d7
AD		 4085 /* We need to clean up RSC frag lists */
4086 skb = ixgbe_merge_active_tail(skb);
4087 ixgbe_close_active_frag_list(skb);
4088 if (IXGBE_CB(skb)->delay_unmap) {
4089 dma_unmap_single(dev,
4090 IXGBE_CB(skb)->dma,
4091 rx_ring->rx_buf_len,
4092 DMA_FROM_DEVICE);
4093 IXGBE_CB(skb)->dma = 0;
4094 IXGBE_CB(skb)->delay_unmap = false;
4095 }
4096 dev_kfree_skb(skb);
9a799d71
AK		 4097 }
4098 if (!rx_buffer_info->page)
4099 continue;
4f57ca6e 4100 if (rx_buffer_info->page_dma) {
b6ec895e 4101 dma_unmap_page(dev, rx_buffer_info->page_dma,
1b507730 4102 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4f57ca6e
JB		 4103 rx_buffer_info->page_dma = 0;
4104 }
9a799d71
AK		 4105 put_page(rx_buffer_info->page);
4106 rx_buffer_info->page = NULL;
762f4c57 4107 rx_buffer_info->page_offset = 0;
9a799d71
AK		 4108 }
4109
4110 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4111 memset(rx_ring->rx_buffer_info, 0, size);
4112
4113 /* Zero out the descriptor ring */
4114 memset(rx_ring->desc, 0, rx_ring->size);
4115
4116 rx_ring->next_to_clean = 0;
4117 rx_ring->next_to_use = 0;
9a799d71
AK		 4118}
4119
4120/**
4121 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4122 * @tx_ring: ring to be cleaned
4123 **/
b6ec895e 4124static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4125{
4126 struct ixgbe_tx_buffer *tx_buffer_info;
4127 unsigned long size;
b6ec895e 4128 u16 i;
9a799d71 4129
84418e3b
AD		 4130 /* ring already cleared, nothing to do */
4131 if (!tx_ring->tx_buffer_info)
4132 return;
9a799d71 4133
84418e3b 4134 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4135 for (i = 0; i < tx_ring->count; i++) {
4136 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4137 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4138 }
4139
4140 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4141 memset(tx_ring->tx_buffer_info, 0, size);
4142
4143 /* Zero out the descriptor ring */
4144 memset(tx_ring->desc, 0, tx_ring->size);
4145
4146 tx_ring->next_to_use = 0;
4147 tx_ring->next_to_clean = 0;
9a799d71
AK		 4148}
4149
4150/**
021230d4 4151 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4152 * @adapter: board private structure
4153 **/
021230d4 4154static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4155{
4156 int i;
4157
021230d4 4158 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4159 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4160}
4161
4162/**
021230d4 4163 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4164 * @adapter: board private structure
4165 **/
021230d4 4166static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4167{
4168 int i;
4169
021230d4 4170 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4171 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4172}
4173
e4911d57
AD		 4174static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4175{
4176 struct hlist_node *node, *node2;
4177 struct ixgbe_fdir_filter *filter;
4178
4179 spin_lock(&adapter->fdir_perfect_lock);
4180
4181 hlist_for_each_entry_safe(filter, node, node2,
4182 &adapter->fdir_filter_list, fdir_node) {
4183 hlist_del(&filter->fdir_node);
4184 kfree(filter);
4185 }
4186 adapter->fdir_filter_count = 0;
4187
4188 spin_unlock(&adapter->fdir_perfect_lock);
4189}
4190
9a799d71
AK		 4191void ixgbe_down(struct ixgbe_adapter *adapter)
4192{
4193 struct net_device *netdev = adapter->netdev;
7f821875 4194 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4195 u32 rxctrl;
bf29ee6c 4196 int i;
9a799d71
AK		 4197
4198 /* signal that we are down to the interrupt handler */
4199 set_bit(__IXGBE_DOWN, &adapter->state);
4200
4201 /* disable receives */
7f821875
JB		 4202 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4203 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4204
2d39d576
YZ		 4205 /* disable all enabled rx queues */
4206 for (i = 0; i < adapter->num_rx_queues; i++)
4207 /* this call also flushes the previous write */
4208 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4209
032b4325 4210 usleep_range(10000, 20000);
9a799d71 4211
7f821875
JB		 4212 netif_tx_stop_all_queues(netdev);
4213
7086400d 4214 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4215 netif_carrier_off(netdev);
4216 netif_tx_disable(netdev);
4217
4218 ixgbe_irq_disable(adapter);
4219
4220 ixgbe_napi_disable_all(adapter);
4221
d034acf1
AD		 4222 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4223 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4224 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4225
4226 del_timer_sync(&adapter->service_timer);
4227
34cecbbf 4228 if (adapter->num_vfs) {
8e34d1aa
AD		 4229 /* Clear EITR Select mapping */
4230 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4231
4232 /* Mark all the VFs as inactive */
4233 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4234 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4235
34cecbbf
AD		 4236 /* ping all the active vfs to let them know we are going down */
4237 ixgbe_ping_all_vfs(adapter);
4238
4239 /* Disable all VFTE/VFRE TX/RX */
4240 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4241 }
4242
7f821875
JB		 4243 /* disable transmits in the hardware now that interrupts are off */
4244 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4245 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4246 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4247 }
34cecbbf
AD		 4248
4249 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4250 switch (hw->mac.type) {
4251 case ixgbe_mac_82599EB:
b93a2226 4252 case ixgbe_mac_X540:
88512539 4253 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4254 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4255 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4256 break;
4257 default:
4258 break;
4259 }
7f821875 4260
6f4a0e45
PL		 4261 if (!pci_channel_offline(adapter->pdev))
4262 ixgbe_reset(adapter);
c6ecf39a
DS		 4263
4264 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4265 if (hw->mac.ops.disable_tx_laser &&
4266 ((hw->phy.multispeed_fiber) ||
9f911707 4267 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
c6ecf39a
DS		 4268 (hw->mac.type == ixgbe_mac_82599EB))))
4269 hw->mac.ops.disable_tx_laser(hw);
4270
9a799d71
AK		 4271 ixgbe_clean_all_tx_rings(adapter);
4272 ixgbe_clean_all_rx_rings(adapter);
4273
5dd2d332 4274#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4275 /* since we reset the hardware DCA settings were cleared */
e35ec126 4276 ixgbe_setup_dca(adapter);
96b0e0f6 4277#endif
9a799d71
AK		 4278}
4279
9a799d71 4280/**
021230d4
AV		 4281 * ixgbe_poll - NAPI Rx polling callback
4282 * @napi: structure for representing this polling device
4283 * @budget: how many packets driver is allowed to clean
4284 *
4285 * This function is used for legacy and MSI, NAPI mode
9a799d71 4286 **/
021230d4 4287static int ixgbe_poll(struct napi_struct *napi, int budget)
9a799d71 4288{
9a1a69ad 4289 struct ixgbe_q_vector *q_vector =
e8e9f696 4290 container_of(napi, struct ixgbe_q_vector, napi);
021230d4 4291 struct ixgbe_adapter *adapter = q_vector->adapter;
4ff7fb12
AD		 4292 struct ixgbe_ring *ring;
4293 int per_ring_budget;
4294 bool clean_complete = true;
9a799d71 4295
5dd2d332 4296#ifdef CONFIG_IXGBE_DCA
33cf09c9
AD		 4297 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4298 ixgbe_update_dca(q_vector);
bd0362dd
JC		 4299#endif
4300
4ff7fb12
AD		 4301 for (ring = q_vector->tx.ring; ring != NULL; ring = ring->next)
4302 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
9a799d71 4303
4ff7fb12
AD		 4304 /* attempt to distribute budget to each queue fairly, but don't allow
4305 * the budget to go below 1 because we'll exit polling */
4306 if (q_vector->rx.count > 1)
4307 per_ring_budget = max(budget/q_vector->rx.count, 1);
4308 else
4309 per_ring_budget = budget;
d2c7ddd6 4310
4ff7fb12
AD		 4311 for (ring = q_vector->rx.ring; ring != NULL; ring = ring->next)
4312 clean_complete &= ixgbe_clean_rx_irq(q_vector, ring,
4313 per_ring_budget);
4314
4315 /* If all work not completed, return budget and keep polling */
4316 if (!clean_complete)
4317 return budget;
4318
4319 /* all work done, exit the polling mode */
4320 napi_complete(napi);
4321 if (adapter->rx_itr_setting & 1)
4322 ixgbe_set_itr(q_vector);
4323 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4324 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
4325
4326 return 0;
9a799d71
AK		 4327}
4328
4329/**
4330 * ixgbe_tx_timeout - Respond to a Tx Hang
4331 * @netdev: network interface device structure
4332 **/
4333static void ixgbe_tx_timeout(struct net_device *netdev)
4334{
4335 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4336
4337 /* Do the reset outside of interrupt context */
c83c6cbd 4338 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4339}
4340
4df10466
JB		 4341/**
4342 * ixgbe_set_rss_queues: Allocate queues for RSS
4343 * @adapter: board private structure to initialize
4344 *
4345 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4346 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4347 *
4348 **/
bc97114d
PWJ		 4349static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4350{
4351 bool ret = false;
0cefafad 4352 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
bc97114d
PWJ		 4353
4354 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
0cefafad
JB		 4355 f->mask = 0xF;
4356 adapter->num_rx_queues = f->indices;
4357 adapter->num_tx_queues = f->indices;
bc97114d
PWJ		 4358 ret = true;
4359 } else {
bc97114d 4360 ret = false;
b9804972
JB		 4361 }
4362
bc97114d
PWJ		 4363 return ret;
4364}
4365
c4cf55e5
PWJ		 4366/**
4367 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4368 * @adapter: board private structure to initialize
4369 *
4370 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4371 * to the original CPU that initiated the Tx session. This runs in addition
4372 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4373 * Rx load across CPUs using RSS.
4374 *
4375 **/
e8e9f696 4376static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4377{
4378 bool ret = false;
4379 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4380
4381 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4382 f_fdir->mask = 0;
4383
4384 /* Flow Director must have RSS enabled */
03ecf91a
AD		 4385 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4386 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5
PWJ		 4387 adapter->num_tx_queues = f_fdir->indices;
4388 adapter->num_rx_queues = f_fdir->indices;
4389 ret = true;
4390 } else {
4391 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5
PWJ		 4392 }
4393 return ret;
4394}
4395
0331a832
YZ		 4396#ifdef IXGBE_FCOE
4397/**
4398 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4399 * @adapter: board private structure to initialize
4400 *
4401 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4402 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4403 * rx queues out of the max number of rx queues, instead, it is used as the
4404 * index of the first rx queue used by FCoE.
4405 *
4406 **/
4407static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4408{
0331a832
YZ		 4409 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4410
e5b64635
JF		 4411 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4412 return false;
4413
e901acd6 4414 f->indices = min((int)num_online_cpus(), f->indices);
e5b64635 4415
e901acd6
JF		 4416 adapter->num_rx_queues = 1;
4417 adapter->num_tx_queues = 1;
e5b64635 4418
e901acd6
JF		 4419 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4420 e_info(probe, "FCoE enabled with RSS\n");
03ecf91a 4421 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
e901acd6
JF		 4422 ixgbe_set_fdir_queues(adapter);
4423 else
4424 ixgbe_set_rss_queues(adapter);
e5b64635 4425 }
03ecf91a 4426
e901acd6
JF		 4427 /* adding FCoE rx rings to the end */
4428 f->mask = adapter->num_rx_queues;
4429 adapter->num_rx_queues += f->indices;
4430 adapter->num_tx_queues += f->indices;
0331a832 4431
e5b64635
JF		 4432 return true;
4433}
4434#endif /* IXGBE_FCOE */
4435
e901acd6
JF		 4436/* Artificial max queue cap per traffic class in DCB mode */
4437#define DCB_QUEUE_CAP 8
4438
e5b64635
JF		 4439#ifdef CONFIG_IXGBE_DCB
4440static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4441{
e901acd6
JF		 4442 int per_tc_q, q, i, offset = 0;
4443 struct net_device *dev = adapter->netdev;
4444 int tcs = netdev_get_num_tc(dev);
e5b64635 4445
e901acd6
JF		 4446 if (!tcs)
4447 return false;
e5b64635 4448
e901acd6
JF		 4449 /* Map queue offset and counts onto allocated tx queues */
4450 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4451 q = min((int)num_online_cpus(), per_tc_q);
8b1c0b24 4452
8b1c0b24 4453 for (i = 0; i < tcs; i++) {
e901acd6
JF		 4454 netdev_set_tc_queue(dev, i, q, offset);
4455 offset += q;
0331a832
YZ		 4456 }
4457
e901acd6
JF		 4458 adapter->num_tx_queues = q * tcs;
4459 adapter->num_rx_queues = q * tcs;
e5b64635
JF		 4460
4461#ifdef IXGBE_FCOE
e901acd6
JF		 4462 /* FCoE enabled queues require special configuration indexed
4463 * by feature specific indices and mask. Here we map FCoE
4464 * indices onto the DCB queue pairs allowing FCoE to own
4465 * configuration later.
e5b64635 4466 */
e901acd6
JF		 4467 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4468 int tc;
4469 struct ixgbe_ring_feature *f =
4470 &adapter->ring_feature[RING_F_FCOE];
4471
4472 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4473 f->indices = dev->tc_to_txq[tc].count;
4474 f->mask = dev->tc_to_txq[tc].offset;
4475 }
e5b64635
JF		 4476#endif
4477
e901acd6 4478 return true;
0331a832 4479}
e5b64635 4480#endif
0331a832 4481
1cdd1ec8
GR		 4482/**
4483 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4484 * @adapter: board private structure to initialize
4485 *
4486 * IOV doesn't actually use anything, so just NAK the
4487 * request for now and let the other queue routines
4488 * figure out what to do.
4489 */
4490static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4491{
4492 return false;
4493}
4494
4df10466 4495/*
25985edc 4496 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4df10466
JB		 4497 * @adapter: board private structure to initialize
4498 *
4499 * This is the top level queue allocation routine. The order here is very
4500 * important, starting with the "most" number of features turned on at once,
4501 * and ending with the smallest set of features. This way large combinations
4502 * can be allocated if they're turned on, and smaller combinations are the
4503 * fallthrough conditions.
4504 *
4505 **/
847f53ff 4506static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
bc97114d 4507{
1cdd1ec8
GR		 4508 /* Start with base case */
4509 adapter->num_rx_queues = 1;
4510 adapter->num_tx_queues = 1;
4511 adapter->num_rx_pools = adapter->num_rx_queues;
4512 adapter->num_rx_queues_per_pool = 1;
4513
4514 if (ixgbe_set_sriov_queues(adapter))
847f53ff 4515 goto done;
1cdd1ec8 4516
bc97114d
PWJ		 4517#ifdef CONFIG_IXGBE_DCB
4518 if (ixgbe_set_dcb_queues(adapter))
af22ab1b 4519 goto done;
bc97114d
PWJ		 4520
4521#endif
e5b64635
JF		 4522#ifdef IXGBE_FCOE
4523 if (ixgbe_set_fcoe_queues(adapter))
4524 goto done;
4525
4526#endif /* IXGBE_FCOE */
c4cf55e5
PWJ		 4527 if (ixgbe_set_fdir_queues(adapter))
4528 goto done;
4529
bc97114d 4530 if (ixgbe_set_rss_queues(adapter))
af22ab1b
WF		 4531 goto done;
4532
4533 /* fallback to base case */
4534 adapter->num_rx_queues = 1;
4535 adapter->num_tx_queues = 1;
4536
4537done:
9d837ea2
YZ		 4538 if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) ||
4539 (adapter->netdev->reg_state == NETREG_UNREGISTERING))
4540 return 0;
4541
847f53ff 4542 /* Notify the stack of the (possibly) reduced queue counts. */
f0796d5c 4543 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
847f53ff
BH		 4544 return netif_set_real_num_rx_queues(adapter->netdev,
4545 adapter->num_rx_queues);
b9804972
JB		 4546}
4547
021230d4 4548static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
e8e9f696 4549 int vectors)
021230d4
AV		 4550{
4551 int err, vector_threshold;
4552
4553 /* We'll want at least 3 (vector_threshold):
4554 * 1) TxQ[0] Cleanup
4555 * 2) RxQ[0] Cleanup
4556 * 3) Other (Link Status Change, etc.)
4557 * 4) TCP Timer (optional)
4558 */
4559 vector_threshold = MIN_MSIX_COUNT;
4560
4561 /* The more we get, the more we will assign to Tx/Rx Cleanup
4562 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4563 * Right now, we simply care about how many we'll get; we'll
4564 * set them up later while requesting irq's.
4565 */
4566 while (vectors >= vector_threshold) {
4567 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
e8e9f696 4568 vectors);
021230d4
AV		 4569 if (!err) /* Success in acquiring all requested vectors. */
4570 break;
4571 else if (err < 0)
4572 vectors = 0; /* Nasty failure, quit now */
4573 else /* err == number of vectors we should try again with */
4574 vectors = err;
4575 }
4576
4577 if (vectors < vector_threshold) {
4578 /* Can't allocate enough MSI-X interrupts? Oh well.
4579 * This just means we'll go with either a single MSI
4580 * vector or fall back to legacy interrupts.
4581 */
849c4542
ET		 4582 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4583 "Unable to allocate MSI-X interrupts\n");
021230d4
AV		 4584 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4585 kfree(adapter->msix_entries);
4586 adapter->msix_entries = NULL;
021230d4
AV		 4587 } else {
4588 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
eb7f139c
PWJ		 4589 /*
4590 * Adjust for only the vectors we'll use, which is minimum
4591 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4592 * vectors we were allocated.
4593 */
4594 adapter->num_msix_vectors = min(vectors,
e8e9f696 4595 adapter->max_msix_q_vectors + NON_Q_VECTORS);
021230d4
AV		 4596 }
4597}
4598
021230d4 4599/**
bc97114d 4600 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
021230d4
AV		 4601 * @adapter: board private structure to initialize
4602 *
bc97114d
PWJ		 4603 * Cache the descriptor ring offsets for RSS to the assigned rings.
4604 *
021230d4 4605 **/
bc97114d 4606static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
021230d4 4607{
bc97114d 4608 int i;
bc97114d 4609
9d6b758f
AD		 4610 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4611 return false;
bc97114d 4612
9d6b758f
AD		 4613 for (i = 0; i < adapter->num_rx_queues; i++)
4614 adapter->rx_ring[i]->reg_idx = i;
4615 for (i = 0; i < adapter->num_tx_queues; i++)
4616 adapter->tx_ring[i]->reg_idx = i;
4617
4618 return true;
bc97114d
PWJ		 4619}
4620
4621#ifdef CONFIG_IXGBE_DCB
e5b64635
JF		 4622
4623/* ixgbe_get_first_reg_idx - Return first register index associated with ring */
b32c8dcc
JF		 4624static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4625 unsigned int *tx, unsigned int *rx)
e5b64635
JF		 4626{
4627 struct net_device *dev = adapter->netdev;
4628 struct ixgbe_hw *hw = &adapter->hw;
4629 u8 num_tcs = netdev_get_num_tc(dev);
4630
4631 *tx = 0;
4632 *rx = 0;
4633
4634 switch (hw->mac.type) {
4635 case ixgbe_mac_82598EB:
aba70d5e
JF		 4636 *tx = tc << 2;
4637 *rx = tc << 3;
e5b64635
JF		 4638 break;
4639 case ixgbe_mac_82599EB:
4640 case ixgbe_mac_X540:
4fa2e0e1 4641 if (num_tcs > 4) {
e5b64635
JF		 4642 if (tc < 3) {
4643 *tx = tc << 5;
4644 *rx = tc << 4;
4645 } else if (tc < 5) {
4646 *tx = ((tc + 2) << 4);
4647 *rx = tc << 4;
4648 } else if (tc < num_tcs) {
4649 *tx = ((tc + 8) << 3);
4650 *rx = tc << 4;
4651 }
4fa2e0e1 4652 } else {
e5b64635
JF		 4653 *rx = tc << 5;
4654 switch (tc) {
4655 case 0:
4656 *tx = 0;
4657 break;
4658 case 1:
4659 *tx = 64;
4660 break;
4661 case 2:
4662 *tx = 96;
4663 break;
4664 case 3:
4665 *tx = 112;
4666 break;
4667 default:
4668 break;
4669 }
4670 }
4671 break;
4672 default:
4673 break;
4674 }
4675}
4676
bc97114d
PWJ		 4677/**
4678 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4679 * @adapter: board private structure to initialize
4680 *
4681 * Cache the descriptor ring offsets for DCB to the assigned rings.
4682 *
4683 **/
4684static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4685{
e5b64635
JF		 4686 struct net_device *dev = adapter->netdev;
4687 int i, j, k;
4688 u8 num_tcs = netdev_get_num_tc(dev);
bc97114d 4689
8b1c0b24 4690 if (!num_tcs)
bd508178 4691 return false;
f92ef202 4692
e5b64635
JF		 4693 for (i = 0, k = 0; i < num_tcs; i++) {
4694 unsigned int tx_s, rx_s;
4695 u16 count = dev->tc_to_txq[i].count;
4696
4697 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4698 for (j = 0; j < count; j++, k++) {
4699 adapter->tx_ring[k]->reg_idx = tx_s + j;
4700 adapter->rx_ring[k]->reg_idx = rx_s + j;
4701 adapter->tx_ring[k]->dcb_tc = i;
4702 adapter->rx_ring[k]->dcb_tc = i;
021230d4 4703 }
021230d4 4704 }
e5b64635
JF		 4705
4706 return true;
bc97114d
PWJ		 4707}
4708#endif
4709
c4cf55e5
PWJ		 4710/**
4711 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4712 * @adapter: board private structure to initialize
4713 *
4714 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4715 *
4716 **/
e8e9f696 4717static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
c4cf55e5
PWJ		 4718{
4719 int i;
4720 bool ret = false;
4721
03ecf91a
AD		 4722 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4723 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
c4cf55e5 4724 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 4725 adapter->rx_ring[i]->reg_idx = i;
c4cf55e5 4726 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 4727 adapter->tx_ring[i]->reg_idx = i;
c4cf55e5
PWJ		 4728 ret = true;
4729 }
4730
4731 return ret;
4732}
4733
0331a832
YZ		 4734#ifdef IXGBE_FCOE
4735/**
4736 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4737 * @adapter: board private structure to initialize
4738 *
4739 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4740 *
4741 */
4742static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4743{
0331a832 4744 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
bf29ee6c
AD		 4745 int i;
4746 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4747
4748 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4749 return false;
0331a832 4750
bf29ee6c 4751 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
03ecf91a 4752 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
bf29ee6c
AD		 4753 ixgbe_cache_ring_fdir(adapter);
4754 else
4755 ixgbe_cache_ring_rss(adapter);
8faa2a78 4756
bf29ee6c
AD		 4757 fcoe_rx_i = f->mask;
4758 fcoe_tx_i = f->mask;
0331a832 4759 }
bf29ee6c
AD		 4760 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4761 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4762 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4763 }
4764 return true;
0331a832
YZ		 4765}
4766
4767#endif /* IXGBE_FCOE */
1cdd1ec8
GR		 4768/**
4769 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4770 * @adapter: board private structure to initialize
4771 *
4772 * SR-IOV doesn't use any descriptor rings but changes the default if
4773 * no other mapping is used.
4774 *
4775 */
4776static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4777{
4a0b9ca0
PW		 4778 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4779 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
1cdd1ec8
GR		 4780 if (adapter->num_vfs)
4781 return true;
4782 else
4783 return false;
4784}
4785
bc97114d
PWJ		 4786/**
4787 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4788 * @adapter: board private structure to initialize
4789 *
4790 * Once we know the feature-set enabled for the device, we'll cache
4791 * the register offset the descriptor ring is assigned to.
4792 *
4793 * Note, the order the various feature calls is important. It must start with
4794 * the "most" features enabled at the same time, then trickle down to the
4795 * least amount of features turned on at once.
4796 **/
4797static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4798{
4799 /* start with default case */
4a0b9ca0
PW		 4800 adapter->rx_ring[0]->reg_idx = 0;
4801 adapter->tx_ring[0]->reg_idx = 0;
bc97114d 4802
1cdd1ec8
GR		 4803 if (ixgbe_cache_ring_sriov(adapter))
4804 return;
4805
e5b64635
JF		 4806#ifdef CONFIG_IXGBE_DCB
4807 if (ixgbe_cache_ring_dcb(adapter))
4808 return;
4809#endif
4810
0331a832
YZ		 4811#ifdef IXGBE_FCOE
4812 if (ixgbe_cache_ring_fcoe(adapter))
4813 return;
0331a832 4814#endif /* IXGBE_FCOE */
bc97114d 4815
c4cf55e5
PWJ		 4816 if (ixgbe_cache_ring_fdir(adapter))
4817 return;
4818
bc97114d
PWJ		 4819 if (ixgbe_cache_ring_rss(adapter))
4820 return;
021230d4
AV		 4821}
4822
9a799d71
AK		 4823/**
4824 * ixgbe_alloc_queues - Allocate memory for all rings
4825 * @adapter: board private structure to initialize
4826 *
4827 * We allocate one ring per queue at run-time since we don't know the
4df10466
JB		 4828 * number of queues at compile-time. The polling_netdev array is
4829 * intended for Multiqueue, but should work fine with a single queue.
9a799d71 4830 **/
2f90b865 4831static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
9a799d71 4832{
e2ddeba9 4833 int rx = 0, tx = 0, nid = adapter->node;
9a799d71 4834
e2ddeba9
ED		 4835 if (nid < 0 || !node_online(nid))
4836 nid = first_online_node;
4837
4838 for (; tx < adapter->num_tx_queues; tx++) {
4839 struct ixgbe_ring *ring;
4840
4841 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4842 if (!ring)
e2ddeba9 4843 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4844 if (!ring)
e2ddeba9 4845 goto err_allocation;
4a0b9ca0 4846 ring->count = adapter->tx_ring_count;
e2ddeba9
ED		 4847 ring->queue_index = tx;
4848 ring->numa_node = nid;
b6ec895e 4849 ring->dev = &adapter->pdev->dev;
fc77dc3c 4850 ring->netdev = adapter->netdev;
4a0b9ca0 4851
e2ddeba9 4852 adapter->tx_ring[tx] = ring;
021230d4 4853 }
b9804972 4854
e2ddeba9
ED		 4855 for (; rx < adapter->num_rx_queues; rx++) {
4856 struct ixgbe_ring *ring;
4a0b9ca0 4857
e2ddeba9 4858 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4a0b9ca0 4859 if (!ring)
e2ddeba9 4860 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4a0b9ca0 4861 if (!ring)
e2ddeba9
ED		 4862 goto err_allocation;
4863 ring->count = adapter->rx_ring_count;
4864 ring->queue_index = rx;
4865 ring->numa_node = nid;
b6ec895e 4866 ring->dev = &adapter->pdev->dev;
fc77dc3c 4867 ring->netdev = adapter->netdev;
4a0b9ca0 4868
8a0da21b
AD		 4869 /*
4870 * 82599 errata, UDP frames with a 0 checksum can be marked as
4871 * checksum errors.
4872 */
4873 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
4874 set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state);
4875
e2ddeba9 4876 adapter->rx_ring[rx] = ring;
021230d4
AV		 4877 }
4878
4879 ixgbe_cache_ring_register(adapter);
4880
4881 return 0;
4882
e2ddeba9
ED		 4883err_allocation:
4884 while (tx)
4885 kfree(adapter->tx_ring[--tx]);
4886
4887 while (rx)
4888 kfree(adapter->rx_ring[--rx]);
021230d4
AV		 4889 return -ENOMEM;
4890}
4891
4892/**
4893 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4894 * @adapter: board private structure to initialize
4895 *
4896 * Attempt to configure the interrupts using the best available
4897 * capabilities of the hardware and the kernel.
4898 **/
feea6a57 4899static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4 4900{
8be0e467 4901 struct ixgbe_hw *hw = &adapter->hw;
021230d4
AV		 4902 int err = 0;
4903 int vector, v_budget;
4904
4905 /*
4906 * It's easy to be greedy for MSI-X vectors, but it really
4907 * doesn't do us much good if we have a lot more vectors
4908 * than CPU's. So let's be conservative and only ask for
342bde1b 4909 * (roughly) the same number of vectors as there are CPU's.
021230d4
AV		 4910 */
4911 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
e8e9f696 4912 (int)num_online_cpus()) + NON_Q_VECTORS;
021230d4
AV		 4913
4914 /*
4915 * At the same time, hardware can only support a maximum of
8be0e467
PW		 4916 * hw.mac->max_msix_vectors vectors. With features
4917 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4918 * descriptor queues supported by our device. Thus, we cap it off in
4919 * those rare cases where the cpu count also exceeds our vector limit.
021230d4 4920 */
8be0e467 4921 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
021230d4
AV		 4922
4923 /* A failure in MSI-X entry allocation isn't fatal, but it does
4924 * mean we disable MSI-X capabilities of the adapter. */
4925 adapter->msix_entries = kcalloc(v_budget,
e8e9f696 4926 sizeof(struct msix_entry), GFP_KERNEL);
7a921c93
AD		 4927 if (adapter->msix_entries) {
4928 for (vector = 0; vector < v_budget; vector++)
4929 adapter->msix_entries[vector].entry = vector;
021230d4 4930
7a921c93 4931 ixgbe_acquire_msix_vectors(adapter, v_budget);
021230d4 4932
7a921c93
AD		 4933 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4934 goto out;
4935 }
26d27844 4936
7a921c93
AD		 4937 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4938 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
03ecf91a 4939 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
45b9f509 4940 e_err(probe,
03ecf91a 4941 "ATR is not supported while multiple "
45b9f509
AD		 4942 "queues are disabled. Disabling Flow Director\n");
4943 }
c4cf55e5 4944 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
c4cf55e5 4945 adapter->atr_sample_rate = 0;
1cdd1ec8
GR		 4946 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4947 ixgbe_disable_sriov(adapter);
4948
847f53ff
BH		 4949 err = ixgbe_set_num_queues(adapter);
4950 if (err)
4951 return err;
021230d4 4952
021230d4
AV		 4953 err = pci_enable_msi(adapter->pdev);
4954 if (!err) {
4955 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4956 } else {
849c4542
ET		 4957 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4958 "Unable to allocate MSI interrupt, "
4959 "falling back to legacy. Error: %d\n", err);
021230d4
AV		 4960 /* reset err */
4961 err = 0;
4962 }
4963
4964out:
021230d4
AV		 4965 return err;
4966}
4967
7a921c93
AD		 4968/**
4969 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4970 * @adapter: board private structure to initialize
4971 *
4972 * We allocate one q_vector per queue interrupt. If allocation fails we
4973 * return -ENOMEM.
4974 **/
4975static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4976{
4ff7fb12 4977 int v_idx, num_q_vectors;
7a921c93 4978 struct ixgbe_q_vector *q_vector;
7a921c93 4979
4ff7fb12 4980 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 4981 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4ff7fb12 4982 else
7a921c93 4983 num_q_vectors = 1;
7a921c93 4984
4ff7fb12 4985 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
1a6c14a2 4986 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
e8e9f696 4987 GFP_KERNEL, adapter->node);
1a6c14a2
JB		 4988 if (!q_vector)
4989 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
e8e9f696 4990 GFP_KERNEL);
7a921c93
AD		 4991 if (!q_vector)
4992 goto err_out;
4ff7fb12 4993
7a921c93 4994 q_vector->adapter = adapter;
4ff7fb12
AD		 4995 q_vector->v_idx = v_idx;
4996
207867f5
AD		 4997 /* Allocate the affinity_hint cpumask, configure the mask */
4998 if (!alloc_cpumask_var(&q_vector->affinity_mask, GFP_KERNEL))
4999 goto err_out;
5000 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
4ff7fb12
AD		 5001 netif_napi_add(adapter->netdev, &q_vector->napi,
5002 ixgbe_poll, 64);
5003 adapter->q_vector[v_idx] = q_vector;
7a921c93
AD		 5004 }
5005
5006 return 0;
5007
5008err_out:
4ff7fb12
AD		 5009 while (v_idx) {
5010 v_idx--;
5011 q_vector = adapter->q_vector[v_idx];
7a921c93 5012 netif_napi_del(&q_vector->napi);
207867f5 5013 free_cpumask_var(q_vector->affinity_mask);
7a921c93 5014 kfree(q_vector);
4ff7fb12 5015 adapter->q_vector[v_idx] = NULL;
7a921c93
AD		 5016 }
5017 return -ENOMEM;
5018}
5019
5020/**
5021 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5022 * @adapter: board private structure to initialize
5023 *
5024 * This function frees the memory allocated to the q_vectors. In addition if
5025 * NAPI is enabled it will delete any references to the NAPI struct prior
5026 * to freeing the q_vector.
5027 **/
5028static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
5029{
207867f5 5030 int v_idx, num_q_vectors;
7a921c93 5031
91281fd3 5032 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
7a921c93 5033 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
91281fd3 5034 else
7a921c93 5035 num_q_vectors = 1;
7a921c93 5036
207867f5
AD		 5037 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
5038 struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx];
5039 adapter->q_vector[v_idx] = NULL;
91281fd3 5040 netif_napi_del(&q_vector->napi);
207867f5 5041 free_cpumask_var(q_vector->affinity_mask);
7a921c93
AD		 5042 kfree(q_vector);
5043 }
5044}
5045
7b25cdba 5046static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
021230d4
AV		 5047{
5048 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5049 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5050 pci_disable_msix(adapter->pdev);
5051 kfree(adapter->msix_entries);
5052 adapter->msix_entries = NULL;
5053 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5054 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5055 pci_disable_msi(adapter->pdev);
5056 }
021230d4
AV		 5057}
5058
5059/**
5060 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5061 * @adapter: board private structure to initialize
5062 *
5063 * We determine which interrupt scheme to use based on...
5064 * - Kernel support (MSI, MSI-X)
5065 * - which can be user-defined (via MODULE_PARAM)
5066 * - Hardware queue count (num_*_queues)
5067 * - defined by miscellaneous hardware support/features (RSS, etc.)
5068 **/
2f90b865 5069int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
021230d4
AV		 5070{
5071 int err;
5072
5073 /* Number of supported queues */
847f53ff
BH		 5074 err = ixgbe_set_num_queues(adapter);
5075 if (err)
5076 return err;
021230d4 5077
021230d4
AV		 5078 err = ixgbe_set_interrupt_capability(adapter);
5079 if (err) {
849c4542 5080 e_dev_err("Unable to setup interrupt capabilities\n");
021230d4 5081 goto err_set_interrupt;
9a799d71
AK		 5082 }
5083
7a921c93
AD		 5084 err = ixgbe_alloc_q_vectors(adapter);
5085 if (err) {
849c4542 5086 e_dev_err("Unable to allocate memory for queue vectors\n");
7a921c93
AD		 5087 goto err_alloc_q_vectors;
5088 }
5089
5090 err = ixgbe_alloc_queues(adapter);
5091 if (err) {
849c4542 5092 e_dev_err("Unable to allocate memory for queues\n");
7a921c93
AD		 5093 goto err_alloc_queues;
5094 }
5095
849c4542 5096 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
396e799c
ET		 5097 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5098 adapter->num_rx_queues, adapter->num_tx_queues);
021230d4
AV		 5099
5100 set_bit(__IXGBE_DOWN, &adapter->state);
5101
9a799d71 5102 return 0;
021230d4 5103
7a921c93
AD		 5104err_alloc_queues:
5105 ixgbe_free_q_vectors(adapter);
5106err_alloc_q_vectors:
5107 ixgbe_reset_interrupt_capability(adapter);
021230d4 5108err_set_interrupt:
7a921c93
AD		 5109 return err;
5110}
5111
5112/**
5113 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5114 * @adapter: board private structure to clear interrupt scheme on
5115 *
5116 * We go through and clear interrupt specific resources and reset the structure
5117 * to pre-load conditions
5118 **/
5119void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5120{
4a0b9ca0
PW		 5121 int i;
5122
5123 for (i = 0; i < adapter->num_tx_queues; i++) {
5124 kfree(adapter->tx_ring[i]);
5125 adapter->tx_ring[i] = NULL;
5126 }
5127 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b
ED		 5128 struct ixgbe_ring *ring = adapter->rx_ring[i];
5129
5130 /* ixgbe_get_stats64() might access this ring, we must wait
5131 * a grace period before freeing it.
5132 */
bcec8b65 5133 kfree_rcu(ring, rcu);
4a0b9ca0
PW		 5134 adapter->rx_ring[i] = NULL;
5135 }
7a921c93 5136
b8eb3a10
DS		 5137 adapter->num_tx_queues = 0;
5138 adapter->num_rx_queues = 0;
5139
7a921c93
AD		 5140 ixgbe_free_q_vectors(adapter);
5141 ixgbe_reset_interrupt_capability(adapter);
9a799d71
AK		 5142}
5143
5144/**
5145 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5146 * @adapter: board private structure to initialize
5147 *
5148 * ixgbe_sw_init initializes the Adapter private data structure.
5149 * Fields are initialized based on PCI device information and
5150 * OS network device settings (MTU size).
5151 **/
5152static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5153{
5154 struct ixgbe_hw *hw = &adapter->hw;
5155 struct pci_dev *pdev = adapter->pdev;
021230d4 5156 unsigned int rss;
7a6b6f51 5157#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5158 int j;
5159 struct tc_configuration *tc;
5160#endif
021230d4 5161
c44ade9e
JB		 5162 /* PCI config space info */
5163
5164 hw->vendor_id = pdev->vendor;
5165 hw->device_id = pdev->device;
5166 hw->revision_id = pdev->revision;
5167 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5168 hw->subsystem_device_id = pdev->subsystem_device;
5169
021230d4
AV		 5170 /* Set capability flags */
5171 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5172 adapter->ring_feature[RING_F_RSS].indices = rss;
5173 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
bd508178
AD		 5174 switch (hw->mac.type) {
5175 case ixgbe_mac_82598EB:
bf069c97
DS		 5176 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5177 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
e8e26350 5178 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
bd508178 5179 break;
b93a2226 5180 case ixgbe_mac_X540:
4f51bf70
JK		 5181 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5182 case ixgbe_mac_82599EB:
e8e26350 5183 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
0c19d6af
PWJ		 5184 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5185 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
119fc60a
MC		 5186 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5187 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
45b9f509
AD		 5188 /* Flow Director hash filters enabled */
5189 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5190 adapter->atr_sample_rate = 20;
c4cf55e5 5191 adapter->ring_feature[RING_F_FDIR].indices =
e8e9f696 5192 IXGBE_MAX_FDIR_INDICES;
c04f6ca8 5193 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
eacd73f7 5194#ifdef IXGBE_FCOE
0d551589
YZ		 5195 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5196 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5197 adapter->ring_feature[RING_F_FCOE].indices = 0;
61a0f421 5198#ifdef CONFIG_IXGBE_DCB
6ee16520 5199 /* Default traffic class to use for FCoE */
56075a98 5200 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
61a0f421 5201#endif
eacd73f7 5202#endif /* IXGBE_FCOE */
bd508178
AD		 5203 break;
5204 default:
5205 break;
f8212f97 5206 }
2f90b865 5207
1fc5f038
AD		 5208 /* n-tuple support exists, always init our spinlock */
5209 spin_lock_init(&adapter->fdir_perfect_lock);
5210
7a6b6f51 5211#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5212 switch (hw->mac.type) {
5213 case ixgbe_mac_X540:
5214 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5215 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5216 break;
5217 default:
5218 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5219 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5220 break;
5221 }
5222
2f90b865
AD		 5223 /* Configure DCB traffic classes */
5224 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5225 tc = &adapter->dcb_cfg.tc_config[j];
5226 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5227 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5228 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5229 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5230 tc->dcb_pfc = pfc_disabled;
5231 }
4de2a022
JF		 5232
5233 /* Initialize default user to priority mapping, UPx->TC0 */
5234 tc = &adapter->dcb_cfg.tc_config[0];
5235 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5236 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5237
2f90b865
AD		 5238 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5239 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5240 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5241 adapter->dcb_set_bitmap = 0x00;
3032309b 5242 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
2f90b865 5243 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
e5b64635 5244 MAX_TRAFFIC_CLASS);
2f90b865
AD		 5245
5246#endif
9a799d71
AK		 5247
5248 /* default flow control settings */
cd7664f6 5249 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5250 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
264857b8
PWJ		 5251#ifdef CONFIG_DCB
5252 adapter->last_lfc_mode = hw->fc.current_mode;
5253#endif
9da712d2 5254 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5255 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5256 hw->fc.send_xon = true;
71fd570b 5257 hw->fc.disable_fc_autoneg = false;
9a799d71 5258
30efa5a3 5259 /* enable itr by default in dynamic mode */
f7554a2b 5260 adapter->rx_itr_setting = 1;
f7554a2b 5261 adapter->tx_itr_setting = 1;
30efa5a3
JB		 5262
5263 /* set defaults for eitr in MegaBytes */
5264 adapter->eitr_low = 10;
5265 adapter->eitr_high = 20;
5266
5267 /* set default ring sizes */
5268 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5269 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5270
bd198058 5271 /* set default work limits */
59224555 5272 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5273
9a799d71 5274 /* initialize eeprom parameters */
c44ade9e 5275 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5276 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5277 return -EIO;
5278 }
5279
1a6c14a2
JB		 5280 /* get assigned NUMA node */
5281 adapter->node = dev_to_node(&pdev->dev);
5282
9a799d71
AK		 5283 set_bit(__IXGBE_DOWN, &adapter->state);
5284
5285 return 0;
5286}
5287
5288/**
5289 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5290 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5291 *
5292 * Return 0 on success, negative on failure
5293 **/
b6ec895e 5294int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5295{
b6ec895e 5296 struct device *dev = tx_ring->dev;
9a799d71
AK		 5297 int size;
5298
3a581073 5299 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
89bf67f1 5300 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
1a6c14a2 5301 if (!tx_ring->tx_buffer_info)
89bf67f1 5302 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5303 if (!tx_ring->tx_buffer_info)
5304 goto err;
9a799d71
AK		 5305
5306 /* round up to nearest 4K */
12207e49 5307 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5308 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5309
b6ec895e 5310 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1b507730 5311 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5312 if (!tx_ring->desc)
5313 goto err;
9a799d71 5314
3a581073
JB		 5315 tx_ring->next_to_use = 0;
5316 tx_ring->next_to_clean = 0;
9a799d71 5317 return 0;
e01c31a5
JB		 5318
5319err:
5320 vfree(tx_ring->tx_buffer_info);
5321 tx_ring->tx_buffer_info = NULL;
b6ec895e 5322 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5323 return -ENOMEM;
9a799d71
AK		 5324}
5325
69888674
AD		 5326/**
5327 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5328 * @adapter: board private structure
5329 *
5330 * If this function returns with an error, then it's possible one or
5331 * more of the rings is populated (while the rest are not). It is the
5332 * callers duty to clean those orphaned rings.
5333 *
5334 * Return 0 on success, negative on failure
5335 **/
5336static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5337{
5338 int i, err = 0;
5339
5340 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5341 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5342 if (!err)
5343 continue;
396e799c 5344 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
69888674
AD		 5345 break;
5346 }
5347
5348 return err;
5349}
5350
9a799d71
AK		 5351/**
5352 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5353 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5354 *
5355 * Returns 0 on success, negative on failure
5356 **/
b6ec895e 5357int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5358{
b6ec895e 5359 struct device *dev = rx_ring->dev;
021230d4 5360 int size;
9a799d71 5361
3a581073 5362 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
89bf67f1 5363 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
1a6c14a2 5364 if (!rx_ring->rx_buffer_info)
89bf67f1 5365 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5366 if (!rx_ring->rx_buffer_info)
5367 goto err;
9a799d71 5368
9a799d71 5369 /* Round up to nearest 4K */
3a581073
JB		 5370 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5371 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5372
b6ec895e 5373 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1b507730 5374 &rx_ring->dma, GFP_KERNEL);
9a799d71 5375
b6ec895e
AD		 5376 if (!rx_ring->desc)
5377 goto err;
9a799d71 5378
3a581073
JB		 5379 rx_ring->next_to_clean = 0;
5380 rx_ring->next_to_use = 0;
9a799d71
AK		 5381
5382 return 0;
b6ec895e
AD		 5383err:
5384 vfree(rx_ring->rx_buffer_info);
5385 rx_ring->rx_buffer_info = NULL;
5386 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5387 return -ENOMEM;
9a799d71
AK		 5388}
5389
69888674
AD		 5390/**
5391 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5392 * @adapter: board private structure
5393 *
5394 * If this function returns with an error, then it's possible one or
5395 * more of the rings is populated (while the rest are not). It is the
5396 * callers duty to clean those orphaned rings.
5397 *
5398 * Return 0 on success, negative on failure
5399 **/
69888674
AD		 5400static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5401{
5402 int i, err = 0;
5403
5404 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5405 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5406 if (!err)
5407 continue;
396e799c 5408 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
69888674
AD		 5409 break;
5410 }
5411
5412 return err;
5413}
5414
9a799d71
AK		 5415/**
5416 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5417 * @tx_ring: Tx descriptor ring for a specific queue
5418 *
5419 * Free all transmit software resources
5420 **/
b6ec895e 5421void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5422{
b6ec895e 5423 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5424
5425 vfree(tx_ring->tx_buffer_info);
5426 tx_ring->tx_buffer_info = NULL;
5427
b6ec895e
AD		 5428 /* if not set, then don't free */
5429 if (!tx_ring->desc)
5430 return;
5431
5432 dma_free_coherent(tx_ring->dev, tx_ring->size,
5433 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5434
5435 tx_ring->desc = NULL;
5436}
5437
5438/**
5439 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5440 * @adapter: board private structure
5441 *
5442 * Free all transmit software resources
5443 **/
5444static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5445{
5446 int i;
5447
5448 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5449 if (adapter->tx_ring[i]->desc)
b6ec895e 5450 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5451}
5452
5453/**
b4617240 5454 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5455 * @rx_ring: ring to clean the resources from
5456 *
5457 * Free all receive software resources
5458 **/
b6ec895e 5459void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5460{
b6ec895e 5461 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5462
5463 vfree(rx_ring->rx_buffer_info);
5464 rx_ring->rx_buffer_info = NULL;
5465
b6ec895e
AD		 5466 /* if not set, then don't free */
5467 if (!rx_ring->desc)
5468 return;
5469
5470 dma_free_coherent(rx_ring->dev, rx_ring->size,
5471 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5472
5473 rx_ring->desc = NULL;
5474}
5475
5476/**
5477 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5478 * @adapter: board private structure
5479 *
5480 * Free all receive software resources
5481 **/
5482static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5483{
5484 int i;
5485
5486 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5487 if (adapter->rx_ring[i]->desc)
b6ec895e 5488 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5489}
5490
9a799d71
AK		 5491/**
5492 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5493 * @netdev: network interface device structure
5494 * @new_mtu: new value for maximum frame size
5495 *
5496 * Returns 0 on success, negative on failure
5497 **/
5498static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5499{
5500 struct ixgbe_adapter *adapter = netdev_priv(netdev);
16b61beb 5501 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 5502 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5503
42c783c5 5504 /* MTU < 68 is an error and causes problems on some kernels */
e9f98072
GR		 5505 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5506 hw->mac.type != ixgbe_mac_X540) {
5507 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5508 return -EINVAL;
5509 } else {
5510 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5511 return -EINVAL;
5512 }
9a799d71 5513
396e799c 5514 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
021230d4 5515 /* must set new MTU before calling down or up */
9a799d71
AK		 5516 netdev->mtu = new_mtu;
5517
d4f80882
AV		 5518 if (netif_running(netdev))
5519 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5520
5521 return 0;
5522}
5523
5524/**
5525 * ixgbe_open - Called when a network interface is made active
5526 * @netdev: network interface device structure
5527 *
5528 * Returns 0 on success, negative value on failure
5529 *
5530 * The open entry point is called when a network interface is made
5531 * active by the system (IFF_UP). At this point all resources needed
5532 * for transmit and receive operations are allocated, the interrupt
5533 * handler is registered with the OS, the watchdog timer is started,
5534 * and the stack is notified that the interface is ready.
5535 **/
5536static int ixgbe_open(struct net_device *netdev)
5537{
5538 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5539 int err;
4bebfaa5
AK		 5540
5541 /* disallow open during test */
5542 if (test_bit(__IXGBE_TESTING, &adapter->state))
5543 return -EBUSY;
9a799d71 5544
54386467
JB		 5545 netif_carrier_off(netdev);
5546
9a799d71
AK		 5547 /* allocate transmit descriptors */
5548 err = ixgbe_setup_all_tx_resources(adapter);
5549 if (err)
5550 goto err_setup_tx;
5551
9a799d71
AK		 5552 /* allocate receive descriptors */
5553 err = ixgbe_setup_all_rx_resources(adapter);
5554 if (err)
5555 goto err_setup_rx;
5556
5557 ixgbe_configure(adapter);
5558
021230d4 5559 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5560 if (err)
5561 goto err_req_irq;
5562
c7ccde0f 5563 ixgbe_up_complete(adapter);
9a799d71
AK		 5564
5565 return 0;
5566
9a799d71 5567err_req_irq:
9a799d71 5568err_setup_rx:
a20a1199 5569 ixgbe_free_all_rx_resources(adapter);
9a799d71 5570err_setup_tx:
a20a1199 5571 ixgbe_free_all_tx_resources(adapter);
9a799d71
AK		 5572 ixgbe_reset(adapter);
5573
5574 return err;
5575}
5576
5577/**
5578 * ixgbe_close - Disables a network interface
5579 * @netdev: network interface device structure
5580 *
5581 * Returns 0, this is not allowed to fail
5582 *
5583 * The close entry point is called when an interface is de-activated
5584 * by the OS. The hardware is still under the drivers control, but
5585 * needs to be disabled. A global MAC reset is issued to stop the
5586 * hardware, and all transmit and receive resources are freed.
5587 **/
5588static int ixgbe_close(struct net_device *netdev)
5589{
5590 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71
AK		 5591
5592 ixgbe_down(adapter);
5593 ixgbe_free_irq(adapter);
5594
e4911d57
AD		 5595 ixgbe_fdir_filter_exit(adapter);
5596
9a799d71
AK		 5597 ixgbe_free_all_tx_resources(adapter);
5598 ixgbe_free_all_rx_resources(adapter);
5599
5eba3699 5600 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5601
5602 return 0;
5603}
5604
b3c8b4ba
AD		 5605#ifdef CONFIG_PM
5606static int ixgbe_resume(struct pci_dev *pdev)
5607{
c60fbb00
AD		 5608 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5609 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5610 u32 err;
5611
5612 pci_set_power_state(pdev, PCI_D0);
5613 pci_restore_state(pdev);
656ab817
DS		 5614 /*
5615 * pci_restore_state clears dev->state_saved so call
5616 * pci_save_state to restore it.
5617 */
5618 pci_save_state(pdev);
9ce77666 5619
5620 err = pci_enable_device_mem(pdev);
b3c8b4ba 5621 if (err) {
849c4542 5622 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5623 return err;
5624 }
5625 pci_set_master(pdev);
5626
dd4d8ca6 5627 pci_wake_from_d3(pdev, false);
b3c8b4ba
AD		 5628
5629 err = ixgbe_init_interrupt_scheme(adapter);
5630 if (err) {
849c4542 5631 e_dev_err("Cannot initialize interrupts for device\n");
b3c8b4ba
AD		 5632 return err;
5633 }
5634
b3c8b4ba
AD		 5635 ixgbe_reset(adapter);
5636
495dce12
WJP		 5637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5638
b3c8b4ba 5639 if (netif_running(netdev)) {
c60fbb00 5640 err = ixgbe_open(netdev);
b3c8b4ba
AD		 5641 if (err)
5642 return err;
5643 }
5644
5645 netif_device_attach(netdev);
5646
5647 return 0;
5648}
b3c8b4ba 5649#endif /* CONFIG_PM */
9d8d05ae
RW		 5650
5651static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5652{
c60fbb00
AD		 5653 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5654 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5655 struct ixgbe_hw *hw = &adapter->hw;
5656 u32 ctrl, fctrl;
5657 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5658#ifdef CONFIG_PM
5659 int retval = 0;
5660#endif
5661
5662 netif_device_detach(netdev);
5663
5664 if (netif_running(netdev)) {
5665 ixgbe_down(adapter);
5666 ixgbe_free_irq(adapter);
5667 ixgbe_free_all_tx_resources(adapter);
5668 ixgbe_free_all_rx_resources(adapter);
5669 }
b3c8b4ba 5670
5f5ae6fc 5671 ixgbe_clear_interrupt_scheme(adapter);
d033d526
JF		 5672#ifdef CONFIG_DCB
5673 kfree(adapter->ixgbe_ieee_pfc);
5674 kfree(adapter->ixgbe_ieee_ets);
5675#endif
5f5ae6fc 5676
b3c8b4ba
AD		 5677#ifdef CONFIG_PM
5678 retval = pci_save_state(pdev);
5679 if (retval)
5680 return retval;
4df10466 5681
b3c8b4ba 5682#endif
e8e26350
PW		 5683 if (wufc) {
5684 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5685
e8e26350
PW		 5686 /* turn on all-multi mode if wake on multicast is enabled */
5687 if (wufc & IXGBE_WUFC_MC) {
5688 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5689 fctrl |= IXGBE_FCTRL_MPE;
5690 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5691 }
5692
5693 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5694 ctrl |= IXGBE_CTRL_GIO_DIS;
5695 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5696
5697 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5698 } else {
5699 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5700 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5701 }
5702
bd508178
AD		 5703 switch (hw->mac.type) {
5704 case ixgbe_mac_82598EB:
dd4d8ca6 5705 pci_wake_from_d3(pdev, false);
bd508178
AD		 5706 break;
5707 case ixgbe_mac_82599EB:
b93a2226 5708 case ixgbe_mac_X540:
bd508178
AD		 5709 pci_wake_from_d3(pdev, !!wufc);
5710 break;
5711 default:
5712 break;
5713 }
b3c8b4ba 5714
9d8d05ae
RW		 5715 *enable_wake = !!wufc;
5716
b3c8b4ba
AD		 5717 ixgbe_release_hw_control(adapter);
5718
5719 pci_disable_device(pdev);
5720
9d8d05ae
RW		 5721 return 0;
5722}
5723
5724#ifdef CONFIG_PM
5725static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5726{
5727 int retval;
5728 bool wake;
5729
5730 retval = __ixgbe_shutdown(pdev, &wake);
5731 if (retval)
5732 return retval;
5733
5734 if (wake) {
5735 pci_prepare_to_sleep(pdev);
5736 } else {
5737 pci_wake_from_d3(pdev, false);
5738 pci_set_power_state(pdev, PCI_D3hot);
5739 }
b3c8b4ba
AD		 5740
5741 return 0;
5742}
9d8d05ae 5743#endif /* CONFIG_PM */
b3c8b4ba
AD		 5744
5745static void ixgbe_shutdown(struct pci_dev *pdev)
5746{
9d8d05ae
RW		 5747 bool wake;
5748
5749 __ixgbe_shutdown(pdev, &wake);
5750
5751 if (system_state == SYSTEM_POWER_OFF) {
5752 pci_wake_from_d3(pdev, wake);
5753 pci_set_power_state(pdev, PCI_D3hot);
5754 }
b3c8b4ba
AD		 5755}
5756
9a799d71
AK		 5757/**
5758 * ixgbe_update_stats - Update the board statistics counters.
5759 * @adapter: board private structure
5760 **/
5761void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5762{
2d86f139 5763 struct net_device *netdev = adapter->netdev;
9a799d71 5764 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5765 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5766 u64 total_mpc = 0;
5767 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5768 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5769 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5770 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7b859ebc
AH		 5771#ifdef IXGBE_FCOE
5772 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5773 unsigned int cpu;
5774 u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0;
5775#endif /* IXGBE_FCOE */
9a799d71 5776
d08935c2
DS		 5777 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5778 test_bit(__IXGBE_RESETTING, &adapter->state))
5779 return;
5780
94b982b2 5781 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5782 u64 rsc_count = 0;
94b982b2 5783 u64 rsc_flush = 0;
d51019a4
PW		 5784 for (i = 0; i < 16; i++)
5785 adapter->hw_rx_no_dma_resources +=
7ca647bd 5786 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
94b982b2 5787 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5788 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5789 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5790 }
5791 adapter->rsc_total_count = rsc_count;
5792 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5793 }
5794
5b7da515
AD		 5795 for (i = 0; i < adapter->num_rx_queues; i++) {
5796 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5797 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5798 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5799 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5800 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5801 bytes += rx_ring->stats.bytes;
5802 packets += rx_ring->stats.packets;
5803 }
5804 adapter->non_eop_descs = non_eop_descs;
5805 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5806 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5807 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5808 netdev->stats.rx_bytes = bytes;
5809 netdev->stats.rx_packets = packets;
5810
5811 bytes = 0;
5812 packets = 0;
7ca3bc58 5813 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5814 for (i = 0; i < adapter->num_tx_queues; i++) {
5815 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5816 restart_queue += tx_ring->tx_stats.restart_queue;
5817 tx_busy += tx_ring->tx_stats.tx_busy;
5818 bytes += tx_ring->stats.bytes;
5819 packets += tx_ring->stats.packets;
5820 }
eb985f09 5821 adapter->restart_queue = restart_queue;
5b7da515
AD		 5822 adapter->tx_busy = tx_busy;
5823 netdev->stats.tx_bytes = bytes;
5824 netdev->stats.tx_packets = packets;
7ca3bc58 5825
7ca647bd 5826 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5827
5828 /* 8 register reads */
6f11eef7
AV		 5829 for (i = 0; i < 8; i++) {
5830 /* for packet buffers not used, the register should read 0 */
5831 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5832 missed_rx += mpc;
7ca647bd
JP		 5833 hwstats->mpc[i] += mpc;
5834 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5835 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5836 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5837 switch (hw->mac.type) {
5838 case ixgbe_mac_82598EB:
1a70db4b
ET		 5839 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5840 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5841 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5842 hwstats->pxonrxc[i] +=
5843 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5844 break;
5845 case ixgbe_mac_82599EB:
b93a2226 5846 case ixgbe_mac_X540:
bd508178
AD		 5847 hwstats->pxonrxc[i] +=
5848 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5849 break;
5850 default:
5851 break;
e8e26350 5852 }
6f11eef7 5853 }
1a70db4b
ET		 5854
5855 /*16 register reads */
5856 for (i = 0; i < 16; i++) {
5857 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5858 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5859 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5860 (hw->mac.type == ixgbe_mac_X540)) {
5861 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5862 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5863 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5864 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5865 }
5866 }
5867
7ca647bd 5868 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5869 /* work around hardware counting issue */
7ca647bd 5870 hwstats->gprc -= missed_rx;
6f11eef7 5871
c84d324c
JF		 5872 ixgbe_update_xoff_received(adapter);
5873
6f11eef7 5874 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5875 switch (hw->mac.type) {
5876 case ixgbe_mac_82598EB:
5877 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5878 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5879 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5880 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5881 break;
b93a2226 5882 case ixgbe_mac_X540:
58f6bcf9
ET		 5883 /* OS2BMC stats are X540 only*/
5884 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5885 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5886 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5887 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5888 case ixgbe_mac_82599EB:
7ca647bd 5889 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5890 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5891 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5892 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5893 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5894 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5895 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5896 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5897 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5898#ifdef IXGBE_FCOE
7ca647bd
JP		 5899 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5900 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5901 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5902 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5903 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5904 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc
AH		 5905 /* Add up per cpu counters for total ddp aloc fail */
5906 if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) {
5907 for_each_possible_cpu(cpu) {
5908 fcoe_noddp_counts_sum +=
5909 *per_cpu_ptr(fcoe->pcpu_noddp, cpu);
5910 fcoe_noddp_ext_buff_counts_sum +=
5911 *per_cpu_ptr(fcoe->
5912 pcpu_noddp_ext_buff, cpu);
5913 }
5914 }
5915 hwstats->fcoe_noddp = fcoe_noddp_counts_sum;
5916 hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum;
6d45522c 5917#endif /* IXGBE_FCOE */
bd508178
AD		 5918 break;
5919 default:
5920 break;
e8e26350 5921 }
9a799d71 5922 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5923 hwstats->bprc += bprc;
5924 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5925 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5926 hwstats->mprc -= bprc;
5927 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5928 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5929 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5930 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5931 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5932 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5933 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5934 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5935 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5936 hwstats->lxontxc += lxon;
6f11eef7 5937 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5938 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5939 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5940 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5941 /*
5942 * 82598 errata - tx of flow control packets is included in tx counters
5943 */
5944 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5945 hwstats->gptc -= xon_off_tot;
5946 hwstats->mptc -= xon_off_tot;
5947 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5948 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5949 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5950 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5951 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5952 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5953 hwstats->ptc64 -= xon_off_tot;
5954 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5955 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5956 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5957 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5958 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5959 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5960
5961 /* Fill out the OS statistics structure */
7ca647bd 5962 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5963
5964 /* Rx Errors */
7ca647bd 5965 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5966 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5967 netdev->stats.rx_length_errors = hwstats->rlec;
5968 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5969 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5970}
5971
5972/**
d034acf1
AD		 5973 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5974 * @adapter - pointer to the device adapter structure
9a799d71 5975 **/
d034acf1 5976static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5977{
cf8280ee 5978 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5979 int i;
cf8280ee 5980
d034acf1
AD		 5981 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5982 return;
5983
5984 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5985
d034acf1 5986 /* if interface is down do nothing */
fe49f04a 5987 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5988 return;
5989
5990 /* do nothing if we are not using signature filters */
5991 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5992 return;
5993
5994 adapter->fdir_overflow++;
5995
93c52dd0
AD		 5996 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5997 for (i = 0; i < adapter->num_tx_queues; i++)
5998 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5999 &(adapter->tx_ring[i]->state));
d034acf1
AD		 6000 /* re-enable flow director interrupts */
6001 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 6002 } else {
6003 e_err(probe, "failed to finish FDIR re-initialization, "
6004 "ignored adding FDIR ATR filters\n");
6005 }
93c52dd0
AD		 6006}
6007
6008/**
6009 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
6010 * @adapter - pointer to the device adapter structure
6011 *
6012 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 6013 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 6014 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 6015 * determine if a hang has occurred.
93c52dd0
AD		 6016 */
6017static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6018{
cf8280ee 6019 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6020 u64 eics = 0;
6021 int i;
cf8280ee 6022
93c52dd0
AD		 6023 /* If we're down or resetting, just bail */
6024 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6025 test_bit(__IXGBE_RESETTING, &adapter->state))
6026 return;
22d5a71b 6027
93c52dd0
AD		 6028 /* Force detection of hung controller */
6029 if (netif_carrier_ok(adapter->netdev)) {
6030 for (i = 0; i < adapter->num_tx_queues; i++)
6031 set_check_for_tx_hang(adapter->tx_ring[i]);
6032 }
22d5a71b 6033
fe49f04a
AD		 6034 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6035 /*
6036 * for legacy and MSI interrupts don't set any bits
6037 * that are enabled for EIAM, because this operation
6038 * would set *both* EIMS and EICS for any bit in EIAM
6039 */
6040 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6041 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6042 } else {
6043 /* get one bit for every active tx/rx interrupt vector */
6044 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
6045 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6046 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6047 eics |= ((u64)1 << i);
6048 }
cf8280ee 6049 }
9a799d71 6050
93c52dd0 6051 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6052 ixgbe_irq_rearm_queues(adapter, eics);
6053
cf8280ee
JB		 6054}
6055
e8e26350 6056/**
93c52dd0
AD		 6057 * ixgbe_watchdog_update_link - update the link status
6058 * @adapter - pointer to the device adapter structure
6059 * @link_speed - pointer to a u32 to store the link_speed
e8e26350 6060 **/
93c52dd0 6061static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6062{
e8e26350 6063 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6064 u32 link_speed = adapter->link_speed;
6065 bool link_up = adapter->link_up;
c4cf55e5 6066 int i;
e8e26350 6067
93c52dd0
AD		 6068 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6069 return;
6070
6071 if (hw->mac.ops.check_link) {
6072 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6073 } else {
93c52dd0
AD		 6074 /* always assume link is up, if no check link function */
6075 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6076 link_up = true;
c4cf55e5 6077 }
93c52dd0
AD		 6078 if (link_up) {
6079 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6080 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6081 hw->mac.ops.fc_enable(hw, i);
6082 } else {
6083 hw->mac.ops.fc_enable(hw, 0);
6084 }
6085 }
6086
6087 if (link_up ||
6088 time_after(jiffies, (adapter->link_check_timeout +
6089 IXGBE_TRY_LINK_TIMEOUT))) {
6090 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6091 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6092 IXGBE_WRITE_FLUSH(hw);
6093 }
6094
6095 adapter->link_up = link_up;
6096 adapter->link_speed = link_speed;
e8e26350
PW		 6097}
6098
6099/**
93c52dd0
AD		 6100 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6101 * print link up message
6102 * @adapter - pointer to the device adapter structure
e8e26350 6103 **/
93c52dd0 6104static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6105{
93c52dd0 6106 struct net_device *netdev = adapter->netdev;
e8e26350 6107 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6108 u32 link_speed = adapter->link_speed;
6109 bool flow_rx, flow_tx;
e8e26350 6110
93c52dd0
AD		 6111 /* only continue if link was previously down */
6112 if (netif_carrier_ok(netdev))
a985b6c3 6113 return;
63d6e1d8 6114
93c52dd0 6115 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6116
93c52dd0
AD		 6117 switch (hw->mac.type) {
6118 case ixgbe_mac_82598EB: {
6119 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6120 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6121 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6122 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6123 }
6124 break;
6125 case ixgbe_mac_X540:
6126 case ixgbe_mac_82599EB: {
6127 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6128 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6129 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6130 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6131 }
6132 break;
6133 default:
6134 flow_tx = false;
6135 flow_rx = false;
6136 break;
e8e26350 6137 }
93c52dd0
AD		 6138 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6139 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6140 "10 Gbps" :
6141 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6142 "1 Gbps" :
6143 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6144 "100 Mbps" :
6145 "unknown speed"))),
6146 ((flow_rx && flow_tx) ? "RX/TX" :
6147 (flow_rx ? "RX" :
6148 (flow_tx ? "TX" : "None"))));
e8e26350 6149
93c52dd0 6150 netif_carrier_on(netdev);
93c52dd0 6151 ixgbe_check_vf_rate_limit(adapter);
e8e26350
PW		 6152}
6153
c4cf55e5 6154/**
93c52dd0
AD		 6155 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6156 * print link down message
6157 * @adapter - pointer to the adapter structure
c4cf55e5 6158 **/
93c52dd0 6159static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
c4cf55e5 6160{
cf8280ee 6161 struct net_device *netdev = adapter->netdev;
c4cf55e5 6162 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6163
93c52dd0
AD		 6164 adapter->link_up = false;
6165 adapter->link_speed = 0;
cf8280ee 6166
93c52dd0
AD		 6167 /* only continue if link was up previously */
6168 if (!netif_carrier_ok(netdev))
6169 return;
264857b8 6170
93c52dd0
AD		 6171 /* poll for SFP+ cable when link is down */
6172 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6173 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6174
93c52dd0
AD		 6175 e_info(drv, "NIC Link is Down\n");
6176 netif_carrier_off(netdev);
6177}
e8e26350 6178
93c52dd0
AD		 6179/**
6180 * ixgbe_watchdog_flush_tx - flush queues on link down
6181 * @adapter - pointer to the device adapter structure
6182 **/
6183static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6184{
c4cf55e5 6185 int i;
93c52dd0 6186 int some_tx_pending = 0;
c4cf55e5 6187
93c52dd0 6188 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6189 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6190 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6191 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6192 some_tx_pending = 1;
6193 break;
6194 }
6195 }
6196
6197 if (some_tx_pending) {
6198 /* We've lost link, so the controller stops DMA,
6199 * but we've got queued Tx work that's never going
6200 * to get done, so reset controller to flush Tx.
6201 * (Do the reset outside of interrupt context).
6202 */
c83c6cbd 6203 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6204 }
c4cf55e5 6205 }
c4cf55e5
PWJ		 6206}
6207
a985b6c3
GR		 6208static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6209{
6210 u32 ssvpc;
6211
6212 /* Do not perform spoof check for 82598 */
6213 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6214 return;
6215
6216 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6217
6218 /*
6219 * ssvpc register is cleared on read, if zero then no
6220 * spoofed packets in the last interval.
6221 */
6222 if (!ssvpc)
6223 return;
6224
6225 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6226}
6227
93c52dd0
AD		 6228/**
6229 * ixgbe_watchdog_subtask - check and bring link up
6230 * @adapter - pointer to the device adapter structure
6231 **/
6232static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6233{
6234 /* if interface is down do nothing */
7edebf9a
ET		 6235 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6236 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6237 return;
6238
6239 ixgbe_watchdog_update_link(adapter);
6240
6241 if (adapter->link_up)
6242 ixgbe_watchdog_link_is_up(adapter);
6243 else
6244 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6245
a985b6c3 6246 ixgbe_spoof_check(adapter);
9a799d71 6247 ixgbe_update_stats(adapter);
93c52dd0
AD		 6248
6249 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6250}
10eec955 6251
cf8280ee 6252/**
7086400d
AD		 6253 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6254 * @adapter - the ixgbe adapter structure
cf8280ee 6255 **/
7086400d 6256static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6257{
cf8280ee 6258 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6259 s32 err;
cf8280ee 6260
7086400d
AD		 6261 /* not searching for SFP so there is nothing to do here */
6262 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6263 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6264 return;
10eec955 6265
7086400d
AD		 6266 /* someone else is in init, wait until next service event */
6267 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6268 return;
cf8280ee 6269
7086400d
AD		 6270 err = hw->phy.ops.identify_sfp(hw);
6271 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6272 goto sfp_out;
264857b8 6273
7086400d
AD		 6274 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6275 /* If no cable is present, then we need to reset
6276 * the next time we find a good cable. */
6277 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6278 }
9a799d71 6279
7086400d
AD		 6280 /* exit on error */
6281 if (err)
6282 goto sfp_out;
e8e26350 6283
7086400d
AD		 6284 /* exit if reset not needed */
6285 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6286 goto sfp_out;
9a799d71 6287
7086400d 6288 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6289
7086400d
AD		 6290 /*
6291 * A module may be identified correctly, but the EEPROM may not have
6292 * support for that module. setup_sfp() will fail in that case, so
6293 * we should not allow that module to load.
6294 */
6295 if (hw->mac.type == ixgbe_mac_82598EB)
6296 err = hw->phy.ops.reset(hw);
6297 else
6298 err = hw->mac.ops.setup_sfp(hw);
6299
6300 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6301 goto sfp_out;
6302
6303 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6304 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6305
6306sfp_out:
6307 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6308
6309 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6310 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6311 e_dev_err("failed to initialize because an unsupported "
6312 "SFP+ module type was detected.\n");
6313 e_dev_err("Reload the driver after installing a "
6314 "supported module.\n");
6315 unregister_netdev(adapter->netdev);
bc59fcda 6316 }
7086400d 6317}
bc59fcda 6318
7086400d
AD		 6319/**
6320 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6321 * @adapter - the ixgbe adapter structure
6322 **/
6323static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6324{
6325 struct ixgbe_hw *hw = &adapter->hw;
6326 u32 autoneg;
6327 bool negotiation;
6328
6329 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6330 return;
6331
6332 /* someone else is in init, wait until next service event */
6333 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6334 return;
6335
6336 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6337
6338 autoneg = hw->phy.autoneg_advertised;
6339 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6340 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
7086400d
AD		 6341 if (hw->mac.ops.setup_link)
6342 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6343
6344 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6345 adapter->link_check_timeout = jiffies;
6346 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6347}
6348
83c61fa9
GR		 6349#ifdef CONFIG_PCI_IOV
6350static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6351{
6352 int vf;
6353 struct ixgbe_hw *hw = &adapter->hw;
6354 struct net_device *netdev = adapter->netdev;
6355 u32 gpc;
6356 u32 ciaa, ciad;
6357
6358 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6359 if (gpc) /* If incrementing then no need for the check below */
6360 return;
6361 /*
6362 * Check to see if a bad DMA write target from an errant or
6363 * malicious VF has caused a PCIe error. If so then we can
6364 * issue a VFLR to the offending VF(s) and then resume without
6365 * requesting a full slot reset.
6366 */
6367
6368 for (vf = 0; vf < adapter->num_vfs; vf++) {
6369 ciaa = (vf << 16) | 0x80000000;
6370 /* 32 bit read so align, we really want status at offset 6 */
6371 ciaa |= PCI_COMMAND;
6372 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6373 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6374 ciaa &= 0x7FFFFFFF;
6375 /* disable debug mode asap after reading data */
6376 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6377 /* Get the upper 16 bits which will be the PCI status reg */
6378 ciad >>= 16;
6379 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6380 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6381 /* Issue VFLR */
6382 ciaa = (vf << 16) | 0x80000000;
6383 ciaa |= 0xA8;
6384 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6385 ciad = 0x00008000; /* VFLR */
6386 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6387 ciaa &= 0x7FFFFFFF;
6388 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6389 }
6390 }
6391}
6392
6393#endif
7086400d
AD		 6394/**
6395 * ixgbe_service_timer - Timer Call-back
6396 * @data: pointer to adapter cast into an unsigned long
6397 **/
6398static void ixgbe_service_timer(unsigned long data)
6399{
6400 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6401 unsigned long next_event_offset;
83c61fa9 6402 bool ready = true;
7086400d 6403
83c61fa9
GR		 6404#ifdef CONFIG_PCI_IOV
6405 ready = false;
6406
6407 /*
6408 * don't bother with SR-IOV VF DMA hang check if there are
6409 * no VFs or the link is down
6410 */
6411 if (!adapter->num_vfs ||
6412 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) {
6413 ready = true;
6414 goto normal_timer_service;
6415 }
6416
6417 /* If we have VFs allocated then we must check for DMA hangs */
6418 ixgbe_check_for_bad_vf(adapter);
6419 next_event_offset = HZ / 50;
6420 adapter->timer_event_accumulator++;
6421
6422 if (adapter->timer_event_accumulator >= 100) {
6423 ready = true;
6424 adapter->timer_event_accumulator = 0;
6425 }
6426
6427 goto schedule_event;
6428
6429normal_timer_service:
6430#endif
7086400d
AD		 6431 /* poll faster when waiting for link */
6432 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6433 next_event_offset = HZ / 10;
6434 else
6435 next_event_offset = HZ * 2;
6436
83c61fa9
GR		 6437#ifdef CONFIG_PCI_IOV
6438schedule_event:
6439#endif
7086400d
AD		 6440 /* Reset the timer */
6441 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6442
83c61fa9
GR		 6443 if (ready)
6444 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6445}
6446
c83c6cbd
AD		 6447static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6448{
6449 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6450 return;
6451
6452 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6453
6454 /* If we're already down or resetting, just bail */
6455 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6456 test_bit(__IXGBE_RESETTING, &adapter->state))
6457 return;
6458
6459 ixgbe_dump(adapter);
6460 netdev_err(adapter->netdev, "Reset adapter\n");
6461 adapter->tx_timeout_count++;
6462
6463 ixgbe_reinit_locked(adapter);
6464}
6465
7086400d
AD		 6466/**
6467 * ixgbe_service_task - manages and runs subtasks
6468 * @work: pointer to work_struct containing our data
6469 **/
6470static void ixgbe_service_task(struct work_struct *work)
6471{
6472 struct ixgbe_adapter *adapter = container_of(work,
6473 struct ixgbe_adapter,
6474 service_task);
6475
c83c6cbd 6476 ixgbe_reset_subtask(adapter);
7086400d
AD		 6477 ixgbe_sfp_detection_subtask(adapter);
6478 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6479 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6480 ixgbe_watchdog_subtask(adapter);
d034acf1 6481 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6482 ixgbe_check_hang_subtask(adapter);
7086400d
AD		 6483
6484 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6485}
6486
897ab156
AD		 6487void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6488 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
9a799d71
AK		 6489{
6490 struct ixgbe_adv_tx_context_desc *context_desc;
897ab156 6491 u16 i = tx_ring->next_to_use;
9a799d71 6492
e4f74028 6493 context_desc = IXGBE_TX_CTXTDESC(tx_ring, i);
9a799d71 6494
897ab156
AD		 6495 i++;
6496 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
9a799d71 6497
897ab156
AD		 6498 /* set bits to identify this as an advanced context descriptor */
6499 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
9a799d71 6500
897ab156
AD		 6501 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6502 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6503 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6504 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6505}
9a799d71 6506
897ab156
AD		 6507static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6508 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6509{
6510 int err;
6511 u32 vlan_macip_lens, type_tucmd;
6512 u32 mss_l4len_idx, l4len;
9a799d71 6513
897ab156
AD		 6514 if (!skb_is_gso(skb))
6515 return 0;
9a799d71 6516
897ab156
AD		 6517 if (skb_header_cloned(skb)) {
6518 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6519 if (err)
6520 return err;
9a799d71 6521 }
9a799d71 6522
897ab156
AD		 6523 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6524 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6525
6526 if (protocol == __constant_htons(ETH_P_IP)) {
6527 struct iphdr *iph = ip_hdr(skb);
6528 iph->tot_len = 0;
6529 iph->check = 0;
6530 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6531 iph->daddr, 0,
6532 IPPROTO_TCP,
6533 0);
6534 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6535 } else if (skb_is_gso_v6(skb)) {
6536 ipv6_hdr(skb)->payload_len = 0;
6537 tcp_hdr(skb)->check =
6538 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6539 &ipv6_hdr(skb)->daddr,
6540 0, IPPROTO_TCP, 0);
6541 }
6542
6543 l4len = tcp_hdrlen(skb);
6544 *hdr_len = skb_transport_offset(skb) + l4len;
6545
6546 /* mss_l4len_id: use 1 as index for TSO */
6547 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6548 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6549 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6550
6551 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6552 vlan_macip_lens = skb_network_header_len(skb);
6553 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6554 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6555
6556 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6557 mss_l4len_idx);
6558
6559 return 1;
6560}
6561
6562static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6563 struct sk_buff *skb, u32 tx_flags,
6564 __be16 protocol)
7ca647bd 6565{
897ab156
AD		 6566 u32 vlan_macip_lens = 0;
6567 u32 mss_l4len_idx = 0;
6568 u32 type_tucmd = 0;
7ca647bd 6569
897ab156 6570 if (skb->ip_summed != CHECKSUM_PARTIAL) {
7f9643fd
AD		 6571 if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6572 !(tx_flags & IXGBE_TX_FLAGS_TXSW))
897ab156
AD		 6573 return false;
6574 } else {
6575 u8 l4_hdr = 0;
6576 switch (protocol) {
6577 case __constant_htons(ETH_P_IP):
6578 vlan_macip_lens |= skb_network_header_len(skb);
6579 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6580 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6581 break;
897ab156
AD		 6582 case __constant_htons(ETH_P_IPV6):
6583 vlan_macip_lens |= skb_network_header_len(skb);
6584 l4_hdr = ipv6_hdr(skb)->nexthdr;
6585 break;
6586 default:
6587 if (unlikely(net_ratelimit())) {
6588 dev_warn(tx_ring->dev,
6589 "partial checksum but proto=%x!\n",
6590 skb->protocol);
6591 }
7ca647bd
JP		 6592 break;
6593 }
897ab156
AD		 6594
6595 switch (l4_hdr) {
7ca647bd 6596 case IPPROTO_TCP:
897ab156
AD		 6597 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6598 mss_l4len_idx = tcp_hdrlen(skb) <<
6599 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6600 break;
6601 case IPPROTO_SCTP:
897ab156
AD		 6602 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6603 mss_l4len_idx = sizeof(struct sctphdr) <<
6604 IXGBE_ADVTXD_L4LEN_SHIFT;
6605 break;
6606 case IPPROTO_UDP:
6607 mss_l4len_idx = sizeof(struct udphdr) <<
6608 IXGBE_ADVTXD_L4LEN_SHIFT;
6609 break;
6610 default:
6611 if (unlikely(net_ratelimit())) {
6612 dev_warn(tx_ring->dev,
6613 "partial checksum but l4 proto=%x!\n",
6614 skb->protocol);
6615 }
7ca647bd
JP		 6616 break;
6617 }
7ca647bd
JP		 6618 }
6619
897ab156
AD		 6620 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6621 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6622
897ab156
AD		 6623 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6624 type_tucmd, mss_l4len_idx);
9a799d71 6625
897ab156 6626 return (skb->ip_summed == CHECKSUM_PARTIAL);
9a799d71
AK		 6627}
6628
d3d00239 6629static __le32 ixgbe_tx_cmd_type(u32 tx_flags)
9a799d71 6630{
d3d00239
AD		 6631 /* set type for advanced descriptor with frame checksum insertion */
6632 __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA |
6633 IXGBE_ADVTXD_DCMD_IFCS |
6634 IXGBE_ADVTXD_DCMD_DEXT);
9a799d71 6635
d3d00239 6636 /* set HW vlan bit if vlan is present */
66f32a8b 6637 if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN)
d3d00239 6638 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE);
9a799d71 6639
d3d00239
AD		 6640 /* set segmentation enable bits for TSO/FSO */
6641#ifdef IXGBE_FCOE
6642 if ((tx_flags & IXGBE_TX_FLAGS_TSO) || (tx_flags & IXGBE_TX_FLAGS_FSO))
6643#else
6644 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6645#endif
6646 cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE);
eacd73f7 6647
d3d00239
AD		 6648 return cmd_type;
6649}
9a799d71 6650
d3d00239
AD		 6651static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen)
6652{
6653 __le32 olinfo_status =
6654 cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT);
44df32c5 6655
d3d00239
AD		 6656 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6657 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM |
6658 (1 << IXGBE_ADVTXD_IDX_SHIFT));
6659 /* enble IPv4 checksum for TSO */
6660 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6661 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM);
9a799d71
AK		 6662 }
6663
d3d00239
AD		 6664 /* enable L4 checksum for TSO and TX checksum offload */
6665 if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6666 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6667
d3d00239
AD		 6668#ifdef IXGBE_FCOE
6669 /* use index 1 context for FCOE/FSO */
6670 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6671 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC |
6672 (1 << IXGBE_ADVTXD_IDX_SHIFT));
9a799d71 6673
d3d00239 6674#endif
7f9643fd
AD		 6675 /*
6676 * Check Context must be set if Tx switch is enabled, which it
6677 * always is for case where virtual functions are running
6678 */
6679 if (tx_flags & IXGBE_TX_FLAGS_TXSW)
6680 olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC);
6681
d3d00239
AD		 6682 return olinfo_status;
6683}
44df32c5 6684
d3d00239
AD		 6685#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6686 IXGBE_TXD_CMD_RS)
6687
6688static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
6689 struct sk_buff *skb,
6690 struct ixgbe_tx_buffer *first,
6691 u32 tx_flags,
6692 const u8 hdr_len)
6693{
6694 struct device *dev = tx_ring->dev;
6695 struct ixgbe_tx_buffer *tx_buffer_info;
6696 union ixgbe_adv_tx_desc *tx_desc;
6697 dma_addr_t dma;
6698 __le32 cmd_type, olinfo_status;
6699 struct skb_frag_struct *frag;
6700 unsigned int f = 0;
6701 unsigned int data_len = skb->data_len;
6702 unsigned int size = skb_headlen(skb);
6703 u32 offset = 0;
6704 u32 paylen = skb->len - hdr_len;
6705 u16 i = tx_ring->next_to_use;
6706 u16 gso_segs;
6707
6708#ifdef IXGBE_FCOE
6709 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6710 if (data_len >= sizeof(struct fcoe_crc_eof)) {
6711 data_len -= sizeof(struct fcoe_crc_eof);
6712 } else {
6713 size -= sizeof(struct fcoe_crc_eof) - data_len;
6714 data_len = 0;
9a799d71
AK		 6715 }
6716 }
44df32c5 6717
d3d00239
AD		 6718#endif
6719 dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE);
6720 if (dma_mapping_error(dev, dma))
6721 goto dma_error;
8ad494b0 6722
d3d00239
AD		 6723 cmd_type = ixgbe_tx_cmd_type(tx_flags);
6724 olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen);
9a799d71 6725
e4f74028 6726 tx_desc = IXGBE_TX_DESC(tx_ring, i);
e5a43549 6727
d3d00239
AD		 6728 for (;;) {
6729 while (size > IXGBE_MAX_DATA_PER_TXD) {
6730 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6731 tx_desc->read.cmd_type_len =
6732 cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD);
6733 tx_desc->read.olinfo_status = olinfo_status;
e5a43549 6734
d3d00239
AD		 6735 offset += IXGBE_MAX_DATA_PER_TXD;
6736 size -= IXGBE_MAX_DATA_PER_TXD;
e5a43549 6737
d3d00239
AD		 6738 tx_desc++;
6739 i++;
6740 if (i == tx_ring->count) {
e4f74028 6741 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6742 i = 0;
6743 }
6744 }
e5a43549 6745
e5a43549 6746 tx_buffer_info = &tx_ring->tx_buffer_info[i];
d3d00239
AD		 6747 tx_buffer_info->length = offset + size;
6748 tx_buffer_info->tx_flags = tx_flags;
6749 tx_buffer_info->dma = dma;
9a799d71 6750
d3d00239
AD		 6751 tx_desc->read.buffer_addr = cpu_to_le64(dma + offset);
6752 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
6753 tx_desc->read.olinfo_status = olinfo_status;
9a799d71 6754
d3d00239
AD		 6755 if (!data_len)
6756 break;
9a799d71 6757
d3d00239
AD		 6758 frag = &skb_shinfo(skb)->frags[f];
6759#ifdef IXGBE_FCOE
9e903e08 6760 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6761#else
9e903e08 6762 size = skb_frag_size(frag);
d3d00239
AD		 6763#endif
6764 data_len -= size;
6765 f++;
9a799d71 6766
d3d00239
AD		 6767 offset = 0;
6768 tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE;
9a799d71 6769
877749bf 6770 dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE);
d3d00239
AD		 6771 if (dma_mapping_error(dev, dma))
6772 goto dma_error;
9a799d71 6773
d3d00239
AD		 6774 tx_desc++;
6775 i++;
6776 if (i == tx_ring->count) {
e4f74028 6777 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6778 i = 0;
6779 }
6780 }
9a799d71 6781
d3d00239 6782 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
9a799d71 6783
d3d00239
AD		 6784 i++;
6785 if (i == tx_ring->count)
6786 i = 0;
9a799d71 6787
d3d00239 6788 tx_ring->next_to_use = i;
eacd73f7 6789
d3d00239
AD		 6790 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6791 gso_segs = skb_shinfo(skb)->gso_segs;
6792#ifdef IXGBE_FCOE
6793 /* adjust for FCoE Sequence Offload */
6794 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6795 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6796 skb_shinfo(skb)->gso_size);
6797#endif /* IXGBE_FCOE */
6798 else
6799 gso_segs = 1;
9a799d71 6800
d3d00239
AD		 6801 /* multiply data chunks by size of headers */
6802 tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len);
6803 tx_buffer_info->gso_segs = gso_segs;
6804 tx_buffer_info->skb = skb;
9a799d71 6805
d3d00239
AD		 6806 /* set the timestamp */
6807 first->time_stamp = jiffies;
9a799d71
AK		 6808
6809 /*
6810 * Force memory writes to complete before letting h/w
6811 * know there are new descriptors to fetch. (Only
6812 * applicable for weak-ordered memory model archs,
6813 * such as IA-64).
6814 */
6815 wmb();
6816
d3d00239
AD		 6817 /* set next_to_watch value indicating a packet is present */
6818 first->next_to_watch = tx_desc;
6819
6820 /* notify HW of packet */
84ea2591 6821 writel(i, tx_ring->tail);
d3d00239
AD		 6822
6823 return;
6824dma_error:
6825 dev_err(dev, "TX DMA map failed\n");
6826
6827 /* clear dma mappings for failed tx_buffer_info map */
6828 for (;;) {
6829 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6830 ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info);
6831 if (tx_buffer_info == first)
6832 break;
6833 if (i == 0)
6834 i = tx_ring->count;
6835 i--;
6836 }
6837
6838 dev_kfree_skb_any(skb);
6839
6840 tx_ring->next_to_use = i;
9a799d71
AK		 6841}
6842
69830529
AD		 6843static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6844 u32 tx_flags, __be16 protocol)
6845{
6846 struct ixgbe_q_vector *q_vector = ring->q_vector;
6847 union ixgbe_atr_hash_dword input = { .dword = 0 };
6848 union ixgbe_atr_hash_dword common = { .dword = 0 };
6849 union {
6850 unsigned char *network;
6851 struct iphdr *ipv4;
6852 struct ipv6hdr *ipv6;
6853 } hdr;
ee9e0f0b 6854 struct tcphdr *th;
905e4a41 6855 __be16 vlan_id;
c4cf55e5 6856
69830529
AD		 6857 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6858 if (!q_vector)
6859 return;
6860
6861 /* do nothing if sampling is disabled */
6862 if (!ring->atr_sample_rate)
d3ead241 6863 return;
c4cf55e5 6864
69830529 6865 ring->atr_count++;
c4cf55e5 6866
69830529
AD		 6867 /* snag network header to get L4 type and address */
6868 hdr.network = skb_network_header(skb);
6869
6870 /* Currently only IPv4/IPv6 with TCP is supported */
6871 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6872 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6873 (protocol != __constant_htons(ETH_P_IP) ||
6874 hdr.ipv4->protocol != IPPROTO_TCP))
6875 return;
ee9e0f0b
AD		 6876
6877 th = tcp_hdr(skb);
c4cf55e5 6878
66f32a8b
AD		 6879 /* skip this packet since it is invalid or the socket is closing */
6880 if (!th || th->fin)
69830529
AD		 6881 return;
6882
6883 /* sample on all syn packets or once every atr sample count */
6884 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6885 return;
6886
6887 /* reset sample count */
6888 ring->atr_count = 0;
6889
6890 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6891
6892 /*
6893 * src and dst are inverted, think how the receiver sees them
6894 *
6895 * The input is broken into two sections, a non-compressed section
6896 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6897 * is XORed together and stored in the compressed dword.
6898 */
6899 input.formatted.vlan_id = vlan_id;
6900
6901 /*
6902 * since src port and flex bytes occupy the same word XOR them together
6903 * and write the value to source port portion of compressed dword
6904 */
66f32a8b 6905 if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6906 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6907 else
6908 common.port.src ^= th->dest ^ protocol;
6909 common.port.dst ^= th->source;
6910
6911 if (protocol == __constant_htons(ETH_P_IP)) {
6912 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6913 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6914 } else {
6915 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6916 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6917 hdr.ipv6->saddr.s6_addr32[1] ^
6918 hdr.ipv6->saddr.s6_addr32[2] ^
6919 hdr.ipv6->saddr.s6_addr32[3] ^
6920 hdr.ipv6->daddr.s6_addr32[0] ^
6921 hdr.ipv6->daddr.s6_addr32[1] ^
6922 hdr.ipv6->daddr.s6_addr32[2] ^
6923 hdr.ipv6->daddr.s6_addr32[3];
6924 }
c4cf55e5
PWJ		 6925
6926 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6927 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6928 input, common, ring->queue_index);
c4cf55e5
PWJ		 6929}
6930
63544e9c 6931static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6932{
fc77dc3c 6933 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6934 /* Herbert's original patch had:
6935 * smp_mb__after_netif_stop_queue();
6936 * but since that doesn't exist yet, just open code it. */
6937 smp_mb();
6938
6939 /* We need to check again in a case another CPU has just
6940 * made room available. */
7d4987de 6941 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6942 return -EBUSY;
6943
6944 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6945 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6946 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6947 return 0;
6948}
6949
82d4e46e 6950static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6951{
7d4987de 6952 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6953 return 0;
fc77dc3c 6954 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6955}
6956
09a3b1f8
SH		 6957static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6958{
6959 struct ixgbe_adapter *adapter = netdev_priv(dev);
6440752c
AD		 6960 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6961 smp_processor_id();
56075a98 6962#ifdef IXGBE_FCOE
6440752c 6963 __be16 protocol = vlan_get_protocol(skb);
5e09a105 6964
e5b64635
JF		 6965 if (((protocol == htons(ETH_P_FCOE)) ||
6966 (protocol == htons(ETH_P_FIP))) &&
6967 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6968 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6969 txq += adapter->ring_feature[RING_F_FCOE].mask;
6970 return txq;
56075a98
JF		 6971 }
6972#endif
6973
fdd3d631
KK		 6974 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6975 while (unlikely(txq >= dev->real_num_tx_queues))
6976 txq -= dev->real_num_tx_queues;
5f715823 6977 return txq;
fdd3d631 6978 }
c4cf55e5 6979
09a3b1f8
SH		 6980 return skb_tx_hash(dev, skb);
6981}
6982
fc77dc3c 6983netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6984 struct ixgbe_adapter *adapter,
6985 struct ixgbe_ring *tx_ring)
9a799d71 6986{
d3d00239 6987 struct ixgbe_tx_buffer *first;
5f715823 6988 int tso;
d3d00239 6989 u32 tx_flags = 0;
a535c30e
AD		 6990#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6991 unsigned short f;
6992#endif
a535c30e 6993 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6994 __be16 protocol = skb->protocol;
63544e9c 6995 u8 hdr_len = 0;
5e09a105 6996
a535c30e
AD		 6997 /*
6998 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6999 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
7000 * + 2 desc gap to keep tail from touching head,
7001 * + 1 desc for context descriptor,
7002 * otherwise try next time
7003 */
7004#if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
7005 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7006 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7007#else
7008 count += skb_shinfo(skb)->nr_frags;
7009#endif
7010 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7011 tx_ring->tx_stats.tx_busy++;
7012 return NETDEV_TX_BUSY;
7013 }
7014
66f32a8b 7015 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7016 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7017 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7018 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7019 /* else if it is a SW VLAN check the next protocol and store the tag */
7020 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
7021 struct vlan_hdr *vhdr, _vhdr;
7022 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7023 if (!vhdr)
7024 goto out_drop;
7025
7026 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7027 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7028 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7029 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7030 }
7031
9e0c5648
AD		 7032#ifdef CONFIG_PCI_IOV
7033 /*
7034 * Use the l2switch_enable flag - would be false if the DMA
7035 * Tx switch had been disabled.
7036 */
7037 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7038 tx_flags |= IXGBE_TX_FLAGS_TXSW;
7039
7040#endif
32701dc2 7041 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7042 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7043 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7044 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7045 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7046 tx_flags |= (skb->priority & 0x7) <<
7047 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7048 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7049 struct vlan_ethhdr *vhdr;
7050 if (skb_header_cloned(skb) &&
7051 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
7052 goto out_drop;
7053 vhdr = (struct vlan_ethhdr *)skb->data;
7054 vhdr->h_vlan_TCI = htons(tx_flags >>
7055 IXGBE_TX_FLAGS_VLAN_SHIFT);
7056 } else {
7057 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7058 }
9a799d71 7059 }
eacd73f7 7060
a535c30e 7061 /* record the location of the first descriptor for this packet */
d3d00239 7062 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
a535c30e 7063
eacd73f7 7064#ifdef IXGBE_FCOE
66f32a8b
AD		 7065 /* setup tx offload for FCoE */
7066 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
7067 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
897ab156
AD		 7068 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
7069 if (tso < 0)
7070 goto out_drop;
7071 else if (tso)
66f32a8b
AD		 7072 tx_flags |= IXGBE_TX_FLAGS_FSO |
7073 IXGBE_TX_FLAGS_FCOE;
7074 else
7075 tx_flags |= IXGBE_TX_FLAGS_FCOE;
9a799d71 7076
66f32a8b 7077 goto xmit_fcoe;
eacd73f7 7078 }
9a799d71 7079
66f32a8b
AD		 7080#endif /* IXGBE_FCOE */
7081 /* setup IPv4/IPv6 offloads */
7082 if (protocol == __constant_htons(ETH_P_IP))
7083 tx_flags |= IXGBE_TX_FLAGS_IPV4;
9a799d71 7084
66f32a8b
AD		 7085 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
7086 if (tso < 0)
897ab156 7087 goto out_drop;
66f32a8b
AD		 7088 else if (tso)
7089 tx_flags |= IXGBE_TX_FLAGS_TSO;
7090 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
7091 tx_flags |= IXGBE_TX_FLAGS_CSUM;
7092
7093 /* add the ATR filter if ATR is on */
7094 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
7095 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
7096
7097#ifdef IXGBE_FCOE
7098xmit_fcoe:
7099#endif /* IXGBE_FCOE */
d3d00239
AD		 7100 ixgbe_tx_map(tx_ring, skb, first, tx_flags, hdr_len);
7101
7102 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7103
7104 return NETDEV_TX_OK;
897ab156
AD		 7105
7106out_drop:
7107 dev_kfree_skb_any(skb);
7108 return NETDEV_TX_OK;
9a799d71
AK		 7109}
7110
84418e3b
AD		 7111static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
7112{
7113 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7114 struct ixgbe_ring *tx_ring;
7115
7116 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 7117 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7118}
7119
9a799d71
AK		 7120/**
7121 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7122 * @netdev: network interface device structure
7123 * @p: pointer to an address structure
7124 *
7125 * Returns 0 on success, negative on failure
7126 **/
7127static int ixgbe_set_mac(struct net_device *netdev, void *p)
7128{
7129 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7130 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7131 struct sockaddr *addr = p;
7132
7133 if (!is_valid_ether_addr(addr->sa_data))
7134 return -EADDRNOTAVAIL;
7135
7136 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7137 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7138
1cdd1ec8
GR		 7139 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
7140 IXGBE_RAH_AV);
9a799d71
AK		 7141
7142 return 0;
7143}
7144
6b73e10d
BH		 7145static int
7146ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7147{
7148 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7149 struct ixgbe_hw *hw = &adapter->hw;
7150 u16 value;
7151 int rc;
7152
7153 if (prtad != hw->phy.mdio.prtad)
7154 return -EINVAL;
7155 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7156 if (!rc)
7157 rc = value;
7158 return rc;
7159}
7160
7161static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7162 u16 addr, u16 value)
7163{
7164 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7165 struct ixgbe_hw *hw = &adapter->hw;
7166
7167 if (prtad != hw->phy.mdio.prtad)
7168 return -EINVAL;
7169 return hw->phy.ops.write_reg(hw, addr, devad, value);
7170}
7171
7172static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7173{
7174 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7175
7176 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7177}
7178
0365e6e4
PW		 7179/**
7180 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7181 * netdev->dev_addrs
0365e6e4
PW		 7182 * @netdev: network interface device structure
7183 *
7184 * Returns non-zero on failure
7185 **/
7186static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7187{
7188 int err = 0;
7189 struct ixgbe_adapter *adapter = netdev_priv(dev);
7190 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7191
7192 if (is_valid_ether_addr(mac->san_addr)) {
7193 rtnl_lock();
7194 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7195 rtnl_unlock();
7196 }
7197 return err;
7198}
7199
7200/**
7201 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7202 * netdev->dev_addrs
0365e6e4
PW		 7203 * @netdev: network interface device structure
7204 *
7205 * Returns non-zero on failure
7206 **/
7207static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7208{
7209 int err = 0;
7210 struct ixgbe_adapter *adapter = netdev_priv(dev);
7211 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7212
7213 if (is_valid_ether_addr(mac->san_addr)) {
7214 rtnl_lock();
7215 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7216 rtnl_unlock();
7217 }
7218 return err;
7219}
7220
9a799d71
AK		 7221#ifdef CONFIG_NET_POLL_CONTROLLER
7222/*
7223 * Polling 'interrupt' - used by things like netconsole to send skbs
7224 * without having to re-enable interrupts. It's not called while
7225 * the interrupt routine is executing.
7226 */
7227static void ixgbe_netpoll(struct net_device *netdev)
7228{
7229 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7230 int i;
9a799d71 7231
1a647bd2
AD		 7232 /* if interface is down do nothing */
7233 if (test_bit(__IXGBE_DOWN, &adapter->state))
7234 return;
7235
9a799d71 7236 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167
PWJ		 7237 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7238 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7239 for (i = 0; i < num_q_vectors; i++) {
7240 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4ff7fb12 7241 ixgbe_msix_clean_rings(0, q_vector);
8f9a7167
PWJ		 7242 }
7243 } else {
7244 ixgbe_intr(adapter->pdev->irq, netdev);
7245 }
9a799d71 7246 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71
AK		 7247}
7248#endif
7249
de1036b1
ED		 7250static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7251 struct rtnl_link_stats64 *stats)
7252{
7253 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7254 int i;
7255
1a51502b 7256 rcu_read_lock();
de1036b1 7257 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7258 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7259 u64 bytes, packets;
7260 unsigned int start;
7261
1a51502b
ED		 7262 if (ring) {
7263 do {
7264 start = u64_stats_fetch_begin_bh(&ring->syncp);
7265 packets = ring->stats.packets;
7266 bytes = ring->stats.bytes;
7267 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7268 stats->rx_packets += packets;
7269 stats->rx_bytes += bytes;
7270 }
de1036b1 7271 }
1ac9ad13
ED		 7272
7273 for (i = 0; i < adapter->num_tx_queues; i++) {
7274 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7275 u64 bytes, packets;
7276 unsigned int start;
7277
7278 if (ring) {
7279 do {
7280 start = u64_stats_fetch_begin_bh(&ring->syncp);
7281 packets = ring->stats.packets;
7282 bytes = ring->stats.bytes;
7283 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7284 stats->tx_packets += packets;
7285 stats->tx_bytes += bytes;
7286 }
7287 }
1a51502b 7288 rcu_read_unlock();
de1036b1
ED		 7289 /* following stats updated by ixgbe_watchdog_task() */
7290 stats->multicast = netdev->stats.multicast;
7291 stats->rx_errors = netdev->stats.rx_errors;
7292 stats->rx_length_errors = netdev->stats.rx_length_errors;
7293 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7294 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7295 return stats;
7296}
7297
8b1c0b24
JF		 7298/* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7299 * #adapter: pointer to ixgbe_adapter
7300 * @tc: number of traffic classes currently enabled
7301 *
7302 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7303 * 802.1Q priority maps to a packet buffer that exists.
7304 */
7305static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7306{
7307 struct ixgbe_hw *hw = &adapter->hw;
7308 u32 reg, rsave;
7309 int i;
7310
7311 /* 82598 have a static priority to TC mapping that can not
7312 * be changed so no validation is needed.
7313 */
7314 if (hw->mac.type == ixgbe_mac_82598EB)
7315 return;
7316
7317 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7318 rsave = reg;
7319
7320 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7321 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7322
7323 /* If up2tc is out of bounds default to zero */
7324 if (up2tc > tc)
7325 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7326 }
7327
7328 if (reg != rsave)
7329 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7330
7331 return;
7332}
7333
7334
7335/* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7336 * classes.
7337 *
7338 * @netdev: net device to configure
7339 * @tc: number of traffic classes to enable
7340 */
7341int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7342{
8b1c0b24
JF		 7343 struct ixgbe_adapter *adapter = netdev_priv(dev);
7344 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7345
e7589eab
JF		 7346 /* Multiple traffic classes requires multiple queues */
7347 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7348 e_err(drv, "Enable failed, needs MSI-X\n");
7349 return -EINVAL;
7350 }
8b1c0b24
JF		 7351
7352 /* Hardware supports up to 8 traffic classes */
4de2a022 7353 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
8b1c0b24
JF		 7354 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7355 return -EINVAL;
7356
7357 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7358 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7359 * hardware is not flexible enough to do this dynamically.
7360 */
7361 if (netif_running(dev))
7362 ixgbe_close(dev);
7363 ixgbe_clear_interrupt_scheme(adapter);
7364
e7589eab 7365 if (tc) {
8b1c0b24 7366 netdev_set_num_tc(dev, tc);
e7589eab
JF		 7367 adapter->last_lfc_mode = adapter->hw.fc.current_mode;
7368
7369 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
7370 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7371
7372 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7373 adapter->hw.fc.requested_mode = ixgbe_fc_none;
7374 } else {
8b1c0b24
JF		 7375 netdev_reset_tc(dev);
7376
e7589eab
JF		 7377 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
7378
7379 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
7380 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7381
7382 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7383 adapter->dcb_cfg.pfc_mode_enable = false;
7384 }
7385
8b1c0b24
JF		 7386 ixgbe_init_interrupt_scheme(adapter);
7387 ixgbe_validate_rtr(adapter, tc);
7388 if (netif_running(dev))
7389 ixgbe_open(dev);
7390
7391 return 0;
7392}
de1036b1 7393
082757af
DS		 7394void ixgbe_do_reset(struct net_device *netdev)
7395{
7396 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7397
7398 if (netif_running(netdev))
7399 ixgbe_reinit_locked(adapter);
7400 else
7401 ixgbe_reset(adapter);
7402}
7403
c8f44aff
MM		 7404static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
7405 netdev_features_t data)
082757af
DS		 7406{
7407 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7408
7409#ifdef CONFIG_DCB
7410 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
7411 data &= ~NETIF_F_HW_VLAN_RX;
7412#endif
7413
7414 /* return error if RXHASH is being enabled when RSS is not supported */
7415 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7416 data &= ~NETIF_F_RXHASH;
7417
7418 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
7419 if (!(data & NETIF_F_RXCSUM))
7420 data &= ~NETIF_F_LRO;
7421
7422 /* Turn off LRO if not RSC capable or invalid ITR settings */
7423 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) {
7424 data &= ~NETIF_F_LRO;
7425 } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
7426 (adapter->rx_itr_setting != 1 &&
7427 adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) {
7428 data &= ~NETIF_F_LRO;
7429 e_info(probe, "rx-usecs set too low, not enabling RSC\n");
7430 }
7431
7432 return data;
7433}
7434
c8f44aff
MM		 7435static int ixgbe_set_features(struct net_device *netdev,
7436 netdev_features_t data)
082757af
DS		 7437{
7438 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7439 bool need_reset = false;
7440
082757af
DS		 7441 /* Make sure RSC matches LRO, reset if change */
7442 if (!!(data & NETIF_F_LRO) !=
7443 !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7444 adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED;
7445 switch (adapter->hw.mac.type) {
7446 case ixgbe_mac_X540:
7447 case ixgbe_mac_82599EB:
7448 need_reset = true;
7449 break;
7450 default:
7451 break;
7452 }
7453 }
7454
7455 /*
7456 * Check if Flow Director n-tuple support was enabled or disabled. If
7457 * the state changed, we need to reset.
7458 */
7459 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
7460 /* turn off ATR, enable perfect filters and reset */
7461 if (data & NETIF_F_NTUPLE) {
7462 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7463 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7464 need_reset = true;
7465 }
7466 } else if (!(data & NETIF_F_NTUPLE)) {
7467 /* turn off Flow Director, set ATR and reset */
7468 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7469 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
7470 !(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7471 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7472 need_reset = true;
7473 }
7474
7475 if (need_reset)
7476 ixgbe_do_reset(netdev);
7477
7478 return 0;
7479
7480}
7481
0edc3527 7482static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7483 .ndo_open = ixgbe_open,
0edc3527 7484 .ndo_stop = ixgbe_close,
00829823 7485 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7486 .ndo_select_queue = ixgbe_select_queue,
e90d400c 7487 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7488 .ndo_validate_addr = eth_validate_addr,
7489 .ndo_set_mac_address = ixgbe_set_mac,
7490 .ndo_change_mtu = ixgbe_change_mtu,
7491 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7492 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7493 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7494 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7495 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7496 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7497 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
de4c7f65 7498 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7499 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7500 .ndo_get_stats64 = ixgbe_get_stats64,
24095aa3 7501 .ndo_setup_tc = ixgbe_setup_tc,
0edc3527
SH		 7502#ifdef CONFIG_NET_POLL_CONTROLLER
7503 .ndo_poll_controller = ixgbe_netpoll,
7504#endif
332d4a7d
YZ		 7505#ifdef IXGBE_FCOE
7506 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7507 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7508 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7509 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7510 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7511 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7512 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7513#endif /* IXGBE_FCOE */
082757af
DS		 7514 .ndo_set_features = ixgbe_set_features,
7515 .ndo_fix_features = ixgbe_fix_features,
0edc3527
SH		 7516};
7517
1cdd1ec8
GR		 7518static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7519 const struct ixgbe_info *ii)
7520{
7521#ifdef CONFIG_PCI_IOV
7522 struct ixgbe_hw *hw = &adapter->hw;
1cdd1ec8 7523
c6bda30a 7524 if (hw->mac.type == ixgbe_mac_82598EB)
1cdd1ec8
GR		 7525 return;
7526
7527 /* The 82599 supports up to 64 VFs per physical function
7528 * but this implementation limits allocation to 63 so that
7529 * basic networking resources are still available to the
7530 * physical function
7531 */
7532 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
c6bda30a 7533 ixgbe_enable_sriov(adapter, ii);
1cdd1ec8
GR		 7534#endif /* CONFIG_PCI_IOV */
7535}
7536
9a799d71
AK		 7537/**
7538 * ixgbe_probe - Device Initialization Routine
7539 * @pdev: PCI device information struct
7540 * @ent: entry in ixgbe_pci_tbl
7541 *
7542 * Returns 0 on success, negative on failure
7543 *
7544 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7545 * The OS initialization, configuring of the adapter private structure,
7546 * and a hardware reset occur.
7547 **/
7548static int __devinit ixgbe_probe(struct pci_dev *pdev,
e8e9f696 7549 const struct pci_device_id *ent)
9a799d71
AK		 7550{
7551 struct net_device *netdev;
7552 struct ixgbe_adapter *adapter = NULL;
7553 struct ixgbe_hw *hw;
7554 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71
AK		 7555 static int cards_found;
7556 int i, err, pci_using_dac;
289700db 7557 u8 part_str[IXGBE_PBANUM_LENGTH];
c85a2618 7558 unsigned int indices = num_possible_cpus();
eacd73f7
YZ		 7559#ifdef IXGBE_FCOE
7560 u16 device_caps;
7561#endif
289700db 7562 u32 eec;
c23f5b6b 7563 u16 wol_cap;
9a799d71 7564
bded64a7
AG		 7565 /* Catch broken hardware that put the wrong VF device ID in
7566 * the PCIe SR-IOV capability.
7567 */
7568 if (pdev->is_virtfn) {
7569 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7570 pci_name(pdev), pdev->vendor, pdev->device);
7571 return -EINVAL;
7572 }
7573
9ce77666 7574 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7575 if (err)
7576 return err;
7577
1b507730
NN		 7578 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7579 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7580 pci_using_dac = 1;
7581 } else {
1b507730 7582 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7583 if (err) {
1b507730
NN		 7584 err = dma_set_coherent_mask(&pdev->dev,
7585 DMA_BIT_MASK(32));
9a799d71 7586 if (err) {
b8bc0421
DC		 7587 dev_err(&pdev->dev,
7588 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7589 goto err_dma;
7590 }
7591 }
7592 pci_using_dac = 0;
7593 }
7594
9ce77666 7595 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7596 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7597 if (err) {
b8bc0421
DC		 7598 dev_err(&pdev->dev,
7599 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7600 goto err_pci_reg;
7601 }
7602
19d5afd4 7603 pci_enable_pcie_error_reporting(pdev);
6fabd715 7604
9a799d71 7605 pci_set_master(pdev);
fb3b27bc 7606 pci_save_state(pdev);
9a799d71 7607
e901acd6
JF		 7608#ifdef CONFIG_IXGBE_DCB
7609 indices *= MAX_TRAFFIC_CLASS;
7610#endif
7611
c85a2618
JF		 7612 if (ii->mac == ixgbe_mac_82598EB)
7613 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7614 else
7615 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7616
e901acd6 7617#ifdef IXGBE_FCOE
c85a2618
JF		 7618 indices += min_t(unsigned int, num_possible_cpus(),
7619 IXGBE_MAX_FCOE_INDICES);
7620#endif
c85a2618 7621 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7622 if (!netdev) {
7623 err = -ENOMEM;
7624 goto err_alloc_etherdev;
7625 }
7626
9a799d71
AK		 7627 SET_NETDEV_DEV(netdev, &pdev->dev);
7628
9a799d71 7629 adapter = netdev_priv(netdev);
c60fbb00 7630 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7631
7632 adapter->netdev = netdev;
7633 adapter->pdev = pdev;
7634 hw = &adapter->hw;
7635 hw->back = adapter;
7636 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7637
05857980 7638 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7639 pci_resource_len(pdev, 0));
9a799d71
AK		 7640 if (!hw->hw_addr) {
7641 err = -EIO;
7642 goto err_ioremap;
7643 }
7644
7645 for (i = 1; i <= 5; i++) {
7646 if (pci_resource_len(pdev, i) == 0)
7647 continue;
7648 }
7649
0edc3527 7650 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7651 ixgbe_set_ethtool_ops(netdev);
9a799d71 7652 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7653 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7654
9a799d71
AK		 7655 adapter->bd_number = cards_found;
7656
9a799d71
AK		 7657 /* Setup hw api */
7658 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7659 hw->mac.type = ii->mac;
9a799d71 7660
c44ade9e
JB		 7661 /* EEPROM */
7662 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7663 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7664 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7665 if (!(eec & (1 << 8)))
7666 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7667
7668 /* PHY */
7669 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7670 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7671 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7672 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7673 hw->phy.mdio.mmds = 0;
7674 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7675 hw->phy.mdio.dev = netdev;
7676 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7677 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7678
8ca783ab 7679 ii->get_invariants(hw);
9a799d71
AK		 7680
7681 /* setup the private structure */
7682 err = ixgbe_sw_init(adapter);
7683 if (err)
7684 goto err_sw_init;
7685
e86bff0e 7686 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7687 switch (adapter->hw.mac.type) {
7688 case ixgbe_mac_82599EB:
7689 case ixgbe_mac_X540:
e86bff0e 7690 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7691 break;
7692 default:
7693 break;
7694 }
e86bff0e 7695
bf069c97
DS		 7696 /*
7697 * If there is a fan on this device and it has failed log the
7698 * failure.
7699 */
7700 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7701 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7702 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7703 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7704 }
7705
8ef78adc
PWJ		 7706 if (allow_unsupported_sfp)
7707 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7708
c44ade9e 7709 /* reset_hw fills in the perm_addr as well */
119fc60a 7710 hw->phy.reset_if_overtemp = true;
c44ade9e 7711 err = hw->mac.ops.reset_hw(hw);
119fc60a 7712 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7713 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7714 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7715 err = 0;
7716 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7717 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7718 "module type was detected.\n");
7719 e_dev_err("Reload the driver after installing a supported "
7720 "module.\n");
04f165ef
PW		 7721 goto err_sw_init;
7722 } else if (err) {
849c4542 7723 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7724 goto err_sw_init;
7725 }
7726
1cdd1ec8
GR		 7727 ixgbe_probe_vf(adapter, ii);
7728
396e799c 7729 netdev->features = NETIF_F_SG |
e8e9f696 7730 NETIF_F_IP_CSUM |
082757af 7731 NETIF_F_IPV6_CSUM |
e8e9f696
JP		 7732 NETIF_F_HW_VLAN_TX |
7733 NETIF_F_HW_VLAN_RX |
082757af
DS		 7734 NETIF_F_HW_VLAN_FILTER |
7735 NETIF_F_TSO |
7736 NETIF_F_TSO6 |
082757af
DS		 7737 NETIF_F_RXHASH |
7738 NETIF_F_RXCSUM;
9a799d71 7739
082757af 7740 netdev->hw_features = netdev->features;
ad31c402 7741
58be7666
DS		 7742 switch (adapter->hw.mac.type) {
7743 case ixgbe_mac_82599EB:
7744 case ixgbe_mac_X540:
45a5ead0 7745 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7746 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7747 NETIF_F_NTUPLE;
58be7666
DS		 7748 break;
7749 default:
7750 break;
7751 }
45a5ead0 7752
ad31c402
JK		 7753 netdev->vlan_features |= NETIF_F_TSO;
7754 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7755 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7756 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7757 netdev->vlan_features |= NETIF_F_SG;
7758
01789349
JP		 7759 netdev->priv_flags |= IFF_UNICAST_FLT;
7760
1cdd1ec8
GR		 7761 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7762 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7763 IXGBE_FLAG_DCB_ENABLED);
2f90b865 7764
7a6b6f51 7765#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7766 netdev->dcbnl_ops = &dcbnl_ops;
7767#endif
7768
eacd73f7 7769#ifdef IXGBE_FCOE
0d551589 7770 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
eacd73f7
YZ		 7771 if (hw->mac.ops.get_device_caps) {
7772 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7773 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7774 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7
YZ		 7775 }
7776 }
5e09d7f6
YZ		 7777 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7778 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7779 netdev->vlan_features |= NETIF_F_FSO;
7780 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7781 }
eacd73f7 7782#endif /* IXGBE_FCOE */
7b872a55 7783 if (pci_using_dac) {
9a799d71 7784 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7785 netdev->vlan_features |= NETIF_F_HIGHDMA;
7786 }
9a799d71 7787
082757af
DS		 7788 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7789 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7790 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7791 netdev->features |= NETIF_F_LRO;
7792
9a799d71 7793 /* make sure the EEPROM is good */
c44ade9e 7794 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7795 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71
AK		 7796 err = -EIO;
7797 goto err_eeprom;
7798 }
7799
7800 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7801 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7802
c44ade9e 7803 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
849c4542 7804 e_dev_err("invalid MAC address\n");
9a799d71
AK		 7805 err = -EIO;
7806 goto err_eeprom;
7807 }
7808
7086400d
AD		 7809 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7810 (unsigned long) adapter);
9a799d71 7811
7086400d
AD		 7812 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7813 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7814
021230d4
AV		 7815 err = ixgbe_init_interrupt_scheme(adapter);
7816 if (err)
7817 goto err_sw_init;
9a799d71 7818
082757af
DS		 7819 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
7820 netdev->hw_features &= ~NETIF_F_RXHASH;
67a74ee2 7821 netdev->features &= ~NETIF_F_RXHASH;
082757af 7822 }
67a74ee2 7823
c23f5b6b
ET		 7824 /* WOL not supported for all but the following */
7825 adapter->wol = 0;
e8e26350 7826 switch (pdev->device) {
0b077fea 7827 case IXGBE_DEV_ID_82599_SFP:
0e22d043
DS		 7828 /* Only these subdevice supports WOL */
7829 switch (pdev->subsystem_device) {
7830 case IXGBE_SUBDEV_ID_82599_560FLR:
7831 /* only support first port */
7832 if (hw->bus.func != 0)
7833 break;
7834 case IXGBE_SUBDEV_ID_82599_SFP:
9417c464 7835 adapter->wol = IXGBE_WUFC_MAG;
0e22d043
DS		 7836 break;
7837 }
0b077fea 7838 break;
50d6c681
AD		 7839 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7840 /* All except this subdevice support WOL */
0b077fea 7841 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
9417c464 7842 adapter->wol = IXGBE_WUFC_MAG;
0b077fea 7843 break;
e8e26350 7844 case IXGBE_DEV_ID_82599_KX4:
9417c464 7845 adapter->wol = IXGBE_WUFC_MAG;
e8e26350 7846 break;
c23f5b6b
ET		 7847 case IXGBE_DEV_ID_X540T:
7848 /* Check eeprom to see if it is enabled */
7849 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
7850 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7851
7852 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7853 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7854 (hw->bus.func == 0)))
7855 adapter->wol = IXGBE_WUFC_MAG;
e8e26350
PW		 7856 break;
7857 }
e8e26350
PW		 7858 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7859
15e5209f
ET		 7860 /* save off EEPROM version number */
7861 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7862 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7863
04f165ef
PW		 7864 /* pick up the PCI bus settings for reporting later */
7865 hw->mac.ops.get_bus_info(hw);
7866
9a799d71 7867 /* print bus type/speed/width info */
849c4542 7868 e_dev_info("(PCI Express:%s:%s) %pM\n",
6716344c
DS		 7869 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7870 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7871 "Unknown"),
7872 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7873 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7874 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7875 "Unknown"),
7876 netdev->dev_addr);
289700db
DS		 7877
7878 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7879 if (err)
9fe93afd 7880 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7881 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7882 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7883 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7884 part_str);
e8e26350 7885 else
289700db
DS		 7886 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7887 hw->mac.type, hw->phy.type, part_str);
9a799d71 7888
e8e26350 7889 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
849c4542
ET		 7890 e_dev_warn("PCI-Express bandwidth available for this card is "
7891 "not sufficient for optimal performance.\n");
7892 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7893 "is required.\n");
0c254d86
AK		 7894 }
7895
9a799d71 7896 /* reset the hardware with the new settings */
794caeb2 7897 err = hw->mac.ops.start_hw(hw);
c44ade9e 7898
794caeb2
PWJ		 7899 if (err == IXGBE_ERR_EEPROM_VERSION) {
7900 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7901 e_dev_warn("This device is a pre-production adapter/LOM. "
7902 "Please be aware there may be issues associated "
7903 "with your hardware. If you are experiencing "
7904 "problems please contact your Intel or hardware "
7905 "representative who provided you with this "
7906 "hardware.\n");
794caeb2 7907 }
9a799d71
AK		 7908 strcpy(netdev->name, "eth%d");
7909 err = register_netdev(netdev);
7910 if (err)
7911 goto err_register;
7912
93d3ce8f
ET		 7913 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7914 if (hw->mac.ops.disable_tx_laser &&
7915 ((hw->phy.multispeed_fiber) ||
7916 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7917 (hw->mac.type == ixgbe_mac_82599EB))))
7918 hw->mac.ops.disable_tx_laser(hw);
7919
54386467
JB		 7920 /* carrier off reporting is important to ethtool even BEFORE open */
7921 netif_carrier_off(netdev);
7922
5dd2d332 7923#ifdef CONFIG_IXGBE_DCA
652f093f 7924 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7925 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7926 ixgbe_setup_dca(adapter);
7927 }
7928#endif
1cdd1ec8 7929 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7930 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7931 for (i = 0; i < adapter->num_vfs; i++)
7932 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7933 }
7934
2466dd9c
JK		 7935 /* firmware requires driver version to be 0xFFFFFFFF
7936 * since os does not support feature
7937 */
9612de92 7938 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7939 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7940 0xFF);
9612de92 7941
0365e6e4
PW		 7942 /* add san mac addr to netdev */
7943 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7944
ea81875a 7945 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71
AK		 7946 cards_found++;
7947 return 0;
7948
7949err_register:
5eba3699 7950 ixgbe_release_hw_control(adapter);
7a921c93 7951 ixgbe_clear_interrupt_scheme(adapter);
9a799d71
AK		 7952err_sw_init:
7953err_eeprom:
1cdd1ec8
GR		 7954 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7955 ixgbe_disable_sriov(adapter);
7086400d 7956 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7957 iounmap(hw->hw_addr);
7958err_ioremap:
7959 free_netdev(netdev);
7960err_alloc_etherdev:
e8e9f696
JP		 7961 pci_release_selected_regions(pdev,
7962 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7963err_pci_reg:
7964err_dma:
7965 pci_disable_device(pdev);
7966 return err;
7967}
7968
7969/**
7970 * ixgbe_remove - Device Removal Routine
7971 * @pdev: PCI device information struct
7972 *
7973 * ixgbe_remove is called by the PCI subsystem to alert the driver
7974 * that it should release a PCI device. The could be caused by a
7975 * Hot-Plug event, or because the driver is going to be removed from
7976 * memory.
7977 **/
7978static void __devexit ixgbe_remove(struct pci_dev *pdev)
7979{
c60fbb00
AD		 7980 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7981 struct net_device *netdev = adapter->netdev;
9a799d71
AK		 7982
7983 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7984 cancel_work_sync(&adapter->service_task);
9a799d71 7985
5dd2d332 7986#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7987 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7988 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7989 dca_remove_requester(&pdev->dev);
7990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7991 }
7992
7993#endif
332d4a7d
YZ		 7994#ifdef IXGBE_FCOE
7995 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7996 ixgbe_cleanup_fcoe(adapter);
7997
7998#endif /* IXGBE_FCOE */
0365e6e4
PW		 7999
8000 /* remove the added san mac */
8001 ixgbe_del_sanmac_netdev(netdev);
8002
c4900be0
DS		 8003 if (netdev->reg_state == NETREG_REGISTERED)
8004 unregister_netdev(netdev);
9a799d71 8005
c6bda30a
GR		 8006 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
8007 if (!(ixgbe_check_vf_assignment(adapter)))
8008 ixgbe_disable_sriov(adapter);
8009 else
8010 e_dev_warn("Unloading driver while VFs are assigned "
8011 "- VFs will not be deallocated\n");
8012 }
1cdd1ec8 8013
7a921c93 8014 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8015
021230d4 8016 ixgbe_release_hw_control(adapter);
9a799d71
AK		 8017
8018 iounmap(adapter->hw.hw_addr);
9ce77666 8019 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8020 IORESOURCE_MEM));
9a799d71 8021
849c4542 8022 e_dev_info("complete\n");
021230d4 8023
9a799d71
AK		 8024 free_netdev(netdev);
8025
19d5afd4 8026 pci_disable_pcie_error_reporting(pdev);
6fabd715 8027
9a799d71
AK		 8028 pci_disable_device(pdev);
8029}
8030
8031/**
8032 * ixgbe_io_error_detected - called when PCI error is detected
8033 * @pdev: Pointer to PCI device
8034 * @state: The current pci connection state
8035 *
8036 * This function is called after a PCI bus error affecting
8037 * this device has been detected.
8038 */
8039static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8040 pci_channel_state_t state)
9a799d71 8041{
c60fbb00
AD		 8042 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8043 struct net_device *netdev = adapter->netdev;
9a799d71 8044
83c61fa9
GR		 8045#ifdef CONFIG_PCI_IOV
8046 struct pci_dev *bdev, *vfdev;
8047 u32 dw0, dw1, dw2, dw3;
8048 int vf, pos;
8049 u16 req_id, pf_func;
8050
8051 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8052 adapter->num_vfs == 0)
8053 goto skip_bad_vf_detection;
8054
8055 bdev = pdev->bus->self;
8056 while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT))
8057 bdev = bdev->bus->self;
8058
8059 if (!bdev)
8060 goto skip_bad_vf_detection;
8061
8062 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8063 if (!pos)
8064 goto skip_bad_vf_detection;
8065
8066 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
8067 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
8068 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
8069 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
8070
8071 req_id = dw1 >> 16;
8072 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8073 if (!(req_id & 0x0080))
8074 goto skip_bad_vf_detection;
8075
8076 pf_func = req_id & 0x01;
8077 if ((pf_func & 1) == (pdev->devfn & 1)) {
8078 unsigned int device_id;
8079
8080 vf = (req_id & 0x7F) >> 1;
8081 e_dev_err("VF %d has caused a PCIe error\n", vf);
8082 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8083 "%8.8x\tdw3: %8.8x\n",
8084 dw0, dw1, dw2, dw3);
8085 switch (adapter->hw.mac.type) {
8086 case ixgbe_mac_82599EB:
8087 device_id = IXGBE_82599_VF_DEVICE_ID;
8088 break;
8089 case ixgbe_mac_X540:
8090 device_id = IXGBE_X540_VF_DEVICE_ID;
8091 break;
8092 default:
8093 device_id = 0;
8094 break;
8095 }
8096
8097 /* Find the pci device of the offending VF */
8098 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL);
8099 while (vfdev) {
8100 if (vfdev->devfn == (req_id & 0xFF))
8101 break;
8102 vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID,
8103 device_id, vfdev);
8104 }
8105 /*
8106 * There's a slim chance the VF could have been hot plugged,
8107 * so if it is no longer present we don't need to issue the
8108 * VFLR. Just clean up the AER in that case.
8109 */
8110 if (vfdev) {
8111 e_dev_err("Issuing VFLR to VF %d\n", vf);
8112 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
8113 }
8114
8115 pci_cleanup_aer_uncorrect_error_status(pdev);
8116 }
8117
8118 /*
8119 * Even though the error may have occurred on the other port
8120 * we still need to increment the vf error reference count for
8121 * both ports because the I/O resume function will be called
8122 * for both of them.
8123 */
8124 adapter->vferr_refcount++;
8125
8126 return PCI_ERS_RESULT_RECOVERED;
8127
8128skip_bad_vf_detection:
8129#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8130 netif_device_detach(netdev);
8131
3044b8d1
BL		 8132 if (state == pci_channel_io_perm_failure)
8133 return PCI_ERS_RESULT_DISCONNECT;
8134
9a799d71
AK		 8135 if (netif_running(netdev))
8136 ixgbe_down(adapter);
8137 pci_disable_device(pdev);
8138
b4617240 8139 /* Request a slot reset. */
9a799d71
AK		 8140 return PCI_ERS_RESULT_NEED_RESET;
8141}
8142
8143/**
8144 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8145 * @pdev: Pointer to PCI device
8146 *
8147 * Restart the card from scratch, as if from a cold-boot.
8148 */
8149static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8150{
c60fbb00 8151 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8152 pci_ers_result_t result;
8153 int err;
9a799d71 8154
9ce77666 8155 if (pci_enable_device_mem(pdev)) {
396e799c 8156 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8157 result = PCI_ERS_RESULT_DISCONNECT;
8158 } else {
8159 pci_set_master(pdev);
8160 pci_restore_state(pdev);
c0e1f68b 8161 pci_save_state(pdev);
9a799d71 8162
dd4d8ca6 8163 pci_wake_from_d3(pdev, false);
9a799d71 8164
6fabd715 8165 ixgbe_reset(adapter);
88512539 8166 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8167 result = PCI_ERS_RESULT_RECOVERED;
8168 }
8169
8170 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8171 if (err) {
849c4542
ET		 8172 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8173 "failed 0x%0x\n", err);
6fabd715
PWJ		 8174 /* non-fatal, continue */
8175 }
9a799d71 8176
6fabd715 8177 return result;
9a799d71
AK		 8178}
8179
8180/**
8181 * ixgbe_io_resume - called when traffic can start flowing again.
8182 * @pdev: Pointer to PCI device
8183 *
8184 * This callback is called when the error recovery driver tells us that
8185 * its OK to resume normal operation.
8186 */
8187static void ixgbe_io_resume(struct pci_dev *pdev)
8188{
c60fbb00
AD		 8189 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8190 struct net_device *netdev = adapter->netdev;
9a799d71 8191
83c61fa9
GR		 8192#ifdef CONFIG_PCI_IOV
8193 if (adapter->vferr_refcount) {
8194 e_info(drv, "Resuming after VF err\n");
8195 adapter->vferr_refcount--;
8196 return;
8197 }
8198
8199#endif
c7ccde0f
AD		 8200 if (netif_running(netdev))
8201 ixgbe_up(adapter);
9a799d71
AK		 8202
8203 netif_device_attach(netdev);
9a799d71
AK		 8204}
8205
8206static struct pci_error_handlers ixgbe_err_handler = {
8207 .error_detected = ixgbe_io_error_detected,
8208 .slot_reset = ixgbe_io_slot_reset,
8209 .resume = ixgbe_io_resume,
8210};
8211
8212static struct pci_driver ixgbe_driver = {
8213 .name = ixgbe_driver_name,
8214 .id_table = ixgbe_pci_tbl,
8215 .probe = ixgbe_probe,
8216 .remove = __devexit_p(ixgbe_remove),
8217#ifdef CONFIG_PM
8218 .suspend = ixgbe_suspend,
8219 .resume = ixgbe_resume,
8220#endif
8221 .shutdown = ixgbe_shutdown,
8222 .err_handler = &ixgbe_err_handler
8223};
8224
8225/**
8226 * ixgbe_init_module - Driver Registration Routine
8227 *
8228 * ixgbe_init_module is the first routine called when the driver is
8229 * loaded. All it does is register with the PCI subsystem.
8230 **/
8231static int __init ixgbe_init_module(void)
8232{
8233 int ret;
c7689578 8234 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8235 pr_info("%s\n", ixgbe_copyright);
9a799d71 8236
5dd2d332 8237#ifdef CONFIG_IXGBE_DCA
bd0362dd 8238 dca_register_notify(&dca_notifier);
bd0362dd 8239#endif
5dd2d332 8240
9a799d71
AK		 8241 ret = pci_register_driver(&ixgbe_driver);
8242 return ret;
8243}
b4617240 8244
9a799d71
AK		 8245module_init(ixgbe_init_module);
8246
8247/**
8248 * ixgbe_exit_module - Driver Exit Cleanup Routine
8249 *
8250 * ixgbe_exit_module is called just before the driver is removed
8251 * from memory.
8252 **/
8253static void __exit ixgbe_exit_module(void)
8254{
5dd2d332 8255#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8256 dca_unregister_notify(&dca_notifier);
8257#endif
9a799d71 8258 pci_unregister_driver(&ixgbe_driver);
1a51502b 8259 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8260}
bd0362dd 8261
5dd2d332 8262#ifdef CONFIG_IXGBE_DCA
bd0362dd 8263static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8264 void *p)
bd0362dd
JC		 8265{
8266 int ret_val;
8267
8268 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8269 __ixgbe_notify_dca);
bd0362dd
JC		 8270
8271 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8272}
b453368d 8273
5dd2d332 8274#endif /* CONFIG_IXGBE_DCA */
849c4542 8275
9a799d71
AK		 8276module_exit(ixgbe_exit_module);
8277
8278/* ixgbe_main.c */
Linux kernel - Deliverables
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