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ixgbe: call pcie_get_mimimum_link to check if device has enough bandwidth
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/types.h>
29#include <linux/module.h>
30#include <linux/pci.h>
31#include <linux/netdevice.h>
32#include <linux/vmalloc.h>
33#include <linux/string.h>
34#include <linux/in.h>
a6b7a407 35#include <linux/interrupt.h>
9a799d71
AK		 36#include <linux/ip.h>
37#include <linux/tcp.h>
897ab156 38#include <linux/sctp.h>
60127865 39#include <linux/pkt_sched.h>
9a799d71 40#include <linux/ipv6.h>
5a0e3ad6 41#include <linux/slab.h>
9a799d71
AK		 42#include <net/checksum.h>
43#include <net/ip6_checksum.h>
44#include <linux/ethtool.h>
01789349 45#include <linux/if.h>
9a799d71 46#include <linux/if_vlan.h>
815cccbf 47#include <linux/if_bridge.h>
70c71606 48#include <linux/prefetch.h>
eacd73f7 49#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 50
51#include "ixgbe.h"
52#include "ixgbe_common.h"
ee5f784a 53#include "ixgbe_dcb_82599.h"
1cdd1ec8 54#include "ixgbe_sriov.h"
9a799d71
AK		 55
56char ixgbe_driver_name[] = "ixgbe";
9c8eb720 57static const char ixgbe_driver_string[] =
e8e9f696 58 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 59#ifdef IXGBE_FCOE
ea81875a
NP		 60char ixgbe_default_device_descr[] =
61 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 62#else
63static char ixgbe_default_device_descr[] =
64 "Intel(R) 10 Gigabit Network Connection";
65#endif
93ac03be 66#define DRV_VERSION "3.15.1-k"
9c8eb720 67const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 68static const char ixgbe_copyright[] =
434c5e39 69 "Copyright (c) 1999-2013 Intel Corporation.";
9a799d71
AK		 70
71static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 72 [board_82598] = &ixgbe_82598_info,
e8e26350 73 [board_82599] = &ixgbe_82599_info,
fe15e8e1 74 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 75};
76
77/* ixgbe_pci_tbl - PCI Device ID Table
78 *
79 * Wildcard entries (PCI_ANY_ID) should come last
80 * Last entry must be all 0s
81 *
82 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
83 * Class, Class Mask, private data (not used) }
84 */
a3aa1884 85static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 86 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
7d145282 112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 115 /* required last entry */
116 {0, }
117};
118MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
119
5dd2d332 120#ifdef CONFIG_IXGBE_DCA
bd0362dd 121static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 122 void *p);
bd0362dd
JC		 123static struct notifier_block dca_notifier = {
124 .notifier_call = ixgbe_notify_dca,
125 .next = NULL,
126 .priority = 0
127};
128#endif
129
1cdd1ec8
GR		 130#ifdef CONFIG_PCI_IOV
131static unsigned int max_vfs;
132module_param(max_vfs, uint, 0);
e8e9f696 133MODULE_PARM_DESC(max_vfs,
6b42a9c5 134 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63");
1cdd1ec8
GR		 135#endif /* CONFIG_PCI_IOV */
136
8ef78adc
PWJ		 137static unsigned int allow_unsupported_sfp;
138module_param(allow_unsupported_sfp, uint, 0);
139MODULE_PARM_DESC(allow_unsupported_sfp,
140 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
141
b3f4d599 142#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
143static int debug = -1;
144module_param(debug, int, 0);
145MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
146
9a799d71
AK		 147MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
148MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
149MODULE_LICENSE("GPL");
150MODULE_VERSION(DRV_VERSION);
151
b8e82001
JK		 152static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
153 u32 reg, u16 *value)
154{
155 int pos = 0;
156 struct pci_dev *parent_dev;
157 struct pci_bus *parent_bus;
158
159 parent_bus = adapter->pdev->bus->parent;
160 if (!parent_bus)
161 return -1;
162
163 parent_dev = parent_bus->self;
164 if (!parent_dev)
165 return -1;
166
167 pos = pci_find_capability(parent_dev, PCI_CAP_ID_EXP);
168 if (!pos)
169 return -1;
170
171 pci_read_config_word(parent_dev, pos + reg, value);
172 return 0;
173}
174
175static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
176{
177 struct ixgbe_hw *hw = &adapter->hw;
178 u16 link_status = 0;
179 int err;
180
181 hw->bus.type = ixgbe_bus_type_pci_express;
182
183 /* Get the negotiated link width and speed from PCI config space of the
184 * parent, as this device is behind a switch
185 */
186 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
187
188 /* assume caller will handle error case */
189 if (err)
190 return err;
191
192 hw->bus.width = ixgbe_convert_bus_width(link_status);
193 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
194
195 return 0;
196}
197
e027d1ae
JK		 198/**
199 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
200 * @hw: hw specific details
201 *
202 * This function is used by probe to determine whether a device's PCI-Express
203 * bandwidth details should be gathered from the parent bus instead of from the
204 * device. Used to ensure that various locations all have the correct device ID
205 * checks.
206 */
207static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
208{
209 switch (hw->device_id) {
210 case IXGBE_DEV_ID_82599_SFP_SF_QP:
211 return true;
212 default:
213 return false;
214 }
215}
216
217static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
218 int expected_gts)
219{
220 int max_gts = 0;
221 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
222 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
223 struct pci_dev *pdev;
224
225 /* determine whether to use the the parent device
226 */
227 if (ixgbe_pcie_from_parent(&adapter->hw))
228 pdev = adapter->pdev->bus->parent->self;
229 else
230 pdev = adapter->pdev;
231
232 if (pcie_get_minimum_link(pdev, &speed, &width) ||
233 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
234 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
235 return;
236 }
237
238 switch (speed) {
239 case PCIE_SPEED_2_5GT:
240 /* 8b/10b encoding reduces max throughput by 20% */
241 max_gts = 2 * width;
242 break;
243 case PCIE_SPEED_5_0GT:
244 /* 8b/10b encoding reduces max throughput by 20% */
245 max_gts = 4 * width;
246 break;
247 case PCIE_SPEED_8_0GT:
248 /* 128b/130b encoding only reduces throughput by 1% */
249 max_gts = 8 * width;
250 break;
251 default:
252 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
253 return;
254 }
255
256 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
257 max_gts);
258 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
259 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
260 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
261 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
262 "Unknown"),
263 width,
264 (speed == PCIE_SPEED_2_5GT ? "20%" :
265 speed == PCIE_SPEED_5_0GT ? "20%" :
266 speed == PCIE_SPEED_8_0GT ? "N/a" :
267 "Unknown"));
268
269 if (max_gts < expected_gts) {
270 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
271 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
272 expected_gts);
273 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
274 }
275}
276
7086400d
AD		 277static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
278{
279 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
280 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
281 schedule_work(&adapter->service_task);
282}
283
284static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
285{
286 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
287
52f33af8 288 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 289 smp_mb__before_clear_bit();
290 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
291}
292
dcd79aeb
TI		 293struct ixgbe_reg_info {
294 u32 ofs;
295 char *name;
296};
297
298static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
299
300 /* General Registers */
301 {IXGBE_CTRL, "CTRL"},
302 {IXGBE_STATUS, "STATUS"},
303 {IXGBE_CTRL_EXT, "CTRL_EXT"},
304
305 /* Interrupt Registers */
306 {IXGBE_EICR, "EICR"},
307
308 /* RX Registers */
309 {IXGBE_SRRCTL(0), "SRRCTL"},
310 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
311 {IXGBE_RDLEN(0), "RDLEN"},
312 {IXGBE_RDH(0), "RDH"},
313 {IXGBE_RDT(0), "RDT"},
314 {IXGBE_RXDCTL(0), "RXDCTL"},
315 {IXGBE_RDBAL(0), "RDBAL"},
316 {IXGBE_RDBAH(0), "RDBAH"},
317
318 /* TX Registers */
319 {IXGBE_TDBAL(0), "TDBAL"},
320 {IXGBE_TDBAH(0), "TDBAH"},
321 {IXGBE_TDLEN(0), "TDLEN"},
322 {IXGBE_TDH(0), "TDH"},
323 {IXGBE_TDT(0), "TDT"},
324 {IXGBE_TXDCTL(0), "TXDCTL"},
325
326 /* List Terminator */
327 {}
328};
329
330
331/*
332 * ixgbe_regdump - register printout routine
333 */
334static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
335{
336 int i = 0, j = 0;
337 char rname[16];
338 u32 regs[64];
339
340 switch (reginfo->ofs) {
341 case IXGBE_SRRCTL(0):
342 for (i = 0; i < 64; i++)
343 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
344 break;
345 case IXGBE_DCA_RXCTRL(0):
346 for (i = 0; i < 64; i++)
347 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
348 break;
349 case IXGBE_RDLEN(0):
350 for (i = 0; i < 64; i++)
351 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
352 break;
353 case IXGBE_RDH(0):
354 for (i = 0; i < 64; i++)
355 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
356 break;
357 case IXGBE_RDT(0):
358 for (i = 0; i < 64; i++)
359 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
360 break;
361 case IXGBE_RXDCTL(0):
362 for (i = 0; i < 64; i++)
363 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
364 break;
365 case IXGBE_RDBAL(0):
366 for (i = 0; i < 64; i++)
367 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
368 break;
369 case IXGBE_RDBAH(0):
370 for (i = 0; i < 64; i++)
371 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
372 break;
373 case IXGBE_TDBAL(0):
374 for (i = 0; i < 64; i++)
375 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
376 break;
377 case IXGBE_TDBAH(0):
378 for (i = 0; i < 64; i++)
379 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
380 break;
381 case IXGBE_TDLEN(0):
382 for (i = 0; i < 64; i++)
383 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
384 break;
385 case IXGBE_TDH(0):
386 for (i = 0; i < 64; i++)
387 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
388 break;
389 case IXGBE_TDT(0):
390 for (i = 0; i < 64; i++)
391 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
392 break;
393 case IXGBE_TXDCTL(0):
394 for (i = 0; i < 64; i++)
395 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
396 break;
397 default:
c7689578 398 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 399 IXGBE_READ_REG(hw, reginfo->ofs));
400 return;
401 }
402
403 for (i = 0; i < 8; i++) {
404 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 405 pr_err("%-15s", rname);
dcd79aeb 406 for (j = 0; j < 8; j++)
c7689578
JP		 407 pr_cont(" %08x", regs[i*8+j]);
408 pr_cont("\n");
dcd79aeb
TI		 409 }
410
411}
412
413/*
414 * ixgbe_dump - Print registers, tx-rings and rx-rings
415 */
416static void ixgbe_dump(struct ixgbe_adapter *adapter)
417{
418 struct net_device *netdev = adapter->netdev;
419 struct ixgbe_hw *hw = &adapter->hw;
420 struct ixgbe_reg_info *reginfo;
421 int n = 0;
422 struct ixgbe_ring *tx_ring;
729739b7 423 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 424 union ixgbe_adv_tx_desc *tx_desc;
425 struct my_u0 { u64 a; u64 b; } *u0;
426 struct ixgbe_ring *rx_ring;
427 union ixgbe_adv_rx_desc *rx_desc;
428 struct ixgbe_rx_buffer *rx_buffer_info;
429 u32 staterr;
430 int i = 0;
431
432 if (!netif_msg_hw(adapter))
433 return;
434
435 /* Print netdevice Info */
436 if (netdev) {
437 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 438 pr_info("Device Name state "
dcd79aeb 439 "trans_start last_rx\n");
c7689578
JP		 440 pr_info("%-15s %016lX %016lX %016lX\n",
441 netdev->name,
442 netdev->state,
443 netdev->trans_start,
444 netdev->last_rx);
dcd79aeb
TI		 445 }
446
447 /* Print Registers */
448 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 449 pr_info(" Register Name Value\n");
dcd79aeb
TI		 450 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
451 reginfo->name; reginfo++) {
452 ixgbe_regdump(hw, reginfo);
453 }
454
455 /* Print TX Ring Summary */
456 if (!netdev || !netif_running(netdev))
457 goto exit;
458
459 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 460 pr_info(" %s %s %s %s\n",
461 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
462 "leng", "ntw", "timestamp");
dcd79aeb
TI		 463 for (n = 0; n < adapter->num_tx_queues; n++) {
464 tx_ring = adapter->tx_ring[n];
729739b7 465 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 466 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 467 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 468 (u64)dma_unmap_addr(tx_buffer, dma),
469 dma_unmap_len(tx_buffer, len),
470 tx_buffer->next_to_watch,
471 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 472 }
473
474 /* Print TX Rings */
475 if (!netif_msg_tx_done(adapter))
476 goto rx_ring_summary;
477
478 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
479
480 /* Transmit Descriptor Formats
481 *
39ac868a 482 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 483 * +--------------------------------------------------------------+
484 * 0 | Buffer Address [63:0] |
485 * +--------------------------------------------------------------+
39ac868a 486 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 487 * +--------------------------------------------------------------+
488 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 489 *
490 * 82598 Advanced Transmit Descriptor (Write-Back Format)
491 * +--------------------------------------------------------------+
492 * 0 | RSV [63:0] |
493 * +--------------------------------------------------------------+
494 * 8 | RSV | STA | NXTSEQ |
495 * +--------------------------------------------------------------+
496 * 63 36 35 32 31 0
497 *
498 * 82599+ Advanced Transmit Descriptor
499 * +--------------------------------------------------------------+
500 * 0 | Buffer Address [63:0] |
501 * +--------------------------------------------------------------+
502 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
503 * +--------------------------------------------------------------+
504 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
505 *
506 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
507 * +--------------------------------------------------------------+
508 * 0 | RSV [63:0] |
509 * +--------------------------------------------------------------+
510 * 8 | RSV | STA | RSV |
511 * +--------------------------------------------------------------+
512 * 63 36 35 32 31 0
dcd79aeb
TI		 513 */
514
515 for (n = 0; n < adapter->num_tx_queues; n++) {
516 tx_ring = adapter->tx_ring[n];
c7689578
JP		 517 pr_info("------------------------------------\n");
518 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
519 pr_info("------------------------------------\n");
8ad88e37
JH		 520 pr_info("%s%s %s %s %s %s\n",
521 "T [desc] [address 63:0 ] ",
522 "[PlPOIdStDDt Ln] [bi->dma ] ",
523 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 524
525 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 526 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 527 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 528 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 529 if (dma_unmap_len(tx_buffer, len) > 0) {
530 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
531 i,
532 le64_to_cpu(u0->a),
533 le64_to_cpu(u0->b),
534 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 535 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 536 tx_buffer->next_to_watch,
537 (u64)tx_buffer->time_stamp,
538 tx_buffer->skb);
539 if (i == tx_ring->next_to_use &&
540 i == tx_ring->next_to_clean)
541 pr_cont(" NTC/U\n");
542 else if (i == tx_ring->next_to_use)
543 pr_cont(" NTU\n");
544 else if (i == tx_ring->next_to_clean)
545 pr_cont(" NTC\n");
546 else
547 pr_cont("\n");
548
549 if (netif_msg_pktdata(adapter) &&
550 tx_buffer->skb)
551 print_hex_dump(KERN_INFO, "",
552 DUMP_PREFIX_ADDRESS, 16, 1,
553 tx_buffer->skb->data,
554 dma_unmap_len(tx_buffer, len),
555 true);
556 }
dcd79aeb
TI		 557 }
558 }
559
560 /* Print RX Rings Summary */
561rx_ring_summary:
562 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 563 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 564 for (n = 0; n < adapter->num_rx_queues; n++) {
565 rx_ring = adapter->rx_ring[n];
c7689578
JP		 566 pr_info("%5d %5X %5X\n",
567 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 568 }
569
570 /* Print RX Rings */
571 if (!netif_msg_rx_status(adapter))
572 goto exit;
573
574 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
575
39ac868a
JH		 576 /* Receive Descriptor Formats
577 *
578 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 579 * 63 1 0
580 * +-----------------------------------------------------+
581 * 0 | Packet Buffer Address [63:1] |A0/NSE|
582 * +----------------------------------------------+------+
583 * 8 | Header Buffer Address [63:1] | DD |
584 * +-----------------------------------------------------+
585 *
586 *
39ac868a 587 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 588 *
589 * 63 48 47 32 31 30 21 20 16 15 4 3 0
590 * +------------------------------------------------------+
39ac868a
JH		 591 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
592 * | Packet | IP | | | | Type | Type |
593 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 594 * +------------------------------------------------------+
595 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
596 * +------------------------------------------------------+
597 * 63 48 47 32 31 20 19 0
39ac868a
JH		 598 *
599 * 82599+ Advanced Receive Descriptor (Read) Format
600 * 63 1 0
601 * +-----------------------------------------------------+
602 * 0 | Packet Buffer Address [63:1] |A0/NSE|
603 * +----------------------------------------------+------+
604 * 8 | Header Buffer Address [63:1] | DD |
605 * +-----------------------------------------------------+
606 *
607 *
608 * 82599+ Advanced Receive Descriptor (Write-Back) Format
609 *
610 * 63 48 47 32 31 30 21 20 17 16 4 3 0
611 * +------------------------------------------------------+
612 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
613 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
614 * |/ Flow Dir Flt ID | | | | | |
615 * +------------------------------------------------------+
616 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
617 * +------------------------------------------------------+
618 * 63 48 47 32 31 20 19 0
dcd79aeb 619 */
39ac868a 620
dcd79aeb
TI		 621 for (n = 0; n < adapter->num_rx_queues; n++) {
622 rx_ring = adapter->rx_ring[n];
c7689578
JP		 623 pr_info("------------------------------------\n");
624 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
625 pr_info("------------------------------------\n");
8ad88e37
JH		 626 pr_info("%s%s%s",
627 "R [desc] [ PktBuf A0] ",
628 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 629 "<-- Adv Rx Read format\n");
8ad88e37
JH		 630 pr_info("%s%s%s",
631 "RWB[desc] [PcsmIpSHl PtRs] ",
632 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 633 "<-- Adv Rx Write-Back format\n");
634
635 for (i = 0; i < rx_ring->count; i++) {
636 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 637 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 638 u0 = (struct my_u0 *)rx_desc;
639 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
640 if (staterr & IXGBE_RXD_STAT_DD) {
641 /* Descriptor Done */
c7689578 642 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 643 "%016llX ---------------- %p", i,
644 le64_to_cpu(u0->a),
645 le64_to_cpu(u0->b),
646 rx_buffer_info->skb);
647 } else {
c7689578 648 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 649 "%016llX %016llX %p", i,
650 le64_to_cpu(u0->a),
651 le64_to_cpu(u0->b),
652 (u64)rx_buffer_info->dma,
653 rx_buffer_info->skb);
654
9c50c035
ET		 655 if (netif_msg_pktdata(adapter) &&
656 rx_buffer_info->dma) {
dcd79aeb
TI		 657 print_hex_dump(KERN_INFO, "",
658 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 659 page_address(rx_buffer_info->page) +
660 rx_buffer_info->page_offset,
f800326d 661 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 662 }
663 }
664
665 if (i == rx_ring->next_to_use)
c7689578 666 pr_cont(" NTU\n");
dcd79aeb 667 else if (i == rx_ring->next_to_clean)
c7689578 668 pr_cont(" NTC\n");
dcd79aeb 669 else
c7689578 670 pr_cont("\n");
dcd79aeb
TI		 671
672 }
673 }
674
675exit:
676 return;
677}
678
5eba3699
AV		 679static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
680{
681 u32 ctrl_ext;
682
683 /* Let firmware take over control of h/w */
684 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
685 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 686 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 687}
688
689static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
690{
691 u32 ctrl_ext;
692
693 /* Let firmware know the driver has taken over */
694 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 696 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 697}
9a799d71 698
49ce9c2c 699/**
e8e26350
PW		 700 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
701 * @adapter: pointer to adapter struct
702 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
703 * @queue: queue to map the corresponding interrupt to
704 * @msix_vector: the vector to map to the corresponding queue
705 *
706 */
707static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 708 u8 queue, u8 msix_vector)
9a799d71
AK		 709{
710 u32 ivar, index;
e8e26350
PW		 711 struct ixgbe_hw *hw = &adapter->hw;
712 switch (hw->mac.type) {
713 case ixgbe_mac_82598EB:
714 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
715 if (direction == -1)
716 direction = 0;
717 index = (((direction * 64) + queue) >> 2) & 0x1F;
718 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
719 ivar &= ~(0xFF << (8 * (queue & 0x3)));
720 ivar |= (msix_vector << (8 * (queue & 0x3)));
721 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
722 break;
723 case ixgbe_mac_82599EB:
b93a2226 724 case ixgbe_mac_X540:
e8e26350
PW		 725 if (direction == -1) {
726 /* other causes */
727 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
728 index = ((queue & 1) * 8);
729 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
730 ivar &= ~(0xFF << index);
731 ivar |= (msix_vector << index);
732 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
733 break;
734 } else {
735 /* tx or rx causes */
736 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
737 index = ((16 * (queue & 1)) + (8 * direction));
738 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
739 ivar &= ~(0xFF << index);
740 ivar |= (msix_vector << index);
741 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
742 break;
743 }
744 default:
745 break;
746 }
9a799d71
AK		 747}
748
fe49f04a 749static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 750 u64 qmask)
fe49f04a
AD		 751{
752 u32 mask;
753
bd508178
AD		 754 switch (adapter->hw.mac.type) {
755 case ixgbe_mac_82598EB:
fe49f04a
AD		 756 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
757 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 758 break;
759 case ixgbe_mac_82599EB:
b93a2226 760 case ixgbe_mac_X540:
fe49f04a
AD		 761 mask = (qmask & 0xFFFFFFFF);
762 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
763 mask = (qmask >> 32);
764 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 765 break;
766 default:
767 break;
fe49f04a
AD		 768 }
769}
770
729739b7
AD		 771void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
772 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 773{
729739b7
AD		 774 if (tx_buffer->skb) {
775 dev_kfree_skb_any(tx_buffer->skb);
776 if (dma_unmap_len(tx_buffer, len))
d3d00239 777 dma_unmap_single(ring->dev,
729739b7
AD		 778 dma_unmap_addr(tx_buffer, dma),
779 dma_unmap_len(tx_buffer, len),
780 DMA_TO_DEVICE);
781 } else if (dma_unmap_len(tx_buffer, len)) {
782 dma_unmap_page(ring->dev,
783 dma_unmap_addr(tx_buffer, dma),
784 dma_unmap_len(tx_buffer, len),
785 DMA_TO_DEVICE);
e5a43549 786 }
729739b7
AD		 787 tx_buffer->next_to_watch = NULL;
788 tx_buffer->skb = NULL;
789 dma_unmap_len_set(tx_buffer, len, 0);
790 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 791}
792
943561d3 793static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 794{
795 struct ixgbe_hw *hw = &adapter->hw;
796 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 797 int i;
943561d3 798 u32 data;
c84d324c 799
943561d3
AD		 800 if ((hw->fc.current_mode != ixgbe_fc_full) &&
801 (hw->fc.current_mode != ixgbe_fc_rx_pause))
802 return;
c84d324c 803
943561d3
AD		 804 switch (hw->mac.type) {
805 case ixgbe_mac_82598EB:
806 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
807 break;
808 default:
809 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
810 }
811 hwstats->lxoffrxc += data;
c84d324c 812
943561d3
AD		 813 /* refill credits (no tx hang) if we received xoff */
814 if (!data)
c84d324c 815 return;
943561d3
AD		 816
817 for (i = 0; i < adapter->num_tx_queues; i++)
818 clear_bit(__IXGBE_HANG_CHECK_ARMED,
819 &adapter->tx_ring[i]->state);
820}
821
822static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
823{
824 struct ixgbe_hw *hw = &adapter->hw;
825 struct ixgbe_hw_stats *hwstats = &adapter->stats;
826 u32 xoff[8] = {0};
2afaa00d 827 u8 tc;
943561d3
AD		 828 int i;
829 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
830
831 if (adapter->ixgbe_ieee_pfc)
832 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
833
834 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
835 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 836 return;
943561d3 837 }
c84d324c
JF		 838
839 /* update stats for each tc, only valid with PFC enabled */
840 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 841 u32 pxoffrxc;
842
c84d324c
JF		 843 switch (hw->mac.type) {
844 case ixgbe_mac_82598EB:
2afaa00d 845 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 846 break;
c84d324c 847 default:
2afaa00d 848 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 849 }
2afaa00d
PN		 850 hwstats->pxoffrxc[i] += pxoffrxc;
851 /* Get the TC for given UP */
852 tc = netdev_get_prio_tc_map(adapter->netdev, i);
853 xoff[tc] += pxoffrxc;
c84d324c
JF		 854 }
855
856 /* disarm tx queues that have received xoff frames */
857 for (i = 0; i < adapter->num_tx_queues; i++) {
858 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 859
2afaa00d 860 tc = tx_ring->dcb_tc;
c84d324c
JF		 861 if (xoff[tc])
862 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 863 }
26f23d82
YZ		 864}
865
c84d324c 866static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 867{
7d7ce682 868 return ring->stats.packets;
c84d324c
JF		 869}
870
871static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
872{
873 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
e01c31a5 874 struct ixgbe_hw *hw = &adapter->hw;
e01c31a5 875
c84d324c
JF		 876 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
877 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
878
879 if (head != tail)
880 return (head < tail) ?
881 tail - head : (tail + ring->count - head);
882
883 return 0;
884}
885
886static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
887{
888 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
889 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
890 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
891 bool ret = false;
892
7d637bcc 893 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 894
895 /*
896 * Check for a hung queue, but be thorough. This verifies
897 * that a transmit has been completed since the previous
898 * check AND there is at least one packet pending. The
899 * ARMED bit is set to indicate a potential hang. The
900 * bit is cleared if a pause frame is received to remove
901 * false hang detection due to PFC or 802.3x frames. By
902 * requiring this to fail twice we avoid races with
903 * pfc clearing the ARMED bit and conditions where we
904 * run the check_tx_hang logic with a transmit completion
905 * pending but without time to complete it yet.
906 */
907 if ((tx_done_old == tx_done) && tx_pending) {
908 /* make sure it is true for two checks in a row */
909 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
910 &tx_ring->state);
911 } else {
912 /* update completed stats and continue */
913 tx_ring->tx_stats.tx_done_old = tx_done;
914 /* reset the countdown */
915 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 916 }
917
c84d324c 918 return ret;
9a799d71
AK		 919}
920
c83c6cbd
AD		 921/**
922 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
923 * @adapter: driver private struct
924 **/
925static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
926{
927
928 /* Do the reset outside of interrupt context */
929 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
930 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 931 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 932 ixgbe_service_event_schedule(adapter);
933 }
934}
e01c31a5 935
9a799d71
AK		 936/**
937 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 938 * @q_vector: structure containing interrupt and ring information
e01c31a5 939 * @tx_ring: tx ring to clean
9a799d71 940 **/
fe49f04a 941static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 942 struct ixgbe_ring *tx_ring)
9a799d71 943{
fe49f04a 944 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 945 struct ixgbe_tx_buffer *tx_buffer;
946 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 947 unsigned int total_bytes = 0, total_packets = 0;
59224555 948 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 949 unsigned int i = tx_ring->next_to_clean;
950
951 if (test_bit(__IXGBE_DOWN, &adapter->state))
952 return true;
9a799d71 953
d3d00239 954 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 955 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 956 i -= tx_ring->count;
12207e49 957
729739b7 958 do {
d3d00239
AD		 959 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
960
961 /* if next_to_watch is not set then there is no work pending */
962 if (!eop_desc)
963 break;
964
7f83a9e6 965 /* prevent any other reads prior to eop_desc */
7e63bf49 966 read_barrier_depends();
7f83a9e6 967
d3d00239
AD		 968 /* if DD is not set pending work has not been completed */
969 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
970 break;
8ad494b0 971
d3d00239
AD		 972 /* clear next_to_watch to prevent false hangs */
973 tx_buffer->next_to_watch = NULL;
8ad494b0 974
091a6246
AD		 975 /* update the statistics for this packet */
976 total_bytes += tx_buffer->bytecount;
977 total_packets += tx_buffer->gso_segs;
978
fd0db0ed
AD		 979 /* free the skb */
980 dev_kfree_skb_any(tx_buffer->skb);
981
729739b7
AD		 982 /* unmap skb header data */
983 dma_unmap_single(tx_ring->dev,
984 dma_unmap_addr(tx_buffer, dma),
985 dma_unmap_len(tx_buffer, len),
986 DMA_TO_DEVICE);
987
fd0db0ed
AD		 988 /* clear tx_buffer data */
989 tx_buffer->skb = NULL;
729739b7 990 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 991
729739b7
AD		 992 /* unmap remaining buffers */
993 while (tx_desc != eop_desc) {
d3d00239
AD		 994 tx_buffer++;
995 tx_desc++;
8ad494b0 996 i++;
729739b7
AD		 997 if (unlikely(!i)) {
998 i -= tx_ring->count;
d3d00239 999 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1000 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1001 }
e01c31a5 1002
729739b7
AD		 1003 /* unmap any remaining paged data */
1004 if (dma_unmap_len(tx_buffer, len)) {
1005 dma_unmap_page(tx_ring->dev,
1006 dma_unmap_addr(tx_buffer, dma),
1007 dma_unmap_len(tx_buffer, len),
1008 DMA_TO_DEVICE);
1009 dma_unmap_len_set(tx_buffer, len, 0);
1010 }
1011 }
1012
1013 /* move us one more past the eop_desc for start of next pkt */
1014 tx_buffer++;
1015 tx_desc++;
1016 i++;
1017 if (unlikely(!i)) {
1018 i -= tx_ring->count;
1019 tx_buffer = tx_ring->tx_buffer_info;
1020 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1021 }
1022
1023 /* issue prefetch for next Tx descriptor */
1024 prefetch(tx_desc);
12207e49 1025
729739b7
AD		 1026 /* update budget accounting */
1027 budget--;
1028 } while (likely(budget));
1029
1030 i += tx_ring->count;
9a799d71 1031 tx_ring->next_to_clean = i;
d3d00239 1032 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1033 tx_ring->stats.bytes += total_bytes;
bd198058 1034 tx_ring->stats.packets += total_packets;
d3d00239 1035 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1036 q_vector->tx.total_bytes += total_bytes;
1037 q_vector->tx.total_packets += total_packets;
b953799e 1038
c84d324c
JF		 1039 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1040 /* schedule immediate reset if we believe we hung */
1041 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1042 e_err(drv, "Detected Tx Unit Hang\n"
1043 " Tx Queue <%d>\n"
1044 " TDH, TDT <%x>, <%x>\n"
1045 " next_to_use <%x>\n"
1046 " next_to_clean <%x>\n"
1047 "tx_buffer_info[next_to_clean]\n"
1048 " time_stamp <%lx>\n"
1049 " jiffies <%lx>\n",
1050 tx_ring->queue_index,
1051 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1052 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1053 tx_ring->next_to_use, i,
1054 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1055
1056 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1057
1058 e_info(probe,
1059 "tx hang %d detected on queue %d, resetting adapter\n",
1060 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1061
b953799e 1062 /* schedule immediate reset if we believe we hung */
c83c6cbd 1063 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1064
1065 /* the adapter is about to reset, no point in enabling stuff */
59224555 1066 return true;
b953799e 1067 }
9a799d71 1068
b2d96e0a
AD		 1069 netdev_tx_completed_queue(txring_txq(tx_ring),
1070 total_packets, total_bytes);
1071
e092be60 1072#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1073 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1074 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1075 /* Make sure that anybody stopping the queue after this
1076 * sees the new next_to_clean.
1077 */
1078 smp_mb();
729739b7
AD		 1079 if (__netif_subqueue_stopped(tx_ring->netdev,
1080 tx_ring->queue_index)
1081 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1082 netif_wake_subqueue(tx_ring->netdev,
1083 tx_ring->queue_index);
5b7da515 1084 ++tx_ring->tx_stats.restart_queue;
30eba97a 1085 }
e092be60 1086 }
9a799d71 1087
59224555 1088 return !!budget;
9a799d71
AK		 1089}
1090
5dd2d332 1091#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1092static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1093 struct ixgbe_ring *tx_ring,
33cf09c9 1094 int cpu)
bd0362dd 1095{
33cf09c9 1096 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1097 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1098 u16 reg_offset;
33cf09c9 1099
33cf09c9
AD		 1100 switch (hw->mac.type) {
1101 case ixgbe_mac_82598EB:
bdda1a61 1102 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1103 break;
1104 case ixgbe_mac_82599EB:
b93a2226 1105 case ixgbe_mac_X540:
bdda1a61
AD		 1106 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1107 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1108 break;
1109 default:
bdda1a61
AD		 1110 /* for unknown hardware do not write register */
1111 return;
bd0362dd 1112 }
bdda1a61
AD		 1113
1114 /*
1115 * We can enable relaxed ordering for reads, but not writes when
1116 * DCA is enabled. This is due to a known issue in some chipsets
1117 * which will cause the DCA tag to be cleared.
1118 */
1119 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1120 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1121 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1122
1123 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1124}
1125
bdda1a61
AD		 1126static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1127 struct ixgbe_ring *rx_ring,
33cf09c9 1128 int cpu)
bd0362dd 1129{
33cf09c9 1130 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1131 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1132 u8 reg_idx = rx_ring->reg_idx;
1133
33cf09c9
AD		 1134
1135 switch (hw->mac.type) {
33cf09c9 1136 case ixgbe_mac_82599EB:
b93a2226 1137 case ixgbe_mac_X540:
bdda1a61 1138 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1139 break;
1140 default:
1141 break;
1142 }
bdda1a61
AD		 1143
1144 /*
1145 * We can enable relaxed ordering for reads, but not writes when
1146 * DCA is enabled. This is due to a known issue in some chipsets
1147 * which will cause the DCA tag to be cleared.
1148 */
1149 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1150 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1151
1152 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1153}
1154
1155static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1156{
1157 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1158 struct ixgbe_ring *ring;
bd0362dd 1159 int cpu = get_cpu();
bd0362dd 1160
33cf09c9
AD		 1161 if (q_vector->cpu == cpu)
1162 goto out_no_update;
1163
a557928e 1164 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1165 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1166
a557928e 1167 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1168 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1169
1170 q_vector->cpu = cpu;
1171out_no_update:
bd0362dd
JC		 1172 put_cpu();
1173}
1174
1175static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1176{
1177 int i;
1178
1179 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1180 return;
1181
e35ec126
AD		 1182 /* always use CB2 mode, difference is masked in the CB driver */
1183 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1184
49c7ffbe 1185 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1186 adapter->q_vector[i]->cpu = -1;
1187 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1188 }
1189}
1190
1191static int __ixgbe_notify_dca(struct device *dev, void *data)
1192{
c60fbb00 1193 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1194 unsigned long event = *(unsigned long *)data;
1195
2a72c31e 1196 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1197 return 0;
1198
bd0362dd
JC		 1199 switch (event) {
1200 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1201 /* if we're already enabled, don't do it again */
1202 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1203 break;
652f093f 1204 if (dca_add_requester(dev) == 0) {
96b0e0f6 1205 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1206 ixgbe_setup_dca(adapter);
1207 break;
1208 }
1209 /* Fall Through since DCA is disabled. */
1210 case DCA_PROVIDER_REMOVE:
1211 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1212 dca_remove_requester(dev);
1213 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1214 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1215 }
1216 break;
1217 }
1218
652f093f 1219 return 0;
bd0362dd 1220}
67a74ee2 1221
bdda1a61 1222#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1223static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1224 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1225 struct sk_buff *skb)
1226{
8a0da21b
AD		 1227 if (ring->netdev->features & NETIF_F_RXHASH)
1228 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
67a74ee2
ET		 1229}
1230
f800326d 1231#ifdef IXGBE_FCOE
ff886dfc
AD		 1232/**
1233 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1234 * @ring: structure containing ring specific data
ff886dfc
AD		 1235 * @rx_desc: advanced rx descriptor
1236 *
1237 * Returns : true if it is FCoE pkt
1238 */
57efd44c 1239static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1240 union ixgbe_adv_rx_desc *rx_desc)
1241{
1242 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1243
57efd44c 1244 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1245 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1246 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1247 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1248}
1249
f800326d 1250#endif /* IXGBE_FCOE */
e59bd25d
AV		 1251/**
1252 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1253 * @ring: structure containing ring specific data
1254 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1255 * @skb: skb currently being received and modified
1256 **/
8a0da21b 1257static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1258 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1259 struct sk_buff *skb)
9a799d71 1260{
8a0da21b 1261 skb_checksum_none_assert(skb);
9a799d71 1262
712744be 1263 /* Rx csum disabled */
8a0da21b 1264 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1265 return;
e59bd25d
AV		 1266
1267 /* if IP and error */
f56e0cb1
AD		 1268 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1269 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1270 ring->rx_stats.csum_err++;
9a799d71
AK		 1271 return;
1272 }
e59bd25d 1273
f56e0cb1 1274 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1275 return;
1276
f56e0cb1 1277 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1278 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1279
1280 /*
1281 * 82599 errata, UDP frames with a 0 checksum can be marked as
1282 * checksum errors.
1283 */
8a0da21b
AD		 1284 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1285 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1286 return;
1287
8a0da21b 1288 ring->rx_stats.csum_err++;
e59bd25d
AV		 1289 return;
1290 }
1291
9a799d71 1292 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1293 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1294}
1295
84ea2591 1296static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1297{
f56e0cb1 1298 rx_ring->next_to_use = val;
f800326d
AD		 1299
1300 /* update next to alloc since we have filled the ring */
1301 rx_ring->next_to_alloc = val;
e8e26350
PW		 1302 /*
1303 * Force memory writes to complete before letting h/w
1304 * know there are new descriptors to fetch. (Only
1305 * applicable for weak-ordered memory model archs,
1306 * such as IA-64).
1307 */
1308 wmb();
84ea2591 1309 writel(val, rx_ring->tail);
e8e26350
PW		 1310}
1311
f990b79b
AD		 1312static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1313 struct ixgbe_rx_buffer *bi)
1314{
1315 struct page *page = bi->page;
f800326d 1316 dma_addr_t dma = bi->dma;
f990b79b 1317
f800326d
AD		 1318 /* since we are recycling buffers we should seldom need to alloc */
1319 if (likely(dma))
f990b79b
AD		 1320 return true;
1321
f800326d
AD		 1322 /* alloc new page for storage */
1323 if (likely(!page)) {
0614002b
MG		 1324 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1325 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1326 if (unlikely(!page)) {
1327 rx_ring->rx_stats.alloc_rx_page_failed++;
1328 return false;
1329 }
f800326d 1330 bi->page = page;
f990b79b
AD		 1331 }
1332
f800326d
AD		 1333 /* map page for use */
1334 dma = dma_map_page(rx_ring->dev, page, 0,
1335 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1336
1337 /*
1338 * if mapping failed free memory back to system since
1339 * there isn't much point in holding memory we can't use
1340 */
1341 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1342 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1343 bi->page = NULL;
f990b79b 1344
f990b79b
AD		 1345 rx_ring->rx_stats.alloc_rx_page_failed++;
1346 return false;
1347 }
1348
f800326d 1349 bi->dma = dma;
afaa9459 1350 bi->page_offset = 0;
f800326d 1351
f990b79b
AD		 1352 return true;
1353}
1354
9a799d71 1355/**
f990b79b 1356 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1357 * @rx_ring: ring to place buffers on
1358 * @cleaned_count: number of buffers to replace
9a799d71 1359 **/
fc77dc3c 1360void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1361{
9a799d71 1362 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1363 struct ixgbe_rx_buffer *bi;
d5f398ed 1364 u16 i = rx_ring->next_to_use;
9a799d71 1365
f800326d
AD		 1366 /* nothing to do */
1367 if (!cleaned_count)
fc77dc3c
AD		 1368 return;
1369
e4f74028 1370 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1371 bi = &rx_ring->rx_buffer_info[i];
1372 i -= rx_ring->count;
9a799d71 1373
f800326d
AD		 1374 do {
1375 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1376 break;
d5f398ed 1377
f800326d
AD		 1378 /*
1379 * Refresh the desc even if buffer_addrs didn't change
1380 * because each write-back erases this info.
1381 */
1382 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1383
f990b79b
AD		 1384 rx_desc++;
1385 bi++;
9a799d71 1386 i++;
f990b79b 1387 if (unlikely(!i)) {
e4f74028 1388 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1389 bi = rx_ring->rx_buffer_info;
1390 i -= rx_ring->count;
1391 }
1392
1393 /* clear the hdr_addr for the next_to_use descriptor */
1394 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1395
1396 cleaned_count--;
1397 } while (cleaned_count);
7c6e0a43 1398
f990b79b
AD		 1399 i += rx_ring->count;
1400
f56e0cb1 1401 if (rx_ring->next_to_use != i)
84ea2591 1402 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1403}
1404
1d2024f6
AD		 1405/**
1406 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1407 * @data: pointer to the start of the headers
1408 * @max_len: total length of section to find headers in
1409 *
1410 * This function is meant to determine the length of headers that will
1411 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1412 * motivation of doing this is to only perform one pull for IPv4 TCP
1413 * packets so that we can do basic things like calculating the gso_size
1414 * based on the average data per packet.
1415 **/
1416static unsigned int ixgbe_get_headlen(unsigned char *data,
1417 unsigned int max_len)
1418{
1419 union {
1420 unsigned char *network;
1421 /* l2 headers */
1422 struct ethhdr *eth;
1423 struct vlan_hdr *vlan;
1424 /* l3 headers */
1425 struct iphdr *ipv4;
a048b40e 1426 struct ipv6hdr *ipv6;
1d2024f6
AD		 1427 } hdr;
1428 __be16 protocol;
1429 u8 nexthdr = 0; /* default to not TCP */
1430 u8 hlen;
1431
1432 /* this should never happen, but better safe than sorry */
1433 if (max_len < ETH_HLEN)
1434 return max_len;
1435
1436 /* initialize network frame pointer */
1437 hdr.network = data;
1438
1439 /* set first protocol and move network header forward */
1440 protocol = hdr.eth->h_proto;
1441 hdr.network += ETH_HLEN;
1442
1443 /* handle any vlan tag if present */
1444 if (protocol == __constant_htons(ETH_P_8021Q)) {
1445 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1446 return max_len;
1447
1448 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1449 hdr.network += VLAN_HLEN;
1450 }
1451
1452 /* handle L3 protocols */
1453 if (protocol == __constant_htons(ETH_P_IP)) {
1454 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1455 return max_len;
1456
1457 /* access ihl as a u8 to avoid unaligned access on ia64 */
1458 hlen = (hdr.network[0] & 0x0F) << 2;
1459
1460 /* verify hlen meets minimum size requirements */
1461 if (hlen < sizeof(struct iphdr))
1462 return hdr.network - data;
1463
ed83da12 1464 /* record next protocol if header is present */
20967f42 1465 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1466 nexthdr = hdr.ipv4->protocol;
a048b40e
AD		 1467 } else if (protocol == __constant_htons(ETH_P_IPV6)) {
1468 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1469 return max_len;
1470
1471 /* record next protocol */
1472 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1473 hlen = sizeof(struct ipv6hdr);
f800326d 1474#ifdef IXGBE_FCOE
1d2024f6
AD		 1475 } else if (protocol == __constant_htons(ETH_P_FCOE)) {
1476 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1477 return max_len;
ed83da12 1478 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1479#endif
1480 } else {
1481 return hdr.network - data;
1482 }
1483
ed83da12
AD		 1484 /* relocate pointer to start of L4 header */
1485 hdr.network += hlen;
1486
a048b40e 1487 /* finally sort out TCP/UDP */
1d2024f6
AD		 1488 if (nexthdr == IPPROTO_TCP) {
1489 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1490 return max_len;
1491
1492 /* access doff as a u8 to avoid unaligned access on ia64 */
1493 hlen = (hdr.network[12] & 0xF0) >> 2;
1494
1495 /* verify hlen meets minimum size requirements */
1496 if (hlen < sizeof(struct tcphdr))
1497 return hdr.network - data;
1498
1499 hdr.network += hlen;
a048b40e
AD		 1500 } else if (nexthdr == IPPROTO_UDP) {
1501 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1502 return max_len;
1503
1504 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1505 }
1506
1507 /*
1508 * If everything has gone correctly hdr.network should be the
1509 * data section of the packet and will be the end of the header.
1510 * If not then it probably represents the end of the last recognized
1511 * header.
1512 */
1513 if ((hdr.network - data) < max_len)
1514 return hdr.network - data;
1515 else
1516 return max_len;
1517}
1518
1d2024f6
AD		 1519static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1520 struct sk_buff *skb)
1521{
f800326d 1522 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1523
1524 /* set gso_size to avoid messing up TCP MSS */
1525 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1526 IXGBE_CB(skb)->append_cnt);
96be80ab 1527 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1528}
1529
1530static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1531 struct sk_buff *skb)
1532{
1533 /* if append_cnt is 0 then frame is not RSC */
1534 if (!IXGBE_CB(skb)->append_cnt)
1535 return;
1536
1537 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1538 rx_ring->rx_stats.rsc_flush++;
1539
1540 ixgbe_set_rsc_gso_size(rx_ring, skb);
1541
1542 /* gso_size is computed using append_cnt so always clear it last */
1543 IXGBE_CB(skb)->append_cnt = 0;
1544}
1545
8a0da21b
AD		 1546/**
1547 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1548 * @rx_ring: rx descriptor ring packet is being transacted on
1549 * @rx_desc: pointer to the EOP Rx descriptor
1550 * @skb: pointer to current skb being populated
f8212f97 1551 *
8a0da21b
AD		 1552 * This function checks the ring, descriptor, and packet information in
1553 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1554 * other fields within the skb.
f8212f97 1555 **/
8a0da21b
AD		 1556static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1557 union ixgbe_adv_rx_desc *rx_desc,
1558 struct sk_buff *skb)
f8212f97 1559{
43e95f11
JF		 1560 struct net_device *dev = rx_ring->netdev;
1561
8a0da21b
AD		 1562 ixgbe_update_rsc_stats(rx_ring, skb);
1563
1564 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1565
8a0da21b
AD		 1566 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1567
6cb562d6 1568 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1569
f646968f 1570 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1571 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1572 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1573 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1574 }
1575
8a0da21b 1576 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1577
43e95f11 1578 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1579}
1580
8a0da21b
AD		 1581static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1582 struct sk_buff *skb)
aa80175a 1583{
8a0da21b
AD		 1584 struct ixgbe_adapter *adapter = q_vector->adapter;
1585
5a85e737
ET		 1586 if (ixgbe_qv_ll_polling(q_vector))
1587 netif_receive_skb(skb);
1588 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1589 napi_gro_receive(&q_vector->napi, skb);
1590 else
1591 netif_rx(skb);
aa80175a 1592}
43634e82 1593
f800326d
AD		 1594/**
1595 * ixgbe_is_non_eop - process handling of non-EOP buffers
1596 * @rx_ring: Rx ring being processed
1597 * @rx_desc: Rx descriptor for current buffer
1598 * @skb: Current socket buffer containing buffer in progress
1599 *
1600 * This function updates next to clean. If the buffer is an EOP buffer
1601 * this function exits returning false, otherwise it will place the
1602 * sk_buff in the next buffer to be chained and return true indicating
1603 * that this is in fact a non-EOP buffer.
1604 **/
1605static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1606 union ixgbe_adv_rx_desc *rx_desc,
1607 struct sk_buff *skb)
1608{
1609 u32 ntc = rx_ring->next_to_clean + 1;
1610
1611 /* fetch, update, and store next to clean */
1612 ntc = (ntc < rx_ring->count) ? ntc : 0;
1613 rx_ring->next_to_clean = ntc;
1614
1615 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1616
5a02cbd1
AD		 1617 /* update RSC append count if present */
1618 if (ring_is_rsc_enabled(rx_ring)) {
1619 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1620 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1621
1622 if (unlikely(rsc_enabled)) {
1623 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1624
1625 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1626 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1627
5a02cbd1
AD		 1628 /* update ntc based on RSC value */
1629 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1630 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1631 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1632 }
f800326d
AD		 1633 }
1634
5a02cbd1
AD		 1635 /* if we are the last buffer then there is nothing else to do */
1636 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1637 return false;
1638
f800326d
AD		 1639 /* place skb in next buffer to be received */
1640 rx_ring->rx_buffer_info[ntc].skb = skb;
1641 rx_ring->rx_stats.non_eop_descs++;
1642
1643 return true;
1644}
1645
19861ce2
AD		 1646/**
1647 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1648 * @rx_ring: rx descriptor ring packet is being transacted on
1649 * @skb: pointer to current skb being adjusted
1650 *
1651 * This function is an ixgbe specific version of __pskb_pull_tail. The
1652 * main difference between this version and the original function is that
1653 * this function can make several assumptions about the state of things
1654 * that allow for significant optimizations versus the standard function.
1655 * As a result we can do things like drop a frag and maintain an accurate
1656 * truesize for the skb.
1657 */
1658static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1659 struct sk_buff *skb)
1660{
1661 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1662 unsigned char *va;
1663 unsigned int pull_len;
1664
1665 /*
1666 * it is valid to use page_address instead of kmap since we are
1667 * working with pages allocated out of the lomem pool per
1668 * alloc_page(GFP_ATOMIC)
1669 */
1670 va = skb_frag_address(frag);
1671
1672 /*
1673 * we need the header to contain the greater of either ETH_HLEN or
1674 * 60 bytes if the skb->len is less than 60 for skb_pad.
1675 */
cf3fe7ac 1676 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1677
1678 /* align pull length to size of long to optimize memcpy performance */
1679 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1680
1681 /* update all of the pointers */
1682 skb_frag_size_sub(frag, pull_len);
1683 frag->page_offset += pull_len;
1684 skb->data_len -= pull_len;
1685 skb->tail += pull_len;
19861ce2
AD		 1686}
1687
42073d91
AD		 1688/**
1689 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1690 * @rx_ring: rx descriptor ring packet is being transacted on
1691 * @skb: pointer to current skb being updated
1692 *
1693 * This function provides a basic DMA sync up for the first fragment of an
1694 * skb. The reason for doing this is that the first fragment cannot be
1695 * unmapped until we have reached the end of packet descriptor for a buffer
1696 * chain.
1697 */
1698static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1699 struct sk_buff *skb)
1700{
1701 /* if the page was released unmap it, else just sync our portion */
1702 if (unlikely(IXGBE_CB(skb)->page_released)) {
1703 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1704 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1705 IXGBE_CB(skb)->page_released = false;
1706 } else {
1707 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1708
1709 dma_sync_single_range_for_cpu(rx_ring->dev,
1710 IXGBE_CB(skb)->dma,
1711 frag->page_offset,
1712 ixgbe_rx_bufsz(rx_ring),
1713 DMA_FROM_DEVICE);
1714 }
1715 IXGBE_CB(skb)->dma = 0;
1716}
1717
f800326d
AD		 1718/**
1719 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1720 * @rx_ring: rx descriptor ring packet is being transacted on
1721 * @rx_desc: pointer to the EOP Rx descriptor
1722 * @skb: pointer to current skb being fixed
1723 *
1724 * Check for corrupted packet headers caused by senders on the local L2
1725 * embedded NIC switch not setting up their Tx Descriptors right. These
1726 * should be very rare.
1727 *
1728 * Also address the case where we are pulling data in on pages only
1729 * and as such no data is present in the skb header.
1730 *
1731 * In addition if skb is not at least 60 bytes we need to pad it so that
1732 * it is large enough to qualify as a valid Ethernet frame.
1733 *
1734 * Returns true if an error was encountered and skb was freed.
1735 **/
1736static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1737 union ixgbe_adv_rx_desc *rx_desc,
1738 struct sk_buff *skb)
1739{
f800326d 1740 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1741
1742 /* verify that the packet does not have any known errors */
1743 if (unlikely(ixgbe_test_staterr(rx_desc,
1744 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1745 !(netdev->features & NETIF_F_RXALL))) {
1746 dev_kfree_skb_any(skb);
1747 return true;
1748 }
1749
19861ce2 1750 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1751 if (skb_is_nonlinear(skb))
1752 ixgbe_pull_tail(rx_ring, skb);
f800326d 1753
57efd44c
AD		 1754#ifdef IXGBE_FCOE
1755 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1756 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1757 return false;
1758
1759#endif
f800326d
AD		 1760 /* if skb_pad returns an error the skb was freed */
1761 if (unlikely(skb->len < 60)) {
1762 int pad_len = 60 - skb->len;
1763
1764 if (skb_pad(skb, pad_len))
1765 return true;
1766 __skb_put(skb, pad_len);
1767 }
1768
1769 return false;
1770}
1771
f800326d
AD		 1772/**
1773 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1774 * @rx_ring: rx descriptor ring to store buffers on
1775 * @old_buff: donor buffer to have page reused
1776 *
0549ae20 1777 * Synchronizes page for reuse by the adapter
f800326d
AD		 1778 **/
1779static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1780 struct ixgbe_rx_buffer *old_buff)
1781{
1782 struct ixgbe_rx_buffer *new_buff;
1783 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1784
1785 new_buff = &rx_ring->rx_buffer_info[nta];
1786
1787 /* update, and store next to alloc */
1788 nta++;
1789 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1790
1791 /* transfer page from old buffer to new buffer */
1792 new_buff->page = old_buff->page;
1793 new_buff->dma = old_buff->dma;
0549ae20 1794 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1795
1796 /* sync the buffer for use by the device */
1797 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1798 new_buff->page_offset,
1799 ixgbe_rx_bufsz(rx_ring),
f800326d 1800 DMA_FROM_DEVICE);
f800326d
AD		 1801}
1802
1803/**
1804 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1805 * @rx_ring: rx descriptor ring to transact packets on
1806 * @rx_buffer: buffer containing page to add
1807 * @rx_desc: descriptor containing length of buffer written by hardware
1808 * @skb: sk_buff to place the data into
1809 *
0549ae20
AD		 1810 * This function will add the data contained in rx_buffer->page to the skb.
1811 * This is done either through a direct copy if the data in the buffer is
1812 * less than the skb header size, otherwise it will just attach the page as
1813 * a frag to the skb.
1814 *
1815 * The function will then update the page offset if necessary and return
1816 * true if the buffer can be reused by the adapter.
f800326d 1817 **/
0549ae20 1818static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1819 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1820 union ixgbe_adv_rx_desc *rx_desc,
1821 struct sk_buff *skb)
f800326d 1822{
0549ae20
AD		 1823 struct page *page = rx_buffer->page;
1824 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1825#if (PAGE_SIZE < 8192)
0549ae20 1826 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1827#else
1828 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1829 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1830 ixgbe_rx_bufsz(rx_ring);
1831#endif
0549ae20 1832
cf3fe7ac
AD		 1833 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1834 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1835
1836 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1837
1838 /* we can reuse buffer as-is, just make sure it is local */
1839 if (likely(page_to_nid(page) == numa_node_id()))
1840 return true;
1841
1842 /* this page cannot be reused so discard it */
1843 put_page(page);
1844 return false;
1845 }
1846
0549ae20
AD		 1847 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1848 rx_buffer->page_offset, size, truesize);
1849
09816fbe
AD		 1850 /* avoid re-using remote pages */
1851 if (unlikely(page_to_nid(page) != numa_node_id()))
1852 return false;
1853
1854#if (PAGE_SIZE < 8192)
1855 /* if we are only owner of page we can reuse it */
1856 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1857 return false;
1858
1859 /* flip page offset to other buffer */
1860 rx_buffer->page_offset ^= truesize;
1861
09816fbe
AD		 1862 /*
1863 * since we are the only owner of the page and we need to
1864 * increment it, just set the value to 2 in order to avoid
1865 * an unecessary locked operation
1866 */
1867 atomic_set(&page->_count, 2);
1868#else
1869 /* move offset up to the next cache line */
1870 rx_buffer->page_offset += truesize;
1871
1872 if (rx_buffer->page_offset > last_offset)
1873 return false;
1874
0549ae20
AD		 1875 /* bump ref count on page before it is given to the stack */
1876 get_page(page);
09816fbe 1877#endif
0549ae20
AD		 1878
1879 return true;
f800326d
AD		 1880}
1881
18806c9e
AD		 1882static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
1883 union ixgbe_adv_rx_desc *rx_desc)
1884{
1885 struct ixgbe_rx_buffer *rx_buffer;
1886 struct sk_buff *skb;
1887 struct page *page;
1888
1889 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
1890 page = rx_buffer->page;
1891 prefetchw(page);
1892
1893 skb = rx_buffer->skb;
1894
1895 if (likely(!skb)) {
1896 void *page_addr = page_address(page) +
1897 rx_buffer->page_offset;
1898
1899 /* prefetch first cache line of first page */
1900 prefetch(page_addr);
1901#if L1_CACHE_BYTES < 128
1902 prefetch(page_addr + L1_CACHE_BYTES);
1903#endif
1904
1905 /* allocate a skb to store the frags */
1906 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1907 IXGBE_RX_HDR_SIZE);
1908 if (unlikely(!skb)) {
1909 rx_ring->rx_stats.alloc_rx_buff_failed++;
1910 return NULL;
1911 }
1912
1913 /*
1914 * we will be copying header into skb->data in
1915 * pskb_may_pull so it is in our interest to prefetch
1916 * it now to avoid a possible cache miss
1917 */
1918 prefetchw(skb->data);
1919
1920 /*
1921 * Delay unmapping of the first packet. It carries the
1922 * header information, HW may still access the header
1923 * after the writeback. Only unmap it when EOP is
1924 * reached
1925 */
1926 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1927 goto dma_sync;
1928
1929 IXGBE_CB(skb)->dma = rx_buffer->dma;
1930 } else {
1931 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
1932 ixgbe_dma_sync_frag(rx_ring, skb);
1933
1934dma_sync:
1935 /* we are reusing so sync this buffer for CPU use */
1936 dma_sync_single_range_for_cpu(rx_ring->dev,
1937 rx_buffer->dma,
1938 rx_buffer->page_offset,
1939 ixgbe_rx_bufsz(rx_ring),
1940 DMA_FROM_DEVICE);
1941 }
1942
1943 /* pull page into skb */
1944 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1945 /* hand second half of page back to the ring */
1946 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
1947 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
1948 /* the page has been released from the ring */
1949 IXGBE_CB(skb)->page_released = true;
1950 } else {
1951 /* we are not reusing the buffer so unmap it */
1952 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
1953 ixgbe_rx_pg_size(rx_ring),
1954 DMA_FROM_DEVICE);
1955 }
1956
1957 /* clear contents of buffer_info */
1958 rx_buffer->skb = NULL;
1959 rx_buffer->dma = 0;
1960 rx_buffer->page = NULL;
1961
1962 return skb;
f800326d
AD		 1963}
1964
1965/**
1966 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1967 * @q_vector: structure containing interrupt and ring information
1968 * @rx_ring: rx descriptor ring to transact packets on
1969 * @budget: Total limit on number of packets to process
1970 *
1971 * This function provides a "bounce buffer" approach to Rx interrupt
1972 * processing. The advantage to this is that on systems that have
1973 * expensive overhead for IOMMU access this provides a means of avoiding
1974 * it by maintaining the mapping of the page to the syste.
1975 *
5a85e737 1976 * Returns amount of work completed
f800326d 1977 **/
5a85e737 1978static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1979 struct ixgbe_ring *rx_ring,
f4de00ed 1980 const int budget)
9a799d71 1981{
d2f4fbe2 1982 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 1983#ifdef IXGBE_FCOE
f800326d 1984 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 1985 int ddp_bytes;
1986 unsigned int mss = 0;
3d8fd385 1987#endif /* IXGBE_FCOE */
f800326d 1988 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 1989
f800326d 1990 do {
f800326d
AD		 1991 union ixgbe_adv_rx_desc *rx_desc;
1992 struct sk_buff *skb;
f800326d
AD		 1993
1994 /* return some buffers to hardware, one at a time is too slow */
1995 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1996 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1997 cleaned_count = 0;
1998 }
1999
18806c9e 2000 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2001
2002 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2003 break;
9a799d71 2004
f800326d
AD		 2005 /*
2006 * This memory barrier is needed to keep us from reading
2007 * any other fields out of the rx_desc until we know the
2008 * RXD_STAT_DD bit is set
2009 */
2010 rmb();
9a799d71 2011
18806c9e
AD		 2012 /* retrieve a buffer from the ring */
2013 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2014
18806c9e
AD		 2015 /* exit if we failed to retrieve a buffer */
2016 if (!skb)
2017 break;
9a799d71 2018
9a799d71 2019 cleaned_count++;
f8212f97 2020
f800326d
AD		 2021 /* place incomplete frames back on ring for completion */
2022 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2023 continue;
c267fc16 2024
f800326d
AD		 2025 /* verify the packet layout is correct */
2026 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2027 continue;
9a799d71 2028
d2f4fbe2
AV		 2029 /* probably a little skewed due to removing CRC */
2030 total_rx_bytes += skb->len;
d2f4fbe2 2031
8a0da21b
AD		 2032 /* populate checksum, timestamp, VLAN, and protocol */
2033 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2034
332d4a7d
YZ		 2035#ifdef IXGBE_FCOE
2036 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2037 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2038 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2039 /* include DDPed FCoE data */
2040 if (ddp_bytes > 0) {
2041 if (!mss) {
2042 mss = rx_ring->netdev->mtu -
2043 sizeof(struct fcoe_hdr) -
2044 sizeof(struct fc_frame_header) -
2045 sizeof(struct fcoe_crc_eof);
2046 if (mss > 512)
2047 mss &= ~511;
2048 }
2049 total_rx_bytes += ddp_bytes;
2050 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2051 mss);
2052 }
63d635b2
AD		 2053 if (!ddp_bytes) {
2054 dev_kfree_skb_any(skb);
f800326d 2055 continue;
63d635b2 2056 }
3d8fd385 2057 }
f800326d 2058
332d4a7d 2059#endif /* IXGBE_FCOE */
8b80cda5 2060 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2061 ixgbe_rx_skb(q_vector, skb);
9a799d71 2062
f800326d 2063 /* update budget accounting */
f4de00ed
AD		 2064 total_rx_packets++;
2065 } while (likely(total_rx_packets < budget));
9a799d71 2066
c267fc16
AD		 2067 u64_stats_update_begin(&rx_ring->syncp);
2068 rx_ring->stats.packets += total_rx_packets;
2069 rx_ring->stats.bytes += total_rx_bytes;
2070 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2071 q_vector->rx.total_packets += total_rx_packets;
2072 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2073
f800326d
AD		 2074 if (cleaned_count)
2075 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2076
5a85e737 2077 return total_rx_packets;
9a799d71
AK		 2078}
2079
5a85e737
ET		 2080#ifdef CONFIG_NET_LL_RX_POLL
2081/* must be called with local_bh_disable()d */
2082static int ixgbe_low_latency_recv(struct napi_struct *napi)
2083{
2084 struct ixgbe_q_vector *q_vector =
2085 container_of(napi, struct ixgbe_q_vector, napi);
2086 struct ixgbe_adapter *adapter = q_vector->adapter;
2087 struct ixgbe_ring *ring;
2088 int found = 0;
2089
2090 if (test_bit(__IXGBE_DOWN, &adapter->state))
2091 return LL_FLUSH_FAILED;
2092
2093 if (!ixgbe_qv_lock_poll(q_vector))
2094 return LL_FLUSH_BUSY;
2095
2096 ixgbe_for_each_ring(ring, q_vector->rx) {
2097 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
7e15b90f
ET		 2098#ifdef LL_EXTENDED_STATS
2099 if (found)
2100 ring->stats.cleaned += found;
2101 else
2102 ring->stats.misses++;
2103#endif
5a85e737
ET		 2104 if (found)
2105 break;
2106 }
2107
2108 ixgbe_qv_unlock_poll(q_vector);
2109
2110 return found;
2111}
2112#endif /* CONFIG_NET_LL_RX_POLL */
2113
9a799d71
AK		 2114/**
2115 * ixgbe_configure_msix - Configure MSI-X hardware
2116 * @adapter: board private structure
2117 *
2118 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2119 * interrupts.
2120 **/
2121static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2122{
021230d4 2123 struct ixgbe_q_vector *q_vector;
49c7ffbe 2124 int v_idx;
021230d4 2125 u32 mask;
9a799d71 2126
8e34d1aa
AD		 2127 /* Populate MSIX to EITR Select */
2128 if (adapter->num_vfs > 32) {
2129 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2130 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2131 }
2132
4df10466
JB		 2133 /*
2134 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2135 * corresponding register.
2136 */
49c7ffbe 2137 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2138 struct ixgbe_ring *ring;
7a921c93 2139 q_vector = adapter->q_vector[v_idx];
021230d4 2140
a557928e 2141 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2142 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2143
a557928e 2144 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2145 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2146
fe49f04a 2147 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2148 }
2149
bd508178
AD		 2150 switch (adapter->hw.mac.type) {
2151 case ixgbe_mac_82598EB:
e8e26350 2152 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2153 v_idx);
bd508178
AD		 2154 break;
2155 case ixgbe_mac_82599EB:
b93a2226 2156 case ixgbe_mac_X540:
e8e26350 2157 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2158 break;
bd508178
AD		 2159 default:
2160 break;
2161 }
021230d4
AV		 2162 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2163
41fb9248 2164 /* set up to autoclear timer, and the vectors */
021230d4 2165 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2166 mask &= ~(IXGBE_EIMS_OTHER |
2167 IXGBE_EIMS_MAILBOX |
2168 IXGBE_EIMS_LSC);
2169
021230d4 2170 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2171}
2172
f494e8fa
AV		 2173enum latency_range {
2174 lowest_latency = 0,
2175 low_latency = 1,
2176 bulk_latency = 2,
2177 latency_invalid = 255
2178};
2179
2180/**
2181 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2182 * @q_vector: structure containing interrupt and ring information
2183 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2184 *
2185 * Stores a new ITR value based on packets and byte
2186 * counts during the last interrupt. The advantage of per interrupt
2187 * computation is faster updates and more accurate ITR for the current
2188 * traffic pattern. Constants in this function were computed
2189 * based on theoretical maximum wire speed and thresholds were set based
2190 * on testing data as well as attempting to minimize response time
2191 * while increasing bulk throughput.
2192 * this functionality is controlled by the InterruptThrottleRate module
2193 * parameter (see ixgbe_param.c)
2194 **/
bd198058
AD		 2195static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2196 struct ixgbe_ring_container *ring_container)
f494e8fa 2197{
bd198058
AD		 2198 int bytes = ring_container->total_bytes;
2199 int packets = ring_container->total_packets;
2200 u32 timepassed_us;
621bd70e 2201 u64 bytes_perint;
bd198058 2202 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2203
2204 if (packets == 0)
bd198058 2205 return;
f494e8fa
AV		 2206
2207 /* simple throttlerate management
621bd70e
AD		 2208 * 0-10MB/s lowest (100000 ints/s)
2209 * 10-20MB/s low (20000 ints/s)
2210 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2211 */
2212 /* what was last interrupt timeslice? */
d5bf4f67 2213 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2214 if (timepassed_us == 0)
2215 return;
2216
f494e8fa
AV		 2217 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2218
2219 switch (itr_setting) {
2220 case lowest_latency:
621bd70e 2221 if (bytes_perint > 10)
bd198058 2222 itr_setting = low_latency;
f494e8fa
AV		 2223 break;
2224 case low_latency:
621bd70e 2225 if (bytes_perint > 20)
bd198058 2226 itr_setting = bulk_latency;
621bd70e 2227 else if (bytes_perint <= 10)
bd198058 2228 itr_setting = lowest_latency;
f494e8fa
AV		 2229 break;
2230 case bulk_latency:
621bd70e 2231 if (bytes_perint <= 20)
bd198058 2232 itr_setting = low_latency;
f494e8fa
AV		 2233 break;
2234 }
2235
bd198058
AD		 2236 /* clear work counters since we have the values we need */
2237 ring_container->total_bytes = 0;
2238 ring_container->total_packets = 0;
2239
2240 /* write updated itr to ring container */
2241 ring_container->itr = itr_setting;
f494e8fa
AV		 2242}
2243
509ee935
JB		 2244/**
2245 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2246 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2247 *
2248 * This function is made to be called by ethtool and by the driver
2249 * when it needs to update EITR registers at runtime. Hardware
2250 * specific quirks/differences are taken care of here.
2251 */
fe49f04a 2252void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2253{
fe49f04a 2254 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2255 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2256 int v_idx = q_vector->v_idx;
5d967eb7 2257 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2258
bd508178
AD		 2259 switch (adapter->hw.mac.type) {
2260 case ixgbe_mac_82598EB:
509ee935
JB		 2261 /* must write high and low 16 bits to reset counter */
2262 itr_reg |= (itr_reg << 16);
bd508178
AD		 2263 break;
2264 case ixgbe_mac_82599EB:
b93a2226 2265 case ixgbe_mac_X540:
509ee935
JB		 2266 /*
2267 * set the WDIS bit to not clear the timer bits and cause an
2268 * immediate assertion of the interrupt
2269 */
2270 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2271 break;
2272 default:
2273 break;
509ee935
JB		 2274 }
2275 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2276}
2277
bd198058 2278static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2279{
d5bf4f67 2280 u32 new_itr = q_vector->itr;
bd198058 2281 u8 current_itr;
f494e8fa 2282
bd198058
AD		 2283 ixgbe_update_itr(q_vector, &q_vector->tx);
2284 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2285
08c8833b 2286 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2287
2288 switch (current_itr) {
2289 /* counts and packets in update_itr are dependent on these numbers */
2290 case lowest_latency:
d5bf4f67 2291 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2292 break;
2293 case low_latency:
d5bf4f67 2294 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2295 break;
2296 case bulk_latency:
d5bf4f67 2297 new_itr = IXGBE_8K_ITR;
f494e8fa 2298 break;
bd198058
AD		 2299 default:
2300 break;
f494e8fa
AV		 2301 }
2302
d5bf4f67 2303 if (new_itr != q_vector->itr) {
fe49f04a 2304 /* do an exponential smoothing */
d5bf4f67
ET		 2305 new_itr = (10 * new_itr * q_vector->itr) /
2306 ((9 * new_itr) + q_vector->itr);
509ee935 2307
bd198058 2308 /* save the algorithm value here */
5d967eb7 2309 q_vector->itr = new_itr;
fe49f04a
AD		 2310
2311 ixgbe_write_eitr(q_vector);
f494e8fa 2312 }
f494e8fa
AV		 2313}
2314
119fc60a 2315/**
de88eeeb 2316 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2317 * @adapter: pointer to adapter
119fc60a 2318 **/
f0f9778d 2319static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2320{
119fc60a
MC		 2321 struct ixgbe_hw *hw = &adapter->hw;
2322 u32 eicr = adapter->interrupt_event;
2323
f0f9778d 2324 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2325 return;
2326
f0f9778d
AD		 2327 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2328 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2329 return;
2330
2331 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2332
7ca647bd 2333 switch (hw->device_id) {
f0f9778d
AD		 2334 case IXGBE_DEV_ID_82599_T3_LOM:
2335 /*
2336 * Since the warning interrupt is for both ports
2337 * we don't have to check if:
2338 * - This interrupt wasn't for our port.
2339 * - We may have missed the interrupt so always have to
2340 * check if we got a LSC
2341 */
2342 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2343 !(eicr & IXGBE_EICR_LSC))
2344 return;
2345
2346 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2347 u32 speed;
f0f9778d 2348 bool link_up = false;
7ca647bd 2349
3d292265 2350 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2351
f0f9778d
AD		 2352 if (link_up)
2353 return;
2354 }
2355
2356 /* Check if this is not due to overtemp */
2357 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2358 return;
2359
2360 break;
7ca647bd
JP		 2361 default:
2362 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2363 return;
7ca647bd 2364 break;
119fc60a 2365 }
7ca647bd
JP		 2366 e_crit(drv,
2367 "Network adapter has been stopped because it has over heated. "
2368 "Restart the computer. If the problem persists, "
2369 "power off the system and replace the adapter\n");
f0f9778d
AD		 2370
2371 adapter->interrupt_event = 0;
119fc60a
MC		 2372}
2373
0befdb3e
JB		 2374static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2375{
2376 struct ixgbe_hw *hw = &adapter->hw;
2377
2378 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2379 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2380 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2381 /* write to clear the interrupt */
2382 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2383 }
2384}
cf8280ee 2385
4f51bf70
JK		 2386static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2387{
2388 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2389 return;
2390
2391 switch (adapter->hw.mac.type) {
2392 case ixgbe_mac_82599EB:
2393 /*
2394 * Need to check link state so complete overtemp check
2395 * on service task
2396 */
2397 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2398 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2399 adapter->interrupt_event = eicr;
2400 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2401 ixgbe_service_event_schedule(adapter);
2402 return;
2403 }
2404 return;
2405 case ixgbe_mac_X540:
2406 if (!(eicr & IXGBE_EICR_TS))
2407 return;
2408 break;
2409 default:
2410 return;
2411 }
2412
2413 e_crit(drv,
2414 "Network adapter has been stopped because it has over heated. "
2415 "Restart the computer. If the problem persists, "
2416 "power off the system and replace the adapter\n");
2417}
2418
e8e26350
PW		 2419static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2420{
2421 struct ixgbe_hw *hw = &adapter->hw;
2422
73c4b7cd
AD		 2423 if (eicr & IXGBE_EICR_GPI_SDP2) {
2424 /* Clear the interrupt */
2425 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2426 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2427 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2428 ixgbe_service_event_schedule(adapter);
2429 }
73c4b7cd
AD		 2430 }
2431
e8e26350
PW		 2432 if (eicr & IXGBE_EICR_GPI_SDP1) {
2433 /* Clear the interrupt */
2434 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2435 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2436 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2437 ixgbe_service_event_schedule(adapter);
2438 }
e8e26350
PW		 2439 }
2440}
2441
cf8280ee
JB		 2442static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2443{
2444 struct ixgbe_hw *hw = &adapter->hw;
2445
2446 adapter->lsc_int++;
2447 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2448 adapter->link_check_timeout = jiffies;
2449 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2450 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2451 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2452 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2453 }
2454}
2455
fe49f04a
AD		 2456static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2457 u64 qmask)
2458{
2459 u32 mask;
bd508178 2460 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2461
bd508178
AD		 2462 switch (hw->mac.type) {
2463 case ixgbe_mac_82598EB:
fe49f04a 2464 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2465 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2466 break;
2467 case ixgbe_mac_82599EB:
b93a2226 2468 case ixgbe_mac_X540:
fe49f04a 2469 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2470 if (mask)
2471 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2472 mask = (qmask >> 32);
bd508178
AD		 2473 if (mask)
2474 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2475 break;
2476 default:
2477 break;
fe49f04a
AD		 2478 }
2479 /* skip the flush */
2480}
2481
2482static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2483 u64 qmask)
fe49f04a
AD		 2484{
2485 u32 mask;
bd508178 2486 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2487
bd508178
AD		 2488 switch (hw->mac.type) {
2489 case ixgbe_mac_82598EB:
fe49f04a 2490 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2491 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2492 break;
2493 case ixgbe_mac_82599EB:
b93a2226 2494 case ixgbe_mac_X540:
fe49f04a 2495 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2496 if (mask)
2497 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2498 mask = (qmask >> 32);
bd508178
AD		 2499 if (mask)
2500 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2501 break;
2502 default:
2503 break;
fe49f04a
AD		 2504 }
2505 /* skip the flush */
2506}
2507
021230d4 2508/**
2c4af694
AD		 2509 * ixgbe_irq_enable - Enable default interrupt generation settings
2510 * @adapter: board private structure
021230d4 2511 **/
2c4af694
AD		 2512static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2513 bool flush)
9a799d71 2514{
2c4af694 2515 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2516
2c4af694
AD		 2517 /* don't reenable LSC while waiting for link */
2518 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2519 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2520
2c4af694 2521 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2522 switch (adapter->hw.mac.type) {
2523 case ixgbe_mac_82599EB:
2524 mask |= IXGBE_EIMS_GPI_SDP0;
2525 break;
2526 case ixgbe_mac_X540:
2527 mask |= IXGBE_EIMS_TS;
2528 break;
2529 default:
2530 break;
2531 }
2c4af694
AD		 2532 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2533 mask |= IXGBE_EIMS_GPI_SDP1;
2534 switch (adapter->hw.mac.type) {
2535 case ixgbe_mac_82599EB:
2c4af694
AD		 2536 mask |= IXGBE_EIMS_GPI_SDP1;
2537 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2538 case ixgbe_mac_X540:
2539 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2540 mask |= IXGBE_EIMS_MAILBOX;
2541 break;
2542 default:
2543 break;
9a799d71 2544 }
db0677fa 2545
db0677fa
JK		 2546 if (adapter->hw.mac.type == ixgbe_mac_X540)
2547 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2548
2c4af694
AD		 2549 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2550 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2551 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2552
2c4af694
AD		 2553 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2554 if (queues)
2555 ixgbe_irq_enable_queues(adapter, ~0);
2556 if (flush)
2557 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2558}
2559
2c4af694 2560static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2561{
a65151ba 2562 struct ixgbe_adapter *adapter = data;
9a799d71 2563 struct ixgbe_hw *hw = &adapter->hw;
54037505 2564 u32 eicr;
91281fd3 2565
54037505
DS		 2566 /*
2567 * Workaround for Silicon errata. Use clear-by-write instead
2568 * of clear-by-read. Reading with EICS will return the
2569 * interrupt causes without clearing, which later be done
2570 * with the write to EICR.
2571 */
2572 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2573
2574 /* The lower 16bits of the EICR register are for the queue interrupts
2575 * which should be masked here in order to not accidently clear them if
2576 * the bits are high when ixgbe_msix_other is called. There is a race
2577 * condition otherwise which results in possible performance loss
2578 * especially if the ixgbe_msix_other interrupt is triggering
2579 * consistently (as it would when PPS is turned on for the X540 device)
2580 */
2581 eicr &= 0xFFFF0000;
2582
54037505 2583 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2584
cf8280ee
JB		 2585 if (eicr & IXGBE_EICR_LSC)
2586 ixgbe_check_lsc(adapter);
f0848276 2587
1cdd1ec8
GR		 2588 if (eicr & IXGBE_EICR_MAILBOX)
2589 ixgbe_msg_task(adapter);
efe3d3c8 2590
bd508178
AD		 2591 switch (hw->mac.type) {
2592 case ixgbe_mac_82599EB:
b93a2226 2593 case ixgbe_mac_X540:
2c4af694
AD		 2594 if (eicr & IXGBE_EICR_ECC)
2595 e_info(link, "Received unrecoverable ECC Err, please "
2596 "reboot\n");
c4cf55e5
PWJ		 2597 /* Handle Flow Director Full threshold interrupt */
2598 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2599 int reinit_count = 0;
c4cf55e5 2600 int i;
c4cf55e5 2601 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2602 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2603 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2604 &ring->state))
2605 reinit_count++;
2606 }
2607 if (reinit_count) {
2608 /* no more flow director interrupts until after init */
2609 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2610 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2611 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2612 }
2613 }
f0f9778d 2614 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2615 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2616 break;
2617 default:
2618 break;
c4cf55e5 2619 }
f0848276 2620
bd508178 2621 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2622
db0677fa
JK		 2623 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2624 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2625
7086400d 2626 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2627 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2628 ixgbe_irq_enable(adapter, false, false);
f0848276 2629
9a799d71 2630 return IRQ_HANDLED;
f0848276 2631}
91281fd3 2632
4ff7fb12 2633static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2634{
021230d4 2635 struct ixgbe_q_vector *q_vector = data;
91281fd3 2636
9b471446 2637 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2638
4ff7fb12
AD		 2639 if (q_vector->rx.ring || q_vector->tx.ring)
2640 napi_schedule(&q_vector->napi);
91281fd3 2641
9a799d71 2642 return IRQ_HANDLED;
91281fd3
AD		 2643}
2644
eb01b975
AD		 2645/**
2646 * ixgbe_poll - NAPI Rx polling callback
2647 * @napi: structure for representing this polling device
2648 * @budget: how many packets driver is allowed to clean
2649 *
2650 * This function is used for legacy and MSI, NAPI mode
2651 **/
8af3c33f 2652int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2653{
2654 struct ixgbe_q_vector *q_vector =
2655 container_of(napi, struct ixgbe_q_vector, napi);
2656 struct ixgbe_adapter *adapter = q_vector->adapter;
2657 struct ixgbe_ring *ring;
2658 int per_ring_budget;
2659 bool clean_complete = true;
2660
2661#ifdef CONFIG_IXGBE_DCA
2662 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2663 ixgbe_update_dca(q_vector);
2664#endif
2665
2666 ixgbe_for_each_ring(ring, q_vector->tx)
2667 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2668
5a85e737
ET		 2669 if (!ixgbe_qv_lock_napi(q_vector))
2670 return budget;
2671
eb01b975
AD		 2672 /* attempt to distribute budget to each queue fairly, but don't allow
2673 * the budget to go below 1 because we'll exit polling */
2674 if (q_vector->rx.count > 1)
2675 per_ring_budget = max(budget/q_vector->rx.count, 1);
2676 else
2677 per_ring_budget = budget;
2678
2679 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2680 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2681 per_ring_budget) < per_ring_budget);
eb01b975 2682
5a85e737 2683 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2684 /* If all work not completed, return budget and keep polling */
2685 if (!clean_complete)
2686 return budget;
2687
2688 /* all work done, exit the polling mode */
2689 napi_complete(napi);
2690 if (adapter->rx_itr_setting & 1)
2691 ixgbe_set_itr(q_vector);
2692 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2693 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2694
2695 return 0;
2696}
2697
021230d4
AV		 2698/**
2699 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2700 * @adapter: board private structure
2701 *
2702 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2703 * interrupts from the kernel.
2704 **/
2705static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2706{
2707 struct net_device *netdev = adapter->netdev;
207867f5 2708 int vector, err;
e8e9f696 2709 int ri = 0, ti = 0;
021230d4 2710
49c7ffbe 2711 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2712 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2713 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2714
4ff7fb12 2715 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2716 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2717 "%s-%s-%d", netdev->name, "TxRx", ri++);
2718 ti++;
2719 } else if (q_vector->rx.ring) {
9fe93afd 2720 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2721 "%s-%s-%d", netdev->name, "rx", ri++);
2722 } else if (q_vector->tx.ring) {
9fe93afd 2723 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2724 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2725 } else {
2726 /* skip this unused q_vector */
2727 continue;
32aa77a4 2728 }
207867f5
AD		 2729 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2730 q_vector->name, q_vector);
9a799d71 2731 if (err) {
396e799c 2732 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2733 "Error: %d\n", err);
021230d4 2734 goto free_queue_irqs;
9a799d71 2735 }
207867f5
AD		 2736 /* If Flow Director is enabled, set interrupt affinity */
2737 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2738 /* assign the mask for this irq */
2739 irq_set_affinity_hint(entry->vector,
de88eeeb 2740 &q_vector->affinity_mask);
207867f5 2741 }
9a799d71
AK		 2742 }
2743
021230d4 2744 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2745 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2746 if (err) {
de88eeeb 2747 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2748 goto free_queue_irqs;
9a799d71
AK		 2749 }
2750
9a799d71
AK		 2751 return 0;
2752
021230d4 2753free_queue_irqs:
207867f5
AD		 2754 while (vector) {
2755 vector--;
2756 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2757 NULL);
2758 free_irq(adapter->msix_entries[vector].vector,
2759 adapter->q_vector[vector]);
2760 }
021230d4
AV		 2761 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2762 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2763 kfree(adapter->msix_entries);
2764 adapter->msix_entries = NULL;
9a799d71
AK		 2765 return err;
2766}
2767
2768/**
021230d4 2769 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2770 * @irq: interrupt number
2771 * @data: pointer to a network interface device structure
9a799d71
AK		 2772 **/
2773static irqreturn_t ixgbe_intr(int irq, void *data)
2774{
a65151ba 2775 struct ixgbe_adapter *adapter = data;
9a799d71 2776 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2777 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2778 u32 eicr;
2779
54037505 2780 /*
24ddd967 2781 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2782 * before the read of EICR.
2783 */
2784 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2785
021230d4 2786 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2787 * therefore no explicit interrupt disable is necessary */
021230d4 2788 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2789 if (!eicr) {
6af3b9eb
ET		 2790 /*
2791 * shared interrupt alert!
f47cf66e 2792 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2793 * have disabled interrupts due to EIAM
2794 * finish the workaround of silicon errata on 82598. Unmask
2795 * the interrupt that we masked before the EICR read.
2796 */
2797 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2798 ixgbe_irq_enable(adapter, true, true);
9a799d71 2799 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2800 }
9a799d71 2801
cf8280ee
JB		 2802 if (eicr & IXGBE_EICR_LSC)
2803 ixgbe_check_lsc(adapter);
021230d4 2804
bd508178
AD		 2805 switch (hw->mac.type) {
2806 case ixgbe_mac_82599EB:
e8e26350 2807 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2808 /* Fall through */
2809 case ixgbe_mac_X540:
2810 if (eicr & IXGBE_EICR_ECC)
2811 e_info(link, "Received unrecoverable ECC err, please "
2812 "reboot\n");
4f51bf70 2813 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2814 break;
2815 default:
2816 break;
2817 }
e8e26350 2818
0befdb3e 2819 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2820 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2821 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2822
b9f6ed2b
AD		 2823 /* would disable interrupts here but EIAM disabled it */
2824 napi_schedule(&q_vector->napi);
9a799d71 2825
6af3b9eb
ET		 2826 /*
2827 * re-enable link(maybe) and non-queue interrupts, no flush.
2828 * ixgbe_poll will re-enable the queue interrupts
2829 */
6af3b9eb
ET		 2830 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2831 ixgbe_irq_enable(adapter, false, false);
2832
9a799d71
AK		 2833 return IRQ_HANDLED;
2834}
2835
2836/**
2837 * ixgbe_request_irq - initialize interrupts
2838 * @adapter: board private structure
2839 *
2840 * Attempts to configure interrupts using the best available
2841 * capabilities of the hardware and kernel.
2842 **/
021230d4 2843static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2844{
2845 struct net_device *netdev = adapter->netdev;
021230d4 2846 int err;
9a799d71 2847
4cc6df29 2848 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2849 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2850 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2851 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2852 netdev->name, adapter);
4cc6df29 2853 else
a0607fd3 2854 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2855 netdev->name, adapter);
9a799d71 2856
de88eeeb 2857 if (err)
396e799c 2858 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2859
9a799d71
AK		 2860 return err;
2861}
2862
2863static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2864{
49c7ffbe 2865 int vector;
9a799d71 2866
49c7ffbe
AD		 2867 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2868 free_irq(adapter->pdev->irq, adapter);
2869 return;
2870 }
4cc6df29 2871
49c7ffbe
AD		 2872 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
2873 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2874 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 2875
49c7ffbe
AD		 2876 /* free only the irqs that were actually requested */
2877 if (!q_vector->rx.ring && !q_vector->tx.ring)
2878 continue;
207867f5 2879
49c7ffbe
AD		 2880 /* clear the affinity_mask in the IRQ descriptor */
2881 irq_set_affinity_hint(entry->vector, NULL);
2882
2883 free_irq(entry->vector, q_vector);
9a799d71 2884 }
49c7ffbe
AD		 2885
2886 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 2887}
2888
22d5a71b
JB		 2889/**
2890 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2891 * @adapter: board private structure
2892 **/
2893static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2894{
bd508178
AD		 2895 switch (adapter->hw.mac.type) {
2896 case ixgbe_mac_82598EB:
835462fc 2897 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 2898 break;
2899 case ixgbe_mac_82599EB:
b93a2226 2900 case ixgbe_mac_X540:
835462fc
NS		 2901 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2902 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 2903 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 2904 break;
2905 default:
2906 break;
22d5a71b
JB		 2907 }
2908 IXGBE_WRITE_FLUSH(&adapter->hw);
2909 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 2910 int vector;
2911
2912 for (vector = 0; vector < adapter->num_q_vectors; vector++)
2913 synchronize_irq(adapter->msix_entries[vector].vector);
2914
2915 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 2916 } else {
2917 synchronize_irq(adapter->pdev->irq);
2918 }
2919}
2920
9a799d71
AK		 2921/**
2922 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2923 *
2924 **/
2925static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2926{
d5bf4f67 2927 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 2928
d5bf4f67 2929 ixgbe_write_eitr(q_vector);
9a799d71 2930
e8e26350
PW		 2931 ixgbe_set_ivar(adapter, 0, 0, 0);
2932 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 2933
396e799c 2934 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 2935}
2936
43e69bf0
AD		 2937/**
2938 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2939 * @adapter: board private structure
2940 * @ring: structure containing ring specific data
2941 *
2942 * Configure the Tx descriptor ring after a reset.
2943 **/
84418e3b
AD		 2944void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2945 struct ixgbe_ring *ring)
43e69bf0
AD		 2946{
2947 struct ixgbe_hw *hw = &adapter->hw;
2948 u64 tdba = ring->dma;
2f1860b8 2949 int wait_loop = 10;
b88c6de2 2950 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 2951 u8 reg_idx = ring->reg_idx;
43e69bf0 2952
2f1860b8 2953 /* disable queue to avoid issues while updating state */
b88c6de2 2954 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 2955 IXGBE_WRITE_FLUSH(hw);
2956
43e69bf0 2957 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 2958 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 2959 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2960 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2961 ring->count * sizeof(union ixgbe_adv_tx_desc));
2962 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2963 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
84ea2591 2964 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
43e69bf0 2965
b88c6de2
AD		 2966 /*
2967 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 2968 * higher than 1 when:
2969 * - ITR is 0 as it could cause false TX hangs
2970 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 2971 *
2972 * In order to avoid issues WTHRESH + PTHRESH should always be equal
2973 * to or less than the number of on chip descriptors, which is
2974 * currently 40.
2975 */
67da097e
ET		 2976#if IS_ENABLED(CONFIG_BQL)
2977 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
2978#else
e954b374 2979 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 2980#endif
b88c6de2
AD		 2981 txdctl |= (1 << 16); /* WTHRESH = 1 */
2982 else
2983 txdctl |= (8 << 16); /* WTHRESH = 8 */
2984
e954b374
AD		 2985 /*
2986 * Setting PTHRESH to 32 both improves performance
2987 * and avoids a TX hang with DFP enabled
2988 */
b88c6de2
AD		 2989 txdctl |= (1 << 8) | /* HTHRESH = 1 */
2990 32; /* PTHRESH = 32 */
2f1860b8
AD		 2991
2992 /* reinitialize flowdirector state */
39cb681b 2993 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 2994 ring->atr_sample_rate = adapter->atr_sample_rate;
2995 ring->atr_count = 0;
2996 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2997 } else {
2998 ring->atr_sample_rate = 0;
2999 }
2f1860b8 3000
fd786b7b
AD		 3001 /* initialize XPS */
3002 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3003 struct ixgbe_q_vector *q_vector = ring->q_vector;
3004
3005 if (q_vector)
3006 netif_set_xps_queue(adapter->netdev,
3007 &q_vector->affinity_mask,
3008 ring->queue_index);
3009 }
3010
c84d324c
JF		 3011 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3012
2f1860b8 3013 /* enable queue */
2f1860b8
AD		 3014 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3015
3016 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3017 if (hw->mac.type == ixgbe_mac_82598EB &&
3018 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3019 return;
3020
3021 /* poll to verify queue is enabled */
3022 do {
032b4325 3023 usleep_range(1000, 2000);
2f1860b8
AD		 3024 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3025 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3026 if (!wait_loop)
3027 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3028}
3029
120ff942
AD		 3030static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3031{
3032 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3033 u32 rttdcs, mtqc;
8b1c0b24 3034 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3035
3036 if (hw->mac.type == ixgbe_mac_82598EB)
3037 return;
3038
3039 /* disable the arbiter while setting MTQC */
3040 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3041 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3042 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3043
3044 /* set transmit pool layout */
671c0adb
AD		 3045 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3046 mtqc = IXGBE_MTQC_VT_ENA;
3047 if (tcs > 4)
3048 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3049 else if (tcs > 1)
3050 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3051 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3052 mtqc |= IXGBE_MTQC_32VF;
3053 else
3054 mtqc |= IXGBE_MTQC_64VF;
3055 } else {
3056 if (tcs > 4)
3057 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3058 else if (tcs > 1)
3059 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3060 else
671c0adb
AD		 3061 mtqc = IXGBE_MTQC_64Q_1PB;
3062 }
120ff942 3063
671c0adb 3064 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3065
671c0adb
AD		 3066 /* Enable Security TX Buffer IFG for multiple pb */
3067 if (tcs) {
3068 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3069 sectx |= IXGBE_SECTX_DCB;
3070 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3071 }
3072
3073 /* re-enable the arbiter */
3074 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3075 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3076}
3077
9a799d71 3078/**
3a581073 3079 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3080 * @adapter: board private structure
3081 *
3082 * Configure the Tx unit of the MAC after a reset.
3083 **/
3084static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3085{
2f1860b8
AD		 3086 struct ixgbe_hw *hw = &adapter->hw;
3087 u32 dmatxctl;
43e69bf0 3088 u32 i;
9a799d71 3089
2f1860b8
AD		 3090 ixgbe_setup_mtqc(adapter);
3091
3092 if (hw->mac.type != ixgbe_mac_82598EB) {
3093 /* DMATXCTL.EN must be before Tx queues are enabled */
3094 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3095 dmatxctl |= IXGBE_DMATXCTL_TE;
3096 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3097 }
3098
9a799d71 3099 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3100 for (i = 0; i < adapter->num_tx_queues; i++)
3101 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3102}
3103
3ebe8fde
AD		 3104static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3105 struct ixgbe_ring *ring)
3106{
3107 struct ixgbe_hw *hw = &adapter->hw;
3108 u8 reg_idx = ring->reg_idx;
3109 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3110
3111 srrctl |= IXGBE_SRRCTL_DROP_EN;
3112
3113 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3114}
3115
3116static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3117 struct ixgbe_ring *ring)
3118{
3119 struct ixgbe_hw *hw = &adapter->hw;
3120 u8 reg_idx = ring->reg_idx;
3121 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3122
3123 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3124
3125 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3126}
3127
3128#ifdef CONFIG_IXGBE_DCB
3129void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3130#else
3131static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3132#endif
3133{
3134 int i;
3135 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3136
3137 if (adapter->ixgbe_ieee_pfc)
3138 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3139
3140 /*
3141 * We should set the drop enable bit if:
3142 * SR-IOV is enabled
3143 * or
3144 * Number of Rx queues > 1 and flow control is disabled
3145 *
3146 * This allows us to avoid head of line blocking for security
3147 * and performance reasons.
3148 */
3149 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3150 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3151 for (i = 0; i < adapter->num_rx_queues; i++)
3152 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3153 } else {
3154 for (i = 0; i < adapter->num_rx_queues; i++)
3155 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3156 }
3157}
3158
e8e26350 3159#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3160
a6616b42 3161static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3162 struct ixgbe_ring *rx_ring)
cc41ac7c 3163{
45e9baa5 3164 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3165 u32 srrctl;
bf29ee6c 3166 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3167
45e9baa5
AD		 3168 if (hw->mac.type == ixgbe_mac_82598EB) {
3169 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3170
45e9baa5
AD		 3171 /*
3172 * if VMDq is not active we must program one srrctl register
3173 * per RSS queue since we have enabled RDRXCTL.MVMEN
3174 */
3175 reg_idx &= mask;
3176 }
cc41ac7c 3177
45e9baa5
AD		 3178 /* configure header buffer length, needed for RSC */
3179 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3180
45e9baa5 3181 /* configure the packet buffer length */
f800326d 3182 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3183
3184 /* configure descriptor type */
f800326d 3185 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3186
45e9baa5 3187 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3188}
9a799d71 3189
05abb126 3190static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3191{
05abb126
AD		 3192 struct ixgbe_hw *hw = &adapter->hw;
3193 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3194 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3195 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3196 u32 mrqc = 0, reta = 0;
3197 u32 rxcsum;
3198 int i, j;
671c0adb
AD		 3199 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3200
671c0adb
AD		 3201 /*
3202 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3203 * make full use of any rings they may have. We will use the
3204 * PSRTYPE register to control how many rings we use within the PF.
3205 */
3206 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3207 rss_i = 2;
0cefafad 3208
05abb126
AD		 3209 /* Fill out hash function seeds */
3210 for (i = 0; i < 10; i++)
3211 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3212
3213 /* Fill out redirection table */
3214 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3215 if (j == rss_i)
05abb126
AD		 3216 j = 0;
3217 /* reta = 4-byte sliding window of
3218 * 0x00..(indices-1)(indices-1)00..etc. */
3219 reta = (reta << 8) | (j * 0x11);
3220 if ((i & 3) == 3)
3221 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3222 }
0cefafad 3223
05abb126
AD		 3224 /* Disable indicating checksum in descriptor, enables RSS hash */
3225 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3226 rxcsum |= IXGBE_RXCSUM_PCSD;
3227 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3228
671c0adb 3229 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3230 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3231 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3232 } else {
671c0adb
AD		 3233 u8 tcs = netdev_get_num_tc(adapter->netdev);
3234
3235 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3236 if (tcs > 4)
3237 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3238 else if (tcs > 1)
3239 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3240 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3241 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3242 else
671c0adb
AD		 3243 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3244 } else {
3245 if (tcs > 4)
8b1c0b24 3246 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3247 else if (tcs > 1)
3248 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3249 else
3250 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3251 }
0cefafad
JB		 3252 }
3253
05abb126 3254 /* Perform hash on these packet types */
671c0adb
AD		 3255 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3256 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3257 IXGBE_MRQC_RSS_FIELD_IPV6 |
3258 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3259
ef6afc0c
AD		 3260 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3261 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3262 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3263 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3264
05abb126 3265 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3266}
3267
bb5a9ad2
NS		 3268/**
3269 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3270 * @adapter: address of board private structure
3271 * @index: index of ring to set
bb5a9ad2 3272 **/
082757af 3273static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3274 struct ixgbe_ring *ring)
bb5a9ad2 3275{
bb5a9ad2 3276 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3277 u32 rscctrl;
bf29ee6c 3278 u8 reg_idx = ring->reg_idx;
7367096a 3279
7d637bcc 3280 if (!ring_is_rsc_enabled(ring))
7367096a 3281 return;
bb5a9ad2 3282
7367096a 3283 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3284 rscctrl |= IXGBE_RSCCTL_RSCEN;
3285 /*
3286 * we must limit the number of descriptors so that the
3287 * total size of max desc * buf_len is not greater
642c680e 3288 * than 65536
bb5a9ad2 3289 */
f800326d 3290 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3291 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3292}
3293
9e10e045
AD		 3294#define IXGBE_MAX_RX_DESC_POLL 10
3295static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3296 struct ixgbe_ring *ring)
3297{
3298 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3299 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3300 u32 rxdctl;
bf29ee6c 3301 u8 reg_idx = ring->reg_idx;
9e10e045
AD		 3302
3303 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3304 if (hw->mac.type == ixgbe_mac_82598EB &&
3305 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3306 return;
3307
3308 do {
032b4325 3309 usleep_range(1000, 2000);
9e10e045
AD		 3310 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3311 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3312
3313 if (!wait_loop) {
3314 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3315 "the polling period\n", reg_idx);
3316 }
3317}
3318
2d39d576
YZ		 3319void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3320 struct ixgbe_ring *ring)
3321{
3322 struct ixgbe_hw *hw = &adapter->hw;
3323 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3324 u32 rxdctl;
3325 u8 reg_idx = ring->reg_idx;
3326
3327 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3328 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3329
3330 /* write value back with RXDCTL.ENABLE bit cleared */
3331 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3332
3333 if (hw->mac.type == ixgbe_mac_82598EB &&
3334 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3335 return;
3336
3337 /* the hardware may take up to 100us to really disable the rx queue */
3338 do {
3339 udelay(10);
3340 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3341 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3342
3343 if (!wait_loop) {
3344 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3345 "the polling period\n", reg_idx);
3346 }
3347}
3348
84418e3b
AD		 3349void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3350 struct ixgbe_ring *ring)
acd37177
AD		 3351{
3352 struct ixgbe_hw *hw = &adapter->hw;
3353 u64 rdba = ring->dma;
9e10e045 3354 u32 rxdctl;
bf29ee6c 3355 u8 reg_idx = ring->reg_idx;
acd37177 3356
9e10e045
AD		 3357 /* disable queue to avoid issues while updating state */
3358 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3359 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3360
acd37177
AD		 3361 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3362 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3363 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3364 ring->count * sizeof(union ixgbe_adv_rx_desc));
3365 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3366 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
84ea2591 3367 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3368
3369 ixgbe_configure_srrctl(adapter, ring);
3370 ixgbe_configure_rscctl(adapter, ring);
3371
3372 if (hw->mac.type == ixgbe_mac_82598EB) {
3373 /*
3374 * enable cache line friendly hardware writes:
3375 * PTHRESH=32 descriptors (half the internal cache),
3376 * this also removes ugly rx_no_buffer_count increment
3377 * HTHRESH=4 descriptors (to minimize latency on fetch)
3378 * WTHRESH=8 burst writeback up to two cache lines
3379 */
3380 rxdctl &= ~0x3FFFFF;
3381 rxdctl |= 0x080420;
3382 }
3383
3384 /* enable receive descriptor ring */
3385 rxdctl |= IXGBE_RXDCTL_ENABLE;
3386 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3387
3388 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3389 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3390}
3391
48654521
AD		 3392static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3393{
3394 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3395 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
48654521
AD		 3396 int p;
3397
3398 /* PSRTYPE must be initialized in non 82598 adapters */
3399 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3400 IXGBE_PSRTYPE_UDPHDR |
3401 IXGBE_PSRTYPE_IPV4HDR |
48654521 3402 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3403 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3404
3405 if (hw->mac.type == ixgbe_mac_82598EB)
3406 return;
3407
fbe7ca7f
AD		 3408 if (rss_i > 3)
3409 psrtype |= 2 << 29;
3410 else if (rss_i > 1)
3411 psrtype |= 1 << 29;
48654521
AD		 3412
3413 for (p = 0; p < adapter->num_rx_pools; p++)
1d9c0bfd 3414 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(p)),
48654521
AD		 3415 psrtype);
3416}
3417
f5b4a52e
AD		 3418static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3419{
3420 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3421 u32 reg_offset, vf_shift;
435b19f6 3422 u32 gcr_ext, vmdctl;
de4c7f65 3423 int i;
f5b4a52e
AD		 3424
3425 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3426 return;
3427
3428 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3429 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3430 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3431 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3432 vmdctl |= IXGBE_VT_CTL_REPLEN;
3433 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3434
1d9c0bfd
AD		 3435 vf_shift = VMDQ_P(0) % 32;
3436 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3437
3438 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3439 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3440 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3441 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3442 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3443 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3444 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3445
3446 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3447 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3448
3449 /*
3450 * Set up VF register offsets for selected VT Mode,
3451 * i.e. 32 or 64 VFs for SR-IOV
3452 */
73079ea0
AD		 3453 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3454 case IXGBE_82599_VMDQ_8Q_MASK:
3455 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3456 break;
3457 case IXGBE_82599_VMDQ_4Q_MASK:
3458 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3459 break;
3460 default:
3461 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3462 break;
3463 }
3464
f5b4a52e
AD		 3465 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3466
435b19f6 3467
a985b6c3 3468 /* Enable MAC Anti-Spoofing */
435b19f6 3469 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3470 adapter->num_vfs);
de4c7f65
GR		 3471 /* For VFs that have spoof checking turned off */
3472 for (i = 0; i < adapter->num_vfs; i++) {
3473 if (!adapter->vfinfo[i].spoofchk_enabled)
3474 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3475 }
f5b4a52e
AD		 3476}
3477
477de6ed 3478static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3479{
9a799d71
AK		 3480 struct ixgbe_hw *hw = &adapter->hw;
3481 struct net_device *netdev = adapter->netdev;
3482 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3483 struct ixgbe_ring *rx_ring;
3484 int i;
3485 u32 mhadd, hlreg0;
48654521 3486
63f39bd1 3487#ifdef IXGBE_FCOE
477de6ed
AD		 3488 /* adjust max frame to be able to do baby jumbo for FCoE */
3489 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3490 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3491 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3492
477de6ed 3493#endif /* IXGBE_FCOE */
872844dd
AD		 3494
3495 /* adjust max frame to be at least the size of a standard frame */
3496 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3497 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3498
477de6ed
AD		 3499 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3500 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3501 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3502 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3503
3504 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3505 }
3506
3507 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3508 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3509 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3510 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3511
0cefafad
JB		 3512 /*
3513 * Setup the HW Rx Head and Tail Descriptor Pointers and
3514 * the Base and Length of the Rx Descriptor Ring
3515 */
9a799d71 3516 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3517 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3518 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3519 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3520 else
7d637bcc 3521 clear_ring_rsc_enabled(rx_ring);
477de6ed 3522 }
477de6ed
AD		 3523}
3524
7367096a
AD		 3525static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3526{
3527 struct ixgbe_hw *hw = &adapter->hw;
3528 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3529
3530 switch (hw->mac.type) {
3531 case ixgbe_mac_82598EB:
3532 /*
3533 * For VMDq support of different descriptor types or
3534 * buffer sizes through the use of multiple SRRCTL
3535 * registers, RDRXCTL.MVMEN must be set to 1
3536 *
3537 * also, the manual doesn't mention it clearly but DCA hints
3538 * will only use queue 0's tags unless this bit is set. Side
3539 * effects of setting this bit are only that SRRCTL must be
3540 * fully programmed [0..15]
3541 */
3542 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3543 break;
3544 case ixgbe_mac_82599EB:
b93a2226 3545 case ixgbe_mac_X540:
7367096a
AD		 3546 /* Disable RSC for ACK packets */
3547 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3548 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3549 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3550 /* hardware requires some bits to be set by default */
3551 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3552 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3553 break;
3554 default:
3555 /* We should do nothing since we don't know this hardware */
3556 return;
3557 }
3558
3559 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3560}
3561
477de6ed
AD		 3562/**
3563 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3564 * @adapter: board private structure
3565 *
3566 * Configure the Rx unit of the MAC after a reset.
3567 **/
3568static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3569{
3570 struct ixgbe_hw *hw = &adapter->hw;
477de6ed
AD		 3571 int i;
3572 u32 rxctrl;
477de6ed
AD		 3573
3574 /* disable receives while setting up the descriptors */
3575 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3576 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3577
3578 ixgbe_setup_psrtype(adapter);
7367096a 3579 ixgbe_setup_rdrxctl(adapter);
477de6ed 3580
9e10e045 3581 /* Program registers for the distribution of queues */
f5b4a52e 3582 ixgbe_setup_mrqc(adapter);
f5b4a52e 3583
477de6ed
AD		 3584 /* set_rx_buffer_len must be called before ring initialization */
3585 ixgbe_set_rx_buffer_len(adapter);
3586
3587 /*
3588 * Setup the HW Rx Head and Tail Descriptor Pointers and
3589 * the Base and Length of the Rx Descriptor Ring
3590 */
9e10e045
AD		 3591 for (i = 0; i < adapter->num_rx_queues; i++)
3592 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3593
9e10e045
AD		 3594 /* disable drop enable for 82598 parts */
3595 if (hw->mac.type == ixgbe_mac_82598EB)
3596 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3597
3598 /* enable all receives */
3599 rxctrl |= IXGBE_RXCTRL_RXEN;
3600 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3601}
3602
80d5c368
PM		 3603static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3604 __be16 proto, u16 vid)
068c89b0
DS		 3605{
3606 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3607 struct ixgbe_hw *hw = &adapter->hw;
3608
3609 /* add VID to filter table */
1d9c0bfd 3610 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3611 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3612
3613 return 0;
068c89b0
DS		 3614}
3615
80d5c368
PM		 3616static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3617 __be16 proto, u16 vid)
068c89b0
DS		 3618{
3619 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3620 struct ixgbe_hw *hw = &adapter->hw;
3621
068c89b0 3622 /* remove VID from filter table */
1d9c0bfd 3623 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3624 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3625
3626 return 0;
068c89b0
DS		 3627}
3628
5f6c0181
JB		 3629/**
3630 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3631 * @adapter: driver data
3632 */
3633static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3634{
3635 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3636 u32 vlnctrl;
3637
3638 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3639 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3640 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3641}
3642
3643/**
3644 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3645 * @adapter: driver data
3646 */
3647static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3648{
3649 struct ixgbe_hw *hw = &adapter->hw;
3650 u32 vlnctrl;
3651
3652 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3653 vlnctrl |= IXGBE_VLNCTRL_VFE;
3654 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3655 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3656}
3657
3658/**
3659 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3660 * @adapter: driver data
3661 */
3662static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3663{
3664 struct ixgbe_hw *hw = &adapter->hw;
3665 u32 vlnctrl;
5f6c0181
JB		 3666 int i, j;
3667
3668 switch (hw->mac.type) {
3669 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3670 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3671 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3672 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3673 break;
3674 case ixgbe_mac_82599EB:
b93a2226 3675 case ixgbe_mac_X540:
5f6c0181
JB		 3676 for (i = 0; i < adapter->num_rx_queues; i++) {
3677 j = adapter->rx_ring[i]->reg_idx;
3678 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3679 vlnctrl &= ~IXGBE_RXDCTL_VME;
3680 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3681 }
3682 break;
3683 default:
3684 break;
3685 }
3686}
3687
3688/**
f62bbb5e 3689 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3690 * @adapter: driver data
3691 */
f62bbb5e 3692static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3693{
3694 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3695 u32 vlnctrl;
5f6c0181
JB		 3696 int i, j;
3697
3698 switch (hw->mac.type) {
3699 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3700 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3701 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3702 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3703 break;
3704 case ixgbe_mac_82599EB:
b93a2226 3705 case ixgbe_mac_X540:
5f6c0181
JB		 3706 for (i = 0; i < adapter->num_rx_queues; i++) {
3707 j = adapter->rx_ring[i]->reg_idx;
3708 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3709 vlnctrl |= IXGBE_RXDCTL_VME;
3710 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3711 }
3712 break;
3713 default:
3714 break;
3715 }
3716}
3717
9a799d71
AK		 3718static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3719{
f62bbb5e 3720 u16 vid;
9a799d71 3721
80d5c368 3722 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3723
3724 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3725 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3726}
3727
2850062a
AD		 3728/**
3729 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3730 * @netdev: network interface device structure
3731 *
3732 * Writes unicast address list to the RAR table.
3733 * Returns: -ENOMEM on failure/insufficient address space
3734 * 0 on no addresses written
3735 * X on writing X addresses to the RAR table
3736 **/
3737static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3738{
3739 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3740 struct ixgbe_hw *hw = &adapter->hw;
95447461 3741 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3742 int count = 0;
3743
95447461
JF		 3744 /* In SR-IOV mode significantly less RAR entries are available */
3745 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3746 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3747
2850062a
AD		 3748 /* return ENOMEM indicating insufficient memory for addresses */
3749 if (netdev_uc_count(netdev) > rar_entries)
3750 return -ENOMEM;
3751
95447461 3752 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3753 struct netdev_hw_addr *ha;
3754 /* return error if we do not support writing to RAR table */
3755 if (!hw->mac.ops.set_rar)
3756 return -ENOMEM;
3757
3758 netdev_for_each_uc_addr(ha, netdev) {
3759 if (!rar_entries)
3760 break;
3761 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3762 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3763 count++;
3764 }
3765 }
3766 /* write the addresses in reverse order to avoid write combining */
3767 for (; rar_entries > 0 ; rar_entries--)
3768 hw->mac.ops.clear_rar(hw, rar_entries);
3769
3770 return count;
3771}
3772
9a799d71 3773/**
2c5645cf 3774 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3775 * @netdev: network interface device structure
3776 *
2c5645cf
CL		 3777 * The set_rx_method entry point is called whenever the unicast/multicast
3778 * address list or the network interface flags are updated. This routine is
3779 * responsible for configuring the hardware for proper unicast, multicast and
3780 * promiscuous mode.
9a799d71 3781 **/
7f870475 3782void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3783{
3784 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3785 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3786 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3787 int count;
9a799d71
AK		 3788
3789 /* Check for Promiscuous and All Multicast modes */
3790
3791 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3792
f5dc442b 3793 /* set all bits that we expect to always be set */
3f2d1c0f 3794 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3795 fctrl |= IXGBE_FCTRL_BAM;
3796 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3797 fctrl |= IXGBE_FCTRL_PMCF;
3798
2850062a
AD		 3799 /* clear the bits we are changing the status of */
3800 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3801
9a799d71 3802 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3803 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3804 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3805 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3806 /* Only disable hardware filter vlans in promiscuous mode
3807 * if SR-IOV and VMDQ are disabled - otherwise ensure
3808 * that hardware VLAN filters remain enabled.
3809 */
3810 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3811 IXGBE_FLAG_SRIOV_ENABLED)))
3812 ixgbe_vlan_filter_disable(adapter);
3813 else
3814 ixgbe_vlan_filter_enable(adapter);
9a799d71 3815 } else {
746b9f02
PM		 3816 if (netdev->flags & IFF_ALLMULTI) {
3817 fctrl |= IXGBE_FCTRL_MPE;
2850062a
AD		 3818 vmolr |= IXGBE_VMOLR_MPE;
3819 } else {
3820 /*
3821 * Write addresses to the MTA, if the attempt fails
25985edc 3822 * then we should just turn on promiscuous mode so
2850062a
AD		 3823 * that we can at least receive multicast traffic
3824 */
3825 hw->mac.ops.update_mc_addr_list(hw, netdev);
3826 vmolr |= IXGBE_VMOLR_ROMPE;
746b9f02 3827 }
5f6c0181 3828 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3829 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3830 }
3831
3832 /*
3833 * Write addresses to available RAR registers, if there is not
3834 * sufficient space to store all the addresses then enable
3835 * unicast promiscuous mode
3836 */
3837 count = ixgbe_write_uc_addr_list(netdev);
3838 if (count < 0) {
3839 fctrl |= IXGBE_FCTRL_UPE;
3840 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3841 }
3842
1d9c0bfd 3843 if (adapter->num_vfs)
1cdd1ec8 3844 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3845
3846 if (hw->mac.type != ixgbe_mac_82598EB) {
3847 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3848 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3849 IXGBE_VMOLR_ROPE);
1d9c0bfd 3850 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3851 }
3852
3f2d1c0f
BG		 3853 /* This is useful for sniffing bad packets. */
3854 if (adapter->netdev->features & NETIF_F_RXALL) {
3855 /* UPE and MPE will be handled by normal PROMISC logic
3856 * in e1000e_set_rx_mode */
3857 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
3858 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
3859 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
3860
3861 fctrl &= ~(IXGBE_FCTRL_DPF);
3862 /* NOTE: VLAN filtering is disabled by setting PROMISC */
3863 }
3864
2850062a 3865 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 3866
f646968f 3867 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 3868 ixgbe_vlan_strip_enable(adapter);
3869 else
3870 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 3871}
3872
021230d4
AV		 3873static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3874{
3875 int q_idx;
021230d4 3876
5a85e737
ET		 3877 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
3878 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 3879 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 3880 }
021230d4
AV		 3881}
3882
3883static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3884{
3885 int q_idx;
021230d4 3886
5a85e737
ET		 3887 local_bh_disable(); /* for ixgbe_qv_lock_napi() */
3888 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 3889 napi_disable(&adapter->q_vector[q_idx]->napi);
5a85e737
ET		 3890 while (!ixgbe_qv_lock_napi(adapter->q_vector[q_idx])) {
3891 pr_info("QV %d locked\n", q_idx);
3892 mdelay(1);
3893 }
3894 }
3895 local_bh_enable();
021230d4
AV		 3896}
3897
7a6b6f51 3898#ifdef CONFIG_IXGBE_DCB
49ce9c2c 3899/**
2f90b865
AD		 3900 * ixgbe_configure_dcb - Configure DCB hardware
3901 * @adapter: ixgbe adapter struct
3902 *
3903 * This is called by the driver on open to configure the DCB hardware.
3904 * This is also called by the gennetlink interface when reconfiguring
3905 * the DCB state.
3906 */
3907static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3908{
3909 struct ixgbe_hw *hw = &adapter->hw;
9806307a 3910 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 3911
67ebd791
AD		 3912 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3913 if (hw->mac.type == ixgbe_mac_82598EB)
3914 netif_set_gso_max_size(adapter->netdev, 65536);
3915 return;
3916 }
3917
3918 if (hw->mac.type == ixgbe_mac_82598EB)
3919 netif_set_gso_max_size(adapter->netdev, 32768);
3920
971060b1 3921#ifdef IXGBE_FCOE
b120818e
JF		 3922 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3923 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 3924#endif
b120818e
JF		 3925
3926 /* reconfigure the hardware */
3927 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 3928 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3929 DCB_TX_CONFIG);
3930 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3931 DCB_RX_CONFIG);
3932 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 3933 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
3934 ixgbe_dcb_hw_ets(&adapter->hw,
3935 adapter->ixgbe_ieee_ets,
3936 max_frame);
3937 ixgbe_dcb_hw_pfc_config(&adapter->hw,
3938 adapter->ixgbe_ieee_pfc->pfc_en,
3939 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 3940 }
8187cd48
JF		 3941
3942 /* Enable RSS Hash per TC */
3943 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 3944 u32 msb = 0;
3945 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 3946
d411a936
AD		 3947 while (rss_i) {
3948 msb++;
3949 rss_i >>= 1;
3950 }
8187cd48 3951
4ae63730
AD		 3952 /* write msb to all 8 TCs in one write */
3953 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 3954 }
2f90b865 3955}
9da712d2
JF		 3956#endif
3957
3958/* Additional bittime to account for IXGBE framing */
3959#define IXGBE_ETH_FRAMING 20
3960
49ce9c2c 3961/**
9da712d2
JF		 3962 * ixgbe_hpbthresh - calculate high water mark for flow control
3963 *
3964 * @adapter: board private structure to calculate for
49ce9c2c 3965 * @pb: packet buffer to calculate
9da712d2
JF		 3966 */
3967static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
3968{
3969 struct ixgbe_hw *hw = &adapter->hw;
3970 struct net_device *dev = adapter->netdev;
3971 int link, tc, kb, marker;
3972 u32 dv_id, rx_pba;
3973
3974 /* Calculate max LAN frame size */
3975 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
3976
3977#ifdef IXGBE_FCOE
3978 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 3979 if ((dev->features & NETIF_F_FCOE_MTU) &&
3980 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
3981 (pb == ixgbe_fcoe_get_tc(adapter)))
3982 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2
JF		 3983
3984#endif
9da712d2
JF		 3985 /* Calculate delay value for device */
3986 switch (hw->mac.type) {
3987 case ixgbe_mac_X540:
3988 dv_id = IXGBE_DV_X540(link, tc);
3989 break;
3990 default:
3991 dv_id = IXGBE_DV(link, tc);
3992 break;
3993 }
3994
3995 /* Loopback switch introduces additional latency */
3996 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3997 dv_id += IXGBE_B2BT(tc);
3998
3999 /* Delay value is calculated in bit times convert to KB */
4000 kb = IXGBE_BT2KB(dv_id);
4001 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4002
4003 marker = rx_pba - kb;
4004
4005 /* It is possible that the packet buffer is not large enough
4006 * to provide required headroom. In this case throw an error
4007 * to user and a do the best we can.
4008 */
4009 if (marker < 0) {
4010 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4011 "headroom to support flow control."
4012 "Decrease MTU or number of traffic classes\n", pb);
4013 marker = tc + 1;
4014 }
4015
4016 return marker;
4017}
4018
49ce9c2c 4019/**
9da712d2
JF		 4020 * ixgbe_lpbthresh - calculate low water mark for for flow control
4021 *
4022 * @adapter: board private structure to calculate for
49ce9c2c 4023 * @pb: packet buffer to calculate
9da712d2
JF		 4024 */
4025static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter)
4026{
4027 struct ixgbe_hw *hw = &adapter->hw;
4028 struct net_device *dev = adapter->netdev;
4029 int tc;
4030 u32 dv_id;
4031
4032 /* Calculate max LAN frame size */
4033 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4034
4035 /* Calculate delay value for device */
4036 switch (hw->mac.type) {
4037 case ixgbe_mac_X540:
4038 dv_id = IXGBE_LOW_DV_X540(tc);
4039 break;
4040 default:
4041 dv_id = IXGBE_LOW_DV(tc);
4042 break;
4043 }
4044
4045 /* Delay value is calculated in bit times convert to KB */
4046 return IXGBE_BT2KB(dv_id);
4047}
4048
4049/*
4050 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4051 */
4052static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4053{
4054 struct ixgbe_hw *hw = &adapter->hw;
4055 int num_tc = netdev_get_num_tc(adapter->netdev);
4056 int i;
4057
4058 if (!num_tc)
4059 num_tc = 1;
4060
4061 hw->fc.low_water = ixgbe_lpbthresh(adapter);
4062
4063 for (i = 0; i < num_tc; i++) {
4064 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
4065
4066 /* Low water marks must not be larger than high water marks */
4067 if (hw->fc.low_water > hw->fc.high_water[i])
4068 hw->fc.low_water = 0;
4069 }
4070}
4071
80605c65
JF		 4072static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4073{
80605c65 4074 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4075 int hdrm;
4076 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4077
4078 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4079 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4080 hdrm = 32 << adapter->fdir_pballoc;
4081 else
4082 hdrm = 0;
80605c65 4083
f7e1027f 4084 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4085 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4086}
4087
e4911d57
AD		 4088static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4089{
4090 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4091 struct hlist_node *node2;
e4911d57
AD		 4092 struct ixgbe_fdir_filter *filter;
4093
4094 spin_lock(&adapter->fdir_perfect_lock);
4095
4096 if (!hlist_empty(&adapter->fdir_filter_list))
4097 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4098
b67bfe0d 4099 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4100 &adapter->fdir_filter_list, fdir_node) {
4101 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4102 &filter->filter,
4103 filter->sw_idx,
4104 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4105 IXGBE_FDIR_DROP_QUEUE :
4106 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4107 }
4108
4109 spin_unlock(&adapter->fdir_perfect_lock);
4110}
4111
9a799d71
AK		 4112static void ixgbe_configure(struct ixgbe_adapter *adapter)
4113{
d2f5e7f3
AS		 4114 struct ixgbe_hw *hw = &adapter->hw;
4115
80605c65 4116 ixgbe_configure_pb(adapter);
7a6b6f51 4117#ifdef CONFIG_IXGBE_DCB
67ebd791 4118 ixgbe_configure_dcb(adapter);
2f90b865 4119#endif
b35d4d42
AD		 4120 /*
4121 * We must restore virtualization before VLANs or else
4122 * the VLVF registers will not be populated
4123 */
4124 ixgbe_configure_virtualization(adapter);
9a799d71 4125
4c1d7b4b 4126 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4127 ixgbe_restore_vlan(adapter);
4128
d2f5e7f3
AS		 4129 switch (hw->mac.type) {
4130 case ixgbe_mac_82599EB:
4131 case ixgbe_mac_X540:
4132 hw->mac.ops.disable_rx_buff(hw);
4133 break;
4134 default:
4135 break;
4136 }
4137
c4cf55e5 4138 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4139 ixgbe_init_fdir_signature_82599(&adapter->hw,
4140 adapter->fdir_pballoc);
e4911d57
AD		 4141 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4142 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4143 adapter->fdir_pballoc);
4144 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4145 }
4c1d7b4b 4146
d2f5e7f3
AS		 4147 switch (hw->mac.type) {
4148 case ixgbe_mac_82599EB:
4149 case ixgbe_mac_X540:
4150 hw->mac.ops.enable_rx_buff(hw);
4151 break;
4152 default:
4153 break;
4154 }
4155
7c8ae65a
AD		 4156#ifdef IXGBE_FCOE
4157 /* configure FCoE L2 filters, redirection table, and Rx control */
4158 ixgbe_configure_fcoe(adapter);
4159
4160#endif /* IXGBE_FCOE */
9a799d71
AK		 4161 ixgbe_configure_tx(adapter);
4162 ixgbe_configure_rx(adapter);
9a799d71
AK		 4163}
4164
e8e26350
PW		 4165static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4166{
4167 switch (hw->phy.type) {
4168 case ixgbe_phy_sfp_avago:
4169 case ixgbe_phy_sfp_ftl:
4170 case ixgbe_phy_sfp_intel:
4171 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4172 case ixgbe_phy_sfp_passive_tyco:
4173 case ixgbe_phy_sfp_passive_unknown:
4174 case ixgbe_phy_sfp_active_unknown:
4175 case ixgbe_phy_sfp_ftl_active:
e8e26350 4176 return true;
8917b447
AD		 4177 case ixgbe_phy_nl:
4178 if (hw->mac.type == ixgbe_mac_82598EB)
4179 return true;
e8e26350
PW		 4180 default:
4181 return false;
4182 }
4183}
4184
0ecc061d 4185/**
e8e26350
PW		 4186 * ixgbe_sfp_link_config - set up SFP+ link
4187 * @adapter: pointer to private adapter struct
4188 **/
4189static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4190{
7086400d 4191 /*
52f33af8 4192 * We are assuming the worst case scenario here, and that
7086400d
AD		 4193 * is that an SFP was inserted/removed after the reset
4194 * but before SFP detection was enabled. As such the best
4195 * solution is to just start searching as soon as we start
4196 */
4197 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4198 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4199
7086400d 4200 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4201}
4202
4203/**
4204 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4205 * @hw: pointer to private hardware struct
4206 *
4207 * Returns 0 on success, negative on failure
4208 **/
e8e26350 4209static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4210{
3d292265
JH		 4211 u32 speed;
4212 bool autoneg, link_up = false;
0ecc061d
PWJ		 4213 u32 ret = IXGBE_ERR_LINK_SETUP;
4214
4215 if (hw->mac.ops.check_link)
3d292265 4216 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4217
4218 if (ret)
4219 goto link_cfg_out;
4220
3d292265
JH		 4221 speed = hw->phy.autoneg_advertised;
4222 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4223 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4224 &autoneg);
0ecc061d
PWJ		 4225 if (ret)
4226 goto link_cfg_out;
4227
8620a103 4228 if (hw->mac.ops.setup_link)
fd0326f2 4229 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4230link_cfg_out:
4231 return ret;
4232}
4233
a34bcfff 4234static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4235{
9a799d71 4236 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4237 u32 gpie = 0;
9a799d71 4238
9b471446 4239 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4240 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4241 IXGBE_GPIE_OCD;
4242 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4243 /*
4244 * use EIAM to auto-mask when MSI-X interrupt is asserted
4245 * this saves a register write for every interrupt
4246 */
4247 switch (hw->mac.type) {
4248 case ixgbe_mac_82598EB:
4249 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4250 break;
9b471446 4251 case ixgbe_mac_82599EB:
b93a2226
DS		 4252 case ixgbe_mac_X540:
4253 default:
9b471446
JB		 4254 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4255 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4256 break;
4257 }
4258 } else {
021230d4
AV		 4259 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4260 * specifically only auto mask tx and rx interrupts */
4261 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4262 }
9a799d71 4263
a34bcfff
AD		 4264 /* XXX: to interrupt immediately for EICS writes, enable this */
4265 /* gpie |= IXGBE_GPIE_EIMEN; */
4266
4267 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4268 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4269
4270 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4271 case IXGBE_82599_VMDQ_8Q_MASK:
4272 gpie |= IXGBE_GPIE_VTMODE_16;
4273 break;
4274 case IXGBE_82599_VMDQ_4Q_MASK:
4275 gpie |= IXGBE_GPIE_VTMODE_32;
4276 break;
4277 default:
4278 gpie |= IXGBE_GPIE_VTMODE_64;
4279 break;
4280 }
119fc60a
MC		 4281 }
4282
5fdd31f9 4283 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4284 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4285 switch (adapter->hw.mac.type) {
4286 case ixgbe_mac_82599EB:
4287 gpie |= IXGBE_SDP0_GPIEN;
4288 break;
4289 case ixgbe_mac_X540:
4290 gpie |= IXGBE_EIMS_TS;
4291 break;
4292 default:
4293 break;
4294 }
4295 }
5fdd31f9 4296
a34bcfff
AD		 4297 /* Enable fan failure interrupt */
4298 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4299 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4300
2698b208 4301 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4302 gpie |= IXGBE_SDP1_GPIEN;
4303 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4304 }
a34bcfff
AD		 4305
4306 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4307}
4308
c7ccde0f 4309static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4310{
4311 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4312 int err;
a34bcfff
AD		 4313 u32 ctrl_ext;
4314
4315 ixgbe_get_hw_control(adapter);
4316 ixgbe_setup_gpie(adapter);
e8e26350 4317
9a799d71
AK		 4318 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4319 ixgbe_configure_msix(adapter);
4320 else
4321 ixgbe_configure_msi_and_legacy(adapter);
4322
ec74a471
ET		 4323 /* enable the optics for 82599 SFP+ fiber */
4324 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4325 hw->mac.ops.enable_tx_laser(hw);
4326
9a799d71 4327 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4328 ixgbe_napi_enable_all(adapter);
4329
73c4b7cd
AD		 4330 if (ixgbe_is_sfp(hw)) {
4331 ixgbe_sfp_link_config(adapter);
4332 } else {
4333 err = ixgbe_non_sfp_link_config(hw);
4334 if (err)
4335 e_err(probe, "link_config FAILED %d\n", err);
4336 }
4337
021230d4
AV		 4338 /* clear any pending interrupts, may auto mask */
4339 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4340 ixgbe_irq_enable(adapter, true, true);
9a799d71 4341
bf069c97
DS		 4342 /*
4343 * If this adapter has a fan, check to see if we had a failure
4344 * before we enabled the interrupt.
4345 */
4346 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4347 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4348 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4349 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4350 }
4351
1da100bb 4352 /* enable transmits */
477de6ed 4353 netif_tx_start_all_queues(adapter->netdev);
1da100bb 4354
9a799d71
AK		 4355 /* bring the link up in the watchdog, this could race with our first
4356 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4357 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4358 adapter->link_check_timeout = jiffies;
7086400d 4359 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4360
4361 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4362 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4363 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4364 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4365}
4366
d4f80882
AV		 4367void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4368{
4369 WARN_ON(in_interrupt());
7086400d
AD		 4370 /* put off any impending NetWatchDogTimeout */
4371 adapter->netdev->trans_start = jiffies;
4372
d4f80882 4373 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4374 usleep_range(1000, 2000);
d4f80882 4375 ixgbe_down(adapter);
5809a1ae
GR		 4376 /*
4377 * If SR-IOV enabled then wait a bit before bringing the adapter
4378 * back up to give the VFs time to respond to the reset. The
4379 * two second wait is based upon the watchdog timer cycle in
4380 * the VF driver.
4381 */
4382 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4383 msleep(2000);
d4f80882
AV		 4384 ixgbe_up(adapter);
4385 clear_bit(__IXGBE_RESETTING, &adapter->state);
4386}
4387
c7ccde0f 4388void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4389{
4390 /* hardware has been reset, we need to reload some things */
4391 ixgbe_configure(adapter);
4392
c7ccde0f 4393 ixgbe_up_complete(adapter);
9a799d71
AK		 4394}
4395
4396void ixgbe_reset(struct ixgbe_adapter *adapter)
4397{
c44ade9e 4398 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4399 int err;
4400
7086400d
AD		 4401 /* lock SFP init bit to prevent race conditions with the watchdog */
4402 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4403 usleep_range(1000, 2000);
4404
4405 /* clear all SFP and link config related flags while holding SFP_INIT */
4406 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4407 IXGBE_FLAG2_SFP_NEEDS_RESET);
4408 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4409
8ca783ab 4410 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4411 switch (err) {
4412 case 0:
4413 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4414 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4415 break;
4416 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4417 e_dev_err("master disable timed out\n");
da4dd0f7 4418 break;
794caeb2
PWJ		 4419 case IXGBE_ERR_EEPROM_VERSION:
4420 /* We are running on a pre-production device, log a warning */
849c4542 4421 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4422 "Please be aware there may be issues associated with "
849c4542
ET		 4423 "your hardware. If you are experiencing problems "
4424 "please contact your Intel or hardware "
4425 "representative who provided you with this "
4426 "hardware.\n");
794caeb2 4427 break;
da4dd0f7 4428 default:
849c4542 4429 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4430 }
9a799d71 4431
7086400d
AD		 4432 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4433
9a799d71 4434 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4435 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4436
4437 /* update SAN MAC vmdq pool selection */
4438 if (hw->mac.san_mac_rar_index)
4439 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4440
1a71ab24
JK		 4441 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
4442 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4443}
4444
9a799d71
AK		 4445/**
4446 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
9a799d71
AK		 4447 * @rx_ring: ring to free buffers from
4448 **/
b6ec895e 4449static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
9a799d71 4450{
b6ec895e 4451 struct device *dev = rx_ring->dev;
9a799d71 4452 unsigned long size;
b6ec895e 4453 u16 i;
9a799d71 4454
84418e3b
AD		 4455 /* ring already cleared, nothing to do */
4456 if (!rx_ring->rx_buffer_info)
4457 return;
9a799d71 4458
84418e3b 4459 /* Free all the Rx ring sk_buffs */
9a799d71 4460 for (i = 0; i < rx_ring->count; i++) {
f800326d
AD		 4461 struct ixgbe_rx_buffer *rx_buffer;
4462
4463 rx_buffer = &rx_ring->rx_buffer_info[i];
4464 if (rx_buffer->skb) {
4465 struct sk_buff *skb = rx_buffer->skb;
4466 if (IXGBE_CB(skb)->page_released) {
4467 dma_unmap_page(dev,
4468 IXGBE_CB(skb)->dma,
4469 ixgbe_rx_bufsz(rx_ring),
4470 DMA_FROM_DEVICE);
4471 IXGBE_CB(skb)->page_released = false;
4c1975d7
AD		 4472 }
4473 dev_kfree_skb(skb);
9a799d71 4474 }
f800326d
AD		 4475 rx_buffer->skb = NULL;
4476 if (rx_buffer->dma)
4477 dma_unmap_page(dev, rx_buffer->dma,
4478 ixgbe_rx_pg_size(rx_ring),
4479 DMA_FROM_DEVICE);
4480 rx_buffer->dma = 0;
4481 if (rx_buffer->page)
dd411ec4
AD		 4482 __free_pages(rx_buffer->page,
4483 ixgbe_rx_pg_order(rx_ring));
f800326d 4484 rx_buffer->page = NULL;
9a799d71
AK		 4485 }
4486
4487 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4488 memset(rx_ring->rx_buffer_info, 0, size);
4489
4490 /* Zero out the descriptor ring */
4491 memset(rx_ring->desc, 0, rx_ring->size);
4492
f800326d 4493 rx_ring->next_to_alloc = 0;
9a799d71
AK		 4494 rx_ring->next_to_clean = 0;
4495 rx_ring->next_to_use = 0;
9a799d71
AK		 4496}
4497
4498/**
4499 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4500 * @tx_ring: ring to be cleaned
4501 **/
b6ec895e 4502static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4503{
4504 struct ixgbe_tx_buffer *tx_buffer_info;
4505 unsigned long size;
b6ec895e 4506 u16 i;
9a799d71 4507
84418e3b
AD		 4508 /* ring already cleared, nothing to do */
4509 if (!tx_ring->tx_buffer_info)
4510 return;
9a799d71 4511
84418e3b 4512 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4513 for (i = 0; i < tx_ring->count; i++) {
4514 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4515 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4516 }
4517
dad8a3b3
JF		 4518 netdev_tx_reset_queue(txring_txq(tx_ring));
4519
9a799d71
AK		 4520 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4521 memset(tx_ring->tx_buffer_info, 0, size);
4522
4523 /* Zero out the descriptor ring */
4524 memset(tx_ring->desc, 0, tx_ring->size);
4525
4526 tx_ring->next_to_use = 0;
4527 tx_ring->next_to_clean = 0;
9a799d71
AK		 4528}
4529
4530/**
021230d4 4531 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4532 * @adapter: board private structure
4533 **/
021230d4 4534static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4535{
4536 int i;
4537
021230d4 4538 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4539 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4540}
4541
4542/**
021230d4 4543 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4544 * @adapter: board private structure
4545 **/
021230d4 4546static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4547{
4548 int i;
4549
021230d4 4550 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4551 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4552}
4553
e4911d57
AD		 4554static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4555{
b67bfe0d 4556 struct hlist_node *node2;
e4911d57
AD		 4557 struct ixgbe_fdir_filter *filter;
4558
4559 spin_lock(&adapter->fdir_perfect_lock);
4560
b67bfe0d 4561 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4562 &adapter->fdir_filter_list, fdir_node) {
4563 hlist_del(&filter->fdir_node);
4564 kfree(filter);
4565 }
4566 adapter->fdir_filter_count = 0;
4567
4568 spin_unlock(&adapter->fdir_perfect_lock);
4569}
4570
9a799d71
AK		 4571void ixgbe_down(struct ixgbe_adapter *adapter)
4572{
4573 struct net_device *netdev = adapter->netdev;
7f821875 4574 struct ixgbe_hw *hw = &adapter->hw;
9a799d71 4575 u32 rxctrl;
bf29ee6c 4576 int i;
9a799d71
AK		 4577
4578 /* signal that we are down to the interrupt handler */
4579 set_bit(__IXGBE_DOWN, &adapter->state);
4580
4581 /* disable receives */
7f821875
JB		 4582 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4583 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4584
2d39d576
YZ		 4585 /* disable all enabled rx queues */
4586 for (i = 0; i < adapter->num_rx_queues; i++)
4587 /* this call also flushes the previous write */
4588 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4589
032b4325 4590 usleep_range(10000, 20000);
9a799d71 4591
7f821875
JB		 4592 netif_tx_stop_all_queues(netdev);
4593
7086400d 4594 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4595 netif_carrier_off(netdev);
4596 netif_tx_disable(netdev);
4597
4598 ixgbe_irq_disable(adapter);
4599
4600 ixgbe_napi_disable_all(adapter);
4601
d034acf1
AD		 4602 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4603 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4604 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4605
4606 del_timer_sync(&adapter->service_timer);
4607
34cecbbf 4608 if (adapter->num_vfs) {
8e34d1aa
AD		 4609 /* Clear EITR Select mapping */
4610 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4611
4612 /* Mark all the VFs as inactive */
4613 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4614 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4615
34cecbbf
AD		 4616 /* ping all the active vfs to let them know we are going down */
4617 ixgbe_ping_all_vfs(adapter);
4618
4619 /* Disable all VFTE/VFRE TX/RX */
4620 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4621 }
4622
7f821875
JB		 4623 /* disable transmits in the hardware now that interrupts are off */
4624 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4625 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4626 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4627 }
34cecbbf
AD		 4628
4629 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4630 switch (hw->mac.type) {
4631 case ixgbe_mac_82599EB:
b93a2226 4632 case ixgbe_mac_X540:
88512539 4633 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4634 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4635 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4636 break;
4637 default:
4638 break;
4639 }
7f821875 4640
6f4a0e45
PL		 4641 if (!pci_channel_offline(adapter->pdev))
4642 ixgbe_reset(adapter);
c6ecf39a 4643
ec74a471
ET		 4644 /* power down the optics for 82599 SFP+ fiber */
4645 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4646 hw->mac.ops.disable_tx_laser(hw);
4647
9a799d71
AK		 4648 ixgbe_clean_all_tx_rings(adapter);
4649 ixgbe_clean_all_rx_rings(adapter);
4650
5dd2d332 4651#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4652 /* since we reset the hardware DCA settings were cleared */
e35ec126 4653 ixgbe_setup_dca(adapter);
96b0e0f6 4654#endif
9a799d71
AK		 4655}
4656
9a799d71
AK		 4657/**
4658 * ixgbe_tx_timeout - Respond to a Tx Hang
4659 * @netdev: network interface device structure
4660 **/
4661static void ixgbe_tx_timeout(struct net_device *netdev)
4662{
4663 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4664
4665 /* Do the reset outside of interrupt context */
c83c6cbd 4666 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 4667}
4668
9a799d71
AK		 4669/**
4670 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4671 * @adapter: board private structure to initialize
4672 *
4673 * ixgbe_sw_init initializes the Adapter private data structure.
4674 * Fields are initialized based on PCI device information and
4675 * OS network device settings (MTU size).
4676 **/
9f9a12f8 4677static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 4678{
4679 struct ixgbe_hw *hw = &adapter->hw;
4680 struct pci_dev *pdev = adapter->pdev;
d3cb9869 4681 unsigned int rss, fdir;
cb6d0f5e 4682 u32 fwsm;
7a6b6f51 4683#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 4684 int j;
4685 struct tc_configuration *tc;
4686#endif
021230d4 4687
c44ade9e
JB		 4688 /* PCI config space info */
4689
4690 hw->vendor_id = pdev->vendor;
4691 hw->device_id = pdev->device;
4692 hw->revision_id = pdev->revision;
4693 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4694 hw->subsystem_device_id = pdev->subsystem_device;
4695
8fc3bb6d 4696 /* Set common capability flags and settings */
3ed69d7e 4697 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 4698 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 4699 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4700 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 4701 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
4702 adapter->atr_sample_rate = 20;
d3cb9869
AD		 4703 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
4704 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 4705 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
4706#ifdef CONFIG_IXGBE_DCA
4707 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
4708#endif
4709#ifdef IXGBE_FCOE
4710 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4711 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4712#ifdef CONFIG_IXGBE_DCB
4713 /* Default traffic class to use for FCoE */
4714 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4715#endif /* CONFIG_IXGBE_DCB */
4716#endif /* IXGBE_FCOE */
4717
4718 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 4719 switch (hw->mac.type) {
4720 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 4721 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
4722 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
4723
bf069c97
DS		 4724 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4725 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 4726
49c7ffbe 4727 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 4728 adapter->ring_feature[RING_F_FDIR].limit = 0;
4729 adapter->atr_sample_rate = 0;
4730 adapter->fdir_pballoc = 0;
4731#ifdef IXGBE_FCOE
4732 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
4733 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4734#ifdef CONFIG_IXGBE_DCB
4735 adapter->fcoe.up = 0;
4736#endif /* IXGBE_DCB */
4737#endif /* IXGBE_FCOE */
4738 break;
4739 case ixgbe_mac_82599EB:
4740 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4741 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 4742 break;
b93a2226 4743 case ixgbe_mac_X540:
cb6d0f5e
JK		 4744 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4745 if (fwsm & IXGBE_FWSM_TS_ENABLED)
4746 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 4747 break;
4748 default:
4749 break;
f8212f97 4750 }
2f90b865 4751
7c8ae65a
AD		 4752#ifdef IXGBE_FCOE
4753 /* FCoE support exists, always init the FCoE lock */
4754 spin_lock_init(&adapter->fcoe.lock);
4755
4756#endif
1fc5f038
AD		 4757 /* n-tuple support exists, always init our spinlock */
4758 spin_lock_init(&adapter->fdir_perfect_lock);
4759
7a6b6f51 4760#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 4761 switch (hw->mac.type) {
4762 case ixgbe_mac_X540:
4763 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
4764 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
4765 break;
4766 default:
4767 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
4768 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
4769 break;
4770 }
4771
2f90b865
AD		 4772 /* Configure DCB traffic classes */
4773 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4774 tc = &adapter->dcb_cfg.tc_config[j];
4775 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4776 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4777 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4778 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4779 tc->dcb_pfc = pfc_disabled;
4780 }
4de2a022
JF		 4781
4782 /* Initialize default user to priority mapping, UPx->TC0 */
4783 tc = &adapter->dcb_cfg.tc_config[0];
4784 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
4785 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
4786
2f90b865
AD		 4787 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4788 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 4789 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 4790 adapter->dcb_set_bitmap = 0x00;
3032309b 4791 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 4792 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
4793 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 4794
4795#endif
9a799d71
AK		 4796
4797 /* default flow control settings */
cd7664f6 4798 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 4799 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 4800 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 4801 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4802 hw->fc.send_xon = true;
73d80953 4803 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 4804
99d74487
AD		 4805#ifdef CONFIG_PCI_IOV
4806 /* assign number of SR-IOV VFs */
4807 if (hw->mac.type != ixgbe_mac_82598EB)
4808 adapter->num_vfs = (max_vfs > 63) ? 0 : max_vfs;
4809
4810#endif
30efa5a3 4811 /* enable itr by default in dynamic mode */
f7554a2b 4812 adapter->rx_itr_setting = 1;
f7554a2b 4813 adapter->tx_itr_setting = 1;
30efa5a3 4814
30efa5a3
JB		 4815 /* set default ring sizes */
4816 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4817 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4818
bd198058 4819 /* set default work limits */
59224555 4820 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 4821
9a799d71 4822 /* initialize eeprom parameters */
c44ade9e 4823 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 4824 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 4825 return -EIO;
4826 }
4827
9a799d71
AK		 4828 set_bit(__IXGBE_DOWN, &adapter->state);
4829
4830 return 0;
4831}
4832
4833/**
4834 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 4835 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4836 *
4837 * Return 0 on success, negative on failure
4838 **/
b6ec895e 4839int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 4840{
b6ec895e 4841 struct device *dev = tx_ring->dev;
de88eeeb
AD		 4842 int orig_node = dev_to_node(dev);
4843 int numa_node = -1;
9a799d71
AK		 4844 int size;
4845
3a581073 4846 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 4847
4848 if (tx_ring->q_vector)
4849 numa_node = tx_ring->q_vector->numa_node;
4850
4851 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4852 if (!tx_ring->tx_buffer_info)
89bf67f1 4853 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 4854 if (!tx_ring->tx_buffer_info)
4855 goto err;
9a799d71
AK		 4856
4857 /* round up to nearest 4K */
12207e49 4858 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 4859 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 4860
de88eeeb
AD		 4861 set_dev_node(dev, numa_node);
4862 tx_ring->desc = dma_alloc_coherent(dev,
4863 tx_ring->size,
4864 &tx_ring->dma,
4865 GFP_KERNEL);
4866 set_dev_node(dev, orig_node);
4867 if (!tx_ring->desc)
4868 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
4869 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 4870 if (!tx_ring->desc)
4871 goto err;
9a799d71 4872
3a581073
JB		 4873 tx_ring->next_to_use = 0;
4874 tx_ring->next_to_clean = 0;
9a799d71 4875 return 0;
e01c31a5
JB		 4876
4877err:
4878 vfree(tx_ring->tx_buffer_info);
4879 tx_ring->tx_buffer_info = NULL;
b6ec895e 4880 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 4881 return -ENOMEM;
9a799d71
AK		 4882}
4883
69888674
AD		 4884/**
4885 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4886 * @adapter: board private structure
4887 *
4888 * If this function returns with an error, then it's possible one or
4889 * more of the rings is populated (while the rest are not). It is the
4890 * callers duty to clean those orphaned rings.
4891 *
4892 * Return 0 on success, negative on failure
4893 **/
4894static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
4895{
4896 int i, err = 0;
4897
4898 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 4899 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4900 if (!err)
4901 continue;
de3d5b94 4902
396e799c 4903 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 4904 goto err_setup_tx;
69888674
AD		 4905 }
4906
de3d5b94
AD		 4907 return 0;
4908err_setup_tx:
4909 /* rewind the index freeing the rings as we go */
4910 while (i--)
4911 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 4912 return err;
4913}
4914
9a799d71
AK		 4915/**
4916 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 4917 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 4918 *
4919 * Returns 0 on success, negative on failure
4920 **/
b6ec895e 4921int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 4922{
b6ec895e 4923 struct device *dev = rx_ring->dev;
de88eeeb
AD		 4924 int orig_node = dev_to_node(dev);
4925 int numa_node = -1;
021230d4 4926 int size;
9a799d71 4927
3a581073 4928 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 4929
4930 if (rx_ring->q_vector)
4931 numa_node = rx_ring->q_vector->numa_node;
4932
4933 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 4934 if (!rx_ring->rx_buffer_info)
89bf67f1 4935 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 4936 if (!rx_ring->rx_buffer_info)
4937 goto err;
9a799d71 4938
9a799d71 4939 /* Round up to nearest 4K */
3a581073
JB		 4940 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
4941 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 4942
de88eeeb
AD		 4943 set_dev_node(dev, numa_node);
4944 rx_ring->desc = dma_alloc_coherent(dev,
4945 rx_ring->size,
4946 &rx_ring->dma,
4947 GFP_KERNEL);
4948 set_dev_node(dev, orig_node);
4949 if (!rx_ring->desc)
4950 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
4951 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 4952 if (!rx_ring->desc)
4953 goto err;
9a799d71 4954
3a581073
JB		 4955 rx_ring->next_to_clean = 0;
4956 rx_ring->next_to_use = 0;
9a799d71
AK		 4957
4958 return 0;
b6ec895e
AD		 4959err:
4960 vfree(rx_ring->rx_buffer_info);
4961 rx_ring->rx_buffer_info = NULL;
4962 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 4963 return -ENOMEM;
9a799d71
AK		 4964}
4965
69888674
AD		 4966/**
4967 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4968 * @adapter: board private structure
4969 *
4970 * If this function returns with an error, then it's possible one or
4971 * more of the rings is populated (while the rest are not). It is the
4972 * callers duty to clean those orphaned rings.
4973 *
4974 * Return 0 on success, negative on failure
4975 **/
69888674
AD		 4976static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4977{
4978 int i, err = 0;
4979
4980 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 4981 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4982 if (!err)
4983 continue;
de3d5b94 4984
396e799c 4985 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 4986 goto err_setup_rx;
69888674
AD		 4987 }
4988
7c8ae65a
AD		 4989#ifdef IXGBE_FCOE
4990 err = ixgbe_setup_fcoe_ddp_resources(adapter);
4991 if (!err)
4992#endif
4993 return 0;
de3d5b94
AD		 4994err_setup_rx:
4995 /* rewind the index freeing the rings as we go */
4996 while (i--)
4997 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 4998 return err;
4999}
5000
9a799d71
AK		 5001/**
5002 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5003 * @tx_ring: Tx descriptor ring for a specific queue
5004 *
5005 * Free all transmit software resources
5006 **/
b6ec895e 5007void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5008{
b6ec895e 5009 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5010
5011 vfree(tx_ring->tx_buffer_info);
5012 tx_ring->tx_buffer_info = NULL;
5013
b6ec895e
AD		 5014 /* if not set, then don't free */
5015 if (!tx_ring->desc)
5016 return;
5017
5018 dma_free_coherent(tx_ring->dev, tx_ring->size,
5019 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5020
5021 tx_ring->desc = NULL;
5022}
5023
5024/**
5025 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5026 * @adapter: board private structure
5027 *
5028 * Free all transmit software resources
5029 **/
5030static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5031{
5032 int i;
5033
5034 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5035 if (adapter->tx_ring[i]->desc)
b6ec895e 5036 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5037}
5038
5039/**
b4617240 5040 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5041 * @rx_ring: ring to clean the resources from
5042 *
5043 * Free all receive software resources
5044 **/
b6ec895e 5045void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5046{
b6ec895e 5047 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5048
5049 vfree(rx_ring->rx_buffer_info);
5050 rx_ring->rx_buffer_info = NULL;
5051
b6ec895e
AD		 5052 /* if not set, then don't free */
5053 if (!rx_ring->desc)
5054 return;
5055
5056 dma_free_coherent(rx_ring->dev, rx_ring->size,
5057 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5058
5059 rx_ring->desc = NULL;
5060}
5061
5062/**
5063 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5064 * @adapter: board private structure
5065 *
5066 * Free all receive software resources
5067 **/
5068static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5069{
5070 int i;
5071
7c8ae65a
AD		 5072#ifdef IXGBE_FCOE
5073 ixgbe_free_fcoe_ddp_resources(adapter);
5074
5075#endif
9a799d71 5076 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5077 if (adapter->rx_ring[i]->desc)
b6ec895e 5078 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5079}
5080
9a799d71
AK		 5081/**
5082 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5083 * @netdev: network interface device structure
5084 * @new_mtu: new value for maximum frame size
5085 *
5086 * Returns 0 on success, negative on failure
5087 **/
5088static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5089{
5090 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5091 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5092
42c783c5 5093 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5094 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5095 return -EINVAL;
5096
5097 /*
872844dd
AD		 5098 * For 82599EB we cannot allow legacy VFs to enable their receive
5099 * paths when MTU greater than 1500 is configured. So display a
5100 * warning that legacy VFs will be disabled.
655309e9
AD		 5101 */
5102 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5103 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5104 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5105 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5106
396e799c 5107 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5108
021230d4 5109 /* must set new MTU before calling down or up */
9a799d71
AK		 5110 netdev->mtu = new_mtu;
5111
d4f80882
AV		 5112 if (netif_running(netdev))
5113 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5114
5115 return 0;
5116}
5117
5118/**
5119 * ixgbe_open - Called when a network interface is made active
5120 * @netdev: network interface device structure
5121 *
5122 * Returns 0 on success, negative value on failure
5123 *
5124 * The open entry point is called when a network interface is made
5125 * active by the system (IFF_UP). At this point all resources needed
5126 * for transmit and receive operations are allocated, the interrupt
5127 * handler is registered with the OS, the watchdog timer is started,
5128 * and the stack is notified that the interface is ready.
5129 **/
5130static int ixgbe_open(struct net_device *netdev)
5131{
5132 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5133 int err;
4bebfaa5
AK		 5134
5135 /* disallow open during test */
5136 if (test_bit(__IXGBE_TESTING, &adapter->state))
5137 return -EBUSY;
9a799d71 5138
54386467
JB		 5139 netif_carrier_off(netdev);
5140
9a799d71
AK		 5141 /* allocate transmit descriptors */
5142 err = ixgbe_setup_all_tx_resources(adapter);
5143 if (err)
5144 goto err_setup_tx;
5145
9a799d71
AK		 5146 /* allocate receive descriptors */
5147 err = ixgbe_setup_all_rx_resources(adapter);
5148 if (err)
5149 goto err_setup_rx;
5150
5151 ixgbe_configure(adapter);
5152
021230d4 5153 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5154 if (err)
5155 goto err_req_irq;
5156
ac802f5d
AD		 5157 /* Notify the stack of the actual queue counts. */
5158 err = netif_set_real_num_tx_queues(netdev,
5159 adapter->num_rx_pools > 1 ? 1 :
5160 adapter->num_tx_queues);
5161 if (err)
5162 goto err_set_queues;
5163
5164
5165 err = netif_set_real_num_rx_queues(netdev,
5166 adapter->num_rx_pools > 1 ? 1 :
5167 adapter->num_rx_queues);
5168 if (err)
5169 goto err_set_queues;
5170
1a71ab24 5171 ixgbe_ptp_init(adapter);
1a71ab24 5172
c7ccde0f 5173 ixgbe_up_complete(adapter);
9a799d71
AK		 5174
5175 return 0;
5176
ac802f5d
AD		 5177err_set_queues:
5178 ixgbe_free_irq(adapter);
9a799d71 5179err_req_irq:
a20a1199 5180 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5181err_setup_rx:
a20a1199 5182 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5183err_setup_tx:
9a799d71
AK		 5184 ixgbe_reset(adapter);
5185
5186 return err;
5187}
5188
5189/**
5190 * ixgbe_close - Disables a network interface
5191 * @netdev: network interface device structure
5192 *
5193 * Returns 0, this is not allowed to fail
5194 *
5195 * The close entry point is called when an interface is de-activated
5196 * by the OS. The hardware is still under the drivers control, but
5197 * needs to be disabled. A global MAC reset is issued to stop the
5198 * hardware, and all transmit and receive resources are freed.
5199 **/
5200static int ixgbe_close(struct net_device *netdev)
5201{
5202 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5203
1a71ab24 5204 ixgbe_ptp_stop(adapter);
1a71ab24 5205
9a799d71
AK		 5206 ixgbe_down(adapter);
5207 ixgbe_free_irq(adapter);
5208
e4911d57
AD		 5209 ixgbe_fdir_filter_exit(adapter);
5210
9a799d71
AK		 5211 ixgbe_free_all_tx_resources(adapter);
5212 ixgbe_free_all_rx_resources(adapter);
5213
5eba3699 5214 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5215
5216 return 0;
5217}
5218
b3c8b4ba
AD		 5219#ifdef CONFIG_PM
5220static int ixgbe_resume(struct pci_dev *pdev)
5221{
c60fbb00
AD		 5222 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5223 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5224 u32 err;
5225
5226 pci_set_power_state(pdev, PCI_D0);
5227 pci_restore_state(pdev);
656ab817
DS		 5228 /*
5229 * pci_restore_state clears dev->state_saved so call
5230 * pci_save_state to restore it.
5231 */
5232 pci_save_state(pdev);
9ce77666 5233
5234 err = pci_enable_device_mem(pdev);
b3c8b4ba 5235 if (err) {
849c4542 5236 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5237 return err;
5238 }
5239 pci_set_master(pdev);
5240
dd4d8ca6 5241 pci_wake_from_d3(pdev, false);
b3c8b4ba 5242
b3c8b4ba
AD		 5243 ixgbe_reset(adapter);
5244
495dce12
WJP		 5245 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5246
ac802f5d
AD		 5247 rtnl_lock();
5248 err = ixgbe_init_interrupt_scheme(adapter);
5249 if (!err && netif_running(netdev))
c60fbb00 5250 err = ixgbe_open(netdev);
ac802f5d
AD		 5251
5252 rtnl_unlock();
5253
5254 if (err)
5255 return err;
b3c8b4ba
AD		 5256
5257 netif_device_attach(netdev);
5258
5259 return 0;
5260}
b3c8b4ba 5261#endif /* CONFIG_PM */
9d8d05ae
RW		 5262
5263static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5264{
c60fbb00
AD		 5265 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5266 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5267 struct ixgbe_hw *hw = &adapter->hw;
5268 u32 ctrl, fctrl;
5269 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5270#ifdef CONFIG_PM
5271 int retval = 0;
5272#endif
5273
5274 netif_device_detach(netdev);
5275
499ab5cc 5276 rtnl_lock();
b3c8b4ba
AD		 5277 if (netif_running(netdev)) {
5278 ixgbe_down(adapter);
5279 ixgbe_free_irq(adapter);
5280 ixgbe_free_all_tx_resources(adapter);
5281 ixgbe_free_all_rx_resources(adapter);
5282 }
499ab5cc 5283 rtnl_unlock();
b3c8b4ba 5284
5f5ae6fc
AD		 5285 ixgbe_clear_interrupt_scheme(adapter);
5286
b3c8b4ba
AD		 5287#ifdef CONFIG_PM
5288 retval = pci_save_state(pdev);
5289 if (retval)
5290 return retval;
4df10466 5291
b3c8b4ba 5292#endif
e8e26350
PW		 5293 if (wufc) {
5294 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5295
ec74a471
ET		 5296 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5297 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5298 hw->mac.ops.enable_tx_laser(hw);
5299
e8e26350
PW		 5300 /* turn on all-multi mode if wake on multicast is enabled */
5301 if (wufc & IXGBE_WUFC_MC) {
5302 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5303 fctrl |= IXGBE_FCTRL_MPE;
5304 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5305 }
5306
5307 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5308 ctrl |= IXGBE_CTRL_GIO_DIS;
5309 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5310
5311 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5312 } else {
5313 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5314 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5315 }
5316
bd508178
AD		 5317 switch (hw->mac.type) {
5318 case ixgbe_mac_82598EB:
dd4d8ca6 5319 pci_wake_from_d3(pdev, false);
bd508178
AD		 5320 break;
5321 case ixgbe_mac_82599EB:
b93a2226 5322 case ixgbe_mac_X540:
bd508178
AD		 5323 pci_wake_from_d3(pdev, !!wufc);
5324 break;
5325 default:
5326 break;
5327 }
b3c8b4ba 5328
9d8d05ae
RW		 5329 *enable_wake = !!wufc;
5330
b3c8b4ba
AD		 5331 ixgbe_release_hw_control(adapter);
5332
5333 pci_disable_device(pdev);
5334
9d8d05ae
RW		 5335 return 0;
5336}
5337
5338#ifdef CONFIG_PM
5339static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5340{
5341 int retval;
5342 bool wake;
5343
5344 retval = __ixgbe_shutdown(pdev, &wake);
5345 if (retval)
5346 return retval;
5347
5348 if (wake) {
5349 pci_prepare_to_sleep(pdev);
5350 } else {
5351 pci_wake_from_d3(pdev, false);
5352 pci_set_power_state(pdev, PCI_D3hot);
5353 }
b3c8b4ba
AD		 5354
5355 return 0;
5356}
9d8d05ae 5357#endif /* CONFIG_PM */
b3c8b4ba
AD		 5358
5359static void ixgbe_shutdown(struct pci_dev *pdev)
5360{
9d8d05ae
RW		 5361 bool wake;
5362
5363 __ixgbe_shutdown(pdev, &wake);
5364
5365 if (system_state == SYSTEM_POWER_OFF) {
5366 pci_wake_from_d3(pdev, wake);
5367 pci_set_power_state(pdev, PCI_D3hot);
5368 }
b3c8b4ba
AD		 5369}
5370
9a799d71
AK		 5371/**
5372 * ixgbe_update_stats - Update the board statistics counters.
5373 * @adapter: board private structure
5374 **/
5375void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5376{
2d86f139 5377 struct net_device *netdev = adapter->netdev;
9a799d71 5378 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5379 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5380 u64 total_mpc = 0;
5381 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5382 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5383 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5384 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5385
d08935c2
DS		 5386 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5387 test_bit(__IXGBE_RESETTING, &adapter->state))
5388 return;
5389
94b982b2 5390 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5391 u64 rsc_count = 0;
94b982b2 5392 u64 rsc_flush = 0;
94b982b2 5393 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5394 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5395 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5396 }
5397 adapter->rsc_total_count = rsc_count;
5398 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5399 }
5400
5b7da515
AD		 5401 for (i = 0; i < adapter->num_rx_queues; i++) {
5402 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5403 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5404 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5405 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5406 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5407 bytes += rx_ring->stats.bytes;
5408 packets += rx_ring->stats.packets;
5409 }
5410 adapter->non_eop_descs = non_eop_descs;
5411 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5412 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5413 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5414 netdev->stats.rx_bytes = bytes;
5415 netdev->stats.rx_packets = packets;
5416
5417 bytes = 0;
5418 packets = 0;
7ca3bc58 5419 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5420 for (i = 0; i < adapter->num_tx_queues; i++) {
5421 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5422 restart_queue += tx_ring->tx_stats.restart_queue;
5423 tx_busy += tx_ring->tx_stats.tx_busy;
5424 bytes += tx_ring->stats.bytes;
5425 packets += tx_ring->stats.packets;
5426 }
eb985f09 5427 adapter->restart_queue = restart_queue;
5b7da515
AD		 5428 adapter->tx_busy = tx_busy;
5429 netdev->stats.tx_bytes = bytes;
5430 netdev->stats.tx_packets = packets;
7ca3bc58 5431
7ca647bd 5432 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5433
5434 /* 8 register reads */
6f11eef7
AV		 5435 for (i = 0; i < 8; i++) {
5436 /* for packet buffers not used, the register should read 0 */
5437 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5438 missed_rx += mpc;
7ca647bd
JP		 5439 hwstats->mpc[i] += mpc;
5440 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5441 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5442 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5443 switch (hw->mac.type) {
5444 case ixgbe_mac_82598EB:
1a70db4b
ET		 5445 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5446 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5447 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5448 hwstats->pxonrxc[i] +=
5449 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5450 break;
5451 case ixgbe_mac_82599EB:
b93a2226 5452 case ixgbe_mac_X540:
bd508178
AD		 5453 hwstats->pxonrxc[i] +=
5454 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5455 break;
5456 default:
5457 break;
e8e26350 5458 }
6f11eef7 5459 }
1a70db4b
ET		 5460
5461 /*16 register reads */
5462 for (i = 0; i < 16; i++) {
5463 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5464 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5465 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5466 (hw->mac.type == ixgbe_mac_X540)) {
5467 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5468 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5469 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5470 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5471 }
5472 }
5473
7ca647bd 5474 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5475 /* work around hardware counting issue */
7ca647bd 5476 hwstats->gprc -= missed_rx;
6f11eef7 5477
c84d324c
JF		 5478 ixgbe_update_xoff_received(adapter);
5479
6f11eef7 5480 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5481 switch (hw->mac.type) {
5482 case ixgbe_mac_82598EB:
5483 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5484 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5485 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5486 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5487 break;
b93a2226 5488 case ixgbe_mac_X540:
58f6bcf9
ET		 5489 /* OS2BMC stats are X540 only*/
5490 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5491 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5492 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5493 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5494 case ixgbe_mac_82599EB:
a4d4f629
AD		 5495 for (i = 0; i < 16; i++)
5496 adapter->hw_rx_no_dma_resources +=
5497 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5498 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5499 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5500 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5501 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5502 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5503 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5504 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5505 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5506 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5507#ifdef IXGBE_FCOE
7ca647bd
JP		 5508 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5509 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5510 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5511 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5512 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5513 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5514 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5515 if (adapter->fcoe.ddp_pool) {
5516 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5517 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5518 unsigned int cpu;
5519 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5520 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5521 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5522 noddp += ddp_pool->noddp;
5523 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5524 }
5a1ee270
AD		 5525 hwstats->fcoe_noddp = noddp;
5526 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5527 }
6d45522c 5528#endif /* IXGBE_FCOE */
bd508178
AD		 5529 break;
5530 default:
5531 break;
e8e26350 5532 }
9a799d71 5533 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5534 hwstats->bprc += bprc;
5535 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5536 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5537 hwstats->mprc -= bprc;
5538 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5539 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5540 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5541 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5542 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5543 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5544 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5545 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5546 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5547 hwstats->lxontxc += lxon;
6f11eef7 5548 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5549 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5550 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5551 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5552 /*
5553 * 82598 errata - tx of flow control packets is included in tx counters
5554 */
5555 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5556 hwstats->gptc -= xon_off_tot;
5557 hwstats->mptc -= xon_off_tot;
5558 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5559 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5560 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5561 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5562 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5563 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5564 hwstats->ptc64 -= xon_off_tot;
5565 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5566 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5567 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5568 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5569 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5570 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5571
5572 /* Fill out the OS statistics structure */
7ca647bd 5573 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5574
5575 /* Rx Errors */
7ca647bd 5576 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5577 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5578 netdev->stats.rx_length_errors = hwstats->rlec;
5579 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5580 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5581}
5582
5583/**
d034acf1 5584 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5585 * @adapter: pointer to the device adapter structure
9a799d71 5586 **/
d034acf1 5587static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5588{
cf8280ee 5589 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5590 int i;
cf8280ee 5591
d034acf1
AD		 5592 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5593 return;
5594
5595 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5596
d034acf1 5597 /* if interface is down do nothing */
fe49f04a 5598 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5599 return;
5600
5601 /* do nothing if we are not using signature filters */
5602 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5603 return;
5604
5605 adapter->fdir_overflow++;
5606
93c52dd0
AD		 5607 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5608 for (i = 0; i < adapter->num_tx_queues; i++)
5609 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5610 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5611 /* re-enable flow director interrupts */
5612 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5613 } else {
5614 e_err(probe, "failed to finish FDIR re-initialization, "
5615 "ignored adding FDIR ATR filters\n");
5616 }
93c52dd0
AD		 5617}
5618
5619/**
5620 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5621 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5622 *
5623 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5624 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5625 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5626 * determine if a hang has occurred.
93c52dd0
AD		 5627 */
5628static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 5629{
cf8280ee 5630 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 5631 u64 eics = 0;
5632 int i;
cf8280ee 5633
93c52dd0
AD		 5634 /* If we're down or resetting, just bail */
5635 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5636 test_bit(__IXGBE_RESETTING, &adapter->state))
5637 return;
22d5a71b 5638
93c52dd0
AD		 5639 /* Force detection of hung controller */
5640 if (netif_carrier_ok(adapter->netdev)) {
5641 for (i = 0; i < adapter->num_tx_queues; i++)
5642 set_check_for_tx_hang(adapter->tx_ring[i]);
5643 }
22d5a71b 5644
fe49f04a
AD		 5645 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5646 /*
5647 * for legacy and MSI interrupts don't set any bits
5648 * that are enabled for EIAM, because this operation
5649 * would set *both* EIMS and EICS for any bit in EIAM
5650 */
5651 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5652 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 5653 } else {
5654 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 5655 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 5656 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 5657 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 5658 eics |= ((u64)1 << i);
5659 }
cf8280ee 5660 }
9a799d71 5661
93c52dd0 5662 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 5663 ixgbe_irq_rearm_queues(adapter, eics);
5664
cf8280ee
JB		 5665}
5666
e8e26350 5667/**
93c52dd0 5668 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 5669 * @adapter: pointer to the device adapter structure
5670 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 5671 **/
93c52dd0 5672static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 5673{
e8e26350 5674 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5675 u32 link_speed = adapter->link_speed;
5676 bool link_up = adapter->link_up;
041441d0 5677 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 5678
93c52dd0
AD		 5679 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5680 return;
5681
5682 if (hw->mac.ops.check_link) {
5683 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 5684 } else {
93c52dd0
AD		 5685 /* always assume link is up, if no check link function */
5686 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5687 link_up = true;
c4cf55e5 5688 }
041441d0
AD		 5689
5690 if (adapter->ixgbe_ieee_pfc)
5691 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
5692
3ebe8fde 5693 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 5694 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 5695 ixgbe_set_rx_drop_en(adapter);
5696 }
93c52dd0
AD		 5697
5698 if (link_up ||
5699 time_after(jiffies, (adapter->link_check_timeout +
5700 IXGBE_TRY_LINK_TIMEOUT))) {
5701 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5702 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5703 IXGBE_WRITE_FLUSH(hw);
5704 }
5705
5706 adapter->link_up = link_up;
5707 adapter->link_speed = link_speed;
e8e26350
PW		 5708}
5709
107d3018
AD		 5710static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
5711{
5712#ifdef CONFIG_IXGBE_DCB
5713 struct net_device *netdev = adapter->netdev;
5714 struct dcb_app app = {
5715 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
5716 .protocol = 0,
5717 };
5718 u8 up = 0;
5719
5720 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
5721 up = dcb_ieee_getapp_mask(netdev, &app);
5722
5723 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
5724#endif
5725}
5726
e8e26350 5727/**
93c52dd0
AD		 5728 * ixgbe_watchdog_link_is_up - update netif_carrier status and
5729 * print link up message
49ce9c2c 5730 * @adapter: pointer to the device adapter structure
e8e26350 5731 **/
93c52dd0 5732static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 5733{
93c52dd0 5734 struct net_device *netdev = adapter->netdev;
e8e26350 5735 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 5736 u32 link_speed = adapter->link_speed;
5737 bool flow_rx, flow_tx;
e8e26350 5738
93c52dd0
AD		 5739 /* only continue if link was previously down */
5740 if (netif_carrier_ok(netdev))
a985b6c3 5741 return;
63d6e1d8 5742
93c52dd0 5743 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 5744
93c52dd0
AD		 5745 switch (hw->mac.type) {
5746 case ixgbe_mac_82598EB: {
5747 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5748 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5749 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5750 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5751 }
5752 break;
5753 case ixgbe_mac_X540:
5754 case ixgbe_mac_82599EB: {
5755 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5756 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5757 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5758 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5759 }
5760 break;
5761 default:
5762 flow_tx = false;
5763 flow_rx = false;
5764 break;
e8e26350 5765 }
3a6a4eda 5766
6cb562d6
JK		 5767 adapter->last_rx_ptp_check = jiffies;
5768
1a71ab24
JK		 5769 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5770 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5771
93c52dd0
AD		 5772 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5773 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5774 "10 Gbps" :
5775 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5776 "1 Gbps" :
5777 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
5778 "100 Mbps" :
5779 "unknown speed"))),
5780 ((flow_rx && flow_tx) ? "RX/TX" :
5781 (flow_rx ? "RX" :
5782 (flow_tx ? "TX" : "None"))));
e8e26350 5783
93c52dd0 5784 netif_carrier_on(netdev);
93c52dd0 5785 ixgbe_check_vf_rate_limit(adapter);
befa2af7 5786
107d3018
AD		 5787 /* update the default user priority for VFs */
5788 ixgbe_update_default_up(adapter);
5789
befa2af7
AD		 5790 /* ping all the active vfs to let them know link has changed */
5791 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 5792}
5793
c4cf55e5 5794/**
93c52dd0
AD		 5795 * ixgbe_watchdog_link_is_down - update netif_carrier status and
5796 * print link down message
49ce9c2c 5797 * @adapter: pointer to the adapter structure
c4cf55e5 5798 **/
581330ba 5799static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 5800{
cf8280ee 5801 struct net_device *netdev = adapter->netdev;
c4cf55e5 5802 struct ixgbe_hw *hw = &adapter->hw;
10eec955 5803
93c52dd0
AD		 5804 adapter->link_up = false;
5805 adapter->link_speed = 0;
cf8280ee 5806
93c52dd0
AD		 5807 /* only continue if link was up previously */
5808 if (!netif_carrier_ok(netdev))
5809 return;
264857b8 5810
93c52dd0
AD		 5811 /* poll for SFP+ cable when link is down */
5812 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
5813 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 5814
1a71ab24
JK		 5815 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED)
5816 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 5817
93c52dd0
AD		 5818 e_info(drv, "NIC Link is Down\n");
5819 netif_carrier_off(netdev);
befa2af7
AD		 5820
5821 /* ping all the active vfs to let them know link has changed */
5822 ixgbe_ping_all_vfs(adapter);
93c52dd0 5823}
e8e26350 5824
93c52dd0
AD		 5825/**
5826 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 5827 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5828 **/
5829static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
5830{
c4cf55e5 5831 int i;
93c52dd0 5832 int some_tx_pending = 0;
c4cf55e5 5833
93c52dd0 5834 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 5835 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 5836 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 5837 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5838 some_tx_pending = 1;
5839 break;
5840 }
5841 }
5842
5843 if (some_tx_pending) {
5844 /* We've lost link, so the controller stops DMA,
5845 * but we've got queued Tx work that's never going
5846 * to get done, so reset controller to flush Tx.
5847 * (Do the reset outside of interrupt context).
5848 */
12ff3f3b 5849 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 5850 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 5851 }
c4cf55e5 5852 }
c4cf55e5
PWJ		 5853}
5854
a985b6c3
GR		 5855static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
5856{
5857 u32 ssvpc;
5858
0584d999
GR		 5859 /* Do not perform spoof check for 82598 or if not in IOV mode */
5860 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
5861 adapter->num_vfs == 0)
a985b6c3
GR		 5862 return;
5863
5864 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
5865
5866 /*
5867 * ssvpc register is cleared on read, if zero then no
5868 * spoofed packets in the last interval.
5869 */
5870 if (!ssvpc)
5871 return;
5872
d6ea0754 5873 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 5874}
5875
93c52dd0
AD		 5876/**
5877 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 5878 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5879 **/
5880static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
5881{
5882 /* if interface is down do nothing */
7edebf9a
ET		 5883 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5884 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 5885 return;
5886
5887 ixgbe_watchdog_update_link(adapter);
5888
5889 if (adapter->link_up)
5890 ixgbe_watchdog_link_is_up(adapter);
5891 else
5892 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 5893
a985b6c3 5894 ixgbe_spoof_check(adapter);
9a799d71 5895 ixgbe_update_stats(adapter);
93c52dd0
AD		 5896
5897 ixgbe_watchdog_flush_tx(adapter);
9a799d71 5898}
10eec955 5899
cf8280ee 5900/**
7086400d 5901 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 5902 * @adapter: the ixgbe adapter structure
cf8280ee 5903 **/
7086400d 5904static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 5905{
cf8280ee 5906 struct ixgbe_hw *hw = &adapter->hw;
7086400d 5907 s32 err;
cf8280ee 5908
7086400d
AD		 5909 /* not searching for SFP so there is nothing to do here */
5910 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
5911 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5912 return;
10eec955 5913
7086400d
AD		 5914 /* someone else is in init, wait until next service event */
5915 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5916 return;
cf8280ee 5917
7086400d
AD		 5918 err = hw->phy.ops.identify_sfp(hw);
5919 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5920 goto sfp_out;
264857b8 5921
7086400d
AD		 5922 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
5923 /* If no cable is present, then we need to reset
5924 * the next time we find a good cable. */
5925 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 5926 }
9a799d71 5927
7086400d
AD		 5928 /* exit on error */
5929 if (err)
5930 goto sfp_out;
e8e26350 5931
7086400d
AD		 5932 /* exit if reset not needed */
5933 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
5934 goto sfp_out;
9a799d71 5935
7086400d 5936 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 5937
7086400d
AD		 5938 /*
5939 * A module may be identified correctly, but the EEPROM may not have
5940 * support for that module. setup_sfp() will fail in that case, so
5941 * we should not allow that module to load.
5942 */
5943 if (hw->mac.type == ixgbe_mac_82598EB)
5944 err = hw->phy.ops.reset(hw);
5945 else
5946 err = hw->mac.ops.setup_sfp(hw);
5947
5948 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
5949 goto sfp_out;
5950
5951 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
5952 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
5953
5954sfp_out:
5955 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5956
5957 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
5958 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
5959 e_dev_err("failed to initialize because an unsupported "
5960 "SFP+ module type was detected.\n");
5961 e_dev_err("Reload the driver after installing a "
5962 "supported module.\n");
5963 unregister_netdev(adapter->netdev);
bc59fcda 5964 }
7086400d 5965}
bc59fcda 5966
7086400d
AD		 5967/**
5968 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 5969 * @adapter: the ixgbe adapter structure
7086400d
AD		 5970 **/
5971static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
5972{
5973 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 5974 u32 speed;
5975 bool autoneg = false;
7086400d
AD		 5976
5977 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
5978 return;
5979
5980 /* someone else is in init, wait until next service event */
5981 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
5982 return;
5983
5984 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
5985
3d292265
JH		 5986 speed = hw->phy.autoneg_advertised;
5987 if ((!speed) && (hw->mac.ops.get_link_capabilities))
5988 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
7086400d 5989 if (hw->mac.ops.setup_link)
fd0326f2 5990 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 5991
5992 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5993 adapter->link_check_timeout = jiffies;
5994 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
5995}
5996
83c61fa9
GR		 5997#ifdef CONFIG_PCI_IOV
5998static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
5999{
6000 int vf;
6001 struct ixgbe_hw *hw = &adapter->hw;
6002 struct net_device *netdev = adapter->netdev;
6003 u32 gpc;
6004 u32 ciaa, ciad;
6005
6006 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6007 if (gpc) /* If incrementing then no need for the check below */
6008 return;
6009 /*
6010 * Check to see if a bad DMA write target from an errant or
6011 * malicious VF has caused a PCIe error. If so then we can
6012 * issue a VFLR to the offending VF(s) and then resume without
6013 * requesting a full slot reset.
6014 */
6015
6016 for (vf = 0; vf < adapter->num_vfs; vf++) {
6017 ciaa = (vf << 16) | 0x80000000;
6018 /* 32 bit read so align, we really want status at offset 6 */
6019 ciaa |= PCI_COMMAND;
6020 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6021 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6022 ciaa &= 0x7FFFFFFF;
6023 /* disable debug mode asap after reading data */
6024 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6025 /* Get the upper 16 bits which will be the PCI status reg */
6026 ciad >>= 16;
6027 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6028 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6029 /* Issue VFLR */
6030 ciaa = (vf << 16) | 0x80000000;
6031 ciaa |= 0xA8;
6032 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6033 ciad = 0x00008000; /* VFLR */
6034 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6035 ciaa &= 0x7FFFFFFF;
6036 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6037 }
6038 }
6039}
6040
6041#endif
7086400d
AD		 6042/**
6043 * ixgbe_service_timer - Timer Call-back
6044 * @data: pointer to adapter cast into an unsigned long
6045 **/
6046static void ixgbe_service_timer(unsigned long data)
6047{
6048 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6049 unsigned long next_event_offset;
83c61fa9 6050 bool ready = true;
7086400d 6051
6bb78cfb
AD		 6052 /* poll faster when waiting for link */
6053 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6054 next_event_offset = HZ / 10;
6055 else
6056 next_event_offset = HZ * 2;
83c61fa9 6057
6bb78cfb 6058#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6059 /*
6060 * don't bother with SR-IOV VF DMA hang check if there are
6061 * no VFs or the link is down
6062 */
6063 if (!adapter->num_vfs ||
6bb78cfb 6064 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6065 goto normal_timer_service;
83c61fa9
GR		 6066
6067 /* If we have VFs allocated then we must check for DMA hangs */
6068 ixgbe_check_for_bad_vf(adapter);
6069 next_event_offset = HZ / 50;
6070 adapter->timer_event_accumulator++;
6071
6bb78cfb 6072 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6073 adapter->timer_event_accumulator = 0;
7086400d 6074 else
6bb78cfb 6075 ready = false;
7086400d 6076
6bb78cfb 6077normal_timer_service:
83c61fa9 6078#endif
7086400d
AD		 6079 /* Reset the timer */
6080 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6081
83c61fa9
GR		 6082 if (ready)
6083 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6084}
6085
c83c6cbd
AD		 6086static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6087{
6088 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6089 return;
6090
6091 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6092
6093 /* If we're already down or resetting, just bail */
6094 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6095 test_bit(__IXGBE_RESETTING, &adapter->state))
6096 return;
6097
6098 ixgbe_dump(adapter);
6099 netdev_err(adapter->netdev, "Reset adapter\n");
6100 adapter->tx_timeout_count++;
6101
6102 ixgbe_reinit_locked(adapter);
6103}
6104
7086400d
AD		 6105/**
6106 * ixgbe_service_task - manages and runs subtasks
6107 * @work: pointer to work_struct containing our data
6108 **/
6109static void ixgbe_service_task(struct work_struct *work)
6110{
6111 struct ixgbe_adapter *adapter = container_of(work,
6112 struct ixgbe_adapter,
6113 service_task);
c83c6cbd 6114 ixgbe_reset_subtask(adapter);
7086400d
AD		 6115 ixgbe_sfp_detection_subtask(adapter);
6116 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6117 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6118 ixgbe_watchdog_subtask(adapter);
d034acf1 6119 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6120 ixgbe_check_hang_subtask(adapter);
891dc082
JK		 6121
6122 if (adapter->flags2 & IXGBE_FLAG2_PTP_ENABLED) {
6123 ixgbe_ptp_overflow_check(adapter);
6124 ixgbe_ptp_rx_hang(adapter);
6125 }
7086400d
AD		 6126
6127 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6128}
6129
fd0db0ed
AD		 6130static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6131 struct ixgbe_tx_buffer *first,
244e27ad 6132 u8 *hdr_len)
897ab156 6133{
fd0db0ed 6134 struct sk_buff *skb = first->skb;
897ab156
AD		 6135 u32 vlan_macip_lens, type_tucmd;
6136 u32 mss_l4len_idx, l4len;
9a799d71 6137
8f4fbb9b
AD		 6138 if (skb->ip_summed != CHECKSUM_PARTIAL)
6139 return 0;
6140
897ab156
AD		 6141 if (!skb_is_gso(skb))
6142 return 0;
9a799d71 6143
897ab156 6144 if (skb_header_cloned(skb)) {
244e27ad 6145 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
897ab156
AD		 6146 if (err)
6147 return err;
9a799d71 6148 }
9a799d71 6149
897ab156
AD		 6150 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6151 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6152
244e27ad 6153 if (first->protocol == __constant_htons(ETH_P_IP)) {
897ab156
AD		 6154 struct iphdr *iph = ip_hdr(skb);
6155 iph->tot_len = 0;
6156 iph->check = 0;
6157 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6158 iph->daddr, 0,
6159 IPPROTO_TCP,
6160 0);
6161 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6162 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6163 IXGBE_TX_FLAGS_CSUM |
6164 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6165 } else if (skb_is_gso_v6(skb)) {
6166 ipv6_hdr(skb)->payload_len = 0;
6167 tcp_hdr(skb)->check =
6168 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6169 &ipv6_hdr(skb)->daddr,
6170 0, IPPROTO_TCP, 0);
244e27ad
AD		 6171 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6172 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6173 }
6174
091a6246 6175 /* compute header lengths */
897ab156
AD		 6176 l4len = tcp_hdrlen(skb);
6177 *hdr_len = skb_transport_offset(skb) + l4len;
6178
091a6246
AD		 6179 /* update gso size and bytecount with header size */
6180 first->gso_segs = skb_shinfo(skb)->gso_segs;
6181 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6182
c44f5f51 6183 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6184 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6185 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6186
6187 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6188 vlan_macip_lens = skb_network_header_len(skb);
6189 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6190 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6191
6192 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6193 mss_l4len_idx);
897ab156
AD		 6194
6195 return 1;
6196}
6197
244e27ad
AD		 6198static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6199 struct ixgbe_tx_buffer *first)
7ca647bd 6200{
fd0db0ed 6201 struct sk_buff *skb = first->skb;
897ab156
AD		 6202 u32 vlan_macip_lens = 0;
6203 u32 mss_l4len_idx = 0;
6204 u32 type_tucmd = 0;
7ca647bd 6205
897ab156 6206 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6207 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6208 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6209 return;
897ab156
AD		 6210 } else {
6211 u8 l4_hdr = 0;
244e27ad 6212 switch (first->protocol) {
897ab156
AD		 6213 case __constant_htons(ETH_P_IP):
6214 vlan_macip_lens |= skb_network_header_len(skb);
6215 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6216 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6217 break;
897ab156
AD		 6218 case __constant_htons(ETH_P_IPV6):
6219 vlan_macip_lens |= skb_network_header_len(skb);
6220 l4_hdr = ipv6_hdr(skb)->nexthdr;
6221 break;
6222 default:
6223 if (unlikely(net_ratelimit())) {
6224 dev_warn(tx_ring->dev,
6225 "partial checksum but proto=%x!\n",
244e27ad 6226 first->protocol);
897ab156 6227 }
7ca647bd
JP		 6228 break;
6229 }
897ab156
AD		 6230
6231 switch (l4_hdr) {
7ca647bd 6232 case IPPROTO_TCP:
897ab156
AD		 6233 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6234 mss_l4len_idx = tcp_hdrlen(skb) <<
6235 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6236 break;
6237 case IPPROTO_SCTP:
897ab156
AD		 6238 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6239 mss_l4len_idx = sizeof(struct sctphdr) <<
6240 IXGBE_ADVTXD_L4LEN_SHIFT;
6241 break;
6242 case IPPROTO_UDP:
6243 mss_l4len_idx = sizeof(struct udphdr) <<
6244 IXGBE_ADVTXD_L4LEN_SHIFT;
6245 break;
6246 default:
6247 if (unlikely(net_ratelimit())) {
6248 dev_warn(tx_ring->dev,
6249 "partial checksum but l4 proto=%x!\n",
244e27ad 6250 l4_hdr);
897ab156 6251 }
7ca647bd
JP		 6252 break;
6253 }
244e27ad
AD		 6254
6255 /* update TX checksum flag */
6256 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6257 }
6258
244e27ad 6259 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6260 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6261 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6262
897ab156
AD		 6263 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6264 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6265}
6266
472148c3
AD		 6267#define IXGBE_SET_FLAG(_input, _flag, _result) \
6268 ((_flag <= _result) ? \
6269 ((u32)(_input & _flag) * (_result / _flag)) : \
6270 ((u32)(_input & _flag) / (_flag / _result)))
6271
6272static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6273{
d3d00239 6274 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6275 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6276 IXGBE_ADVTXD_DCMD_DEXT |
6277 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6278
d3d00239 6279 /* set HW vlan bit if vlan is present */
472148c3
AD		 6280 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6281 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6282
d3d00239 6283 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6284 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6285 IXGBE_ADVTXD_DCMD_TSE);
6286
6287 /* set timestamp bit if present */
6288 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6289 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6290
62748b7b 6291 /* insert frame checksum */
472148c3 6292 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6293
d3d00239
AD		 6294 return cmd_type;
6295}
9a799d71 6296
729739b7
AD		 6297static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6298 u32 tx_flags, unsigned int paylen)
d3d00239 6299{
472148c3 6300 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6301
d3d00239 6302 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6303 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6304 IXGBE_TX_FLAGS_CSUM,
6305 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6306
93f5b3c1 6307 /* enble IPv4 checksum for TSO */
472148c3
AD		 6308 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6309 IXGBE_TX_FLAGS_IPV4,
6310 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6311
7f9643fd
AD		 6312 /*
6313 * Check Context must be set if Tx switch is enabled, which it
6314 * always is for case where virtual functions are running
6315 */
472148c3
AD		 6316 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6317 IXGBE_TX_FLAGS_CC,
6318 IXGBE_ADVTXD_CC);
7f9643fd 6319
472148c3 6320 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6321}
44df32c5 6322
d3d00239
AD		 6323#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6324 IXGBE_TXD_CMD_RS)
6325
6326static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6327 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6328 const u8 hdr_len)
6329{
fd0db0ed 6330 struct sk_buff *skb = first->skb;
729739b7 6331 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6332 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6333 struct skb_frag_struct *frag;
6334 dma_addr_t dma;
6335 unsigned int data_len, size;
244e27ad 6336 u32 tx_flags = first->tx_flags;
472148c3 6337 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6338 u16 i = tx_ring->next_to_use;
d3d00239 6339
729739b7
AD		 6340 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6341
ec718254
AD		 6342 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6343
6344 size = skb_headlen(skb);
6345 data_len = skb->data_len;
729739b7 6346
d3d00239
AD		 6347#ifdef IXGBE_FCOE
6348 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6349 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6350 size -= sizeof(struct fcoe_crc_eof) - data_len;
6351 data_len = 0;
729739b7
AD		 6352 } else {
6353 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6354 }
6355 }
44df32c5 6356
d3d00239 6357#endif
729739b7 6358 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6359
ec718254 6360 tx_buffer = first;
9a799d71 6361
ec718254
AD		 6362 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6363 if (dma_mapping_error(tx_ring->dev, dma))
6364 goto dma_error;
6365
6366 /* record length, and DMA address */
6367 dma_unmap_len_set(tx_buffer, len, size);
6368 dma_unmap_addr_set(tx_buffer, dma, dma);
6369
6370 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6371
729739b7 6372 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6373 tx_desc->read.cmd_type_len =
472148c3 6374 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6375
d3d00239 6376 i++;
729739b7 6377 tx_desc++;
d3d00239 6378 if (i == tx_ring->count) {
e4f74028 6379 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6380 i = 0;
6381 }
ec718254 6382 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6383
6384 dma += IXGBE_MAX_DATA_PER_TXD;
6385 size -= IXGBE_MAX_DATA_PER_TXD;
6386
6387 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6388 }
e5a43549 6389
729739b7
AD		 6390 if (likely(!data_len))
6391 break;
9a799d71 6392
472148c3 6393 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6394
729739b7
AD		 6395 i++;
6396 tx_desc++;
6397 if (i == tx_ring->count) {
6398 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6399 i = 0;
6400 }
ec718254 6401 tx_desc->read.olinfo_status = 0;
9a799d71 6402
d3d00239 6403#ifdef IXGBE_FCOE
9e903e08 6404 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6405#else
9e903e08 6406 size = skb_frag_size(frag);
d3d00239
AD		 6407#endif
6408 data_len -= size;
9a799d71 6409
729739b7
AD		 6410 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6411 DMA_TO_DEVICE);
9a799d71 6412
729739b7 6413 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6414 }
9a799d71 6415
729739b7 6416 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6417 cmd_type |= size | IXGBE_TXD_CMD;
6418 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6419
091a6246 6420 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6421
d3d00239
AD		 6422 /* set the timestamp */
6423 first->time_stamp = jiffies;
9a799d71
AK		 6424
6425 /*
729739b7
AD		 6426 * Force memory writes to complete before letting h/w know there
6427 * are new descriptors to fetch. (Only applicable for weak-ordered
6428 * memory model archs, such as IA-64).
6429 *
6430 * We also need this memory barrier to make certain all of the
6431 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6432 */
6433 wmb();
6434
d3d00239
AD		 6435 /* set next_to_watch value indicating a packet is present */
6436 first->next_to_watch = tx_desc;
6437
729739b7
AD		 6438 i++;
6439 if (i == tx_ring->count)
6440 i = 0;
6441
6442 tx_ring->next_to_use = i;
6443
d3d00239 6444 /* notify HW of packet */
84ea2591 6445 writel(i, tx_ring->tail);
d3d00239
AD		 6446
6447 return;
6448dma_error:
729739b7 6449 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6450
6451 /* clear dma mappings for failed tx_buffer_info map */
6452 for (;;) {
729739b7
AD		 6453 tx_buffer = &tx_ring->tx_buffer_info[i];
6454 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6455 if (tx_buffer == first)
d3d00239
AD		 6456 break;
6457 if (i == 0)
6458 i = tx_ring->count;
6459 i--;
6460 }
6461
d3d00239 6462 tx_ring->next_to_use = i;
9a799d71
AK		 6463}
6464
fd0db0ed 6465static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6466 struct ixgbe_tx_buffer *first)
69830529
AD		 6467{
6468 struct ixgbe_q_vector *q_vector = ring->q_vector;
6469 union ixgbe_atr_hash_dword input = { .dword = 0 };
6470 union ixgbe_atr_hash_dword common = { .dword = 0 };
6471 union {
6472 unsigned char *network;
6473 struct iphdr *ipv4;
6474 struct ipv6hdr *ipv6;
6475 } hdr;
ee9e0f0b 6476 struct tcphdr *th;
905e4a41 6477 __be16 vlan_id;
c4cf55e5 6478
69830529
AD		 6479 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6480 if (!q_vector)
6481 return;
6482
6483 /* do nothing if sampling is disabled */
6484 if (!ring->atr_sample_rate)
d3ead241 6485 return;
c4cf55e5 6486
69830529 6487 ring->atr_count++;
c4cf55e5 6488
69830529 6489 /* snag network header to get L4 type and address */
fd0db0ed 6490 hdr.network = skb_network_header(first->skb);
69830529
AD		 6491
6492 /* Currently only IPv4/IPv6 with TCP is supported */
244e27ad 6493 if ((first->protocol != __constant_htons(ETH_P_IPV6) ||
69830529 6494 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
244e27ad 6495 (first->protocol != __constant_htons(ETH_P_IP) ||
69830529
AD		 6496 hdr.ipv4->protocol != IPPROTO_TCP))
6497 return;
ee9e0f0b 6498
fd0db0ed 6499 th = tcp_hdr(first->skb);
c4cf55e5 6500
66f32a8b
AD		 6501 /* skip this packet since it is invalid or the socket is closing */
6502 if (!th || th->fin)
69830529
AD		 6503 return;
6504
6505 /* sample on all syn packets or once every atr sample count */
6506 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6507 return;
6508
6509 /* reset sample count */
6510 ring->atr_count = 0;
6511
244e27ad 6512 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6513
6514 /*
6515 * src and dst are inverted, think how the receiver sees them
6516 *
6517 * The input is broken into two sections, a non-compressed section
6518 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6519 * is XORed together and stored in the compressed dword.
6520 */
6521 input.formatted.vlan_id = vlan_id;
6522
6523 /*
6524 * since src port and flex bytes occupy the same word XOR them together
6525 * and write the value to source port portion of compressed dword
6526 */
244e27ad 6527 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
69830529
AD		 6528 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6529 else
244e27ad 6530 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6531 common.port.dst ^= th->source;
6532
244e27ad 6533 if (first->protocol == __constant_htons(ETH_P_IP)) {
69830529
AD		 6534 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6535 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6536 } else {
6537 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6538 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6539 hdr.ipv6->saddr.s6_addr32[1] ^
6540 hdr.ipv6->saddr.s6_addr32[2] ^
6541 hdr.ipv6->saddr.s6_addr32[3] ^
6542 hdr.ipv6->daddr.s6_addr32[0] ^
6543 hdr.ipv6->daddr.s6_addr32[1] ^
6544 hdr.ipv6->daddr.s6_addr32[2] ^
6545 hdr.ipv6->daddr.s6_addr32[3];
6546 }
c4cf55e5
PWJ		 6547
6548 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6549 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6550 input, common, ring->queue_index);
c4cf55e5
PWJ		 6551}
6552
63544e9c 6553static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6554{
fc77dc3c 6555 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6556 /* Herbert's original patch had:
6557 * smp_mb__after_netif_stop_queue();
6558 * but since that doesn't exist yet, just open code it. */
6559 smp_mb();
6560
6561 /* We need to check again in a case another CPU has just
6562 * made room available. */
7d4987de 6563 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6564 return -EBUSY;
6565
6566 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6567 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6568 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6569 return 0;
6570}
6571
82d4e46e 6572static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6573{
7d4987de 6574 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6575 return 0;
fc77dc3c 6576 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6577}
6578
97488bd1 6579#ifdef IXGBE_FCOE
09a3b1f8
SH		 6580static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6581{
97488bd1
AD		 6582 struct ixgbe_adapter *adapter;
6583 struct ixgbe_ring_feature *f;
6584 int txq;
5e09a105 6585
97488bd1
AD		 6586 /*
6587 * only execute the code below if protocol is FCoE
6588 * or FIP and we have FCoE enabled on the adapter
6589 */
6590 switch (vlan_get_protocol(skb)) {
6591 case __constant_htons(ETH_P_FCOE):
6592 case __constant_htons(ETH_P_FIP):
6593 adapter = netdev_priv(dev);
c087663e 6594
97488bd1
AD		 6595 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
6596 break;
6597 default:
6598 return __netdev_pick_tx(dev, skb);
6599 }
c087663e 6600
97488bd1 6601 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 6602
97488bd1
AD		 6603 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6604 smp_processor_id();
56075a98 6605
97488bd1
AD		 6606 while (txq >= f->indices)
6607 txq -= f->indices;
c4cf55e5 6608
97488bd1 6609 return txq + f->offset;
09a3b1f8
SH		 6610}
6611
97488bd1 6612#endif
fc77dc3c 6613netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 6614 struct ixgbe_adapter *adapter,
6615 struct ixgbe_ring *tx_ring)
9a799d71 6616{
d3d00239 6617 struct ixgbe_tx_buffer *first;
5f715823 6618 int tso;
d3d00239 6619 u32 tx_flags = 0;
a535c30e 6620 unsigned short f;
a535c30e 6621 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 6622 __be16 protocol = skb->protocol;
63544e9c 6623 u8 hdr_len = 0;
5e09a105 6624
a535c30e
AD		 6625 /*
6626 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 6627 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 6628 * + 2 desc gap to keep tail from touching head,
6629 * + 1 desc for context descriptor,
6630 * otherwise try next time
6631 */
a535c30e
AD		 6632 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6633 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 6634
a535c30e
AD		 6635 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6636 tx_ring->tx_stats.tx_busy++;
6637 return NETDEV_TX_BUSY;
6638 }
6639
fd0db0ed
AD		 6640 /* record the location of the first descriptor for this packet */
6641 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
6642 first->skb = skb;
091a6246
AD		 6643 first->bytecount = skb->len;
6644 first->gso_segs = 1;
fd0db0ed 6645
66f32a8b 6646 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 6647 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 6648 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
6649 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
6650 /* else if it is a SW VLAN check the next protocol and store the tag */
6651 } else if (protocol == __constant_htons(ETH_P_8021Q)) {
6652 struct vlan_hdr *vhdr, _vhdr;
6653 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
6654 if (!vhdr)
6655 goto out_drop;
6656
6657 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 6658 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
6659 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 6660 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
6661 }
6662
aa7bd467
JK		 6663 skb_tx_timestamp(skb);
6664
3a6a4eda
JK		 6665 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
6666 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
6667 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 6668
6669 /* schedule check for Tx timestamp */
6670 adapter->ptp_tx_skb = skb_get(skb);
6671 adapter->ptp_tx_start = jiffies;
6672 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 6673 }
3a6a4eda 6674
9e0c5648
AD		 6675#ifdef CONFIG_PCI_IOV
6676 /*
6677 * Use the l2switch_enable flag - would be false if the DMA
6678 * Tx switch had been disabled.
6679 */
6680 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 6681 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 6682
6683#endif
32701dc2 6684 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 6685 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 6686 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
6687 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 6688 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 6689 tx_flags |= (skb->priority & 0x7) <<
6690 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 6691 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
6692 struct vlan_ethhdr *vhdr;
6693 if (skb_header_cloned(skb) &&
6694 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))
6695 goto out_drop;
6696 vhdr = (struct vlan_ethhdr *)skb->data;
6697 vhdr->h_vlan_TCI = htons(tx_flags >>
6698 IXGBE_TX_FLAGS_VLAN_SHIFT);
6699 } else {
6700 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 6701 }
9a799d71 6702 }
eacd73f7 6703
244e27ad
AD		 6704 /* record initial flags and protocol */
6705 first->tx_flags = tx_flags;
6706 first->protocol = protocol;
6707
eacd73f7 6708#ifdef IXGBE_FCOE
66f32a8b
AD		 6709 /* setup tx offload for FCoE */
6710 if ((protocol == __constant_htons(ETH_P_FCOE)) &&
a58915c7 6711 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 6712 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 6713 if (tso < 0)
6714 goto out_drop;
9a799d71 6715
66f32a8b 6716 goto xmit_fcoe;
eacd73f7 6717 }
9a799d71 6718
66f32a8b 6719#endif /* IXGBE_FCOE */
244e27ad 6720 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 6721 if (tso < 0)
897ab156 6722 goto out_drop;
244e27ad
AD		 6723 else if (!tso)
6724 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 6725
6726 /* add the ATR filter if ATR is on */
6727 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 6728 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 6729
6730#ifdef IXGBE_FCOE
6731xmit_fcoe:
6732#endif /* IXGBE_FCOE */
244e27ad 6733 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 6734
6735 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 6736
6737 return NETDEV_TX_OK;
897ab156
AD		 6738
6739out_drop:
fd0db0ed
AD		 6740 dev_kfree_skb_any(first->skb);
6741 first->skb = NULL;
6742
897ab156 6743 return NETDEV_TX_OK;
9a799d71
AK		 6744}
6745
a50c29dd
AD		 6746static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
6747 struct net_device *netdev)
84418e3b
AD		 6748{
6749 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6750 struct ixgbe_ring *tx_ring;
6751
a50c29dd
AD		 6752 /*
6753 * The minimum packet size for olinfo paylen is 17 so pad the skb
6754 * in order to meet this minimum size requirement.
6755 */
f73332fc
SH		 6756 if (unlikely(skb->len < 17)) {
6757 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 6758 return NETDEV_TX_OK;
6759 skb->len = 17;
71a49f77 6760 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 6761 }
6762
84418e3b 6763 tx_ring = adapter->tx_ring[skb->queue_mapping];
fc77dc3c 6764 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 6765}
6766
9a799d71
AK		 6767/**
6768 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6769 * @netdev: network interface device structure
6770 * @p: pointer to an address structure
6771 *
6772 * Returns 0 on success, negative on failure
6773 **/
6774static int ixgbe_set_mac(struct net_device *netdev, void *p)
6775{
6776 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 6777 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 6778 struct sockaddr *addr = p;
6779
6780 if (!is_valid_ether_addr(addr->sa_data))
6781 return -EADDRNOTAVAIL;
6782
6783 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 6784 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 6785
1d9c0bfd 6786 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 6787
6788 return 0;
6789}
6790
6b73e10d
BH		 6791static int
6792ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6793{
6794 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6795 struct ixgbe_hw *hw = &adapter->hw;
6796 u16 value;
6797 int rc;
6798
6799 if (prtad != hw->phy.mdio.prtad)
6800 return -EINVAL;
6801 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6802 if (!rc)
6803 rc = value;
6804 return rc;
6805}
6806
6807static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6808 u16 addr, u16 value)
6809{
6810 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6811 struct ixgbe_hw *hw = &adapter->hw;
6812
6813 if (prtad != hw->phy.mdio.prtad)
6814 return -EINVAL;
6815 return hw->phy.ops.write_reg(hw, addr, devad, value);
6816}
6817
6818static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6819{
6820 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6821
3a6a4eda 6822 switch (cmd) {
3a6a4eda
JK		 6823 case SIOCSHWTSTAMP:
6824 return ixgbe_ptp_hwtstamp_ioctl(adapter, req, cmd);
3a6a4eda
JK		 6825 default:
6826 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6827 }
6b73e10d
BH		 6828}
6829
0365e6e4
PW		 6830/**
6831 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 6832 * netdev->dev_addrs
0365e6e4
PW		 6833 * @netdev: network interface device structure
6834 *
6835 * Returns non-zero on failure
6836 **/
6837static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6838{
6839 int err = 0;
6840 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 6841 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 6842
7fa7c9dc 6843 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 6844 rtnl_lock();
7fa7c9dc 6845 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 6846 rtnl_unlock();
7fa7c9dc
AD		 6847
6848 /* update SAN MAC vmdq pool selection */
6849 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 6850 }
6851 return err;
6852}
6853
6854/**
6855 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 6856 * netdev->dev_addrs
0365e6e4
PW		 6857 * @netdev: network interface device structure
6858 *
6859 * Returns non-zero on failure
6860 **/
6861static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6862{
6863 int err = 0;
6864 struct ixgbe_adapter *adapter = netdev_priv(dev);
6865 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6866
6867 if (is_valid_ether_addr(mac->san_addr)) {
6868 rtnl_lock();
6869 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6870 rtnl_unlock();
6871 }
6872 return err;
6873}
6874
9a799d71
AK		 6875#ifdef CONFIG_NET_POLL_CONTROLLER
6876/*
6877 * Polling 'interrupt' - used by things like netconsole to send skbs
6878 * without having to re-enable interrupts. It's not called while
6879 * the interrupt routine is executing.
6880 */
6881static void ixgbe_netpoll(struct net_device *netdev)
6882{
6883 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 6884 int i;
9a799d71 6885
1a647bd2
AD		 6886 /* if interface is down do nothing */
6887 if (test_bit(__IXGBE_DOWN, &adapter->state))
6888 return;
6889
9a799d71 6890 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 6891 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 6892 for (i = 0; i < adapter->num_q_vectors; i++)
6893 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 6894 } else {
6895 ixgbe_intr(adapter->pdev->irq, netdev);
6896 }
9a799d71 6897 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 6898}
9a799d71 6899
581330ba 6900#endif
de1036b1
ED		 6901static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6902 struct rtnl_link_stats64 *stats)
6903{
6904 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6905 int i;
6906
1a51502b 6907 rcu_read_lock();
de1036b1 6908 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 6909 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 6910 u64 bytes, packets;
6911 unsigned int start;
6912
1a51502b
ED		 6913 if (ring) {
6914 do {
6915 start = u64_stats_fetch_begin_bh(&ring->syncp);
6916 packets = ring->stats.packets;
6917 bytes = ring->stats.bytes;
6918 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6919 stats->rx_packets += packets;
6920 stats->rx_bytes += bytes;
6921 }
de1036b1 6922 }
1ac9ad13
ED		 6923
6924 for (i = 0; i < adapter->num_tx_queues; i++) {
6925 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
6926 u64 bytes, packets;
6927 unsigned int start;
6928
6929 if (ring) {
6930 do {
6931 start = u64_stats_fetch_begin_bh(&ring->syncp);
6932 packets = ring->stats.packets;
6933 bytes = ring->stats.bytes;
6934 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6935 stats->tx_packets += packets;
6936 stats->tx_bytes += bytes;
6937 }
6938 }
1a51502b 6939 rcu_read_unlock();
de1036b1
ED		 6940 /* following stats updated by ixgbe_watchdog_task() */
6941 stats->multicast = netdev->stats.multicast;
6942 stats->rx_errors = netdev->stats.rx_errors;
6943 stats->rx_length_errors = netdev->stats.rx_length_errors;
6944 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6945 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6946 return stats;
6947}
6948
8af3c33f 6949#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 6950/**
6951 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
6952 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 6953 * @tc: number of traffic classes currently enabled
6954 *
6955 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
6956 * 802.1Q priority maps to a packet buffer that exists.
6957 */
6958static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
6959{
6960 struct ixgbe_hw *hw = &adapter->hw;
6961 u32 reg, rsave;
6962 int i;
6963
6964 /* 82598 have a static priority to TC mapping that can not
6965 * be changed so no validation is needed.
6966 */
6967 if (hw->mac.type == ixgbe_mac_82598EB)
6968 return;
6969
6970 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
6971 rsave = reg;
6972
6973 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
6974 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
6975
6976 /* If up2tc is out of bounds default to zero */
6977 if (up2tc > tc)
6978 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
6979 }
6980
6981 if (reg != rsave)
6982 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
6983
6984 return;
6985}
6986
02debdc9
AD		 6987/**
6988 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
6989 * @adapter: Pointer to adapter struct
6990 *
6991 * Populate the netdev user priority to tc map
6992 */
6993static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
6994{
6995 struct net_device *dev = adapter->netdev;
6996 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
6997 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
6998 u8 prio;
6999
7000 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7001 u8 tc = 0;
7002
7003 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7004 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7005 else if (ets)
7006 tc = ets->prio_tc[prio];
7007
7008 netdev_set_prio_tc_map(dev, prio, tc);
7009 }
7010}
7011
cca73c59 7012#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7013/**
7014 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7015 *
7016 * @netdev: net device to configure
7017 * @tc: number of traffic classes to enable
7018 */
7019int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7020{
8b1c0b24
JF		 7021 struct ixgbe_adapter *adapter = netdev_priv(dev);
7022 struct ixgbe_hw *hw = &adapter->hw;
8b1c0b24 7023
8b1c0b24 7024 /* Hardware supports up to 8 traffic classes */
4de2a022 7025 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7026 (hw->mac.type == ixgbe_mac_82598EB &&
7027 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7028 return -EINVAL;
7029
7030 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7031 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7032 * hardware is not flexible enough to do this dynamically.
7033 */
7034 if (netif_running(dev))
7035 ixgbe_close(dev);
7036 ixgbe_clear_interrupt_scheme(adapter);
7037
cca73c59 7038#ifdef CONFIG_IXGBE_DCB
e7589eab 7039 if (tc) {
8b1c0b24 7040 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7041 ixgbe_set_prio_tc_map(adapter);
7042
e7589eab 7043 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7044
943561d3
AD		 7045 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7046 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7047 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7048 }
e7589eab 7049 } else {
8b1c0b24 7050 netdev_reset_tc(dev);
02debdc9 7051
943561d3
AD		 7052 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7053 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7054
7055 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7056
7057 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7058 adapter->dcb_cfg.pfc_mode_enable = false;
7059 }
7060
8b1c0b24 7061 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7062
7063#endif /* CONFIG_IXGBE_DCB */
7064 ixgbe_init_interrupt_scheme(adapter);
7065
8b1c0b24 7066 if (netif_running(dev))
cca73c59 7067 return ixgbe_open(dev);
8b1c0b24
JF		 7068
7069 return 0;
7070}
de1036b1 7071
da36b647
GR		 7072#ifdef CONFIG_PCI_IOV
7073void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7074{
7075 struct net_device *netdev = adapter->netdev;
7076
7077 rtnl_lock();
da36b647 7078 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7079 rtnl_unlock();
7080}
7081
7082#endif
082757af
DS		 7083void ixgbe_do_reset(struct net_device *netdev)
7084{
7085 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7086
7087 if (netif_running(netdev))
7088 ixgbe_reinit_locked(adapter);
7089 else
7090 ixgbe_reset(adapter);
7091}
7092
c8f44aff 7093static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7094 netdev_features_t features)
082757af
DS		 7095{
7096 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7097
082757af 7098 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7099 if (!(features & NETIF_F_RXCSUM))
7100 features &= ~NETIF_F_LRO;
082757af 7101
567d2de2
AD		 7102 /* Turn off LRO if not RSC capable */
7103 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7104 features &= ~NETIF_F_LRO;
8e2813f5 7105
567d2de2 7106 return features;
082757af
DS		 7107}
7108
c8f44aff 7109static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7110 netdev_features_t features)
082757af
DS		 7111{
7112 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7113 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7114 bool need_reset = false;
7115
082757af 7116 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7117 if (!(features & NETIF_F_LRO)) {
7118 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7119 need_reset = true;
567d2de2
AD		 7120 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7121 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7122 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7123 if (adapter->rx_itr_setting == 1 ||
7124 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7125 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7126 need_reset = true;
7127 } else if ((changed ^ features) & NETIF_F_LRO) {
7128 e_info(probe, "rx-usecs set too low, "
7129 "disabling RSC\n");
082757af
DS		 7130 }
7131 }
7132
7133 /*
7134 * Check if Flow Director n-tuple support was enabled or disabled. If
7135 * the state changed, we need to reset.
7136 */
39cb681b
AD		 7137 switch (features & NETIF_F_NTUPLE) {
7138 case NETIF_F_NTUPLE:
567d2de2 7139 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7140 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7141 need_reset = true;
7142
567d2de2
AD		 7143 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7144 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7145 break;
7146 default:
7147 /* turn off perfect filters, enable ATR and reset */
7148 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7149 need_reset = true;
7150
7151 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7152
7153 /* We cannot enable ATR if SR-IOV is enabled */
7154 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7155 break;
7156
7157 /* We cannot enable ATR if we have 2 or more traffic classes */
7158 if (netdev_get_num_tc(netdev) > 1)
7159 break;
7160
7161 /* We cannot enable ATR if RSS is disabled */
7162 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7163 break;
7164
7165 /* A sample rate of 0 indicates ATR disabled */
7166 if (!adapter->atr_sample_rate)
7167 break;
7168
7169 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7170 break;
082757af
DS		 7171 }
7172
f646968f 7173 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7174 ixgbe_vlan_strip_enable(adapter);
7175 else
7176 ixgbe_vlan_strip_disable(adapter);
7177
3f2d1c0f
BG		 7178 if (changed & NETIF_F_RXALL)
7179 need_reset = true;
7180
567d2de2 7181 netdev->features = features;
082757af
DS		 7182 if (need_reset)
7183 ixgbe_do_reset(netdev);
7184
7185 return 0;
082757af
DS		 7186}
7187
edc7d573 7188static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7189 struct net_device *dev,
6b6e2725 7190 const unsigned char *addr,
0f4b0add
JF		 7191 u16 flags)
7192{
7193 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7194 int err;
7195
7196 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7197 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7198
b1ac1ef7
JF		 7199 /* Hardware does not support aging addresses so if a
7200 * ndm_state is given only allow permanent addresses
7201 */
7202 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7203 pr_info("%s: FDB only supports static addresses\n",
7204 ixgbe_driver_name);
7205 return -EINVAL;
7206 }
7207
46acc460 7208 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7209 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7210
7211 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7212 err = dev_uc_add_excl(dev, addr);
0f4b0add 7213 else
95447461
JF		 7214 err = -ENOMEM;
7215 } else if (is_multicast_ether_addr(addr)) {
7216 err = dev_mc_add_excl(dev, addr);
7217 } else {
7218 err = -EINVAL;
0f4b0add
JF		 7219 }
7220
7221 /* Only return duplicate errors if NLM_F_EXCL is set */
7222 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7223 err = 0;
7224
7225 return err;
7226}
7227
815cccbf
JF		 7228static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7229 struct nlmsghdr *nlh)
7230{
7231 struct ixgbe_adapter *adapter = netdev_priv(dev);
7232 struct nlattr *attr, *br_spec;
7233 int rem;
7234
7235 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7236 return -EOPNOTSUPP;
7237
7238 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7239
7240 nla_for_each_nested(attr, br_spec, rem) {
7241 __u16 mode;
7242 u32 reg = 0;
7243
7244 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7245 continue;
7246
7247 mode = nla_get_u16(attr);
9b735984 7248 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7249 reg = 0;
9b735984
GR		 7250 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7251 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7252 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7253 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7254 } else
815cccbf
JF		 7255 return -EINVAL;
7256
7257 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7258
7259 e_info(drv, "enabling bridge mode: %s\n",
7260 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7261 }
7262
7263 return 0;
7264}
7265
7266static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7267 struct net_device *dev,
7268 u32 filter_mask)
815cccbf
JF		 7269{
7270 struct ixgbe_adapter *adapter = netdev_priv(dev);
7271 u16 mode;
7272
7273 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7274 return 0;
7275
9b735984 7276 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7277 mode = BRIDGE_MODE_VEB;
7278 else
7279 mode = BRIDGE_MODE_VEPA;
7280
7281 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7282}
7283
0edc3527 7284static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7285 .ndo_open = ixgbe_open,
0edc3527 7286 .ndo_stop = ixgbe_close,
00829823 7287 .ndo_start_xmit = ixgbe_xmit_frame,
97488bd1 7288#ifdef IXGBE_FCOE
09a3b1f8 7289 .ndo_select_queue = ixgbe_select_queue,
97488bd1 7290#endif
581330ba 7291 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7292 .ndo_validate_addr = eth_validate_addr,
7293 .ndo_set_mac_address = ixgbe_set_mac,
7294 .ndo_change_mtu = ixgbe_change_mtu,
7295 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7296 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7297 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7298 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7299 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7300 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7301 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7302 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7303 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7304 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7305#ifdef CONFIG_IXGBE_DCB
24095aa3 7306 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7307#endif
0edc3527
SH		 7308#ifdef CONFIG_NET_POLL_CONTROLLER
7309 .ndo_poll_controller = ixgbe_netpoll,
7310#endif
5a85e737 7311#ifdef CONFIG_NET_LL_RX_POLL
8b80cda5 7312 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7313#endif
332d4a7d
YZ		 7314#ifdef IXGBE_FCOE
7315 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7316 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7317 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7318 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7319 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7320 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7321 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7322#endif /* IXGBE_FCOE */
082757af
DS		 7323 .ndo_set_features = ixgbe_set_features,
7324 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7325 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7326 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7327 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
0edc3527
SH		 7328};
7329
e027d1ae
JK		 7330/**
7331 * ixgbe_enumerate_functions - Get the number of ports this device has
7332 * @adapter: adapter structure
7333 *
7334 * This function enumerates the phsyical functions co-located on a single slot,
7335 * in order to determine how many ports a device has. This is most useful in
7336 * determining the required GT/s of PCIe bandwidth necessary for optimal
7337 * performance.
7338 **/
7339static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7340{
7341 struct ixgbe_hw *hw = &adapter->hw;
7342 struct list_head *entry;
7343 int physfns = 0;
7344
7345 /* Some cards can not use the generic count PCIe functions method, and
7346 * so must be hardcoded to the correct value.
7347 */
7348 switch (hw->device_id) {
7349 case IXGBE_DEV_ID_82599_SFP_SF_QP:
7350 physfns = 4;
7351 break;
7352 default:
7353 list_for_each(entry, &adapter->pdev->bus_list) {
7354 struct pci_dev *pdev =
7355 list_entry(entry, struct pci_dev, bus_list);
7356 /* don't count virtual functions */
7357 if (!pdev->is_virtfn)
7358 physfns++;
7359 }
7360 }
7361
7362 return physfns;
7363}
7364
8e2813f5
JK		 7365/**
7366 * ixgbe_wol_supported - Check whether device supports WoL
7367 * @hw: hw specific details
7368 * @device_id: the device ID
7369 * @subdev_id: the subsystem device ID
7370 *
7371 * This function is used by probe and ethtool to determine
7372 * which devices have WoL support
7373 *
7374 **/
7375int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7376 u16 subdevice_id)
7377{
7378 struct ixgbe_hw *hw = &adapter->hw;
7379 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7380 int is_wol_supported = 0;
7381
7382 switch (device_id) {
7383 case IXGBE_DEV_ID_82599_SFP:
7384 /* Only these subdevices could supports WOL */
7385 switch (subdevice_id) {
7386 case IXGBE_SUBDEV_ID_82599_560FLR:
7387 /* only support first port */
7388 if (hw->bus.func != 0)
7389 break;
5700ff26 7390 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7391 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7392 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7393 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7394 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7395 is_wol_supported = 1;
7396 break;
7397 }
7398 break;
5daebbb0
DS		 7399 case IXGBE_DEV_ID_82599EN_SFP:
7400 /* Only this subdevice supports WOL */
7401 switch (subdevice_id) {
7402 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7403 is_wol_supported = 1;
7404 break;
7405 }
7406 break;
8e2813f5
JK		 7407 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7408 /* All except this subdevice support WOL */
7409 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7410 is_wol_supported = 1;
7411 break;
7412 case IXGBE_DEV_ID_82599_KX4:
7413 is_wol_supported = 1;
7414 break;
7415 case IXGBE_DEV_ID_X540T:
df376f0d 7416 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7417 /* check eeprom to see if enabled wol */
7418 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7419 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7420 (hw->bus.func == 0))) {
7421 is_wol_supported = 1;
7422 }
7423 break;
7424 }
7425
7426 return is_wol_supported;
7427}
7428
9a799d71
AK		 7429/**
7430 * ixgbe_probe - Device Initialization Routine
7431 * @pdev: PCI device information struct
7432 * @ent: entry in ixgbe_pci_tbl
7433 *
7434 * Returns 0 on success, negative on failure
7435 *
7436 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7437 * The OS initialization, configuring of the adapter private structure,
7438 * and a hardware reset occur.
7439 **/
1dd06ae8 7440static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7441{
7442 struct net_device *netdev;
7443 struct ixgbe_adapter *adapter = NULL;
7444 struct ixgbe_hw *hw;
7445 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7446 static int cards_found;
e027d1ae 7447 int i, err, pci_using_dac, expected_gts;
d3cb9869 7448 unsigned int indices = MAX_TX_QUEUES;
289700db 7449 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7450#ifdef IXGBE_FCOE
7451 u16 device_caps;
7452#endif
289700db 7453 u32 eec;
9a799d71 7454
bded64a7
AG		 7455 /* Catch broken hardware that put the wrong VF device ID in
7456 * the PCIe SR-IOV capability.
7457 */
7458 if (pdev->is_virtfn) {
7459 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7460 pci_name(pdev), pdev->vendor, pdev->device);
7461 return -EINVAL;
7462 }
7463
9ce77666 7464 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7465 if (err)
7466 return err;
7467
1b507730
NN		 7468 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7469 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7470 pci_using_dac = 1;
7471 } else {
1b507730 7472 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7473 if (err) {
1b507730
NN		 7474 err = dma_set_coherent_mask(&pdev->dev,
7475 DMA_BIT_MASK(32));
9a799d71 7476 if (err) {
b8bc0421
DC		 7477 dev_err(&pdev->dev,
7478 "No usable DMA configuration, aborting\n");
9a799d71
AK		 7479 goto err_dma;
7480 }
7481 }
7482 pci_using_dac = 0;
7483 }
7484
9ce77666 7485 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7486 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 7487 if (err) {
b8bc0421
DC		 7488 dev_err(&pdev->dev,
7489 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 7490 goto err_pci_reg;
7491 }
7492
19d5afd4 7493 pci_enable_pcie_error_reporting(pdev);
6fabd715 7494
9a799d71 7495 pci_set_master(pdev);
fb3b27bc 7496 pci_save_state(pdev);
9a799d71 7497
d3cb9869 7498 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 7499#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 7500 /* 8 TC w/ 4 queues per TC */
7501 indices = 4 * MAX_TRAFFIC_CLASS;
7502#else
7503 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 7504#endif
d3cb9869 7505 }
e901acd6 7506
c85a2618 7507 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 7508 if (!netdev) {
7509 err = -ENOMEM;
7510 goto err_alloc_etherdev;
7511 }
7512
9a799d71
AK		 7513 SET_NETDEV_DEV(netdev, &pdev->dev);
7514
9a799d71 7515 adapter = netdev_priv(netdev);
c60fbb00 7516 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 7517
7518 adapter->netdev = netdev;
7519 adapter->pdev = pdev;
7520 hw = &adapter->hw;
7521 hw->back = adapter;
b3f4d599 7522 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 7523
05857980 7524 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 7525 pci_resource_len(pdev, 0));
9a799d71
AK		 7526 if (!hw->hw_addr) {
7527 err = -EIO;
7528 goto err_ioremap;
7529 }
7530
0edc3527 7531 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 7532 ixgbe_set_ethtool_ops(netdev);
9a799d71 7533 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 7534 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 7535
9a799d71
AK		 7536 adapter->bd_number = cards_found;
7537
9a799d71
AK		 7538 /* Setup hw api */
7539 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 7540 hw->mac.type = ii->mac;
9a799d71 7541
c44ade9e
JB		 7542 /* EEPROM */
7543 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7544 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7545 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7546 if (!(eec & (1 << 8)))
7547 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7548
7549 /* PHY */
7550 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 7551 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 7552 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7553 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7554 hw->phy.mdio.mmds = 0;
7555 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7556 hw->phy.mdio.dev = netdev;
7557 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7558 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 7559
8ca783ab 7560 ii->get_invariants(hw);
9a799d71
AK		 7561
7562 /* setup the private structure */
7563 err = ixgbe_sw_init(adapter);
7564 if (err)
7565 goto err_sw_init;
7566
0b2679d6
DS		 7567 /* Cache if MNG FW is up so we don't have to read the REG later */
7568 if (hw->mac.ops.mng_fw_enabled)
7569 hw->mng_fw_enabled = hw->mac.ops.mng_fw_enabled(hw);
7570
e86bff0e 7571 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 7572 switch (adapter->hw.mac.type) {
7573 case ixgbe_mac_82599EB:
7574 case ixgbe_mac_X540:
e86bff0e 7575 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 7576 break;
7577 default:
7578 break;
7579 }
e86bff0e 7580
bf069c97
DS		 7581 /*
7582 * If there is a fan on this device and it has failed log the
7583 * failure.
7584 */
7585 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7586 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7587 if (esdp & IXGBE_ESDP_SDP1)
396e799c 7588 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 7589 }
7590
8ef78adc
PWJ		 7591 if (allow_unsupported_sfp)
7592 hw->allow_unsupported_sfp = allow_unsupported_sfp;
7593
c44ade9e 7594 /* reset_hw fills in the perm_addr as well */
119fc60a 7595 hw->phy.reset_if_overtemp = true;
c44ade9e 7596 err = hw->mac.ops.reset_hw(hw);
119fc60a 7597 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 7598 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7599 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 7600 err = 0;
7601 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7086400d 7602 e_dev_err("failed to load because an unsupported SFP+ "
849c4542
ET		 7603 "module type was detected.\n");
7604 e_dev_err("Reload the driver after installing a supported "
7605 "module.\n");
04f165ef
PW		 7606 goto err_sw_init;
7607 } else if (err) {
849c4542 7608 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 7609 goto err_sw_init;
7610 }
7611
99d74487 7612#ifdef CONFIG_PCI_IOV
60a1a680
GR		 7613 /* SR-IOV not supported on the 82598 */
7614 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7615 goto skip_sriov;
7616 /* Mailbox */
7617 ixgbe_init_mbx_params_pf(hw);
7618 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
7619 ixgbe_enable_sriov(adapter);
43dc4e01 7620 pci_sriov_set_totalvfs(pdev, 63);
60a1a680 7621skip_sriov:
1cdd1ec8 7622
99d74487 7623#endif
396e799c 7624 netdev->features = NETIF_F_SG |
e8e9f696 7625 NETIF_F_IP_CSUM |
082757af 7626 NETIF_F_IPV6_CSUM |
f646968f
PM		 7627 NETIF_F_HW_VLAN_CTAG_TX |
7628 NETIF_F_HW_VLAN_CTAG_RX |
7629 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 7630 NETIF_F_TSO |
7631 NETIF_F_TSO6 |
082757af
DS		 7632 NETIF_F_RXHASH |
7633 NETIF_F_RXCSUM;
9a799d71 7634
082757af 7635 netdev->hw_features = netdev->features;
ad31c402 7636
58be7666
DS		 7637 switch (adapter->hw.mac.type) {
7638 case ixgbe_mac_82599EB:
7639 case ixgbe_mac_X540:
45a5ead0 7640 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 7641 netdev->hw_features |= NETIF_F_SCTP_CSUM |
7642 NETIF_F_NTUPLE;
58be7666
DS		 7643 break;
7644 default:
7645 break;
7646 }
45a5ead0 7647
3f2d1c0f
BG		 7648 netdev->hw_features |= NETIF_F_RXALL;
7649
ad31c402
JK		 7650 netdev->vlan_features |= NETIF_F_TSO;
7651 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 7652 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 7653 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 7654 netdev->vlan_features |= NETIF_F_SG;
7655
01789349 7656 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 7657 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 7658
7a6b6f51 7659#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 7660 netdev->dcbnl_ops = &dcbnl_ops;
7661#endif
7662
eacd73f7 7663#ifdef IXGBE_FCOE
0d551589 7664 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 7665 unsigned int fcoe_l;
7666
eacd73f7
YZ		 7667 if (hw->mac.ops.get_device_caps) {
7668 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 7669 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7670 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 7671 }
7c8ae65a 7672
d3cb9869
AD		 7673
7674 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
7675 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 7676
a58915c7
AD		 7677 netdev->features |= NETIF_F_FSO |
7678 NETIF_F_FCOE_CRC;
7679
7c8ae65a
AD		 7680 netdev->vlan_features |= NETIF_F_FSO |
7681 NETIF_F_FCOE_CRC |
7682 NETIF_F_FCOE_MTU;
5e09d7f6 7683 }
eacd73f7 7684#endif /* IXGBE_FCOE */
7b872a55 7685 if (pci_using_dac) {
9a799d71 7686 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 7687 netdev->vlan_features |= NETIF_F_HIGHDMA;
7688 }
9a799d71 7689
082757af
DS		 7690 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
7691 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 7692 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 7693 netdev->features |= NETIF_F_LRO;
7694
9a799d71 7695 /* make sure the EEPROM is good */
c44ade9e 7696 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 7697 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 7698 err = -EIO;
35937c05 7699 goto err_sw_init;
9a799d71
AK		 7700 }
7701
7702 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 7703
aaeb6cdf 7704 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 7705 e_dev_err("invalid MAC address\n");
9a799d71 7706 err = -EIO;
35937c05 7707 goto err_sw_init;
9a799d71
AK		 7708 }
7709
7086400d 7710 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 7711 (unsigned long) adapter);
9a799d71 7712
7086400d
AD		 7713 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7714 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 7715
021230d4
AV		 7716 err = ixgbe_init_interrupt_scheme(adapter);
7717 if (err)
7718 goto err_sw_init;
9a799d71 7719
8e2813f5 7720 /* WOL not supported for all devices */
c23f5b6b 7721 adapter->wol = 0;
8e2813f5 7722 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 7723 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 7724 pdev->subsystem_device);
6b92b0ba 7725 if (hw->wol_enabled)
9417c464 7726 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 7727
e8e26350
PW		 7728 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7729
15e5209f
ET		 7730 /* save off EEPROM version number */
7731 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
7732 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
7733
04f165ef
PW		 7734 /* pick up the PCI bus settings for reporting later */
7735 hw->mac.ops.get_bus_info(hw);
e027d1ae 7736 if (ixgbe_pcie_from_parent(hw))
b8e82001 7737 ixgbe_get_parent_bus_info(adapter);
04f165ef 7738
9a799d71 7739 /* print bus type/speed/width info */
849c4542 7740 e_dev_info("(PCI Express:%s:%s) %pM\n",
e8710a5f
JK		 7741 (hw->bus.speed == ixgbe_bus_speed_8000 ? "8.0GT/s" :
7742 hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
6716344c 7743 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
e8e9f696
JP		 7744 "Unknown"),
7745 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7746 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7747 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7748 "Unknown"),
7749 netdev->dev_addr);
289700db
DS		 7750
7751 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7752 if (err)
9fe93afd 7753 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
e8e26350 7754 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
289700db 7755 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
849c4542 7756 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
289700db 7757 part_str);
e8e26350 7758 else
289700db
DS		 7759 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7760 hw->mac.type, hw->phy.type, part_str);
9a799d71 7761
e027d1ae
JK		 7762 /* calculate the expected PCIe bandwidth required for optimal
7763 * performance. Note that some older parts will never have enough
7764 * bandwidth due to being older generation PCIe parts. We clamp these
7765 * parts to ensure no warning is displayed if it can't be fixed.
7766 */
7767 switch (hw->mac.type) {
7768 case ixgbe_mac_82598EB:
7769 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
7770 break;
7771 default:
7772 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
7773 break;
0c254d86 7774 }
e027d1ae 7775 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 7776
9a799d71 7777 /* reset the hardware with the new settings */
794caeb2 7778 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 7779 if (err == IXGBE_ERR_EEPROM_VERSION) {
7780 /* We are running on a pre-production device, log a warning */
849c4542
ET		 7781 e_dev_warn("This device is a pre-production adapter/LOM. "
7782 "Please be aware there may be issues associated "
7783 "with your hardware. If you are experiencing "
7784 "problems please contact your Intel or hardware "
7785 "representative who provided you with this "
7786 "hardware.\n");
794caeb2 7787 }
9a799d71
AK		 7788 strcpy(netdev->name, "eth%d");
7789 err = register_netdev(netdev);
7790 if (err)
7791 goto err_register;
7792
ec74a471
ET		 7793 /* power down the optics for 82599 SFP+ fiber */
7794 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 7795 hw->mac.ops.disable_tx_laser(hw);
7796
54386467
JB		 7797 /* carrier off reporting is important to ethtool even BEFORE open */
7798 netif_carrier_off(netdev);
7799
5dd2d332 7800#ifdef CONFIG_IXGBE_DCA
652f093f 7801 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 7802 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 7803 ixgbe_setup_dca(adapter);
7804 }
7805#endif
1cdd1ec8 7806 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 7807 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 7808 for (i = 0; i < adapter->num_vfs; i++)
7809 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7810 }
7811
2466dd9c
JK		 7812 /* firmware requires driver version to be 0xFFFFFFFF
7813 * since os does not support feature
7814 */
9612de92 7815 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 7816 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
7817 0xFF);
9612de92 7818
0365e6e4
PW		 7819 /* add san mac addr to netdev */
7820 ixgbe_add_sanmac_netdev(netdev);
9a799d71 7821
ea81875a 7822 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 7823 cards_found++;
3ca8bc6d 7824
1210982b 7825#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 7826 if (ixgbe_sysfs_init(adapter))
7827 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 7828#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7829
00949167 7830 ixgbe_dbg_adapter_init(adapter);
00949167 7831
0b2679d6
DS		 7832 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7833 if (hw->mng_fw_enabled && hw->mac.ops.setup_link)
7834 hw->mac.ops.setup_link(hw,
7835 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
7836 true);
7837
9a799d71
AK		 7838 return 0;
7839
7840err_register:
5eba3699 7841 ixgbe_release_hw_control(adapter);
7a921c93 7842 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 7843err_sw_init:
99d74487 7844 ixgbe_disable_sriov(adapter);
7086400d 7845 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71
AK		 7846 iounmap(hw->hw_addr);
7847err_ioremap:
7848 free_netdev(netdev);
7849err_alloc_etherdev:
e8e9f696
JP		 7850 pci_release_selected_regions(pdev,
7851 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 7852err_pci_reg:
7853err_dma:
7854 pci_disable_device(pdev);
7855 return err;
7856}
7857
7858/**
7859 * ixgbe_remove - Device Removal Routine
7860 * @pdev: PCI device information struct
7861 *
7862 * ixgbe_remove is called by the PCI subsystem to alert the driver
7863 * that it should release a PCI device. The could be caused by a
7864 * Hot-Plug event, or because the driver is going to be removed from
7865 * memory.
7866 **/
9f9a12f8 7867static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 7868{
c60fbb00
AD		 7869 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7870 struct net_device *netdev = adapter->netdev;
9a799d71 7871
00949167 7872 ixgbe_dbg_adapter_exit(adapter);
00949167 7873
9a799d71 7874 set_bit(__IXGBE_DOWN, &adapter->state);
7086400d 7875 cancel_work_sync(&adapter->service_task);
9a799d71 7876
3a6a4eda 7877
5dd2d332 7878#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 7879 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7880 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7881 dca_remove_requester(&pdev->dev);
7882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7883 }
7884
7885#endif
1210982b 7886#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 7887 ixgbe_sysfs_exit(adapter);
1210982b 7888#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 7889
0365e6e4
PW		 7890 /* remove the added san mac */
7891 ixgbe_del_sanmac_netdev(netdev);
7892
c4900be0
DS		 7893 if (netdev->reg_state == NETREG_REGISTERED)
7894 unregister_netdev(netdev);
9a799d71 7895
da36b647
GR		 7896#ifdef CONFIG_PCI_IOV
7897 /*
7898 * Only disable SR-IOV on unload if the user specified the now
7899 * deprecated max_vfs module parameter.
7900 */
7901 if (max_vfs)
7902 ixgbe_disable_sriov(adapter);
7903#endif
7a921c93 7904 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 7905
021230d4 7906 ixgbe_release_hw_control(adapter);
9a799d71 7907
2b1588c3
AD		 7908#ifdef CONFIG_DCB
7909 kfree(adapter->ixgbe_ieee_pfc);
7910 kfree(adapter->ixgbe_ieee_ets);
7911
7912#endif
9a799d71 7913 iounmap(adapter->hw.hw_addr);
9ce77666 7914 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 7915 IORESOURCE_MEM));
9a799d71 7916
849c4542 7917 e_dev_info("complete\n");
021230d4 7918
9a799d71
AK		 7919 free_netdev(netdev);
7920
19d5afd4 7921 pci_disable_pcie_error_reporting(pdev);
6fabd715 7922
9a799d71
AK		 7923 pci_disable_device(pdev);
7924}
7925
7926/**
7927 * ixgbe_io_error_detected - called when PCI error is detected
7928 * @pdev: Pointer to PCI device
7929 * @state: The current pci connection state
7930 *
7931 * This function is called after a PCI bus error affecting
7932 * this device has been detected.
7933 */
7934static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 7935 pci_channel_state_t state)
9a799d71 7936{
c60fbb00
AD		 7937 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7938 struct net_device *netdev = adapter->netdev;
9a799d71 7939
83c61fa9
GR		 7940#ifdef CONFIG_PCI_IOV
7941 struct pci_dev *bdev, *vfdev;
7942 u32 dw0, dw1, dw2, dw3;
7943 int vf, pos;
7944 u16 req_id, pf_func;
7945
7946 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7947 adapter->num_vfs == 0)
7948 goto skip_bad_vf_detection;
7949
7950 bdev = pdev->bus->self;
62f87c0e 7951 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 7952 bdev = bdev->bus->self;
7953
7954 if (!bdev)
7955 goto skip_bad_vf_detection;
7956
7957 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
7958 if (!pos)
7959 goto skip_bad_vf_detection;
7960
7961 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0);
7962 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1);
7963 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2);
7964 pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3);
7965
7966 req_id = dw1 >> 16;
7967 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
7968 if (!(req_id & 0x0080))
7969 goto skip_bad_vf_detection;
7970
7971 pf_func = req_id & 0x01;
7972 if ((pf_func & 1) == (pdev->devfn & 1)) {
7973 unsigned int device_id;
7974
7975 vf = (req_id & 0x7F) >> 1;
7976 e_dev_err("VF %d has caused a PCIe error\n", vf);
7977 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
7978 "%8.8x\tdw3: %8.8x\n",
7979 dw0, dw1, dw2, dw3);
7980 switch (adapter->hw.mac.type) {
7981 case ixgbe_mac_82599EB:
7982 device_id = IXGBE_82599_VF_DEVICE_ID;
7983 break;
7984 case ixgbe_mac_X540:
7985 device_id = IXGBE_X540_VF_DEVICE_ID;
7986 break;
7987 default:
7988 device_id = 0;
7989 break;
7990 }
7991
7992 /* Find the pci device of the offending VF */
36e90319 7993 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 7994 while (vfdev) {
7995 if (vfdev->devfn == (req_id & 0xFF))
7996 break;
36e90319 7997 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 7998 device_id, vfdev);
7999 }
8000 /*
8001 * There's a slim chance the VF could have been hot plugged,
8002 * so if it is no longer present we don't need to issue the
8003 * VFLR. Just clean up the AER in that case.
8004 */
8005 if (vfdev) {
8006 e_dev_err("Issuing VFLR to VF %d\n", vf);
8007 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8008 /* Free device reference count */
8009 pci_dev_put(vfdev);
83c61fa9
GR		 8010 }
8011
8012 pci_cleanup_aer_uncorrect_error_status(pdev);
8013 }
8014
8015 /*
8016 * Even though the error may have occurred on the other port
8017 * we still need to increment the vf error reference count for
8018 * both ports because the I/O resume function will be called
8019 * for both of them.
8020 */
8021 adapter->vferr_refcount++;
8022
8023 return PCI_ERS_RESULT_RECOVERED;
8024
8025skip_bad_vf_detection:
8026#endif /* CONFIG_PCI_IOV */
9a799d71
AK		 8027 netif_device_detach(netdev);
8028
3044b8d1
BL		 8029 if (state == pci_channel_io_perm_failure)
8030 return PCI_ERS_RESULT_DISCONNECT;
8031
9a799d71
AK		 8032 if (netif_running(netdev))
8033 ixgbe_down(adapter);
8034 pci_disable_device(pdev);
8035
b4617240 8036 /* Request a slot reset. */
9a799d71
AK		 8037 return PCI_ERS_RESULT_NEED_RESET;
8038}
8039
8040/**
8041 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8042 * @pdev: Pointer to PCI device
8043 *
8044 * Restart the card from scratch, as if from a cold-boot.
8045 */
8046static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8047{
c60fbb00 8048 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8049 pci_ers_result_t result;
8050 int err;
9a799d71 8051
9ce77666 8052 if (pci_enable_device_mem(pdev)) {
396e799c 8053 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8054 result = PCI_ERS_RESULT_DISCONNECT;
8055 } else {
8056 pci_set_master(pdev);
8057 pci_restore_state(pdev);
c0e1f68b 8058 pci_save_state(pdev);
9a799d71 8059
dd4d8ca6 8060 pci_wake_from_d3(pdev, false);
9a799d71 8061
6fabd715 8062 ixgbe_reset(adapter);
88512539 8063 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8064 result = PCI_ERS_RESULT_RECOVERED;
8065 }
8066
8067 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8068 if (err) {
849c4542
ET		 8069 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8070 "failed 0x%0x\n", err);
6fabd715
PWJ		 8071 /* non-fatal, continue */
8072 }
9a799d71 8073
6fabd715 8074 return result;
9a799d71
AK		 8075}
8076
8077/**
8078 * ixgbe_io_resume - called when traffic can start flowing again.
8079 * @pdev: Pointer to PCI device
8080 *
8081 * This callback is called when the error recovery driver tells us that
8082 * its OK to resume normal operation.
8083 */
8084static void ixgbe_io_resume(struct pci_dev *pdev)
8085{
c60fbb00
AD		 8086 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8087 struct net_device *netdev = adapter->netdev;
9a799d71 8088
83c61fa9
GR		 8089#ifdef CONFIG_PCI_IOV
8090 if (adapter->vferr_refcount) {
8091 e_info(drv, "Resuming after VF err\n");
8092 adapter->vferr_refcount--;
8093 return;
8094 }
8095
8096#endif
c7ccde0f
AD		 8097 if (netif_running(netdev))
8098 ixgbe_up(adapter);
9a799d71
AK		 8099
8100 netif_device_attach(netdev);
9a799d71
AK		 8101}
8102
3646f0e5 8103static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8104 .error_detected = ixgbe_io_error_detected,
8105 .slot_reset = ixgbe_io_slot_reset,
8106 .resume = ixgbe_io_resume,
8107};
8108
8109static struct pci_driver ixgbe_driver = {
8110 .name = ixgbe_driver_name,
8111 .id_table = ixgbe_pci_tbl,
8112 .probe = ixgbe_probe,
9f9a12f8 8113 .remove = ixgbe_remove,
9a799d71
AK		 8114#ifdef CONFIG_PM
8115 .suspend = ixgbe_suspend,
8116 .resume = ixgbe_resume,
8117#endif
8118 .shutdown = ixgbe_shutdown,
da36b647 8119 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8120 .err_handler = &ixgbe_err_handler
8121};
8122
8123/**
8124 * ixgbe_init_module - Driver Registration Routine
8125 *
8126 * ixgbe_init_module is the first routine called when the driver is
8127 * loaded. All it does is register with the PCI subsystem.
8128 **/
8129static int __init ixgbe_init_module(void)
8130{
8131 int ret;
c7689578 8132 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8133 pr_info("%s\n", ixgbe_copyright);
9a799d71 8134
00949167 8135 ixgbe_dbg_init();
00949167 8136
f01fc1a8
JK		 8137 ret = pci_register_driver(&ixgbe_driver);
8138 if (ret) {
f01fc1a8 8139 ixgbe_dbg_exit();
f01fc1a8
JK		 8140 return ret;
8141 }
8142
5dd2d332 8143#ifdef CONFIG_IXGBE_DCA
bd0362dd 8144 dca_register_notify(&dca_notifier);
bd0362dd 8145#endif
5dd2d332 8146
f01fc1a8 8147 return 0;
9a799d71 8148}
b4617240 8149
9a799d71
AK		 8150module_init(ixgbe_init_module);
8151
8152/**
8153 * ixgbe_exit_module - Driver Exit Cleanup Routine
8154 *
8155 * ixgbe_exit_module is called just before the driver is removed
8156 * from memory.
8157 **/
8158static void __exit ixgbe_exit_module(void)
8159{
5dd2d332 8160#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8161 dca_unregister_notify(&dca_notifier);
8162#endif
9a799d71 8163 pci_unregister_driver(&ixgbe_driver);
00949167 8164
00949167 8165 ixgbe_dbg_exit();
00949167 8166
1a51502b 8167 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8168}
bd0362dd 8169
5dd2d332 8170#ifdef CONFIG_IXGBE_DCA
bd0362dd 8171static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8172 void *p)
bd0362dd
JC		 8173{
8174 int ret_val;
8175
8176 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8177 __ixgbe_notify_dca);
bd0362dd
JC		 8178
8179 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8180}
b453368d 8181
5dd2d332 8182#endif /* CONFIG_IXGBE_DCA */
849c4542 8183
9a799d71
AK		 8184module_exit(ixgbe_exit_module);
8185
8186/* ixgbe_main.c */
Linux kernel - Deliverables
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