projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: Use out-of-line function for register reads
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
0391bbe3 4 Copyright(c) 1999 - 2014 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
b89aae71 23 Linux NICS <linux.nics@intel.com>
9a799d71
AK		 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27*******************************************************************************/
28
29#include <linux/types.h>
30#include <linux/module.h>
31#include <linux/pci.h>
32#include <linux/netdevice.h>
33#include <linux/vmalloc.h>
34#include <linux/string.h>
35#include <linux/in.h>
a6b7a407 36#include <linux/interrupt.h>
9a799d71
AK		 37#include <linux/ip.h>
38#include <linux/tcp.h>
897ab156 39#include <linux/sctp.h>
60127865 40#include <linux/pkt_sched.h>
9a799d71 41#include <linux/ipv6.h>
5a0e3ad6 42#include <linux/slab.h>
9a799d71
AK		 43#include <net/checksum.h>
44#include <net/ip6_checksum.h>
45#include <linux/ethtool.h>
01789349 46#include <linux/if.h>
9a799d71 47#include <linux/if_vlan.h>
2a47fa45 48#include <linux/if_macvlan.h>
815cccbf 49#include <linux/if_bridge.h>
70c71606 50#include <linux/prefetch.h>
eacd73f7 51#include <scsi/fc/fc_fcoe.h>
9a799d71
AK		 52
53#include "ixgbe.h"
54#include "ixgbe_common.h"
ee5f784a 55#include "ixgbe_dcb_82599.h"
1cdd1ec8 56#include "ixgbe_sriov.h"
9a799d71
AK		 57
58char ixgbe_driver_name[] = "ixgbe";
9c8eb720 59static const char ixgbe_driver_string[] =
e8e9f696 60 "Intel(R) 10 Gigabit PCI Express Network Driver";
8af3c33f 61#ifdef IXGBE_FCOE
ea81875a
NP		 62char ixgbe_default_device_descr[] =
63 "Intel(R) 10 Gigabit Network Connection";
8af3c33f
JK		 64#else
65static char ixgbe_default_device_descr[] =
66 "Intel(R) 10 Gigabit Network Connection";
67#endif
f341c4e0 68#define DRV_VERSION "3.19.1-k"
9c8eb720 69const char ixgbe_driver_version[] = DRV_VERSION;
a52055e0 70static const char ixgbe_copyright[] =
0391bbe3 71 "Copyright (c) 1999-2014 Intel Corporation.";
9a799d71
AK		 72
73static const struct ixgbe_info *ixgbe_info_tbl[] = {
b4617240 74 [board_82598] = &ixgbe_82598_info,
e8e26350 75 [board_82599] = &ixgbe_82599_info,
fe15e8e1 76 [board_X540] = &ixgbe_X540_info,
9a799d71
AK		 77};
78
79/* ixgbe_pci_tbl - PCI Device ID Table
80 *
81 * Wildcard entries (PCI_ANY_ID) should come last
82 * Last entry must be all 0s
83 *
84 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
85 * Class, Class Mask, private data (not used) }
86 */
a3aa1884 87static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
54239c67
AD		 88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
8f58332b 114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
7d145282 115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
9e791e4a 116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
df376f0d 117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
9a799d71
AK		 118 /* required last entry */
119 {0, }
120};
121MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
122
5dd2d332 123#ifdef CONFIG_IXGBE_DCA
bd0362dd 124static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
e8e9f696 125 void *p);
bd0362dd
JC		 126static struct notifier_block dca_notifier = {
127 .notifier_call = ixgbe_notify_dca,
128 .next = NULL,
129 .priority = 0
130};
131#endif
132
1cdd1ec8
GR		 133#ifdef CONFIG_PCI_IOV
134static unsigned int max_vfs;
135module_param(max_vfs, uint, 0);
e8e9f696 136MODULE_PARM_DESC(max_vfs,
170e8543 137 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
1cdd1ec8
GR		 138#endif /* CONFIG_PCI_IOV */
139
8ef78adc
PWJ		 140static unsigned int allow_unsupported_sfp;
141module_param(allow_unsupported_sfp, uint, 0);
142MODULE_PARM_DESC(allow_unsupported_sfp,
143 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
144
b3f4d599 145#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
146static int debug = -1;
147module_param(debug, int, 0);
148MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
149
9a799d71
AK		 150MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
151MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
152MODULE_LICENSE("GPL");
153MODULE_VERSION(DRV_VERSION);
154
14438464
MR		 155static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
156
b8e82001
JK		 157static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
158 u32 reg, u16 *value)
159{
b8e82001
JK		 160 struct pci_dev *parent_dev;
161 struct pci_bus *parent_bus;
162
163 parent_bus = adapter->pdev->bus->parent;
164 if (!parent_bus)
165 return -1;
166
167 parent_dev = parent_bus->self;
168 if (!parent_dev)
169 return -1;
170
c0798edf 171 if (!pci_is_pcie(parent_dev))
b8e82001
JK		 172 return -1;
173
c0798edf 174 pcie_capability_read_word(parent_dev, reg, value);
14438464
MR		 175 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
176 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
177 return -1;
b8e82001
JK		 178 return 0;
179}
180
181static s32 ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
182{
183 struct ixgbe_hw *hw = &adapter->hw;
184 u16 link_status = 0;
185 int err;
186
187 hw->bus.type = ixgbe_bus_type_pci_express;
188
189 /* Get the negotiated link width and speed from PCI config space of the
190 * parent, as this device is behind a switch
191 */
192 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
193
194 /* assume caller will handle error case */
195 if (err)
196 return err;
197
198 hw->bus.width = ixgbe_convert_bus_width(link_status);
199 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
200
201 return 0;
202}
203
e027d1ae
JK		 204/**
205 * ixgbe_check_from_parent - Determine whether PCIe info should come from parent
206 * @hw: hw specific details
207 *
208 * This function is used by probe to determine whether a device's PCI-Express
209 * bandwidth details should be gathered from the parent bus instead of from the
210 * device. Used to ensure that various locations all have the correct device ID
211 * checks.
212 */
213static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
214{
215 switch (hw->device_id) {
216 case IXGBE_DEV_ID_82599_SFP_SF_QP:
8f58332b 217 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
e027d1ae
JK		 218 return true;
219 default:
220 return false;
221 }
222}
223
224static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
225 int expected_gts)
226{
227 int max_gts = 0;
228 enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
229 enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
230 struct pci_dev *pdev;
231
232 /* determine whether to use the the parent device
233 */
234 if (ixgbe_pcie_from_parent(&adapter->hw))
235 pdev = adapter->pdev->bus->parent->self;
236 else
237 pdev = adapter->pdev;
238
239 if (pcie_get_minimum_link(pdev, &speed, &width) ||
240 speed == PCI_SPEED_UNKNOWN || width == PCIE_LNK_WIDTH_UNKNOWN) {
241 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
242 return;
243 }
244
245 switch (speed) {
246 case PCIE_SPEED_2_5GT:
247 /* 8b/10b encoding reduces max throughput by 20% */
248 max_gts = 2 * width;
249 break;
250 case PCIE_SPEED_5_0GT:
251 /* 8b/10b encoding reduces max throughput by 20% */
252 max_gts = 4 * width;
253 break;
254 case PCIE_SPEED_8_0GT:
9f0a433c 255 /* 128b/130b encoding reduces throughput by less than 2% */
e027d1ae
JK		 256 max_gts = 8 * width;
257 break;
258 default:
259 e_dev_warn("Unable to determine PCI Express bandwidth.\n");
260 return;
261 }
262
263 e_dev_info("PCI Express bandwidth of %dGT/s available\n",
264 max_gts);
265 e_dev_info("(Speed:%s, Width: x%d, Encoding Loss:%s)\n",
266 (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" :
267 speed == PCIE_SPEED_5_0GT ? "5.0GT/s" :
268 speed == PCIE_SPEED_2_5GT ? "2.5GT/s" :
269 "Unknown"),
270 width,
271 (speed == PCIE_SPEED_2_5GT ? "20%" :
272 speed == PCIE_SPEED_5_0GT ? "20%" :
9f0a433c 273 speed == PCIE_SPEED_8_0GT ? "<2%" :
e027d1ae
JK		 274 "Unknown"));
275
276 if (max_gts < expected_gts) {
277 e_dev_warn("This is not sufficient for optimal performance of this card.\n");
278 e_dev_warn("For optimal performance, at least %dGT/s of bandwidth is required.\n",
279 expected_gts);
280 e_dev_warn("A slot with more lanes and/or higher speed is suggested.\n");
281 }
282}
283
7086400d
AD		 284static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
285{
286 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
09f40aed 287 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
7086400d
AD		 288 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
289 schedule_work(&adapter->service_task);
290}
291
2a1a091c
MR		 292static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
293{
294 struct ixgbe_adapter *adapter = hw->back;
295
296 if (!hw->hw_addr)
297 return;
298 hw->hw_addr = NULL;
299 e_dev_err("Adapter removed\n");
58cf663f
MR		 300 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
301 ixgbe_service_event_schedule(adapter);
2a1a091c
MR		 302}
303
f8e2472f 304static void ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
2a1a091c
MR		 305{
306 u32 value;
307
308 /* The following check not only optimizes a bit by not
309 * performing a read on the status register when the
310 * register just read was a status register read that
311 * returned IXGBE_FAILED_READ_REG. It also blocks any
312 * potential recursion.
313 */
314 if (reg == IXGBE_STATUS) {
315 ixgbe_remove_adapter(hw);
316 return;
317 }
318 value = ixgbe_read_reg(hw, IXGBE_STATUS);
319 if (value == IXGBE_FAILED_READ_REG)
320 ixgbe_remove_adapter(hw);
321}
322
f8e2472f
MR		 323/**
324 * ixgbe_read_reg - Read from device register
325 * @hw: hw specific details
326 * @reg: offset of register to read
327 *
328 * Returns : value read or IXGBE_FAILED_READ_REG if removed
329 *
330 * This function is used to read device registers. It checks for device
331 * removal by confirming any read that returns all ones by checking the
332 * status register value for all ones. This function avoids reading from
333 * the hardware if a removal was previously detected in which case it
334 * returns IXGBE_FAILED_READ_REG (all ones).
335 */
336u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
337{
338 u8 __iomem *reg_addr = ACCESS_ONCE(hw->hw_addr);
339 u32 value;
340
341 if (ixgbe_removed(reg_addr))
342 return IXGBE_FAILED_READ_REG;
343 value = readl(reg_addr + reg);
344 if (unlikely(value == IXGBE_FAILED_READ_REG))
345 ixgbe_check_remove(hw, reg);
346 return value;
347}
348
14438464
MR		 349static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
350{
351 u16 value;
352
353 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
354 if (value == IXGBE_FAILED_READ_CFG_WORD) {
355 ixgbe_remove_adapter(hw);
356 return true;
357 }
358 return false;
359}
360
361u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
362{
363 struct ixgbe_adapter *adapter = hw->back;
364 u16 value;
365
366 if (ixgbe_removed(hw->hw_addr))
367 return IXGBE_FAILED_READ_CFG_WORD;
368 pci_read_config_word(adapter->pdev, reg, &value);
369 if (value == IXGBE_FAILED_READ_CFG_WORD &&
370 ixgbe_check_cfg_remove(hw, adapter->pdev))
371 return IXGBE_FAILED_READ_CFG_WORD;
372 return value;
373}
374
375#ifdef CONFIG_PCI_IOV
376static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
377{
378 struct ixgbe_adapter *adapter = hw->back;
379 u32 value;
380
381 if (ixgbe_removed(hw->hw_addr))
382 return IXGBE_FAILED_READ_CFG_DWORD;
383 pci_read_config_dword(adapter->pdev, reg, &value);
384 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
385 ixgbe_check_cfg_remove(hw, adapter->pdev))
386 return IXGBE_FAILED_READ_CFG_DWORD;
387 return value;
388}
389#endif /* CONFIG_PCI_IOV */
390
ed19231c
JK		 391void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
392{
393 struct ixgbe_adapter *adapter = hw->back;
394
395 if (ixgbe_removed(hw->hw_addr))
396 return;
397 pci_write_config_word(adapter->pdev, reg, value);
398}
399
7086400d
AD		 400static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
401{
402 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
403
52f33af8 404 /* flush memory to make sure state is correct before next watchdog */
7086400d
AD		 405 smp_mb__before_clear_bit();
406 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
407}
408
dcd79aeb
TI		 409struct ixgbe_reg_info {
410 u32 ofs;
411 char *name;
412};
413
414static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
415
416 /* General Registers */
417 {IXGBE_CTRL, "CTRL"},
418 {IXGBE_STATUS, "STATUS"},
419 {IXGBE_CTRL_EXT, "CTRL_EXT"},
420
421 /* Interrupt Registers */
422 {IXGBE_EICR, "EICR"},
423
424 /* RX Registers */
425 {IXGBE_SRRCTL(0), "SRRCTL"},
426 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
427 {IXGBE_RDLEN(0), "RDLEN"},
428 {IXGBE_RDH(0), "RDH"},
429 {IXGBE_RDT(0), "RDT"},
430 {IXGBE_RXDCTL(0), "RXDCTL"},
431 {IXGBE_RDBAL(0), "RDBAL"},
432 {IXGBE_RDBAH(0), "RDBAH"},
433
434 /* TX Registers */
435 {IXGBE_TDBAL(0), "TDBAL"},
436 {IXGBE_TDBAH(0), "TDBAH"},
437 {IXGBE_TDLEN(0), "TDLEN"},
438 {IXGBE_TDH(0), "TDH"},
439 {IXGBE_TDT(0), "TDT"},
440 {IXGBE_TXDCTL(0), "TXDCTL"},
441
442 /* List Terminator */
443 {}
444};
445
446
447/*
448 * ixgbe_regdump - register printout routine
449 */
450static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
451{
452 int i = 0, j = 0;
453 char rname[16];
454 u32 regs[64];
455
456 switch (reginfo->ofs) {
457 case IXGBE_SRRCTL(0):
458 for (i = 0; i < 64; i++)
459 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
460 break;
461 case IXGBE_DCA_RXCTRL(0):
462 for (i = 0; i < 64; i++)
463 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
464 break;
465 case IXGBE_RDLEN(0):
466 for (i = 0; i < 64; i++)
467 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
468 break;
469 case IXGBE_RDH(0):
470 for (i = 0; i < 64; i++)
471 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
472 break;
473 case IXGBE_RDT(0):
474 for (i = 0; i < 64; i++)
475 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
476 break;
477 case IXGBE_RXDCTL(0):
478 for (i = 0; i < 64; i++)
479 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
480 break;
481 case IXGBE_RDBAL(0):
482 for (i = 0; i < 64; i++)
483 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
484 break;
485 case IXGBE_RDBAH(0):
486 for (i = 0; i < 64; i++)
487 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
488 break;
489 case IXGBE_TDBAL(0):
490 for (i = 0; i < 64; i++)
491 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
492 break;
493 case IXGBE_TDBAH(0):
494 for (i = 0; i < 64; i++)
495 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
496 break;
497 case IXGBE_TDLEN(0):
498 for (i = 0; i < 64; i++)
499 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
500 break;
501 case IXGBE_TDH(0):
502 for (i = 0; i < 64; i++)
503 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
504 break;
505 case IXGBE_TDT(0):
506 for (i = 0; i < 64; i++)
507 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
508 break;
509 case IXGBE_TXDCTL(0):
510 for (i = 0; i < 64; i++)
511 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
512 break;
513 default:
c7689578 514 pr_info("%-15s %08x\n", reginfo->name,
dcd79aeb
TI		 515 IXGBE_READ_REG(hw, reginfo->ofs));
516 return;
517 }
518
519 for (i = 0; i < 8; i++) {
520 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
c7689578 521 pr_err("%-15s", rname);
dcd79aeb 522 for (j = 0; j < 8; j++)
c7689578
JP		 523 pr_cont(" %08x", regs[i*8+j]);
524 pr_cont("\n");
dcd79aeb
TI		 525 }
526
527}
528
529/*
530 * ixgbe_dump - Print registers, tx-rings and rx-rings
531 */
532static void ixgbe_dump(struct ixgbe_adapter *adapter)
533{
534 struct net_device *netdev = adapter->netdev;
535 struct ixgbe_hw *hw = &adapter->hw;
536 struct ixgbe_reg_info *reginfo;
537 int n = 0;
538 struct ixgbe_ring *tx_ring;
729739b7 539 struct ixgbe_tx_buffer *tx_buffer;
dcd79aeb
TI		 540 union ixgbe_adv_tx_desc *tx_desc;
541 struct my_u0 { u64 a; u64 b; } *u0;
542 struct ixgbe_ring *rx_ring;
543 union ixgbe_adv_rx_desc *rx_desc;
544 struct ixgbe_rx_buffer *rx_buffer_info;
545 u32 staterr;
546 int i = 0;
547
548 if (!netif_msg_hw(adapter))
549 return;
550
551 /* Print netdevice Info */
552 if (netdev) {
553 dev_info(&adapter->pdev->dev, "Net device Info\n");
c7689578 554 pr_info("Device Name state "
dcd79aeb 555 "trans_start last_rx\n");
c7689578
JP		 556 pr_info("%-15s %016lX %016lX %016lX\n",
557 netdev->name,
558 netdev->state,
559 netdev->trans_start,
560 netdev->last_rx);
dcd79aeb
TI		 561 }
562
563 /* Print Registers */
564 dev_info(&adapter->pdev->dev, "Register Dump\n");
c7689578 565 pr_info(" Register Name Value\n");
dcd79aeb
TI		 566 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
567 reginfo->name; reginfo++) {
568 ixgbe_regdump(hw, reginfo);
569 }
570
571 /* Print TX Ring Summary */
572 if (!netdev || !netif_running(netdev))
573 goto exit;
574
575 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
8ad88e37
JH		 576 pr_info(" %s %s %s %s\n",
577 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
578 "leng", "ntw", "timestamp");
dcd79aeb
TI		 579 for (n = 0; n < adapter->num_tx_queues; n++) {
580 tx_ring = adapter->tx_ring[n];
729739b7 581 tx_buffer = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
8ad88e37 582 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
dcd79aeb 583 n, tx_ring->next_to_use, tx_ring->next_to_clean,
729739b7
AD		 584 (u64)dma_unmap_addr(tx_buffer, dma),
585 dma_unmap_len(tx_buffer, len),
586 tx_buffer->next_to_watch,
587 (u64)tx_buffer->time_stamp);
dcd79aeb
TI		 588 }
589
590 /* Print TX Rings */
591 if (!netif_msg_tx_done(adapter))
592 goto rx_ring_summary;
593
594 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
595
596 /* Transmit Descriptor Formats
597 *
39ac868a 598 * 82598 Advanced Transmit Descriptor
dcd79aeb
TI		 599 * +--------------------------------------------------------------+
600 * 0 | Buffer Address [63:0] |
601 * +--------------------------------------------------------------+
39ac868a 602 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
dcd79aeb
TI		 603 * +--------------------------------------------------------------+
604 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
39ac868a
JH		 605 *
606 * 82598 Advanced Transmit Descriptor (Write-Back Format)
607 * +--------------------------------------------------------------+
608 * 0 | RSV [63:0] |
609 * +--------------------------------------------------------------+
610 * 8 | RSV | STA | NXTSEQ |
611 * +--------------------------------------------------------------+
612 * 63 36 35 32 31 0
613 *
614 * 82599+ Advanced Transmit Descriptor
615 * +--------------------------------------------------------------+
616 * 0 | Buffer Address [63:0] |
617 * +--------------------------------------------------------------+
618 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
619 * +--------------------------------------------------------------+
620 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
621 *
622 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
623 * +--------------------------------------------------------------+
624 * 0 | RSV [63:0] |
625 * +--------------------------------------------------------------+
626 * 8 | RSV | STA | RSV |
627 * +--------------------------------------------------------------+
628 * 63 36 35 32 31 0
dcd79aeb
TI		 629 */
630
631 for (n = 0; n < adapter->num_tx_queues; n++) {
632 tx_ring = adapter->tx_ring[n];
c7689578
JP		 633 pr_info("------------------------------------\n");
634 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
635 pr_info("------------------------------------\n");
8ad88e37
JH		 636 pr_info("%s%s %s %s %s %s\n",
637 "T [desc] [address 63:0 ] ",
638 "[PlPOIdStDDt Ln] [bi->dma ] ",
639 "leng", "ntw", "timestamp", "bi->skb");
dcd79aeb
TI		 640
641 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
e4f74028 642 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 643 tx_buffer = &tx_ring->tx_buffer_info[i];
dcd79aeb 644 u0 = (struct my_u0 *)tx_desc;
8ad88e37
JH		 645 if (dma_unmap_len(tx_buffer, len) > 0) {
646 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p",
647 i,
648 le64_to_cpu(u0->a),
649 le64_to_cpu(u0->b),
650 (u64)dma_unmap_addr(tx_buffer, dma),
729739b7 651 dma_unmap_len(tx_buffer, len),
8ad88e37
JH		 652 tx_buffer->next_to_watch,
653 (u64)tx_buffer->time_stamp,
654 tx_buffer->skb);
655 if (i == tx_ring->next_to_use &&
656 i == tx_ring->next_to_clean)
657 pr_cont(" NTC/U\n");
658 else if (i == tx_ring->next_to_use)
659 pr_cont(" NTU\n");
660 else if (i == tx_ring->next_to_clean)
661 pr_cont(" NTC\n");
662 else
663 pr_cont("\n");
664
665 if (netif_msg_pktdata(adapter) &&
666 tx_buffer->skb)
667 print_hex_dump(KERN_INFO, "",
668 DUMP_PREFIX_ADDRESS, 16, 1,
669 tx_buffer->skb->data,
670 dma_unmap_len(tx_buffer, len),
671 true);
672 }
dcd79aeb
TI		 673 }
674 }
675
676 /* Print RX Rings Summary */
677rx_ring_summary:
678 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
c7689578 679 pr_info("Queue [NTU] [NTC]\n");
dcd79aeb
TI		 680 for (n = 0; n < adapter->num_rx_queues; n++) {
681 rx_ring = adapter->rx_ring[n];
c7689578
JP		 682 pr_info("%5d %5X %5X\n",
683 n, rx_ring->next_to_use, rx_ring->next_to_clean);
dcd79aeb
TI		 684 }
685
686 /* Print RX Rings */
687 if (!netif_msg_rx_status(adapter))
688 goto exit;
689
690 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
691
39ac868a
JH		 692 /* Receive Descriptor Formats
693 *
694 * 82598 Advanced Receive Descriptor (Read) Format
dcd79aeb
TI		 695 * 63 1 0
696 * +-----------------------------------------------------+
697 * 0 | Packet Buffer Address [63:1] |A0/NSE|
698 * +----------------------------------------------+------+
699 * 8 | Header Buffer Address [63:1] | DD |
700 * +-----------------------------------------------------+
701 *
702 *
39ac868a 703 * 82598 Advanced Receive Descriptor (Write-Back) Format
dcd79aeb
TI		 704 *
705 * 63 48 47 32 31 30 21 20 16 15 4 3 0
706 * +------------------------------------------------------+
39ac868a
JH		 707 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
708 * | Packet | IP | | | | Type | Type |
709 * | Checksum | Ident | | | | | |
dcd79aeb
TI		 710 * +------------------------------------------------------+
711 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
712 * +------------------------------------------------------+
713 * 63 48 47 32 31 20 19 0
39ac868a
JH		 714 *
715 * 82599+ Advanced Receive Descriptor (Read) Format
716 * 63 1 0
717 * +-----------------------------------------------------+
718 * 0 | Packet Buffer Address [63:1] |A0/NSE|
719 * +----------------------------------------------+------+
720 * 8 | Header Buffer Address [63:1] | DD |
721 * +-----------------------------------------------------+
722 *
723 *
724 * 82599+ Advanced Receive Descriptor (Write-Back) Format
725 *
726 * 63 48 47 32 31 30 21 20 17 16 4 3 0
727 * +------------------------------------------------------+
728 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
729 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
730 * |/ Flow Dir Flt ID | | | | | |
731 * +------------------------------------------------------+
732 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
733 * +------------------------------------------------------+
734 * 63 48 47 32 31 20 19 0
dcd79aeb 735 */
39ac868a 736
dcd79aeb
TI		 737 for (n = 0; n < adapter->num_rx_queues; n++) {
738 rx_ring = adapter->rx_ring[n];
c7689578
JP		 739 pr_info("------------------------------------\n");
740 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
741 pr_info("------------------------------------\n");
8ad88e37
JH		 742 pr_info("%s%s%s",
743 "R [desc] [ PktBuf A0] ",
744 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
dcd79aeb 745 "<-- Adv Rx Read format\n");
8ad88e37
JH		 746 pr_info("%s%s%s",
747 "RWB[desc] [PcsmIpSHl PtRs] ",
748 "[vl er S cks ln] ---------------- [bi->skb ] ",
dcd79aeb
TI		 749 "<-- Adv Rx Write-Back format\n");
750
751 for (i = 0; i < rx_ring->count; i++) {
752 rx_buffer_info = &rx_ring->rx_buffer_info[i];
e4f74028 753 rx_desc = IXGBE_RX_DESC(rx_ring, i);
dcd79aeb
TI		 754 u0 = (struct my_u0 *)rx_desc;
755 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
756 if (staterr & IXGBE_RXD_STAT_DD) {
757 /* Descriptor Done */
c7689578 758 pr_info("RWB[0x%03X] %016llX "
dcd79aeb
TI		 759 "%016llX ---------------- %p", i,
760 le64_to_cpu(u0->a),
761 le64_to_cpu(u0->b),
762 rx_buffer_info->skb);
763 } else {
c7689578 764 pr_info("R [0x%03X] %016llX "
dcd79aeb
TI		 765 "%016llX %016llX %p", i,
766 le64_to_cpu(u0->a),
767 le64_to_cpu(u0->b),
768 (u64)rx_buffer_info->dma,
769 rx_buffer_info->skb);
770
9c50c035
ET		 771 if (netif_msg_pktdata(adapter) &&
772 rx_buffer_info->dma) {
dcd79aeb
TI		 773 print_hex_dump(KERN_INFO, "",
774 DUMP_PREFIX_ADDRESS, 16, 1,
9c50c035
ET		 775 page_address(rx_buffer_info->page) +
776 rx_buffer_info->page_offset,
f800326d 777 ixgbe_rx_bufsz(rx_ring), true);
dcd79aeb
TI		 778 }
779 }
780
781 if (i == rx_ring->next_to_use)
c7689578 782 pr_cont(" NTU\n");
dcd79aeb 783 else if (i == rx_ring->next_to_clean)
c7689578 784 pr_cont(" NTC\n");
dcd79aeb 785 else
c7689578 786 pr_cont("\n");
dcd79aeb
TI		 787
788 }
789 }
790
791exit:
792 return;
793}
794
5eba3699
AV		 795static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
796{
797 u32 ctrl_ext;
798
799 /* Let firmware take over control of h/w */
800 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
801 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 802 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699
AV		 803}
804
805static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
806{
807 u32 ctrl_ext;
808
809 /* Let firmware know the driver has taken over */
810 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
811 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
e8e9f696 812 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
5eba3699 813}
9a799d71 814
49ce9c2c 815/**
e8e26350
PW		 816 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
817 * @adapter: pointer to adapter struct
818 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
819 * @queue: queue to map the corresponding interrupt to
820 * @msix_vector: the vector to map to the corresponding queue
821 *
822 */
823static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
e8e9f696 824 u8 queue, u8 msix_vector)
9a799d71
AK		 825{
826 u32 ivar, index;
e8e26350
PW		 827 struct ixgbe_hw *hw = &adapter->hw;
828 switch (hw->mac.type) {
829 case ixgbe_mac_82598EB:
830 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
831 if (direction == -1)
832 direction = 0;
833 index = (((direction * 64) + queue) >> 2) & 0x1F;
834 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
835 ivar &= ~(0xFF << (8 * (queue & 0x3)));
836 ivar |= (msix_vector << (8 * (queue & 0x3)));
837 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
838 break;
839 case ixgbe_mac_82599EB:
b93a2226 840 case ixgbe_mac_X540:
e8e26350
PW		 841 if (direction == -1) {
842 /* other causes */
843 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
844 index = ((queue & 1) * 8);
845 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
846 ivar &= ~(0xFF << index);
847 ivar |= (msix_vector << index);
848 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
849 break;
850 } else {
851 /* tx or rx causes */
852 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
853 index = ((16 * (queue & 1)) + (8 * direction));
854 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
855 ivar &= ~(0xFF << index);
856 ivar |= (msix_vector << index);
857 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
858 break;
859 }
860 default:
861 break;
862 }
9a799d71
AK		 863}
864
fe49f04a 865static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
e8e9f696 866 u64 qmask)
fe49f04a
AD		 867{
868 u32 mask;
869
bd508178
AD		 870 switch (adapter->hw.mac.type) {
871 case ixgbe_mac_82598EB:
fe49f04a
AD		 872 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
873 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
bd508178
AD		 874 break;
875 case ixgbe_mac_82599EB:
b93a2226 876 case ixgbe_mac_X540:
fe49f04a
AD		 877 mask = (qmask & 0xFFFFFFFF);
878 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
879 mask = (qmask >> 32);
880 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
bd508178
AD		 881 break;
882 default:
883 break;
fe49f04a
AD		 884 }
885}
886
729739b7
AD		 887void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *ring,
888 struct ixgbe_tx_buffer *tx_buffer)
9a799d71 889{
729739b7
AD		 890 if (tx_buffer->skb) {
891 dev_kfree_skb_any(tx_buffer->skb);
892 if (dma_unmap_len(tx_buffer, len))
d3d00239 893 dma_unmap_single(ring->dev,
729739b7
AD		 894 dma_unmap_addr(tx_buffer, dma),
895 dma_unmap_len(tx_buffer, len),
896 DMA_TO_DEVICE);
897 } else if (dma_unmap_len(tx_buffer, len)) {
898 dma_unmap_page(ring->dev,
899 dma_unmap_addr(tx_buffer, dma),
900 dma_unmap_len(tx_buffer, len),
901 DMA_TO_DEVICE);
e5a43549 902 }
729739b7
AD		 903 tx_buffer->next_to_watch = NULL;
904 tx_buffer->skb = NULL;
905 dma_unmap_len_set(tx_buffer, len, 0);
906 /* tx_buffer must be completely set up in the transmit path */
9a799d71
AK		 907}
908
943561d3 909static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
c84d324c
JF		 910{
911 struct ixgbe_hw *hw = &adapter->hw;
912 struct ixgbe_hw_stats *hwstats = &adapter->stats;
c84d324c 913 int i;
943561d3 914 u32 data;
c84d324c 915
943561d3
AD		 916 if ((hw->fc.current_mode != ixgbe_fc_full) &&
917 (hw->fc.current_mode != ixgbe_fc_rx_pause))
918 return;
c84d324c 919
943561d3
AD		 920 switch (hw->mac.type) {
921 case ixgbe_mac_82598EB:
922 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
923 break;
924 default:
925 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
926 }
927 hwstats->lxoffrxc += data;
c84d324c 928
943561d3
AD		 929 /* refill credits (no tx hang) if we received xoff */
930 if (!data)
c84d324c 931 return;
943561d3
AD		 932
933 for (i = 0; i < adapter->num_tx_queues; i++)
934 clear_bit(__IXGBE_HANG_CHECK_ARMED,
935 &adapter->tx_ring[i]->state);
936}
937
938static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
939{
940 struct ixgbe_hw *hw = &adapter->hw;
941 struct ixgbe_hw_stats *hwstats = &adapter->stats;
942 u32 xoff[8] = {0};
2afaa00d 943 u8 tc;
943561d3
AD		 944 int i;
945 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
946
947 if (adapter->ixgbe_ieee_pfc)
948 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
949
950 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
951 ixgbe_update_xoff_rx_lfc(adapter);
c84d324c 952 return;
943561d3 953 }
c84d324c
JF		 954
955 /* update stats for each tc, only valid with PFC enabled */
956 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
2afaa00d
PN		 957 u32 pxoffrxc;
958
c84d324c
JF		 959 switch (hw->mac.type) {
960 case ixgbe_mac_82598EB:
2afaa00d 961 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
bd508178 962 break;
c84d324c 963 default:
2afaa00d 964 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
26f23d82 965 }
2afaa00d
PN		 966 hwstats->pxoffrxc[i] += pxoffrxc;
967 /* Get the TC for given UP */
968 tc = netdev_get_prio_tc_map(adapter->netdev, i);
969 xoff[tc] += pxoffrxc;
c84d324c
JF		 970 }
971
972 /* disarm tx queues that have received xoff frames */
973 for (i = 0; i < adapter->num_tx_queues; i++) {
974 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
c84d324c 975
2afaa00d 976 tc = tx_ring->dcb_tc;
c84d324c
JF		 977 if (xoff[tc])
978 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
26f23d82 979 }
26f23d82
YZ		 980}
981
c84d324c 982static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
9a799d71 983{
7d7ce682 984 return ring->stats.packets;
c84d324c
JF		 985}
986
987static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
988{
2a47fa45
JF		 989 struct ixgbe_adapter *adapter;
990 struct ixgbe_hw *hw;
991 u32 head, tail;
992
993 if (ring->l2_accel_priv)
994 adapter = ring->l2_accel_priv->real_adapter;
995 else
996 adapter = netdev_priv(ring->netdev);
e01c31a5 997
2a47fa45
JF		 998 hw = &adapter->hw;
999 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
1000 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
c84d324c
JF		 1001
1002 if (head != tail)
1003 return (head < tail) ?
1004 tail - head : (tail + ring->count - head);
1005
1006 return 0;
1007}
1008
1009static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1010{
1011 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1012 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1013 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1014 bool ret = false;
1015
7d637bcc 1016 clear_check_for_tx_hang(tx_ring);
c84d324c
JF		 1017
1018 /*
1019 * Check for a hung queue, but be thorough. This verifies
1020 * that a transmit has been completed since the previous
1021 * check AND there is at least one packet pending. The
1022 * ARMED bit is set to indicate a potential hang. The
1023 * bit is cleared if a pause frame is received to remove
1024 * false hang detection due to PFC or 802.3x frames. By
1025 * requiring this to fail twice we avoid races with
1026 * pfc clearing the ARMED bit and conditions where we
1027 * run the check_tx_hang logic with a transmit completion
1028 * pending but without time to complete it yet.
1029 */
1030 if ((tx_done_old == tx_done) && tx_pending) {
1031 /* make sure it is true for two checks in a row */
1032 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1033 &tx_ring->state);
1034 } else {
1035 /* update completed stats and continue */
1036 tx_ring->tx_stats.tx_done_old = tx_done;
1037 /* reset the countdown */
1038 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
9a799d71
AK		 1039 }
1040
c84d324c 1041 return ret;
9a799d71
AK		 1042}
1043
c83c6cbd
AD		 1044/**
1045 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1046 * @adapter: driver private struct
1047 **/
1048static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1049{
1050
1051 /* Do the reset outside of interrupt context */
1052 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1053 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
12ff3f3b 1054 e_warn(drv, "initiating reset due to tx timeout\n");
c83c6cbd
AD		 1055 ixgbe_service_event_schedule(adapter);
1056 }
1057}
e01c31a5 1058
9a799d71
AK		 1059/**
1060 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
fe49f04a 1061 * @q_vector: structure containing interrupt and ring information
e01c31a5 1062 * @tx_ring: tx ring to clean
9a799d71 1063 **/
fe49f04a 1064static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 1065 struct ixgbe_ring *tx_ring)
9a799d71 1066{
fe49f04a 1067 struct ixgbe_adapter *adapter = q_vector->adapter;
d3d00239
AD		 1068 struct ixgbe_tx_buffer *tx_buffer;
1069 union ixgbe_adv_tx_desc *tx_desc;
e01c31a5 1070 unsigned int total_bytes = 0, total_packets = 0;
59224555 1071 unsigned int budget = q_vector->tx.work_limit;
729739b7
AD		 1072 unsigned int i = tx_ring->next_to_clean;
1073
1074 if (test_bit(__IXGBE_DOWN, &adapter->state))
1075 return true;
9a799d71 1076
d3d00239 1077 tx_buffer = &tx_ring->tx_buffer_info[i];
e4f74028 1078 tx_desc = IXGBE_TX_DESC(tx_ring, i);
729739b7 1079 i -= tx_ring->count;
12207e49 1080
729739b7 1081 do {
d3d00239
AD		 1082 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1083
1084 /* if next_to_watch is not set then there is no work pending */
1085 if (!eop_desc)
1086 break;
1087
7f83a9e6 1088 /* prevent any other reads prior to eop_desc */
7e63bf49 1089 read_barrier_depends();
7f83a9e6 1090
d3d00239
AD		 1091 /* if DD is not set pending work has not been completed */
1092 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1093 break;
8ad494b0 1094
d3d00239
AD		 1095 /* clear next_to_watch to prevent false hangs */
1096 tx_buffer->next_to_watch = NULL;
8ad494b0 1097
091a6246
AD		 1098 /* update the statistics for this packet */
1099 total_bytes += tx_buffer->bytecount;
1100 total_packets += tx_buffer->gso_segs;
1101
fd0db0ed
AD		 1102 /* free the skb */
1103 dev_kfree_skb_any(tx_buffer->skb);
1104
729739b7
AD		 1105 /* unmap skb header data */
1106 dma_unmap_single(tx_ring->dev,
1107 dma_unmap_addr(tx_buffer, dma),
1108 dma_unmap_len(tx_buffer, len),
1109 DMA_TO_DEVICE);
1110
fd0db0ed
AD		 1111 /* clear tx_buffer data */
1112 tx_buffer->skb = NULL;
729739b7 1113 dma_unmap_len_set(tx_buffer, len, 0);
fd0db0ed 1114
729739b7
AD		 1115 /* unmap remaining buffers */
1116 while (tx_desc != eop_desc) {
d3d00239
AD		 1117 tx_buffer++;
1118 tx_desc++;
8ad494b0 1119 i++;
729739b7
AD		 1120 if (unlikely(!i)) {
1121 i -= tx_ring->count;
d3d00239 1122 tx_buffer = tx_ring->tx_buffer_info;
e4f74028 1123 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
e092be60 1124 }
e01c31a5 1125
729739b7
AD		 1126 /* unmap any remaining paged data */
1127 if (dma_unmap_len(tx_buffer, len)) {
1128 dma_unmap_page(tx_ring->dev,
1129 dma_unmap_addr(tx_buffer, dma),
1130 dma_unmap_len(tx_buffer, len),
1131 DMA_TO_DEVICE);
1132 dma_unmap_len_set(tx_buffer, len, 0);
1133 }
1134 }
1135
1136 /* move us one more past the eop_desc for start of next pkt */
1137 tx_buffer++;
1138 tx_desc++;
1139 i++;
1140 if (unlikely(!i)) {
1141 i -= tx_ring->count;
1142 tx_buffer = tx_ring->tx_buffer_info;
1143 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1144 }
1145
1146 /* issue prefetch for next Tx descriptor */
1147 prefetch(tx_desc);
12207e49 1148
729739b7
AD		 1149 /* update budget accounting */
1150 budget--;
1151 } while (likely(budget));
1152
1153 i += tx_ring->count;
9a799d71 1154 tx_ring->next_to_clean = i;
d3d00239 1155 u64_stats_update_begin(&tx_ring->syncp);
b953799e 1156 tx_ring->stats.bytes += total_bytes;
bd198058 1157 tx_ring->stats.packets += total_packets;
d3d00239 1158 u64_stats_update_end(&tx_ring->syncp);
bd198058
AD		 1159 q_vector->tx.total_bytes += total_bytes;
1160 q_vector->tx.total_packets += total_packets;
b953799e 1161
c84d324c
JF		 1162 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1163 /* schedule immediate reset if we believe we hung */
1164 struct ixgbe_hw *hw = &adapter->hw;
c84d324c
JF		 1165 e_err(drv, "Detected Tx Unit Hang\n"
1166 " Tx Queue <%d>\n"
1167 " TDH, TDT <%x>, <%x>\n"
1168 " next_to_use <%x>\n"
1169 " next_to_clean <%x>\n"
1170 "tx_buffer_info[next_to_clean]\n"
1171 " time_stamp <%lx>\n"
1172 " jiffies <%lx>\n",
1173 tx_ring->queue_index,
1174 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1175 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
d3d00239
AD		 1176 tx_ring->next_to_use, i,
1177 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
c84d324c
JF		 1178
1179 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1180
1181 e_info(probe,
1182 "tx hang %d detected on queue %d, resetting adapter\n",
1183 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1184
b953799e 1185 /* schedule immediate reset if we believe we hung */
c83c6cbd 1186 ixgbe_tx_timeout_reset(adapter);
b953799e
AD		 1187
1188 /* the adapter is about to reset, no point in enabling stuff */
59224555 1189 return true;
b953799e 1190 }
9a799d71 1191
b2d96e0a
AD		 1192 netdev_tx_completed_queue(txring_txq(tx_ring),
1193 total_packets, total_bytes);
1194
e092be60 1195#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
30065e63 1196 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
7d4987de 1197 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
e092be60
AV		 1198 /* Make sure that anybody stopping the queue after this
1199 * sees the new next_to_clean.
1200 */
1201 smp_mb();
729739b7
AD		 1202 if (__netif_subqueue_stopped(tx_ring->netdev,
1203 tx_ring->queue_index)
1204 && !test_bit(__IXGBE_DOWN, &adapter->state)) {
1205 netif_wake_subqueue(tx_ring->netdev,
1206 tx_ring->queue_index);
5b7da515 1207 ++tx_ring->tx_stats.restart_queue;
30eba97a 1208 }
e092be60 1209 }
9a799d71 1210
59224555 1211 return !!budget;
9a799d71
AK		 1212}
1213
5dd2d332 1214#ifdef CONFIG_IXGBE_DCA
bdda1a61
AD		 1215static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1216 struct ixgbe_ring *tx_ring,
33cf09c9 1217 int cpu)
bd0362dd 1218{
33cf09c9 1219 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1220 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1221 u16 reg_offset;
33cf09c9 1222
33cf09c9
AD		 1223 switch (hw->mac.type) {
1224 case ixgbe_mac_82598EB:
bdda1a61 1225 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
33cf09c9
AD		 1226 break;
1227 case ixgbe_mac_82599EB:
b93a2226 1228 case ixgbe_mac_X540:
bdda1a61
AD		 1229 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1230 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1231 break;
1232 default:
bdda1a61
AD		 1233 /* for unknown hardware do not write register */
1234 return;
bd0362dd 1235 }
bdda1a61
AD		 1236
1237 /*
1238 * We can enable relaxed ordering for reads, but not writes when
1239 * DCA is enabled. This is due to a known issue in some chipsets
1240 * which will cause the DCA tag to be cleared.
1241 */
1242 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1243 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1244 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1245
1246 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
bd0362dd
JC		 1247}
1248
bdda1a61
AD		 1249static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1250 struct ixgbe_ring *rx_ring,
33cf09c9 1251 int cpu)
bd0362dd 1252{
33cf09c9 1253 struct ixgbe_hw *hw = &adapter->hw;
bdda1a61
AD		 1254 u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1255 u8 reg_idx = rx_ring->reg_idx;
1256
33cf09c9
AD		 1257
1258 switch (hw->mac.type) {
33cf09c9 1259 case ixgbe_mac_82599EB:
b93a2226 1260 case ixgbe_mac_X540:
bdda1a61 1261 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
33cf09c9
AD		 1262 break;
1263 default:
1264 break;
1265 }
bdda1a61
AD		 1266
1267 /*
1268 * We can enable relaxed ordering for reads, but not writes when
1269 * DCA is enabled. This is due to a known issue in some chipsets
1270 * which will cause the DCA tag to be cleared.
1271 */
1272 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
bdda1a61
AD		 1273 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1274
1275 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
33cf09c9
AD		 1276}
1277
1278static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1279{
1280 struct ixgbe_adapter *adapter = q_vector->adapter;
efe3d3c8 1281 struct ixgbe_ring *ring;
bd0362dd 1282 int cpu = get_cpu();
bd0362dd 1283
33cf09c9
AD		 1284 if (q_vector->cpu == cpu)
1285 goto out_no_update;
1286
a557928e 1287 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8 1288 ixgbe_update_tx_dca(adapter, ring, cpu);
33cf09c9 1289
a557928e 1290 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8 1291 ixgbe_update_rx_dca(adapter, ring, cpu);
33cf09c9
AD		 1292
1293 q_vector->cpu = cpu;
1294out_no_update:
bd0362dd
JC		 1295 put_cpu();
1296}
1297
1298static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1299{
1300 int i;
1301
1302 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1303 return;
1304
e35ec126
AD		 1305 /* always use CB2 mode, difference is masked in the CB driver */
1306 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1307
49c7ffbe 1308 for (i = 0; i < adapter->num_q_vectors; i++) {
33cf09c9
AD		 1309 adapter->q_vector[i]->cpu = -1;
1310 ixgbe_update_dca(adapter->q_vector[i]);
bd0362dd
JC		 1311 }
1312}
1313
1314static int __ixgbe_notify_dca(struct device *dev, void *data)
1315{
c60fbb00 1316 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
bd0362dd
JC		 1317 unsigned long event = *(unsigned long *)data;
1318
2a72c31e 1319 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
33cf09c9
AD		 1320 return 0;
1321
bd0362dd
JC		 1322 switch (event) {
1323 case DCA_PROVIDER_ADD:
96b0e0f6
JB		 1324 /* if we're already enabled, don't do it again */
1325 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1326 break;
652f093f 1327 if (dca_add_requester(dev) == 0) {
96b0e0f6 1328 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 1329 ixgbe_setup_dca(adapter);
1330 break;
1331 }
1332 /* Fall Through since DCA is disabled. */
1333 case DCA_PROVIDER_REMOVE:
1334 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1335 dca_remove_requester(dev);
1336 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1337 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1338 }
1339 break;
1340 }
1341
652f093f 1342 return 0;
bd0362dd 1343}
67a74ee2 1344
bdda1a61 1345#endif /* CONFIG_IXGBE_DCA */
8a0da21b
AD		 1346static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1347 union ixgbe_adv_rx_desc *rx_desc,
67a74ee2
ET		 1348 struct sk_buff *skb)
1349{
8a0da21b 1350 if (ring->netdev->features & NETIF_F_RXHASH)
38da9853
TH		 1351 skb_set_hash(skb,
1352 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1353 PKT_HASH_TYPE_L3);
67a74ee2
ET		 1354}
1355
f800326d 1356#ifdef IXGBE_FCOE
ff886dfc
AD		 1357/**
1358 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
57efd44c 1359 * @ring: structure containing ring specific data
ff886dfc
AD		 1360 * @rx_desc: advanced rx descriptor
1361 *
1362 * Returns : true if it is FCoE pkt
1363 */
57efd44c 1364static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
ff886dfc
AD		 1365 union ixgbe_adv_rx_desc *rx_desc)
1366{
1367 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1368
57efd44c 1369 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
ff886dfc
AD		 1370 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1371 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1372 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1373}
1374
f800326d 1375#endif /* IXGBE_FCOE */
e59bd25d
AV		 1376/**
1377 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
8a0da21b
AD		 1378 * @ring: structure containing ring specific data
1379 * @rx_desc: current Rx descriptor being processed
e59bd25d
AV		 1380 * @skb: skb currently being received and modified
1381 **/
8a0da21b 1382static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
8bae1b2b 1383 union ixgbe_adv_rx_desc *rx_desc,
f56e0cb1 1384 struct sk_buff *skb)
9a799d71 1385{
8a0da21b 1386 skb_checksum_none_assert(skb);
9a799d71 1387
712744be 1388 /* Rx csum disabled */
8a0da21b 1389 if (!(ring->netdev->features & NETIF_F_RXCSUM))
9a799d71 1390 return;
e59bd25d
AV		 1391
1392 /* if IP and error */
f56e0cb1
AD		 1393 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1394 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
8a0da21b 1395 ring->rx_stats.csum_err++;
9a799d71
AK		 1396 return;
1397 }
e59bd25d 1398
f56e0cb1 1399 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
e59bd25d
AV		 1400 return;
1401
f56e0cb1 1402 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
f800326d 1403 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
8bae1b2b
DS		 1404
1405 /*
1406 * 82599 errata, UDP frames with a 0 checksum can be marked as
1407 * checksum errors.
1408 */
8a0da21b
AD		 1409 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1410 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
8bae1b2b
DS		 1411 return;
1412
8a0da21b 1413 ring->rx_stats.csum_err++;
e59bd25d
AV		 1414 return;
1415 }
1416
9a799d71 1417 /* It must be a TCP or UDP packet with a valid checksum */
e59bd25d 1418 skb->ip_summed = CHECKSUM_UNNECESSARY;
9a799d71
AK		 1419}
1420
84ea2591 1421static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
e8e26350 1422{
f56e0cb1 1423 rx_ring->next_to_use = val;
f800326d
AD		 1424
1425 /* update next to alloc since we have filled the ring */
1426 rx_ring->next_to_alloc = val;
e8e26350
PW		 1427 /*
1428 * Force memory writes to complete before letting h/w
1429 * know there are new descriptors to fetch. (Only
1430 * applicable for weak-ordered memory model archs,
1431 * such as IA-64).
1432 */
1433 wmb();
84227bcd 1434 ixgbe_write_tail(rx_ring, val);
e8e26350
PW		 1435}
1436
f990b79b
AD		 1437static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1438 struct ixgbe_rx_buffer *bi)
1439{
1440 struct page *page = bi->page;
f800326d 1441 dma_addr_t dma = bi->dma;
f990b79b 1442
f800326d
AD		 1443 /* since we are recycling buffers we should seldom need to alloc */
1444 if (likely(dma))
f990b79b
AD		 1445 return true;
1446
f800326d
AD		 1447 /* alloc new page for storage */
1448 if (likely(!page)) {
0614002b
MG		 1449 page = __skb_alloc_pages(GFP_ATOMIC | __GFP_COLD | __GFP_COMP,
1450 bi->skb, ixgbe_rx_pg_order(rx_ring));
f990b79b
AD		 1451 if (unlikely(!page)) {
1452 rx_ring->rx_stats.alloc_rx_page_failed++;
1453 return false;
1454 }
f800326d 1455 bi->page = page;
f990b79b
AD		 1456 }
1457
f800326d
AD		 1458 /* map page for use */
1459 dma = dma_map_page(rx_ring->dev, page, 0,
1460 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1461
1462 /*
1463 * if mapping failed free memory back to system since
1464 * there isn't much point in holding memory we can't use
1465 */
1466 if (dma_mapping_error(rx_ring->dev, dma)) {
dd411ec4 1467 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
f800326d 1468 bi->page = NULL;
f990b79b 1469
f990b79b
AD		 1470 rx_ring->rx_stats.alloc_rx_page_failed++;
1471 return false;
1472 }
1473
f800326d 1474 bi->dma = dma;
afaa9459 1475 bi->page_offset = 0;
f800326d 1476
f990b79b
AD		 1477 return true;
1478}
1479
9a799d71 1480/**
f990b79b 1481 * ixgbe_alloc_rx_buffers - Replace used receive buffers
fc77dc3c
AD		 1482 * @rx_ring: ring to place buffers on
1483 * @cleaned_count: number of buffers to replace
9a799d71 1484 **/
fc77dc3c 1485void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
9a799d71 1486{
9a799d71 1487 union ixgbe_adv_rx_desc *rx_desc;
3a581073 1488 struct ixgbe_rx_buffer *bi;
d5f398ed 1489 u16 i = rx_ring->next_to_use;
9a799d71 1490
f800326d
AD		 1491 /* nothing to do */
1492 if (!cleaned_count)
fc77dc3c
AD		 1493 return;
1494
e4f74028 1495 rx_desc = IXGBE_RX_DESC(rx_ring, i);
f990b79b
AD		 1496 bi = &rx_ring->rx_buffer_info[i];
1497 i -= rx_ring->count;
9a799d71 1498
f800326d
AD		 1499 do {
1500 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
f990b79b 1501 break;
d5f398ed 1502
f800326d
AD		 1503 /*
1504 * Refresh the desc even if buffer_addrs didn't change
1505 * because each write-back erases this info.
1506 */
1507 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
9a799d71 1508
f990b79b
AD		 1509 rx_desc++;
1510 bi++;
9a799d71 1511 i++;
f990b79b 1512 if (unlikely(!i)) {
e4f74028 1513 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
f990b79b
AD		 1514 bi = rx_ring->rx_buffer_info;
1515 i -= rx_ring->count;
1516 }
1517
1518 /* clear the hdr_addr for the next_to_use descriptor */
1519 rx_desc->read.hdr_addr = 0;
f800326d
AD		 1520
1521 cleaned_count--;
1522 } while (cleaned_count);
7c6e0a43 1523
f990b79b
AD		 1524 i += rx_ring->count;
1525
f56e0cb1 1526 if (rx_ring->next_to_use != i)
84ea2591 1527 ixgbe_release_rx_desc(rx_ring, i);
9a799d71
AK		 1528}
1529
1d2024f6
AD		 1530/**
1531 * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
1532 * @data: pointer to the start of the headers
1533 * @max_len: total length of section to find headers in
1534 *
1535 * This function is meant to determine the length of headers that will
1536 * be recognized by hardware for LRO, GRO, and RSC offloads. The main
1537 * motivation of doing this is to only perform one pull for IPv4 TCP
1538 * packets so that we can do basic things like calculating the gso_size
1539 * based on the average data per packet.
1540 **/
1541static unsigned int ixgbe_get_headlen(unsigned char *data,
1542 unsigned int max_len)
1543{
1544 union {
1545 unsigned char *network;
1546 /* l2 headers */
1547 struct ethhdr *eth;
1548 struct vlan_hdr *vlan;
1549 /* l3 headers */
1550 struct iphdr *ipv4;
a048b40e 1551 struct ipv6hdr *ipv6;
1d2024f6
AD		 1552 } hdr;
1553 __be16 protocol;
1554 u8 nexthdr = 0; /* default to not TCP */
1555 u8 hlen;
1556
1557 /* this should never happen, but better safe than sorry */
1558 if (max_len < ETH_HLEN)
1559 return max_len;
1560
1561 /* initialize network frame pointer */
1562 hdr.network = data;
1563
1564 /* set first protocol and move network header forward */
1565 protocol = hdr.eth->h_proto;
1566 hdr.network += ETH_HLEN;
1567
1568 /* handle any vlan tag if present */
a1108ffd 1569 if (protocol == htons(ETH_P_8021Q)) {
1d2024f6
AD		 1570 if ((hdr.network - data) > (max_len - VLAN_HLEN))
1571 return max_len;
1572
1573 protocol = hdr.vlan->h_vlan_encapsulated_proto;
1574 hdr.network += VLAN_HLEN;
1575 }
1576
1577 /* handle L3 protocols */
a1108ffd 1578 if (protocol == htons(ETH_P_IP)) {
1d2024f6
AD		 1579 if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
1580 return max_len;
1581
1582 /* access ihl as a u8 to avoid unaligned access on ia64 */
1583 hlen = (hdr.network[0] & 0x0F) << 2;
1584
1585 /* verify hlen meets minimum size requirements */
1586 if (hlen < sizeof(struct iphdr))
1587 return hdr.network - data;
1588
ed83da12 1589 /* record next protocol if header is present */
20967f42 1590 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
ed83da12 1591 nexthdr = hdr.ipv4->protocol;
a1108ffd 1592 } else if (protocol == htons(ETH_P_IPV6)) {
a048b40e
AD		 1593 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
1594 return max_len;
1595
1596 /* record next protocol */
1597 nexthdr = hdr.ipv6->nexthdr;
ed83da12 1598 hlen = sizeof(struct ipv6hdr);
f800326d 1599#ifdef IXGBE_FCOE
a1108ffd 1600 } else if (protocol == htons(ETH_P_FCOE)) {
1d2024f6
AD		 1601 if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
1602 return max_len;
ed83da12 1603 hlen = FCOE_HEADER_LEN;
1d2024f6
AD		 1604#endif
1605 } else {
1606 return hdr.network - data;
1607 }
1608
ed83da12
AD		 1609 /* relocate pointer to start of L4 header */
1610 hdr.network += hlen;
1611
a048b40e 1612 /* finally sort out TCP/UDP */
1d2024f6
AD		 1613 if (nexthdr == IPPROTO_TCP) {
1614 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
1615 return max_len;
1616
1617 /* access doff as a u8 to avoid unaligned access on ia64 */
1618 hlen = (hdr.network[12] & 0xF0) >> 2;
1619
1620 /* verify hlen meets minimum size requirements */
1621 if (hlen < sizeof(struct tcphdr))
1622 return hdr.network - data;
1623
1624 hdr.network += hlen;
a048b40e
AD		 1625 } else if (nexthdr == IPPROTO_UDP) {
1626 if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
1627 return max_len;
1628
1629 hdr.network += sizeof(struct udphdr);
1d2024f6
AD		 1630 }
1631
1632 /*
1633 * If everything has gone correctly hdr.network should be the
1634 * data section of the packet and will be the end of the header.
1635 * If not then it probably represents the end of the last recognized
1636 * header.
1637 */
1638 if ((hdr.network - data) < max_len)
1639 return hdr.network - data;
1640 else
1641 return max_len;
1642}
1643
1d2024f6
AD		 1644static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1645 struct sk_buff *skb)
1646{
f800326d 1647 u16 hdr_len = skb_headlen(skb);
1d2024f6
AD		 1648
1649 /* set gso_size to avoid messing up TCP MSS */
1650 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1651 IXGBE_CB(skb)->append_cnt);
96be80ab 1652 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1d2024f6
AD		 1653}
1654
1655static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1656 struct sk_buff *skb)
1657{
1658 /* if append_cnt is 0 then frame is not RSC */
1659 if (!IXGBE_CB(skb)->append_cnt)
1660 return;
1661
1662 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1663 rx_ring->rx_stats.rsc_flush++;
1664
1665 ixgbe_set_rsc_gso_size(rx_ring, skb);
1666
1667 /* gso_size is computed using append_cnt so always clear it last */
1668 IXGBE_CB(skb)->append_cnt = 0;
1669}
1670
8a0da21b
AD		 1671/**
1672 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1673 * @rx_ring: rx descriptor ring packet is being transacted on
1674 * @rx_desc: pointer to the EOP Rx descriptor
1675 * @skb: pointer to current skb being populated
f8212f97 1676 *
8a0da21b
AD		 1677 * This function checks the ring, descriptor, and packet information in
1678 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1679 * other fields within the skb.
f8212f97 1680 **/
8a0da21b
AD		 1681static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1682 union ixgbe_adv_rx_desc *rx_desc,
1683 struct sk_buff *skb)
f8212f97 1684{
43e95f11
JF		 1685 struct net_device *dev = rx_ring->netdev;
1686
8a0da21b
AD		 1687 ixgbe_update_rsc_stats(rx_ring, skb);
1688
1689 ixgbe_rx_hash(rx_ring, rx_desc, skb);
f8212f97 1690
8a0da21b
AD		 1691 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1692
6cb562d6 1693 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
3a6a4eda 1694
f646968f 1695 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
43e95f11 1696 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
8a0da21b 1697 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
86a9bad3 1698 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
f8212f97
AD		 1699 }
1700
8a0da21b 1701 skb_record_rx_queue(skb, rx_ring->queue_index);
aa80175a 1702
43e95f11 1703 skb->protocol = eth_type_trans(skb, dev);
f8212f97
AD		 1704}
1705
8a0da21b
AD		 1706static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1707 struct sk_buff *skb)
aa80175a 1708{
8a0da21b
AD		 1709 struct ixgbe_adapter *adapter = q_vector->adapter;
1710
b4640030 1711 if (ixgbe_qv_busy_polling(q_vector))
5a85e737
ET		 1712 netif_receive_skb(skb);
1713 else if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
8a0da21b
AD		 1714 napi_gro_receive(&q_vector->napi, skb);
1715 else
1716 netif_rx(skb);
aa80175a 1717}
43634e82 1718
f800326d
AD		 1719/**
1720 * ixgbe_is_non_eop - process handling of non-EOP buffers
1721 * @rx_ring: Rx ring being processed
1722 * @rx_desc: Rx descriptor for current buffer
1723 * @skb: Current socket buffer containing buffer in progress
1724 *
1725 * This function updates next to clean. If the buffer is an EOP buffer
1726 * this function exits returning false, otherwise it will place the
1727 * sk_buff in the next buffer to be chained and return true indicating
1728 * that this is in fact a non-EOP buffer.
1729 **/
1730static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1731 union ixgbe_adv_rx_desc *rx_desc,
1732 struct sk_buff *skb)
1733{
1734 u32 ntc = rx_ring->next_to_clean + 1;
1735
1736 /* fetch, update, and store next to clean */
1737 ntc = (ntc < rx_ring->count) ? ntc : 0;
1738 rx_ring->next_to_clean = ntc;
1739
1740 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1741
5a02cbd1
AD		 1742 /* update RSC append count if present */
1743 if (ring_is_rsc_enabled(rx_ring)) {
1744 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1745 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1746
1747 if (unlikely(rsc_enabled)) {
1748 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1749
1750 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1751 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
f800326d 1752
5a02cbd1
AD		 1753 /* update ntc based on RSC value */
1754 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1755 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1756 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1757 }
f800326d
AD		 1758 }
1759
5a02cbd1
AD		 1760 /* if we are the last buffer then there is nothing else to do */
1761 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1762 return false;
1763
f800326d
AD		 1764 /* place skb in next buffer to be received */
1765 rx_ring->rx_buffer_info[ntc].skb = skb;
1766 rx_ring->rx_stats.non_eop_descs++;
1767
1768 return true;
1769}
1770
19861ce2
AD		 1771/**
1772 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1773 * @rx_ring: rx descriptor ring packet is being transacted on
1774 * @skb: pointer to current skb being adjusted
1775 *
1776 * This function is an ixgbe specific version of __pskb_pull_tail. The
1777 * main difference between this version and the original function is that
1778 * this function can make several assumptions about the state of things
1779 * that allow for significant optimizations versus the standard function.
1780 * As a result we can do things like drop a frag and maintain an accurate
1781 * truesize for the skb.
1782 */
1783static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1784 struct sk_buff *skb)
1785{
1786 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1787 unsigned char *va;
1788 unsigned int pull_len;
1789
1790 /*
1791 * it is valid to use page_address instead of kmap since we are
1792 * working with pages allocated out of the lomem pool per
1793 * alloc_page(GFP_ATOMIC)
1794 */
1795 va = skb_frag_address(frag);
1796
1797 /*
1798 * we need the header to contain the greater of either ETH_HLEN or
1799 * 60 bytes if the skb->len is less than 60 for skb_pad.
1800 */
cf3fe7ac 1801 pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
19861ce2
AD		 1802
1803 /* align pull length to size of long to optimize memcpy performance */
1804 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1805
1806 /* update all of the pointers */
1807 skb_frag_size_sub(frag, pull_len);
1808 frag->page_offset += pull_len;
1809 skb->data_len -= pull_len;
1810 skb->tail += pull_len;
19861ce2
AD		 1811}
1812
42073d91
AD		 1813/**
1814 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1815 * @rx_ring: rx descriptor ring packet is being transacted on
1816 * @skb: pointer to current skb being updated
1817 *
1818 * This function provides a basic DMA sync up for the first fragment of an
1819 * skb. The reason for doing this is that the first fragment cannot be
1820 * unmapped until we have reached the end of packet descriptor for a buffer
1821 * chain.
1822 */
1823static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1824 struct sk_buff *skb)
1825{
1826 /* if the page was released unmap it, else just sync our portion */
1827 if (unlikely(IXGBE_CB(skb)->page_released)) {
1828 dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma,
1829 ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE);
1830 IXGBE_CB(skb)->page_released = false;
1831 } else {
1832 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1833
1834 dma_sync_single_range_for_cpu(rx_ring->dev,
1835 IXGBE_CB(skb)->dma,
1836 frag->page_offset,
1837 ixgbe_rx_bufsz(rx_ring),
1838 DMA_FROM_DEVICE);
1839 }
1840 IXGBE_CB(skb)->dma = 0;
1841}
1842
f800326d
AD		 1843/**
1844 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1845 * @rx_ring: rx descriptor ring packet is being transacted on
1846 * @rx_desc: pointer to the EOP Rx descriptor
1847 * @skb: pointer to current skb being fixed
1848 *
1849 * Check for corrupted packet headers caused by senders on the local L2
1850 * embedded NIC switch not setting up their Tx Descriptors right. These
1851 * should be very rare.
1852 *
1853 * Also address the case where we are pulling data in on pages only
1854 * and as such no data is present in the skb header.
1855 *
1856 * In addition if skb is not at least 60 bytes we need to pad it so that
1857 * it is large enough to qualify as a valid Ethernet frame.
1858 *
1859 * Returns true if an error was encountered and skb was freed.
1860 **/
1861static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1862 union ixgbe_adv_rx_desc *rx_desc,
1863 struct sk_buff *skb)
1864{
f800326d 1865 struct net_device *netdev = rx_ring->netdev;
f800326d
AD		 1866
1867 /* verify that the packet does not have any known errors */
1868 if (unlikely(ixgbe_test_staterr(rx_desc,
1869 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1870 !(netdev->features & NETIF_F_RXALL))) {
1871 dev_kfree_skb_any(skb);
1872 return true;
1873 }
1874
19861ce2 1875 /* place header in linear portion of buffer */
cf3fe7ac
AD		 1876 if (skb_is_nonlinear(skb))
1877 ixgbe_pull_tail(rx_ring, skb);
f800326d 1878
57efd44c
AD		 1879#ifdef IXGBE_FCOE
1880 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1881 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1882 return false;
1883
1884#endif
f800326d
AD		 1885 /* if skb_pad returns an error the skb was freed */
1886 if (unlikely(skb->len < 60)) {
1887 int pad_len = 60 - skb->len;
1888
1889 if (skb_pad(skb, pad_len))
1890 return true;
1891 __skb_put(skb, pad_len);
1892 }
1893
1894 return false;
1895}
1896
f800326d
AD		 1897/**
1898 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1899 * @rx_ring: rx descriptor ring to store buffers on
1900 * @old_buff: donor buffer to have page reused
1901 *
0549ae20 1902 * Synchronizes page for reuse by the adapter
f800326d
AD		 1903 **/
1904static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1905 struct ixgbe_rx_buffer *old_buff)
1906{
1907 struct ixgbe_rx_buffer *new_buff;
1908 u16 nta = rx_ring->next_to_alloc;
f800326d
AD		 1909
1910 new_buff = &rx_ring->rx_buffer_info[nta];
1911
1912 /* update, and store next to alloc */
1913 nta++;
1914 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1915
1916 /* transfer page from old buffer to new buffer */
1917 new_buff->page = old_buff->page;
1918 new_buff->dma = old_buff->dma;
0549ae20 1919 new_buff->page_offset = old_buff->page_offset;
f800326d
AD		 1920
1921 /* sync the buffer for use by the device */
1922 dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma,
0549ae20
AD		 1923 new_buff->page_offset,
1924 ixgbe_rx_bufsz(rx_ring),
f800326d 1925 DMA_FROM_DEVICE);
f800326d
AD		 1926}
1927
1928/**
1929 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
1930 * @rx_ring: rx descriptor ring to transact packets on
1931 * @rx_buffer: buffer containing page to add
1932 * @rx_desc: descriptor containing length of buffer written by hardware
1933 * @skb: sk_buff to place the data into
1934 *
0549ae20
AD		 1935 * This function will add the data contained in rx_buffer->page to the skb.
1936 * This is done either through a direct copy if the data in the buffer is
1937 * less than the skb header size, otherwise it will just attach the page as
1938 * a frag to the skb.
1939 *
1940 * The function will then update the page offset if necessary and return
1941 * true if the buffer can be reused by the adapter.
f800326d 1942 **/
0549ae20 1943static bool ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
f800326d 1944 struct ixgbe_rx_buffer *rx_buffer,
0549ae20
AD		 1945 union ixgbe_adv_rx_desc *rx_desc,
1946 struct sk_buff *skb)
f800326d 1947{
0549ae20
AD		 1948 struct page *page = rx_buffer->page;
1949 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length);
09816fbe 1950#if (PAGE_SIZE < 8192)
0549ae20 1951 unsigned int truesize = ixgbe_rx_bufsz(rx_ring);
09816fbe
AD		 1952#else
1953 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1954 unsigned int last_offset = ixgbe_rx_pg_size(rx_ring) -
1955 ixgbe_rx_bufsz(rx_ring);
1956#endif
0549ae20 1957
cf3fe7ac
AD		 1958 if ((size <= IXGBE_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1959 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1960
1961 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1962
1963 /* we can reuse buffer as-is, just make sure it is local */
1964 if (likely(page_to_nid(page) == numa_node_id()))
1965 return true;
1966
1967 /* this page cannot be reused so discard it */
1968 put_page(page);
1969 return false;
1970 }
1971
0549ae20
AD		 1972 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1973 rx_buffer->page_offset, size, truesize);
1974
09816fbe
AD		 1975 /* avoid re-using remote pages */
1976 if (unlikely(page_to_nid(page) != numa_node_id()))
1977 return false;
1978
1979#if (PAGE_SIZE < 8192)
1980 /* if we are only owner of page we can reuse it */
1981 if (unlikely(page_count(page) != 1))
0549ae20
AD		 1982 return false;
1983
1984 /* flip page offset to other buffer */
1985 rx_buffer->page_offset ^= truesize;
1986
09816fbe
AD		 1987 /*
1988 * since we are the only owner of the page and we need to
1989 * increment it, just set the value to 2 in order to avoid
1990 * an unecessary locked operation
1991 */
1992 atomic_set(&page->_count, 2);
1993#else
1994 /* move offset up to the next cache line */
1995 rx_buffer->page_offset += truesize;
1996
1997 if (rx_buffer->page_offset > last_offset)
1998 return false;
1999
0549ae20
AD		 2000 /* bump ref count on page before it is given to the stack */
2001 get_page(page);
09816fbe 2002#endif
0549ae20
AD		 2003
2004 return true;
f800326d
AD		 2005}
2006
18806c9e
AD		 2007static struct sk_buff *ixgbe_fetch_rx_buffer(struct ixgbe_ring *rx_ring,
2008 union ixgbe_adv_rx_desc *rx_desc)
2009{
2010 struct ixgbe_rx_buffer *rx_buffer;
2011 struct sk_buff *skb;
2012 struct page *page;
2013
2014 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2015 page = rx_buffer->page;
2016 prefetchw(page);
2017
2018 skb = rx_buffer->skb;
2019
2020 if (likely(!skb)) {
2021 void *page_addr = page_address(page) +
2022 rx_buffer->page_offset;
2023
2024 /* prefetch first cache line of first page */
2025 prefetch(page_addr);
2026#if L1_CACHE_BYTES < 128
2027 prefetch(page_addr + L1_CACHE_BYTES);
2028#endif
2029
2030 /* allocate a skb to store the frags */
2031 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
2032 IXGBE_RX_HDR_SIZE);
2033 if (unlikely(!skb)) {
2034 rx_ring->rx_stats.alloc_rx_buff_failed++;
2035 return NULL;
2036 }
2037
2038 /*
2039 * we will be copying header into skb->data in
2040 * pskb_may_pull so it is in our interest to prefetch
2041 * it now to avoid a possible cache miss
2042 */
2043 prefetchw(skb->data);
2044
2045 /*
2046 * Delay unmapping of the first packet. It carries the
2047 * header information, HW may still access the header
2048 * after the writeback. Only unmap it when EOP is
2049 * reached
2050 */
2051 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
2052 goto dma_sync;
2053
2054 IXGBE_CB(skb)->dma = rx_buffer->dma;
2055 } else {
2056 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2057 ixgbe_dma_sync_frag(rx_ring, skb);
2058
2059dma_sync:
2060 /* we are reusing so sync this buffer for CPU use */
2061 dma_sync_single_range_for_cpu(rx_ring->dev,
2062 rx_buffer->dma,
2063 rx_buffer->page_offset,
2064 ixgbe_rx_bufsz(rx_ring),
2065 DMA_FROM_DEVICE);
2066 }
2067
2068 /* pull page into skb */
2069 if (ixgbe_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
2070 /* hand second half of page back to the ring */
2071 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2072 } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) {
2073 /* the page has been released from the ring */
2074 IXGBE_CB(skb)->page_released = true;
2075 } else {
2076 /* we are not reusing the buffer so unmap it */
2077 dma_unmap_page(rx_ring->dev, rx_buffer->dma,
2078 ixgbe_rx_pg_size(rx_ring),
2079 DMA_FROM_DEVICE);
2080 }
2081
2082 /* clear contents of buffer_info */
2083 rx_buffer->skb = NULL;
2084 rx_buffer->dma = 0;
2085 rx_buffer->page = NULL;
2086
2087 return skb;
f800326d
AD		 2088}
2089
2090/**
2091 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2092 * @q_vector: structure containing interrupt and ring information
2093 * @rx_ring: rx descriptor ring to transact packets on
2094 * @budget: Total limit on number of packets to process
2095 *
2096 * This function provides a "bounce buffer" approach to Rx interrupt
2097 * processing. The advantage to this is that on systems that have
2098 * expensive overhead for IOMMU access this provides a means of avoiding
2099 * it by maintaining the mapping of the page to the syste.
2100 *
5a85e737 2101 * Returns amount of work completed
f800326d 2102 **/
5a85e737 2103static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
e8e9f696 2104 struct ixgbe_ring *rx_ring,
f4de00ed 2105 const int budget)
9a799d71 2106{
d2f4fbe2 2107 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
3f2d1c0f 2108#ifdef IXGBE_FCOE
f800326d 2109 struct ixgbe_adapter *adapter = q_vector->adapter;
4ffdf91a
MR		 2110 int ddp_bytes;
2111 unsigned int mss = 0;
3d8fd385 2112#endif /* IXGBE_FCOE */
f800326d 2113 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
9a799d71 2114
fdabfc8a 2115 while (likely(total_rx_packets < budget)) {
f800326d
AD		 2116 union ixgbe_adv_rx_desc *rx_desc;
2117 struct sk_buff *skb;
f800326d
AD		 2118
2119 /* return some buffers to hardware, one at a time is too slow */
2120 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2121 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2122 cleaned_count = 0;
2123 }
2124
18806c9e 2125 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
f800326d
AD		 2126
2127 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD))
2128 break;
9a799d71 2129
f800326d
AD		 2130 /*
2131 * This memory barrier is needed to keep us from reading
2132 * any other fields out of the rx_desc until we know the
2133 * RXD_STAT_DD bit is set
2134 */
2135 rmb();
9a799d71 2136
18806c9e
AD		 2137 /* retrieve a buffer from the ring */
2138 skb = ixgbe_fetch_rx_buffer(rx_ring, rx_desc);
f800326d 2139
18806c9e
AD		 2140 /* exit if we failed to retrieve a buffer */
2141 if (!skb)
2142 break;
9a799d71 2143
9a799d71 2144 cleaned_count++;
f8212f97 2145
f800326d
AD		 2146 /* place incomplete frames back on ring for completion */
2147 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2148 continue;
c267fc16 2149
f800326d
AD		 2150 /* verify the packet layout is correct */
2151 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2152 continue;
9a799d71 2153
d2f4fbe2
AV		 2154 /* probably a little skewed due to removing CRC */
2155 total_rx_bytes += skb->len;
d2f4fbe2 2156
8a0da21b
AD		 2157 /* populate checksum, timestamp, VLAN, and protocol */
2158 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2159
332d4a7d
YZ		 2160#ifdef IXGBE_FCOE
2161 /* if ddp, not passing to ULD unless for FCP_RSP or error */
57efd44c 2162 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
f56e0cb1 2163 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
4ffdf91a
MR		 2164 /* include DDPed FCoE data */
2165 if (ddp_bytes > 0) {
2166 if (!mss) {
2167 mss = rx_ring->netdev->mtu -
2168 sizeof(struct fcoe_hdr) -
2169 sizeof(struct fc_frame_header) -
2170 sizeof(struct fcoe_crc_eof);
2171 if (mss > 512)
2172 mss &= ~511;
2173 }
2174 total_rx_bytes += ddp_bytes;
2175 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2176 mss);
2177 }
63d635b2
AD		 2178 if (!ddp_bytes) {
2179 dev_kfree_skb_any(skb);
f800326d 2180 continue;
63d635b2 2181 }
3d8fd385 2182 }
f800326d 2183
332d4a7d 2184#endif /* IXGBE_FCOE */
8b80cda5 2185 skb_mark_napi_id(skb, &q_vector->napi);
8a0da21b 2186 ixgbe_rx_skb(q_vector, skb);
9a799d71 2187
f800326d 2188 /* update budget accounting */
f4de00ed 2189 total_rx_packets++;
fdabfc8a 2190 }
9a799d71 2191
c267fc16
AD		 2192 u64_stats_update_begin(&rx_ring->syncp);
2193 rx_ring->stats.packets += total_rx_packets;
2194 rx_ring->stats.bytes += total_rx_bytes;
2195 u64_stats_update_end(&rx_ring->syncp);
bd198058
AD		 2196 q_vector->rx.total_packets += total_rx_packets;
2197 q_vector->rx.total_bytes += total_rx_bytes;
4ff7fb12 2198
f800326d
AD		 2199 if (cleaned_count)
2200 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2201
5a85e737 2202 return total_rx_packets;
9a799d71
AK		 2203}
2204
e0d1095a 2205#ifdef CONFIG_NET_RX_BUSY_POLL
5a85e737
ET		 2206/* must be called with local_bh_disable()d */
2207static int ixgbe_low_latency_recv(struct napi_struct *napi)
2208{
2209 struct ixgbe_q_vector *q_vector =
2210 container_of(napi, struct ixgbe_q_vector, napi);
2211 struct ixgbe_adapter *adapter = q_vector->adapter;
2212 struct ixgbe_ring *ring;
2213 int found = 0;
2214
2215 if (test_bit(__IXGBE_DOWN, &adapter->state))
2216 return LL_FLUSH_FAILED;
2217
2218 if (!ixgbe_qv_lock_poll(q_vector))
2219 return LL_FLUSH_BUSY;
2220
2221 ixgbe_for_each_ring(ring, q_vector->rx) {
2222 found = ixgbe_clean_rx_irq(q_vector, ring, 4);
b4640030 2223#ifdef BP_EXTENDED_STATS
7e15b90f
ET		 2224 if (found)
2225 ring->stats.cleaned += found;
2226 else
2227 ring->stats.misses++;
2228#endif
5a85e737
ET		 2229 if (found)
2230 break;
2231 }
2232
2233 ixgbe_qv_unlock_poll(q_vector);
2234
2235 return found;
2236}
e0d1095a 2237#endif /* CONFIG_NET_RX_BUSY_POLL */
5a85e737 2238
9a799d71
AK		 2239/**
2240 * ixgbe_configure_msix - Configure MSI-X hardware
2241 * @adapter: board private structure
2242 *
2243 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2244 * interrupts.
2245 **/
2246static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2247{
021230d4 2248 struct ixgbe_q_vector *q_vector;
49c7ffbe 2249 int v_idx;
021230d4 2250 u32 mask;
9a799d71 2251
8e34d1aa
AD		 2252 /* Populate MSIX to EITR Select */
2253 if (adapter->num_vfs > 32) {
2254 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2255 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2256 }
2257
4df10466
JB		 2258 /*
2259 * Populate the IVAR table and set the ITR values to the
021230d4
AV		 2260 * corresponding register.
2261 */
49c7ffbe 2262 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
efe3d3c8 2263 struct ixgbe_ring *ring;
7a921c93 2264 q_vector = adapter->q_vector[v_idx];
021230d4 2265
a557928e 2266 ixgbe_for_each_ring(ring, q_vector->rx)
efe3d3c8
AD		 2267 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2268
a557928e 2269 ixgbe_for_each_ring(ring, q_vector->tx)
efe3d3c8
AD		 2270 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2271
fe49f04a 2272 ixgbe_write_eitr(q_vector);
9a799d71
AK		 2273 }
2274
bd508178
AD		 2275 switch (adapter->hw.mac.type) {
2276 case ixgbe_mac_82598EB:
e8e26350 2277 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
e8e9f696 2278 v_idx);
bd508178
AD		 2279 break;
2280 case ixgbe_mac_82599EB:
b93a2226 2281 case ixgbe_mac_X540:
e8e26350 2282 ixgbe_set_ivar(adapter, -1, 1, v_idx);
bd508178 2283 break;
bd508178
AD		 2284 default:
2285 break;
2286 }
021230d4
AV		 2287 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2288
41fb9248 2289 /* set up to autoclear timer, and the vectors */
021230d4 2290 mask = IXGBE_EIMS_ENABLE_MASK;
d5bf4f67
ET		 2291 mask &= ~(IXGBE_EIMS_OTHER |
2292 IXGBE_EIMS_MAILBOX |
2293 IXGBE_EIMS_LSC);
2294
021230d4 2295 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
9a799d71
AK		 2296}
2297
f494e8fa
AV		 2298enum latency_range {
2299 lowest_latency = 0,
2300 low_latency = 1,
2301 bulk_latency = 2,
2302 latency_invalid = 255
2303};
2304
2305/**
2306 * ixgbe_update_itr - update the dynamic ITR value based on statistics
bd198058
AD		 2307 * @q_vector: structure containing interrupt and ring information
2308 * @ring_container: structure containing ring performance data
f494e8fa
AV		 2309 *
2310 * Stores a new ITR value based on packets and byte
2311 * counts during the last interrupt. The advantage of per interrupt
2312 * computation is faster updates and more accurate ITR for the current
2313 * traffic pattern. Constants in this function were computed
2314 * based on theoretical maximum wire speed and thresholds were set based
2315 * on testing data as well as attempting to minimize response time
2316 * while increasing bulk throughput.
2317 * this functionality is controlled by the InterruptThrottleRate module
2318 * parameter (see ixgbe_param.c)
2319 **/
bd198058
AD		 2320static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2321 struct ixgbe_ring_container *ring_container)
f494e8fa 2322{
bd198058
AD		 2323 int bytes = ring_container->total_bytes;
2324 int packets = ring_container->total_packets;
2325 u32 timepassed_us;
621bd70e 2326 u64 bytes_perint;
bd198058 2327 u8 itr_setting = ring_container->itr;
f494e8fa
AV		 2328
2329 if (packets == 0)
bd198058 2330 return;
f494e8fa
AV		 2331
2332 /* simple throttlerate management
621bd70e
AD		 2333 * 0-10MB/s lowest (100000 ints/s)
2334 * 10-20MB/s low (20000 ints/s)
2335 * 20-1249MB/s bulk (8000 ints/s)
f494e8fa
AV		 2336 */
2337 /* what was last interrupt timeslice? */
d5bf4f67 2338 timepassed_us = q_vector->itr >> 2;
bdbeefe8
DS		 2339 if (timepassed_us == 0)
2340 return;
2341
f494e8fa
AV		 2342 bytes_perint = bytes / timepassed_us; /* bytes/usec */
2343
2344 switch (itr_setting) {
2345 case lowest_latency:
621bd70e 2346 if (bytes_perint > 10)
bd198058 2347 itr_setting = low_latency;
f494e8fa
AV		 2348 break;
2349 case low_latency:
621bd70e 2350 if (bytes_perint > 20)
bd198058 2351 itr_setting = bulk_latency;
621bd70e 2352 else if (bytes_perint <= 10)
bd198058 2353 itr_setting = lowest_latency;
f494e8fa
AV		 2354 break;
2355 case bulk_latency:
621bd70e 2356 if (bytes_perint <= 20)
bd198058 2357 itr_setting = low_latency;
f494e8fa
AV		 2358 break;
2359 }
2360
bd198058
AD		 2361 /* clear work counters since we have the values we need */
2362 ring_container->total_bytes = 0;
2363 ring_container->total_packets = 0;
2364
2365 /* write updated itr to ring container */
2366 ring_container->itr = itr_setting;
f494e8fa
AV		 2367}
2368
509ee935
JB		 2369/**
2370 * ixgbe_write_eitr - write EITR register in hardware specific way
fe49f04a 2371 * @q_vector: structure containing interrupt and ring information
509ee935
JB		 2372 *
2373 * This function is made to be called by ethtool and by the driver
2374 * when it needs to update EITR registers at runtime. Hardware
2375 * specific quirks/differences are taken care of here.
2376 */
fe49f04a 2377void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
509ee935 2378{
fe49f04a 2379 struct ixgbe_adapter *adapter = q_vector->adapter;
509ee935 2380 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2381 int v_idx = q_vector->v_idx;
5d967eb7 2382 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
fe49f04a 2383
bd508178
AD		 2384 switch (adapter->hw.mac.type) {
2385 case ixgbe_mac_82598EB:
509ee935
JB		 2386 /* must write high and low 16 bits to reset counter */
2387 itr_reg |= (itr_reg << 16);
bd508178
AD		 2388 break;
2389 case ixgbe_mac_82599EB:
b93a2226 2390 case ixgbe_mac_X540:
509ee935
JB		 2391 /*
2392 * set the WDIS bit to not clear the timer bits and cause an
2393 * immediate assertion of the interrupt
2394 */
2395 itr_reg |= IXGBE_EITR_CNT_WDIS;
bd508178
AD		 2396 break;
2397 default:
2398 break;
509ee935
JB		 2399 }
2400 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2401}
2402
bd198058 2403static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
f494e8fa 2404{
d5bf4f67 2405 u32 new_itr = q_vector->itr;
bd198058 2406 u8 current_itr;
f494e8fa 2407
bd198058
AD		 2408 ixgbe_update_itr(q_vector, &q_vector->tx);
2409 ixgbe_update_itr(q_vector, &q_vector->rx);
f494e8fa 2410
08c8833b 2411 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
f494e8fa
AV		 2412
2413 switch (current_itr) {
2414 /* counts and packets in update_itr are dependent on these numbers */
2415 case lowest_latency:
d5bf4f67 2416 new_itr = IXGBE_100K_ITR;
f494e8fa
AV		 2417 break;
2418 case low_latency:
d5bf4f67 2419 new_itr = IXGBE_20K_ITR;
f494e8fa
AV		 2420 break;
2421 case bulk_latency:
d5bf4f67 2422 new_itr = IXGBE_8K_ITR;
f494e8fa 2423 break;
bd198058
AD		 2424 default:
2425 break;
f494e8fa
AV		 2426 }
2427
d5bf4f67 2428 if (new_itr != q_vector->itr) {
fe49f04a 2429 /* do an exponential smoothing */
d5bf4f67
ET		 2430 new_itr = (10 * new_itr * q_vector->itr) /
2431 ((9 * new_itr) + q_vector->itr);
509ee935 2432
bd198058 2433 /* save the algorithm value here */
5d967eb7 2434 q_vector->itr = new_itr;
fe49f04a
AD		 2435
2436 ixgbe_write_eitr(q_vector);
f494e8fa 2437 }
f494e8fa
AV		 2438}
2439
119fc60a 2440/**
de88eeeb 2441 * ixgbe_check_overtemp_subtask - check for over temperature
f0f9778d 2442 * @adapter: pointer to adapter
119fc60a 2443 **/
f0f9778d 2444static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
119fc60a 2445{
119fc60a
MC		 2446 struct ixgbe_hw *hw = &adapter->hw;
2447 u32 eicr = adapter->interrupt_event;
2448
f0f9778d 2449 if (test_bit(__IXGBE_DOWN, &adapter->state))
7ca647bd
JP		 2450 return;
2451
f0f9778d
AD		 2452 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2453 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2454 return;
2455
2456 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2457
7ca647bd 2458 switch (hw->device_id) {
f0f9778d
AD		 2459 case IXGBE_DEV_ID_82599_T3_LOM:
2460 /*
2461 * Since the warning interrupt is for both ports
2462 * we don't have to check if:
2463 * - This interrupt wasn't for our port.
2464 * - We may have missed the interrupt so always have to
2465 * check if we got a LSC
2466 */
2467 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
2468 !(eicr & IXGBE_EICR_LSC))
2469 return;
2470
2471 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
3d292265 2472 u32 speed;
f0f9778d 2473 bool link_up = false;
7ca647bd 2474
3d292265 2475 hw->mac.ops.check_link(hw, &speed, &link_up, false);
7ca647bd 2476
f0f9778d
AD		 2477 if (link_up)
2478 return;
2479 }
2480
2481 /* Check if this is not due to overtemp */
2482 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
2483 return;
2484
2485 break;
7ca647bd
JP		 2486 default:
2487 if (!(eicr & IXGBE_EICR_GPI_SDP0))
119fc60a 2488 return;
7ca647bd 2489 break;
119fc60a 2490 }
7ca647bd
JP		 2491 e_crit(drv,
2492 "Network adapter has been stopped because it has over heated. "
2493 "Restart the computer. If the problem persists, "
2494 "power off the system and replace the adapter\n");
f0f9778d
AD		 2495
2496 adapter->interrupt_event = 0;
119fc60a
MC		 2497}
2498
0befdb3e
JB		 2499static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2500{
2501 struct ixgbe_hw *hw = &adapter->hw;
2502
2503 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2504 (eicr & IXGBE_EICR_GPI_SDP1)) {
396e799c 2505 e_crit(probe, "Fan has stopped, replace the adapter\n");
0befdb3e
JB		 2506 /* write to clear the interrupt */
2507 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
2508 }
2509}
cf8280ee 2510
4f51bf70
JK		 2511static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2512{
2513 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2514 return;
2515
2516 switch (adapter->hw.mac.type) {
2517 case ixgbe_mac_82599EB:
2518 /*
2519 * Need to check link state so complete overtemp check
2520 * on service task
2521 */
2522 if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) &&
2523 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2524 adapter->interrupt_event = eicr;
2525 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2526 ixgbe_service_event_schedule(adapter);
2527 return;
2528 }
2529 return;
2530 case ixgbe_mac_X540:
2531 if (!(eicr & IXGBE_EICR_TS))
2532 return;
2533 break;
2534 default:
2535 return;
2536 }
2537
2538 e_crit(drv,
2539 "Network adapter has been stopped because it has over heated. "
2540 "Restart the computer. If the problem persists, "
2541 "power off the system and replace the adapter\n");
2542}
2543
e8e26350
PW		 2544static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2545{
2546 struct ixgbe_hw *hw = &adapter->hw;
2547
73c4b7cd
AD		 2548 if (eicr & IXGBE_EICR_GPI_SDP2) {
2549 /* Clear the interrupt */
2550 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
7086400d
AD		 2551 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2552 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2553 ixgbe_service_event_schedule(adapter);
2554 }
73c4b7cd
AD		 2555 }
2556
e8e26350
PW		 2557 if (eicr & IXGBE_EICR_GPI_SDP1) {
2558 /* Clear the interrupt */
2559 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
7086400d
AD		 2560 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2561 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2562 ixgbe_service_event_schedule(adapter);
2563 }
e8e26350
PW		 2564 }
2565}
2566
cf8280ee
JB		 2567static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2568{
2569 struct ixgbe_hw *hw = &adapter->hw;
2570
2571 adapter->lsc_int++;
2572 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2573 adapter->link_check_timeout = jiffies;
2574 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2575 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
8a0717f3 2576 IXGBE_WRITE_FLUSH(hw);
93c52dd0 2577 ixgbe_service_event_schedule(adapter);
cf8280ee
JB		 2578 }
2579}
2580
fe49f04a
AD		 2581static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2582 u64 qmask)
2583{
2584 u32 mask;
bd508178 2585 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2586
bd508178
AD		 2587 switch (hw->mac.type) {
2588 case ixgbe_mac_82598EB:
fe49f04a 2589 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2590 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2591 break;
2592 case ixgbe_mac_82599EB:
b93a2226 2593 case ixgbe_mac_X540:
fe49f04a 2594 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2595 if (mask)
2596 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
fe49f04a 2597 mask = (qmask >> 32);
bd508178
AD		 2598 if (mask)
2599 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2600 break;
2601 default:
2602 break;
fe49f04a
AD		 2603 }
2604 /* skip the flush */
2605}
2606
2607static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
e8e9f696 2608 u64 qmask)
fe49f04a
AD		 2609{
2610 u32 mask;
bd508178 2611 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 2612
bd508178
AD		 2613 switch (hw->mac.type) {
2614 case ixgbe_mac_82598EB:
fe49f04a 2615 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
bd508178
AD		 2616 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
2617 break;
2618 case ixgbe_mac_82599EB:
b93a2226 2619 case ixgbe_mac_X540:
fe49f04a 2620 mask = (qmask & 0xFFFFFFFF);
bd508178
AD		 2621 if (mask)
2622 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
fe49f04a 2623 mask = (qmask >> 32);
bd508178
AD		 2624 if (mask)
2625 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
2626 break;
2627 default:
2628 break;
fe49f04a
AD		 2629 }
2630 /* skip the flush */
2631}
2632
021230d4 2633/**
2c4af694
AD		 2634 * ixgbe_irq_enable - Enable default interrupt generation settings
2635 * @adapter: board private structure
021230d4 2636 **/
2c4af694
AD		 2637static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2638 bool flush)
9a799d71 2639{
2c4af694 2640 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
9a799d71 2641
2c4af694
AD		 2642 /* don't reenable LSC while waiting for link */
2643 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
2644 mask &= ~IXGBE_EIMS_LSC;
9a799d71 2645
2c4af694 2646 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
4f51bf70
JK		 2647 switch (adapter->hw.mac.type) {
2648 case ixgbe_mac_82599EB:
2649 mask |= IXGBE_EIMS_GPI_SDP0;
2650 break;
2651 case ixgbe_mac_X540:
2652 mask |= IXGBE_EIMS_TS;
2653 break;
2654 default:
2655 break;
2656 }
2c4af694
AD		 2657 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2658 mask |= IXGBE_EIMS_GPI_SDP1;
2659 switch (adapter->hw.mac.type) {
2660 case ixgbe_mac_82599EB:
2c4af694
AD		 2661 mask |= IXGBE_EIMS_GPI_SDP1;
2662 mask |= IXGBE_EIMS_GPI_SDP2;
858bc081
DS		 2663 case ixgbe_mac_X540:
2664 mask |= IXGBE_EIMS_ECC;
2c4af694
AD		 2665 mask |= IXGBE_EIMS_MAILBOX;
2666 break;
2667 default:
2668 break;
9a799d71 2669 }
db0677fa 2670
db0677fa
JK		 2671 if (adapter->hw.mac.type == ixgbe_mac_X540)
2672 mask |= IXGBE_EIMS_TIMESYNC;
db0677fa 2673
2c4af694
AD		 2674 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2675 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
2676 mask |= IXGBE_EIMS_FLOW_DIR;
9a799d71 2677
2c4af694
AD		 2678 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2679 if (queues)
2680 ixgbe_irq_enable_queues(adapter, ~0);
2681 if (flush)
2682 IXGBE_WRITE_FLUSH(&adapter->hw);
9a799d71
AK		 2683}
2684
2c4af694 2685static irqreturn_t ixgbe_msix_other(int irq, void *data)
f0848276 2686{
a65151ba 2687 struct ixgbe_adapter *adapter = data;
9a799d71 2688 struct ixgbe_hw *hw = &adapter->hw;
54037505 2689 u32 eicr;
91281fd3 2690
54037505
DS		 2691 /*
2692 * Workaround for Silicon errata. Use clear-by-write instead
2693 * of clear-by-read. Reading with EICS will return the
2694 * interrupt causes without clearing, which later be done
2695 * with the write to EICR.
2696 */
2697 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
d87d8307
JK		 2698
2699 /* The lower 16bits of the EICR register are for the queue interrupts
2700 * which should be masked here in order to not accidently clear them if
2701 * the bits are high when ixgbe_msix_other is called. There is a race
2702 * condition otherwise which results in possible performance loss
2703 * especially if the ixgbe_msix_other interrupt is triggering
2704 * consistently (as it would when PPS is turned on for the X540 device)
2705 */
2706 eicr &= 0xFFFF0000;
2707
54037505 2708 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
33cf09c9 2709
cf8280ee
JB		 2710 if (eicr & IXGBE_EICR_LSC)
2711 ixgbe_check_lsc(adapter);
f0848276 2712
1cdd1ec8
GR		 2713 if (eicr & IXGBE_EICR_MAILBOX)
2714 ixgbe_msg_task(adapter);
efe3d3c8 2715
bd508178
AD		 2716 switch (hw->mac.type) {
2717 case ixgbe_mac_82599EB:
b93a2226 2718 case ixgbe_mac_X540:
d773ce2d
DS		 2719 if (eicr & IXGBE_EICR_ECC) {
2720 e_info(link, "Received ECC Err, initiating reset\n");
2721 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2722 ixgbe_service_event_schedule(adapter);
2723 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2724 }
c4cf55e5
PWJ		 2725 /* Handle Flow Director Full threshold interrupt */
2726 if (eicr & IXGBE_EICR_FLOW_DIR) {
d034acf1 2727 int reinit_count = 0;
c4cf55e5 2728 int i;
c4cf55e5 2729 for (i = 0; i < adapter->num_tx_queues; i++) {
d034acf1 2730 struct ixgbe_ring *ring = adapter->tx_ring[i];
7d637bcc 2731 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
d034acf1
AD		 2732 &ring->state))
2733 reinit_count++;
2734 }
2735 if (reinit_count) {
2736 /* no more flow director interrupts until after init */
2737 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
d034acf1
AD		 2738 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
2739 ixgbe_service_event_schedule(adapter);
c4cf55e5
PWJ		 2740 }
2741 }
f0f9778d 2742 ixgbe_check_sfp_event(adapter, eicr);
4f51bf70 2743 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2744 break;
2745 default:
2746 break;
c4cf55e5 2747 }
f0848276 2748
bd508178 2749 ixgbe_check_fan_failure(adapter, eicr);
db0677fa 2750
db0677fa
JK		 2751 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2752 ixgbe_ptp_check_pps_event(adapter, eicr);
efe3d3c8 2753
7086400d 2754 /* re-enable the original interrupt state, no lsc, no queues */
d4f80882 2755 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2c4af694 2756 ixgbe_irq_enable(adapter, false, false);
f0848276 2757
9a799d71 2758 return IRQ_HANDLED;
f0848276 2759}
91281fd3 2760
4ff7fb12 2761static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
91281fd3 2762{
021230d4 2763 struct ixgbe_q_vector *q_vector = data;
91281fd3 2764
9b471446 2765 /* EIAM disabled interrupts (on this vector) for us */
91281fd3 2766
4ff7fb12
AD		 2767 if (q_vector->rx.ring || q_vector->tx.ring)
2768 napi_schedule(&q_vector->napi);
91281fd3 2769
9a799d71 2770 return IRQ_HANDLED;
91281fd3
AD		 2771}
2772
eb01b975
AD		 2773/**
2774 * ixgbe_poll - NAPI Rx polling callback
2775 * @napi: structure for representing this polling device
2776 * @budget: how many packets driver is allowed to clean
2777 *
2778 * This function is used for legacy and MSI, NAPI mode
2779 **/
8af3c33f 2780int ixgbe_poll(struct napi_struct *napi, int budget)
eb01b975
AD		 2781{
2782 struct ixgbe_q_vector *q_vector =
2783 container_of(napi, struct ixgbe_q_vector, napi);
2784 struct ixgbe_adapter *adapter = q_vector->adapter;
2785 struct ixgbe_ring *ring;
2786 int per_ring_budget;
2787 bool clean_complete = true;
2788
2789#ifdef CONFIG_IXGBE_DCA
2790 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2791 ixgbe_update_dca(q_vector);
2792#endif
2793
2794 ixgbe_for_each_ring(ring, q_vector->tx)
2795 clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring);
2796
5a85e737
ET		 2797 if (!ixgbe_qv_lock_napi(q_vector))
2798 return budget;
2799
eb01b975
AD		 2800 /* attempt to distribute budget to each queue fairly, but don't allow
2801 * the budget to go below 1 because we'll exit polling */
2802 if (q_vector->rx.count > 1)
2803 per_ring_budget = max(budget/q_vector->rx.count, 1);
2804 else
2805 per_ring_budget = budget;
2806
2807 ixgbe_for_each_ring(ring, q_vector->rx)
5a85e737
ET		 2808 clean_complete &= (ixgbe_clean_rx_irq(q_vector, ring,
2809 per_ring_budget) < per_ring_budget);
eb01b975 2810
5a85e737 2811 ixgbe_qv_unlock_napi(q_vector);
eb01b975
AD		 2812 /* If all work not completed, return budget and keep polling */
2813 if (!clean_complete)
2814 return budget;
2815
2816 /* all work done, exit the polling mode */
2817 napi_complete(napi);
2818 if (adapter->rx_itr_setting & 1)
2819 ixgbe_set_itr(q_vector);
2820 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2821 ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
2822
2823 return 0;
2824}
2825
021230d4
AV		 2826/**
2827 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2828 * @adapter: board private structure
2829 *
2830 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2831 * interrupts from the kernel.
2832 **/
2833static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2834{
2835 struct net_device *netdev = adapter->netdev;
207867f5 2836 int vector, err;
e8e9f696 2837 int ri = 0, ti = 0;
021230d4 2838
49c7ffbe 2839 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
d0759ebb 2840 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
207867f5 2841 struct msix_entry *entry = &adapter->msix_entries[vector];
cb13fc20 2842
4ff7fb12 2843 if (q_vector->tx.ring && q_vector->rx.ring) {
9fe93afd 2844 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2845 "%s-%s-%d", netdev->name, "TxRx", ri++);
2846 ti++;
2847 } else if (q_vector->rx.ring) {
9fe93afd 2848 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12
AD		 2849 "%s-%s-%d", netdev->name, "rx", ri++);
2850 } else if (q_vector->tx.ring) {
9fe93afd 2851 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
4ff7fb12 2852 "%s-%s-%d", netdev->name, "tx", ti++);
d0759ebb
AD		 2853 } else {
2854 /* skip this unused q_vector */
2855 continue;
32aa77a4 2856 }
207867f5
AD		 2857 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
2858 q_vector->name, q_vector);
9a799d71 2859 if (err) {
396e799c 2860 e_err(probe, "request_irq failed for MSIX interrupt "
849c4542 2861 "Error: %d\n", err);
021230d4 2862 goto free_queue_irqs;
9a799d71 2863 }
207867f5
AD		 2864 /* If Flow Director is enabled, set interrupt affinity */
2865 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2866 /* assign the mask for this irq */
2867 irq_set_affinity_hint(entry->vector,
de88eeeb 2868 &q_vector->affinity_mask);
207867f5 2869 }
9a799d71
AK		 2870 }
2871
021230d4 2872 err = request_irq(adapter->msix_entries[vector].vector,
2c4af694 2873 ixgbe_msix_other, 0, netdev->name, adapter);
9a799d71 2874 if (err) {
de88eeeb 2875 e_err(probe, "request_irq for msix_other failed: %d\n", err);
021230d4 2876 goto free_queue_irqs;
9a799d71
AK		 2877 }
2878
9a799d71
AK		 2879 return 0;
2880
021230d4 2881free_queue_irqs:
207867f5
AD		 2882 while (vector) {
2883 vector--;
2884 irq_set_affinity_hint(adapter->msix_entries[vector].vector,
2885 NULL);
2886 free_irq(adapter->msix_entries[vector].vector,
2887 adapter->q_vector[vector]);
2888 }
021230d4
AV		 2889 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2890 pci_disable_msix(adapter->pdev);
9a799d71
AK		 2891 kfree(adapter->msix_entries);
2892 adapter->msix_entries = NULL;
9a799d71
AK		 2893 return err;
2894}
2895
2896/**
021230d4 2897 * ixgbe_intr - legacy mode Interrupt Handler
9a799d71
AK		 2898 * @irq: interrupt number
2899 * @data: pointer to a network interface device structure
9a799d71
AK		 2900 **/
2901static irqreturn_t ixgbe_intr(int irq, void *data)
2902{
a65151ba 2903 struct ixgbe_adapter *adapter = data;
9a799d71 2904 struct ixgbe_hw *hw = &adapter->hw;
7a921c93 2905 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71
AK		 2906 u32 eicr;
2907
54037505 2908 /*
24ddd967 2909 * Workaround for silicon errata #26 on 82598. Mask the interrupt
54037505
DS		 2910 * before the read of EICR.
2911 */
2912 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2913
021230d4 2914 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
52f33af8 2915 * therefore no explicit interrupt disable is necessary */
021230d4 2916 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
f47cf66e 2917 if (!eicr) {
6af3b9eb
ET		 2918 /*
2919 * shared interrupt alert!
f47cf66e 2920 * make sure interrupts are enabled because the read will
6af3b9eb
ET		 2921 * have disabled interrupts due to EIAM
2922 * finish the workaround of silicon errata on 82598. Unmask
2923 * the interrupt that we masked before the EICR read.
2924 */
2925 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2926 ixgbe_irq_enable(adapter, true, true);
9a799d71 2927 return IRQ_NONE; /* Not our interrupt */
f47cf66e 2928 }
9a799d71 2929
cf8280ee
JB		 2930 if (eicr & IXGBE_EICR_LSC)
2931 ixgbe_check_lsc(adapter);
021230d4 2932
bd508178
AD		 2933 switch (hw->mac.type) {
2934 case ixgbe_mac_82599EB:
e8e26350 2935 ixgbe_check_sfp_event(adapter, eicr);
0ccb974d
DS		 2936 /* Fall through */
2937 case ixgbe_mac_X540:
d773ce2d
DS		 2938 if (eicr & IXGBE_EICR_ECC) {
2939 e_info(link, "Received ECC Err, initiating reset\n");
2940 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
2941 ixgbe_service_event_schedule(adapter);
2942 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
2943 }
4f51bf70 2944 ixgbe_check_overtemp_event(adapter, eicr);
bd508178
AD		 2945 break;
2946 default:
2947 break;
2948 }
e8e26350 2949
0befdb3e 2950 ixgbe_check_fan_failure(adapter, eicr);
db0677fa
JK		 2951 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
2952 ixgbe_ptp_check_pps_event(adapter, eicr);
0befdb3e 2953
b9f6ed2b
AD		 2954 /* would disable interrupts here but EIAM disabled it */
2955 napi_schedule(&q_vector->napi);
9a799d71 2956
6af3b9eb
ET		 2957 /*
2958 * re-enable link(maybe) and non-queue interrupts, no flush.
2959 * ixgbe_poll will re-enable the queue interrupts
2960 */
6af3b9eb
ET		 2961 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2962 ixgbe_irq_enable(adapter, false, false);
2963
9a799d71
AK		 2964 return IRQ_HANDLED;
2965}
2966
2967/**
2968 * ixgbe_request_irq - initialize interrupts
2969 * @adapter: board private structure
2970 *
2971 * Attempts to configure interrupts using the best available
2972 * capabilities of the hardware and kernel.
2973 **/
021230d4 2974static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
9a799d71
AK		 2975{
2976 struct net_device *netdev = adapter->netdev;
021230d4 2977 int err;
9a799d71 2978
4cc6df29 2979 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
021230d4 2980 err = ixgbe_request_msix_irqs(adapter);
4cc6df29 2981 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
a0607fd3 2982 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
a65151ba 2983 netdev->name, adapter);
4cc6df29 2984 else
a0607fd3 2985 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
a65151ba 2986 netdev->name, adapter);
9a799d71 2987
de88eeeb 2988 if (err)
396e799c 2989 e_err(probe, "request_irq failed, Error %d\n", err);
9a799d71 2990
9a799d71
AK		 2991 return err;
2992}
2993
2994static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2995{
49c7ffbe 2996 int vector;
9a799d71 2997
49c7ffbe
AD		 2998 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2999 free_irq(adapter->pdev->irq, adapter);
3000 return;
3001 }
4cc6df29 3002
49c7ffbe
AD		 3003 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3004 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3005 struct msix_entry *entry = &adapter->msix_entries[vector];
894ff7cf 3006
49c7ffbe
AD		 3007 /* free only the irqs that were actually requested */
3008 if (!q_vector->rx.ring && !q_vector->tx.ring)
3009 continue;
207867f5 3010
49c7ffbe
AD		 3011 /* clear the affinity_mask in the IRQ descriptor */
3012 irq_set_affinity_hint(entry->vector, NULL);
3013
3014 free_irq(entry->vector, q_vector);
9a799d71 3015 }
49c7ffbe
AD		 3016
3017 free_irq(adapter->msix_entries[vector++].vector, adapter);
9a799d71
AK		 3018}
3019
22d5a71b
JB		 3020/**
3021 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3022 * @adapter: board private structure
3023 **/
3024static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3025{
bd508178
AD		 3026 switch (adapter->hw.mac.type) {
3027 case ixgbe_mac_82598EB:
835462fc 3028 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
bd508178
AD		 3029 break;
3030 case ixgbe_mac_82599EB:
b93a2226 3031 case ixgbe_mac_X540:
835462fc
NS		 3032 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3033 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
22d5a71b 3034 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
bd508178
AD		 3035 break;
3036 default:
3037 break;
22d5a71b
JB		 3038 }
3039 IXGBE_WRITE_FLUSH(&adapter->hw);
3040 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 3041 int vector;
3042
3043 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3044 synchronize_irq(adapter->msix_entries[vector].vector);
3045
3046 synchronize_irq(adapter->msix_entries[vector++].vector);
22d5a71b
JB		 3047 } else {
3048 synchronize_irq(adapter->pdev->irq);
3049 }
3050}
3051
9a799d71
AK		 3052/**
3053 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3054 *
3055 **/
3056static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3057{
d5bf4f67 3058 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
9a799d71 3059
d5bf4f67 3060 ixgbe_write_eitr(q_vector);
9a799d71 3061
e8e26350
PW		 3062 ixgbe_set_ivar(adapter, 0, 0, 0);
3063 ixgbe_set_ivar(adapter, 1, 0, 0);
021230d4 3064
396e799c 3065 e_info(hw, "Legacy interrupt IVAR setup done\n");
9a799d71
AK		 3066}
3067
43e69bf0
AD		 3068/**
3069 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3070 * @adapter: board private structure
3071 * @ring: structure containing ring specific data
3072 *
3073 * Configure the Tx descriptor ring after a reset.
3074 **/
84418e3b
AD		 3075void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3076 struct ixgbe_ring *ring)
43e69bf0
AD		 3077{
3078 struct ixgbe_hw *hw = &adapter->hw;
3079 u64 tdba = ring->dma;
2f1860b8 3080 int wait_loop = 10;
b88c6de2 3081 u32 txdctl = IXGBE_TXDCTL_ENABLE;
bf29ee6c 3082 u8 reg_idx = ring->reg_idx;
43e69bf0 3083
2f1860b8 3084 /* disable queue to avoid issues while updating state */
b88c6de2 3085 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
2f1860b8
AD		 3086 IXGBE_WRITE_FLUSH(hw);
3087
43e69bf0 3088 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
e8e9f696 3089 (tdba & DMA_BIT_MASK(32)));
43e69bf0
AD		 3090 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3091 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3092 ring->count * sizeof(union ixgbe_adv_tx_desc));
3093 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3094 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2a1a091c 3095 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
43e69bf0 3096
b88c6de2
AD		 3097 /*
3098 * set WTHRESH to encourage burst writeback, it should not be set
67da097e
ET		 3099 * higher than 1 when:
3100 * - ITR is 0 as it could cause false TX hangs
3101 * - ITR is set to > 100k int/sec and BQL is enabled
b88c6de2
AD		 3102 *
3103 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3104 * to or less than the number of on chip descriptors, which is
3105 * currently 40.
3106 */
67da097e
ET		 3107#if IS_ENABLED(CONFIG_BQL)
3108 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3109#else
e954b374 3110 if (!ring->q_vector || (ring->q_vector->itr < 8))
67da097e 3111#endif
b88c6de2
AD		 3112 txdctl |= (1 << 16); /* WTHRESH = 1 */
3113 else
3114 txdctl |= (8 << 16); /* WTHRESH = 8 */
3115
e954b374
AD		 3116 /*
3117 * Setting PTHRESH to 32 both improves performance
3118 * and avoids a TX hang with DFP enabled
3119 */
b88c6de2
AD		 3120 txdctl |= (1 << 8) | /* HTHRESH = 1 */
3121 32; /* PTHRESH = 32 */
2f1860b8
AD		 3122
3123 /* reinitialize flowdirector state */
39cb681b 3124 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
ee9e0f0b
AD		 3125 ring->atr_sample_rate = adapter->atr_sample_rate;
3126 ring->atr_count = 0;
3127 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3128 } else {
3129 ring->atr_sample_rate = 0;
3130 }
2f1860b8 3131
fd786b7b
AD		 3132 /* initialize XPS */
3133 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3134 struct ixgbe_q_vector *q_vector = ring->q_vector;
3135
3136 if (q_vector)
2a47fa45 3137 netif_set_xps_queue(ring->netdev,
fd786b7b
AD		 3138 &q_vector->affinity_mask,
3139 ring->queue_index);
3140 }
3141
c84d324c
JF		 3142 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3143
2f1860b8 3144 /* enable queue */
2f1860b8
AD		 3145 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3146
3147 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3148 if (hw->mac.type == ixgbe_mac_82598EB &&
3149 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3150 return;
3151
3152 /* poll to verify queue is enabled */
3153 do {
032b4325 3154 usleep_range(1000, 2000);
2f1860b8
AD		 3155 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3156 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3157 if (!wait_loop)
3158 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
43e69bf0
AD		 3159}
3160
120ff942
AD		 3161static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3162{
3163 struct ixgbe_hw *hw = &adapter->hw;
671c0adb 3164 u32 rttdcs, mtqc;
8b1c0b24 3165 u8 tcs = netdev_get_num_tc(adapter->netdev);
120ff942
AD		 3166
3167 if (hw->mac.type == ixgbe_mac_82598EB)
3168 return;
3169
3170 /* disable the arbiter while setting MTQC */
3171 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3172 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3173 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3174
3175 /* set transmit pool layout */
671c0adb
AD		 3176 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3177 mtqc = IXGBE_MTQC_VT_ENA;
3178 if (tcs > 4)
3179 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3180 else if (tcs > 1)
3181 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3182 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3183 mtqc |= IXGBE_MTQC_32VF;
3184 else
3185 mtqc |= IXGBE_MTQC_64VF;
3186 } else {
3187 if (tcs > 4)
3188 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3189 else if (tcs > 1)
3190 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
8b1c0b24 3191 else
671c0adb
AD		 3192 mtqc = IXGBE_MTQC_64Q_1PB;
3193 }
120ff942 3194
671c0adb 3195 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
120ff942 3196
671c0adb
AD		 3197 /* Enable Security TX Buffer IFG for multiple pb */
3198 if (tcs) {
3199 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3200 sectx |= IXGBE_SECTX_DCB;
3201 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
120ff942
AD		 3202 }
3203
3204 /* re-enable the arbiter */
3205 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3206 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3207}
3208
9a799d71 3209/**
3a581073 3210 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
9a799d71
AK		 3211 * @adapter: board private structure
3212 *
3213 * Configure the Tx unit of the MAC after a reset.
3214 **/
3215static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3216{
2f1860b8
AD		 3217 struct ixgbe_hw *hw = &adapter->hw;
3218 u32 dmatxctl;
43e69bf0 3219 u32 i;
9a799d71 3220
2f1860b8
AD		 3221 ixgbe_setup_mtqc(adapter);
3222
3223 if (hw->mac.type != ixgbe_mac_82598EB) {
3224 /* DMATXCTL.EN must be before Tx queues are enabled */
3225 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3226 dmatxctl |= IXGBE_DMATXCTL_TE;
3227 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3228 }
3229
9a799d71 3230 /* Setup the HW Tx Head and Tail descriptor pointers */
43e69bf0
AD		 3231 for (i = 0; i < adapter->num_tx_queues; i++)
3232 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
9a799d71
AK		 3233}
3234
3ebe8fde
AD		 3235static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3236 struct ixgbe_ring *ring)
3237{
3238 struct ixgbe_hw *hw = &adapter->hw;
3239 u8 reg_idx = ring->reg_idx;
3240 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3241
3242 srrctl |= IXGBE_SRRCTL_DROP_EN;
3243
3244 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3245}
3246
3247static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3248 struct ixgbe_ring *ring)
3249{
3250 struct ixgbe_hw *hw = &adapter->hw;
3251 u8 reg_idx = ring->reg_idx;
3252 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3253
3254 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3255
3256 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3257}
3258
3259#ifdef CONFIG_IXGBE_DCB
3260void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3261#else
3262static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3263#endif
3264{
3265 int i;
3266 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3267
3268 if (adapter->ixgbe_ieee_pfc)
3269 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3270
3271 /*
3272 * We should set the drop enable bit if:
3273 * SR-IOV is enabled
3274 * or
3275 * Number of Rx queues > 1 and flow control is disabled
3276 *
3277 * This allows us to avoid head of line blocking for security
3278 * and performance reasons.
3279 */
3280 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3281 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3282 for (i = 0; i < adapter->num_rx_queues; i++)
3283 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3284 } else {
3285 for (i = 0; i < adapter->num_rx_queues; i++)
3286 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3287 }
3288}
3289
e8e26350 3290#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
cc41ac7c 3291
a6616b42 3292static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
e8e9f696 3293 struct ixgbe_ring *rx_ring)
cc41ac7c 3294{
45e9baa5 3295 struct ixgbe_hw *hw = &adapter->hw;
cc41ac7c 3296 u32 srrctl;
bf29ee6c 3297 u8 reg_idx = rx_ring->reg_idx;
3be1adfb 3298
45e9baa5
AD		 3299 if (hw->mac.type == ixgbe_mac_82598EB) {
3300 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
cc41ac7c 3301
45e9baa5
AD		 3302 /*
3303 * if VMDq is not active we must program one srrctl register
3304 * per RSS queue since we have enabled RDRXCTL.MVMEN
3305 */
3306 reg_idx &= mask;
3307 }
cc41ac7c 3308
45e9baa5
AD		 3309 /* configure header buffer length, needed for RSC */
3310 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
afafd5b0 3311
45e9baa5 3312 /* configure the packet buffer length */
f800326d 3313 srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
45e9baa5
AD		 3314
3315 /* configure descriptor type */
f800326d 3316 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
e8e26350 3317
45e9baa5 3318 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
cc41ac7c 3319}
9a799d71 3320
05abb126 3321static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
0cefafad 3322{
05abb126
AD		 3323 struct ixgbe_hw *hw = &adapter->hw;
3324 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
e8e9f696
JP		 3325 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
3326 0x6A3E67EA, 0x14364D17, 0x3BED200D};
05abb126
AD		 3327 u32 mrqc = 0, reta = 0;
3328 u32 rxcsum;
3329 int i, j;
671c0adb
AD		 3330 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3331
671c0adb
AD		 3332 /*
3333 * Program table for at least 2 queues w/ SR-IOV so that VFs can
3334 * make full use of any rings they may have. We will use the
3335 * PSRTYPE register to control how many rings we use within the PF.
3336 */
3337 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 2))
3338 rss_i = 2;
0cefafad 3339
05abb126
AD		 3340 /* Fill out hash function seeds */
3341 for (i = 0; i < 10; i++)
3342 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
3343
3344 /* Fill out redirection table */
3345 for (i = 0, j = 0; i < 128; i++, j++) {
671c0adb 3346 if (j == rss_i)
05abb126
AD		 3347 j = 0;
3348 /* reta = 4-byte sliding window of
3349 * 0x00..(indices-1)(indices-1)00..etc. */
3350 reta = (reta << 8) | (j * 0x11);
3351 if ((i & 3) == 3)
3352 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3353 }
0cefafad 3354
05abb126
AD		 3355 /* Disable indicating checksum in descriptor, enables RSS hash */
3356 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3357 rxcsum |= IXGBE_RXCSUM_PCSD;
3358 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3359
671c0adb 3360 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
fbe7ca7f 3361 if (adapter->ring_feature[RING_F_RSS].mask)
671c0adb 3362 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3363 } else {
671c0adb
AD		 3364 u8 tcs = netdev_get_num_tc(adapter->netdev);
3365
3366 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3367 if (tcs > 4)
3368 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3369 else if (tcs > 1)
3370 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3371 else if (adapter->ring_feature[RING_F_RSS].indices == 4)
3372 mrqc = IXGBE_MRQC_VMDQRSS32EN;
8b1c0b24 3373 else
671c0adb
AD		 3374 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3375 } else {
3376 if (tcs > 4)
8b1c0b24 3377 mrqc = IXGBE_MRQC_RTRSS8TCEN;
671c0adb
AD		 3378 else if (tcs > 1)
3379 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3380 else
3381 mrqc = IXGBE_MRQC_RSSEN;
8b1c0b24 3382 }
0cefafad
JB		 3383 }
3384
05abb126 3385 /* Perform hash on these packet types */
671c0adb
AD		 3386 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3387 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3388 IXGBE_MRQC_RSS_FIELD_IPV6 |
3389 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
05abb126 3390
ef6afc0c
AD		 3391 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3392 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3393 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3394 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3395
05abb126 3396 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
0cefafad
JB		 3397}
3398
bb5a9ad2
NS		 3399/**
3400 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3401 * @adapter: address of board private structure
3402 * @index: index of ring to set
bb5a9ad2 3403 **/
082757af 3404static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
7367096a 3405 struct ixgbe_ring *ring)
bb5a9ad2 3406{
bb5a9ad2 3407 struct ixgbe_hw *hw = &adapter->hw;
bb5a9ad2 3408 u32 rscctrl;
bf29ee6c 3409 u8 reg_idx = ring->reg_idx;
7367096a 3410
7d637bcc 3411 if (!ring_is_rsc_enabled(ring))
7367096a 3412 return;
bb5a9ad2 3413
7367096a 3414 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
bb5a9ad2
NS		 3415 rscctrl |= IXGBE_RSCCTL_RSCEN;
3416 /*
3417 * we must limit the number of descriptors so that the
3418 * total size of max desc * buf_len is not greater
642c680e 3419 * than 65536
bb5a9ad2 3420 */
f800326d 3421 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
7367096a 3422 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
bb5a9ad2
NS		 3423}
3424
9e10e045
AD		 3425#define IXGBE_MAX_RX_DESC_POLL 10
3426static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3427 struct ixgbe_ring *ring)
3428{
3429 struct ixgbe_hw *hw = &adapter->hw;
9e10e045
AD		 3430 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3431 u32 rxdctl;
bf29ee6c 3432 u8 reg_idx = ring->reg_idx;
9e10e045 3433
b0483c8f
MR		 3434 if (ixgbe_removed(hw->hw_addr))
3435 return;
9e10e045
AD		 3436 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3437 if (hw->mac.type == ixgbe_mac_82598EB &&
3438 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3439 return;
3440
3441 do {
032b4325 3442 usleep_range(1000, 2000);
9e10e045
AD		 3443 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3444 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3445
3446 if (!wait_loop) {
3447 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3448 "the polling period\n", reg_idx);
3449 }
3450}
3451
2d39d576
YZ		 3452void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3453 struct ixgbe_ring *ring)
3454{
3455 struct ixgbe_hw *hw = &adapter->hw;
3456 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3457 u32 rxdctl;
3458 u8 reg_idx = ring->reg_idx;
3459
b0483c8f
MR		 3460 if (ixgbe_removed(hw->hw_addr))
3461 return;
2d39d576
YZ		 3462 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3463 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3464
3465 /* write value back with RXDCTL.ENABLE bit cleared */
3466 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3467
3468 if (hw->mac.type == ixgbe_mac_82598EB &&
3469 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3470 return;
3471
3472 /* the hardware may take up to 100us to really disable the rx queue */
3473 do {
3474 udelay(10);
3475 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3476 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3477
3478 if (!wait_loop) {
3479 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3480 "the polling period\n", reg_idx);
3481 }
3482}
3483
84418e3b
AD		 3484void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3485 struct ixgbe_ring *ring)
acd37177
AD		 3486{
3487 struct ixgbe_hw *hw = &adapter->hw;
3488 u64 rdba = ring->dma;
9e10e045 3489 u32 rxdctl;
bf29ee6c 3490 u8 reg_idx = ring->reg_idx;
acd37177 3491
9e10e045
AD		 3492 /* disable queue to avoid issues while updating state */
3493 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2d39d576 3494 ixgbe_disable_rx_queue(adapter, ring);
9e10e045 3495
acd37177
AD		 3496 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3497 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3498 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3499 ring->count * sizeof(union ixgbe_adv_rx_desc));
3500 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3501 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2a1a091c 3502 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
9e10e045
AD		 3503
3504 ixgbe_configure_srrctl(adapter, ring);
3505 ixgbe_configure_rscctl(adapter, ring);
3506
3507 if (hw->mac.type == ixgbe_mac_82598EB) {
3508 /*
3509 * enable cache line friendly hardware writes:
3510 * PTHRESH=32 descriptors (half the internal cache),
3511 * this also removes ugly rx_no_buffer_count increment
3512 * HTHRESH=4 descriptors (to minimize latency on fetch)
3513 * WTHRESH=8 burst writeback up to two cache lines
3514 */
3515 rxdctl &= ~0x3FFFFF;
3516 rxdctl |= 0x080420;
3517 }
3518
3519 /* enable receive descriptor ring */
3520 rxdctl |= IXGBE_RXDCTL_ENABLE;
3521 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3522
3523 ixgbe_rx_desc_queue_enable(adapter, ring);
7d4987de 3524 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
acd37177
AD		 3525}
3526
48654521
AD		 3527static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3528{
3529 struct ixgbe_hw *hw = &adapter->hw;
fbe7ca7f 3530 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
2a47fa45 3531 u16 pool;
48654521
AD		 3532
3533 /* PSRTYPE must be initialized in non 82598 adapters */
3534 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
e8e9f696
JP		 3535 IXGBE_PSRTYPE_UDPHDR |
3536 IXGBE_PSRTYPE_IPV4HDR |
48654521 3537 IXGBE_PSRTYPE_L2HDR |
e8e9f696 3538 IXGBE_PSRTYPE_IPV6HDR;
48654521
AD		 3539
3540 if (hw->mac.type == ixgbe_mac_82598EB)
3541 return;
3542
fbe7ca7f
AD		 3543 if (rss_i > 3)
3544 psrtype |= 2 << 29;
3545 else if (rss_i > 1)
3546 psrtype |= 1 << 29;
48654521 3547
2a47fa45
JF		 3548 for_each_set_bit(pool, &adapter->fwd_bitmask, 32)
3549 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
48654521
AD		 3550}
3551
f5b4a52e
AD		 3552static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3553{
3554 struct ixgbe_hw *hw = &adapter->hw;
f5b4a52e 3555 u32 reg_offset, vf_shift;
435b19f6 3556 u32 gcr_ext, vmdctl;
de4c7f65 3557 int i;
f5b4a52e
AD		 3558
3559 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3560 return;
3561
3562 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
435b19f6
AD		 3563 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
3564 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
1d9c0bfd 3565 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
435b19f6
AD		 3566 vmdctl |= IXGBE_VT_CTL_REPLEN;
3567 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
f5b4a52e 3568
1d9c0bfd
AD		 3569 vf_shift = VMDQ_P(0) % 32;
3570 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
f5b4a52e
AD		 3571
3572 /* Enable only the PF's pool for Tx/Rx */
435b19f6
AD		 3573 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (~0) << vf_shift);
3574 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
3575 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (~0) << vf_shift);
3576 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
9b735984
GR		 3577 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
3578 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
f5b4a52e
AD		 3579
3580 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
1d9c0bfd 3581 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
f5b4a52e
AD		 3582
3583 /*
3584 * Set up VF register offsets for selected VT Mode,
3585 * i.e. 32 or 64 VFs for SR-IOV
3586 */
73079ea0
AD		 3587 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
3588 case IXGBE_82599_VMDQ_8Q_MASK:
3589 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
3590 break;
3591 case IXGBE_82599_VMDQ_4Q_MASK:
3592 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
3593 break;
3594 default:
3595 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
3596 break;
3597 }
3598
f5b4a52e
AD		 3599 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3600
435b19f6 3601
a985b6c3 3602 /* Enable MAC Anti-Spoofing */
435b19f6 3603 hw->mac.ops.set_mac_anti_spoofing(hw, (adapter->num_vfs != 0),
a985b6c3 3604 adapter->num_vfs);
de4c7f65
GR		 3605 /* For VFs that have spoof checking turned off */
3606 for (i = 0; i < adapter->num_vfs; i++) {
3607 if (!adapter->vfinfo[i].spoofchk_enabled)
3608 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false);
3609 }
f5b4a52e
AD		 3610}
3611
477de6ed 3612static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
9a799d71 3613{
9a799d71
AK		 3614 struct ixgbe_hw *hw = &adapter->hw;
3615 struct net_device *netdev = adapter->netdev;
3616 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
477de6ed
AD		 3617 struct ixgbe_ring *rx_ring;
3618 int i;
3619 u32 mhadd, hlreg0;
48654521 3620
63f39bd1 3621#ifdef IXGBE_FCOE
477de6ed
AD		 3622 /* adjust max frame to be able to do baby jumbo for FCoE */
3623 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3624 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3625 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9a799d71 3626
477de6ed 3627#endif /* IXGBE_FCOE */
872844dd
AD		 3628
3629 /* adjust max frame to be at least the size of a standard frame */
3630 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
3631 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
3632
477de6ed
AD		 3633 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3634 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3635 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3636 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3637
3638 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3639 }
3640
3641 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3642 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3643 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3644 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
9a799d71 3645
0cefafad
JB		 3646 /*
3647 * Setup the HW Rx Head and Tail Descriptor Pointers and
3648 * the Base and Length of the Rx Descriptor Ring
3649 */
9a799d71 3650 for (i = 0; i < adapter->num_rx_queues; i++) {
4a0b9ca0 3651 rx_ring = adapter->rx_ring[i];
7d637bcc
AD		 3652 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3653 set_ring_rsc_enabled(rx_ring);
1b3ff02e 3654 else
7d637bcc 3655 clear_ring_rsc_enabled(rx_ring);
477de6ed 3656 }
477de6ed
AD		 3657}
3658
7367096a
AD		 3659static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3660{
3661 struct ixgbe_hw *hw = &adapter->hw;
3662 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3663
3664 switch (hw->mac.type) {
3665 case ixgbe_mac_82598EB:
3666 /*
3667 * For VMDq support of different descriptor types or
3668 * buffer sizes through the use of multiple SRRCTL
3669 * registers, RDRXCTL.MVMEN must be set to 1
3670 *
3671 * also, the manual doesn't mention it clearly but DCA hints
3672 * will only use queue 0's tags unless this bit is set. Side
3673 * effects of setting this bit are only that SRRCTL must be
3674 * fully programmed [0..15]
3675 */
3676 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3677 break;
3678 case ixgbe_mac_82599EB:
b93a2226 3679 case ixgbe_mac_X540:
7367096a
AD		 3680 /* Disable RSC for ACK packets */
3681 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3682 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3683 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3684 /* hardware requires some bits to be set by default */
3685 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3686 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3687 break;
3688 default:
3689 /* We should do nothing since we don't know this hardware */
3690 return;
3691 }
3692
3693 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3694}
3695
477de6ed
AD		 3696/**
3697 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3698 * @adapter: board private structure
3699 *
3700 * Configure the Rx unit of the MAC after a reset.
3701 **/
3702static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3703{
3704 struct ixgbe_hw *hw = &adapter->hw;
477de6ed 3705 int i;
6dcc28b9 3706 u32 rxctrl, rfctl;
477de6ed
AD		 3707
3708 /* disable receives while setting up the descriptors */
3709 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3710 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3711
3712 ixgbe_setup_psrtype(adapter);
7367096a 3713 ixgbe_setup_rdrxctl(adapter);
477de6ed 3714
6dcc28b9
JK		 3715 /* RSC Setup */
3716 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
3717 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
3718 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
3719 rfctl |= IXGBE_RFCTL_RSC_DIS;
3720 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
3721
9e10e045 3722 /* Program registers for the distribution of queues */
f5b4a52e 3723 ixgbe_setup_mrqc(adapter);
f5b4a52e 3724
477de6ed
AD		 3725 /* set_rx_buffer_len must be called before ring initialization */
3726 ixgbe_set_rx_buffer_len(adapter);
3727
3728 /*
3729 * Setup the HW Rx Head and Tail Descriptor Pointers and
3730 * the Base and Length of the Rx Descriptor Ring
3731 */
9e10e045
AD		 3732 for (i = 0; i < adapter->num_rx_queues; i++)
3733 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
177db6ff 3734
9e10e045
AD		 3735 /* disable drop enable for 82598 parts */
3736 if (hw->mac.type == ixgbe_mac_82598EB)
3737 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3738
3739 /* enable all receives */
3740 rxctrl |= IXGBE_RXCTRL_RXEN;
3741 hw->mac.ops.enable_rx_dma(hw, rxctrl);
9a799d71
AK		 3742}
3743
80d5c368
PM		 3744static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
3745 __be16 proto, u16 vid)
068c89b0
DS		 3746{
3747 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3748 struct ixgbe_hw *hw = &adapter->hw;
3749
3750 /* add VID to filter table */
1d9c0bfd 3751 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true);
f62bbb5e 3752 set_bit(vid, adapter->active_vlans);
8e586137
JP		 3753
3754 return 0;
068c89b0
DS		 3755}
3756
80d5c368
PM		 3757static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
3758 __be16 proto, u16 vid)
068c89b0
DS		 3759{
3760 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3761 struct ixgbe_hw *hw = &adapter->hw;
3762
068c89b0 3763 /* remove VID from filter table */
1d9c0bfd 3764 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), false);
f62bbb5e 3765 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 3766
3767 return 0;
068c89b0
DS		 3768}
3769
5f6c0181
JB		 3770/**
3771 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3772 * @adapter: driver data
3773 */
3774static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3775{
3776 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e
JG		 3777 u32 vlnctrl;
3778
3779 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3780 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3781 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3782}
3783
3784/**
3785 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3786 * @adapter: driver data
3787 */
3788static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3789{
3790 struct ixgbe_hw *hw = &adapter->hw;
3791 u32 vlnctrl;
3792
3793 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3794 vlnctrl |= IXGBE_VLNCTRL_VFE;
3795 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3796 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3797}
3798
3799/**
3800 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3801 * @adapter: driver data
3802 */
3803static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3804{
3805 struct ixgbe_hw *hw = &adapter->hw;
3806 u32 vlnctrl;
5f6c0181
JB		 3807 int i, j;
3808
3809 switch (hw->mac.type) {
3810 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3811 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3812 vlnctrl &= ~IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3813 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3814 break;
3815 case ixgbe_mac_82599EB:
b93a2226 3816 case ixgbe_mac_X540:
5f6c0181 3817 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3818 struct ixgbe_ring *ring = adapter->rx_ring[i];
3819
3820 if (ring->l2_accel_priv)
3821 continue;
3822 j = ring->reg_idx;
5f6c0181
JB		 3823 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3824 vlnctrl &= ~IXGBE_RXDCTL_VME;
3825 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3826 }
3827 break;
3828 default:
3829 break;
3830 }
3831}
3832
3833/**
f62bbb5e 3834 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
5f6c0181
JB		 3835 * @adapter: driver data
3836 */
f62bbb5e 3837static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
5f6c0181
JB		 3838{
3839 struct ixgbe_hw *hw = &adapter->hw;
f62bbb5e 3840 u32 vlnctrl;
5f6c0181
JB		 3841 int i, j;
3842
3843 switch (hw->mac.type) {
3844 case ixgbe_mac_82598EB:
f62bbb5e
JG		 3845 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3846 vlnctrl |= IXGBE_VLNCTRL_VME;
5f6c0181
JB		 3847 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3848 break;
3849 case ixgbe_mac_82599EB:
b93a2226 3850 case ixgbe_mac_X540:
5f6c0181 3851 for (i = 0; i < adapter->num_rx_queues; i++) {
2a47fa45
JF		 3852 struct ixgbe_ring *ring = adapter->rx_ring[i];
3853
3854 if (ring->l2_accel_priv)
3855 continue;
3856 j = ring->reg_idx;
5f6c0181
JB		 3857 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3858 vlnctrl |= IXGBE_RXDCTL_VME;
3859 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3860 }
3861 break;
3862 default:
3863 break;
3864 }
3865}
3866
9a799d71
AK		 3867static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3868{
f62bbb5e 3869 u16 vid;
9a799d71 3870
80d5c368 3871 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
f62bbb5e
JG		 3872
3873 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
80d5c368 3874 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
9a799d71
AK		 3875}
3876
2850062a
AD		 3877/**
3878 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3879 * @netdev: network interface device structure
3880 *
3881 * Writes unicast address list to the RAR table.
3882 * Returns: -ENOMEM on failure/insufficient address space
3883 * 0 on no addresses written
3884 * X on writing X addresses to the RAR table
3885 **/
3886static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3887{
3888 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3889 struct ixgbe_hw *hw = &adapter->hw;
95447461 3890 unsigned int rar_entries = hw->mac.num_rar_entries - 1;
2850062a
AD		 3891 int count = 0;
3892
2a47fa45 3893 /* In SR-IOV/VMDQ modes significantly less RAR entries are available */
95447461
JF		 3894 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3895 rar_entries = IXGBE_MAX_PF_MACVLANS - 1;
3896
2850062a
AD		 3897 /* return ENOMEM indicating insufficient memory for addresses */
3898 if (netdev_uc_count(netdev) > rar_entries)
3899 return -ENOMEM;
3900
95447461 3901 if (!netdev_uc_empty(netdev)) {
2850062a
AD		 3902 struct netdev_hw_addr *ha;
3903 /* return error if we do not support writing to RAR table */
3904 if (!hw->mac.ops.set_rar)
3905 return -ENOMEM;
3906
3907 netdev_for_each_uc_addr(ha, netdev) {
3908 if (!rar_entries)
3909 break;
3910 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
1d9c0bfd 3911 VMDQ_P(0), IXGBE_RAH_AV);
2850062a
AD		 3912 count++;
3913 }
3914 }
3915 /* write the addresses in reverse order to avoid write combining */
3916 for (; rar_entries > 0 ; rar_entries--)
3917 hw->mac.ops.clear_rar(hw, rar_entries);
3918
3919 return count;
3920}
3921
9a799d71 3922/**
2c5645cf 3923 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
9a799d71
AK		 3924 * @netdev: network interface device structure
3925 *
2c5645cf
CL		 3926 * The set_rx_method entry point is called whenever the unicast/multicast
3927 * address list or the network interface flags are updated. This routine is
3928 * responsible for configuring the hardware for proper unicast, multicast and
3929 * promiscuous mode.
9a799d71 3930 **/
7f870475 3931void ixgbe_set_rx_mode(struct net_device *netdev)
9a799d71
AK		 3932{
3933 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3934 struct ixgbe_hw *hw = &adapter->hw;
2850062a
AD		 3935 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3936 int count;
9a799d71
AK		 3937
3938 /* Check for Promiscuous and All Multicast modes */
3939
3940 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3941
f5dc442b 3942 /* set all bits that we expect to always be set */
3f2d1c0f 3943 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
f5dc442b
AD		 3944 fctrl |= IXGBE_FCTRL_BAM;
3945 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3946 fctrl |= IXGBE_FCTRL_PMCF;
3947
2850062a
AD		 3948 /* clear the bits we are changing the status of */
3949 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3950
9a799d71 3951 if (netdev->flags & IFF_PROMISC) {
e433ea1f 3952 hw->addr_ctrl.user_set_promisc = true;
9a799d71 3953 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2850062a 3954 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
670224f1
GR		 3955 /* Only disable hardware filter vlans in promiscuous mode
3956 * if SR-IOV and VMDQ are disabled - otherwise ensure
3957 * that hardware VLAN filters remain enabled.
3958 */
3959 if (!(adapter->flags & (IXGBE_FLAG_VMDQ_ENABLED |
3960 IXGBE_FLAG_SRIOV_ENABLED)))
3961 ixgbe_vlan_filter_disable(adapter);
3962 else
3963 ixgbe_vlan_filter_enable(adapter);
9a799d71 3964 } else {
746b9f02
PM		 3965 if (netdev->flags & IFF_ALLMULTI) {
3966 fctrl |= IXGBE_FCTRL_MPE;
2850062a 3967 vmolr |= IXGBE_VMOLR_MPE;
746b9f02 3968 }
5f6c0181 3969 ixgbe_vlan_filter_enable(adapter);
e433ea1f 3970 hw->addr_ctrl.user_set_promisc = false;
9dcb373c
JF		 3971 }
3972
3973 /*
3974 * Write addresses to available RAR registers, if there is not
3975 * sufficient space to store all the addresses then enable
3976 * unicast promiscuous mode
3977 */
3978 count = ixgbe_write_uc_addr_list(netdev);
3979 if (count < 0) {
3980 fctrl |= IXGBE_FCTRL_UPE;
3981 vmolr |= IXGBE_VMOLR_ROPE;
9a799d71
AK		 3982 }
3983
cf78959c
ET		 3984 /* Write addresses to the MTA, if the attempt fails
3985 * then we should just turn on promiscuous mode so
3986 * that we can at least receive multicast traffic
3987 */
3988 hw->mac.ops.update_mc_addr_list(hw, netdev);
3989 vmolr |= IXGBE_VMOLR_ROMPE;
3990
1d9c0bfd 3991 if (adapter->num_vfs)
1cdd1ec8 3992 ixgbe_restore_vf_multicasts(adapter);
1d9c0bfd
AD		 3993
3994 if (hw->mac.type != ixgbe_mac_82598EB) {
3995 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
2850062a
AD		 3996 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3997 IXGBE_VMOLR_ROPE);
1d9c0bfd 3998 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
2850062a
AD		 3999 }
4000
3f2d1c0f
BG		 4001 /* This is useful for sniffing bad packets. */
4002 if (adapter->netdev->features & NETIF_F_RXALL) {
4003 /* UPE and MPE will be handled by normal PROMISC logic
4004 * in e1000e_set_rx_mode */
4005 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4006 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4007 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4008
4009 fctrl &= ~(IXGBE_FCTRL_DPF);
4010 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4011 }
4012
2850062a 4013 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
f62bbb5e 4014
f646968f 4015 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
f62bbb5e
JG		 4016 ixgbe_vlan_strip_enable(adapter);
4017 else
4018 ixgbe_vlan_strip_disable(adapter);
9a799d71
AK		 4019}
4020
021230d4
AV		 4021static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
4022{
4023 int q_idx;
021230d4 4024
5a85e737
ET		 4025 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
4026 ixgbe_qv_init_lock(adapter->q_vector[q_idx]);
49c7ffbe 4027 napi_enable(&adapter->q_vector[q_idx]->napi);
5a85e737 4028 }
021230d4
AV		 4029}
4030
4031static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
4032{
4033 int q_idx;
021230d4 4034
5a85e737 4035 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++) {
49c7ffbe 4036 napi_disable(&adapter->q_vector[q_idx]->napi);
27d9ce4f 4037 while (!ixgbe_qv_disable(adapter->q_vector[q_idx])) {
5a85e737 4038 pr_info("QV %d locked\n", q_idx);
27d9ce4f 4039 usleep_range(1000, 20000);
5a85e737
ET		 4040 }
4041 }
021230d4
AV		 4042}
4043
7a6b6f51 4044#ifdef CONFIG_IXGBE_DCB
49ce9c2c 4045/**
2f90b865
AD		 4046 * ixgbe_configure_dcb - Configure DCB hardware
4047 * @adapter: ixgbe adapter struct
4048 *
4049 * This is called by the driver on open to configure the DCB hardware.
4050 * This is also called by the gennetlink interface when reconfiguring
4051 * the DCB state.
4052 */
4053static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
4054{
4055 struct ixgbe_hw *hw = &adapter->hw;
9806307a 4056 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2f90b865 4057
67ebd791
AD		 4058 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
4059 if (hw->mac.type == ixgbe_mac_82598EB)
4060 netif_set_gso_max_size(adapter->netdev, 65536);
4061 return;
4062 }
4063
4064 if (hw->mac.type == ixgbe_mac_82598EB)
4065 netif_set_gso_max_size(adapter->netdev, 32768);
4066
971060b1 4067#ifdef IXGBE_FCOE
b120818e
JF		 4068 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
4069 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
c27931da 4070#endif
b120818e
JF		 4071
4072 /* reconfigure the hardware */
4073 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
c27931da
JF		 4074 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4075 DCB_TX_CONFIG);
4076 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
4077 DCB_RX_CONFIG);
4078 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
b120818e
JF		 4079 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
4080 ixgbe_dcb_hw_ets(&adapter->hw,
4081 adapter->ixgbe_ieee_ets,
4082 max_frame);
4083 ixgbe_dcb_hw_pfc_config(&adapter->hw,
4084 adapter->ixgbe_ieee_pfc->pfc_en,
4085 adapter->ixgbe_ieee_ets->prio_tc);
c27931da 4086 }
8187cd48
JF		 4087
4088 /* Enable RSS Hash per TC */
4089 if (hw->mac.type != ixgbe_mac_82598EB) {
4ae63730
AD		 4090 u32 msb = 0;
4091 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
8187cd48 4092
d411a936
AD		 4093 while (rss_i) {
4094 msb++;
4095 rss_i >>= 1;
4096 }
8187cd48 4097
4ae63730
AD		 4098 /* write msb to all 8 TCs in one write */
4099 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
8187cd48 4100 }
2f90b865 4101}
9da712d2
JF		 4102#endif
4103
4104/* Additional bittime to account for IXGBE framing */
4105#define IXGBE_ETH_FRAMING 20
4106
49ce9c2c 4107/**
9da712d2
JF		 4108 * ixgbe_hpbthresh - calculate high water mark for flow control
4109 *
4110 * @adapter: board private structure to calculate for
49ce9c2c 4111 * @pb: packet buffer to calculate
9da712d2
JF		 4112 */
4113static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
4114{
4115 struct ixgbe_hw *hw = &adapter->hw;
4116 struct net_device *dev = adapter->netdev;
4117 int link, tc, kb, marker;
4118 u32 dv_id, rx_pba;
4119
4120 /* Calculate max LAN frame size */
4121 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
4122
4123#ifdef IXGBE_FCOE
4124 /* FCoE traffic class uses FCOE jumbo frames */
800bd607
AD		 4125 if ((dev->features & NETIF_F_FCOE_MTU) &&
4126 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4127 (pb == ixgbe_fcoe_get_tc(adapter)))
4128 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
9da712d2 4129#endif
e5776620 4130
9da712d2
JF		 4131 /* Calculate delay value for device */
4132 switch (hw->mac.type) {
4133 case ixgbe_mac_X540:
4134 dv_id = IXGBE_DV_X540(link, tc);
4135 break;
4136 default:
4137 dv_id = IXGBE_DV(link, tc);
4138 break;
4139 }
4140
4141 /* Loopback switch introduces additional latency */
4142 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4143 dv_id += IXGBE_B2BT(tc);
4144
4145 /* Delay value is calculated in bit times convert to KB */
4146 kb = IXGBE_BT2KB(dv_id);
4147 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
4148
4149 marker = rx_pba - kb;
4150
4151 /* It is possible that the packet buffer is not large enough
4152 * to provide required headroom. In this case throw an error
4153 * to user and a do the best we can.
4154 */
4155 if (marker < 0) {
4156 e_warn(drv, "Packet Buffer(%i) can not provide enough"
4157 "headroom to support flow control."
4158 "Decrease MTU or number of traffic classes\n", pb);
4159 marker = tc + 1;
4160 }
4161
4162 return marker;
4163}
4164
49ce9c2c 4165/**
9da712d2
JF		 4166 * ixgbe_lpbthresh - calculate low water mark for for flow control
4167 *
4168 * @adapter: board private structure to calculate for
49ce9c2c 4169 * @pb: packet buffer to calculate
9da712d2 4170 */
e5776620 4171static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
9da712d2
JF		 4172{
4173 struct ixgbe_hw *hw = &adapter->hw;
4174 struct net_device *dev = adapter->netdev;
4175 int tc;
4176 u32 dv_id;
4177
4178 /* Calculate max LAN frame size */
4179 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
4180
e5776620
JK		 4181#ifdef IXGBE_FCOE
4182 /* FCoE traffic class uses FCOE jumbo frames */
4183 if ((dev->features & NETIF_F_FCOE_MTU) &&
4184 (tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) &&
4185 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
4186 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4187#endif
4188
9da712d2
JF		 4189 /* Calculate delay value for device */
4190 switch (hw->mac.type) {
4191 case ixgbe_mac_X540:
4192 dv_id = IXGBE_LOW_DV_X540(tc);
4193 break;
4194 default:
4195 dv_id = IXGBE_LOW_DV(tc);
4196 break;
4197 }
4198
4199 /* Delay value is calculated in bit times convert to KB */
4200 return IXGBE_BT2KB(dv_id);
4201}
4202
4203/*
4204 * ixgbe_pbthresh_setup - calculate and setup high low water marks
4205 */
4206static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
4207{
4208 struct ixgbe_hw *hw = &adapter->hw;
4209 int num_tc = netdev_get_num_tc(adapter->netdev);
4210 int i;
4211
4212 if (!num_tc)
4213 num_tc = 1;
4214
9da712d2
JF		 4215 for (i = 0; i < num_tc; i++) {
4216 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
e5776620 4217 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
9da712d2
JF		 4218
4219 /* Low water marks must not be larger than high water marks */
e5776620
JK		 4220 if (hw->fc.low_water[i] > hw->fc.high_water[i])
4221 hw->fc.low_water[i] = 0;
9da712d2 4222 }
e5776620
JK		 4223
4224 for (; i < MAX_TRAFFIC_CLASS; i++)
4225 hw->fc.high_water[i] = 0;
9da712d2
JF		 4226}
4227
80605c65
JF		 4228static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
4229{
80605c65 4230 struct ixgbe_hw *hw = &adapter->hw;
f7e1027f
AD		 4231 int hdrm;
4232 u8 tc = netdev_get_num_tc(adapter->netdev);
80605c65
JF		 4233
4234 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4235 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
f7e1027f
AD		 4236 hdrm = 32 << adapter->fdir_pballoc;
4237 else
4238 hdrm = 0;
80605c65 4239
f7e1027f 4240 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
9da712d2 4241 ixgbe_pbthresh_setup(adapter);
80605c65
JF		 4242}
4243
e4911d57
AD		 4244static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
4245{
4246 struct ixgbe_hw *hw = &adapter->hw;
b67bfe0d 4247 struct hlist_node *node2;
e4911d57
AD		 4248 struct ixgbe_fdir_filter *filter;
4249
4250 spin_lock(&adapter->fdir_perfect_lock);
4251
4252 if (!hlist_empty(&adapter->fdir_filter_list))
4253 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
4254
b67bfe0d 4255 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4256 &adapter->fdir_filter_list, fdir_node) {
4257 ixgbe_fdir_write_perfect_filter_82599(hw,
1f4d5183
AD		 4258 &filter->filter,
4259 filter->sw_idx,
4260 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
4261 IXGBE_FDIR_DROP_QUEUE :
4262 adapter->rx_ring[filter->action]->reg_idx);
e4911d57
AD		 4263 }
4264
4265 spin_unlock(&adapter->fdir_perfect_lock);
4266}
4267
2a47fa45
JF		 4268static void ixgbe_macvlan_set_rx_mode(struct net_device *dev, unsigned int pool,
4269 struct ixgbe_adapter *adapter)
4270{
4271 struct ixgbe_hw *hw = &adapter->hw;
4272 u32 vmolr;
4273
4274 /* No unicast promiscuous support for VMDQ devices. */
4275 vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(pool));
4276 vmolr |= (IXGBE_VMOLR_ROMPE | IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
4277
4278 /* clear the affected bit */
4279 vmolr &= ~IXGBE_VMOLR_MPE;
4280
4281 if (dev->flags & IFF_ALLMULTI) {
4282 vmolr |= IXGBE_VMOLR_MPE;
4283 } else {
4284 vmolr |= IXGBE_VMOLR_ROMPE;
4285 hw->mac.ops.update_mc_addr_list(hw, dev);
4286 }
4287 ixgbe_write_uc_addr_list(adapter->netdev);
4288 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(pool), vmolr);
4289}
4290
4291static void ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4292 u8 *addr, u16 pool)
4293{
4294 struct ixgbe_hw *hw = &adapter->hw;
4295 unsigned int entry;
4296
4297 entry = hw->mac.num_rar_entries - pool;
4298 hw->mac.ops.set_rar(hw, entry, addr, VMDQ_P(pool), IXGBE_RAH_AV);
4299}
4300
4301static void ixgbe_fwd_psrtype(struct ixgbe_fwd_adapter *vadapter)
4302{
4303 struct ixgbe_adapter *adapter = vadapter->real_adapter;
219354d4 4304 int rss_i = adapter->num_rx_queues_per_pool;
2a47fa45
JF		 4305 struct ixgbe_hw *hw = &adapter->hw;
4306 u16 pool = vadapter->pool;
4307 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4308 IXGBE_PSRTYPE_UDPHDR |
4309 IXGBE_PSRTYPE_IPV4HDR |
4310 IXGBE_PSRTYPE_L2HDR |
4311 IXGBE_PSRTYPE_IPV6HDR;
4312
4313 if (hw->mac.type == ixgbe_mac_82598EB)
4314 return;
4315
4316 if (rss_i > 3)
4317 psrtype |= 2 << 29;
4318 else if (rss_i > 1)
4319 psrtype |= 1 << 29;
4320
4321 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4322}
4323
4324/**
4325 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4326 * @rx_ring: ring to free buffers from
4327 **/
4328static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4329{
4330 struct device *dev = rx_ring->dev;
4331 unsigned long size;
4332 u16 i;
4333
4334 /* ring already cleared, nothing to do */
4335 if (!rx_ring->rx_buffer_info)
4336 return;
4337
4338 /* Free all the Rx ring sk_buffs */
4339 for (i = 0; i < rx_ring->count; i++) {
4340 struct ixgbe_rx_buffer *rx_buffer;
4341
4342 rx_buffer = &rx_ring->rx_buffer_info[i];
4343 if (rx_buffer->skb) {
4344 struct sk_buff *skb = rx_buffer->skb;
4345 if (IXGBE_CB(skb)->page_released) {
4346 dma_unmap_page(dev,
4347 IXGBE_CB(skb)->dma,
4348 ixgbe_rx_bufsz(rx_ring),
4349 DMA_FROM_DEVICE);
4350 IXGBE_CB(skb)->page_released = false;
4351 }
4352 dev_kfree_skb(skb);
4353 }
4354 rx_buffer->skb = NULL;
4355 if (rx_buffer->dma)
4356 dma_unmap_page(dev, rx_buffer->dma,
4357 ixgbe_rx_pg_size(rx_ring),
4358 DMA_FROM_DEVICE);
4359 rx_buffer->dma = 0;
4360 if (rx_buffer->page)
4361 __free_pages(rx_buffer->page,
4362 ixgbe_rx_pg_order(rx_ring));
4363 rx_buffer->page = NULL;
4364 }
4365
4366 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4367 memset(rx_ring->rx_buffer_info, 0, size);
4368
4369 /* Zero out the descriptor ring */
4370 memset(rx_ring->desc, 0, rx_ring->size);
4371
4372 rx_ring->next_to_alloc = 0;
4373 rx_ring->next_to_clean = 0;
4374 rx_ring->next_to_use = 0;
4375}
4376
4377static void ixgbe_disable_fwd_ring(struct ixgbe_fwd_adapter *vadapter,
4378 struct ixgbe_ring *rx_ring)
4379{
4380 struct ixgbe_adapter *adapter = vadapter->real_adapter;
4381 int index = rx_ring->queue_index + vadapter->rx_base_queue;
4382
4383 /* shutdown specific queue receive and wait for dma to settle */
4384 ixgbe_disable_rx_queue(adapter, rx_ring);
4385 usleep_range(10000, 20000);
4386 ixgbe_irq_disable_queues(adapter, ((u64)1 << index));
4387 ixgbe_clean_rx_ring(rx_ring);
4388 rx_ring->l2_accel_priv = NULL;
4389}
4390
ae72c8d0
JF		 4391static int ixgbe_fwd_ring_down(struct net_device *vdev,
4392 struct ixgbe_fwd_adapter *accel)
2a47fa45
JF		 4393{
4394 struct ixgbe_adapter *adapter = accel->real_adapter;
4395 unsigned int rxbase = accel->rx_base_queue;
4396 unsigned int txbase = accel->tx_base_queue;
4397 int i;
4398
4399 netif_tx_stop_all_queues(vdev);
4400
4401 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4402 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4403 adapter->rx_ring[rxbase + i]->netdev = adapter->netdev;
4404 }
4405
4406 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4407 adapter->tx_ring[txbase + i]->l2_accel_priv = NULL;
4408 adapter->tx_ring[txbase + i]->netdev = adapter->netdev;
4409 }
4410
4411
4412 return 0;
4413}
4414
4415static int ixgbe_fwd_ring_up(struct net_device *vdev,
4416 struct ixgbe_fwd_adapter *accel)
4417{
4418 struct ixgbe_adapter *adapter = accel->real_adapter;
4419 unsigned int rxbase, txbase, queues;
4420 int i, baseq, err = 0;
4421
4422 if (!test_bit(accel->pool, &adapter->fwd_bitmask))
4423 return 0;
4424
4425 baseq = accel->pool * adapter->num_rx_queues_per_pool;
4426 netdev_dbg(vdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
4427 accel->pool, adapter->num_rx_pools,
4428 baseq, baseq + adapter->num_rx_queues_per_pool,
4429 adapter->fwd_bitmask);
4430
4431 accel->netdev = vdev;
4432 accel->rx_base_queue = rxbase = baseq;
4433 accel->tx_base_queue = txbase = baseq;
4434
4435 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
4436 ixgbe_disable_fwd_ring(accel, adapter->rx_ring[rxbase + i]);
4437
4438 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4439 adapter->rx_ring[rxbase + i]->netdev = vdev;
4440 adapter->rx_ring[rxbase + i]->l2_accel_priv = accel;
4441 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[rxbase + i]);
4442 }
4443
4444 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
4445 adapter->tx_ring[txbase + i]->netdev = vdev;
4446 adapter->tx_ring[txbase + i]->l2_accel_priv = accel;
4447 }
4448
4449 queues = min_t(unsigned int,
4450 adapter->num_rx_queues_per_pool, vdev->num_tx_queues);
4451 err = netif_set_real_num_tx_queues(vdev, queues);
4452 if (err)
4453 goto fwd_queue_err;
4454
2a47fa45
JF		 4455 err = netif_set_real_num_rx_queues(vdev, queues);
4456 if (err)
4457 goto fwd_queue_err;
4458
4459 if (is_valid_ether_addr(vdev->dev_addr))
4460 ixgbe_add_mac_filter(adapter, vdev->dev_addr, accel->pool);
4461
4462 ixgbe_fwd_psrtype(accel);
4463 ixgbe_macvlan_set_rx_mode(vdev, accel->pool, adapter);
4464 return err;
4465fwd_queue_err:
4466 ixgbe_fwd_ring_down(vdev, accel);
4467 return err;
4468}
4469
4470static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
4471{
4472 struct net_device *upper;
4473 struct list_head *iter;
4474 int err;
4475
4476 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4477 if (netif_is_macvlan(upper)) {
4478 struct macvlan_dev *dfwd = netdev_priv(upper);
4479 struct ixgbe_fwd_adapter *vadapter = dfwd->fwd_priv;
4480
4481 if (dfwd->fwd_priv) {
4482 err = ixgbe_fwd_ring_up(upper, vadapter);
4483 if (err)
4484 continue;
4485 }
4486 }
4487 }
4488}
4489
9a799d71
AK		 4490static void ixgbe_configure(struct ixgbe_adapter *adapter)
4491{
d2f5e7f3
AS		 4492 struct ixgbe_hw *hw = &adapter->hw;
4493
80605c65 4494 ixgbe_configure_pb(adapter);
7a6b6f51 4495#ifdef CONFIG_IXGBE_DCB
67ebd791 4496 ixgbe_configure_dcb(adapter);
2f90b865 4497#endif
b35d4d42
AD		 4498 /*
4499 * We must restore virtualization before VLANs or else
4500 * the VLVF registers will not be populated
4501 */
4502 ixgbe_configure_virtualization(adapter);
9a799d71 4503
4c1d7b4b 4504 ixgbe_set_rx_mode(adapter->netdev);
f62bbb5e
JG		 4505 ixgbe_restore_vlan(adapter);
4506
d2f5e7f3
AS		 4507 switch (hw->mac.type) {
4508 case ixgbe_mac_82599EB:
4509 case ixgbe_mac_X540:
4510 hw->mac.ops.disable_rx_buff(hw);
4511 break;
4512 default:
4513 break;
4514 }
4515
c4cf55e5 4516 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4c1d7b4b
AD		 4517 ixgbe_init_fdir_signature_82599(&adapter->hw,
4518 adapter->fdir_pballoc);
e4911d57
AD		 4519 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
4520 ixgbe_init_fdir_perfect_82599(&adapter->hw,
4521 adapter->fdir_pballoc);
4522 ixgbe_fdir_filter_restore(adapter);
c4cf55e5 4523 }
4c1d7b4b 4524
d2f5e7f3
AS		 4525 switch (hw->mac.type) {
4526 case ixgbe_mac_82599EB:
4527 case ixgbe_mac_X540:
4528 hw->mac.ops.enable_rx_buff(hw);
4529 break;
4530 default:
4531 break;
4532 }
4533
7c8ae65a
AD		 4534#ifdef IXGBE_FCOE
4535 /* configure FCoE L2 filters, redirection table, and Rx control */
4536 ixgbe_configure_fcoe(adapter);
4537
4538#endif /* IXGBE_FCOE */
9a799d71
AK		 4539 ixgbe_configure_tx(adapter);
4540 ixgbe_configure_rx(adapter);
2a47fa45 4541 ixgbe_configure_dfwd(adapter);
9a799d71
AK		 4542}
4543
e8e26350
PW		 4544static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
4545{
4546 switch (hw->phy.type) {
4547 case ixgbe_phy_sfp_avago:
4548 case ixgbe_phy_sfp_ftl:
4549 case ixgbe_phy_sfp_intel:
4550 case ixgbe_phy_sfp_unknown:
ea0a04df
DS		 4551 case ixgbe_phy_sfp_passive_tyco:
4552 case ixgbe_phy_sfp_passive_unknown:
4553 case ixgbe_phy_sfp_active_unknown:
4554 case ixgbe_phy_sfp_ftl_active:
987e1d56
ET		 4555 case ixgbe_phy_qsfp_passive_unknown:
4556 case ixgbe_phy_qsfp_active_unknown:
4557 case ixgbe_phy_qsfp_intel:
4558 case ixgbe_phy_qsfp_unknown:
e8e26350 4559 return true;
8917b447
AD		 4560 case ixgbe_phy_nl:
4561 if (hw->mac.type == ixgbe_mac_82598EB)
4562 return true;
e8e26350
PW		 4563 default:
4564 return false;
4565 }
4566}
4567
0ecc061d 4568/**
e8e26350
PW		 4569 * ixgbe_sfp_link_config - set up SFP+ link
4570 * @adapter: pointer to private adapter struct
4571 **/
4572static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
4573{
7086400d 4574 /*
52f33af8 4575 * We are assuming the worst case scenario here, and that
7086400d
AD		 4576 * is that an SFP was inserted/removed after the reset
4577 * but before SFP detection was enabled. As such the best
4578 * solution is to just start searching as soon as we start
4579 */
4580 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
4581 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
e8e26350 4582
7086400d 4583 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
e8e26350
PW		 4584}
4585
4586/**
4587 * ixgbe_non_sfp_link_config - set up non-SFP+ link
0ecc061d
PWJ		 4588 * @hw: pointer to private hardware struct
4589 *
4590 * Returns 0 on success, negative on failure
4591 **/
e8e26350 4592static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
0ecc061d 4593{
3d292265
JH		 4594 u32 speed;
4595 bool autoneg, link_up = false;
0ecc061d
PWJ		 4596 u32 ret = IXGBE_ERR_LINK_SETUP;
4597
4598 if (hw->mac.ops.check_link)
3d292265 4599 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
0ecc061d
PWJ		 4600
4601 if (ret)
4602 goto link_cfg_out;
4603
3d292265
JH		 4604 speed = hw->phy.autoneg_advertised;
4605 if ((!speed) && (hw->mac.ops.get_link_capabilities))
4606 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
4607 &autoneg);
0ecc061d
PWJ		 4608 if (ret)
4609 goto link_cfg_out;
4610
8620a103 4611 if (hw->mac.ops.setup_link)
fd0326f2 4612 ret = hw->mac.ops.setup_link(hw, speed, link_up);
0ecc061d
PWJ		 4613link_cfg_out:
4614 return ret;
4615}
4616
a34bcfff 4617static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
9a799d71 4618{
9a799d71 4619 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4620 u32 gpie = 0;
9a799d71 4621
9b471446 4622 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
a34bcfff
AD		 4623 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
4624 IXGBE_GPIE_OCD;
4625 gpie |= IXGBE_GPIE_EIAME;
9b471446
JB		 4626 /*
4627 * use EIAM to auto-mask when MSI-X interrupt is asserted
4628 * this saves a register write for every interrupt
4629 */
4630 switch (hw->mac.type) {
4631 case ixgbe_mac_82598EB:
4632 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4633 break;
9b471446 4634 case ixgbe_mac_82599EB:
b93a2226
DS		 4635 case ixgbe_mac_X540:
4636 default:
9b471446
JB		 4637 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
4638 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
4639 break;
4640 }
4641 } else {
021230d4
AV		 4642 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
4643 * specifically only auto mask tx and rx interrupts */
4644 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
4645 }
9a799d71 4646
a34bcfff
AD		 4647 /* XXX: to interrupt immediately for EICS writes, enable this */
4648 /* gpie |= IXGBE_GPIE_EIMEN; */
4649
4650 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
4651 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
73079ea0
AD		 4652
4653 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4654 case IXGBE_82599_VMDQ_8Q_MASK:
4655 gpie |= IXGBE_GPIE_VTMODE_16;
4656 break;
4657 case IXGBE_82599_VMDQ_4Q_MASK:
4658 gpie |= IXGBE_GPIE_VTMODE_32;
4659 break;
4660 default:
4661 gpie |= IXGBE_GPIE_VTMODE_64;
4662 break;
4663 }
119fc60a
MC		 4664 }
4665
5fdd31f9 4666 /* Enable Thermal over heat sensor interrupt */
f3df98ec
DS		 4667 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
4668 switch (adapter->hw.mac.type) {
4669 case ixgbe_mac_82599EB:
4670 gpie |= IXGBE_SDP0_GPIEN;
4671 break;
4672 case ixgbe_mac_X540:
4673 gpie |= IXGBE_EIMS_TS;
4674 break;
4675 default:
4676 break;
4677 }
4678 }
5fdd31f9 4679
a34bcfff
AD		 4680 /* Enable fan failure interrupt */
4681 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
0befdb3e 4682 gpie |= IXGBE_SDP1_GPIEN;
0befdb3e 4683
2698b208 4684 if (hw->mac.type == ixgbe_mac_82599EB) {
e8e26350
PW		 4685 gpie |= IXGBE_SDP1_GPIEN;
4686 gpie |= IXGBE_SDP2_GPIEN;
2698b208 4687 }
a34bcfff
AD		 4688
4689 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
4690}
4691
c7ccde0f 4692static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
a34bcfff
AD		 4693{
4694 struct ixgbe_hw *hw = &adapter->hw;
a34bcfff 4695 int err;
a34bcfff
AD		 4696 u32 ctrl_ext;
4697
4698 ixgbe_get_hw_control(adapter);
4699 ixgbe_setup_gpie(adapter);
e8e26350 4700
9a799d71
AK		 4701 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4702 ixgbe_configure_msix(adapter);
4703 else
4704 ixgbe_configure_msi_and_legacy(adapter);
4705
ec74a471
ET		 4706 /* enable the optics for 82599 SFP+ fiber */
4707 if (hw->mac.ops.enable_tx_laser)
61fac744
PW		 4708 hw->mac.ops.enable_tx_laser(hw);
4709
c3049c8f 4710 smp_mb__before_clear_bit();
9a799d71 4711 clear_bit(__IXGBE_DOWN, &adapter->state);
021230d4
AV		 4712 ixgbe_napi_enable_all(adapter);
4713
73c4b7cd
AD		 4714 if (ixgbe_is_sfp(hw)) {
4715 ixgbe_sfp_link_config(adapter);
4716 } else {
4717 err = ixgbe_non_sfp_link_config(hw);
4718 if (err)
4719 e_err(probe, "link_config FAILED %d\n", err);
4720 }
4721
021230d4
AV		 4722 /* clear any pending interrupts, may auto mask */
4723 IXGBE_READ_REG(hw, IXGBE_EICR);
6af3b9eb 4724 ixgbe_irq_enable(adapter, true, true);
9a799d71 4725
bf069c97
DS		 4726 /*
4727 * If this adapter has a fan, check to see if we had a failure
4728 * before we enabled the interrupt.
4729 */
4730 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
4731 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
4732 if (esdp & IXGBE_ESDP_SDP1)
396e799c 4733 e_crit(drv, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 4734 }
4735
9a799d71
AK		 4736 /* bring the link up in the watchdog, this could race with our first
4737 * link up interrupt but shouldn't be a problem */
cf8280ee
JB		 4738 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4739 adapter->link_check_timeout = jiffies;
7086400d 4740 mod_timer(&adapter->service_timer, jiffies);
c9205697
GR		 4741
4742 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4743 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
4744 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
4745 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
9a799d71
AK		 4746}
4747
d4f80882
AV		 4748void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
4749{
4750 WARN_ON(in_interrupt());
7086400d
AD		 4751 /* put off any impending NetWatchDogTimeout */
4752 adapter->netdev->trans_start = jiffies;
4753
d4f80882 4754 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
032b4325 4755 usleep_range(1000, 2000);
d4f80882 4756 ixgbe_down(adapter);
5809a1ae
GR		 4757 /*
4758 * If SR-IOV enabled then wait a bit before bringing the adapter
4759 * back up to give the VFs time to respond to the reset. The
4760 * two second wait is based upon the watchdog timer cycle in
4761 * the VF driver.
4762 */
4763 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4764 msleep(2000);
d4f80882
AV		 4765 ixgbe_up(adapter);
4766 clear_bit(__IXGBE_RESETTING, &adapter->state);
4767}
4768
c7ccde0f 4769void ixgbe_up(struct ixgbe_adapter *adapter)
9a799d71
AK		 4770{
4771 /* hardware has been reset, we need to reload some things */
4772 ixgbe_configure(adapter);
4773
c7ccde0f 4774 ixgbe_up_complete(adapter);
9a799d71
AK		 4775}
4776
4777void ixgbe_reset(struct ixgbe_adapter *adapter)
4778{
c44ade9e 4779 struct ixgbe_hw *hw = &adapter->hw;
8ca783ab
DS		 4780 int err;
4781
b0483c8f
MR		 4782 if (ixgbe_removed(hw->hw_addr))
4783 return;
7086400d
AD		 4784 /* lock SFP init bit to prevent race conditions with the watchdog */
4785 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4786 usleep_range(1000, 2000);
4787
4788 /* clear all SFP and link config related flags while holding SFP_INIT */
4789 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4790 IXGBE_FLAG2_SFP_NEEDS_RESET);
4791 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4792
8ca783ab 4793 err = hw->mac.ops.init_hw(hw);
da4dd0f7
PWJ		 4794 switch (err) {
4795 case 0:
4796 case IXGBE_ERR_SFP_NOT_PRESENT:
7086400d 4797 case IXGBE_ERR_SFP_NOT_SUPPORTED:
da4dd0f7
PWJ		 4798 break;
4799 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
849c4542 4800 e_dev_err("master disable timed out\n");
da4dd0f7 4801 break;
794caeb2
PWJ		 4802 case IXGBE_ERR_EEPROM_VERSION:
4803 /* We are running on a pre-production device, log a warning */
849c4542 4804 e_dev_warn("This device is a pre-production adapter/LOM. "
52f33af8 4805 "Please be aware there may be issues associated with "
849c4542
ET		 4806 "your hardware. If you are experiencing problems "
4807 "please contact your Intel or hardware "
4808 "representative who provided you with this "
4809 "hardware.\n");
794caeb2 4810 break;
da4dd0f7 4811 default:
849c4542 4812 e_dev_err("Hardware Error: %d\n", err);
da4dd0f7 4813 }
9a799d71 4814
7086400d
AD		 4815 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4816
9a799d71 4817 /* reprogram the RAR[0] in case user changed it. */
1d9c0bfd 4818 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
7fa7c9dc
AD		 4819
4820 /* update SAN MAC vmdq pool selection */
4821 if (hw->mac.san_mac_rar_index)
4822 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
1a71ab24 4823
8fecf67c 4824 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 4825 ixgbe_ptp_reset(adapter);
9a799d71
AK		 4826}
4827
9a799d71
AK		 4828/**
4829 * ixgbe_clean_tx_ring - Free Tx Buffers
9a799d71
AK		 4830 * @tx_ring: ring to be cleaned
4831 **/
b6ec895e 4832static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
9a799d71
AK		 4833{
4834 struct ixgbe_tx_buffer *tx_buffer_info;
4835 unsigned long size;
b6ec895e 4836 u16 i;
9a799d71 4837
84418e3b
AD		 4838 /* ring already cleared, nothing to do */
4839 if (!tx_ring->tx_buffer_info)
4840 return;
9a799d71 4841
84418e3b 4842 /* Free all the Tx ring sk_buffs */
9a799d71
AK		 4843 for (i = 0; i < tx_ring->count; i++) {
4844 tx_buffer_info = &tx_ring->tx_buffer_info[i];
b6ec895e 4845 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
9a799d71
AK		 4846 }
4847
dad8a3b3
JF		 4848 netdev_tx_reset_queue(txring_txq(tx_ring));
4849
9a799d71
AK		 4850 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4851 memset(tx_ring->tx_buffer_info, 0, size);
4852
4853 /* Zero out the descriptor ring */
4854 memset(tx_ring->desc, 0, tx_ring->size);
4855
4856 tx_ring->next_to_use = 0;
4857 tx_ring->next_to_clean = 0;
9a799d71
AK		 4858}
4859
4860/**
021230d4 4861 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
9a799d71
AK		 4862 * @adapter: board private structure
4863 **/
021230d4 4864static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4865{
4866 int i;
4867
021230d4 4868 for (i = 0; i < adapter->num_rx_queues; i++)
b6ec895e 4869 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
9a799d71
AK		 4870}
4871
4872/**
021230d4 4873 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
9a799d71
AK		 4874 * @adapter: board private structure
4875 **/
021230d4 4876static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
9a799d71
AK		 4877{
4878 int i;
4879
021230d4 4880 for (i = 0; i < adapter->num_tx_queues; i++)
b6ec895e 4881 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
9a799d71
AK		 4882}
4883
e4911d57
AD		 4884static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4885{
b67bfe0d 4886 struct hlist_node *node2;
e4911d57
AD		 4887 struct ixgbe_fdir_filter *filter;
4888
4889 spin_lock(&adapter->fdir_perfect_lock);
4890
b67bfe0d 4891 hlist_for_each_entry_safe(filter, node2,
e4911d57
AD		 4892 &adapter->fdir_filter_list, fdir_node) {
4893 hlist_del(&filter->fdir_node);
4894 kfree(filter);
4895 }
4896 adapter->fdir_filter_count = 0;
4897
4898 spin_unlock(&adapter->fdir_perfect_lock);
4899}
4900
9a799d71
AK		 4901void ixgbe_down(struct ixgbe_adapter *adapter)
4902{
4903 struct net_device *netdev = adapter->netdev;
7f821875 4904 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45
JF		 4905 struct net_device *upper;
4906 struct list_head *iter;
9a799d71 4907 u32 rxctrl;
bf29ee6c 4908 int i;
9a799d71
AK		 4909
4910 /* signal that we are down to the interrupt handler */
c3049c8f
MR		 4911 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
4912 return; /* do nothing if already down */
9a799d71
AK		 4913
4914 /* disable receives */
7f821875
JB		 4915 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4916 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
9a799d71 4917
2d39d576
YZ		 4918 /* disable all enabled rx queues */
4919 for (i = 0; i < adapter->num_rx_queues; i++)
4920 /* this call also flushes the previous write */
4921 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4922
032b4325 4923 usleep_range(10000, 20000);
9a799d71 4924
7f821875
JB		 4925 netif_tx_stop_all_queues(netdev);
4926
7086400d 4927 /* call carrier off first to avoid false dev_watchdog timeouts */
c0dfb90e
JF		 4928 netif_carrier_off(netdev);
4929 netif_tx_disable(netdev);
4930
2a47fa45
JF		 4931 /* disable any upper devices */
4932 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
4933 if (netif_is_macvlan(upper)) {
4934 struct macvlan_dev *vlan = netdev_priv(upper);
4935
4936 if (vlan->fwd_priv) {
4937 netif_tx_stop_all_queues(upper);
4938 netif_carrier_off(upper);
4939 netif_tx_disable(upper);
4940 }
4941 }
4942 }
4943
c0dfb90e
JF		 4944 ixgbe_irq_disable(adapter);
4945
4946 ixgbe_napi_disable_all(adapter);
4947
d034acf1
AD		 4948 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4949 IXGBE_FLAG2_RESET_REQUESTED);
7086400d
AD		 4950 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4951
4952 del_timer_sync(&adapter->service_timer);
4953
34cecbbf 4954 if (adapter->num_vfs) {
8e34d1aa
AD		 4955 /* Clear EITR Select mapping */
4956 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
34cecbbf
AD		 4957
4958 /* Mark all the VFs as inactive */
4959 for (i = 0 ; i < adapter->num_vfs; i++)
3db1cd5c 4960 adapter->vfinfo[i].clear_to_send = false;
34cecbbf 4961
34cecbbf
AD		 4962 /* ping all the active vfs to let them know we are going down */
4963 ixgbe_ping_all_vfs(adapter);
4964
4965 /* Disable all VFTE/VFRE TX/RX */
4966 ixgbe_disable_tx_rx(adapter);
b25ebfd2
PW		 4967 }
4968
7f821875
JB		 4969 /* disable transmits in the hardware now that interrupts are off */
4970 for (i = 0; i < adapter->num_tx_queues; i++) {
bf29ee6c 4971 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
34cecbbf 4972 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
7f821875 4973 }
34cecbbf
AD		 4974
4975 /* Disable the Tx DMA engine on 82599 and X540 */
bd508178
AD		 4976 switch (hw->mac.type) {
4977 case ixgbe_mac_82599EB:
b93a2226 4978 case ixgbe_mac_X540:
88512539 4979 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
e8e9f696
JP		 4980 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4981 ~IXGBE_DMATXCTL_TE));
bd508178
AD		 4982 break;
4983 default:
4984 break;
4985 }
7f821875 4986
6f4a0e45
PL		 4987 if (!pci_channel_offline(adapter->pdev))
4988 ixgbe_reset(adapter);
c6ecf39a 4989
ec74a471
ET		 4990 /* power down the optics for 82599 SFP+ fiber */
4991 if (hw->mac.ops.disable_tx_laser)
c6ecf39a
DS		 4992 hw->mac.ops.disable_tx_laser(hw);
4993
9a799d71
AK		 4994 ixgbe_clean_all_tx_rings(adapter);
4995 ixgbe_clean_all_rx_rings(adapter);
4996
5dd2d332 4997#ifdef CONFIG_IXGBE_DCA
96b0e0f6 4998 /* since we reset the hardware DCA settings were cleared */
e35ec126 4999 ixgbe_setup_dca(adapter);
96b0e0f6 5000#endif
9a799d71
AK		 5001}
5002
9a799d71
AK		 5003/**
5004 * ixgbe_tx_timeout - Respond to a Tx Hang
5005 * @netdev: network interface device structure
5006 **/
5007static void ixgbe_tx_timeout(struct net_device *netdev)
5008{
5009 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5010
5011 /* Do the reset outside of interrupt context */
c83c6cbd 5012 ixgbe_tx_timeout_reset(adapter);
9a799d71
AK		 5013}
5014
9a799d71
AK		 5015/**
5016 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5017 * @adapter: board private structure to initialize
5018 *
5019 * ixgbe_sw_init initializes the Adapter private data structure.
5020 * Fields are initialized based on PCI device information and
5021 * OS network device settings (MTU size).
5022 **/
9f9a12f8 5023static int ixgbe_sw_init(struct ixgbe_adapter *adapter)
9a799d71
AK		 5024{
5025 struct ixgbe_hw *hw = &adapter->hw;
5026 struct pci_dev *pdev = adapter->pdev;
d3cb9869 5027 unsigned int rss, fdir;
cb6d0f5e 5028 u32 fwsm;
7a6b6f51 5029#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 5030 int j;
5031 struct tc_configuration *tc;
5032#endif
021230d4 5033
c44ade9e
JB		 5034 /* PCI config space info */
5035
5036 hw->vendor_id = pdev->vendor;
5037 hw->device_id = pdev->device;
5038 hw->revision_id = pdev->revision;
5039 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5040 hw->subsystem_device_id = pdev->subsystem_device;
5041
8fc3bb6d 5042 /* Set common capability flags and settings */
3ed69d7e 5043 rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus());
c087663e 5044 adapter->ring_feature[RING_F_RSS].limit = rss;
8fc3bb6d
ET		 5045 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5046 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
8fc3bb6d
ET		 5047 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
5048 adapter->atr_sample_rate = 20;
d3cb9869
AD		 5049 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
5050 adapter->ring_feature[RING_F_FDIR].limit = fdir;
8fc3bb6d
ET		 5051 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5052#ifdef CONFIG_IXGBE_DCA
5053 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
5054#endif
5055#ifdef IXGBE_FCOE
5056 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5057 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5058#ifdef CONFIG_IXGBE_DCB
5059 /* Default traffic class to use for FCoE */
5060 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5061#endif /* CONFIG_IXGBE_DCB */
5062#endif /* IXGBE_FCOE */
5063
5064 /* Set MAC specific capability flags and exceptions */
bd508178
AD		 5065 switch (hw->mac.type) {
5066 case ixgbe_mac_82598EB:
8fc3bb6d
ET		 5067 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
5068 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
5069
bf069c97
DS		 5070 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5071 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
8fc3bb6d 5072
49c7ffbe 5073 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
8fc3bb6d
ET		 5074 adapter->ring_feature[RING_F_FDIR].limit = 0;
5075 adapter->atr_sample_rate = 0;
5076 adapter->fdir_pballoc = 0;
5077#ifdef IXGBE_FCOE
5078 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5079 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5080#ifdef CONFIG_IXGBE_DCB
5081 adapter->fcoe.up = 0;
5082#endif /* IXGBE_DCB */
5083#endif /* IXGBE_FCOE */
5084 break;
5085 case ixgbe_mac_82599EB:
5086 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5087 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178 5088 break;
b93a2226 5089 case ixgbe_mac_X540:
cb6d0f5e
JK		 5090 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
5091 if (fwsm & IXGBE_FWSM_TS_ENABLED)
5092 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
bd508178
AD		 5093 break;
5094 default:
5095 break;
f8212f97 5096 }
2f90b865 5097
7c8ae65a
AD		 5098#ifdef IXGBE_FCOE
5099 /* FCoE support exists, always init the FCoE lock */
5100 spin_lock_init(&adapter->fcoe.lock);
5101
5102#endif
1fc5f038
AD		 5103 /* n-tuple support exists, always init our spinlock */
5104 spin_lock_init(&adapter->fdir_perfect_lock);
5105
7a6b6f51 5106#ifdef CONFIG_IXGBE_DCB
4de2a022
JF		 5107 switch (hw->mac.type) {
5108 case ixgbe_mac_X540:
5109 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
5110 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
5111 break;
5112 default:
5113 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
5114 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
5115 break;
5116 }
5117
2f90b865
AD		 5118 /* Configure DCB traffic classes */
5119 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5120 tc = &adapter->dcb_cfg.tc_config[j];
5121 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5122 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5123 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5124 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5125 tc->dcb_pfc = pfc_disabled;
5126 }
4de2a022
JF		 5127
5128 /* Initialize default user to priority mapping, UPx->TC0 */
5129 tc = &adapter->dcb_cfg.tc_config[0];
5130 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
5131 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
5132
2f90b865
AD		 5133 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5134 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
264857b8 5135 adapter->dcb_cfg.pfc_mode_enable = false;
2f90b865 5136 adapter->dcb_set_bitmap = 0x00;
3032309b 5137 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
f525c6d2
JF		 5138 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
5139 sizeof(adapter->temp_dcb_cfg));
2f90b865
AD		 5140
5141#endif
9a799d71
AK		 5142
5143 /* default flow control settings */
cd7664f6 5144 hw->fc.requested_mode = ixgbe_fc_full;
71fd570b 5145 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
9da712d2 5146 ixgbe_pbthresh_setup(adapter);
2b9ade93
JB		 5147 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5148 hw->fc.send_xon = true;
73d80953 5149 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
9a799d71 5150
99d74487 5151#ifdef CONFIG_PCI_IOV
170e8543
JK		 5152 if (max_vfs > 0)
5153 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
5154
99d74487 5155 /* assign number of SR-IOV VFs */
170e8543 5156 if (hw->mac.type != ixgbe_mac_82598EB) {
dcc23e3a 5157 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
170e8543
JK		 5158 adapter->num_vfs = 0;
5159 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
5160 } else {
5161 adapter->num_vfs = max_vfs;
5162 }
5163 }
5164#endif /* CONFIG_PCI_IOV */
99d74487 5165
30efa5a3 5166 /* enable itr by default in dynamic mode */
f7554a2b 5167 adapter->rx_itr_setting = 1;
f7554a2b 5168 adapter->tx_itr_setting = 1;
30efa5a3 5169
30efa5a3
JB		 5170 /* set default ring sizes */
5171 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5172 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5173
bd198058 5174 /* set default work limits */
59224555 5175 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
bd198058 5176
9a799d71 5177 /* initialize eeprom parameters */
c44ade9e 5178 if (ixgbe_init_eeprom_params_generic(hw)) {
849c4542 5179 e_dev_err("EEPROM initialization failed\n");
9a799d71
AK		 5180 return -EIO;
5181 }
5182
2a47fa45
JF		 5183 /* PF holds first pool slot */
5184 set_bit(0, &adapter->fwd_bitmask);
9a799d71
AK		 5185 set_bit(__IXGBE_DOWN, &adapter->state);
5186
5187 return 0;
5188}
5189
5190/**
5191 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3a581073 5192 * @tx_ring: tx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5193 *
5194 * Return 0 on success, negative on failure
5195 **/
b6ec895e 5196int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5197{
b6ec895e 5198 struct device *dev = tx_ring->dev;
de88eeeb
AD		 5199 int orig_node = dev_to_node(dev);
5200 int numa_node = -1;
9a799d71
AK		 5201 int size;
5202
3a581073 5203 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
de88eeeb
AD		 5204
5205 if (tx_ring->q_vector)
5206 numa_node = tx_ring->q_vector->numa_node;
5207
5208 tx_ring->tx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5209 if (!tx_ring->tx_buffer_info)
89bf67f1 5210 tx_ring->tx_buffer_info = vzalloc(size);
e01c31a5
JB		 5211 if (!tx_ring->tx_buffer_info)
5212 goto err;
9a799d71 5213
827da44c
JS		 5214 u64_stats_init(&tx_ring->syncp);
5215
9a799d71 5216 /* round up to nearest 4K */
12207e49 5217 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3a581073 5218 tx_ring->size = ALIGN(tx_ring->size, 4096);
9a799d71 5219
de88eeeb
AD		 5220 set_dev_node(dev, numa_node);
5221 tx_ring->desc = dma_alloc_coherent(dev,
5222 tx_ring->size,
5223 &tx_ring->dma,
5224 GFP_KERNEL);
5225 set_dev_node(dev, orig_node);
5226 if (!tx_ring->desc)
5227 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5228 &tx_ring->dma, GFP_KERNEL);
e01c31a5
JB		 5229 if (!tx_ring->desc)
5230 goto err;
9a799d71 5231
3a581073
JB		 5232 tx_ring->next_to_use = 0;
5233 tx_ring->next_to_clean = 0;
9a799d71 5234 return 0;
e01c31a5
JB		 5235
5236err:
5237 vfree(tx_ring->tx_buffer_info);
5238 tx_ring->tx_buffer_info = NULL;
b6ec895e 5239 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
e01c31a5 5240 return -ENOMEM;
9a799d71
AK		 5241}
5242
69888674
AD		 5243/**
5244 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5245 * @adapter: board private structure
5246 *
5247 * If this function returns with an error, then it's possible one or
5248 * more of the rings is populated (while the rest are not). It is the
5249 * callers duty to clean those orphaned rings.
5250 *
5251 * Return 0 on success, negative on failure
5252 **/
5253static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5254{
5255 int i, err = 0;
5256
5257 for (i = 0; i < adapter->num_tx_queues; i++) {
b6ec895e 5258 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5259 if (!err)
5260 continue;
de3d5b94 5261
396e799c 5262 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
de3d5b94 5263 goto err_setup_tx;
69888674
AD		 5264 }
5265
de3d5b94
AD		 5266 return 0;
5267err_setup_tx:
5268 /* rewind the index freeing the rings as we go */
5269 while (i--)
5270 ixgbe_free_tx_resources(adapter->tx_ring[i]);
69888674
AD		 5271 return err;
5272}
5273
9a799d71
AK		 5274/**
5275 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3a581073 5276 * @rx_ring: rx descriptor ring (for a specific queue) to setup
9a799d71
AK		 5277 *
5278 * Returns 0 on success, negative on failure
5279 **/
b6ec895e 5280int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5281{
b6ec895e 5282 struct device *dev = rx_ring->dev;
de88eeeb
AD		 5283 int orig_node = dev_to_node(dev);
5284 int numa_node = -1;
021230d4 5285 int size;
9a799d71 5286
3a581073 5287 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
de88eeeb
AD		 5288
5289 if (rx_ring->q_vector)
5290 numa_node = rx_ring->q_vector->numa_node;
5291
5292 rx_ring->rx_buffer_info = vzalloc_node(size, numa_node);
1a6c14a2 5293 if (!rx_ring->rx_buffer_info)
89bf67f1 5294 rx_ring->rx_buffer_info = vzalloc(size);
b6ec895e
AD		 5295 if (!rx_ring->rx_buffer_info)
5296 goto err;
9a799d71 5297
827da44c
JS		 5298 u64_stats_init(&rx_ring->syncp);
5299
9a799d71 5300 /* Round up to nearest 4K */
3a581073
JB		 5301 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5302 rx_ring->size = ALIGN(rx_ring->size, 4096);
9a799d71 5303
de88eeeb
AD		 5304 set_dev_node(dev, numa_node);
5305 rx_ring->desc = dma_alloc_coherent(dev,
5306 rx_ring->size,
5307 &rx_ring->dma,
5308 GFP_KERNEL);
5309 set_dev_node(dev, orig_node);
5310 if (!rx_ring->desc)
5311 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5312 &rx_ring->dma, GFP_KERNEL);
b6ec895e
AD		 5313 if (!rx_ring->desc)
5314 goto err;
9a799d71 5315
3a581073
JB		 5316 rx_ring->next_to_clean = 0;
5317 rx_ring->next_to_use = 0;
9a799d71
AK		 5318
5319 return 0;
b6ec895e
AD		 5320err:
5321 vfree(rx_ring->rx_buffer_info);
5322 rx_ring->rx_buffer_info = NULL;
5323 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
177db6ff 5324 return -ENOMEM;
9a799d71
AK		 5325}
5326
69888674
AD		 5327/**
5328 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5329 * @adapter: board private structure
5330 *
5331 * If this function returns with an error, then it's possible one or
5332 * more of the rings is populated (while the rest are not). It is the
5333 * callers duty to clean those orphaned rings.
5334 *
5335 * Return 0 on success, negative on failure
5336 **/
69888674
AD		 5337static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5338{
5339 int i, err = 0;
5340
5341 for (i = 0; i < adapter->num_rx_queues; i++) {
b6ec895e 5342 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5343 if (!err)
5344 continue;
de3d5b94 5345
396e799c 5346 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
de3d5b94 5347 goto err_setup_rx;
69888674
AD		 5348 }
5349
7c8ae65a
AD		 5350#ifdef IXGBE_FCOE
5351 err = ixgbe_setup_fcoe_ddp_resources(adapter);
5352 if (!err)
5353#endif
5354 return 0;
de3d5b94
AD		 5355err_setup_rx:
5356 /* rewind the index freeing the rings as we go */
5357 while (i--)
5358 ixgbe_free_rx_resources(adapter->rx_ring[i]);
69888674
AD		 5359 return err;
5360}
5361
9a799d71
AK		 5362/**
5363 * ixgbe_free_tx_resources - Free Tx Resources per Queue
9a799d71
AK		 5364 * @tx_ring: Tx descriptor ring for a specific queue
5365 *
5366 * Free all transmit software resources
5367 **/
b6ec895e 5368void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
9a799d71 5369{
b6ec895e 5370 ixgbe_clean_tx_ring(tx_ring);
9a799d71
AK		 5371
5372 vfree(tx_ring->tx_buffer_info);
5373 tx_ring->tx_buffer_info = NULL;
5374
b6ec895e
AD		 5375 /* if not set, then don't free */
5376 if (!tx_ring->desc)
5377 return;
5378
5379 dma_free_coherent(tx_ring->dev, tx_ring->size,
5380 tx_ring->desc, tx_ring->dma);
9a799d71
AK		 5381
5382 tx_ring->desc = NULL;
5383}
5384
5385/**
5386 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5387 * @adapter: board private structure
5388 *
5389 * Free all transmit software resources
5390 **/
5391static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5392{
5393 int i;
5394
5395 for (i = 0; i < adapter->num_tx_queues; i++)
4a0b9ca0 5396 if (adapter->tx_ring[i]->desc)
b6ec895e 5397 ixgbe_free_tx_resources(adapter->tx_ring[i]);
9a799d71
AK		 5398}
5399
5400/**
b4617240 5401 * ixgbe_free_rx_resources - Free Rx Resources
9a799d71
AK		 5402 * @rx_ring: ring to clean the resources from
5403 *
5404 * Free all receive software resources
5405 **/
b6ec895e 5406void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
9a799d71 5407{
b6ec895e 5408 ixgbe_clean_rx_ring(rx_ring);
9a799d71
AK		 5409
5410 vfree(rx_ring->rx_buffer_info);
5411 rx_ring->rx_buffer_info = NULL;
5412
b6ec895e
AD		 5413 /* if not set, then don't free */
5414 if (!rx_ring->desc)
5415 return;
5416
5417 dma_free_coherent(rx_ring->dev, rx_ring->size,
5418 rx_ring->desc, rx_ring->dma);
9a799d71
AK		 5419
5420 rx_ring->desc = NULL;
5421}
5422
5423/**
5424 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5425 * @adapter: board private structure
5426 *
5427 * Free all receive software resources
5428 **/
5429static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5430{
5431 int i;
5432
7c8ae65a
AD		 5433#ifdef IXGBE_FCOE
5434 ixgbe_free_fcoe_ddp_resources(adapter);
5435
5436#endif
9a799d71 5437 for (i = 0; i < adapter->num_rx_queues; i++)
4a0b9ca0 5438 if (adapter->rx_ring[i]->desc)
b6ec895e 5439 ixgbe_free_rx_resources(adapter->rx_ring[i]);
9a799d71
AK		 5440}
5441
9a799d71
AK		 5442/**
5443 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5444 * @netdev: network interface device structure
5445 * @new_mtu: new value for maximum frame size
5446 *
5447 * Returns 0 on success, negative on failure
5448 **/
5449static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5450{
5451 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5452 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5453
42c783c5 5454 /* MTU < 68 is an error and causes problems on some kernels */
655309e9
AD		 5455 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5456 return -EINVAL;
5457
5458 /*
872844dd
AD		 5459 * For 82599EB we cannot allow legacy VFs to enable their receive
5460 * paths when MTU greater than 1500 is configured. So display a
5461 * warning that legacy VFs will be disabled.
655309e9
AD		 5462 */
5463 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
5464 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
c560451c 5465 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
872844dd 5466 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
9a799d71 5467
396e799c 5468 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
655309e9 5469
021230d4 5470 /* must set new MTU before calling down or up */
9a799d71
AK		 5471 netdev->mtu = new_mtu;
5472
d4f80882
AV		 5473 if (netif_running(netdev))
5474 ixgbe_reinit_locked(adapter);
9a799d71
AK		 5475
5476 return 0;
5477}
5478
5479/**
5480 * ixgbe_open - Called when a network interface is made active
5481 * @netdev: network interface device structure
5482 *
5483 * Returns 0 on success, negative value on failure
5484 *
5485 * The open entry point is called when a network interface is made
5486 * active by the system (IFF_UP). At this point all resources needed
5487 * for transmit and receive operations are allocated, the interrupt
5488 * handler is registered with the OS, the watchdog timer is started,
5489 * and the stack is notified that the interface is ready.
5490 **/
5491static int ixgbe_open(struct net_device *netdev)
5492{
5493 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2a47fa45 5494 int err, queues;
4bebfaa5
AK		 5495
5496 /* disallow open during test */
5497 if (test_bit(__IXGBE_TESTING, &adapter->state))
5498 return -EBUSY;
9a799d71 5499
54386467
JB		 5500 netif_carrier_off(netdev);
5501
9a799d71
AK		 5502 /* allocate transmit descriptors */
5503 err = ixgbe_setup_all_tx_resources(adapter);
5504 if (err)
5505 goto err_setup_tx;
5506
9a799d71
AK		 5507 /* allocate receive descriptors */
5508 err = ixgbe_setup_all_rx_resources(adapter);
5509 if (err)
5510 goto err_setup_rx;
5511
5512 ixgbe_configure(adapter);
5513
021230d4 5514 err = ixgbe_request_irq(adapter);
9a799d71
AK		 5515 if (err)
5516 goto err_req_irq;
5517
ac802f5d 5518 /* Notify the stack of the actual queue counts. */
2a47fa45
JF		 5519 if (adapter->num_rx_pools > 1)
5520 queues = adapter->num_rx_queues_per_pool;
5521 else
5522 queues = adapter->num_tx_queues;
5523
5524 err = netif_set_real_num_tx_queues(netdev, queues);
ac802f5d
AD		 5525 if (err)
5526 goto err_set_queues;
5527
2a47fa45
JF		 5528 if (adapter->num_rx_pools > 1 &&
5529 adapter->num_rx_queues > IXGBE_MAX_L2A_QUEUES)
5530 queues = IXGBE_MAX_L2A_QUEUES;
5531 else
5532 queues = adapter->num_rx_queues;
5533 err = netif_set_real_num_rx_queues(netdev, queues);
ac802f5d
AD		 5534 if (err)
5535 goto err_set_queues;
5536
1a71ab24 5537 ixgbe_ptp_init(adapter);
1a71ab24 5538
c7ccde0f 5539 ixgbe_up_complete(adapter);
9a799d71
AK		 5540
5541 return 0;
5542
ac802f5d
AD		 5543err_set_queues:
5544 ixgbe_free_irq(adapter);
9a799d71 5545err_req_irq:
a20a1199 5546 ixgbe_free_all_rx_resources(adapter);
de3d5b94 5547err_setup_rx:
a20a1199 5548 ixgbe_free_all_tx_resources(adapter);
de3d5b94 5549err_setup_tx:
9a799d71
AK		 5550 ixgbe_reset(adapter);
5551
5552 return err;
5553}
5554
5555/**
5556 * ixgbe_close - Disables a network interface
5557 * @netdev: network interface device structure
5558 *
5559 * Returns 0, this is not allowed to fail
5560 *
5561 * The close entry point is called when an interface is de-activated
5562 * by the OS. The hardware is still under the drivers control, but
5563 * needs to be disabled. A global MAC reset is issued to stop the
5564 * hardware, and all transmit and receive resources are freed.
5565 **/
5566static int ixgbe_close(struct net_device *netdev)
5567{
5568 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9a799d71 5569
1a71ab24 5570 ixgbe_ptp_stop(adapter);
1a71ab24 5571
9a799d71
AK		 5572 ixgbe_down(adapter);
5573 ixgbe_free_irq(adapter);
5574
e4911d57
AD		 5575 ixgbe_fdir_filter_exit(adapter);
5576
9a799d71
AK		 5577 ixgbe_free_all_tx_resources(adapter);
5578 ixgbe_free_all_rx_resources(adapter);
5579
5eba3699 5580 ixgbe_release_hw_control(adapter);
9a799d71
AK		 5581
5582 return 0;
5583}
5584
b3c8b4ba
AD		 5585#ifdef CONFIG_PM
5586static int ixgbe_resume(struct pci_dev *pdev)
5587{
c60fbb00
AD		 5588 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5589 struct net_device *netdev = adapter->netdev;
b3c8b4ba
AD		 5590 u32 err;
5591
0391bbe3 5592 adapter->hw.hw_addr = adapter->io_addr;
b3c8b4ba
AD		 5593 pci_set_power_state(pdev, PCI_D0);
5594 pci_restore_state(pdev);
656ab817
DS		 5595 /*
5596 * pci_restore_state clears dev->state_saved so call
5597 * pci_save_state to restore it.
5598 */
5599 pci_save_state(pdev);
9ce77666 5600
5601 err = pci_enable_device_mem(pdev);
b3c8b4ba 5602 if (err) {
849c4542 5603 e_dev_err("Cannot enable PCI device from suspend\n");
b3c8b4ba
AD		 5604 return err;
5605 }
41c62843
MR		 5606 smp_mb__before_clear_bit();
5607 clear_bit(__IXGBE_DISABLED, &adapter->state);
b3c8b4ba
AD		 5608 pci_set_master(pdev);
5609
dd4d8ca6 5610 pci_wake_from_d3(pdev, false);
b3c8b4ba 5611
b3c8b4ba
AD		 5612 ixgbe_reset(adapter);
5613
495dce12
WJP		 5614 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5615
ac802f5d
AD		 5616 rtnl_lock();
5617 err = ixgbe_init_interrupt_scheme(adapter);
5618 if (!err && netif_running(netdev))
c60fbb00 5619 err = ixgbe_open(netdev);
ac802f5d
AD		 5620
5621 rtnl_unlock();
5622
5623 if (err)
5624 return err;
b3c8b4ba
AD		 5625
5626 netif_device_attach(netdev);
5627
5628 return 0;
5629}
b3c8b4ba 5630#endif /* CONFIG_PM */
9d8d05ae
RW		 5631
5632static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
b3c8b4ba 5633{
c60fbb00
AD		 5634 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5635 struct net_device *netdev = adapter->netdev;
e8e26350
PW		 5636 struct ixgbe_hw *hw = &adapter->hw;
5637 u32 ctrl, fctrl;
5638 u32 wufc = adapter->wol;
b3c8b4ba
AD		 5639#ifdef CONFIG_PM
5640 int retval = 0;
5641#endif
5642
5643 netif_device_detach(netdev);
5644
499ab5cc 5645 rtnl_lock();
b3c8b4ba
AD		 5646 if (netif_running(netdev)) {
5647 ixgbe_down(adapter);
5648 ixgbe_free_irq(adapter);
5649 ixgbe_free_all_tx_resources(adapter);
5650 ixgbe_free_all_rx_resources(adapter);
5651 }
499ab5cc 5652 rtnl_unlock();
b3c8b4ba 5653
5f5ae6fc
AD		 5654 ixgbe_clear_interrupt_scheme(adapter);
5655
b3c8b4ba
AD		 5656#ifdef CONFIG_PM
5657 retval = pci_save_state(pdev);
5658 if (retval)
5659 return retval;
4df10466 5660
b3c8b4ba 5661#endif
f4f1040a
JK		 5662 if (hw->mac.ops.stop_link_on_d3)
5663 hw->mac.ops.stop_link_on_d3(hw);
5664
e8e26350
PW		 5665 if (wufc) {
5666 ixgbe_set_rx_mode(netdev);
b3c8b4ba 5667
ec74a471
ET		 5668 /* enable the optics for 82599 SFP+ fiber as we can WoL */
5669 if (hw->mac.ops.enable_tx_laser)
c509e754
DS		 5670 hw->mac.ops.enable_tx_laser(hw);
5671
e8e26350
PW		 5672 /* turn on all-multi mode if wake on multicast is enabled */
5673 if (wufc & IXGBE_WUFC_MC) {
5674 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5675 fctrl |= IXGBE_FCTRL_MPE;
5676 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5677 }
5678
5679 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5680 ctrl |= IXGBE_CTRL_GIO_DIS;
5681 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5682
5683 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5684 } else {
5685 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5686 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5687 }
5688
bd508178
AD		 5689 switch (hw->mac.type) {
5690 case ixgbe_mac_82598EB:
dd4d8ca6 5691 pci_wake_from_d3(pdev, false);
bd508178
AD		 5692 break;
5693 case ixgbe_mac_82599EB:
b93a2226 5694 case ixgbe_mac_X540:
bd508178
AD		 5695 pci_wake_from_d3(pdev, !!wufc);
5696 break;
5697 default:
5698 break;
5699 }
b3c8b4ba 5700
9d8d05ae
RW		 5701 *enable_wake = !!wufc;
5702
b3c8b4ba
AD		 5703 ixgbe_release_hw_control(adapter);
5704
41c62843
MR		 5705 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
5706 pci_disable_device(pdev);
b3c8b4ba 5707
9d8d05ae
RW		 5708 return 0;
5709}
5710
5711#ifdef CONFIG_PM
5712static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5713{
5714 int retval;
5715 bool wake;
5716
5717 retval = __ixgbe_shutdown(pdev, &wake);
5718 if (retval)
5719 return retval;
5720
5721 if (wake) {
5722 pci_prepare_to_sleep(pdev);
5723 } else {
5724 pci_wake_from_d3(pdev, false);
5725 pci_set_power_state(pdev, PCI_D3hot);
5726 }
b3c8b4ba
AD		 5727
5728 return 0;
5729}
9d8d05ae 5730#endif /* CONFIG_PM */
b3c8b4ba
AD		 5731
5732static void ixgbe_shutdown(struct pci_dev *pdev)
5733{
9d8d05ae
RW		 5734 bool wake;
5735
5736 __ixgbe_shutdown(pdev, &wake);
5737
5738 if (system_state == SYSTEM_POWER_OFF) {
5739 pci_wake_from_d3(pdev, wake);
5740 pci_set_power_state(pdev, PCI_D3hot);
5741 }
b3c8b4ba
AD		 5742}
5743
9a799d71
AK		 5744/**
5745 * ixgbe_update_stats - Update the board statistics counters.
5746 * @adapter: board private structure
5747 **/
5748void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5749{
2d86f139 5750 struct net_device *netdev = adapter->netdev;
9a799d71 5751 struct ixgbe_hw *hw = &adapter->hw;
5b7da515 5752 struct ixgbe_hw_stats *hwstats = &adapter->stats;
6f11eef7
AV		 5753 u64 total_mpc = 0;
5754 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5b7da515
AD		 5755 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5756 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
8a0da21b 5757 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
9a799d71 5758
d08935c2
DS		 5759 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5760 test_bit(__IXGBE_RESETTING, &adapter->state))
5761 return;
5762
94b982b2 5763 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
f8212f97 5764 u64 rsc_count = 0;
94b982b2 5765 u64 rsc_flush = 0;
94b982b2 5766 for (i = 0; i < adapter->num_rx_queues; i++) {
5b7da515
AD		 5767 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5768 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
94b982b2
MC		 5769 }
5770 adapter->rsc_total_count = rsc_count;
5771 adapter->rsc_total_flush = rsc_flush;
d51019a4
PW		 5772 }
5773
5b7da515
AD		 5774 for (i = 0; i < adapter->num_rx_queues; i++) {
5775 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5776 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5777 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5778 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
8a0da21b 5779 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
5b7da515
AD		 5780 bytes += rx_ring->stats.bytes;
5781 packets += rx_ring->stats.packets;
5782 }
5783 adapter->non_eop_descs = non_eop_descs;
5784 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5785 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
8a0da21b 5786 adapter->hw_csum_rx_error = hw_csum_rx_error;
5b7da515
AD		 5787 netdev->stats.rx_bytes = bytes;
5788 netdev->stats.rx_packets = packets;
5789
5790 bytes = 0;
5791 packets = 0;
7ca3bc58 5792 /* gather some stats to the adapter struct that are per queue */
5b7da515
AD		 5793 for (i = 0; i < adapter->num_tx_queues; i++) {
5794 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5795 restart_queue += tx_ring->tx_stats.restart_queue;
5796 tx_busy += tx_ring->tx_stats.tx_busy;
5797 bytes += tx_ring->stats.bytes;
5798 packets += tx_ring->stats.packets;
5799 }
eb985f09 5800 adapter->restart_queue = restart_queue;
5b7da515
AD		 5801 adapter->tx_busy = tx_busy;
5802 netdev->stats.tx_bytes = bytes;
5803 netdev->stats.tx_packets = packets;
7ca3bc58 5804
7ca647bd 5805 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
1a70db4b
ET		 5806
5807 /* 8 register reads */
6f11eef7
AV		 5808 for (i = 0; i < 8; i++) {
5809 /* for packet buffers not used, the register should read 0 */
5810 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5811 missed_rx += mpc;
7ca647bd
JP		 5812 hwstats->mpc[i] += mpc;
5813 total_mpc += hwstats->mpc[i];
1a70db4b
ET		 5814 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5815 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
bd508178
AD		 5816 switch (hw->mac.type) {
5817 case ixgbe_mac_82598EB:
1a70db4b
ET		 5818 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5819 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5820 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7ca647bd
JP		 5821 hwstats->pxonrxc[i] +=
5822 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
bd508178
AD		 5823 break;
5824 case ixgbe_mac_82599EB:
b93a2226 5825 case ixgbe_mac_X540:
bd508178
AD		 5826 hwstats->pxonrxc[i] +=
5827 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
bd508178
AD		 5828 break;
5829 default:
5830 break;
e8e26350 5831 }
6f11eef7 5832 }
1a70db4b
ET		 5833
5834 /*16 register reads */
5835 for (i = 0; i < 16; i++) {
5836 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5837 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5838 if ((hw->mac.type == ixgbe_mac_82599EB) ||
5839 (hw->mac.type == ixgbe_mac_X540)) {
5840 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
5841 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
5842 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
5843 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
5844 }
5845 }
5846
7ca647bd 5847 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
6f11eef7 5848 /* work around hardware counting issue */
7ca647bd 5849 hwstats->gprc -= missed_rx;
6f11eef7 5850
c84d324c
JF		 5851 ixgbe_update_xoff_received(adapter);
5852
6f11eef7 5853 /* 82598 hardware only has a 32 bit counter in the high register */
bd508178
AD		 5854 switch (hw->mac.type) {
5855 case ixgbe_mac_82598EB:
5856 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
bd508178
AD		 5857 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5858 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5859 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5860 break;
b93a2226 5861 case ixgbe_mac_X540:
58f6bcf9
ET		 5862 /* OS2BMC stats are X540 only*/
5863 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5864 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5865 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5866 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5867 case ixgbe_mac_82599EB:
a4d4f629
AD		 5868 for (i = 0; i < 16; i++)
5869 adapter->hw_rx_no_dma_resources +=
5870 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7ca647bd 5871 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
bd508178 5872 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7ca647bd 5873 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
bd508178 5874 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7ca647bd 5875 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
bd508178 5876 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7ca647bd 5877 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7ca647bd
JP		 5878 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5879 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
6d45522c 5880#ifdef IXGBE_FCOE
7ca647bd
JP		 5881 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5882 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5883 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5884 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5885 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5886 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7b859ebc 5887 /* Add up per cpu counters for total ddp aloc fail */
5a1ee270
AD		 5888 if (adapter->fcoe.ddp_pool) {
5889 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
5890 struct ixgbe_fcoe_ddp_pool *ddp_pool;
5891 unsigned int cpu;
5892 u64 noddp = 0, noddp_ext_buff = 0;
7b859ebc 5893 for_each_possible_cpu(cpu) {
5a1ee270
AD		 5894 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
5895 noddp += ddp_pool->noddp;
5896 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7b859ebc 5897 }
5a1ee270
AD		 5898 hwstats->fcoe_noddp = noddp;
5899 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7b859ebc 5900 }
6d45522c 5901#endif /* IXGBE_FCOE */
bd508178
AD		 5902 break;
5903 default:
5904 break;
e8e26350 5905 }
9a799d71 5906 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7ca647bd
JP		 5907 hwstats->bprc += bprc;
5908 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
e8e26350 5909 if (hw->mac.type == ixgbe_mac_82598EB)
7ca647bd
JP		 5910 hwstats->mprc -= bprc;
5911 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5912 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5913 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5914 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5915 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5916 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5917 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5918 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
6f11eef7 5919 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7ca647bd 5920 hwstats->lxontxc += lxon;
6f11eef7 5921 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7ca647bd 5922 hwstats->lxofftxc += lxoff;
7ca647bd
JP		 5923 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5924 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
6f11eef7
AV		 5925 /*
5926 * 82598 errata - tx of flow control packets is included in tx counters
5927 */
5928 xon_off_tot = lxon + lxoff;
7ca647bd
JP		 5929 hwstats->gptc -= xon_off_tot;
5930 hwstats->mptc -= xon_off_tot;
5931 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5932 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5933 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5934 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5935 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5936 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5937 hwstats->ptc64 -= xon_off_tot;
5938 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5939 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5940 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5941 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5942 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5943 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
9a799d71
AK		 5944
5945 /* Fill out the OS statistics structure */
7ca647bd 5946 netdev->stats.multicast = hwstats->mprc;
9a799d71
AK		 5947
5948 /* Rx Errors */
7ca647bd 5949 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
2d86f139 5950 netdev->stats.rx_dropped = 0;
7ca647bd
JP		 5951 netdev->stats.rx_length_errors = hwstats->rlec;
5952 netdev->stats.rx_crc_errors = hwstats->crcerrs;
2d86f139 5953 netdev->stats.rx_missed_errors = total_mpc;
9a799d71
AK		 5954}
5955
5956/**
d034acf1 5957 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
49ce9c2c 5958 * @adapter: pointer to the device adapter structure
9a799d71 5959 **/
d034acf1 5960static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
9a799d71 5961{
cf8280ee 5962 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a 5963 int i;
cf8280ee 5964
d034acf1
AD		 5965 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5966 return;
5967
5968 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
22d5a71b 5969
d034acf1 5970 /* if interface is down do nothing */
fe49f04a 5971 if (test_bit(__IXGBE_DOWN, &adapter->state))
d034acf1
AD		 5972 return;
5973
5974 /* do nothing if we are not using signature filters */
5975 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5976 return;
5977
5978 adapter->fdir_overflow++;
5979
93c52dd0
AD		 5980 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5981 for (i = 0; i < adapter->num_tx_queues; i++)
5982 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
f0f9778d 5983 &(adapter->tx_ring[i]->state));
d034acf1
AD		 5984 /* re-enable flow director interrupts */
5985 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
93c52dd0
AD		 5986 } else {
5987 e_err(probe, "failed to finish FDIR re-initialization, "
5988 "ignored adding FDIR ATR filters\n");
5989 }
93c52dd0
AD		 5990}
5991
5992/**
5993 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
49ce9c2c 5994 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 5995 *
5996 * This function serves two purposes. First it strobes the interrupt lines
52f33af8 5997 * in order to make certain interrupts are occurring. Secondly it sets the
93c52dd0 5998 * bits needed to check for TX hangs. As a result we should immediately
52f33af8 5999 * determine if a hang has occurred.
93c52dd0
AD		 6000 */
6001static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
9a799d71 6002{
cf8280ee 6003 struct ixgbe_hw *hw = &adapter->hw;
fe49f04a
AD		 6004 u64 eics = 0;
6005 int i;
cf8280ee 6006
09f40aed 6007 /* If we're down, removing or resetting, just bail */
93c52dd0 6008 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6009 test_bit(__IXGBE_REMOVING, &adapter->state) ||
93c52dd0
AD		 6010 test_bit(__IXGBE_RESETTING, &adapter->state))
6011 return;
22d5a71b 6012
93c52dd0
AD		 6013 /* Force detection of hung controller */
6014 if (netif_carrier_ok(adapter->netdev)) {
6015 for (i = 0; i < adapter->num_tx_queues; i++)
6016 set_check_for_tx_hang(adapter->tx_ring[i]);
6017 }
22d5a71b 6018
fe49f04a
AD		 6019 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
6020 /*
6021 * for legacy and MSI interrupts don't set any bits
6022 * that are enabled for EIAM, because this operation
6023 * would set *both* EIMS and EICS for any bit in EIAM
6024 */
6025 IXGBE_WRITE_REG(hw, IXGBE_EICS,
6026 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
93c52dd0
AD		 6027 } else {
6028 /* get one bit for every active tx/rx interrupt vector */
49c7ffbe 6029 for (i = 0; i < adapter->num_q_vectors; i++) {
93c52dd0 6030 struct ixgbe_q_vector *qv = adapter->q_vector[i];
efe3d3c8 6031 if (qv->rx.ring || qv->tx.ring)
93c52dd0
AD		 6032 eics |= ((u64)1 << i);
6033 }
cf8280ee 6034 }
9a799d71 6035
93c52dd0 6036 /* Cause software interrupt to ensure rings are cleaned */
fe49f04a
AD		 6037 ixgbe_irq_rearm_queues(adapter, eics);
6038
cf8280ee
JB		 6039}
6040
e8e26350 6041/**
93c52dd0 6042 * ixgbe_watchdog_update_link - update the link status
49ce9c2c
BH		 6043 * @adapter: pointer to the device adapter structure
6044 * @link_speed: pointer to a u32 to store the link_speed
e8e26350 6045 **/
93c52dd0 6046static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
e8e26350 6047{
e8e26350 6048 struct ixgbe_hw *hw = &adapter->hw;
93c52dd0
AD		 6049 u32 link_speed = adapter->link_speed;
6050 bool link_up = adapter->link_up;
041441d0 6051 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
e8e26350 6052
93c52dd0
AD		 6053 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6054 return;
6055
6056 if (hw->mac.ops.check_link) {
6057 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
c4cf55e5 6058 } else {
93c52dd0
AD		 6059 /* always assume link is up, if no check link function */
6060 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6061 link_up = true;
c4cf55e5 6062 }
041441d0
AD		 6063
6064 if (adapter->ixgbe_ieee_pfc)
6065 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
6066
3ebe8fde 6067 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
041441d0 6068 hw->mac.ops.fc_enable(hw);
3ebe8fde
AD		 6069 ixgbe_set_rx_drop_en(adapter);
6070 }
93c52dd0
AD		 6071
6072 if (link_up ||
6073 time_after(jiffies, (adapter->link_check_timeout +
6074 IXGBE_TRY_LINK_TIMEOUT))) {
6075 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6076 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6077 IXGBE_WRITE_FLUSH(hw);
6078 }
6079
6080 adapter->link_up = link_up;
6081 adapter->link_speed = link_speed;
e8e26350
PW		 6082}
6083
107d3018
AD		 6084static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
6085{
6086#ifdef CONFIG_IXGBE_DCB
6087 struct net_device *netdev = adapter->netdev;
6088 struct dcb_app app = {
6089 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
6090 .protocol = 0,
6091 };
6092 u8 up = 0;
6093
6094 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
6095 up = dcb_ieee_getapp_mask(netdev, &app);
6096
6097 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
6098#endif
6099}
6100
e8e26350 6101/**
93c52dd0
AD		 6102 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6103 * print link up message
49ce9c2c 6104 * @adapter: pointer to the device adapter structure
e8e26350 6105 **/
93c52dd0 6106static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
e8e26350 6107{
93c52dd0 6108 struct net_device *netdev = adapter->netdev;
e8e26350 6109 struct ixgbe_hw *hw = &adapter->hw;
cdc04dcc
ET		 6110 struct net_device *upper;
6111 struct list_head *iter;
93c52dd0
AD		 6112 u32 link_speed = adapter->link_speed;
6113 bool flow_rx, flow_tx;
e8e26350 6114
93c52dd0
AD		 6115 /* only continue if link was previously down */
6116 if (netif_carrier_ok(netdev))
a985b6c3 6117 return;
63d6e1d8 6118
93c52dd0 6119 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
63d6e1d8 6120
93c52dd0
AD		 6121 switch (hw->mac.type) {
6122 case ixgbe_mac_82598EB: {
6123 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6124 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6125 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6126 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6127 }
6128 break;
6129 case ixgbe_mac_X540:
6130 case ixgbe_mac_82599EB: {
6131 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6132 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6133 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6134 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6135 }
6136 break;
6137 default:
6138 flow_tx = false;
6139 flow_rx = false;
6140 break;
e8e26350 6141 }
3a6a4eda 6142
6cb562d6
JK		 6143 adapter->last_rx_ptp_check = jiffies;
6144
8fecf67c 6145 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6146 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6147
93c52dd0
AD		 6148 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6149 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6150 "10 Gbps" :
6151 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6152 "1 Gbps" :
6153 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6154 "100 Mbps" :
6155 "unknown speed"))),
6156 ((flow_rx && flow_tx) ? "RX/TX" :
6157 (flow_rx ? "RX" :
6158 (flow_tx ? "TX" : "None"))));
e8e26350 6159
93c52dd0 6160 netif_carrier_on(netdev);
93c52dd0 6161 ixgbe_check_vf_rate_limit(adapter);
befa2af7 6162
cdc04dcc
ET		 6163 /* enable transmits */
6164 netif_tx_wake_all_queues(adapter->netdev);
6165
6166 /* enable any upper devices */
6167 rtnl_lock();
6168 netdev_for_each_all_upper_dev_rcu(adapter->netdev, upper, iter) {
6169 if (netif_is_macvlan(upper)) {
6170 struct macvlan_dev *vlan = netdev_priv(upper);
6171
6172 if (vlan->fwd_priv)
6173 netif_tx_wake_all_queues(upper);
6174 }
6175 }
6176 rtnl_unlock();
6177
107d3018
AD		 6178 /* update the default user priority for VFs */
6179 ixgbe_update_default_up(adapter);
6180
befa2af7
AD		 6181 /* ping all the active vfs to let them know link has changed */
6182 ixgbe_ping_all_vfs(adapter);
e8e26350
PW		 6183}
6184
c4cf55e5 6185/**
93c52dd0
AD		 6186 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6187 * print link down message
49ce9c2c 6188 * @adapter: pointer to the adapter structure
c4cf55e5 6189 **/
581330ba 6190static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
c4cf55e5 6191{
cf8280ee 6192 struct net_device *netdev = adapter->netdev;
c4cf55e5 6193 struct ixgbe_hw *hw = &adapter->hw;
10eec955 6194
93c52dd0
AD		 6195 adapter->link_up = false;
6196 adapter->link_speed = 0;
cf8280ee 6197
93c52dd0
AD		 6198 /* only continue if link was up previously */
6199 if (!netif_carrier_ok(netdev))
6200 return;
264857b8 6201
93c52dd0
AD		 6202 /* poll for SFP+ cable when link is down */
6203 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6204 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
9a799d71 6205
8fecf67c 6206 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1a71ab24 6207 ixgbe_ptp_start_cyclecounter(adapter);
3a6a4eda 6208
93c52dd0
AD		 6209 e_info(drv, "NIC Link is Down\n");
6210 netif_carrier_off(netdev);
befa2af7
AD		 6211
6212 /* ping all the active vfs to let them know link has changed */
6213 ixgbe_ping_all_vfs(adapter);
93c52dd0 6214}
e8e26350 6215
93c52dd0
AD		 6216/**
6217 * ixgbe_watchdog_flush_tx - flush queues on link down
49ce9c2c 6218 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6219 **/
6220static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6221{
c4cf55e5 6222 int i;
93c52dd0 6223 int some_tx_pending = 0;
c4cf55e5 6224
93c52dd0 6225 if (!netif_carrier_ok(adapter->netdev)) {
bc59fcda 6226 for (i = 0; i < adapter->num_tx_queues; i++) {
93c52dd0 6227 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
bc59fcda
NS		 6228 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6229 some_tx_pending = 1;
6230 break;
6231 }
6232 }
6233
6234 if (some_tx_pending) {
6235 /* We've lost link, so the controller stops DMA,
6236 * but we've got queued Tx work that's never going
6237 * to get done, so reset controller to flush Tx.
6238 * (Do the reset outside of interrupt context).
6239 */
12ff3f3b 6240 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
c83c6cbd 6241 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
bc59fcda 6242 }
c4cf55e5 6243 }
c4cf55e5
PWJ		 6244}
6245
a985b6c3
GR		 6246static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6247{
6248 u32 ssvpc;
6249
0584d999
GR		 6250 /* Do not perform spoof check for 82598 or if not in IOV mode */
6251 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
6252 adapter->num_vfs == 0)
a985b6c3
GR		 6253 return;
6254
6255 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6256
6257 /*
6258 * ssvpc register is cleared on read, if zero then no
6259 * spoofed packets in the last interval.
6260 */
6261 if (!ssvpc)
6262 return;
6263
d6ea0754 6264 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
a985b6c3
GR		 6265}
6266
93c52dd0
AD		 6267/**
6268 * ixgbe_watchdog_subtask - check and bring link up
49ce9c2c 6269 * @adapter: pointer to the device adapter structure
93c52dd0
AD		 6270 **/
6271static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6272{
09f40aed 6273 /* if interface is down, removing or resetting, do nothing */
7edebf9a 6274 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6275 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7edebf9a 6276 test_bit(__IXGBE_RESETTING, &adapter->state))
93c52dd0
AD		 6277 return;
6278
6279 ixgbe_watchdog_update_link(adapter);
6280
6281 if (adapter->link_up)
6282 ixgbe_watchdog_link_is_up(adapter);
6283 else
6284 ixgbe_watchdog_link_is_down(adapter);
bc59fcda 6285
a985b6c3 6286 ixgbe_spoof_check(adapter);
9a799d71 6287 ixgbe_update_stats(adapter);
93c52dd0
AD		 6288
6289 ixgbe_watchdog_flush_tx(adapter);
9a799d71 6290}
10eec955 6291
cf8280ee 6292/**
7086400d 6293 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
49ce9c2c 6294 * @adapter: the ixgbe adapter structure
cf8280ee 6295 **/
7086400d 6296static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
cf8280ee 6297{
cf8280ee 6298 struct ixgbe_hw *hw = &adapter->hw;
7086400d 6299 s32 err;
cf8280ee 6300
7086400d
AD		 6301 /* not searching for SFP so there is nothing to do here */
6302 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6303 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6304 return;
10eec955 6305
7086400d
AD		 6306 /* someone else is in init, wait until next service event */
6307 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6308 return;
cf8280ee 6309
7086400d
AD		 6310 err = hw->phy.ops.identify_sfp(hw);
6311 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6312 goto sfp_out;
264857b8 6313
7086400d
AD		 6314 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6315 /* If no cable is present, then we need to reset
6316 * the next time we find a good cable. */
6317 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
cf8280ee 6318 }
9a799d71 6319
7086400d
AD		 6320 /* exit on error */
6321 if (err)
6322 goto sfp_out;
e8e26350 6323
7086400d
AD		 6324 /* exit if reset not needed */
6325 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6326 goto sfp_out;
9a799d71 6327
7086400d 6328 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
bc59fcda 6329
7086400d
AD		 6330 /*
6331 * A module may be identified correctly, but the EEPROM may not have
6332 * support for that module. setup_sfp() will fail in that case, so
6333 * we should not allow that module to load.
6334 */
6335 if (hw->mac.type == ixgbe_mac_82598EB)
6336 err = hw->phy.ops.reset(hw);
6337 else
6338 err = hw->mac.ops.setup_sfp(hw);
6339
6340 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6341 goto sfp_out;
6342
6343 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6344 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6345
6346sfp_out:
6347 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6348
6349 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6350 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6351 e_dev_err("failed to initialize because an unsupported "
6352 "SFP+ module type was detected.\n");
6353 e_dev_err("Reload the driver after installing a "
6354 "supported module.\n");
6355 unregister_netdev(adapter->netdev);
bc59fcda 6356 }
7086400d 6357}
bc59fcda 6358
7086400d
AD		 6359/**
6360 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
49ce9c2c 6361 * @adapter: the ixgbe adapter structure
7086400d
AD		 6362 **/
6363static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6364{
6365 struct ixgbe_hw *hw = &adapter->hw;
3d292265
JH		 6366 u32 speed;
6367 bool autoneg = false;
7086400d
AD		 6368
6369 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6370 return;
6371
6372 /* someone else is in init, wait until next service event */
6373 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6374 return;
6375
6376 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6377
3d292265 6378 speed = hw->phy.autoneg_advertised;
ed33ff66 6379 if ((!speed) && (hw->mac.ops.get_link_capabilities)) {
3d292265 6380 hw->mac.ops.get_link_capabilities(hw, &speed, &autoneg);
ed33ff66
ET		 6381
6382 /* setup the highest link when no autoneg */
6383 if (!autoneg) {
6384 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
6385 speed = IXGBE_LINK_SPEED_10GB_FULL;
6386 }
6387 }
6388
7086400d 6389 if (hw->mac.ops.setup_link)
fd0326f2 6390 hw->mac.ops.setup_link(hw, speed, true);
7086400d
AD		 6391
6392 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6393 adapter->link_check_timeout = jiffies;
6394 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6395}
6396
83c61fa9
GR		 6397#ifdef CONFIG_PCI_IOV
6398static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
6399{
6400 int vf;
6401 struct ixgbe_hw *hw = &adapter->hw;
6402 struct net_device *netdev = adapter->netdev;
6403 u32 gpc;
6404 u32 ciaa, ciad;
6405
6406 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
6407 if (gpc) /* If incrementing then no need for the check below */
6408 return;
6409 /*
6410 * Check to see if a bad DMA write target from an errant or
6411 * malicious VF has caused a PCIe error. If so then we can
6412 * issue a VFLR to the offending VF(s) and then resume without
6413 * requesting a full slot reset.
6414 */
6415
6416 for (vf = 0; vf < adapter->num_vfs; vf++) {
6417 ciaa = (vf << 16) | 0x80000000;
6418 /* 32 bit read so align, we really want status at offset 6 */
6419 ciaa |= PCI_COMMAND;
6420 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6421 ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599);
6422 ciaa &= 0x7FFFFFFF;
6423 /* disable debug mode asap after reading data */
6424 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6425 /* Get the upper 16 bits which will be the PCI status reg */
6426 ciad >>= 16;
6427 if (ciad & PCI_STATUS_REC_MASTER_ABORT) {
6428 netdev_err(netdev, "VF %d Hung DMA\n", vf);
6429 /* Issue VFLR */
6430 ciaa = (vf << 16) | 0x80000000;
6431 ciaa |= 0xA8;
6432 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6433 ciad = 0x00008000; /* VFLR */
6434 IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad);
6435 ciaa &= 0x7FFFFFFF;
6436 IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa);
6437 }
6438 }
6439}
6440
6441#endif
7086400d
AD		 6442/**
6443 * ixgbe_service_timer - Timer Call-back
6444 * @data: pointer to adapter cast into an unsigned long
6445 **/
6446static void ixgbe_service_timer(unsigned long data)
6447{
6448 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6449 unsigned long next_event_offset;
83c61fa9 6450 bool ready = true;
7086400d 6451
6bb78cfb
AD		 6452 /* poll faster when waiting for link */
6453 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6454 next_event_offset = HZ / 10;
6455 else
6456 next_event_offset = HZ * 2;
83c61fa9 6457
6bb78cfb 6458#ifdef CONFIG_PCI_IOV
83c61fa9
GR		 6459 /*
6460 * don't bother with SR-IOV VF DMA hang check if there are
6461 * no VFs or the link is down
6462 */
6463 if (!adapter->num_vfs ||
6bb78cfb 6464 (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
83c61fa9 6465 goto normal_timer_service;
83c61fa9
GR		 6466
6467 /* If we have VFs allocated then we must check for DMA hangs */
6468 ixgbe_check_for_bad_vf(adapter);
6469 next_event_offset = HZ / 50;
6470 adapter->timer_event_accumulator++;
6471
6bb78cfb 6472 if (adapter->timer_event_accumulator >= 100)
83c61fa9 6473 adapter->timer_event_accumulator = 0;
7086400d 6474 else
6bb78cfb 6475 ready = false;
7086400d 6476
6bb78cfb 6477normal_timer_service:
83c61fa9 6478#endif
7086400d
AD		 6479 /* Reset the timer */
6480 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6481
83c61fa9
GR		 6482 if (ready)
6483 ixgbe_service_event_schedule(adapter);
7086400d
AD		 6484}
6485
c83c6cbd
AD		 6486static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6487{
6488 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6489 return;
6490
6491 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6492
09f40aed 6493 /* If we're already down, removing or resetting, just bail */
c83c6cbd 6494 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
09f40aed 6495 test_bit(__IXGBE_REMOVING, &adapter->state) ||
c83c6cbd
AD		 6496 test_bit(__IXGBE_RESETTING, &adapter->state))
6497 return;
6498
6499 ixgbe_dump(adapter);
6500 netdev_err(adapter->netdev, "Reset adapter\n");
6501 adapter->tx_timeout_count++;
6502
8f4c5c9f 6503 rtnl_lock();
c83c6cbd 6504 ixgbe_reinit_locked(adapter);
8f4c5c9f 6505 rtnl_unlock();
c83c6cbd
AD		 6506}
6507
7086400d
AD		 6508/**
6509 * ixgbe_service_task - manages and runs subtasks
6510 * @work: pointer to work_struct containing our data
6511 **/
6512static void ixgbe_service_task(struct work_struct *work)
6513{
6514 struct ixgbe_adapter *adapter = container_of(work,
6515 struct ixgbe_adapter,
6516 service_task);
b0483c8f
MR		 6517 if (ixgbe_removed(adapter->hw.hw_addr)) {
6518 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
6519 rtnl_lock();
6520 ixgbe_down(adapter);
6521 rtnl_unlock();
6522 }
6523 ixgbe_service_event_complete(adapter);
6524 return;
6525 }
c83c6cbd 6526 ixgbe_reset_subtask(adapter);
7086400d
AD		 6527 ixgbe_sfp_detection_subtask(adapter);
6528 ixgbe_sfp_link_config_subtask(adapter);
f0f9778d 6529 ixgbe_check_overtemp_subtask(adapter);
93c52dd0 6530 ixgbe_watchdog_subtask(adapter);
d034acf1 6531 ixgbe_fdir_reinit_subtask(adapter);
93c52dd0 6532 ixgbe_check_hang_subtask(adapter);
891dc082 6533
8fecf67c 6534 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
891dc082
JK		 6535 ixgbe_ptp_overflow_check(adapter);
6536 ixgbe_ptp_rx_hang(adapter);
6537 }
7086400d
AD		 6538
6539 ixgbe_service_event_complete(adapter);
9a799d71
AK		 6540}
6541
fd0db0ed
AD		 6542static int ixgbe_tso(struct ixgbe_ring *tx_ring,
6543 struct ixgbe_tx_buffer *first,
244e27ad 6544 u8 *hdr_len)
897ab156 6545{
fd0db0ed 6546 struct sk_buff *skb = first->skb;
897ab156
AD		 6547 u32 vlan_macip_lens, type_tucmd;
6548 u32 mss_l4len_idx, l4len;
2049e1f6 6549 int err;
9a799d71 6550
8f4fbb9b
AD		 6551 if (skb->ip_summed != CHECKSUM_PARTIAL)
6552 return 0;
6553
897ab156
AD		 6554 if (!skb_is_gso(skb))
6555 return 0;
9a799d71 6556
2049e1f6
FR		 6557 err = skb_cow_head(skb, 0);
6558 if (err < 0)
6559 return err;
9a799d71 6560
897ab156
AD		 6561 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6562 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6563
a1108ffd 6564 if (first->protocol == htons(ETH_P_IP)) {
897ab156
AD		 6565 struct iphdr *iph = ip_hdr(skb);
6566 iph->tot_len = 0;
6567 iph->check = 0;
6568 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6569 iph->daddr, 0,
6570 IPPROTO_TCP,
6571 0);
6572 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
244e27ad
AD		 6573 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6574 IXGBE_TX_FLAGS_CSUM |
6575 IXGBE_TX_FLAGS_IPV4;
897ab156
AD		 6576 } else if (skb_is_gso_v6(skb)) {
6577 ipv6_hdr(skb)->payload_len = 0;
6578 tcp_hdr(skb)->check =
6579 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6580 &ipv6_hdr(skb)->daddr,
6581 0, IPPROTO_TCP, 0);
244e27ad
AD		 6582 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
6583 IXGBE_TX_FLAGS_CSUM;
897ab156
AD		 6584 }
6585
091a6246 6586 /* compute header lengths */
897ab156
AD		 6587 l4len = tcp_hdrlen(skb);
6588 *hdr_len = skb_transport_offset(skb) + l4len;
6589
091a6246
AD		 6590 /* update gso size and bytecount with header size */
6591 first->gso_segs = skb_shinfo(skb)->gso_segs;
6592 first->bytecount += (first->gso_segs - 1) * *hdr_len;
6593
c44f5f51 6594 /* mss_l4len_id: use 0 as index for TSO */
897ab156
AD		 6595 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6596 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
897ab156
AD		 6597
6598 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6599 vlan_macip_lens = skb_network_header_len(skb);
6600 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6601 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
897ab156
AD		 6602
6603 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
244e27ad 6604 mss_l4len_idx);
897ab156
AD		 6605
6606 return 1;
6607}
6608
244e27ad
AD		 6609static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6610 struct ixgbe_tx_buffer *first)
7ca647bd 6611{
fd0db0ed 6612 struct sk_buff *skb = first->skb;
897ab156
AD		 6613 u32 vlan_macip_lens = 0;
6614 u32 mss_l4len_idx = 0;
6615 u32 type_tucmd = 0;
7ca647bd 6616
897ab156 6617 if (skb->ip_summed != CHECKSUM_PARTIAL) {
472148c3
AD		 6618 if (!(first->tx_flags & IXGBE_TX_FLAGS_HW_VLAN) &&
6619 !(first->tx_flags & IXGBE_TX_FLAGS_CC))
6620 return;
897ab156
AD		 6621 } else {
6622 u8 l4_hdr = 0;
244e27ad 6623 switch (first->protocol) {
a1108ffd 6624 case htons(ETH_P_IP):
897ab156
AD		 6625 vlan_macip_lens |= skb_network_header_len(skb);
6626 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6627 l4_hdr = ip_hdr(skb)->protocol;
7ca647bd 6628 break;
a1108ffd 6629 case htons(ETH_P_IPV6):
897ab156
AD		 6630 vlan_macip_lens |= skb_network_header_len(skb);
6631 l4_hdr = ipv6_hdr(skb)->nexthdr;
6632 break;
6633 default:
6634 if (unlikely(net_ratelimit())) {
6635 dev_warn(tx_ring->dev,
6636 "partial checksum but proto=%x!\n",
244e27ad 6637 first->protocol);
897ab156 6638 }
7ca647bd
JP		 6639 break;
6640 }
897ab156
AD		 6641
6642 switch (l4_hdr) {
7ca647bd 6643 case IPPROTO_TCP:
897ab156
AD		 6644 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6645 mss_l4len_idx = tcp_hdrlen(skb) <<
6646 IXGBE_ADVTXD_L4LEN_SHIFT;
7ca647bd
JP		 6647 break;
6648 case IPPROTO_SCTP:
897ab156
AD		 6649 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6650 mss_l4len_idx = sizeof(struct sctphdr) <<
6651 IXGBE_ADVTXD_L4LEN_SHIFT;
6652 break;
6653 case IPPROTO_UDP:
6654 mss_l4len_idx = sizeof(struct udphdr) <<
6655 IXGBE_ADVTXD_L4LEN_SHIFT;
6656 break;
6657 default:
6658 if (unlikely(net_ratelimit())) {
6659 dev_warn(tx_ring->dev,
6660 "partial checksum but l4 proto=%x!\n",
244e27ad 6661 l4_hdr);
897ab156 6662 }
7ca647bd
JP		 6663 break;
6664 }
244e27ad
AD		 6665
6666 /* update TX checksum flag */
6667 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
7ca647bd
JP		 6668 }
6669
244e27ad 6670 /* vlan_macip_lens: MACLEN, VLAN tag */
897ab156 6671 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
244e27ad 6672 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
9a799d71 6673
897ab156
AD		 6674 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6675 type_tucmd, mss_l4len_idx);
9a799d71
AK		 6676}
6677
472148c3
AD		 6678#define IXGBE_SET_FLAG(_input, _flag, _result) \
6679 ((_flag <= _result) ? \
6680 ((u32)(_input & _flag) * (_result / _flag)) : \
6681 ((u32)(_input & _flag) / (_flag / _result)))
6682
6683static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
9a799d71 6684{
d3d00239 6685 /* set type for advanced descriptor with frame checksum insertion */
472148c3
AD		 6686 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
6687 IXGBE_ADVTXD_DCMD_DEXT |
6688 IXGBE_ADVTXD_DCMD_IFCS;
9a799d71 6689
d3d00239 6690 /* set HW vlan bit if vlan is present */
472148c3
AD		 6691 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
6692 IXGBE_ADVTXD_DCMD_VLE);
3a6a4eda 6693
d3d00239 6694 /* set segmentation enable bits for TSO/FSO */
472148c3
AD		 6695 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
6696 IXGBE_ADVTXD_DCMD_TSE);
6697
6698 /* set timestamp bit if present */
6699 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
6700 IXGBE_ADVTXD_MAC_TSTAMP);
eacd73f7 6701
62748b7b 6702 /* insert frame checksum */
472148c3 6703 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
62748b7b 6704
d3d00239
AD		 6705 return cmd_type;
6706}
9a799d71 6707
729739b7
AD		 6708static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
6709 u32 tx_flags, unsigned int paylen)
d3d00239 6710{
472148c3 6711 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
9a799d71 6712
d3d00239 6713 /* enable L4 checksum for TSO and TX checksum offload */
472148c3
AD		 6714 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6715 IXGBE_TX_FLAGS_CSUM,
6716 IXGBE_ADVTXD_POPTS_TXSM);
9a799d71 6717
93f5b3c1 6718 /* enble IPv4 checksum for TSO */
472148c3
AD		 6719 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6720 IXGBE_TX_FLAGS_IPV4,
6721 IXGBE_ADVTXD_POPTS_IXSM);
9a799d71 6722
7f9643fd
AD		 6723 /*
6724 * Check Context must be set if Tx switch is enabled, which it
6725 * always is for case where virtual functions are running
6726 */
472148c3
AD		 6727 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
6728 IXGBE_TX_FLAGS_CC,
6729 IXGBE_ADVTXD_CC);
7f9643fd 6730
472148c3 6731 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
d3d00239 6732}
44df32c5 6733
d3d00239
AD		 6734#define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
6735 IXGBE_TXD_CMD_RS)
6736
6737static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
d3d00239 6738 struct ixgbe_tx_buffer *first,
d3d00239
AD		 6739 const u8 hdr_len)
6740{
fd0db0ed 6741 struct sk_buff *skb = first->skb;
729739b7 6742 struct ixgbe_tx_buffer *tx_buffer;
d3d00239 6743 union ixgbe_adv_tx_desc *tx_desc;
ec718254
AD		 6744 struct skb_frag_struct *frag;
6745 dma_addr_t dma;
6746 unsigned int data_len, size;
244e27ad 6747 u32 tx_flags = first->tx_flags;
472148c3 6748 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
d3d00239 6749 u16 i = tx_ring->next_to_use;
d3d00239 6750
729739b7
AD		 6751 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6752
ec718254
AD		 6753 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
6754
6755 size = skb_headlen(skb);
6756 data_len = skb->data_len;
729739b7 6757
d3d00239
AD		 6758#ifdef IXGBE_FCOE
6759 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
729739b7 6760 if (data_len < sizeof(struct fcoe_crc_eof)) {
d3d00239
AD		 6761 size -= sizeof(struct fcoe_crc_eof) - data_len;
6762 data_len = 0;
729739b7
AD		 6763 } else {
6764 data_len -= sizeof(struct fcoe_crc_eof);
9a799d71
AK		 6765 }
6766 }
44df32c5 6767
d3d00239 6768#endif
729739b7 6769 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8ad494b0 6770
ec718254 6771 tx_buffer = first;
9a799d71 6772
ec718254
AD		 6773 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
6774 if (dma_mapping_error(tx_ring->dev, dma))
6775 goto dma_error;
6776
6777 /* record length, and DMA address */
6778 dma_unmap_len_set(tx_buffer, len, size);
6779 dma_unmap_addr_set(tx_buffer, dma, dma);
6780
6781 tx_desc->read.buffer_addr = cpu_to_le64(dma);
e5a43549 6782
729739b7 6783 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
d3d00239 6784 tx_desc->read.cmd_type_len =
472148c3 6785 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
e5a43549 6786
d3d00239 6787 i++;
729739b7 6788 tx_desc++;
d3d00239 6789 if (i == tx_ring->count) {
e4f74028 6790 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
d3d00239
AD		 6791 i = 0;
6792 }
ec718254 6793 tx_desc->read.olinfo_status = 0;
729739b7
AD		 6794
6795 dma += IXGBE_MAX_DATA_PER_TXD;
6796 size -= IXGBE_MAX_DATA_PER_TXD;
6797
6798 tx_desc->read.buffer_addr = cpu_to_le64(dma);
d3d00239 6799 }
e5a43549 6800
729739b7
AD		 6801 if (likely(!data_len))
6802 break;
9a799d71 6803
472148c3 6804 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
9a799d71 6805
729739b7
AD		 6806 i++;
6807 tx_desc++;
6808 if (i == tx_ring->count) {
6809 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6810 i = 0;
6811 }
ec718254 6812 tx_desc->read.olinfo_status = 0;
9a799d71 6813
d3d00239 6814#ifdef IXGBE_FCOE
9e903e08 6815 size = min_t(unsigned int, data_len, skb_frag_size(frag));
d3d00239 6816#else
9e903e08 6817 size = skb_frag_size(frag);
d3d00239
AD		 6818#endif
6819 data_len -= size;
9a799d71 6820
729739b7
AD		 6821 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
6822 DMA_TO_DEVICE);
9a799d71 6823
729739b7 6824 tx_buffer = &tx_ring->tx_buffer_info[i];
729739b7 6825 }
9a799d71 6826
729739b7 6827 /* write last descriptor with RS and EOP bits */
472148c3
AD		 6828 cmd_type |= size | IXGBE_TXD_CMD;
6829 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
eacd73f7 6830
091a6246 6831 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
b2d96e0a 6832
d3d00239
AD		 6833 /* set the timestamp */
6834 first->time_stamp = jiffies;
9a799d71
AK		 6835
6836 /*
729739b7
AD		 6837 * Force memory writes to complete before letting h/w know there
6838 * are new descriptors to fetch. (Only applicable for weak-ordered
6839 * memory model archs, such as IA-64).
6840 *
6841 * We also need this memory barrier to make certain all of the
6842 * status bits have been updated before next_to_watch is written.
9a799d71
AK		 6843 */
6844 wmb();
6845
d3d00239
AD		 6846 /* set next_to_watch value indicating a packet is present */
6847 first->next_to_watch = tx_desc;
6848
729739b7
AD		 6849 i++;
6850 if (i == tx_ring->count)
6851 i = 0;
6852
6853 tx_ring->next_to_use = i;
6854
d3d00239 6855 /* notify HW of packet */
84227bcd 6856 ixgbe_write_tail(tx_ring, i);
d3d00239
AD		 6857
6858 return;
6859dma_error:
729739b7 6860 dev_err(tx_ring->dev, "TX DMA map failed\n");
d3d00239
AD		 6861
6862 /* clear dma mappings for failed tx_buffer_info map */
6863 for (;;) {
729739b7
AD		 6864 tx_buffer = &tx_ring->tx_buffer_info[i];
6865 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer);
6866 if (tx_buffer == first)
d3d00239
AD		 6867 break;
6868 if (i == 0)
6869 i = tx_ring->count;
6870 i--;
6871 }
6872
d3d00239 6873 tx_ring->next_to_use = i;
9a799d71
AK		 6874}
6875
fd0db0ed 6876static void ixgbe_atr(struct ixgbe_ring *ring,
244e27ad 6877 struct ixgbe_tx_buffer *first)
69830529
AD		 6878{
6879 struct ixgbe_q_vector *q_vector = ring->q_vector;
6880 union ixgbe_atr_hash_dword input = { .dword = 0 };
6881 union ixgbe_atr_hash_dword common = { .dword = 0 };
6882 union {
6883 unsigned char *network;
6884 struct iphdr *ipv4;
6885 struct ipv6hdr *ipv6;
6886 } hdr;
ee9e0f0b 6887 struct tcphdr *th;
905e4a41 6888 __be16 vlan_id;
c4cf55e5 6889
69830529
AD		 6890 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6891 if (!q_vector)
6892 return;
6893
6894 /* do nothing if sampling is disabled */
6895 if (!ring->atr_sample_rate)
d3ead241 6896 return;
c4cf55e5 6897
69830529 6898 ring->atr_count++;
c4cf55e5 6899
69830529 6900 /* snag network header to get L4 type and address */
fd0db0ed 6901 hdr.network = skb_network_header(first->skb);
69830529
AD		 6902
6903 /* Currently only IPv4/IPv6 with TCP is supported */
a1108ffd 6904 if ((first->protocol != htons(ETH_P_IPV6) ||
69830529 6905 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
a1108ffd 6906 (first->protocol != htons(ETH_P_IP) ||
69830529
AD		 6907 hdr.ipv4->protocol != IPPROTO_TCP))
6908 return;
ee9e0f0b 6909
fd0db0ed 6910 th = tcp_hdr(first->skb);
c4cf55e5 6911
66f32a8b
AD		 6912 /* skip this packet since it is invalid or the socket is closing */
6913 if (!th || th->fin)
69830529
AD		 6914 return;
6915
6916 /* sample on all syn packets or once every atr sample count */
6917 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6918 return;
6919
6920 /* reset sample count */
6921 ring->atr_count = 0;
6922
244e27ad 6923 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
69830529
AD		 6924
6925 /*
6926 * src and dst are inverted, think how the receiver sees them
6927 *
6928 * The input is broken into two sections, a non-compressed section
6929 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6930 * is XORed together and stored in the compressed dword.
6931 */
6932 input.formatted.vlan_id = vlan_id;
6933
6934 /*
6935 * since src port and flex bytes occupy the same word XOR them together
6936 * and write the value to source port portion of compressed dword
6937 */
244e27ad 6938 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
a1108ffd 6939 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
69830529 6940 else
244e27ad 6941 common.port.src ^= th->dest ^ first->protocol;
69830529
AD		 6942 common.port.dst ^= th->source;
6943
a1108ffd 6944 if (first->protocol == htons(ETH_P_IP)) {
69830529
AD		 6945 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6946 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6947 } else {
6948 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6949 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6950 hdr.ipv6->saddr.s6_addr32[1] ^
6951 hdr.ipv6->saddr.s6_addr32[2] ^
6952 hdr.ipv6->saddr.s6_addr32[3] ^
6953 hdr.ipv6->daddr.s6_addr32[0] ^
6954 hdr.ipv6->daddr.s6_addr32[1] ^
6955 hdr.ipv6->daddr.s6_addr32[2] ^
6956 hdr.ipv6->daddr.s6_addr32[3];
6957 }
c4cf55e5
PWJ		 6958
6959 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
69830529
AD		 6960 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6961 input, common, ring->queue_index);
c4cf55e5
PWJ		 6962}
6963
63544e9c 6964static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6965{
fc77dc3c 6966 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
e092be60
AV		 6967 /* Herbert's original patch had:
6968 * smp_mb__after_netif_stop_queue();
6969 * but since that doesn't exist yet, just open code it. */
6970 smp_mb();
6971
6972 /* We need to check again in a case another CPU has just
6973 * made room available. */
7d4987de 6974 if (likely(ixgbe_desc_unused(tx_ring) < size))
e092be60
AV		 6975 return -EBUSY;
6976
6977 /* A reprieve! - use start_queue because it doesn't call schedule */
fc77dc3c 6978 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
5b7da515 6979 ++tx_ring->tx_stats.restart_queue;
e092be60
AV		 6980 return 0;
6981}
6982
82d4e46e 6983static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
e092be60 6984{
7d4987de 6985 if (likely(ixgbe_desc_unused(tx_ring) >= size))
e092be60 6986 return 0;
fc77dc3c 6987 return __ixgbe_maybe_stop_tx(tx_ring, size);
e092be60
AV		 6988}
6989
f663dd9a 6990static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 6991 void *accel_priv, select_queue_fallback_t fallback)
09a3b1f8 6992{
f663dd9a
JW		 6993 struct ixgbe_fwd_adapter *fwd_adapter = accel_priv;
6994#ifdef IXGBE_FCOE
97488bd1
AD		 6995 struct ixgbe_adapter *adapter;
6996 struct ixgbe_ring_feature *f;
6997 int txq;
f663dd9a
JW		 6998#endif
6999
7000 if (fwd_adapter)
7001 return skb->queue_mapping + fwd_adapter->tx_base_queue;
7002
7003#ifdef IXGBE_FCOE
5e09a105 7004
97488bd1
AD		 7005 /*
7006 * only execute the code below if protocol is FCoE
7007 * or FIP and we have FCoE enabled on the adapter
7008 */
7009 switch (vlan_get_protocol(skb)) {
a1108ffd
JP		 7010 case htons(ETH_P_FCOE):
7011 case htons(ETH_P_FIP):
97488bd1 7012 adapter = netdev_priv(dev);
c087663e 7013
97488bd1
AD		 7014 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7015 break;
7016 default:
99932d4f 7017 return fallback(dev, skb);
97488bd1 7018 }
c087663e 7019
97488bd1 7020 f = &adapter->ring_feature[RING_F_FCOE];
c087663e 7021
97488bd1
AD		 7022 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
7023 smp_processor_id();
56075a98 7024
97488bd1
AD		 7025 while (txq >= f->indices)
7026 txq -= f->indices;
c4cf55e5 7027
97488bd1 7028 return txq + f->offset;
f663dd9a 7029#else
99932d4f 7030 return fallback(dev, skb);
f663dd9a 7031#endif
09a3b1f8
SH		 7032}
7033
fc77dc3c 7034netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
84418e3b
AD		 7035 struct ixgbe_adapter *adapter,
7036 struct ixgbe_ring *tx_ring)
9a799d71 7037{
d3d00239 7038 struct ixgbe_tx_buffer *first;
5f715823 7039 int tso;
d3d00239 7040 u32 tx_flags = 0;
a535c30e 7041 unsigned short f;
a535c30e 7042 u16 count = TXD_USE_COUNT(skb_headlen(skb));
66f32a8b 7043 __be16 protocol = skb->protocol;
63544e9c 7044 u8 hdr_len = 0;
5e09a105 7045
a535c30e
AD		 7046 /*
7047 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
24ddd967 7048 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
a535c30e
AD		 7049 * + 2 desc gap to keep tail from touching head,
7050 * + 1 desc for context descriptor,
7051 * otherwise try next time
7052 */
a535c30e
AD		 7053 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
7054 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
7f66162b 7055
a535c30e
AD		 7056 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
7057 tx_ring->tx_stats.tx_busy++;
7058 return NETDEV_TX_BUSY;
7059 }
7060
fd0db0ed
AD		 7061 /* record the location of the first descriptor for this packet */
7062 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
7063 first->skb = skb;
091a6246
AD		 7064 first->bytecount = skb->len;
7065 first->gso_segs = 1;
fd0db0ed 7066
66f32a8b 7067 /* if we have a HW VLAN tag being added default to the HW one */
eab6d18d 7068 if (vlan_tx_tag_present(skb)) {
66f32a8b
AD		 7069 tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
7070 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
7071 /* else if it is a SW VLAN check the next protocol and store the tag */
a1108ffd 7072 } else if (protocol == htons(ETH_P_8021Q)) {
66f32a8b
AD		 7073 struct vlan_hdr *vhdr, _vhdr;
7074 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
7075 if (!vhdr)
7076 goto out_drop;
7077
7078 protocol = vhdr->h_vlan_encapsulated_proto;
9e0c5648
AD		 7079 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
7080 IXGBE_TX_FLAGS_VLAN_SHIFT;
66f32a8b
AD		 7081 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
7082 }
7083
151b260c
JK		 7084 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
7085 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
7086 &adapter->state))) {
3a6a4eda
JK		 7087 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
7088 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
891dc082
JK		 7089
7090 /* schedule check for Tx timestamp */
7091 adapter->ptp_tx_skb = skb_get(skb);
7092 adapter->ptp_tx_start = jiffies;
7093 schedule_work(&adapter->ptp_tx_work);
3a6a4eda 7094 }
3a6a4eda 7095
ff29a86e
JK		 7096 skb_tx_timestamp(skb);
7097
9e0c5648
AD		 7098#ifdef CONFIG_PCI_IOV
7099 /*
7100 * Use the l2switch_enable flag - would be false if the DMA
7101 * Tx switch had been disabled.
7102 */
7103 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
472148c3 7104 tx_flags |= IXGBE_TX_FLAGS_CC;
9e0c5648
AD		 7105
7106#endif
32701dc2 7107 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
66f32a8b 7108 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
09dca476
AD		 7109 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
7110 (skb->priority != TC_PRIO_CONTROL))) {
66f32a8b 7111 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
32701dc2
JF		 7112 tx_flags |= (skb->priority & 0x7) <<
7113 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
66f32a8b
AD		 7114 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
7115 struct vlan_ethhdr *vhdr;
2049e1f6
FR		 7116
7117 if (skb_cow_head(skb, 0))
66f32a8b
AD		 7118 goto out_drop;
7119 vhdr = (struct vlan_ethhdr *)skb->data;
7120 vhdr->h_vlan_TCI = htons(tx_flags >>
7121 IXGBE_TX_FLAGS_VLAN_SHIFT);
7122 } else {
7123 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
2f90b865 7124 }
9a799d71 7125 }
eacd73f7 7126
244e27ad
AD		 7127 /* record initial flags and protocol */
7128 first->tx_flags = tx_flags;
7129 first->protocol = protocol;
7130
eacd73f7 7131#ifdef IXGBE_FCOE
66f32a8b 7132 /* setup tx offload for FCoE */
a1108ffd 7133 if ((protocol == htons(ETH_P_FCOE)) &&
a58915c7 7134 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
244e27ad 7135 tso = ixgbe_fso(tx_ring, first, &hdr_len);
897ab156
AD		 7136 if (tso < 0)
7137 goto out_drop;
9a799d71 7138
66f32a8b 7139 goto xmit_fcoe;
eacd73f7 7140 }
9a799d71 7141
66f32a8b 7142#endif /* IXGBE_FCOE */
244e27ad 7143 tso = ixgbe_tso(tx_ring, first, &hdr_len);
66f32a8b 7144 if (tso < 0)
897ab156 7145 goto out_drop;
244e27ad
AD		 7146 else if (!tso)
7147 ixgbe_tx_csum(tx_ring, first);
66f32a8b
AD		 7148
7149 /* add the ATR filter if ATR is on */
7150 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
244e27ad 7151 ixgbe_atr(tx_ring, first);
66f32a8b
AD		 7152
7153#ifdef IXGBE_FCOE
7154xmit_fcoe:
7155#endif /* IXGBE_FCOE */
244e27ad 7156 ixgbe_tx_map(tx_ring, first, hdr_len);
d3d00239
AD		 7157
7158 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
9a799d71
AK		 7159
7160 return NETDEV_TX_OK;
897ab156
AD		 7161
7162out_drop:
fd0db0ed
AD		 7163 dev_kfree_skb_any(first->skb);
7164 first->skb = NULL;
7165
897ab156 7166 return NETDEV_TX_OK;
9a799d71
AK		 7167}
7168
2a47fa45
JF		 7169static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
7170 struct net_device *netdev,
7171 struct ixgbe_ring *ring)
84418e3b
AD		 7172{
7173 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7174 struct ixgbe_ring *tx_ring;
7175
a50c29dd
AD		 7176 /*
7177 * The minimum packet size for olinfo paylen is 17 so pad the skb
7178 * in order to meet this minimum size requirement.
7179 */
f73332fc
SH		 7180 if (unlikely(skb->len < 17)) {
7181 if (skb_pad(skb, 17 - skb->len))
a50c29dd
AD		 7182 return NETDEV_TX_OK;
7183 skb->len = 17;
71a49f77 7184 skb_set_tail_pointer(skb, 17);
a50c29dd
AD		 7185 }
7186
2a47fa45
JF		 7187 tx_ring = ring ? ring : adapter->tx_ring[skb->queue_mapping];
7188
fc77dc3c 7189 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
84418e3b
AD		 7190}
7191
2a47fa45
JF		 7192static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
7193 struct net_device *netdev)
7194{
7195 return __ixgbe_xmit_frame(skb, netdev, NULL);
7196}
7197
9a799d71
AK		 7198/**
7199 * ixgbe_set_mac - Change the Ethernet Address of the NIC
7200 * @netdev: network interface device structure
7201 * @p: pointer to an address structure
7202 *
7203 * Returns 0 on success, negative on failure
7204 **/
7205static int ixgbe_set_mac(struct net_device *netdev, void *p)
7206{
7207 struct ixgbe_adapter *adapter = netdev_priv(netdev);
b4617240 7208 struct ixgbe_hw *hw = &adapter->hw;
9a799d71
AK		 7209 struct sockaddr *addr = p;
7210
7211 if (!is_valid_ether_addr(addr->sa_data))
7212 return -EADDRNOTAVAIL;
7213
7214 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
b4617240 7215 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
9a799d71 7216
1d9c0bfd 7217 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, VMDQ_P(0), IXGBE_RAH_AV);
9a799d71
AK		 7218
7219 return 0;
7220}
7221
6b73e10d
BH		 7222static int
7223ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
7224{
7225 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7226 struct ixgbe_hw *hw = &adapter->hw;
7227 u16 value;
7228 int rc;
7229
7230 if (prtad != hw->phy.mdio.prtad)
7231 return -EINVAL;
7232 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
7233 if (!rc)
7234 rc = value;
7235 return rc;
7236}
7237
7238static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
7239 u16 addr, u16 value)
7240{
7241 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7242 struct ixgbe_hw *hw = &adapter->hw;
7243
7244 if (prtad != hw->phy.mdio.prtad)
7245 return -EINVAL;
7246 return hw->phy.ops.write_reg(hw, addr, devad, value);
7247}
7248
7249static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
7250{
7251 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7252
3a6a4eda 7253 switch (cmd) {
3a6a4eda 7254 case SIOCSHWTSTAMP:
93501d48
JK		 7255 return ixgbe_ptp_set_ts_config(adapter, req);
7256 case SIOCGHWTSTAMP:
7257 return ixgbe_ptp_get_ts_config(adapter, req);
3a6a4eda
JK		 7258 default:
7259 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
7260 }
6b73e10d
BH		 7261}
7262
0365e6e4
PW		 7263/**
7264 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
31278e71 7265 * netdev->dev_addrs
0365e6e4
PW		 7266 * @netdev: network interface device structure
7267 *
7268 * Returns non-zero on failure
7269 **/
7270static int ixgbe_add_sanmac_netdev(struct net_device *dev)
7271{
7272 int err = 0;
7273 struct ixgbe_adapter *adapter = netdev_priv(dev);
7fa7c9dc 7274 struct ixgbe_hw *hw = &adapter->hw;
0365e6e4 7275
7fa7c9dc 7276 if (is_valid_ether_addr(hw->mac.san_addr)) {
0365e6e4 7277 rtnl_lock();
7fa7c9dc 7278 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
0365e6e4 7279 rtnl_unlock();
7fa7c9dc
AD		 7280
7281 /* update SAN MAC vmdq pool selection */
7282 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
0365e6e4
PW		 7283 }
7284 return err;
7285}
7286
7287/**
7288 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
31278e71 7289 * netdev->dev_addrs
0365e6e4
PW		 7290 * @netdev: network interface device structure
7291 *
7292 * Returns non-zero on failure
7293 **/
7294static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7295{
7296 int err = 0;
7297 struct ixgbe_adapter *adapter = netdev_priv(dev);
7298 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7299
7300 if (is_valid_ether_addr(mac->san_addr)) {
7301 rtnl_lock();
7302 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7303 rtnl_unlock();
7304 }
7305 return err;
7306}
7307
9a799d71
AK		 7308#ifdef CONFIG_NET_POLL_CONTROLLER
7309/*
7310 * Polling 'interrupt' - used by things like netconsole to send skbs
7311 * without having to re-enable interrupts. It's not called while
7312 * the interrupt routine is executing.
7313 */
7314static void ixgbe_netpoll(struct net_device *netdev)
7315{
7316 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8f9a7167 7317 int i;
9a799d71 7318
1a647bd2
AD		 7319 /* if interface is down do nothing */
7320 if (test_bit(__IXGBE_DOWN, &adapter->state))
7321 return;
7322
9a799d71 7323 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
8f9a7167 7324 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
49c7ffbe
AD		 7325 for (i = 0; i < adapter->num_q_vectors; i++)
7326 ixgbe_msix_clean_rings(0, adapter->q_vector[i]);
8f9a7167
PWJ		 7327 } else {
7328 ixgbe_intr(adapter->pdev->irq, netdev);
7329 }
9a799d71 7330 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
9a799d71 7331}
9a799d71 7332
581330ba 7333#endif
de1036b1
ED		 7334static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7335 struct rtnl_link_stats64 *stats)
7336{
7337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7338 int i;
7339
1a51502b 7340 rcu_read_lock();
de1036b1 7341 for (i = 0; i < adapter->num_rx_queues; i++) {
1a51502b 7342 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
de1036b1
ED		 7343 u64 bytes, packets;
7344 unsigned int start;
7345
1a51502b
ED		 7346 if (ring) {
7347 do {
57a7744e 7348 start = u64_stats_fetch_begin_irq(&ring->syncp);
1a51502b
ED		 7349 packets = ring->stats.packets;
7350 bytes = ring->stats.bytes;
57a7744e 7351 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1a51502b
ED		 7352 stats->rx_packets += packets;
7353 stats->rx_bytes += bytes;
7354 }
de1036b1 7355 }
1ac9ad13
ED		 7356
7357 for (i = 0; i < adapter->num_tx_queues; i++) {
7358 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7359 u64 bytes, packets;
7360 unsigned int start;
7361
7362 if (ring) {
7363 do {
57a7744e 7364 start = u64_stats_fetch_begin_irq(&ring->syncp);
1ac9ad13
ED		 7365 packets = ring->stats.packets;
7366 bytes = ring->stats.bytes;
57a7744e 7367 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
1ac9ad13
ED		 7368 stats->tx_packets += packets;
7369 stats->tx_bytes += bytes;
7370 }
7371 }
1a51502b 7372 rcu_read_unlock();
de1036b1
ED		 7373 /* following stats updated by ixgbe_watchdog_task() */
7374 stats->multicast = netdev->stats.multicast;
7375 stats->rx_errors = netdev->stats.rx_errors;
7376 stats->rx_length_errors = netdev->stats.rx_length_errors;
7377 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7378 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7379 return stats;
7380}
7381
8af3c33f 7382#ifdef CONFIG_IXGBE_DCB
49ce9c2c
BH		 7383/**
7384 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7385 * @adapter: pointer to ixgbe_adapter
8b1c0b24
JF		 7386 * @tc: number of traffic classes currently enabled
7387 *
7388 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7389 * 802.1Q priority maps to a packet buffer that exists.
7390 */
7391static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7392{
7393 struct ixgbe_hw *hw = &adapter->hw;
7394 u32 reg, rsave;
7395 int i;
7396
7397 /* 82598 have a static priority to TC mapping that can not
7398 * be changed so no validation is needed.
7399 */
7400 if (hw->mac.type == ixgbe_mac_82598EB)
7401 return;
7402
7403 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7404 rsave = reg;
7405
7406 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7407 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7408
7409 /* If up2tc is out of bounds default to zero */
7410 if (up2tc > tc)
7411 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7412 }
7413
7414 if (reg != rsave)
7415 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7416
7417 return;
7418}
7419
02debdc9
AD		 7420/**
7421 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
7422 * @adapter: Pointer to adapter struct
7423 *
7424 * Populate the netdev user priority to tc map
7425 */
7426static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
7427{
7428 struct net_device *dev = adapter->netdev;
7429 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
7430 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
7431 u8 prio;
7432
7433 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
7434 u8 tc = 0;
7435
7436 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
7437 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
7438 else if (ets)
7439 tc = ets->prio_tc[prio];
7440
7441 netdev_set_prio_tc_map(dev, prio, tc);
7442 }
7443}
7444
cca73c59 7445#endif /* CONFIG_IXGBE_DCB */
49ce9c2c
BH		 7446/**
7447 * ixgbe_setup_tc - configure net_device for multiple traffic classes
8b1c0b24
JF		 7448 *
7449 * @netdev: net device to configure
7450 * @tc: number of traffic classes to enable
7451 */
7452int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7453{
8b1c0b24
JF		 7454 struct ixgbe_adapter *adapter = netdev_priv(dev);
7455 struct ixgbe_hw *hw = &adapter->hw;
2a47fa45 7456 bool pools;
8b1c0b24 7457
8b1c0b24 7458 /* Hardware supports up to 8 traffic classes */
4de2a022 7459 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs ||
581330ba
AD		 7460 (hw->mac.type == ixgbe_mac_82598EB &&
7461 tc < MAX_TRAFFIC_CLASS))
8b1c0b24
JF		 7462 return -EINVAL;
7463
2a47fa45
JF		 7464 pools = (find_first_zero_bit(&adapter->fwd_bitmask, 32) > 1);
7465 if (tc && pools && adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS)
7466 return -EBUSY;
7467
8b1c0b24 7468 /* Hardware has to reinitialize queues and interrupts to
52f33af8 7469 * match packet buffer alignment. Unfortunately, the
8b1c0b24
JF		 7470 * hardware is not flexible enough to do this dynamically.
7471 */
7472 if (netif_running(dev))
7473 ixgbe_close(dev);
7474 ixgbe_clear_interrupt_scheme(adapter);
7475
cca73c59 7476#ifdef CONFIG_IXGBE_DCB
e7589eab 7477 if (tc) {
8b1c0b24 7478 netdev_set_num_tc(dev, tc);
02debdc9
AD		 7479 ixgbe_set_prio_tc_map(adapter);
7480
e7589eab 7481 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
e7589eab 7482
943561d3
AD		 7483 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
7484 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
e7589eab 7485 adapter->hw.fc.requested_mode = ixgbe_fc_none;
943561d3 7486 }
e7589eab 7487 } else {
8b1c0b24 7488 netdev_reset_tc(dev);
02debdc9 7489
943561d3
AD		 7490 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
7491 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
e7589eab
JF		 7492
7493 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
e7589eab
JF		 7494
7495 adapter->temp_dcb_cfg.pfc_mode_enable = false;
7496 adapter->dcb_cfg.pfc_mode_enable = false;
7497 }
7498
8b1c0b24 7499 ixgbe_validate_rtr(adapter, tc);
cca73c59
AD		 7500
7501#endif /* CONFIG_IXGBE_DCB */
7502 ixgbe_init_interrupt_scheme(adapter);
7503
8b1c0b24 7504 if (netif_running(dev))
cca73c59 7505 return ixgbe_open(dev);
8b1c0b24
JF		 7506
7507 return 0;
7508}
de1036b1 7509
da36b647
GR		 7510#ifdef CONFIG_PCI_IOV
7511void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
7512{
7513 struct net_device *netdev = adapter->netdev;
7514
7515 rtnl_lock();
da36b647 7516 ixgbe_setup_tc(netdev, netdev_get_num_tc(netdev));
da36b647
GR		 7517 rtnl_unlock();
7518}
7519
7520#endif
082757af
DS		 7521void ixgbe_do_reset(struct net_device *netdev)
7522{
7523 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7524
7525 if (netif_running(netdev))
7526 ixgbe_reinit_locked(adapter);
7527 else
7528 ixgbe_reset(adapter);
7529}
7530
c8f44aff 7531static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
567d2de2 7532 netdev_features_t features)
082757af
DS		 7533{
7534 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7535
082757af 7536 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
567d2de2
AD		 7537 if (!(features & NETIF_F_RXCSUM))
7538 features &= ~NETIF_F_LRO;
082757af 7539
567d2de2
AD		 7540 /* Turn off LRO if not RSC capable */
7541 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
7542 features &= ~NETIF_F_LRO;
8e2813f5 7543
567d2de2 7544 return features;
082757af
DS		 7545}
7546
c8f44aff 7547static int ixgbe_set_features(struct net_device *netdev,
567d2de2 7548 netdev_features_t features)
082757af
DS		 7549{
7550 struct ixgbe_adapter *adapter = netdev_priv(netdev);
567d2de2 7551 netdev_features_t changed = netdev->features ^ features;
082757af
DS		 7552 bool need_reset = false;
7553
082757af 7554 /* Make sure RSC matches LRO, reset if change */
567d2de2
AD		 7555 if (!(features & NETIF_F_LRO)) {
7556 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
082757af 7557 need_reset = true;
567d2de2
AD		 7558 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
7559 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
7560 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
7561 if (adapter->rx_itr_setting == 1 ||
7562 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
7563 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
7564 need_reset = true;
7565 } else if ((changed ^ features) & NETIF_F_LRO) {
7566 e_info(probe, "rx-usecs set too low, "
7567 "disabling RSC\n");
082757af
DS		 7568 }
7569 }
7570
7571 /*
7572 * Check if Flow Director n-tuple support was enabled or disabled. If
7573 * the state changed, we need to reset.
7574 */
39cb681b
AD		 7575 switch (features & NETIF_F_NTUPLE) {
7576 case NETIF_F_NTUPLE:
567d2de2 7577 /* turn off ATR, enable perfect filters and reset */
39cb681b
AD		 7578 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
7579 need_reset = true;
7580
567d2de2
AD		 7581 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
7582 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
39cb681b
AD		 7583 break;
7584 default:
7585 /* turn off perfect filters, enable ATR and reset */
7586 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7587 need_reset = true;
7588
7589 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
7590
7591 /* We cannot enable ATR if SR-IOV is enabled */
7592 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7593 break;
7594
7595 /* We cannot enable ATR if we have 2 or more traffic classes */
7596 if (netdev_get_num_tc(netdev) > 1)
7597 break;
7598
7599 /* We cannot enable ATR if RSS is disabled */
7600 if (adapter->ring_feature[RING_F_RSS].limit <= 1)
7601 break;
7602
7603 /* A sample rate of 0 indicates ATR disabled */
7604 if (!adapter->atr_sample_rate)
7605 break;
7606
7607 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
7608 break;
082757af
DS		 7609 }
7610
f646968f 7611 if (features & NETIF_F_HW_VLAN_CTAG_RX)
146d4cc9
JF		 7612 ixgbe_vlan_strip_enable(adapter);
7613 else
7614 ixgbe_vlan_strip_disable(adapter);
7615
3f2d1c0f
BG		 7616 if (changed & NETIF_F_RXALL)
7617 need_reset = true;
7618
567d2de2 7619 netdev->features = features;
082757af
DS		 7620 if (need_reset)
7621 ixgbe_do_reset(netdev);
7622
7623 return 0;
082757af
DS		 7624}
7625
edc7d573 7626static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
0f4b0add 7627 struct net_device *dev,
6b6e2725 7628 const unsigned char *addr,
0f4b0add
JF		 7629 u16 flags)
7630{
7631 struct ixgbe_adapter *adapter = netdev_priv(dev);
95447461
JF		 7632 int err;
7633
7634 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
faaf02d2 7635 return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
0f4b0add 7636
b1ac1ef7
JF		 7637 /* Hardware does not support aging addresses so if a
7638 * ndm_state is given only allow permanent addresses
7639 */
7640 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
0f4b0add
JF		 7641 pr_info("%s: FDB only supports static addresses\n",
7642 ixgbe_driver_name);
7643 return -EINVAL;
7644 }
7645
46acc460 7646 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
95447461
JF		 7647 u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
7648
7649 if (netdev_uc_count(dev) < rar_uc_entries)
0f4b0add 7650 err = dev_uc_add_excl(dev, addr);
0f4b0add 7651 else
95447461
JF		 7652 err = -ENOMEM;
7653 } else if (is_multicast_ether_addr(addr)) {
7654 err = dev_mc_add_excl(dev, addr);
7655 } else {
7656 err = -EINVAL;
0f4b0add
JF		 7657 }
7658
7659 /* Only return duplicate errors if NLM_F_EXCL is set */
7660 if (err == -EEXIST && !(flags & NLM_F_EXCL))
7661 err = 0;
7662
7663 return err;
7664}
7665
815cccbf
JF		 7666static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
7667 struct nlmsghdr *nlh)
7668{
7669 struct ixgbe_adapter *adapter = netdev_priv(dev);
7670 struct nlattr *attr, *br_spec;
7671 int rem;
7672
7673 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7674 return -EOPNOTSUPP;
7675
7676 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
7677
7678 nla_for_each_nested(attr, br_spec, rem) {
7679 __u16 mode;
7680 u32 reg = 0;
7681
7682 if (nla_type(attr) != IFLA_BRIDGE_MODE)
7683 continue;
7684
7685 mode = nla_get_u16(attr);
9b735984 7686 if (mode == BRIDGE_MODE_VEPA) {
815cccbf 7687 reg = 0;
9b735984
GR		 7688 adapter->flags2 &= ~IXGBE_FLAG2_BRIDGE_MODE_VEB;
7689 } else if (mode == BRIDGE_MODE_VEB) {
815cccbf 7690 reg = IXGBE_PFDTXGSWC_VT_LBEN;
9b735984
GR		 7691 adapter->flags2 |= IXGBE_FLAG2_BRIDGE_MODE_VEB;
7692 } else
815cccbf
JF		 7693 return -EINVAL;
7694
7695 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, reg);
7696
7697 e_info(drv, "enabling bridge mode: %s\n",
7698 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
7699 }
7700
7701 return 0;
7702}
7703
7704static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
6cbdceeb
VY		 7705 struct net_device *dev,
7706 u32 filter_mask)
815cccbf
JF		 7707{
7708 struct ixgbe_adapter *adapter = netdev_priv(dev);
7709 u16 mode;
7710
7711 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
7712 return 0;
7713
9b735984 7714 if (adapter->flags2 & IXGBE_FLAG2_BRIDGE_MODE_VEB)
815cccbf
JF		 7715 mode = BRIDGE_MODE_VEB;
7716 else
7717 mode = BRIDGE_MODE_VEPA;
7718
7719 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, mode);
7720}
7721
2a47fa45
JF		 7722static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
7723{
7724 struct ixgbe_fwd_adapter *fwd_adapter = NULL;
7725 struct ixgbe_adapter *adapter = netdev_priv(pdev);
51f3773b 7726 unsigned int limit;
2a47fa45
JF		 7727 int pool, err;
7728
219354d4
JF		 7729#ifdef CONFIG_RPS
7730 if (vdev->num_rx_queues != vdev->num_tx_queues) {
7731 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
7732 vdev->name);
7733 return ERR_PTR(-EINVAL);
7734 }
7735#endif
2a47fa45 7736 /* Check for hardware restriction on number of rx/tx queues */
219354d4 7737 if (vdev->num_tx_queues > IXGBE_MAX_L2A_QUEUES ||
2a47fa45
JF		 7738 vdev->num_tx_queues == IXGBE_BAD_L2A_QUEUE) {
7739 netdev_info(pdev,
7740 "%s: Supports RX/TX Queue counts 1,2, and 4\n",
7741 pdev->name);
7742 return ERR_PTR(-EINVAL);
7743 }
7744
7745 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
7746 adapter->num_rx_pools > IXGBE_MAX_DCBMACVLANS - 1) ||
7747 (adapter->num_rx_pools > IXGBE_MAX_MACVLANS))
7748 return ERR_PTR(-EBUSY);
7749
7750 fwd_adapter = kcalloc(1, sizeof(struct ixgbe_fwd_adapter), GFP_KERNEL);
7751 if (!fwd_adapter)
7752 return ERR_PTR(-ENOMEM);
7753
7754 pool = find_first_zero_bit(&adapter->fwd_bitmask, 32);
7755 adapter->num_rx_pools++;
7756 set_bit(pool, &adapter->fwd_bitmask);
51f3773b 7757 limit = find_last_bit(&adapter->fwd_bitmask, 32);
2a47fa45
JF		 7758
7759 /* Enable VMDq flag so device will be set in VM mode */
7760 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED | IXGBE_FLAG_SRIOV_ENABLED;
51f3773b 7761 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
219354d4 7762 adapter->ring_feature[RING_F_RSS].limit = vdev->num_tx_queues;
2a47fa45
JF		 7763
7764 /* Force reinit of ring allocation with VMDQ enabled */
7765 err = ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7766 if (err)
7767 goto fwd_add_err;
7768 fwd_adapter->pool = pool;
7769 fwd_adapter->real_adapter = adapter;
7770 err = ixgbe_fwd_ring_up(vdev, fwd_adapter);
7771 if (err)
7772 goto fwd_add_err;
7773 netif_tx_start_all_queues(vdev);
7774 return fwd_adapter;
7775fwd_add_err:
7776 /* unwind counter and free adapter struct */
7777 netdev_info(pdev,
7778 "%s: dfwd hardware acceleration failed\n", vdev->name);
7779 clear_bit(pool, &adapter->fwd_bitmask);
7780 adapter->num_rx_pools--;
7781 kfree(fwd_adapter);
7782 return ERR_PTR(err);
7783}
7784
7785static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
7786{
7787 struct ixgbe_fwd_adapter *fwd_adapter = priv;
7788 struct ixgbe_adapter *adapter = fwd_adapter->real_adapter;
51f3773b 7789 unsigned int limit;
2a47fa45
JF		 7790
7791 clear_bit(fwd_adapter->pool, &adapter->fwd_bitmask);
7792 adapter->num_rx_pools--;
7793
51f3773b
JF		 7794 limit = find_last_bit(&adapter->fwd_bitmask, 32);
7795 adapter->ring_feature[RING_F_VMDQ].limit = limit + 1;
2a47fa45
JF		 7796 ixgbe_fwd_ring_down(fwd_adapter->netdev, fwd_adapter);
7797 ixgbe_setup_tc(pdev, netdev_get_num_tc(pdev));
7798 netdev_dbg(pdev, "pool %i:%i queues %i:%i VSI bitmask %lx\n",
7799 fwd_adapter->pool, adapter->num_rx_pools,
7800 fwd_adapter->rx_base_queue,
7801 fwd_adapter->rx_base_queue + adapter->num_rx_queues_per_pool,
7802 adapter->fwd_bitmask);
7803 kfree(fwd_adapter);
7804}
7805
0edc3527 7806static const struct net_device_ops ixgbe_netdev_ops = {
e8e9f696 7807 .ndo_open = ixgbe_open,
0edc3527 7808 .ndo_stop = ixgbe_close,
00829823 7809 .ndo_start_xmit = ixgbe_xmit_frame,
09a3b1f8 7810 .ndo_select_queue = ixgbe_select_queue,
581330ba 7811 .ndo_set_rx_mode = ixgbe_set_rx_mode,
0edc3527
SH		 7812 .ndo_validate_addr = eth_validate_addr,
7813 .ndo_set_mac_address = ixgbe_set_mac,
7814 .ndo_change_mtu = ixgbe_change_mtu,
7815 .ndo_tx_timeout = ixgbe_tx_timeout,
0edc3527
SH		 7816 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7817 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6b73e10d 7818 .ndo_do_ioctl = ixgbe_ioctl,
7f01648a
GR		 7819 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7820 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7821 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
581330ba 7822 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
7f01648a 7823 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
de1036b1 7824 .ndo_get_stats64 = ixgbe_get_stats64,
8af3c33f 7825#ifdef CONFIG_IXGBE_DCB
24095aa3 7826 .ndo_setup_tc = ixgbe_setup_tc,
8af3c33f 7827#endif
0edc3527
SH		 7828#ifdef CONFIG_NET_POLL_CONTROLLER
7829 .ndo_poll_controller = ixgbe_netpoll,
7830#endif
e0d1095a 7831#ifdef CONFIG_NET_RX_BUSY_POLL
8b80cda5 7832 .ndo_busy_poll = ixgbe_low_latency_recv,
5a85e737 7833#endif
332d4a7d
YZ		 7834#ifdef IXGBE_FCOE
7835 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
68a683cf 7836 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
332d4a7d 7837 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
8450ff8c
YZ		 7838 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7839 .ndo_fcoe_disable = ixgbe_fcoe_disable,
61a1fa10 7840 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
ea81875a 7841 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
332d4a7d 7842#endif /* IXGBE_FCOE */
082757af
DS		 7843 .ndo_set_features = ixgbe_set_features,
7844 .ndo_fix_features = ixgbe_fix_features,
0f4b0add 7845 .ndo_fdb_add = ixgbe_ndo_fdb_add,
815cccbf
JF		 7846 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
7847 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
2a47fa45
JF		 7848 .ndo_dfwd_add_station = ixgbe_fwd_add,
7849 .ndo_dfwd_del_station = ixgbe_fwd_del,
0edc3527
SH		 7850};
7851
e027d1ae
JK		 7852/**
7853 * ixgbe_enumerate_functions - Get the number of ports this device has
7854 * @adapter: adapter structure
7855 *
7856 * This function enumerates the phsyical functions co-located on a single slot,
7857 * in order to determine how many ports a device has. This is most useful in
7858 * determining the required GT/s of PCIe bandwidth necessary for optimal
7859 * performance.
7860 **/
7861static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
7862{
e027d1ae
JK		 7863 struct list_head *entry;
7864 int physfns = 0;
7865
f1f96579
JK		 7866 /* Some cards can not use the generic count PCIe functions method,
7867 * because they are behind a parent switch, so we hardcode these with
7868 * the correct number of functions.
e027d1ae 7869 */
f1f96579 7870 if (ixgbe_pcie_from_parent(&adapter->hw)) {
e027d1ae 7871 physfns = 4;
f1f96579 7872 } else {
e027d1ae
JK		 7873 list_for_each(entry, &adapter->pdev->bus_list) {
7874 struct pci_dev *pdev =
7875 list_entry(entry, struct pci_dev, bus_list);
7876 /* don't count virtual functions */
7877 if (!pdev->is_virtfn)
7878 physfns++;
7879 }
7880 }
7881
7882 return physfns;
7883}
7884
8e2813f5
JK		 7885/**
7886 * ixgbe_wol_supported - Check whether device supports WoL
7887 * @hw: hw specific details
7888 * @device_id: the device ID
7889 * @subdev_id: the subsystem device ID
7890 *
7891 * This function is used by probe and ethtool to determine
7892 * which devices have WoL support
7893 *
7894 **/
7895int ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
7896 u16 subdevice_id)
7897{
7898 struct ixgbe_hw *hw = &adapter->hw;
7899 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
7900 int is_wol_supported = 0;
7901
7902 switch (device_id) {
7903 case IXGBE_DEV_ID_82599_SFP:
7904 /* Only these subdevices could supports WOL */
7905 switch (subdevice_id) {
87557440 7906 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
8e2813f5
JK		 7907 case IXGBE_SUBDEV_ID_82599_560FLR:
7908 /* only support first port */
7909 if (hw->bus.func != 0)
7910 break;
5700ff26 7911 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
8e2813f5 7912 case IXGBE_SUBDEV_ID_82599_SFP:
b6dfd939 7913 case IXGBE_SUBDEV_ID_82599_RNDC:
f8a06c2c 7914 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
979fe5f7 7915 case IXGBE_SUBDEV_ID_82599_LOM_SFP:
8e2813f5
JK		 7916 is_wol_supported = 1;
7917 break;
7918 }
7919 break;
5daebbb0
DS		 7920 case IXGBE_DEV_ID_82599EN_SFP:
7921 /* Only this subdevice supports WOL */
7922 switch (subdevice_id) {
7923 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
7924 is_wol_supported = 1;
7925 break;
7926 }
7927 break;
8e2813f5
JK		 7928 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7929 /* All except this subdevice support WOL */
7930 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7931 is_wol_supported = 1;
7932 break;
7933 case IXGBE_DEV_ID_82599_KX4:
7934 is_wol_supported = 1;
7935 break;
7936 case IXGBE_DEV_ID_X540T:
df376f0d 7937 case IXGBE_DEV_ID_X540T1:
8e2813f5
JK		 7938 /* check eeprom to see if enabled wol */
7939 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
7940 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
7941 (hw->bus.func == 0))) {
7942 is_wol_supported = 1;
7943 }
7944 break;
7945 }
7946
7947 return is_wol_supported;
7948}
7949
9a799d71
AK		 7950/**
7951 * ixgbe_probe - Device Initialization Routine
7952 * @pdev: PCI device information struct
7953 * @ent: entry in ixgbe_pci_tbl
7954 *
7955 * Returns 0 on success, negative on failure
7956 *
7957 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7958 * The OS initialization, configuring of the adapter private structure,
7959 * and a hardware reset occur.
7960 **/
1dd06ae8 7961static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
9a799d71
AK		 7962{
7963 struct net_device *netdev;
7964 struct ixgbe_adapter *adapter = NULL;
7965 struct ixgbe_hw *hw;
7966 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
9a799d71 7967 static int cards_found;
e027d1ae 7968 int i, err, pci_using_dac, expected_gts;
d3cb9869 7969 unsigned int indices = MAX_TX_QUEUES;
289700db 7970 u8 part_str[IXGBE_PBANUM_LENGTH];
eacd73f7
YZ		 7971#ifdef IXGBE_FCOE
7972 u16 device_caps;
7973#endif
289700db 7974 u32 eec;
9a799d71 7975
bded64a7
AG		 7976 /* Catch broken hardware that put the wrong VF device ID in
7977 * the PCIe SR-IOV capability.
7978 */
7979 if (pdev->is_virtfn) {
7980 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7981 pci_name(pdev), pdev->vendor, pdev->device);
7982 return -EINVAL;
7983 }
7984
9ce77666 7985 err = pci_enable_device_mem(pdev);
9a799d71
AK		 7986 if (err)
7987 return err;
7988
f5f2eda8 7989 if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
9a799d71
AK		 7990 pci_using_dac = 1;
7991 } else {
f5f2eda8 7992 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
9a799d71 7993 if (err) {
f5f2eda8
RK		 7994 dev_err(&pdev->dev,
7995 "No usable DMA configuration, aborting\n");
7996 goto err_dma;
9a799d71
AK		 7997 }
7998 pci_using_dac = 0;
7999 }
8000
9ce77666 8001 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8002 IORESOURCE_MEM), ixgbe_driver_name);
9a799d71 8003 if (err) {
b8bc0421
DC		 8004 dev_err(&pdev->dev,
8005 "pci_request_selected_regions failed 0x%x\n", err);
9a799d71
AK		 8006 goto err_pci_reg;
8007 }
8008
19d5afd4 8009 pci_enable_pcie_error_reporting(pdev);
6fabd715 8010
9a799d71 8011 pci_set_master(pdev);
fb3b27bc 8012 pci_save_state(pdev);
9a799d71 8013
d3cb9869 8014 if (ii->mac == ixgbe_mac_82598EB) {
e901acd6 8015#ifdef CONFIG_IXGBE_DCB
d3cb9869
AD		 8016 /* 8 TC w/ 4 queues per TC */
8017 indices = 4 * MAX_TRAFFIC_CLASS;
8018#else
8019 indices = IXGBE_MAX_RSS_INDICES;
e901acd6 8020#endif
d3cb9869 8021 }
e901acd6 8022
c85a2618 8023 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
9a799d71
AK		 8024 if (!netdev) {
8025 err = -ENOMEM;
8026 goto err_alloc_etherdev;
8027 }
8028
9a799d71
AK		 8029 SET_NETDEV_DEV(netdev, &pdev->dev);
8030
9a799d71 8031 adapter = netdev_priv(netdev);
c60fbb00 8032 pci_set_drvdata(pdev, adapter);
9a799d71
AK		 8033
8034 adapter->netdev = netdev;
8035 adapter->pdev = pdev;
8036 hw = &adapter->hw;
8037 hw->back = adapter;
b3f4d599 8038 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
9a799d71 8039
05857980 8040 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
e8e9f696 8041 pci_resource_len(pdev, 0));
2a1a091c 8042 adapter->io_addr = hw->hw_addr;
9a799d71
AK		 8043 if (!hw->hw_addr) {
8044 err = -EIO;
8045 goto err_ioremap;
8046 }
8047
0edc3527 8048 netdev->netdev_ops = &ixgbe_netdev_ops;
9a799d71 8049 ixgbe_set_ethtool_ops(netdev);
9a799d71 8050 netdev->watchdog_timeo = 5 * HZ;
9fe93afd 8051 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
9a799d71 8052
9a799d71
AK		 8053 adapter->bd_number = cards_found;
8054
9a799d71
AK		 8055 /* Setup hw api */
8056 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
021230d4 8057 hw->mac.type = ii->mac;
9a799d71 8058
c44ade9e
JB		 8059 /* EEPROM */
8060 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
8061 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
58cf663f
MR		 8062 if (ixgbe_removed(hw->hw_addr)) {
8063 err = -EIO;
8064 goto err_ioremap;
8065 }
c44ade9e
JB		 8066 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
8067 if (!(eec & (1 << 8)))
8068 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
8069
8070 /* PHY */
8071 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
c4900be0 8072 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6b73e10d
BH		 8073 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
8074 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
8075 hw->phy.mdio.mmds = 0;
8076 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
8077 hw->phy.mdio.dev = netdev;
8078 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
8079 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
c4900be0 8080
8ca783ab 8081 ii->get_invariants(hw);
9a799d71
AK		 8082
8083 /* setup the private structure */
8084 err = ixgbe_sw_init(adapter);
8085 if (err)
8086 goto err_sw_init;
8087
e86bff0e 8088 /* Make it possible the adapter to be woken up via WOL */
b93a2226
DS		 8089 switch (adapter->hw.mac.type) {
8090 case ixgbe_mac_82599EB:
8091 case ixgbe_mac_X540:
e86bff0e 8092 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
b93a2226
DS		 8093 break;
8094 default:
8095 break;
8096 }
e86bff0e 8097
bf069c97
DS		 8098 /*
8099 * If there is a fan on this device and it has failed log the
8100 * failure.
8101 */
8102 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
8103 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
8104 if (esdp & IXGBE_ESDP_SDP1)
396e799c 8105 e_crit(probe, "Fan has stopped, replace the adapter\n");
bf069c97
DS		 8106 }
8107
8ef78adc
PWJ		 8108 if (allow_unsupported_sfp)
8109 hw->allow_unsupported_sfp = allow_unsupported_sfp;
8110
c44ade9e 8111 /* reset_hw fills in the perm_addr as well */
119fc60a 8112 hw->phy.reset_if_overtemp = true;
c44ade9e 8113 err = hw->mac.ops.reset_hw(hw);
119fc60a 8114 hw->phy.reset_if_overtemp = false;
8ca783ab
DS		 8115 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
8116 hw->mac.type == ixgbe_mac_82598EB) {
8ca783ab
DS		 8117 err = 0;
8118 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
1b1bf31a
DS		 8119 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
8120 e_dev_err("Reload the driver after installing a supported module.\n");
04f165ef
PW		 8121 goto err_sw_init;
8122 } else if (err) {
849c4542 8123 e_dev_err("HW Init failed: %d\n", err);
c44ade9e
JB		 8124 goto err_sw_init;
8125 }
8126
99d74487 8127#ifdef CONFIG_PCI_IOV
60a1a680
GR		 8128 /* SR-IOV not supported on the 82598 */
8129 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
8130 goto skip_sriov;
8131 /* Mailbox */
8132 ixgbe_init_mbx_params_pf(hw);
8133 memcpy(&hw->mbx.ops, ii->mbx_ops, sizeof(hw->mbx.ops));
dcc23e3a 8134 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
31ac910e 8135 ixgbe_enable_sriov(adapter);
60a1a680 8136skip_sriov:
1cdd1ec8 8137
99d74487 8138#endif
396e799c 8139 netdev->features = NETIF_F_SG |
e8e9f696 8140 NETIF_F_IP_CSUM |
082757af 8141 NETIF_F_IPV6_CSUM |
f646968f
PM		 8142 NETIF_F_HW_VLAN_CTAG_TX |
8143 NETIF_F_HW_VLAN_CTAG_RX |
8144 NETIF_F_HW_VLAN_CTAG_FILTER |
082757af
DS		 8145 NETIF_F_TSO |
8146 NETIF_F_TSO6 |
082757af 8147 NETIF_F_RXHASH |
8bf1264d 8148 NETIF_F_RXCSUM;
9a799d71 8149
8bf1264d 8150 netdev->hw_features = netdev->features | NETIF_F_HW_L2FW_DOFFLOAD;
ad31c402 8151
58be7666
DS		 8152 switch (adapter->hw.mac.type) {
8153 case ixgbe_mac_82599EB:
8154 case ixgbe_mac_X540:
45a5ead0 8155 netdev->features |= NETIF_F_SCTP_CSUM;
082757af
DS		 8156 netdev->hw_features |= NETIF_F_SCTP_CSUM |
8157 NETIF_F_NTUPLE;
58be7666
DS		 8158 break;
8159 default:
8160 break;
8161 }
45a5ead0 8162
3f2d1c0f
BG		 8163 netdev->hw_features |= NETIF_F_RXALL;
8164
ad31c402
JK		 8165 netdev->vlan_features |= NETIF_F_TSO;
8166 netdev->vlan_features |= NETIF_F_TSO6;
22f32b7a 8167 netdev->vlan_features |= NETIF_F_IP_CSUM;
cd1da503 8168 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
ad31c402
JK		 8169 netdev->vlan_features |= NETIF_F_SG;
8170
01789349 8171 netdev->priv_flags |= IFF_UNICAST_FLT;
f43f313e 8172 netdev->priv_flags |= IFF_SUPP_NOFCS;
01789349 8173
7a6b6f51 8174#ifdef CONFIG_IXGBE_DCB
2f90b865
AD		 8175 netdev->dcbnl_ops = &dcbnl_ops;
8176#endif
8177
eacd73f7 8178#ifdef IXGBE_FCOE
0d551589 8179 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
d3cb9869
AD		 8180 unsigned int fcoe_l;
8181
eacd73f7
YZ		 8182 if (hw->mac.ops.get_device_caps) {
8183 hw->mac.ops.get_device_caps(hw, &device_caps);
0d551589
YZ		 8184 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
8185 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
eacd73f7 8186 }
7c8ae65a 8187
d3cb9869
AD		 8188
8189 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
8190 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
7c8ae65a 8191
a58915c7
AD		 8192 netdev->features |= NETIF_F_FSO |
8193 NETIF_F_FCOE_CRC;
8194
7c8ae65a
AD		 8195 netdev->vlan_features |= NETIF_F_FSO |
8196 NETIF_F_FCOE_CRC |
8197 NETIF_F_FCOE_MTU;
5e09d7f6 8198 }
eacd73f7 8199#endif /* IXGBE_FCOE */
7b872a55 8200 if (pci_using_dac) {
9a799d71 8201 netdev->features |= NETIF_F_HIGHDMA;
7b872a55
YZ		 8202 netdev->vlan_features |= NETIF_F_HIGHDMA;
8203 }
9a799d71 8204
082757af
DS		 8205 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
8206 netdev->hw_features |= NETIF_F_LRO;
0c19d6af 8207 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
f8212f97
AD		 8208 netdev->features |= NETIF_F_LRO;
8209
9a799d71 8210 /* make sure the EEPROM is good */
c44ade9e 8211 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
849c4542 8212 e_dev_err("The EEPROM Checksum Is Not Valid\n");
9a799d71 8213 err = -EIO;
35937c05 8214 goto err_sw_init;
9a799d71
AK		 8215 }
8216
8217 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
9a799d71 8218
aaeb6cdf 8219 if (!is_valid_ether_addr(netdev->dev_addr)) {
849c4542 8220 e_dev_err("invalid MAC address\n");
9a799d71 8221 err = -EIO;
35937c05 8222 goto err_sw_init;
9a799d71
AK		 8223 }
8224
7086400d 8225 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
581330ba 8226 (unsigned long) adapter);
9a799d71 8227
58cf663f
MR		 8228 if (ixgbe_removed(hw->hw_addr)) {
8229 err = -EIO;
8230 goto err_sw_init;
8231 }
7086400d 8232 INIT_WORK(&adapter->service_task, ixgbe_service_task);
58cf663f 8233 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
7086400d 8234 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
9a799d71 8235
021230d4
AV		 8236 err = ixgbe_init_interrupt_scheme(adapter);
8237 if (err)
8238 goto err_sw_init;
9a799d71 8239
8e2813f5 8240 /* WOL not supported for all devices */
c23f5b6b 8241 adapter->wol = 0;
8e2813f5 8242 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
6b92b0ba 8243 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
b8f83638 8244 pdev->subsystem_device);
6b92b0ba 8245 if (hw->wol_enabled)
9417c464 8246 adapter->wol = IXGBE_WUFC_MAG;
c23f5b6b 8247
e8e26350
PW		 8248 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
8249
15e5209f
ET		 8250 /* save off EEPROM version number */
8251 hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh);
8252 hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
8253
04f165ef
PW		 8254 /* pick up the PCI bus settings for reporting later */
8255 hw->mac.ops.get_bus_info(hw);
e027d1ae 8256 if (ixgbe_pcie_from_parent(hw))
b8e82001 8257 ixgbe_get_parent_bus_info(adapter);
04f165ef 8258
e027d1ae
JK		 8259 /* calculate the expected PCIe bandwidth required for optimal
8260 * performance. Note that some older parts will never have enough
8261 * bandwidth due to being older generation PCIe parts. We clamp these
8262 * parts to ensure no warning is displayed if it can't be fixed.
8263 */
8264 switch (hw->mac.type) {
8265 case ixgbe_mac_82598EB:
8266 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
8267 break;
8268 default:
8269 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
8270 break;
0c254d86 8271 }
e027d1ae 8272 ixgbe_check_minimum_link(adapter, expected_gts);
0c254d86 8273
6a2aae5a
JK		 8274 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
8275 if (err)
8276 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
8277 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
8278 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
8279 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
8280 part_str);
8281 else
8282 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
8283 hw->mac.type, hw->phy.type, part_str);
8284
8285 e_dev_info("%pM\n", netdev->dev_addr);
8286
9a799d71 8287 /* reset the hardware with the new settings */
794caeb2 8288 err = hw->mac.ops.start_hw(hw);
794caeb2
PWJ		 8289 if (err == IXGBE_ERR_EEPROM_VERSION) {
8290 /* We are running on a pre-production device, log a warning */
849c4542
ET		 8291 e_dev_warn("This device is a pre-production adapter/LOM. "
8292 "Please be aware there may be issues associated "
8293 "with your hardware. If you are experiencing "
8294 "problems please contact your Intel or hardware "
8295 "representative who provided you with this "
8296 "hardware.\n");
794caeb2 8297 }
9a799d71
AK		 8298 strcpy(netdev->name, "eth%d");
8299 err = register_netdev(netdev);
8300 if (err)
8301 goto err_register;
8302
ec74a471
ET		 8303 /* power down the optics for 82599 SFP+ fiber */
8304 if (hw->mac.ops.disable_tx_laser)
93d3ce8f
ET		 8305 hw->mac.ops.disable_tx_laser(hw);
8306
54386467
JB		 8307 /* carrier off reporting is important to ethtool even BEFORE open */
8308 netif_carrier_off(netdev);
8309
5dd2d332 8310#ifdef CONFIG_IXGBE_DCA
652f093f 8311 if (dca_add_requester(&pdev->dev) == 0) {
bd0362dd 8312 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
bd0362dd
JC		 8313 ixgbe_setup_dca(adapter);
8314 }
8315#endif
1cdd1ec8 8316 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
396e799c 8317 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
1cdd1ec8
GR		 8318 for (i = 0; i < adapter->num_vfs; i++)
8319 ixgbe_vf_configuration(pdev, (i | 0x10000000));
8320 }
8321
2466dd9c
JK		 8322 /* firmware requires driver version to be 0xFFFFFFFF
8323 * since os does not support feature
8324 */
9612de92 8325 if (hw->mac.ops.set_fw_drv_ver)
2466dd9c
JK		 8326 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF,
8327 0xFF);
9612de92 8328
0365e6e4
PW		 8329 /* add san mac addr to netdev */
8330 ixgbe_add_sanmac_netdev(netdev);
9a799d71 8331
ea81875a 8332 e_dev_info("%s\n", ixgbe_default_device_descr);
9a799d71 8333 cards_found++;
3ca8bc6d 8334
1210982b 8335#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d
DS		 8336 if (ixgbe_sysfs_init(adapter))
8337 e_err(probe, "failed to allocate sysfs resources\n");
1210982b 8338#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8339
00949167 8340 ixgbe_dbg_adapter_init(adapter);
00949167 8341
0b2679d6 8342 /* Need link setup for MNG FW, else wait for IXGBE_UP */
7155d051 8343 if (ixgbe_mng_enabled(hw) && hw->mac.ops.setup_link)
0b2679d6
DS		 8344 hw->mac.ops.setup_link(hw,
8345 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
8346 true);
8347
9a799d71
AK		 8348 return 0;
8349
8350err_register:
5eba3699 8351 ixgbe_release_hw_control(adapter);
7a921c93 8352 ixgbe_clear_interrupt_scheme(adapter);
9a799d71 8353err_sw_init:
99d74487 8354 ixgbe_disable_sriov(adapter);
7086400d 8355 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
2a1a091c 8356 iounmap(adapter->io_addr);
9a799d71
AK		 8357err_ioremap:
8358 free_netdev(netdev);
8359err_alloc_etherdev:
e8e9f696
JP		 8360 pci_release_selected_regions(pdev,
8361 pci_select_bars(pdev, IORESOURCE_MEM));
9a799d71
AK		 8362err_pci_reg:
8363err_dma:
41c62843
MR		 8364 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8365 pci_disable_device(pdev);
9a799d71
AK		 8366 return err;
8367}
8368
8369/**
8370 * ixgbe_remove - Device Removal Routine
8371 * @pdev: PCI device information struct
8372 *
8373 * ixgbe_remove is called by the PCI subsystem to alert the driver
8374 * that it should release a PCI device. The could be caused by a
8375 * Hot-Plug event, or because the driver is going to be removed from
8376 * memory.
8377 **/
9f9a12f8 8378static void ixgbe_remove(struct pci_dev *pdev)
9a799d71 8379{
c60fbb00
AD		 8380 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8381 struct net_device *netdev = adapter->netdev;
9a799d71 8382
00949167 8383 ixgbe_dbg_adapter_exit(adapter);
00949167 8384
09f40aed 8385 set_bit(__IXGBE_REMOVING, &adapter->state);
7086400d 8386 cancel_work_sync(&adapter->service_task);
9a799d71 8387
3a6a4eda 8388
5dd2d332 8389#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8390 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
8391 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
8392 dca_remove_requester(&pdev->dev);
8393 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
8394 }
8395
8396#endif
1210982b 8397#ifdef CONFIG_IXGBE_HWMON
3ca8bc6d 8398 ixgbe_sysfs_exit(adapter);
1210982b 8399#endif /* CONFIG_IXGBE_HWMON */
3ca8bc6d 8400
0365e6e4
PW		 8401 /* remove the added san mac */
8402 ixgbe_del_sanmac_netdev(netdev);
8403
c4900be0
DS		 8404 if (netdev->reg_state == NETREG_REGISTERED)
8405 unregister_netdev(netdev);
9a799d71 8406
da36b647
GR		 8407#ifdef CONFIG_PCI_IOV
8408 /*
8409 * Only disable SR-IOV on unload if the user specified the now
8410 * deprecated max_vfs module parameter.
8411 */
8412 if (max_vfs)
8413 ixgbe_disable_sriov(adapter);
8414#endif
7a921c93 8415 ixgbe_clear_interrupt_scheme(adapter);
5eba3699 8416
021230d4 8417 ixgbe_release_hw_control(adapter);
9a799d71 8418
2b1588c3
AD		 8419#ifdef CONFIG_DCB
8420 kfree(adapter->ixgbe_ieee_pfc);
8421 kfree(adapter->ixgbe_ieee_ets);
8422
8423#endif
2a1a091c 8424 iounmap(adapter->io_addr);
9ce77666 8425 pci_release_selected_regions(pdev, pci_select_bars(pdev,
e8e9f696 8426 IORESOURCE_MEM));
9a799d71 8427
849c4542 8428 e_dev_info("complete\n");
021230d4 8429
9a799d71
AK		 8430 free_netdev(netdev);
8431
19d5afd4 8432 pci_disable_pcie_error_reporting(pdev);
6fabd715 8433
41c62843
MR		 8434 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8435 pci_disable_device(pdev);
9a799d71
AK		 8436}
8437
8438/**
8439 * ixgbe_io_error_detected - called when PCI error is detected
8440 * @pdev: Pointer to PCI device
8441 * @state: The current pci connection state
8442 *
8443 * This function is called after a PCI bus error affecting
8444 * this device has been detected.
8445 */
8446static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
e8e9f696 8447 pci_channel_state_t state)
9a799d71 8448{
c60fbb00
AD		 8449 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8450 struct net_device *netdev = adapter->netdev;
9a799d71 8451
83c61fa9 8452#ifdef CONFIG_PCI_IOV
14438464 8453 struct ixgbe_hw *hw = &adapter->hw;
83c61fa9
GR		 8454 struct pci_dev *bdev, *vfdev;
8455 u32 dw0, dw1, dw2, dw3;
8456 int vf, pos;
8457 u16 req_id, pf_func;
8458
8459 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
8460 adapter->num_vfs == 0)
8461 goto skip_bad_vf_detection;
8462
8463 bdev = pdev->bus->self;
62f87c0e 8464 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
83c61fa9
GR		 8465 bdev = bdev->bus->self;
8466
8467 if (!bdev)
8468 goto skip_bad_vf_detection;
8469
8470 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
8471 if (!pos)
8472 goto skip_bad_vf_detection;
8473
14438464
MR		 8474 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
8475 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
8476 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
8477 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
8478 if (ixgbe_removed(hw->hw_addr))
8479 goto skip_bad_vf_detection;
83c61fa9
GR		 8480
8481 req_id = dw1 >> 16;
8482 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
8483 if (!(req_id & 0x0080))
8484 goto skip_bad_vf_detection;
8485
8486 pf_func = req_id & 0x01;
8487 if ((pf_func & 1) == (pdev->devfn & 1)) {
8488 unsigned int device_id;
8489
8490 vf = (req_id & 0x7F) >> 1;
8491 e_dev_err("VF %d has caused a PCIe error\n", vf);
8492 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
8493 "%8.8x\tdw3: %8.8x\n",
8494 dw0, dw1, dw2, dw3);
8495 switch (adapter->hw.mac.type) {
8496 case ixgbe_mac_82599EB:
8497 device_id = IXGBE_82599_VF_DEVICE_ID;
8498 break;
8499 case ixgbe_mac_X540:
8500 device_id = IXGBE_X540_VF_DEVICE_ID;
8501 break;
8502 default:
8503 device_id = 0;
8504 break;
8505 }
8506
8507 /* Find the pci device of the offending VF */
36e90319 8508 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
83c61fa9
GR		 8509 while (vfdev) {
8510 if (vfdev->devfn == (req_id & 0xFF))
8511 break;
36e90319 8512 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
83c61fa9
GR		 8513 device_id, vfdev);
8514 }
8515 /*
8516 * There's a slim chance the VF could have been hot plugged,
8517 * so if it is no longer present we don't need to issue the
8518 * VFLR. Just clean up the AER in that case.
8519 */
8520 if (vfdev) {
8521 e_dev_err("Issuing VFLR to VF %d\n", vf);
8522 pci_write_config_dword(vfdev, 0xA8, 0x00008000);
b4fafbe9
GR		 8523 /* Free device reference count */
8524 pci_dev_put(vfdev);
83c61fa9
GR		 8525 }
8526
8527 pci_cleanup_aer_uncorrect_error_status(pdev);
8528 }
8529
8530 /*
8531 * Even though the error may have occurred on the other port
8532 * we still need to increment the vf error reference count for
8533 * both ports because the I/O resume function will be called
8534 * for both of them.
8535 */
8536 adapter->vferr_refcount++;
8537
8538 return PCI_ERS_RESULT_RECOVERED;
8539
8540skip_bad_vf_detection:
8541#endif /* CONFIG_PCI_IOV */
58cf663f
MR		 8542 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
8543 return PCI_ERS_RESULT_DISCONNECT;
8544
41c62843 8545 rtnl_lock();
9a799d71
AK		 8546 netif_device_detach(netdev);
8547
41c62843
MR		 8548 if (state == pci_channel_io_perm_failure) {
8549 rtnl_unlock();
3044b8d1 8550 return PCI_ERS_RESULT_DISCONNECT;
41c62843 8551 }
3044b8d1 8552
9a799d71
AK		 8553 if (netif_running(netdev))
8554 ixgbe_down(adapter);
41c62843
MR		 8555
8556 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
8557 pci_disable_device(pdev);
8558 rtnl_unlock();
9a799d71 8559
b4617240 8560 /* Request a slot reset. */
9a799d71
AK		 8561 return PCI_ERS_RESULT_NEED_RESET;
8562}
8563
8564/**
8565 * ixgbe_io_slot_reset - called after the pci bus has been reset.
8566 * @pdev: Pointer to PCI device
8567 *
8568 * Restart the card from scratch, as if from a cold-boot.
8569 */
8570static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
8571{
c60fbb00 8572 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6fabd715
PWJ		 8573 pci_ers_result_t result;
8574 int err;
9a799d71 8575
9ce77666 8576 if (pci_enable_device_mem(pdev)) {
396e799c 8577 e_err(probe, "Cannot re-enable PCI device after reset.\n");
6fabd715
PWJ		 8578 result = PCI_ERS_RESULT_DISCONNECT;
8579 } else {
41c62843
MR		 8580 smp_mb__before_clear_bit();
8581 clear_bit(__IXGBE_DISABLED, &adapter->state);
0391bbe3 8582 adapter->hw.hw_addr = adapter->io_addr;
6fabd715
PWJ		 8583 pci_set_master(pdev);
8584 pci_restore_state(pdev);
c0e1f68b 8585 pci_save_state(pdev);
9a799d71 8586
dd4d8ca6 8587 pci_wake_from_d3(pdev, false);
9a799d71 8588
6fabd715 8589 ixgbe_reset(adapter);
88512539 8590 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6fabd715
PWJ		 8591 result = PCI_ERS_RESULT_RECOVERED;
8592 }
8593
8594 err = pci_cleanup_aer_uncorrect_error_status(pdev);
8595 if (err) {
849c4542
ET		 8596 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
8597 "failed 0x%0x\n", err);
6fabd715
PWJ		 8598 /* non-fatal, continue */
8599 }
9a799d71 8600
6fabd715 8601 return result;
9a799d71
AK		 8602}
8603
8604/**
8605 * ixgbe_io_resume - called when traffic can start flowing again.
8606 * @pdev: Pointer to PCI device
8607 *
8608 * This callback is called when the error recovery driver tells us that
8609 * its OK to resume normal operation.
8610 */
8611static void ixgbe_io_resume(struct pci_dev *pdev)
8612{
c60fbb00
AD		 8613 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
8614 struct net_device *netdev = adapter->netdev;
9a799d71 8615
83c61fa9
GR		 8616#ifdef CONFIG_PCI_IOV
8617 if (adapter->vferr_refcount) {
8618 e_info(drv, "Resuming after VF err\n");
8619 adapter->vferr_refcount--;
8620 return;
8621 }
8622
8623#endif
c7ccde0f
AD		 8624 if (netif_running(netdev))
8625 ixgbe_up(adapter);
9a799d71
AK		 8626
8627 netif_device_attach(netdev);
9a799d71
AK		 8628}
8629
3646f0e5 8630static const struct pci_error_handlers ixgbe_err_handler = {
9a799d71
AK		 8631 .error_detected = ixgbe_io_error_detected,
8632 .slot_reset = ixgbe_io_slot_reset,
8633 .resume = ixgbe_io_resume,
8634};
8635
8636static struct pci_driver ixgbe_driver = {
8637 .name = ixgbe_driver_name,
8638 .id_table = ixgbe_pci_tbl,
8639 .probe = ixgbe_probe,
9f9a12f8 8640 .remove = ixgbe_remove,
9a799d71
AK		 8641#ifdef CONFIG_PM
8642 .suspend = ixgbe_suspend,
8643 .resume = ixgbe_resume,
8644#endif
8645 .shutdown = ixgbe_shutdown,
da36b647 8646 .sriov_configure = ixgbe_pci_sriov_configure,
9a799d71
AK		 8647 .err_handler = &ixgbe_err_handler
8648};
8649
8650/**
8651 * ixgbe_init_module - Driver Registration Routine
8652 *
8653 * ixgbe_init_module is the first routine called when the driver is
8654 * loaded. All it does is register with the PCI subsystem.
8655 **/
8656static int __init ixgbe_init_module(void)
8657{
8658 int ret;
c7689578 8659 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
849c4542 8660 pr_info("%s\n", ixgbe_copyright);
9a799d71 8661
00949167 8662 ixgbe_dbg_init();
00949167 8663
f01fc1a8
JK		 8664 ret = pci_register_driver(&ixgbe_driver);
8665 if (ret) {
f01fc1a8 8666 ixgbe_dbg_exit();
f01fc1a8
JK		 8667 return ret;
8668 }
8669
5dd2d332 8670#ifdef CONFIG_IXGBE_DCA
bd0362dd 8671 dca_register_notify(&dca_notifier);
bd0362dd 8672#endif
5dd2d332 8673
f01fc1a8 8674 return 0;
9a799d71 8675}
b4617240 8676
9a799d71
AK		 8677module_init(ixgbe_init_module);
8678
8679/**
8680 * ixgbe_exit_module - Driver Exit Cleanup Routine
8681 *
8682 * ixgbe_exit_module is called just before the driver is removed
8683 * from memory.
8684 **/
8685static void __exit ixgbe_exit_module(void)
8686{
5dd2d332 8687#ifdef CONFIG_IXGBE_DCA
bd0362dd
JC		 8688 dca_unregister_notify(&dca_notifier);
8689#endif
9a799d71 8690 pci_unregister_driver(&ixgbe_driver);
00949167 8691
00949167 8692 ixgbe_dbg_exit();
00949167 8693
1a51502b 8694 rcu_barrier(); /* Wait for completion of call_rcu()'s */
9a799d71 8695}
bd0362dd 8696
5dd2d332 8697#ifdef CONFIG_IXGBE_DCA
bd0362dd 8698static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
e8e9f696 8699 void *p)
bd0362dd
JC		 8700{
8701 int ret_val;
8702
8703 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
e8e9f696 8704 __ixgbe_notify_dca);
bd0362dd
JC		 8705
8706 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
8707}
b453368d 8708
5dd2d332 8709#endif /* CONFIG_IXGBE_DCA */
849c4542 8710
9a799d71
AK		 8711module_exit(ixgbe_exit_module);
8712
8713/* ixgbe_main.c */
Linux kernel - Deliverables
This page took 1.840515 seconds and 5 git commands to generate.