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9a799d71 AK |
1 | /******************************************************************************* |
2 | ||
3 | Intel 10 Gigabit PCI Express Linux driver | |
94971820 | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
9a799d71 AK |
5 | |
6 | This program is free software; you can redistribute it and/or modify it | |
7 | under the terms and conditions of the GNU General Public License, | |
8 | version 2, as published by the Free Software Foundation. | |
9 | ||
10 | This program is distributed in the hope it will be useful, but WITHOUT | |
11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | more details. | |
14 | ||
15 | You should have received a copy of the GNU General Public License along with | |
16 | this program; if not, write to the Free Software Foundation, Inc., | |
17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
18 | ||
19 | The full GNU General Public License is included in this distribution in | |
20 | the file called "COPYING". | |
21 | ||
22 | Contact Information: | |
9a799d71 AK |
23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 | |
25 | ||
26 | *******************************************************************************/ | |
27 | ||
28 | #include <linux/types.h> | |
29 | #include <linux/module.h> | |
30 | #include <linux/pci.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/vmalloc.h> | |
33 | #include <linux/string.h> | |
34 | #include <linux/in.h> | |
a6b7a407 | 35 | #include <linux/interrupt.h> |
9a799d71 AK |
36 | #include <linux/ip.h> |
37 | #include <linux/tcp.h> | |
897ab156 | 38 | #include <linux/sctp.h> |
60127865 | 39 | #include <linux/pkt_sched.h> |
9a799d71 | 40 | #include <linux/ipv6.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
9a799d71 AK |
42 | #include <net/checksum.h> |
43 | #include <net/ip6_checksum.h> | |
44 | #include <linux/ethtool.h> | |
01789349 | 45 | #include <linux/if.h> |
9a799d71 | 46 | #include <linux/if_vlan.h> |
70c71606 | 47 | #include <linux/prefetch.h> |
eacd73f7 | 48 | #include <scsi/fc/fc_fcoe.h> |
9a799d71 AK |
49 | |
50 | #include "ixgbe.h" | |
51 | #include "ixgbe_common.h" | |
ee5f784a | 52 | #include "ixgbe_dcb_82599.h" |
1cdd1ec8 | 53 | #include "ixgbe_sriov.h" |
9a799d71 AK |
54 | |
55 | char ixgbe_driver_name[] = "ixgbe"; | |
9c8eb720 | 56 | static const char ixgbe_driver_string[] = |
e8e9f696 | 57 | "Intel(R) 10 Gigabit PCI Express Network Driver"; |
ea81875a NP |
58 | char ixgbe_default_device_descr[] = |
59 | "Intel(R) 10 Gigabit Network Connection"; | |
75e3d3c6 | 60 | #define MAJ 3 |
19d478bb DS |
61 | #define MIN 6 |
62 | #define BUILD 7 | |
75e3d3c6 | 63 | #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ |
a38a104d | 64 | __stringify(BUILD) "-k" |
9c8eb720 | 65 | const char ixgbe_driver_version[] = DRV_VERSION; |
a52055e0 | 66 | static const char ixgbe_copyright[] = |
94971820 | 67 | "Copyright (c) 1999-2012 Intel Corporation."; |
9a799d71 AK |
68 | |
69 | static const struct ixgbe_info *ixgbe_info_tbl[] = { | |
b4617240 | 70 | [board_82598] = &ixgbe_82598_info, |
e8e26350 | 71 | [board_82599] = &ixgbe_82599_info, |
fe15e8e1 | 72 | [board_X540] = &ixgbe_X540_info, |
9a799d71 AK |
73 | }; |
74 | ||
75 | /* ixgbe_pci_tbl - PCI Device ID Table | |
76 | * | |
77 | * Wildcard entries (PCI_ANY_ID) should come last | |
78 | * Last entry must be all 0s | |
79 | * | |
80 | * { Vendor ID, Device ID, SubVendor ID, SubDevice ID, | |
81 | * Class, Class Mask, private data (not used) } | |
82 | */ | |
a3aa1884 | 83 | static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = { |
54239c67 AD |
84 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 }, |
85 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 }, | |
86 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 }, | |
87 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 }, | |
88 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 }, | |
89 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 }, | |
90 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 }, | |
91 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 }, | |
92 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 }, | |
93 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 }, | |
94 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 }, | |
95 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 }, | |
96 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 }, | |
97 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 }, | |
98 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 }, | |
99 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 }, | |
100 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 }, | |
101 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 }, | |
102 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 }, | |
103 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 }, | |
104 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 }, | |
105 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 }, | |
106 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 }, | |
107 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 }, | |
108 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 }, | |
109 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 }, | |
7d145282 | 110 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 }, |
9e791e4a | 111 | {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 }, |
9a799d71 AK |
112 | /* required last entry */ |
113 | {0, } | |
114 | }; | |
115 | MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl); | |
116 | ||
5dd2d332 | 117 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 118 | static int ixgbe_notify_dca(struct notifier_block *, unsigned long event, |
e8e9f696 | 119 | void *p); |
bd0362dd JC |
120 | static struct notifier_block dca_notifier = { |
121 | .notifier_call = ixgbe_notify_dca, | |
122 | .next = NULL, | |
123 | .priority = 0 | |
124 | }; | |
125 | #endif | |
126 | ||
1cdd1ec8 GR |
127 | #ifdef CONFIG_PCI_IOV |
128 | static unsigned int max_vfs; | |
129 | module_param(max_vfs, uint, 0); | |
e8e9f696 JP |
130 | MODULE_PARM_DESC(max_vfs, |
131 | "Maximum number of virtual functions to allocate per physical function"); | |
1cdd1ec8 GR |
132 | #endif /* CONFIG_PCI_IOV */ |
133 | ||
8ef78adc PWJ |
134 | static unsigned int allow_unsupported_sfp; |
135 | module_param(allow_unsupported_sfp, uint, 0); | |
136 | MODULE_PARM_DESC(allow_unsupported_sfp, | |
137 | "Allow unsupported and untested SFP+ modules on 82599-based adapters"); | |
138 | ||
9a799d71 AK |
139 | MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>"); |
140 | MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver"); | |
141 | MODULE_LICENSE("GPL"); | |
142 | MODULE_VERSION(DRV_VERSION); | |
143 | ||
144 | #define DEFAULT_DEBUG_LEVEL_SHIFT 3 | |
145 | ||
7086400d AD |
146 | static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter) |
147 | { | |
148 | if (!test_bit(__IXGBE_DOWN, &adapter->state) && | |
149 | !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state)) | |
150 | schedule_work(&adapter->service_task); | |
151 | } | |
152 | ||
153 | static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter) | |
154 | { | |
155 | BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state)); | |
156 | ||
52f33af8 | 157 | /* flush memory to make sure state is correct before next watchdog */ |
7086400d AD |
158 | smp_mb__before_clear_bit(); |
159 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
160 | } | |
161 | ||
dcd79aeb TI |
162 | struct ixgbe_reg_info { |
163 | u32 ofs; | |
164 | char *name; | |
165 | }; | |
166 | ||
167 | static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = { | |
168 | ||
169 | /* General Registers */ | |
170 | {IXGBE_CTRL, "CTRL"}, | |
171 | {IXGBE_STATUS, "STATUS"}, | |
172 | {IXGBE_CTRL_EXT, "CTRL_EXT"}, | |
173 | ||
174 | /* Interrupt Registers */ | |
175 | {IXGBE_EICR, "EICR"}, | |
176 | ||
177 | /* RX Registers */ | |
178 | {IXGBE_SRRCTL(0), "SRRCTL"}, | |
179 | {IXGBE_DCA_RXCTRL(0), "DRXCTL"}, | |
180 | {IXGBE_RDLEN(0), "RDLEN"}, | |
181 | {IXGBE_RDH(0), "RDH"}, | |
182 | {IXGBE_RDT(0), "RDT"}, | |
183 | {IXGBE_RXDCTL(0), "RXDCTL"}, | |
184 | {IXGBE_RDBAL(0), "RDBAL"}, | |
185 | {IXGBE_RDBAH(0), "RDBAH"}, | |
186 | ||
187 | /* TX Registers */ | |
188 | {IXGBE_TDBAL(0), "TDBAL"}, | |
189 | {IXGBE_TDBAH(0), "TDBAH"}, | |
190 | {IXGBE_TDLEN(0), "TDLEN"}, | |
191 | {IXGBE_TDH(0), "TDH"}, | |
192 | {IXGBE_TDT(0), "TDT"}, | |
193 | {IXGBE_TXDCTL(0), "TXDCTL"}, | |
194 | ||
195 | /* List Terminator */ | |
196 | {} | |
197 | }; | |
198 | ||
199 | ||
200 | /* | |
201 | * ixgbe_regdump - register printout routine | |
202 | */ | |
203 | static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo) | |
204 | { | |
205 | int i = 0, j = 0; | |
206 | char rname[16]; | |
207 | u32 regs[64]; | |
208 | ||
209 | switch (reginfo->ofs) { | |
210 | case IXGBE_SRRCTL(0): | |
211 | for (i = 0; i < 64; i++) | |
212 | regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i)); | |
213 | break; | |
214 | case IXGBE_DCA_RXCTRL(0): | |
215 | for (i = 0; i < 64; i++) | |
216 | regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); | |
217 | break; | |
218 | case IXGBE_RDLEN(0): | |
219 | for (i = 0; i < 64; i++) | |
220 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i)); | |
221 | break; | |
222 | case IXGBE_RDH(0): | |
223 | for (i = 0; i < 64; i++) | |
224 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i)); | |
225 | break; | |
226 | case IXGBE_RDT(0): | |
227 | for (i = 0; i < 64; i++) | |
228 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i)); | |
229 | break; | |
230 | case IXGBE_RXDCTL(0): | |
231 | for (i = 0; i < 64; i++) | |
232 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); | |
233 | break; | |
234 | case IXGBE_RDBAL(0): | |
235 | for (i = 0; i < 64; i++) | |
236 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i)); | |
237 | break; | |
238 | case IXGBE_RDBAH(0): | |
239 | for (i = 0; i < 64; i++) | |
240 | regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i)); | |
241 | break; | |
242 | case IXGBE_TDBAL(0): | |
243 | for (i = 0; i < 64; i++) | |
244 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i)); | |
245 | break; | |
246 | case IXGBE_TDBAH(0): | |
247 | for (i = 0; i < 64; i++) | |
248 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i)); | |
249 | break; | |
250 | case IXGBE_TDLEN(0): | |
251 | for (i = 0; i < 64; i++) | |
252 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i)); | |
253 | break; | |
254 | case IXGBE_TDH(0): | |
255 | for (i = 0; i < 64; i++) | |
256 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i)); | |
257 | break; | |
258 | case IXGBE_TDT(0): | |
259 | for (i = 0; i < 64; i++) | |
260 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i)); | |
261 | break; | |
262 | case IXGBE_TXDCTL(0): | |
263 | for (i = 0; i < 64; i++) | |
264 | regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); | |
265 | break; | |
266 | default: | |
c7689578 | 267 | pr_info("%-15s %08x\n", reginfo->name, |
dcd79aeb TI |
268 | IXGBE_READ_REG(hw, reginfo->ofs)); |
269 | return; | |
270 | } | |
271 | ||
272 | for (i = 0; i < 8; i++) { | |
273 | snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7); | |
c7689578 | 274 | pr_err("%-15s", rname); |
dcd79aeb | 275 | for (j = 0; j < 8; j++) |
c7689578 JP |
276 | pr_cont(" %08x", regs[i*8+j]); |
277 | pr_cont("\n"); | |
dcd79aeb TI |
278 | } |
279 | ||
280 | } | |
281 | ||
282 | /* | |
283 | * ixgbe_dump - Print registers, tx-rings and rx-rings | |
284 | */ | |
285 | static void ixgbe_dump(struct ixgbe_adapter *adapter) | |
286 | { | |
287 | struct net_device *netdev = adapter->netdev; | |
288 | struct ixgbe_hw *hw = &adapter->hw; | |
289 | struct ixgbe_reg_info *reginfo; | |
290 | int n = 0; | |
291 | struct ixgbe_ring *tx_ring; | |
292 | struct ixgbe_tx_buffer *tx_buffer_info; | |
293 | union ixgbe_adv_tx_desc *tx_desc; | |
294 | struct my_u0 { u64 a; u64 b; } *u0; | |
295 | struct ixgbe_ring *rx_ring; | |
296 | union ixgbe_adv_rx_desc *rx_desc; | |
297 | struct ixgbe_rx_buffer *rx_buffer_info; | |
298 | u32 staterr; | |
299 | int i = 0; | |
300 | ||
301 | if (!netif_msg_hw(adapter)) | |
302 | return; | |
303 | ||
304 | /* Print netdevice Info */ | |
305 | if (netdev) { | |
306 | dev_info(&adapter->pdev->dev, "Net device Info\n"); | |
c7689578 | 307 | pr_info("Device Name state " |
dcd79aeb | 308 | "trans_start last_rx\n"); |
c7689578 JP |
309 | pr_info("%-15s %016lX %016lX %016lX\n", |
310 | netdev->name, | |
311 | netdev->state, | |
312 | netdev->trans_start, | |
313 | netdev->last_rx); | |
dcd79aeb TI |
314 | } |
315 | ||
316 | /* Print Registers */ | |
317 | dev_info(&adapter->pdev->dev, "Register Dump\n"); | |
c7689578 | 318 | pr_info(" Register Name Value\n"); |
dcd79aeb TI |
319 | for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl; |
320 | reginfo->name; reginfo++) { | |
321 | ixgbe_regdump(hw, reginfo); | |
322 | } | |
323 | ||
324 | /* Print TX Ring Summary */ | |
325 | if (!netdev || !netif_running(netdev)) | |
326 | goto exit; | |
327 | ||
328 | dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); | |
c7689578 | 329 | pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); |
dcd79aeb TI |
330 | for (n = 0; n < adapter->num_tx_queues; n++) { |
331 | tx_ring = adapter->tx_ring[n]; | |
332 | tx_buffer_info = | |
333 | &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; | |
d3d00239 | 334 | pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", |
dcd79aeb TI |
335 | n, tx_ring->next_to_use, tx_ring->next_to_clean, |
336 | (u64)tx_buffer_info->dma, | |
337 | tx_buffer_info->length, | |
338 | tx_buffer_info->next_to_watch, | |
339 | (u64)tx_buffer_info->time_stamp); | |
340 | } | |
341 | ||
342 | /* Print TX Rings */ | |
343 | if (!netif_msg_tx_done(adapter)) | |
344 | goto rx_ring_summary; | |
345 | ||
346 | dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); | |
347 | ||
348 | /* Transmit Descriptor Formats | |
349 | * | |
350 | * Advanced Transmit Descriptor | |
351 | * +--------------------------------------------------------------+ | |
352 | * 0 | Buffer Address [63:0] | | |
353 | * +--------------------------------------------------------------+ | |
354 | * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN | | |
355 | * +--------------------------------------------------------------+ | |
356 | * 63 46 45 40 39 36 35 32 31 24 23 20 19 0 | |
357 | */ | |
358 | ||
359 | for (n = 0; n < adapter->num_tx_queues; n++) { | |
360 | tx_ring = adapter->tx_ring[n]; | |
c7689578 JP |
361 | pr_info("------------------------------------\n"); |
362 | pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); | |
363 | pr_info("------------------------------------\n"); | |
364 | pr_info("T [desc] [address 63:0 ] " | |
dcd79aeb TI |
365 | "[PlPOIdStDDt Ln] [bi->dma ] " |
366 | "leng ntw timestamp bi->skb\n"); | |
367 | ||
368 | for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { | |
e4f74028 | 369 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
dcd79aeb TI |
370 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
371 | u0 = (struct my_u0 *)tx_desc; | |
c7689578 | 372 | pr_info("T [0x%03X] %016llX %016llX %016llX" |
d3d00239 | 373 | " %04X %p %016llX %p", i, |
dcd79aeb TI |
374 | le64_to_cpu(u0->a), |
375 | le64_to_cpu(u0->b), | |
376 | (u64)tx_buffer_info->dma, | |
377 | tx_buffer_info->length, | |
378 | tx_buffer_info->next_to_watch, | |
379 | (u64)tx_buffer_info->time_stamp, | |
380 | tx_buffer_info->skb); | |
381 | if (i == tx_ring->next_to_use && | |
382 | i == tx_ring->next_to_clean) | |
c7689578 | 383 | pr_cont(" NTC/U\n"); |
dcd79aeb | 384 | else if (i == tx_ring->next_to_use) |
c7689578 | 385 | pr_cont(" NTU\n"); |
dcd79aeb | 386 | else if (i == tx_ring->next_to_clean) |
c7689578 | 387 | pr_cont(" NTC\n"); |
dcd79aeb | 388 | else |
c7689578 | 389 | pr_cont("\n"); |
dcd79aeb TI |
390 | |
391 | if (netif_msg_pktdata(adapter) && | |
392 | tx_buffer_info->dma != 0) | |
393 | print_hex_dump(KERN_INFO, "", | |
394 | DUMP_PREFIX_ADDRESS, 16, 1, | |
395 | phys_to_virt(tx_buffer_info->dma), | |
396 | tx_buffer_info->length, true); | |
397 | } | |
398 | } | |
399 | ||
400 | /* Print RX Rings Summary */ | |
401 | rx_ring_summary: | |
402 | dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); | |
c7689578 | 403 | pr_info("Queue [NTU] [NTC]\n"); |
dcd79aeb TI |
404 | for (n = 0; n < adapter->num_rx_queues; n++) { |
405 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
406 | pr_info("%5d %5X %5X\n", |
407 | n, rx_ring->next_to_use, rx_ring->next_to_clean); | |
dcd79aeb TI |
408 | } |
409 | ||
410 | /* Print RX Rings */ | |
411 | if (!netif_msg_rx_status(adapter)) | |
412 | goto exit; | |
413 | ||
414 | dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); | |
415 | ||
416 | /* Advanced Receive Descriptor (Read) Format | |
417 | * 63 1 0 | |
418 | * +-----------------------------------------------------+ | |
419 | * 0 | Packet Buffer Address [63:1] |A0/NSE| | |
420 | * +----------------------------------------------+------+ | |
421 | * 8 | Header Buffer Address [63:1] | DD | | |
422 | * +-----------------------------------------------------+ | |
423 | * | |
424 | * | |
425 | * Advanced Receive Descriptor (Write-Back) Format | |
426 | * | |
427 | * 63 48 47 32 31 30 21 20 16 15 4 3 0 | |
428 | * +------------------------------------------------------+ | |
429 | * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | | |
430 | * | Checksum Ident | | | | Type | Type | | |
431 | * +------------------------------------------------------+ | |
432 | * 8 | VLAN Tag | Length | Extended Error | Extended Status | | |
433 | * +------------------------------------------------------+ | |
434 | * 63 48 47 32 31 20 19 0 | |
435 | */ | |
436 | for (n = 0; n < adapter->num_rx_queues; n++) { | |
437 | rx_ring = adapter->rx_ring[n]; | |
c7689578 JP |
438 | pr_info("------------------------------------\n"); |
439 | pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); | |
440 | pr_info("------------------------------------\n"); | |
441 | pr_info("R [desc] [ PktBuf A0] " | |
dcd79aeb TI |
442 | "[ HeadBuf DD] [bi->dma ] [bi->skb] " |
443 | "<-- Adv Rx Read format\n"); | |
c7689578 | 444 | pr_info("RWB[desc] [PcsmIpSHl PtRs] " |
dcd79aeb TI |
445 | "[vl er S cks ln] ---------------- [bi->skb] " |
446 | "<-- Adv Rx Write-Back format\n"); | |
447 | ||
448 | for (i = 0; i < rx_ring->count; i++) { | |
449 | rx_buffer_info = &rx_ring->rx_buffer_info[i]; | |
e4f74028 | 450 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
dcd79aeb TI |
451 | u0 = (struct my_u0 *)rx_desc; |
452 | staterr = le32_to_cpu(rx_desc->wb.upper.status_error); | |
453 | if (staterr & IXGBE_RXD_STAT_DD) { | |
454 | /* Descriptor Done */ | |
c7689578 | 455 | pr_info("RWB[0x%03X] %016llX " |
dcd79aeb TI |
456 | "%016llX ---------------- %p", i, |
457 | le64_to_cpu(u0->a), | |
458 | le64_to_cpu(u0->b), | |
459 | rx_buffer_info->skb); | |
460 | } else { | |
c7689578 | 461 | pr_info("R [0x%03X] %016llX " |
dcd79aeb TI |
462 | "%016llX %016llX %p", i, |
463 | le64_to_cpu(u0->a), | |
464 | le64_to_cpu(u0->b), | |
465 | (u64)rx_buffer_info->dma, | |
466 | rx_buffer_info->skb); | |
467 | ||
468 | if (netif_msg_pktdata(adapter)) { | |
469 | print_hex_dump(KERN_INFO, "", | |
470 | DUMP_PREFIX_ADDRESS, 16, 1, | |
471 | phys_to_virt(rx_buffer_info->dma), | |
f800326d | 472 | ixgbe_rx_bufsz(rx_ring), true); |
dcd79aeb TI |
473 | } |
474 | } | |
475 | ||
476 | if (i == rx_ring->next_to_use) | |
c7689578 | 477 | pr_cont(" NTU\n"); |
dcd79aeb | 478 | else if (i == rx_ring->next_to_clean) |
c7689578 | 479 | pr_cont(" NTC\n"); |
dcd79aeb | 480 | else |
c7689578 | 481 | pr_cont("\n"); |
dcd79aeb TI |
482 | |
483 | } | |
484 | } | |
485 | ||
486 | exit: | |
487 | return; | |
488 | } | |
489 | ||
5eba3699 AV |
490 | static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter) |
491 | { | |
492 | u32 ctrl_ext; | |
493 | ||
494 | /* Let firmware take over control of h/w */ | |
495 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
496 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 497 | ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 AV |
498 | } |
499 | ||
500 | static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter) | |
501 | { | |
502 | u32 ctrl_ext; | |
503 | ||
504 | /* Let firmware know the driver has taken over */ | |
505 | ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT); | |
506 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT, | |
e8e9f696 | 507 | ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD); |
5eba3699 | 508 | } |
9a799d71 | 509 | |
e8e26350 PW |
510 | /* |
511 | * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors | |
512 | * @adapter: pointer to adapter struct | |
513 | * @direction: 0 for Rx, 1 for Tx, -1 for other causes | |
514 | * @queue: queue to map the corresponding interrupt to | |
515 | * @msix_vector: the vector to map to the corresponding queue | |
516 | * | |
517 | */ | |
518 | static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction, | |
e8e9f696 | 519 | u8 queue, u8 msix_vector) |
9a799d71 AK |
520 | { |
521 | u32 ivar, index; | |
e8e26350 PW |
522 | struct ixgbe_hw *hw = &adapter->hw; |
523 | switch (hw->mac.type) { | |
524 | case ixgbe_mac_82598EB: | |
525 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
526 | if (direction == -1) | |
527 | direction = 0; | |
528 | index = (((direction * 64) + queue) >> 2) & 0x1F; | |
529 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index)); | |
530 | ivar &= ~(0xFF << (8 * (queue & 0x3))); | |
531 | ivar |= (msix_vector << (8 * (queue & 0x3))); | |
532 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar); | |
533 | break; | |
534 | case ixgbe_mac_82599EB: | |
b93a2226 | 535 | case ixgbe_mac_X540: |
e8e26350 PW |
536 | if (direction == -1) { |
537 | /* other causes */ | |
538 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
539 | index = ((queue & 1) * 8); | |
540 | ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC); | |
541 | ivar &= ~(0xFF << index); | |
542 | ivar |= (msix_vector << index); | |
543 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar); | |
544 | break; | |
545 | } else { | |
546 | /* tx or rx causes */ | |
547 | msix_vector |= IXGBE_IVAR_ALLOC_VAL; | |
548 | index = ((16 * (queue & 1)) + (8 * direction)); | |
549 | ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1)); | |
550 | ivar &= ~(0xFF << index); | |
551 | ivar |= (msix_vector << index); | |
552 | IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar); | |
553 | break; | |
554 | } | |
555 | default: | |
556 | break; | |
557 | } | |
9a799d71 AK |
558 | } |
559 | ||
fe49f04a | 560 | static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter, |
e8e9f696 | 561 | u64 qmask) |
fe49f04a AD |
562 | { |
563 | u32 mask; | |
564 | ||
bd508178 AD |
565 | switch (adapter->hw.mac.type) { |
566 | case ixgbe_mac_82598EB: | |
fe49f04a AD |
567 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
568 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask); | |
bd508178 AD |
569 | break; |
570 | case ixgbe_mac_82599EB: | |
b93a2226 | 571 | case ixgbe_mac_X540: |
fe49f04a AD |
572 | mask = (qmask & 0xFFFFFFFF); |
573 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask); | |
574 | mask = (qmask >> 32); | |
575 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask); | |
bd508178 AD |
576 | break; |
577 | default: | |
578 | break; | |
fe49f04a AD |
579 | } |
580 | } | |
581 | ||
d3d00239 AD |
582 | static inline void ixgbe_unmap_tx_resource(struct ixgbe_ring *ring, |
583 | struct ixgbe_tx_buffer *tx_buffer) | |
9a799d71 | 584 | { |
d3d00239 AD |
585 | if (tx_buffer->dma) { |
586 | if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_MAPPED_AS_PAGE) | |
587 | dma_unmap_page(ring->dev, | |
588 | tx_buffer->dma, | |
589 | tx_buffer->length, | |
590 | DMA_TO_DEVICE); | |
e5a43549 | 591 | else |
d3d00239 AD |
592 | dma_unmap_single(ring->dev, |
593 | tx_buffer->dma, | |
594 | tx_buffer->length, | |
595 | DMA_TO_DEVICE); | |
e5a43549 | 596 | } |
d3d00239 AD |
597 | tx_buffer->dma = 0; |
598 | } | |
599 | ||
600 | void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring, | |
601 | struct ixgbe_tx_buffer *tx_buffer_info) | |
602 | { | |
603 | ixgbe_unmap_tx_resource(tx_ring, tx_buffer_info); | |
604 | if (tx_buffer_info->skb) | |
9a799d71 | 605 | dev_kfree_skb_any(tx_buffer_info->skb); |
d3d00239 | 606 | tx_buffer_info->skb = NULL; |
9a799d71 AK |
607 | /* tx_buffer_info must be completely set up in the transmit path */ |
608 | } | |
609 | ||
c84d324c JF |
610 | static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter) |
611 | { | |
612 | struct ixgbe_hw *hw = &adapter->hw; | |
613 | struct ixgbe_hw_stats *hwstats = &adapter->stats; | |
614 | u32 data = 0; | |
615 | u32 xoff[8] = {0}; | |
616 | int i; | |
617 | ||
618 | if ((hw->fc.current_mode == ixgbe_fc_full) || | |
619 | (hw->fc.current_mode == ixgbe_fc_rx_pause)) { | |
620 | switch (hw->mac.type) { | |
621 | case ixgbe_mac_82598EB: | |
622 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); | |
6837e895 PW |
623 | break; |
624 | default: | |
c84d324c JF |
625 | data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); |
626 | } | |
627 | hwstats->lxoffrxc += data; | |
628 | ||
629 | /* refill credits (no tx hang) if we received xoff */ | |
630 | if (!data) | |
631 | return; | |
632 | ||
633 | for (i = 0; i < adapter->num_tx_queues; i++) | |
634 | clear_bit(__IXGBE_HANG_CHECK_ARMED, | |
635 | &adapter->tx_ring[i]->state); | |
636 | return; | |
637 | } else if (!(adapter->dcb_cfg.pfc_mode_enable)) | |
638 | return; | |
639 | ||
640 | /* update stats for each tc, only valid with PFC enabled */ | |
641 | for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) { | |
642 | switch (hw->mac.type) { | |
643 | case ixgbe_mac_82598EB: | |
644 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); | |
bd508178 | 645 | break; |
c84d324c JF |
646 | default: |
647 | xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); | |
26f23d82 | 648 | } |
c84d324c JF |
649 | hwstats->pxoffrxc[i] += xoff[i]; |
650 | } | |
651 | ||
652 | /* disarm tx queues that have received xoff frames */ | |
653 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
654 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
fb5475ff | 655 | u8 tc = tx_ring->dcb_tc; |
c84d324c JF |
656 | |
657 | if (xoff[tc]) | |
658 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
26f23d82 | 659 | } |
26f23d82 YZ |
660 | } |
661 | ||
c84d324c | 662 | static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring) |
9a799d71 | 663 | { |
7d7ce682 | 664 | return ring->stats.packets; |
c84d324c JF |
665 | } |
666 | ||
667 | static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring) | |
668 | { | |
669 | struct ixgbe_adapter *adapter = netdev_priv(ring->netdev); | |
e01c31a5 | 670 | struct ixgbe_hw *hw = &adapter->hw; |
e01c31a5 | 671 | |
c84d324c JF |
672 | u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx)); |
673 | u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx)); | |
674 | ||
675 | if (head != tail) | |
676 | return (head < tail) ? | |
677 | tail - head : (tail + ring->count - head); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
682 | static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring) | |
683 | { | |
684 | u32 tx_done = ixgbe_get_tx_completed(tx_ring); | |
685 | u32 tx_done_old = tx_ring->tx_stats.tx_done_old; | |
686 | u32 tx_pending = ixgbe_get_tx_pending(tx_ring); | |
687 | bool ret = false; | |
688 | ||
7d637bcc | 689 | clear_check_for_tx_hang(tx_ring); |
c84d324c JF |
690 | |
691 | /* | |
692 | * Check for a hung queue, but be thorough. This verifies | |
693 | * that a transmit has been completed since the previous | |
694 | * check AND there is at least one packet pending. The | |
695 | * ARMED bit is set to indicate a potential hang. The | |
696 | * bit is cleared if a pause frame is received to remove | |
697 | * false hang detection due to PFC or 802.3x frames. By | |
698 | * requiring this to fail twice we avoid races with | |
699 | * pfc clearing the ARMED bit and conditions where we | |
700 | * run the check_tx_hang logic with a transmit completion | |
701 | * pending but without time to complete it yet. | |
702 | */ | |
703 | if ((tx_done_old == tx_done) && tx_pending) { | |
704 | /* make sure it is true for two checks in a row */ | |
705 | ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED, | |
706 | &tx_ring->state); | |
707 | } else { | |
708 | /* update completed stats and continue */ | |
709 | tx_ring->tx_stats.tx_done_old = tx_done; | |
710 | /* reset the countdown */ | |
711 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state); | |
9a799d71 AK |
712 | } |
713 | ||
c84d324c | 714 | return ret; |
9a799d71 AK |
715 | } |
716 | ||
c83c6cbd AD |
717 | /** |
718 | * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout | |
719 | * @adapter: driver private struct | |
720 | **/ | |
721 | static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter) | |
722 | { | |
723 | ||
724 | /* Do the reset outside of interrupt context */ | |
725 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
726 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; | |
727 | ixgbe_service_event_schedule(adapter); | |
728 | } | |
729 | } | |
e01c31a5 | 730 | |
9a799d71 AK |
731 | /** |
732 | * ixgbe_clean_tx_irq - Reclaim resources after transmit completes | |
fe49f04a | 733 | * @q_vector: structure containing interrupt and ring information |
e01c31a5 | 734 | * @tx_ring: tx ring to clean |
9a799d71 | 735 | **/ |
fe49f04a | 736 | static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 737 | struct ixgbe_ring *tx_ring) |
9a799d71 | 738 | { |
fe49f04a | 739 | struct ixgbe_adapter *adapter = q_vector->adapter; |
d3d00239 AD |
740 | struct ixgbe_tx_buffer *tx_buffer; |
741 | union ixgbe_adv_tx_desc *tx_desc; | |
e01c31a5 | 742 | unsigned int total_bytes = 0, total_packets = 0; |
59224555 | 743 | unsigned int budget = q_vector->tx.work_limit; |
d3d00239 | 744 | u16 i = tx_ring->next_to_clean; |
9a799d71 | 745 | |
d3d00239 | 746 | tx_buffer = &tx_ring->tx_buffer_info[i]; |
e4f74028 | 747 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
12207e49 | 748 | |
30065e63 | 749 | for (; budget; budget--) { |
d3d00239 AD |
750 | union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; |
751 | ||
752 | /* if next_to_watch is not set then there is no work pending */ | |
753 | if (!eop_desc) | |
754 | break; | |
755 | ||
7f83a9e6 AD |
756 | /* prevent any other reads prior to eop_desc */ |
757 | rmb(); | |
758 | ||
d3d00239 AD |
759 | /* if DD is not set pending work has not been completed */ |
760 | if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD))) | |
761 | break; | |
8ad494b0 | 762 | |
d3d00239 AD |
763 | /* clear next_to_watch to prevent false hangs */ |
764 | tx_buffer->next_to_watch = NULL; | |
8ad494b0 | 765 | |
fd0db0ed AD |
766 | /* free the skb */ |
767 | dev_kfree_skb_any(tx_buffer->skb); | |
768 | ||
769 | /* clear tx_buffer data */ | |
770 | tx_buffer->skb = NULL; | |
771 | ||
d3d00239 AD |
772 | do { |
773 | ixgbe_unmap_tx_resource(tx_ring, tx_buffer); | |
d3d00239 AD |
774 | if (likely(tx_desc == eop_desc)) { |
775 | eop_desc = NULL; | |
d3d00239 AD |
776 | |
777 | total_bytes += tx_buffer->bytecount; | |
778 | total_packets += tx_buffer->gso_segs; | |
779 | } | |
9a799d71 | 780 | |
d3d00239 AD |
781 | tx_buffer++; |
782 | tx_desc++; | |
8ad494b0 | 783 | i++; |
d3d00239 | 784 | if (unlikely(i == tx_ring->count)) { |
8ad494b0 | 785 | i = 0; |
e01c31a5 | 786 | |
d3d00239 | 787 | tx_buffer = tx_ring->tx_buffer_info; |
e4f74028 | 788 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
e092be60 | 789 | } |
e01c31a5 | 790 | |
d3d00239 | 791 | } while (eop_desc); |
12207e49 PWJ |
792 | } |
793 | ||
9a799d71 | 794 | tx_ring->next_to_clean = i; |
d3d00239 | 795 | u64_stats_update_begin(&tx_ring->syncp); |
b953799e | 796 | tx_ring->stats.bytes += total_bytes; |
bd198058 | 797 | tx_ring->stats.packets += total_packets; |
d3d00239 | 798 | u64_stats_update_end(&tx_ring->syncp); |
bd198058 AD |
799 | q_vector->tx.total_bytes += total_bytes; |
800 | q_vector->tx.total_packets += total_packets; | |
b953799e | 801 | |
c84d324c JF |
802 | if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) { |
803 | /* schedule immediate reset if we believe we hung */ | |
804 | struct ixgbe_hw *hw = &adapter->hw; | |
e4f74028 | 805 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
c84d324c JF |
806 | e_err(drv, "Detected Tx Unit Hang\n" |
807 | " Tx Queue <%d>\n" | |
808 | " TDH, TDT <%x>, <%x>\n" | |
809 | " next_to_use <%x>\n" | |
810 | " next_to_clean <%x>\n" | |
811 | "tx_buffer_info[next_to_clean]\n" | |
812 | " time_stamp <%lx>\n" | |
813 | " jiffies <%lx>\n", | |
814 | tx_ring->queue_index, | |
815 | IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), | |
816 | IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), | |
d3d00239 AD |
817 | tx_ring->next_to_use, i, |
818 | tx_ring->tx_buffer_info[i].time_stamp, jiffies); | |
c84d324c JF |
819 | |
820 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); | |
821 | ||
822 | e_info(probe, | |
823 | "tx hang %d detected on queue %d, resetting adapter\n", | |
824 | adapter->tx_timeout_count + 1, tx_ring->queue_index); | |
825 | ||
b953799e | 826 | /* schedule immediate reset if we believe we hung */ |
c83c6cbd | 827 | ixgbe_tx_timeout_reset(adapter); |
b953799e AD |
828 | |
829 | /* the adapter is about to reset, no point in enabling stuff */ | |
59224555 | 830 | return true; |
b953799e | 831 | } |
9a799d71 | 832 | |
b2d96e0a AD |
833 | netdev_tx_completed_queue(txring_txq(tx_ring), |
834 | total_packets, total_bytes); | |
835 | ||
e092be60 | 836 | #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) |
30065e63 | 837 | if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && |
7d4987de | 838 | (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { |
e092be60 AV |
839 | /* Make sure that anybody stopping the queue after this |
840 | * sees the new next_to_clean. | |
841 | */ | |
842 | smp_mb(); | |
fc77dc3c | 843 | if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) && |
30eba97a | 844 | !test_bit(__IXGBE_DOWN, &adapter->state)) { |
fc77dc3c | 845 | netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 846 | ++tx_ring->tx_stats.restart_queue; |
30eba97a | 847 | } |
e092be60 | 848 | } |
9a799d71 | 849 | |
59224555 | 850 | return !!budget; |
9a799d71 AK |
851 | } |
852 | ||
5dd2d332 | 853 | #ifdef CONFIG_IXGBE_DCA |
bdda1a61 AD |
854 | static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter, |
855 | struct ixgbe_ring *tx_ring, | |
33cf09c9 | 856 | int cpu) |
bd0362dd | 857 | { |
33cf09c9 | 858 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
859 | u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); |
860 | u16 reg_offset; | |
33cf09c9 | 861 | |
33cf09c9 AD |
862 | switch (hw->mac.type) { |
863 | case ixgbe_mac_82598EB: | |
bdda1a61 | 864 | reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); |
33cf09c9 AD |
865 | break; |
866 | case ixgbe_mac_82599EB: | |
b93a2226 | 867 | case ixgbe_mac_X540: |
bdda1a61 AD |
868 | reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); |
869 | txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599; | |
33cf09c9 AD |
870 | break; |
871 | default: | |
bdda1a61 AD |
872 | /* for unknown hardware do not write register */ |
873 | return; | |
bd0362dd | 874 | } |
bdda1a61 AD |
875 | |
876 | /* | |
877 | * We can enable relaxed ordering for reads, but not writes when | |
878 | * DCA is enabled. This is due to a known issue in some chipsets | |
879 | * which will cause the DCA tag to be cleared. | |
880 | */ | |
881 | txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN | | |
882 | IXGBE_DCA_TXCTRL_DATA_RRO_EN | | |
883 | IXGBE_DCA_TXCTRL_DESC_DCA_EN; | |
884 | ||
885 | IXGBE_WRITE_REG(hw, reg_offset, txctrl); | |
bd0362dd JC |
886 | } |
887 | ||
bdda1a61 AD |
888 | static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter, |
889 | struct ixgbe_ring *rx_ring, | |
33cf09c9 | 890 | int cpu) |
bd0362dd | 891 | { |
33cf09c9 | 892 | struct ixgbe_hw *hw = &adapter->hw; |
bdda1a61 AD |
893 | u32 rxctrl = dca3_get_tag(rx_ring->dev, cpu); |
894 | u8 reg_idx = rx_ring->reg_idx; | |
895 | ||
33cf09c9 AD |
896 | |
897 | switch (hw->mac.type) { | |
33cf09c9 | 898 | case ixgbe_mac_82599EB: |
b93a2226 | 899 | case ixgbe_mac_X540: |
bdda1a61 | 900 | rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599; |
33cf09c9 AD |
901 | break; |
902 | default: | |
903 | break; | |
904 | } | |
bdda1a61 AD |
905 | |
906 | /* | |
907 | * We can enable relaxed ordering for reads, but not writes when | |
908 | * DCA is enabled. This is due to a known issue in some chipsets | |
909 | * which will cause the DCA tag to be cleared. | |
910 | */ | |
911 | rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN | | |
912 | IXGBE_DCA_RXCTRL_DATA_DCA_EN | | |
913 | IXGBE_DCA_RXCTRL_DESC_DCA_EN; | |
914 | ||
915 | IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); | |
33cf09c9 AD |
916 | } |
917 | ||
918 | static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector) | |
919 | { | |
920 | struct ixgbe_adapter *adapter = q_vector->adapter; | |
efe3d3c8 | 921 | struct ixgbe_ring *ring; |
bd0362dd | 922 | int cpu = get_cpu(); |
bd0362dd | 923 | |
33cf09c9 AD |
924 | if (q_vector->cpu == cpu) |
925 | goto out_no_update; | |
926 | ||
a557928e | 927 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 | 928 | ixgbe_update_tx_dca(adapter, ring, cpu); |
33cf09c9 | 929 | |
a557928e | 930 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 | 931 | ixgbe_update_rx_dca(adapter, ring, cpu); |
33cf09c9 AD |
932 | |
933 | q_vector->cpu = cpu; | |
934 | out_no_update: | |
bd0362dd JC |
935 | put_cpu(); |
936 | } | |
937 | ||
938 | static void ixgbe_setup_dca(struct ixgbe_adapter *adapter) | |
939 | { | |
33cf09c9 | 940 | int num_q_vectors; |
bd0362dd JC |
941 | int i; |
942 | ||
943 | if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED)) | |
944 | return; | |
945 | ||
e35ec126 AD |
946 | /* always use CB2 mode, difference is masked in the CB driver */ |
947 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2); | |
948 | ||
33cf09c9 AD |
949 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
950 | num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
951 | else | |
952 | num_q_vectors = 1; | |
953 | ||
954 | for (i = 0; i < num_q_vectors; i++) { | |
955 | adapter->q_vector[i]->cpu = -1; | |
956 | ixgbe_update_dca(adapter->q_vector[i]); | |
bd0362dd JC |
957 | } |
958 | } | |
959 | ||
960 | static int __ixgbe_notify_dca(struct device *dev, void *data) | |
961 | { | |
c60fbb00 | 962 | struct ixgbe_adapter *adapter = dev_get_drvdata(dev); |
bd0362dd JC |
963 | unsigned long event = *(unsigned long *)data; |
964 | ||
2a72c31e | 965 | if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE)) |
33cf09c9 AD |
966 | return 0; |
967 | ||
bd0362dd JC |
968 | switch (event) { |
969 | case DCA_PROVIDER_ADD: | |
96b0e0f6 JB |
970 | /* if we're already enabled, don't do it again */ |
971 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) | |
972 | break; | |
652f093f | 973 | if (dca_add_requester(dev) == 0) { |
96b0e0f6 | 974 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
975 | ixgbe_setup_dca(adapter); |
976 | break; | |
977 | } | |
978 | /* Fall Through since DCA is disabled. */ | |
979 | case DCA_PROVIDER_REMOVE: | |
980 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { | |
981 | dca_remove_requester(dev); | |
982 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
983 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
984 | } | |
985 | break; | |
986 | } | |
987 | ||
652f093f | 988 | return 0; |
bd0362dd | 989 | } |
67a74ee2 | 990 | |
bdda1a61 | 991 | #endif /* CONFIG_IXGBE_DCA */ |
8a0da21b AD |
992 | static inline void ixgbe_rx_hash(struct ixgbe_ring *ring, |
993 | union ixgbe_adv_rx_desc *rx_desc, | |
67a74ee2 ET |
994 | struct sk_buff *skb) |
995 | { | |
8a0da21b AD |
996 | if (ring->netdev->features & NETIF_F_RXHASH) |
997 | skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); | |
67a74ee2 ET |
998 | } |
999 | ||
f800326d | 1000 | #ifdef IXGBE_FCOE |
ff886dfc AD |
1001 | /** |
1002 | * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type | |
1003 | * @adapter: address of board private structure | |
1004 | * @rx_desc: advanced rx descriptor | |
1005 | * | |
1006 | * Returns : true if it is FCoE pkt | |
1007 | */ | |
1008 | static inline bool ixgbe_rx_is_fcoe(struct ixgbe_adapter *adapter, | |
1009 | union ixgbe_adv_rx_desc *rx_desc) | |
1010 | { | |
1011 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; | |
1012 | ||
1013 | return (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
1014 | ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) == | |
1015 | (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE << | |
1016 | IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT))); | |
1017 | } | |
1018 | ||
f800326d | 1019 | #endif /* IXGBE_FCOE */ |
e59bd25d AV |
1020 | /** |
1021 | * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum | |
8a0da21b AD |
1022 | * @ring: structure containing ring specific data |
1023 | * @rx_desc: current Rx descriptor being processed | |
e59bd25d AV |
1024 | * @skb: skb currently being received and modified |
1025 | **/ | |
8a0da21b | 1026 | static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring, |
8bae1b2b | 1027 | union ixgbe_adv_rx_desc *rx_desc, |
f56e0cb1 | 1028 | struct sk_buff *skb) |
9a799d71 | 1029 | { |
8a0da21b | 1030 | skb_checksum_none_assert(skb); |
9a799d71 | 1031 | |
712744be | 1032 | /* Rx csum disabled */ |
8a0da21b | 1033 | if (!(ring->netdev->features & NETIF_F_RXCSUM)) |
9a799d71 | 1034 | return; |
e59bd25d AV |
1035 | |
1036 | /* if IP and error */ | |
f56e0cb1 AD |
1037 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) && |
1038 | ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) { | |
8a0da21b | 1039 | ring->rx_stats.csum_err++; |
9a799d71 AK |
1040 | return; |
1041 | } | |
e59bd25d | 1042 | |
f56e0cb1 | 1043 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS)) |
e59bd25d AV |
1044 | return; |
1045 | ||
f56e0cb1 | 1046 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) { |
f800326d | 1047 | __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info; |
8bae1b2b DS |
1048 | |
1049 | /* | |
1050 | * 82599 errata, UDP frames with a 0 checksum can be marked as | |
1051 | * checksum errors. | |
1052 | */ | |
8a0da21b AD |
1053 | if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) && |
1054 | test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state)) | |
8bae1b2b DS |
1055 | return; |
1056 | ||
8a0da21b | 1057 | ring->rx_stats.csum_err++; |
e59bd25d AV |
1058 | return; |
1059 | } | |
1060 | ||
9a799d71 | 1061 | /* It must be a TCP or UDP packet with a valid checksum */ |
e59bd25d | 1062 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
9a799d71 AK |
1063 | } |
1064 | ||
84ea2591 | 1065 | static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val) |
e8e26350 | 1066 | { |
f56e0cb1 | 1067 | rx_ring->next_to_use = val; |
f800326d AD |
1068 | |
1069 | /* update next to alloc since we have filled the ring */ | |
1070 | rx_ring->next_to_alloc = val; | |
e8e26350 PW |
1071 | /* |
1072 | * Force memory writes to complete before letting h/w | |
1073 | * know there are new descriptors to fetch. (Only | |
1074 | * applicable for weak-ordered memory model archs, | |
1075 | * such as IA-64). | |
1076 | */ | |
1077 | wmb(); | |
84ea2591 | 1078 | writel(val, rx_ring->tail); |
e8e26350 PW |
1079 | } |
1080 | ||
f990b79b AD |
1081 | static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring, |
1082 | struct ixgbe_rx_buffer *bi) | |
1083 | { | |
1084 | struct page *page = bi->page; | |
f800326d | 1085 | dma_addr_t dma = bi->dma; |
f990b79b | 1086 | |
f800326d AD |
1087 | /* since we are recycling buffers we should seldom need to alloc */ |
1088 | if (likely(dma)) | |
f990b79b AD |
1089 | return true; |
1090 | ||
f800326d AD |
1091 | /* alloc new page for storage */ |
1092 | if (likely(!page)) { | |
1093 | page = alloc_pages(GFP_ATOMIC | __GFP_COLD, | |
1094 | ixgbe_rx_pg_order(rx_ring)); | |
f990b79b AD |
1095 | if (unlikely(!page)) { |
1096 | rx_ring->rx_stats.alloc_rx_page_failed++; | |
1097 | return false; | |
1098 | } | |
f800326d | 1099 | bi->page = page; |
f990b79b AD |
1100 | } |
1101 | ||
f800326d AD |
1102 | /* map page for use */ |
1103 | dma = dma_map_page(rx_ring->dev, page, 0, | |
1104 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1105 | ||
1106 | /* | |
1107 | * if mapping failed free memory back to system since | |
1108 | * there isn't much point in holding memory we can't use | |
1109 | */ | |
1110 | if (dma_mapping_error(rx_ring->dev, dma)) { | |
1111 | put_page(page); | |
1112 | bi->page = NULL; | |
f990b79b | 1113 | |
f990b79b AD |
1114 | rx_ring->rx_stats.alloc_rx_page_failed++; |
1115 | return false; | |
1116 | } | |
1117 | ||
f800326d AD |
1118 | bi->dma = dma; |
1119 | bi->page_offset ^= ixgbe_rx_bufsz(rx_ring); | |
1120 | ||
f990b79b AD |
1121 | return true; |
1122 | } | |
1123 | ||
9a799d71 | 1124 | /** |
f990b79b | 1125 | * ixgbe_alloc_rx_buffers - Replace used receive buffers |
fc77dc3c AD |
1126 | * @rx_ring: ring to place buffers on |
1127 | * @cleaned_count: number of buffers to replace | |
9a799d71 | 1128 | **/ |
fc77dc3c | 1129 | void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count) |
9a799d71 | 1130 | { |
9a799d71 | 1131 | union ixgbe_adv_rx_desc *rx_desc; |
3a581073 | 1132 | struct ixgbe_rx_buffer *bi; |
d5f398ed | 1133 | u16 i = rx_ring->next_to_use; |
9a799d71 | 1134 | |
f800326d AD |
1135 | /* nothing to do */ |
1136 | if (!cleaned_count) | |
fc77dc3c AD |
1137 | return; |
1138 | ||
e4f74028 | 1139 | rx_desc = IXGBE_RX_DESC(rx_ring, i); |
f990b79b AD |
1140 | bi = &rx_ring->rx_buffer_info[i]; |
1141 | i -= rx_ring->count; | |
9a799d71 | 1142 | |
f800326d AD |
1143 | do { |
1144 | if (!ixgbe_alloc_mapped_page(rx_ring, bi)) | |
f990b79b | 1145 | break; |
d5f398ed | 1146 | |
f800326d AD |
1147 | /* |
1148 | * Refresh the desc even if buffer_addrs didn't change | |
1149 | * because each write-back erases this info. | |
1150 | */ | |
1151 | rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); | |
9a799d71 | 1152 | |
f990b79b AD |
1153 | rx_desc++; |
1154 | bi++; | |
9a799d71 | 1155 | i++; |
f990b79b | 1156 | if (unlikely(!i)) { |
e4f74028 | 1157 | rx_desc = IXGBE_RX_DESC(rx_ring, 0); |
f990b79b AD |
1158 | bi = rx_ring->rx_buffer_info; |
1159 | i -= rx_ring->count; | |
1160 | } | |
1161 | ||
1162 | /* clear the hdr_addr for the next_to_use descriptor */ | |
1163 | rx_desc->read.hdr_addr = 0; | |
f800326d AD |
1164 | |
1165 | cleaned_count--; | |
1166 | } while (cleaned_count); | |
7c6e0a43 | 1167 | |
f990b79b AD |
1168 | i += rx_ring->count; |
1169 | ||
f56e0cb1 | 1170 | if (rx_ring->next_to_use != i) |
84ea2591 | 1171 | ixgbe_release_rx_desc(rx_ring, i); |
9a799d71 AK |
1172 | } |
1173 | ||
1d2024f6 AD |
1174 | /** |
1175 | * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE | |
1176 | * @data: pointer to the start of the headers | |
1177 | * @max_len: total length of section to find headers in | |
1178 | * | |
1179 | * This function is meant to determine the length of headers that will | |
1180 | * be recognized by hardware for LRO, GRO, and RSC offloads. The main | |
1181 | * motivation of doing this is to only perform one pull for IPv4 TCP | |
1182 | * packets so that we can do basic things like calculating the gso_size | |
1183 | * based on the average data per packet. | |
1184 | **/ | |
1185 | static unsigned int ixgbe_get_headlen(unsigned char *data, | |
1186 | unsigned int max_len) | |
1187 | { | |
1188 | union { | |
1189 | unsigned char *network; | |
1190 | /* l2 headers */ | |
1191 | struct ethhdr *eth; | |
1192 | struct vlan_hdr *vlan; | |
1193 | /* l3 headers */ | |
1194 | struct iphdr *ipv4; | |
1195 | } hdr; | |
1196 | __be16 protocol; | |
1197 | u8 nexthdr = 0; /* default to not TCP */ | |
1198 | u8 hlen; | |
1199 | ||
1200 | /* this should never happen, but better safe than sorry */ | |
1201 | if (max_len < ETH_HLEN) | |
1202 | return max_len; | |
1203 | ||
1204 | /* initialize network frame pointer */ | |
1205 | hdr.network = data; | |
1206 | ||
1207 | /* set first protocol and move network header forward */ | |
1208 | protocol = hdr.eth->h_proto; | |
1209 | hdr.network += ETH_HLEN; | |
1210 | ||
1211 | /* handle any vlan tag if present */ | |
1212 | if (protocol == __constant_htons(ETH_P_8021Q)) { | |
1213 | if ((hdr.network - data) > (max_len - VLAN_HLEN)) | |
1214 | return max_len; | |
1215 | ||
1216 | protocol = hdr.vlan->h_vlan_encapsulated_proto; | |
1217 | hdr.network += VLAN_HLEN; | |
1218 | } | |
1219 | ||
1220 | /* handle L3 protocols */ | |
1221 | if (protocol == __constant_htons(ETH_P_IP)) { | |
1222 | if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) | |
1223 | return max_len; | |
1224 | ||
1225 | /* access ihl as a u8 to avoid unaligned access on ia64 */ | |
1226 | hlen = (hdr.network[0] & 0x0F) << 2; | |
1227 | ||
1228 | /* verify hlen meets minimum size requirements */ | |
1229 | if (hlen < sizeof(struct iphdr)) | |
1230 | return hdr.network - data; | |
1231 | ||
1232 | /* record next protocol */ | |
1233 | nexthdr = hdr.ipv4->protocol; | |
1234 | hdr.network += hlen; | |
f800326d | 1235 | #ifdef IXGBE_FCOE |
1d2024f6 AD |
1236 | } else if (protocol == __constant_htons(ETH_P_FCOE)) { |
1237 | if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN)) | |
1238 | return max_len; | |
1239 | hdr.network += FCOE_HEADER_LEN; | |
1240 | #endif | |
1241 | } else { | |
1242 | return hdr.network - data; | |
1243 | } | |
1244 | ||
1245 | /* finally sort out TCP */ | |
1246 | if (nexthdr == IPPROTO_TCP) { | |
1247 | if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) | |
1248 | return max_len; | |
1249 | ||
1250 | /* access doff as a u8 to avoid unaligned access on ia64 */ | |
1251 | hlen = (hdr.network[12] & 0xF0) >> 2; | |
1252 | ||
1253 | /* verify hlen meets minimum size requirements */ | |
1254 | if (hlen < sizeof(struct tcphdr)) | |
1255 | return hdr.network - data; | |
1256 | ||
1257 | hdr.network += hlen; | |
1258 | } | |
1259 | ||
1260 | /* | |
1261 | * If everything has gone correctly hdr.network should be the | |
1262 | * data section of the packet and will be the end of the header. | |
1263 | * If not then it probably represents the end of the last recognized | |
1264 | * header. | |
1265 | */ | |
1266 | if ((hdr.network - data) < max_len) | |
1267 | return hdr.network - data; | |
1268 | else | |
1269 | return max_len; | |
1270 | } | |
1271 | ||
4c1975d7 AD |
1272 | static void ixgbe_get_rsc_cnt(struct ixgbe_ring *rx_ring, |
1273 | union ixgbe_adv_rx_desc *rx_desc, | |
1274 | struct sk_buff *skb) | |
aa80175a | 1275 | { |
4c1975d7 AD |
1276 | __le32 rsc_enabled; |
1277 | u32 rsc_cnt; | |
1278 | ||
1279 | if (!ring_is_rsc_enabled(rx_ring)) | |
1280 | return; | |
1281 | ||
1282 | rsc_enabled = rx_desc->wb.lower.lo_dword.data & | |
1283 | cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK); | |
1284 | ||
1285 | /* If this is an RSC frame rsc_cnt should be non-zero */ | |
1286 | if (!rsc_enabled) | |
1287 | return; | |
1288 | ||
1289 | rsc_cnt = le32_to_cpu(rsc_enabled); | |
1290 | rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT; | |
1291 | ||
1292 | IXGBE_CB(skb)->append_cnt += rsc_cnt - 1; | |
aa80175a | 1293 | } |
43634e82 | 1294 | |
1d2024f6 AD |
1295 | static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring, |
1296 | struct sk_buff *skb) | |
1297 | { | |
f800326d | 1298 | u16 hdr_len = skb_headlen(skb); |
1d2024f6 AD |
1299 | |
1300 | /* set gso_size to avoid messing up TCP MSS */ | |
1301 | skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len), | |
1302 | IXGBE_CB(skb)->append_cnt); | |
1303 | } | |
1304 | ||
1305 | static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring, | |
1306 | struct sk_buff *skb) | |
1307 | { | |
1308 | /* if append_cnt is 0 then frame is not RSC */ | |
1309 | if (!IXGBE_CB(skb)->append_cnt) | |
1310 | return; | |
1311 | ||
1312 | rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt; | |
1313 | rx_ring->rx_stats.rsc_flush++; | |
1314 | ||
1315 | ixgbe_set_rsc_gso_size(rx_ring, skb); | |
1316 | ||
1317 | /* gso_size is computed using append_cnt so always clear it last */ | |
1318 | IXGBE_CB(skb)->append_cnt = 0; | |
1319 | } | |
1320 | ||
8a0da21b AD |
1321 | /** |
1322 | * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor | |
1323 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1324 | * @rx_desc: pointer to the EOP Rx descriptor | |
1325 | * @skb: pointer to current skb being populated | |
f8212f97 | 1326 | * |
8a0da21b AD |
1327 | * This function checks the ring, descriptor, and packet information in |
1328 | * order to populate the hash, checksum, VLAN, timestamp, protocol, and | |
1329 | * other fields within the skb. | |
f8212f97 | 1330 | **/ |
8a0da21b AD |
1331 | static void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring, |
1332 | union ixgbe_adv_rx_desc *rx_desc, | |
1333 | struct sk_buff *skb) | |
f8212f97 | 1334 | { |
8a0da21b AD |
1335 | ixgbe_update_rsc_stats(rx_ring, skb); |
1336 | ||
1337 | ixgbe_rx_hash(rx_ring, rx_desc, skb); | |
f8212f97 | 1338 | |
8a0da21b AD |
1339 | ixgbe_rx_checksum(rx_ring, rx_desc, skb); |
1340 | ||
1341 | if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) { | |
1342 | u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan); | |
1343 | __vlan_hwaccel_put_tag(skb, vid); | |
f8212f97 AD |
1344 | } |
1345 | ||
8a0da21b | 1346 | skb_record_rx_queue(skb, rx_ring->queue_index); |
aa80175a | 1347 | |
8a0da21b | 1348 | skb->protocol = eth_type_trans(skb, rx_ring->netdev); |
f8212f97 AD |
1349 | } |
1350 | ||
8a0da21b AD |
1351 | static void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector, |
1352 | struct sk_buff *skb) | |
aa80175a | 1353 | { |
8a0da21b AD |
1354 | struct ixgbe_adapter *adapter = q_vector->adapter; |
1355 | ||
1356 | if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) | |
1357 | napi_gro_receive(&q_vector->napi, skb); | |
1358 | else | |
1359 | netif_rx(skb); | |
aa80175a | 1360 | } |
43634e82 | 1361 | |
f800326d AD |
1362 | /** |
1363 | * ixgbe_is_non_eop - process handling of non-EOP buffers | |
1364 | * @rx_ring: Rx ring being processed | |
1365 | * @rx_desc: Rx descriptor for current buffer | |
1366 | * @skb: Current socket buffer containing buffer in progress | |
1367 | * | |
1368 | * This function updates next to clean. If the buffer is an EOP buffer | |
1369 | * this function exits returning false, otherwise it will place the | |
1370 | * sk_buff in the next buffer to be chained and return true indicating | |
1371 | * that this is in fact a non-EOP buffer. | |
1372 | **/ | |
1373 | static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring, | |
1374 | union ixgbe_adv_rx_desc *rx_desc, | |
1375 | struct sk_buff *skb) | |
1376 | { | |
1377 | u32 ntc = rx_ring->next_to_clean + 1; | |
1378 | ||
1379 | /* fetch, update, and store next to clean */ | |
1380 | ntc = (ntc < rx_ring->count) ? ntc : 0; | |
1381 | rx_ring->next_to_clean = ntc; | |
1382 | ||
1383 | prefetch(IXGBE_RX_DESC(rx_ring, ntc)); | |
1384 | ||
1385 | if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))) | |
1386 | return false; | |
1387 | ||
1388 | /* append_cnt indicates packet is RSC, if so fetch nextp */ | |
1389 | if (IXGBE_CB(skb)->append_cnt) { | |
1390 | ntc = le32_to_cpu(rx_desc->wb.upper.status_error); | |
1391 | ntc &= IXGBE_RXDADV_NEXTP_MASK; | |
1392 | ntc >>= IXGBE_RXDADV_NEXTP_SHIFT; | |
1393 | } | |
1394 | ||
1395 | /* place skb in next buffer to be received */ | |
1396 | rx_ring->rx_buffer_info[ntc].skb = skb; | |
1397 | rx_ring->rx_stats.non_eop_descs++; | |
1398 | ||
1399 | return true; | |
1400 | } | |
1401 | ||
1402 | /** | |
1403 | * ixgbe_cleanup_headers - Correct corrupted or empty headers | |
1404 | * @rx_ring: rx descriptor ring packet is being transacted on | |
1405 | * @rx_desc: pointer to the EOP Rx descriptor | |
1406 | * @skb: pointer to current skb being fixed | |
1407 | * | |
1408 | * Check for corrupted packet headers caused by senders on the local L2 | |
1409 | * embedded NIC switch not setting up their Tx Descriptors right. These | |
1410 | * should be very rare. | |
1411 | * | |
1412 | * Also address the case where we are pulling data in on pages only | |
1413 | * and as such no data is present in the skb header. | |
1414 | * | |
1415 | * In addition if skb is not at least 60 bytes we need to pad it so that | |
1416 | * it is large enough to qualify as a valid Ethernet frame. | |
1417 | * | |
1418 | * Returns true if an error was encountered and skb was freed. | |
1419 | **/ | |
1420 | static bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring, | |
1421 | union ixgbe_adv_rx_desc *rx_desc, | |
1422 | struct sk_buff *skb) | |
1423 | { | |
1424 | struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; | |
1425 | struct net_device *netdev = rx_ring->netdev; | |
1426 | unsigned char *va; | |
1427 | unsigned int pull_len; | |
1428 | ||
1429 | /* if the page was released unmap it, else just sync our portion */ | |
1430 | if (unlikely(IXGBE_CB(skb)->page_released)) { | |
1431 | dma_unmap_page(rx_ring->dev, IXGBE_CB(skb)->dma, | |
1432 | ixgbe_rx_pg_size(rx_ring), DMA_FROM_DEVICE); | |
1433 | IXGBE_CB(skb)->page_released = false; | |
1434 | } else { | |
1435 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1436 | IXGBE_CB(skb)->dma, | |
1437 | frag->page_offset, | |
1438 | ixgbe_rx_bufsz(rx_ring), | |
1439 | DMA_FROM_DEVICE); | |
1440 | } | |
1441 | IXGBE_CB(skb)->dma = 0; | |
1442 | ||
1443 | /* verify that the packet does not have any known errors */ | |
1444 | if (unlikely(ixgbe_test_staterr(rx_desc, | |
1445 | IXGBE_RXDADV_ERR_FRAME_ERR_MASK) && | |
1446 | !(netdev->features & NETIF_F_RXALL))) { | |
1447 | dev_kfree_skb_any(skb); | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | /* | |
1452 | * it is valid to use page_address instead of kmap since we are | |
1453 | * working with pages allocated out of the lomem pool per | |
1454 | * alloc_page(GFP_ATOMIC) | |
1455 | */ | |
1456 | va = skb_frag_address(frag); | |
1457 | ||
1458 | /* | |
1459 | * we need the header to contain the greater of either ETH_HLEN or | |
1460 | * 60 bytes if the skb->len is less than 60 for skb_pad. | |
1461 | */ | |
1462 | pull_len = skb_frag_size(frag); | |
1463 | if (pull_len > 256) | |
1464 | pull_len = ixgbe_get_headlen(va, pull_len); | |
1465 | ||
1466 | /* align pull length to size of long to optimize memcpy performance */ | |
1467 | skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); | |
1468 | ||
1469 | /* update all of the pointers */ | |
1470 | skb_frag_size_sub(frag, pull_len); | |
1471 | frag->page_offset += pull_len; | |
1472 | skb->data_len -= pull_len; | |
1473 | skb->tail += pull_len; | |
1474 | ||
1475 | /* | |
1476 | * if we sucked the frag empty then we should free it, | |
1477 | * if there are other frags here something is screwed up in hardware | |
1478 | */ | |
1479 | if (skb_frag_size(frag) == 0) { | |
1480 | BUG_ON(skb_shinfo(skb)->nr_frags != 1); | |
1481 | skb_shinfo(skb)->nr_frags = 0; | |
1482 | __skb_frag_unref(frag); | |
1483 | skb->truesize -= ixgbe_rx_bufsz(rx_ring); | |
1484 | } | |
1485 | ||
1486 | /* if skb_pad returns an error the skb was freed */ | |
1487 | if (unlikely(skb->len < 60)) { | |
1488 | int pad_len = 60 - skb->len; | |
1489 | ||
1490 | if (skb_pad(skb, pad_len)) | |
1491 | return true; | |
1492 | __skb_put(skb, pad_len); | |
1493 | } | |
1494 | ||
1495 | return false; | |
1496 | } | |
1497 | ||
1498 | /** | |
1499 | * ixgbe_can_reuse_page - determine if we can reuse a page | |
1500 | * @rx_buffer: pointer to rx_buffer containing the page we want to reuse | |
1501 | * | |
1502 | * Returns true if page can be reused in another Rx buffer | |
1503 | **/ | |
1504 | static inline bool ixgbe_can_reuse_page(struct ixgbe_rx_buffer *rx_buffer) | |
1505 | { | |
1506 | struct page *page = rx_buffer->page; | |
1507 | ||
1508 | /* if we are only owner of page and it is local we can reuse it */ | |
1509 | return likely(page_count(page) == 1) && | |
1510 | likely(page_to_nid(page) == numa_node_id()); | |
1511 | } | |
1512 | ||
1513 | /** | |
1514 | * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring | |
1515 | * @rx_ring: rx descriptor ring to store buffers on | |
1516 | * @old_buff: donor buffer to have page reused | |
1517 | * | |
1518 | * Syncronizes page for reuse by the adapter | |
1519 | **/ | |
1520 | static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring, | |
1521 | struct ixgbe_rx_buffer *old_buff) | |
1522 | { | |
1523 | struct ixgbe_rx_buffer *new_buff; | |
1524 | u16 nta = rx_ring->next_to_alloc; | |
1525 | u16 bufsz = ixgbe_rx_bufsz(rx_ring); | |
1526 | ||
1527 | new_buff = &rx_ring->rx_buffer_info[nta]; | |
1528 | ||
1529 | /* update, and store next to alloc */ | |
1530 | nta++; | |
1531 | rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; | |
1532 | ||
1533 | /* transfer page from old buffer to new buffer */ | |
1534 | new_buff->page = old_buff->page; | |
1535 | new_buff->dma = old_buff->dma; | |
1536 | ||
1537 | /* flip page offset to other buffer and store to new_buff */ | |
1538 | new_buff->page_offset = old_buff->page_offset ^ bufsz; | |
1539 | ||
1540 | /* sync the buffer for use by the device */ | |
1541 | dma_sync_single_range_for_device(rx_ring->dev, new_buff->dma, | |
1542 | new_buff->page_offset, bufsz, | |
1543 | DMA_FROM_DEVICE); | |
1544 | ||
1545 | /* bump ref count on page before it is given to the stack */ | |
1546 | get_page(new_buff->page); | |
1547 | } | |
1548 | ||
1549 | /** | |
1550 | * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff | |
1551 | * @rx_ring: rx descriptor ring to transact packets on | |
1552 | * @rx_buffer: buffer containing page to add | |
1553 | * @rx_desc: descriptor containing length of buffer written by hardware | |
1554 | * @skb: sk_buff to place the data into | |
1555 | * | |
1556 | * This function is based on skb_add_rx_frag. I would have used that | |
1557 | * function however it doesn't handle the truesize case correctly since we | |
1558 | * are allocating more memory than might be used for a single receive. | |
1559 | **/ | |
1560 | static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring, | |
1561 | struct ixgbe_rx_buffer *rx_buffer, | |
1562 | struct sk_buff *skb, int size) | |
1563 | { | |
1564 | skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, | |
1565 | rx_buffer->page, rx_buffer->page_offset, | |
1566 | size); | |
1567 | skb->len += size; | |
1568 | skb->data_len += size; | |
1569 | skb->truesize += ixgbe_rx_bufsz(rx_ring); | |
1570 | } | |
1571 | ||
1572 | /** | |
1573 | * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf | |
1574 | * @q_vector: structure containing interrupt and ring information | |
1575 | * @rx_ring: rx descriptor ring to transact packets on | |
1576 | * @budget: Total limit on number of packets to process | |
1577 | * | |
1578 | * This function provides a "bounce buffer" approach to Rx interrupt | |
1579 | * processing. The advantage to this is that on systems that have | |
1580 | * expensive overhead for IOMMU access this provides a means of avoiding | |
1581 | * it by maintaining the mapping of the page to the syste. | |
1582 | * | |
1583 | * Returns true if all work is completed without reaching budget | |
1584 | **/ | |
4ff7fb12 | 1585 | static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector, |
e8e9f696 | 1586 | struct ixgbe_ring *rx_ring, |
4ff7fb12 | 1587 | int budget) |
9a799d71 | 1588 | { |
d2f4fbe2 | 1589 | unsigned int total_rx_bytes = 0, total_rx_packets = 0; |
3f2d1c0f | 1590 | #ifdef IXGBE_FCOE |
f800326d | 1591 | struct ixgbe_adapter *adapter = q_vector->adapter; |
3d8fd385 YZ |
1592 | int ddp_bytes = 0; |
1593 | #endif /* IXGBE_FCOE */ | |
f800326d | 1594 | u16 cleaned_count = ixgbe_desc_unused(rx_ring); |
9a799d71 | 1595 | |
f800326d AD |
1596 | do { |
1597 | struct ixgbe_rx_buffer *rx_buffer; | |
1598 | union ixgbe_adv_rx_desc *rx_desc; | |
1599 | struct sk_buff *skb; | |
1600 | struct page *page; | |
1601 | u16 ntc; | |
1602 | ||
1603 | /* return some buffers to hardware, one at a time is too slow */ | |
1604 | if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) { | |
1605 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1606 | cleaned_count = 0; | |
1607 | } | |
1608 | ||
1609 | ntc = rx_ring->next_to_clean; | |
1610 | rx_desc = IXGBE_RX_DESC(rx_ring, ntc); | |
1611 | rx_buffer = &rx_ring->rx_buffer_info[ntc]; | |
1612 | ||
1613 | if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_DD)) | |
1614 | break; | |
9a799d71 | 1615 | |
f800326d AD |
1616 | /* |
1617 | * This memory barrier is needed to keep us from reading | |
1618 | * any other fields out of the rx_desc until we know the | |
1619 | * RXD_STAT_DD bit is set | |
1620 | */ | |
1621 | rmb(); | |
9a799d71 | 1622 | |
f800326d AD |
1623 | page = rx_buffer->page; |
1624 | prefetchw(page); | |
9a799d71 | 1625 | |
f800326d | 1626 | skb = rx_buffer->skb; |
c267fc16 | 1627 | |
f800326d AD |
1628 | if (likely(!skb)) { |
1629 | void *page_addr = page_address(page) + | |
1630 | rx_buffer->page_offset; | |
9a799d71 | 1631 | |
f800326d AD |
1632 | /* prefetch first cache line of first page */ |
1633 | prefetch(page_addr); | |
1634 | #if L1_CACHE_BYTES < 128 | |
1635 | prefetch(page_addr + L1_CACHE_BYTES); | |
1636 | #endif | |
1637 | ||
1638 | /* allocate a skb to store the frags */ | |
1639 | skb = netdev_alloc_skb_ip_align(rx_ring->netdev, | |
1640 | IXGBE_RX_HDR_SIZE); | |
1641 | if (unlikely(!skb)) { | |
1642 | rx_ring->rx_stats.alloc_rx_buff_failed++; | |
1643 | break; | |
c267fc16 AD |
1644 | } |
1645 | ||
f800326d AD |
1646 | /* |
1647 | * we will be copying header into skb->data in | |
1648 | * pskb_may_pull so it is in our interest to prefetch | |
1649 | * it now to avoid a possible cache miss | |
1650 | */ | |
1651 | prefetchw(skb->data); | |
4c1975d7 AD |
1652 | |
1653 | /* | |
1654 | * Delay unmapping of the first packet. It carries the | |
1655 | * header information, HW may still access the header | |
f800326d AD |
1656 | * after the writeback. Only unmap it when EOP is |
1657 | * reached | |
4c1975d7 | 1658 | */ |
f800326d | 1659 | IXGBE_CB(skb)->dma = rx_buffer->dma; |
c267fc16 | 1660 | } else { |
f800326d AD |
1661 | /* we are reusing so sync this buffer for CPU use */ |
1662 | dma_sync_single_range_for_cpu(rx_ring->dev, | |
1663 | rx_buffer->dma, | |
1664 | rx_buffer->page_offset, | |
1665 | ixgbe_rx_bufsz(rx_ring), | |
1666 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1667 | } |
1668 | ||
f800326d AD |
1669 | /* pull page into skb */ |
1670 | ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, | |
1671 | le16_to_cpu(rx_desc->wb.upper.length)); | |
9a799d71 | 1672 | |
f800326d AD |
1673 | if (ixgbe_can_reuse_page(rx_buffer)) { |
1674 | /* hand second half of page back to the ring */ | |
1675 | ixgbe_reuse_rx_page(rx_ring, rx_buffer); | |
1676 | } else if (IXGBE_CB(skb)->dma == rx_buffer->dma) { | |
1677 | /* the page has been released from the ring */ | |
1678 | IXGBE_CB(skb)->page_released = true; | |
1679 | } else { | |
1680 | /* we are not reusing the buffer so unmap it */ | |
1681 | dma_unmap_page(rx_ring->dev, rx_buffer->dma, | |
1682 | ixgbe_rx_pg_size(rx_ring), | |
1683 | DMA_FROM_DEVICE); | |
9a799d71 AK |
1684 | } |
1685 | ||
f800326d AD |
1686 | /* clear contents of buffer_info */ |
1687 | rx_buffer->skb = NULL; | |
1688 | rx_buffer->dma = 0; | |
1689 | rx_buffer->page = NULL; | |
4c1975d7 | 1690 | |
f800326d | 1691 | ixgbe_get_rsc_cnt(rx_ring, rx_desc, skb); |
9a799d71 | 1692 | |
9a799d71 | 1693 | cleaned_count++; |
f8212f97 | 1694 | |
f800326d AD |
1695 | /* place incomplete frames back on ring for completion */ |
1696 | if (ixgbe_is_non_eop(rx_ring, rx_desc, skb)) | |
1697 | continue; | |
c267fc16 | 1698 | |
f800326d AD |
1699 | /* verify the packet layout is correct */ |
1700 | if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb)) | |
1701 | continue; | |
9a799d71 | 1702 | |
d2f4fbe2 AV |
1703 | /* probably a little skewed due to removing CRC */ |
1704 | total_rx_bytes += skb->len; | |
1705 | total_rx_packets++; | |
1706 | ||
8a0da21b AD |
1707 | /* populate checksum, timestamp, VLAN, and protocol */ |
1708 | ixgbe_process_skb_fields(rx_ring, rx_desc, skb); | |
1709 | ||
332d4a7d YZ |
1710 | #ifdef IXGBE_FCOE |
1711 | /* if ddp, not passing to ULD unless for FCP_RSP or error */ | |
ff886dfc | 1712 | if (ixgbe_rx_is_fcoe(adapter, rx_desc)) { |
f56e0cb1 | 1713 | ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb); |
63d635b2 AD |
1714 | if (!ddp_bytes) { |
1715 | dev_kfree_skb_any(skb); | |
f800326d | 1716 | continue; |
63d635b2 | 1717 | } |
3d8fd385 | 1718 | } |
f800326d | 1719 | |
332d4a7d | 1720 | #endif /* IXGBE_FCOE */ |
8a0da21b | 1721 | ixgbe_rx_skb(q_vector, skb); |
9a799d71 | 1722 | |
f800326d | 1723 | /* update budget accounting */ |
4ff7fb12 | 1724 | budget--; |
f800326d | 1725 | } while (likely(budget)); |
9a799d71 | 1726 | |
3d8fd385 YZ |
1727 | #ifdef IXGBE_FCOE |
1728 | /* include DDPed FCoE data */ | |
1729 | if (ddp_bytes > 0) { | |
1730 | unsigned int mss; | |
1731 | ||
fc77dc3c | 1732 | mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) - |
3d8fd385 YZ |
1733 | sizeof(struct fc_frame_header) - |
1734 | sizeof(struct fcoe_crc_eof); | |
1735 | if (mss > 512) | |
1736 | mss &= ~511; | |
1737 | total_rx_bytes += ddp_bytes; | |
1738 | total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss); | |
1739 | } | |
3d8fd385 | 1740 | |
f800326d | 1741 | #endif /* IXGBE_FCOE */ |
c267fc16 AD |
1742 | u64_stats_update_begin(&rx_ring->syncp); |
1743 | rx_ring->stats.packets += total_rx_packets; | |
1744 | rx_ring->stats.bytes += total_rx_bytes; | |
1745 | u64_stats_update_end(&rx_ring->syncp); | |
bd198058 AD |
1746 | q_vector->rx.total_packets += total_rx_packets; |
1747 | q_vector->rx.total_bytes += total_rx_bytes; | |
4ff7fb12 | 1748 | |
f800326d AD |
1749 | if (cleaned_count) |
1750 | ixgbe_alloc_rx_buffers(rx_ring, cleaned_count); | |
1751 | ||
4ff7fb12 | 1752 | return !!budget; |
9a799d71 AK |
1753 | } |
1754 | ||
9a799d71 AK |
1755 | /** |
1756 | * ixgbe_configure_msix - Configure MSI-X hardware | |
1757 | * @adapter: board private structure | |
1758 | * | |
1759 | * ixgbe_configure_msix sets up the hardware to properly generate MSI-X | |
1760 | * interrupts. | |
1761 | **/ | |
1762 | static void ixgbe_configure_msix(struct ixgbe_adapter *adapter) | |
1763 | { | |
021230d4 | 1764 | struct ixgbe_q_vector *q_vector; |
efe3d3c8 | 1765 | int q_vectors, v_idx; |
021230d4 | 1766 | u32 mask; |
9a799d71 | 1767 | |
021230d4 | 1768 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
9a799d71 | 1769 | |
8e34d1aa AD |
1770 | /* Populate MSIX to EITR Select */ |
1771 | if (adapter->num_vfs > 32) { | |
1772 | u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1; | |
1773 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel); | |
1774 | } | |
1775 | ||
4df10466 JB |
1776 | /* |
1777 | * Populate the IVAR table and set the ITR values to the | |
021230d4 AV |
1778 | * corresponding register. |
1779 | */ | |
1780 | for (v_idx = 0; v_idx < q_vectors; v_idx++) { | |
efe3d3c8 | 1781 | struct ixgbe_ring *ring; |
7a921c93 | 1782 | q_vector = adapter->q_vector[v_idx]; |
021230d4 | 1783 | |
a557928e | 1784 | ixgbe_for_each_ring(ring, q_vector->rx) |
efe3d3c8 AD |
1785 | ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); |
1786 | ||
a557928e | 1787 | ixgbe_for_each_ring(ring, q_vector->tx) |
efe3d3c8 AD |
1788 | ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); |
1789 | ||
d5bf4f67 ET |
1790 | if (q_vector->tx.ring && !q_vector->rx.ring) { |
1791 | /* tx only vector */ | |
1792 | if (adapter->tx_itr_setting == 1) | |
1793 | q_vector->itr = IXGBE_10K_ITR; | |
1794 | else | |
1795 | q_vector->itr = adapter->tx_itr_setting; | |
1796 | } else { | |
1797 | /* rx or rx/tx vector */ | |
1798 | if (adapter->rx_itr_setting == 1) | |
1799 | q_vector->itr = IXGBE_20K_ITR; | |
1800 | else | |
1801 | q_vector->itr = adapter->rx_itr_setting; | |
1802 | } | |
021230d4 | 1803 | |
fe49f04a | 1804 | ixgbe_write_eitr(q_vector); |
9a799d71 AK |
1805 | } |
1806 | ||
bd508178 AD |
1807 | switch (adapter->hw.mac.type) { |
1808 | case ixgbe_mac_82598EB: | |
e8e26350 | 1809 | ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX, |
e8e9f696 | 1810 | v_idx); |
bd508178 AD |
1811 | break; |
1812 | case ixgbe_mac_82599EB: | |
b93a2226 | 1813 | case ixgbe_mac_X540: |
e8e26350 | 1814 | ixgbe_set_ivar(adapter, -1, 1, v_idx); |
bd508178 | 1815 | break; |
bd508178 AD |
1816 | default: |
1817 | break; | |
1818 | } | |
021230d4 AV |
1819 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950); |
1820 | ||
41fb9248 | 1821 | /* set up to autoclear timer, and the vectors */ |
021230d4 | 1822 | mask = IXGBE_EIMS_ENABLE_MASK; |
d5bf4f67 ET |
1823 | mask &= ~(IXGBE_EIMS_OTHER | |
1824 | IXGBE_EIMS_MAILBOX | | |
1825 | IXGBE_EIMS_LSC); | |
1826 | ||
021230d4 | 1827 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask); |
9a799d71 AK |
1828 | } |
1829 | ||
f494e8fa AV |
1830 | enum latency_range { |
1831 | lowest_latency = 0, | |
1832 | low_latency = 1, | |
1833 | bulk_latency = 2, | |
1834 | latency_invalid = 255 | |
1835 | }; | |
1836 | ||
1837 | /** | |
1838 | * ixgbe_update_itr - update the dynamic ITR value based on statistics | |
bd198058 AD |
1839 | * @q_vector: structure containing interrupt and ring information |
1840 | * @ring_container: structure containing ring performance data | |
f494e8fa AV |
1841 | * |
1842 | * Stores a new ITR value based on packets and byte | |
1843 | * counts during the last interrupt. The advantage of per interrupt | |
1844 | * computation is faster updates and more accurate ITR for the current | |
1845 | * traffic pattern. Constants in this function were computed | |
1846 | * based on theoretical maximum wire speed and thresholds were set based | |
1847 | * on testing data as well as attempting to minimize response time | |
1848 | * while increasing bulk throughput. | |
1849 | * this functionality is controlled by the InterruptThrottleRate module | |
1850 | * parameter (see ixgbe_param.c) | |
1851 | **/ | |
bd198058 AD |
1852 | static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector, |
1853 | struct ixgbe_ring_container *ring_container) | |
f494e8fa | 1854 | { |
bd198058 AD |
1855 | int bytes = ring_container->total_bytes; |
1856 | int packets = ring_container->total_packets; | |
1857 | u32 timepassed_us; | |
621bd70e | 1858 | u64 bytes_perint; |
bd198058 | 1859 | u8 itr_setting = ring_container->itr; |
f494e8fa AV |
1860 | |
1861 | if (packets == 0) | |
bd198058 | 1862 | return; |
f494e8fa AV |
1863 | |
1864 | /* simple throttlerate management | |
621bd70e AD |
1865 | * 0-10MB/s lowest (100000 ints/s) |
1866 | * 10-20MB/s low (20000 ints/s) | |
1867 | * 20-1249MB/s bulk (8000 ints/s) | |
f494e8fa AV |
1868 | */ |
1869 | /* what was last interrupt timeslice? */ | |
d5bf4f67 | 1870 | timepassed_us = q_vector->itr >> 2; |
f494e8fa AV |
1871 | bytes_perint = bytes / timepassed_us; /* bytes/usec */ |
1872 | ||
1873 | switch (itr_setting) { | |
1874 | case lowest_latency: | |
621bd70e | 1875 | if (bytes_perint > 10) |
bd198058 | 1876 | itr_setting = low_latency; |
f494e8fa AV |
1877 | break; |
1878 | case low_latency: | |
621bd70e | 1879 | if (bytes_perint > 20) |
bd198058 | 1880 | itr_setting = bulk_latency; |
621bd70e | 1881 | else if (bytes_perint <= 10) |
bd198058 | 1882 | itr_setting = lowest_latency; |
f494e8fa AV |
1883 | break; |
1884 | case bulk_latency: | |
621bd70e | 1885 | if (bytes_perint <= 20) |
bd198058 | 1886 | itr_setting = low_latency; |
f494e8fa AV |
1887 | break; |
1888 | } | |
1889 | ||
bd198058 AD |
1890 | /* clear work counters since we have the values we need */ |
1891 | ring_container->total_bytes = 0; | |
1892 | ring_container->total_packets = 0; | |
1893 | ||
1894 | /* write updated itr to ring container */ | |
1895 | ring_container->itr = itr_setting; | |
f494e8fa AV |
1896 | } |
1897 | ||
509ee935 JB |
1898 | /** |
1899 | * ixgbe_write_eitr - write EITR register in hardware specific way | |
fe49f04a | 1900 | * @q_vector: structure containing interrupt and ring information |
509ee935 JB |
1901 | * |
1902 | * This function is made to be called by ethtool and by the driver | |
1903 | * when it needs to update EITR registers at runtime. Hardware | |
1904 | * specific quirks/differences are taken care of here. | |
1905 | */ | |
fe49f04a | 1906 | void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector) |
509ee935 | 1907 | { |
fe49f04a | 1908 | struct ixgbe_adapter *adapter = q_vector->adapter; |
509ee935 | 1909 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 1910 | int v_idx = q_vector->v_idx; |
5d967eb7 | 1911 | u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR; |
fe49f04a | 1912 | |
bd508178 AD |
1913 | switch (adapter->hw.mac.type) { |
1914 | case ixgbe_mac_82598EB: | |
509ee935 JB |
1915 | /* must write high and low 16 bits to reset counter */ |
1916 | itr_reg |= (itr_reg << 16); | |
bd508178 AD |
1917 | break; |
1918 | case ixgbe_mac_82599EB: | |
b93a2226 | 1919 | case ixgbe_mac_X540: |
509ee935 JB |
1920 | /* |
1921 | * set the WDIS bit to not clear the timer bits and cause an | |
1922 | * immediate assertion of the interrupt | |
1923 | */ | |
1924 | itr_reg |= IXGBE_EITR_CNT_WDIS; | |
bd508178 AD |
1925 | break; |
1926 | default: | |
1927 | break; | |
509ee935 JB |
1928 | } |
1929 | IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg); | |
1930 | } | |
1931 | ||
bd198058 | 1932 | static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector) |
f494e8fa | 1933 | { |
d5bf4f67 | 1934 | u32 new_itr = q_vector->itr; |
bd198058 | 1935 | u8 current_itr; |
f494e8fa | 1936 | |
bd198058 AD |
1937 | ixgbe_update_itr(q_vector, &q_vector->tx); |
1938 | ixgbe_update_itr(q_vector, &q_vector->rx); | |
f494e8fa | 1939 | |
08c8833b | 1940 | current_itr = max(q_vector->rx.itr, q_vector->tx.itr); |
f494e8fa AV |
1941 | |
1942 | switch (current_itr) { | |
1943 | /* counts and packets in update_itr are dependent on these numbers */ | |
1944 | case lowest_latency: | |
d5bf4f67 | 1945 | new_itr = IXGBE_100K_ITR; |
f494e8fa AV |
1946 | break; |
1947 | case low_latency: | |
d5bf4f67 | 1948 | new_itr = IXGBE_20K_ITR; |
f494e8fa AV |
1949 | break; |
1950 | case bulk_latency: | |
d5bf4f67 | 1951 | new_itr = IXGBE_8K_ITR; |
f494e8fa | 1952 | break; |
bd198058 AD |
1953 | default: |
1954 | break; | |
f494e8fa AV |
1955 | } |
1956 | ||
d5bf4f67 | 1957 | if (new_itr != q_vector->itr) { |
fe49f04a | 1958 | /* do an exponential smoothing */ |
d5bf4f67 ET |
1959 | new_itr = (10 * new_itr * q_vector->itr) / |
1960 | ((9 * new_itr) + q_vector->itr); | |
509ee935 | 1961 | |
bd198058 | 1962 | /* save the algorithm value here */ |
5d967eb7 | 1963 | q_vector->itr = new_itr; |
fe49f04a AD |
1964 | |
1965 | ixgbe_write_eitr(q_vector); | |
f494e8fa | 1966 | } |
f494e8fa AV |
1967 | } |
1968 | ||
119fc60a | 1969 | /** |
de88eeeb | 1970 | * ixgbe_check_overtemp_subtask - check for over temperature |
f0f9778d | 1971 | * @adapter: pointer to adapter |
119fc60a | 1972 | **/ |
f0f9778d | 1973 | static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter) |
119fc60a | 1974 | { |
119fc60a MC |
1975 | struct ixgbe_hw *hw = &adapter->hw; |
1976 | u32 eicr = adapter->interrupt_event; | |
1977 | ||
f0f9778d | 1978 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
7ca647bd JP |
1979 | return; |
1980 | ||
f0f9778d AD |
1981 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) && |
1982 | !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT)) | |
1983 | return; | |
1984 | ||
1985 | adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
1986 | ||
7ca647bd | 1987 | switch (hw->device_id) { |
f0f9778d AD |
1988 | case IXGBE_DEV_ID_82599_T3_LOM: |
1989 | /* | |
1990 | * Since the warning interrupt is for both ports | |
1991 | * we don't have to check if: | |
1992 | * - This interrupt wasn't for our port. | |
1993 | * - We may have missed the interrupt so always have to | |
1994 | * check if we got a LSC | |
1995 | */ | |
1996 | if (!(eicr & IXGBE_EICR_GPI_SDP0) && | |
1997 | !(eicr & IXGBE_EICR_LSC)) | |
1998 | return; | |
1999 | ||
2000 | if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) { | |
2001 | u32 autoneg; | |
2002 | bool link_up = false; | |
7ca647bd | 2003 | |
7ca647bd JP |
2004 | hw->mac.ops.check_link(hw, &autoneg, &link_up, false); |
2005 | ||
f0f9778d AD |
2006 | if (link_up) |
2007 | return; | |
2008 | } | |
2009 | ||
2010 | /* Check if this is not due to overtemp */ | |
2011 | if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP) | |
2012 | return; | |
2013 | ||
2014 | break; | |
7ca647bd JP |
2015 | default: |
2016 | if (!(eicr & IXGBE_EICR_GPI_SDP0)) | |
119fc60a | 2017 | return; |
7ca647bd | 2018 | break; |
119fc60a | 2019 | } |
7ca647bd JP |
2020 | e_crit(drv, |
2021 | "Network adapter has been stopped because it has over heated. " | |
2022 | "Restart the computer. If the problem persists, " | |
2023 | "power off the system and replace the adapter\n"); | |
f0f9778d AD |
2024 | |
2025 | adapter->interrupt_event = 0; | |
119fc60a MC |
2026 | } |
2027 | ||
0befdb3e JB |
2028 | static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr) |
2029 | { | |
2030 | struct ixgbe_hw *hw = &adapter->hw; | |
2031 | ||
2032 | if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) && | |
2033 | (eicr & IXGBE_EICR_GPI_SDP1)) { | |
396e799c | 2034 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
0befdb3e JB |
2035 | /* write to clear the interrupt */ |
2036 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
2037 | } | |
2038 | } | |
cf8280ee | 2039 | |
4f51bf70 JK |
2040 | static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2041 | { | |
2042 | if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)) | |
2043 | return; | |
2044 | ||
2045 | switch (adapter->hw.mac.type) { | |
2046 | case ixgbe_mac_82599EB: | |
2047 | /* | |
2048 | * Need to check link state so complete overtemp check | |
2049 | * on service task | |
2050 | */ | |
2051 | if (((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)) && | |
2052 | (!test_bit(__IXGBE_DOWN, &adapter->state))) { | |
2053 | adapter->interrupt_event = eicr; | |
2054 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT; | |
2055 | ixgbe_service_event_schedule(adapter); | |
2056 | return; | |
2057 | } | |
2058 | return; | |
2059 | case ixgbe_mac_X540: | |
2060 | if (!(eicr & IXGBE_EICR_TS)) | |
2061 | return; | |
2062 | break; | |
2063 | default: | |
2064 | return; | |
2065 | } | |
2066 | ||
2067 | e_crit(drv, | |
2068 | "Network adapter has been stopped because it has over heated. " | |
2069 | "Restart the computer. If the problem persists, " | |
2070 | "power off the system and replace the adapter\n"); | |
2071 | } | |
2072 | ||
e8e26350 PW |
2073 | static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr) |
2074 | { | |
2075 | struct ixgbe_hw *hw = &adapter->hw; | |
2076 | ||
73c4b7cd AD |
2077 | if (eicr & IXGBE_EICR_GPI_SDP2) { |
2078 | /* Clear the interrupt */ | |
2079 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2); | |
7086400d AD |
2080 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2081 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
2082 | ixgbe_service_event_schedule(adapter); | |
2083 | } | |
73c4b7cd AD |
2084 | } |
2085 | ||
e8e26350 PW |
2086 | if (eicr & IXGBE_EICR_GPI_SDP1) { |
2087 | /* Clear the interrupt */ | |
2088 | IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1); | |
7086400d AD |
2089 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { |
2090 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
2091 | ixgbe_service_event_schedule(adapter); | |
2092 | } | |
e8e26350 PW |
2093 | } |
2094 | } | |
2095 | ||
cf8280ee JB |
2096 | static void ixgbe_check_lsc(struct ixgbe_adapter *adapter) |
2097 | { | |
2098 | struct ixgbe_hw *hw = &adapter->hw; | |
2099 | ||
2100 | adapter->lsc_int++; | |
2101 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
2102 | adapter->link_check_timeout = jiffies; | |
2103 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) { | |
2104 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC); | |
8a0717f3 | 2105 | IXGBE_WRITE_FLUSH(hw); |
93c52dd0 | 2106 | ixgbe_service_event_schedule(adapter); |
cf8280ee JB |
2107 | } |
2108 | } | |
2109 | ||
fe49f04a AD |
2110 | static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter, |
2111 | u64 qmask) | |
2112 | { | |
2113 | u32 mask; | |
bd508178 | 2114 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2115 | |
bd508178 AD |
2116 | switch (hw->mac.type) { |
2117 | case ixgbe_mac_82598EB: | |
fe49f04a | 2118 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2119 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask); |
2120 | break; | |
2121 | case ixgbe_mac_82599EB: | |
b93a2226 | 2122 | case ixgbe_mac_X540: |
fe49f04a | 2123 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2124 | if (mask) |
2125 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask); | |
fe49f04a | 2126 | mask = (qmask >> 32); |
bd508178 AD |
2127 | if (mask) |
2128 | IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask); | |
2129 | break; | |
2130 | default: | |
2131 | break; | |
fe49f04a AD |
2132 | } |
2133 | /* skip the flush */ | |
2134 | } | |
2135 | ||
2136 | static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter, | |
e8e9f696 | 2137 | u64 qmask) |
fe49f04a AD |
2138 | { |
2139 | u32 mask; | |
bd508178 | 2140 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 2141 | |
bd508178 AD |
2142 | switch (hw->mac.type) { |
2143 | case ixgbe_mac_82598EB: | |
fe49f04a | 2144 | mask = (IXGBE_EIMS_RTX_QUEUE & qmask); |
bd508178 AD |
2145 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask); |
2146 | break; | |
2147 | case ixgbe_mac_82599EB: | |
b93a2226 | 2148 | case ixgbe_mac_X540: |
fe49f04a | 2149 | mask = (qmask & 0xFFFFFFFF); |
bd508178 AD |
2150 | if (mask) |
2151 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask); | |
fe49f04a | 2152 | mask = (qmask >> 32); |
bd508178 AD |
2153 | if (mask) |
2154 | IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask); | |
2155 | break; | |
2156 | default: | |
2157 | break; | |
fe49f04a AD |
2158 | } |
2159 | /* skip the flush */ | |
2160 | } | |
2161 | ||
021230d4 | 2162 | /** |
2c4af694 AD |
2163 | * ixgbe_irq_enable - Enable default interrupt generation settings |
2164 | * @adapter: board private structure | |
021230d4 | 2165 | **/ |
2c4af694 AD |
2166 | static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues, |
2167 | bool flush) | |
9a799d71 | 2168 | { |
2c4af694 | 2169 | u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE); |
9a799d71 | 2170 | |
2c4af694 AD |
2171 | /* don't reenable LSC while waiting for link */ |
2172 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
2173 | mask &= ~IXGBE_EIMS_LSC; | |
9a799d71 | 2174 | |
2c4af694 | 2175 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) |
4f51bf70 JK |
2176 | switch (adapter->hw.mac.type) { |
2177 | case ixgbe_mac_82599EB: | |
2178 | mask |= IXGBE_EIMS_GPI_SDP0; | |
2179 | break; | |
2180 | case ixgbe_mac_X540: | |
2181 | mask |= IXGBE_EIMS_TS; | |
2182 | break; | |
2183 | default: | |
2184 | break; | |
2185 | } | |
2c4af694 AD |
2186 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) |
2187 | mask |= IXGBE_EIMS_GPI_SDP1; | |
2188 | switch (adapter->hw.mac.type) { | |
2189 | case ixgbe_mac_82599EB: | |
2c4af694 AD |
2190 | mask |= IXGBE_EIMS_GPI_SDP1; |
2191 | mask |= IXGBE_EIMS_GPI_SDP2; | |
858bc081 DS |
2192 | case ixgbe_mac_X540: |
2193 | mask |= IXGBE_EIMS_ECC; | |
2c4af694 AD |
2194 | mask |= IXGBE_EIMS_MAILBOX; |
2195 | break; | |
2196 | default: | |
2197 | break; | |
9a799d71 | 2198 | } |
2c4af694 AD |
2199 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2200 | !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) | |
2201 | mask |= IXGBE_EIMS_FLOW_DIR; | |
9a799d71 | 2202 | |
2c4af694 AD |
2203 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask); |
2204 | if (queues) | |
2205 | ixgbe_irq_enable_queues(adapter, ~0); | |
2206 | if (flush) | |
2207 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
9a799d71 AK |
2208 | } |
2209 | ||
2c4af694 | 2210 | static irqreturn_t ixgbe_msix_other(int irq, void *data) |
f0848276 | 2211 | { |
a65151ba | 2212 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2213 | struct ixgbe_hw *hw = &adapter->hw; |
54037505 | 2214 | u32 eicr; |
91281fd3 | 2215 | |
54037505 DS |
2216 | /* |
2217 | * Workaround for Silicon errata. Use clear-by-write instead | |
2218 | * of clear-by-read. Reading with EICS will return the | |
2219 | * interrupt causes without clearing, which later be done | |
2220 | * with the write to EICR. | |
2221 | */ | |
2222 | eicr = IXGBE_READ_REG(hw, IXGBE_EICS); | |
2223 | IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr); | |
33cf09c9 | 2224 | |
cf8280ee JB |
2225 | if (eicr & IXGBE_EICR_LSC) |
2226 | ixgbe_check_lsc(adapter); | |
f0848276 | 2227 | |
1cdd1ec8 GR |
2228 | if (eicr & IXGBE_EICR_MAILBOX) |
2229 | ixgbe_msg_task(adapter); | |
efe3d3c8 | 2230 | |
bd508178 AD |
2231 | switch (hw->mac.type) { |
2232 | case ixgbe_mac_82599EB: | |
b93a2226 | 2233 | case ixgbe_mac_X540: |
2c4af694 AD |
2234 | if (eicr & IXGBE_EICR_ECC) |
2235 | e_info(link, "Received unrecoverable ECC Err, please " | |
2236 | "reboot\n"); | |
c4cf55e5 PWJ |
2237 | /* Handle Flow Director Full threshold interrupt */ |
2238 | if (eicr & IXGBE_EICR_FLOW_DIR) { | |
d034acf1 | 2239 | int reinit_count = 0; |
c4cf55e5 | 2240 | int i; |
c4cf55e5 | 2241 | for (i = 0; i < adapter->num_tx_queues; i++) { |
d034acf1 | 2242 | struct ixgbe_ring *ring = adapter->tx_ring[i]; |
7d637bcc | 2243 | if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE, |
d034acf1 AD |
2244 | &ring->state)) |
2245 | reinit_count++; | |
2246 | } | |
2247 | if (reinit_count) { | |
2248 | /* no more flow director interrupts until after init */ | |
2249 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR); | |
d034acf1 AD |
2250 | adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT; |
2251 | ixgbe_service_event_schedule(adapter); | |
c4cf55e5 PWJ |
2252 | } |
2253 | } | |
f0f9778d | 2254 | ixgbe_check_sfp_event(adapter, eicr); |
4f51bf70 | 2255 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2256 | break; |
2257 | default: | |
2258 | break; | |
c4cf55e5 | 2259 | } |
f0848276 | 2260 | |
bd508178 | 2261 | ixgbe_check_fan_failure(adapter, eicr); |
efe3d3c8 | 2262 | |
7086400d | 2263 | /* re-enable the original interrupt state, no lsc, no queues */ |
d4f80882 | 2264 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2c4af694 | 2265 | ixgbe_irq_enable(adapter, false, false); |
f0848276 | 2266 | |
9a799d71 | 2267 | return IRQ_HANDLED; |
f0848276 | 2268 | } |
91281fd3 | 2269 | |
4ff7fb12 | 2270 | static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data) |
91281fd3 | 2271 | { |
021230d4 | 2272 | struct ixgbe_q_vector *q_vector = data; |
91281fd3 | 2273 | |
9b471446 | 2274 | /* EIAM disabled interrupts (on this vector) for us */ |
91281fd3 | 2275 | |
4ff7fb12 AD |
2276 | if (q_vector->rx.ring || q_vector->tx.ring) |
2277 | napi_schedule(&q_vector->napi); | |
91281fd3 | 2278 | |
9a799d71 | 2279 | return IRQ_HANDLED; |
91281fd3 AD |
2280 | } |
2281 | ||
021230d4 AV |
2282 | /** |
2283 | * ixgbe_request_msix_irqs - Initialize MSI-X interrupts | |
2284 | * @adapter: board private structure | |
2285 | * | |
2286 | * ixgbe_request_msix_irqs allocates MSI-X vectors and requests | |
2287 | * interrupts from the kernel. | |
2288 | **/ | |
2289 | static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) | |
2290 | { | |
2291 | struct net_device *netdev = adapter->netdev; | |
207867f5 AD |
2292 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
2293 | int vector, err; | |
e8e9f696 | 2294 | int ri = 0, ti = 0; |
021230d4 | 2295 | |
021230d4 | 2296 | for (vector = 0; vector < q_vectors; vector++) { |
d0759ebb | 2297 | struct ixgbe_q_vector *q_vector = adapter->q_vector[vector]; |
207867f5 | 2298 | struct msix_entry *entry = &adapter->msix_entries[vector]; |
cb13fc20 | 2299 | |
4ff7fb12 | 2300 | if (q_vector->tx.ring && q_vector->rx.ring) { |
9fe93afd | 2301 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2302 | "%s-%s-%d", netdev->name, "TxRx", ri++); |
2303 | ti++; | |
2304 | } else if (q_vector->rx.ring) { | |
9fe93afd | 2305 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 AD |
2306 | "%s-%s-%d", netdev->name, "rx", ri++); |
2307 | } else if (q_vector->tx.ring) { | |
9fe93afd | 2308 | snprintf(q_vector->name, sizeof(q_vector->name) - 1, |
4ff7fb12 | 2309 | "%s-%s-%d", netdev->name, "tx", ti++); |
d0759ebb AD |
2310 | } else { |
2311 | /* skip this unused q_vector */ | |
2312 | continue; | |
32aa77a4 | 2313 | } |
207867f5 AD |
2314 | err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0, |
2315 | q_vector->name, q_vector); | |
9a799d71 | 2316 | if (err) { |
396e799c | 2317 | e_err(probe, "request_irq failed for MSIX interrupt " |
849c4542 | 2318 | "Error: %d\n", err); |
021230d4 | 2319 | goto free_queue_irqs; |
9a799d71 | 2320 | } |
207867f5 AD |
2321 | /* If Flow Director is enabled, set interrupt affinity */ |
2322 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
2323 | /* assign the mask for this irq */ | |
2324 | irq_set_affinity_hint(entry->vector, | |
de88eeeb | 2325 | &q_vector->affinity_mask); |
207867f5 | 2326 | } |
9a799d71 AK |
2327 | } |
2328 | ||
021230d4 | 2329 | err = request_irq(adapter->msix_entries[vector].vector, |
2c4af694 | 2330 | ixgbe_msix_other, 0, netdev->name, adapter); |
9a799d71 | 2331 | if (err) { |
de88eeeb | 2332 | e_err(probe, "request_irq for msix_other failed: %d\n", err); |
021230d4 | 2333 | goto free_queue_irqs; |
9a799d71 AK |
2334 | } |
2335 | ||
9a799d71 AK |
2336 | return 0; |
2337 | ||
021230d4 | 2338 | free_queue_irqs: |
207867f5 AD |
2339 | while (vector) { |
2340 | vector--; | |
2341 | irq_set_affinity_hint(adapter->msix_entries[vector].vector, | |
2342 | NULL); | |
2343 | free_irq(adapter->msix_entries[vector].vector, | |
2344 | adapter->q_vector[vector]); | |
2345 | } | |
021230d4 AV |
2346 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
2347 | pci_disable_msix(adapter->pdev); | |
9a799d71 AK |
2348 | kfree(adapter->msix_entries); |
2349 | adapter->msix_entries = NULL; | |
9a799d71 AK |
2350 | return err; |
2351 | } | |
2352 | ||
2353 | /** | |
021230d4 | 2354 | * ixgbe_intr - legacy mode Interrupt Handler |
9a799d71 AK |
2355 | * @irq: interrupt number |
2356 | * @data: pointer to a network interface device structure | |
9a799d71 AK |
2357 | **/ |
2358 | static irqreturn_t ixgbe_intr(int irq, void *data) | |
2359 | { | |
a65151ba | 2360 | struct ixgbe_adapter *adapter = data; |
9a799d71 | 2361 | struct ixgbe_hw *hw = &adapter->hw; |
7a921c93 | 2362 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 AK |
2363 | u32 eicr; |
2364 | ||
54037505 | 2365 | /* |
24ddd967 | 2366 | * Workaround for silicon errata #26 on 82598. Mask the interrupt |
54037505 DS |
2367 | * before the read of EICR. |
2368 | */ | |
2369 | IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); | |
2370 | ||
021230d4 | 2371 | /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read |
52f33af8 | 2372 | * therefore no explicit interrupt disable is necessary */ |
021230d4 | 2373 | eicr = IXGBE_READ_REG(hw, IXGBE_EICR); |
f47cf66e | 2374 | if (!eicr) { |
6af3b9eb ET |
2375 | /* |
2376 | * shared interrupt alert! | |
f47cf66e | 2377 | * make sure interrupts are enabled because the read will |
6af3b9eb ET |
2378 | * have disabled interrupts due to EIAM |
2379 | * finish the workaround of silicon errata on 82598. Unmask | |
2380 | * the interrupt that we masked before the EICR read. | |
2381 | */ | |
2382 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
2383 | ixgbe_irq_enable(adapter, true, true); | |
9a799d71 | 2384 | return IRQ_NONE; /* Not our interrupt */ |
f47cf66e | 2385 | } |
9a799d71 | 2386 | |
cf8280ee JB |
2387 | if (eicr & IXGBE_EICR_LSC) |
2388 | ixgbe_check_lsc(adapter); | |
021230d4 | 2389 | |
bd508178 AD |
2390 | switch (hw->mac.type) { |
2391 | case ixgbe_mac_82599EB: | |
e8e26350 | 2392 | ixgbe_check_sfp_event(adapter, eicr); |
0ccb974d DS |
2393 | /* Fall through */ |
2394 | case ixgbe_mac_X540: | |
2395 | if (eicr & IXGBE_EICR_ECC) | |
2396 | e_info(link, "Received unrecoverable ECC err, please " | |
2397 | "reboot\n"); | |
4f51bf70 | 2398 | ixgbe_check_overtemp_event(adapter, eicr); |
bd508178 AD |
2399 | break; |
2400 | default: | |
2401 | break; | |
2402 | } | |
e8e26350 | 2403 | |
0befdb3e JB |
2404 | ixgbe_check_fan_failure(adapter, eicr); |
2405 | ||
b9f6ed2b AD |
2406 | /* would disable interrupts here but EIAM disabled it */ |
2407 | napi_schedule(&q_vector->napi); | |
9a799d71 | 2408 | |
6af3b9eb ET |
2409 | /* |
2410 | * re-enable link(maybe) and non-queue interrupts, no flush. | |
2411 | * ixgbe_poll will re-enable the queue interrupts | |
2412 | */ | |
6af3b9eb ET |
2413 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) |
2414 | ixgbe_irq_enable(adapter, false, false); | |
2415 | ||
9a799d71 AK |
2416 | return IRQ_HANDLED; |
2417 | } | |
2418 | ||
2419 | /** | |
2420 | * ixgbe_request_irq - initialize interrupts | |
2421 | * @adapter: board private structure | |
2422 | * | |
2423 | * Attempts to configure interrupts using the best available | |
2424 | * capabilities of the hardware and kernel. | |
2425 | **/ | |
021230d4 | 2426 | static int ixgbe_request_irq(struct ixgbe_adapter *adapter) |
9a799d71 AK |
2427 | { |
2428 | struct net_device *netdev = adapter->netdev; | |
021230d4 | 2429 | int err; |
9a799d71 | 2430 | |
4cc6df29 | 2431 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
021230d4 | 2432 | err = ixgbe_request_msix_irqs(adapter); |
4cc6df29 | 2433 | else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) |
a0607fd3 | 2434 | err = request_irq(adapter->pdev->irq, ixgbe_intr, 0, |
a65151ba | 2435 | netdev->name, adapter); |
4cc6df29 | 2436 | else |
a0607fd3 | 2437 | err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED, |
a65151ba | 2438 | netdev->name, adapter); |
9a799d71 | 2439 | |
de88eeeb | 2440 | if (err) |
396e799c | 2441 | e_err(probe, "request_irq failed, Error %d\n", err); |
9a799d71 | 2442 | |
9a799d71 AK |
2443 | return err; |
2444 | } | |
2445 | ||
2446 | static void ixgbe_free_irq(struct ixgbe_adapter *adapter) | |
2447 | { | |
9a799d71 | 2448 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
021230d4 | 2449 | int i, q_vectors; |
9a799d71 | 2450 | |
021230d4 | 2451 | q_vectors = adapter->num_msix_vectors; |
021230d4 | 2452 | i = q_vectors - 1; |
a65151ba | 2453 | free_irq(adapter->msix_entries[i].vector, adapter); |
021230d4 | 2454 | i--; |
4cc6df29 | 2455 | |
021230d4 | 2456 | for (; i >= 0; i--) { |
894ff7cf | 2457 | /* free only the irqs that were actually requested */ |
4ff7fb12 AD |
2458 | if (!adapter->q_vector[i]->rx.ring && |
2459 | !adapter->q_vector[i]->tx.ring) | |
894ff7cf AD |
2460 | continue; |
2461 | ||
207867f5 AD |
2462 | /* clear the affinity_mask in the IRQ descriptor */ |
2463 | irq_set_affinity_hint(adapter->msix_entries[i].vector, | |
2464 | NULL); | |
2465 | ||
021230d4 | 2466 | free_irq(adapter->msix_entries[i].vector, |
e8e9f696 | 2467 | adapter->q_vector[i]); |
021230d4 | 2468 | } |
021230d4 | 2469 | } else { |
a65151ba | 2470 | free_irq(adapter->pdev->irq, adapter); |
9a799d71 AK |
2471 | } |
2472 | } | |
2473 | ||
22d5a71b JB |
2474 | /** |
2475 | * ixgbe_irq_disable - Mask off interrupt generation on the NIC | |
2476 | * @adapter: board private structure | |
2477 | **/ | |
2478 | static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter) | |
2479 | { | |
bd508178 AD |
2480 | switch (adapter->hw.mac.type) { |
2481 | case ixgbe_mac_82598EB: | |
835462fc | 2482 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0); |
bd508178 AD |
2483 | break; |
2484 | case ixgbe_mac_82599EB: | |
b93a2226 | 2485 | case ixgbe_mac_X540: |
835462fc NS |
2486 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000); |
2487 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0); | |
22d5a71b | 2488 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0); |
bd508178 AD |
2489 | break; |
2490 | default: | |
2491 | break; | |
22d5a71b JB |
2492 | } |
2493 | IXGBE_WRITE_FLUSH(&adapter->hw); | |
2494 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
2495 | int i; | |
2496 | for (i = 0; i < adapter->num_msix_vectors; i++) | |
2497 | synchronize_irq(adapter->msix_entries[i].vector); | |
2498 | } else { | |
2499 | synchronize_irq(adapter->pdev->irq); | |
2500 | } | |
2501 | } | |
2502 | ||
9a799d71 AK |
2503 | /** |
2504 | * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts | |
2505 | * | |
2506 | **/ | |
2507 | static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter) | |
2508 | { | |
d5bf4f67 | 2509 | struct ixgbe_q_vector *q_vector = adapter->q_vector[0]; |
9a799d71 | 2510 | |
d5bf4f67 ET |
2511 | /* rx/tx vector */ |
2512 | if (adapter->rx_itr_setting == 1) | |
2513 | q_vector->itr = IXGBE_20K_ITR; | |
2514 | else | |
2515 | q_vector->itr = adapter->rx_itr_setting; | |
2516 | ||
2517 | ixgbe_write_eitr(q_vector); | |
9a799d71 | 2518 | |
e8e26350 PW |
2519 | ixgbe_set_ivar(adapter, 0, 0, 0); |
2520 | ixgbe_set_ivar(adapter, 1, 0, 0); | |
021230d4 | 2521 | |
396e799c | 2522 | e_info(hw, "Legacy interrupt IVAR setup done\n"); |
9a799d71 AK |
2523 | } |
2524 | ||
43e69bf0 AD |
2525 | /** |
2526 | * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset | |
2527 | * @adapter: board private structure | |
2528 | * @ring: structure containing ring specific data | |
2529 | * | |
2530 | * Configure the Tx descriptor ring after a reset. | |
2531 | **/ | |
84418e3b AD |
2532 | void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter, |
2533 | struct ixgbe_ring *ring) | |
43e69bf0 AD |
2534 | { |
2535 | struct ixgbe_hw *hw = &adapter->hw; | |
2536 | u64 tdba = ring->dma; | |
2f1860b8 | 2537 | int wait_loop = 10; |
b88c6de2 | 2538 | u32 txdctl = IXGBE_TXDCTL_ENABLE; |
bf29ee6c | 2539 | u8 reg_idx = ring->reg_idx; |
43e69bf0 | 2540 | |
2f1860b8 | 2541 | /* disable queue to avoid issues while updating state */ |
b88c6de2 | 2542 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); |
2f1860b8 AD |
2543 | IXGBE_WRITE_FLUSH(hw); |
2544 | ||
43e69bf0 | 2545 | IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx), |
e8e9f696 | 2546 | (tdba & DMA_BIT_MASK(32))); |
43e69bf0 AD |
2547 | IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32)); |
2548 | IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx), | |
2549 | ring->count * sizeof(union ixgbe_adv_tx_desc)); | |
2550 | IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0); | |
2551 | IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0); | |
84ea2591 | 2552 | ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx); |
43e69bf0 | 2553 | |
b88c6de2 AD |
2554 | /* |
2555 | * set WTHRESH to encourage burst writeback, it should not be set | |
2556 | * higher than 1 when ITR is 0 as it could cause false TX hangs | |
2557 | * | |
2558 | * In order to avoid issues WTHRESH + PTHRESH should always be equal | |
2559 | * to or less than the number of on chip descriptors, which is | |
2560 | * currently 40. | |
2561 | */ | |
e954b374 | 2562 | if (!ring->q_vector || (ring->q_vector->itr < 8)) |
b88c6de2 AD |
2563 | txdctl |= (1 << 16); /* WTHRESH = 1 */ |
2564 | else | |
2565 | txdctl |= (8 << 16); /* WTHRESH = 8 */ | |
2566 | ||
e954b374 AD |
2567 | /* |
2568 | * Setting PTHRESH to 32 both improves performance | |
2569 | * and avoids a TX hang with DFP enabled | |
2570 | */ | |
b88c6de2 AD |
2571 | txdctl |= (1 << 8) | /* HTHRESH = 1 */ |
2572 | 32; /* PTHRESH = 32 */ | |
2f1860b8 AD |
2573 | |
2574 | /* reinitialize flowdirector state */ | |
ee9e0f0b AD |
2575 | if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) && |
2576 | adapter->atr_sample_rate) { | |
2577 | ring->atr_sample_rate = adapter->atr_sample_rate; | |
2578 | ring->atr_count = 0; | |
2579 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state); | |
2580 | } else { | |
2581 | ring->atr_sample_rate = 0; | |
2582 | } | |
2f1860b8 | 2583 | |
c84d324c JF |
2584 | clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state); |
2585 | ||
2f1860b8 | 2586 | /* enable queue */ |
2f1860b8 AD |
2587 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); |
2588 | ||
b2d96e0a AD |
2589 | netdev_tx_reset_queue(txring_txq(ring)); |
2590 | ||
2f1860b8 AD |
2591 | /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ |
2592 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2593 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2594 | return; | |
2595 | ||
2596 | /* poll to verify queue is enabled */ | |
2597 | do { | |
032b4325 | 2598 | usleep_range(1000, 2000); |
2f1860b8 AD |
2599 | txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx)); |
2600 | } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE)); | |
2601 | if (!wait_loop) | |
2602 | e_err(drv, "Could not enable Tx Queue %d\n", reg_idx); | |
43e69bf0 AD |
2603 | } |
2604 | ||
120ff942 AD |
2605 | static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter) |
2606 | { | |
2607 | struct ixgbe_hw *hw = &adapter->hw; | |
2608 | u32 rttdcs; | |
72a32f1f | 2609 | u32 reg; |
8b1c0b24 | 2610 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
120ff942 AD |
2611 | |
2612 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2613 | return; | |
2614 | ||
2615 | /* disable the arbiter while setting MTQC */ | |
2616 | rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS); | |
2617 | rttdcs |= IXGBE_RTTDCS_ARBDIS; | |
2618 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2619 | ||
2620 | /* set transmit pool layout */ | |
8b1c0b24 | 2621 | switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
120ff942 AD |
2622 | case (IXGBE_FLAG_SRIOV_ENABLED): |
2623 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, | |
2624 | (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF)); | |
2625 | break; | |
8b1c0b24 JF |
2626 | default: |
2627 | if (!tcs) | |
2628 | reg = IXGBE_MTQC_64Q_1PB; | |
2629 | else if (tcs <= 4) | |
2630 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ; | |
2631 | else | |
2632 | reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ; | |
120ff942 | 2633 | |
8b1c0b24 | 2634 | IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg); |
120ff942 | 2635 | |
8b1c0b24 JF |
2636 | /* Enable Security TX Buffer IFG for multiple pb */ |
2637 | if (tcs) { | |
2638 | reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG); | |
2639 | reg |= IXGBE_SECTX_DCB; | |
2640 | IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg); | |
2641 | } | |
120ff942 AD |
2642 | break; |
2643 | } | |
2644 | ||
2645 | /* re-enable the arbiter */ | |
2646 | rttdcs &= ~IXGBE_RTTDCS_ARBDIS; | |
2647 | IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs); | |
2648 | } | |
2649 | ||
9a799d71 | 2650 | /** |
3a581073 | 2651 | * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset |
9a799d71 AK |
2652 | * @adapter: board private structure |
2653 | * | |
2654 | * Configure the Tx unit of the MAC after a reset. | |
2655 | **/ | |
2656 | static void ixgbe_configure_tx(struct ixgbe_adapter *adapter) | |
2657 | { | |
2f1860b8 AD |
2658 | struct ixgbe_hw *hw = &adapter->hw; |
2659 | u32 dmatxctl; | |
43e69bf0 | 2660 | u32 i; |
9a799d71 | 2661 | |
2f1860b8 AD |
2662 | ixgbe_setup_mtqc(adapter); |
2663 | ||
2664 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
2665 | /* DMATXCTL.EN must be before Tx queues are enabled */ | |
2666 | dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); | |
2667 | dmatxctl |= IXGBE_DMATXCTL_TE; | |
2668 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl); | |
2669 | } | |
2670 | ||
9a799d71 | 2671 | /* Setup the HW Tx Head and Tail descriptor pointers */ |
43e69bf0 AD |
2672 | for (i = 0; i < adapter->num_tx_queues; i++) |
2673 | ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]); | |
9a799d71 AK |
2674 | } |
2675 | ||
e8e26350 | 2676 | #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 |
cc41ac7c | 2677 | |
a6616b42 | 2678 | static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, |
e8e9f696 | 2679 | struct ixgbe_ring *rx_ring) |
cc41ac7c | 2680 | { |
cc41ac7c | 2681 | u32 srrctl; |
bf29ee6c | 2682 | u8 reg_idx = rx_ring->reg_idx; |
3be1adfb | 2683 | |
bd508178 AD |
2684 | switch (adapter->hw.mac.type) { |
2685 | case ixgbe_mac_82598EB: { | |
2686 | struct ixgbe_ring_feature *feature = adapter->ring_feature; | |
2687 | const int mask = feature[RING_F_RSS].mask; | |
bf29ee6c | 2688 | reg_idx = reg_idx & mask; |
cc41ac7c | 2689 | } |
bd508178 AD |
2690 | break; |
2691 | case ixgbe_mac_82599EB: | |
b93a2226 | 2692 | case ixgbe_mac_X540: |
bd508178 AD |
2693 | default: |
2694 | break; | |
2695 | } | |
2696 | ||
bf29ee6c | 2697 | srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx)); |
cc41ac7c JB |
2698 | |
2699 | srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2700 | srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK; | |
9e10e045 AD |
2701 | if (adapter->num_vfs) |
2702 | srrctl |= IXGBE_SRRCTL_DROP_EN; | |
cc41ac7c | 2703 | |
afafd5b0 AD |
2704 | srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) & |
2705 | IXGBE_SRRCTL_BSIZEHDR_MASK; | |
2706 | ||
f800326d AD |
2707 | #if PAGE_SIZE > IXGBE_MAX_RXBUFFER |
2708 | srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; | |
afafd5b0 | 2709 | #else |
f800326d | 2710 | srrctl |= ixgbe_rx_bufsz(rx_ring) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT; |
afafd5b0 | 2711 | #endif |
f800326d | 2712 | srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF; |
e8e26350 | 2713 | |
bf29ee6c | 2714 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl); |
cc41ac7c | 2715 | } |
9a799d71 | 2716 | |
05abb126 | 2717 | static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter) |
0cefafad | 2718 | { |
05abb126 AD |
2719 | struct ixgbe_hw *hw = &adapter->hw; |
2720 | static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D, | |
e8e9f696 JP |
2721 | 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE, |
2722 | 0x6A3E67EA, 0x14364D17, 0x3BED200D}; | |
05abb126 AD |
2723 | u32 mrqc = 0, reta = 0; |
2724 | u32 rxcsum; | |
2725 | int i, j; | |
8b1c0b24 | 2726 | u8 tcs = netdev_get_num_tc(adapter->netdev); |
86b4db3b JF |
2727 | int maxq = adapter->ring_feature[RING_F_RSS].indices; |
2728 | ||
2729 | if (tcs) | |
2730 | maxq = min(maxq, adapter->num_tx_queues / tcs); | |
0cefafad | 2731 | |
05abb126 AD |
2732 | /* Fill out hash function seeds */ |
2733 | for (i = 0; i < 10; i++) | |
2734 | IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]); | |
2735 | ||
2736 | /* Fill out redirection table */ | |
2737 | for (i = 0, j = 0; i < 128; i++, j++) { | |
86b4db3b | 2738 | if (j == maxq) |
05abb126 AD |
2739 | j = 0; |
2740 | /* reta = 4-byte sliding window of | |
2741 | * 0x00..(indices-1)(indices-1)00..etc. */ | |
2742 | reta = (reta << 8) | (j * 0x11); | |
2743 | if ((i & 3) == 3) | |
2744 | IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta); | |
2745 | } | |
0cefafad | 2746 | |
05abb126 AD |
2747 | /* Disable indicating checksum in descriptor, enables RSS hash */ |
2748 | rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM); | |
2749 | rxcsum |= IXGBE_RXCSUM_PCSD; | |
2750 | IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum); | |
2751 | ||
8b1c0b24 JF |
2752 | if (adapter->hw.mac.type == ixgbe_mac_82598EB && |
2753 | (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { | |
0cefafad | 2754 | mrqc = IXGBE_MRQC_RSSEN; |
8b1c0b24 JF |
2755 | } else { |
2756 | int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED | |
2757 | | IXGBE_FLAG_SRIOV_ENABLED); | |
2758 | ||
2759 | switch (mask) { | |
2760 | case (IXGBE_FLAG_RSS_ENABLED): | |
2761 | if (!tcs) | |
2762 | mrqc = IXGBE_MRQC_RSSEN; | |
2763 | else if (tcs <= 4) | |
2764 | mrqc = IXGBE_MRQC_RTRSS4TCEN; | |
2765 | else | |
2766 | mrqc = IXGBE_MRQC_RTRSS8TCEN; | |
2767 | break; | |
2768 | case (IXGBE_FLAG_SRIOV_ENABLED): | |
2769 | mrqc = IXGBE_MRQC_VMDQEN; | |
2770 | break; | |
2771 | default: | |
2772 | break; | |
2773 | } | |
0cefafad JB |
2774 | } |
2775 | ||
05abb126 AD |
2776 | /* Perform hash on these packet types */ |
2777 | mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4 | |
2778 | | IXGBE_MRQC_RSS_FIELD_IPV4_TCP | |
2779 | | IXGBE_MRQC_RSS_FIELD_IPV6 | |
2780 | | IXGBE_MRQC_RSS_FIELD_IPV6_TCP; | |
2781 | ||
2782 | IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc); | |
0cefafad JB |
2783 | } |
2784 | ||
bb5a9ad2 NS |
2785 | /** |
2786 | * ixgbe_configure_rscctl - enable RSC for the indicated ring | |
2787 | * @adapter: address of board private structure | |
2788 | * @index: index of ring to set | |
bb5a9ad2 | 2789 | **/ |
082757af | 2790 | static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter, |
7367096a | 2791 | struct ixgbe_ring *ring) |
bb5a9ad2 | 2792 | { |
bb5a9ad2 | 2793 | struct ixgbe_hw *hw = &adapter->hw; |
bb5a9ad2 | 2794 | u32 rscctrl; |
bf29ee6c | 2795 | u8 reg_idx = ring->reg_idx; |
7367096a | 2796 | |
7d637bcc | 2797 | if (!ring_is_rsc_enabled(ring)) |
7367096a | 2798 | return; |
bb5a9ad2 | 2799 | |
7367096a | 2800 | rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx)); |
bb5a9ad2 NS |
2801 | rscctrl |= IXGBE_RSCCTL_RSCEN; |
2802 | /* | |
2803 | * we must limit the number of descriptors so that the | |
2804 | * total size of max desc * buf_len is not greater | |
642c680e | 2805 | * than 65536 |
bb5a9ad2 | 2806 | */ |
f800326d AD |
2807 | #if (PAGE_SIZE <= 8192) |
2808 | rscctrl |= IXGBE_RSCCTL_MAXDESC_16; | |
2809 | #elif (PAGE_SIZE <= 16384) | |
2810 | rscctrl |= IXGBE_RSCCTL_MAXDESC_8; | |
bb5a9ad2 | 2811 | #else |
f800326d | 2812 | rscctrl |= IXGBE_RSCCTL_MAXDESC_4; |
bb5a9ad2 | 2813 | #endif |
7367096a | 2814 | IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl); |
bb5a9ad2 NS |
2815 | } |
2816 | ||
9e10e045 AD |
2817 | /** |
2818 | * ixgbe_set_uta - Set unicast filter table address | |
2819 | * @adapter: board private structure | |
2820 | * | |
2821 | * The unicast table address is a register array of 32-bit registers. | |
2822 | * The table is meant to be used in a way similar to how the MTA is used | |
2823 | * however due to certain limitations in the hardware it is necessary to | |
2824 | * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous | |
2825 | * enable bit to allow vlan tag stripping when promiscuous mode is enabled | |
2826 | **/ | |
2827 | static void ixgbe_set_uta(struct ixgbe_adapter *adapter) | |
2828 | { | |
2829 | struct ixgbe_hw *hw = &adapter->hw; | |
2830 | int i; | |
2831 | ||
2832 | /* The UTA table only exists on 82599 hardware and newer */ | |
2833 | if (hw->mac.type < ixgbe_mac_82599EB) | |
2834 | return; | |
2835 | ||
2836 | /* we only need to do this if VMDq is enabled */ | |
2837 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2838 | return; | |
2839 | ||
2840 | for (i = 0; i < 128; i++) | |
2841 | IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0); | |
2842 | } | |
2843 | ||
2844 | #define IXGBE_MAX_RX_DESC_POLL 10 | |
2845 | static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter, | |
2846 | struct ixgbe_ring *ring) | |
2847 | { | |
2848 | struct ixgbe_hw *hw = &adapter->hw; | |
9e10e045 AD |
2849 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; |
2850 | u32 rxdctl; | |
bf29ee6c | 2851 | u8 reg_idx = ring->reg_idx; |
9e10e045 AD |
2852 | |
2853 | /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */ | |
2854 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2855 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2856 | return; | |
2857 | ||
2858 | do { | |
032b4325 | 2859 | usleep_range(1000, 2000); |
9e10e045 AD |
2860 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); |
2861 | } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2862 | ||
2863 | if (!wait_loop) { | |
2864 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within " | |
2865 | "the polling period\n", reg_idx); | |
2866 | } | |
2867 | } | |
2868 | ||
2d39d576 YZ |
2869 | void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter, |
2870 | struct ixgbe_ring *ring) | |
2871 | { | |
2872 | struct ixgbe_hw *hw = &adapter->hw; | |
2873 | int wait_loop = IXGBE_MAX_RX_DESC_POLL; | |
2874 | u32 rxdctl; | |
2875 | u8 reg_idx = ring->reg_idx; | |
2876 | ||
2877 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2878 | rxdctl &= ~IXGBE_RXDCTL_ENABLE; | |
2879 | ||
2880 | /* write value back with RXDCTL.ENABLE bit cleared */ | |
2881 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2882 | ||
2883 | if (hw->mac.type == ixgbe_mac_82598EB && | |
2884 | !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) | |
2885 | return; | |
2886 | ||
2887 | /* the hardware may take up to 100us to really disable the rx queue */ | |
2888 | do { | |
2889 | udelay(10); | |
2890 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2891 | } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE)); | |
2892 | ||
2893 | if (!wait_loop) { | |
2894 | e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within " | |
2895 | "the polling period\n", reg_idx); | |
2896 | } | |
2897 | } | |
2898 | ||
84418e3b AD |
2899 | void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter, |
2900 | struct ixgbe_ring *ring) | |
acd37177 AD |
2901 | { |
2902 | struct ixgbe_hw *hw = &adapter->hw; | |
2903 | u64 rdba = ring->dma; | |
9e10e045 | 2904 | u32 rxdctl; |
bf29ee6c | 2905 | u8 reg_idx = ring->reg_idx; |
acd37177 | 2906 | |
9e10e045 AD |
2907 | /* disable queue to avoid issues while updating state */ |
2908 | rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx)); | |
2d39d576 | 2909 | ixgbe_disable_rx_queue(adapter, ring); |
9e10e045 | 2910 | |
acd37177 AD |
2911 | IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32))); |
2912 | IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32)); | |
2913 | IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx), | |
2914 | ring->count * sizeof(union ixgbe_adv_rx_desc)); | |
2915 | IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0); | |
2916 | IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0); | |
84ea2591 | 2917 | ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx); |
9e10e045 AD |
2918 | |
2919 | ixgbe_configure_srrctl(adapter, ring); | |
2920 | ixgbe_configure_rscctl(adapter, ring); | |
2921 | ||
e9f98072 GR |
2922 | /* If operating in IOV mode set RLPML for X540 */ |
2923 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
2924 | hw->mac.type == ixgbe_mac_X540) { | |
2925 | rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK; | |
2926 | rxdctl |= ((ring->netdev->mtu + ETH_HLEN + | |
2927 | ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN); | |
2928 | } | |
2929 | ||
9e10e045 AD |
2930 | if (hw->mac.type == ixgbe_mac_82598EB) { |
2931 | /* | |
2932 | * enable cache line friendly hardware writes: | |
2933 | * PTHRESH=32 descriptors (half the internal cache), | |
2934 | * this also removes ugly rx_no_buffer_count increment | |
2935 | * HTHRESH=4 descriptors (to minimize latency on fetch) | |
2936 | * WTHRESH=8 burst writeback up to two cache lines | |
2937 | */ | |
2938 | rxdctl &= ~0x3FFFFF; | |
2939 | rxdctl |= 0x080420; | |
2940 | } | |
2941 | ||
2942 | /* enable receive descriptor ring */ | |
2943 | rxdctl |= IXGBE_RXDCTL_ENABLE; | |
2944 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl); | |
2945 | ||
2946 | ixgbe_rx_desc_queue_enable(adapter, ring); | |
7d4987de | 2947 | ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring)); |
acd37177 AD |
2948 | } |
2949 | ||
48654521 AD |
2950 | static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter) |
2951 | { | |
2952 | struct ixgbe_hw *hw = &adapter->hw; | |
2953 | int p; | |
2954 | ||
2955 | /* PSRTYPE must be initialized in non 82598 adapters */ | |
2956 | u32 psrtype = IXGBE_PSRTYPE_TCPHDR | | |
e8e9f696 JP |
2957 | IXGBE_PSRTYPE_UDPHDR | |
2958 | IXGBE_PSRTYPE_IPV4HDR | | |
48654521 | 2959 | IXGBE_PSRTYPE_L2HDR | |
e8e9f696 | 2960 | IXGBE_PSRTYPE_IPV6HDR; |
48654521 AD |
2961 | |
2962 | if (hw->mac.type == ixgbe_mac_82598EB) | |
2963 | return; | |
2964 | ||
2965 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) | |
2966 | psrtype |= (adapter->num_rx_queues_per_pool << 29); | |
2967 | ||
2968 | for (p = 0; p < adapter->num_rx_pools; p++) | |
2969 | IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p), | |
2970 | psrtype); | |
2971 | } | |
2972 | ||
f5b4a52e AD |
2973 | static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter) |
2974 | { | |
2975 | struct ixgbe_hw *hw = &adapter->hw; | |
2976 | u32 gcr_ext; | |
2977 | u32 vt_reg_bits; | |
2978 | u32 reg_offset, vf_shift; | |
2979 | u32 vmdctl; | |
de4c7f65 | 2980 | int i; |
f5b4a52e AD |
2981 | |
2982 | if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) | |
2983 | return; | |
2984 | ||
2985 | vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL); | |
2986 | vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN; | |
2987 | vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT); | |
2988 | IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits); | |
2989 | ||
2990 | vf_shift = adapter->num_vfs % 32; | |
4cd6923d | 2991 | reg_offset = (adapter->num_vfs >= 32) ? 1 : 0; |
f5b4a52e AD |
2992 | |
2993 | /* Enable only the PF's pool for Tx/Rx */ | |
2994 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift)); | |
2995 | IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0); | |
2996 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift)); | |
2997 | IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0); | |
2998 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
2999 | ||
3000 | /* Map PF MAC address in RAR Entry 0 to first pool following VFs */ | |
3001 | hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs); | |
3002 | ||
3003 | /* | |
3004 | * Set up VF register offsets for selected VT Mode, | |
3005 | * i.e. 32 or 64 VFs for SR-IOV | |
3006 | */ | |
3007 | gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); | |
3008 | gcr_ext |= IXGBE_GCR_EXT_MSIX_EN; | |
3009 | gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64; | |
3010 | IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); | |
3011 | ||
3012 | /* enable Tx loopback for VF/PF communication */ | |
3013 | IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN); | |
a985b6c3 | 3014 | /* Enable MAC Anti-Spoofing */ |
a1cbb15c | 3015 | hw->mac.ops.set_mac_anti_spoofing(hw, |
de4c7f65 | 3016 | (adapter->num_vfs != 0), |
a985b6c3 | 3017 | adapter->num_vfs); |
de4c7f65 GR |
3018 | /* For VFs that have spoof checking turned off */ |
3019 | for (i = 0; i < adapter->num_vfs; i++) { | |
3020 | if (!adapter->vfinfo[i].spoofchk_enabled) | |
3021 | ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i, false); | |
3022 | } | |
f5b4a52e AD |
3023 | } |
3024 | ||
477de6ed | 3025 | static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter) |
9a799d71 | 3026 | { |
9a799d71 AK |
3027 | struct ixgbe_hw *hw = &adapter->hw; |
3028 | struct net_device *netdev = adapter->netdev; | |
3029 | int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
477de6ed AD |
3030 | struct ixgbe_ring *rx_ring; |
3031 | int i; | |
3032 | u32 mhadd, hlreg0; | |
48654521 | 3033 | |
63f39bd1 | 3034 | #ifdef IXGBE_FCOE |
477de6ed AD |
3035 | /* adjust max frame to be able to do baby jumbo for FCoE */ |
3036 | if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) && | |
3037 | (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE)) | |
3038 | max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
9a799d71 | 3039 | |
477de6ed AD |
3040 | #endif /* IXGBE_FCOE */ |
3041 | mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD); | |
3042 | if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) { | |
3043 | mhadd &= ~IXGBE_MHADD_MFS_MASK; | |
3044 | mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT; | |
3045 | ||
3046 | IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd); | |
3047 | } | |
3048 | ||
919e78a6 AD |
3049 | /* MHADD will allow an extra 4 bytes past for vlan tagged frames */ |
3050 | max_frame += VLAN_HLEN; | |
3051 | ||
477de6ed AD |
3052 | hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); |
3053 | /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */ | |
3054 | hlreg0 |= IXGBE_HLREG0_JUMBOEN; | |
3055 | IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); | |
9a799d71 | 3056 | |
0cefafad JB |
3057 | /* |
3058 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3059 | * the Base and Length of the Rx Descriptor Ring | |
3060 | */ | |
9a799d71 | 3061 | for (i = 0; i < adapter->num_rx_queues; i++) { |
4a0b9ca0 | 3062 | rx_ring = adapter->rx_ring[i]; |
7d637bcc AD |
3063 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
3064 | set_ring_rsc_enabled(rx_ring); | |
1b3ff02e | 3065 | else |
7d637bcc | 3066 | clear_ring_rsc_enabled(rx_ring); |
63f39bd1 | 3067 | #ifdef IXGBE_FCOE |
e8e9f696 | 3068 | if (netdev->features & NETIF_F_FCOE_MTU) { |
63f39bd1 YZ |
3069 | struct ixgbe_ring_feature *f; |
3070 | f = &adapter->ring_feature[RING_F_FCOE]; | |
f800326d AD |
3071 | if ((i >= f->mask) && (i < f->mask + f->indices)) |
3072 | set_bit(__IXGBE_RX_FCOE_BUFSZ, &rx_ring->state); | |
63f39bd1 | 3073 | } |
63f39bd1 | 3074 | #endif /* IXGBE_FCOE */ |
477de6ed | 3075 | } |
477de6ed AD |
3076 | } |
3077 | ||
7367096a AD |
3078 | static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter) |
3079 | { | |
3080 | struct ixgbe_hw *hw = &adapter->hw; | |
3081 | u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); | |
3082 | ||
3083 | switch (hw->mac.type) { | |
3084 | case ixgbe_mac_82598EB: | |
3085 | /* | |
3086 | * For VMDq support of different descriptor types or | |
3087 | * buffer sizes through the use of multiple SRRCTL | |
3088 | * registers, RDRXCTL.MVMEN must be set to 1 | |
3089 | * | |
3090 | * also, the manual doesn't mention it clearly but DCA hints | |
3091 | * will only use queue 0's tags unless this bit is set. Side | |
3092 | * effects of setting this bit are only that SRRCTL must be | |
3093 | * fully programmed [0..15] | |
3094 | */ | |
3095 | rdrxctl |= IXGBE_RDRXCTL_MVMEN; | |
3096 | break; | |
3097 | case ixgbe_mac_82599EB: | |
b93a2226 | 3098 | case ixgbe_mac_X540: |
7367096a AD |
3099 | /* Disable RSC for ACK packets */ |
3100 | IXGBE_WRITE_REG(hw, IXGBE_RSCDBU, | |
3101 | (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU))); | |
3102 | rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE; | |
3103 | /* hardware requires some bits to be set by default */ | |
3104 | rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX); | |
3105 | rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP; | |
3106 | break; | |
3107 | default: | |
3108 | /* We should do nothing since we don't know this hardware */ | |
3109 | return; | |
3110 | } | |
3111 | ||
3112 | IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl); | |
3113 | } | |
3114 | ||
477de6ed AD |
3115 | /** |
3116 | * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset | |
3117 | * @adapter: board private structure | |
3118 | * | |
3119 | * Configure the Rx unit of the MAC after a reset. | |
3120 | **/ | |
3121 | static void ixgbe_configure_rx(struct ixgbe_adapter *adapter) | |
3122 | { | |
3123 | struct ixgbe_hw *hw = &adapter->hw; | |
477de6ed AD |
3124 | int i; |
3125 | u32 rxctrl; | |
477de6ed AD |
3126 | |
3127 | /* disable receives while setting up the descriptors */ | |
3128 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); | |
3129 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
3130 | ||
3131 | ixgbe_setup_psrtype(adapter); | |
7367096a | 3132 | ixgbe_setup_rdrxctl(adapter); |
477de6ed | 3133 | |
9e10e045 | 3134 | /* Program registers for the distribution of queues */ |
f5b4a52e | 3135 | ixgbe_setup_mrqc(adapter); |
f5b4a52e | 3136 | |
9e10e045 AD |
3137 | ixgbe_set_uta(adapter); |
3138 | ||
477de6ed AD |
3139 | /* set_rx_buffer_len must be called before ring initialization */ |
3140 | ixgbe_set_rx_buffer_len(adapter); | |
3141 | ||
3142 | /* | |
3143 | * Setup the HW Rx Head and Tail Descriptor Pointers and | |
3144 | * the Base and Length of the Rx Descriptor Ring | |
3145 | */ | |
9e10e045 AD |
3146 | for (i = 0; i < adapter->num_rx_queues; i++) |
3147 | ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]); | |
177db6ff | 3148 | |
9e10e045 AD |
3149 | /* disable drop enable for 82598 parts */ |
3150 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3151 | rxctrl |= IXGBE_RXCTRL_DMBYPS; | |
3152 | ||
3153 | /* enable all receives */ | |
3154 | rxctrl |= IXGBE_RXCTRL_RXEN; | |
3155 | hw->mac.ops.enable_rx_dma(hw, rxctrl); | |
9a799d71 AK |
3156 | } |
3157 | ||
8e586137 | 3158 | static int ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3159 | { |
3160 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3161 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3162 | int pool_ndx = adapter->num_vfs; |
068c89b0 DS |
3163 | |
3164 | /* add VID to filter table */ | |
1ada1b1b | 3165 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true); |
f62bbb5e | 3166 | set_bit(vid, adapter->active_vlans); |
8e586137 JP |
3167 | |
3168 | return 0; | |
068c89b0 DS |
3169 | } |
3170 | ||
8e586137 | 3171 | static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) |
068c89b0 DS |
3172 | { |
3173 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3174 | struct ixgbe_hw *hw = &adapter->hw; | |
1ada1b1b | 3175 | int pool_ndx = adapter->num_vfs; |
068c89b0 | 3176 | |
068c89b0 | 3177 | /* remove VID from filter table */ |
1ada1b1b | 3178 | hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false); |
f62bbb5e | 3179 | clear_bit(vid, adapter->active_vlans); |
8e586137 JP |
3180 | |
3181 | return 0; | |
068c89b0 DS |
3182 | } |
3183 | ||
5f6c0181 JB |
3184 | /** |
3185 | * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering | |
3186 | * @adapter: driver data | |
3187 | */ | |
3188 | static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter) | |
3189 | { | |
3190 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e JG |
3191 | u32 vlnctrl; |
3192 | ||
3193 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3194 | vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN); | |
3195 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3196 | } | |
3197 | ||
3198 | /** | |
3199 | * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering | |
3200 | * @adapter: driver data | |
3201 | */ | |
3202 | static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter) | |
3203 | { | |
3204 | struct ixgbe_hw *hw = &adapter->hw; | |
3205 | u32 vlnctrl; | |
3206 | ||
3207 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); | |
3208 | vlnctrl |= IXGBE_VLNCTRL_VFE; | |
3209 | vlnctrl &= ~IXGBE_VLNCTRL_CFIEN; | |
3210 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); | |
3211 | } | |
3212 | ||
3213 | /** | |
3214 | * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping | |
3215 | * @adapter: driver data | |
3216 | */ | |
3217 | static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter) | |
3218 | { | |
3219 | struct ixgbe_hw *hw = &adapter->hw; | |
3220 | u32 vlnctrl; | |
5f6c0181 JB |
3221 | int i, j; |
3222 | ||
3223 | switch (hw->mac.type) { | |
3224 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3225 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3226 | vlnctrl &= ~IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3227 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3228 | break; | |
3229 | case ixgbe_mac_82599EB: | |
b93a2226 | 3230 | case ixgbe_mac_X540: |
5f6c0181 JB |
3231 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3232 | j = adapter->rx_ring[i]->reg_idx; | |
3233 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3234 | vlnctrl &= ~IXGBE_RXDCTL_VME; | |
3235 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3236 | } | |
3237 | break; | |
3238 | default: | |
3239 | break; | |
3240 | } | |
3241 | } | |
3242 | ||
3243 | /** | |
f62bbb5e | 3244 | * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping |
5f6c0181 JB |
3245 | * @adapter: driver data |
3246 | */ | |
f62bbb5e | 3247 | static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter) |
5f6c0181 JB |
3248 | { |
3249 | struct ixgbe_hw *hw = &adapter->hw; | |
f62bbb5e | 3250 | u32 vlnctrl; |
5f6c0181 JB |
3251 | int i, j; |
3252 | ||
3253 | switch (hw->mac.type) { | |
3254 | case ixgbe_mac_82598EB: | |
f62bbb5e JG |
3255 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL); |
3256 | vlnctrl |= IXGBE_VLNCTRL_VME; | |
5f6c0181 JB |
3257 | IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl); |
3258 | break; | |
3259 | case ixgbe_mac_82599EB: | |
b93a2226 | 3260 | case ixgbe_mac_X540: |
5f6c0181 JB |
3261 | for (i = 0; i < adapter->num_rx_queues; i++) { |
3262 | j = adapter->rx_ring[i]->reg_idx; | |
3263 | vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j)); | |
3264 | vlnctrl |= IXGBE_RXDCTL_VME; | |
3265 | IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl); | |
3266 | } | |
3267 | break; | |
3268 | default: | |
3269 | break; | |
3270 | } | |
3271 | } | |
3272 | ||
9a799d71 AK |
3273 | static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter) |
3274 | { | |
f62bbb5e | 3275 | u16 vid; |
9a799d71 | 3276 | |
f62bbb5e JG |
3277 | ixgbe_vlan_rx_add_vid(adapter->netdev, 0); |
3278 | ||
3279 | for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) | |
3280 | ixgbe_vlan_rx_add_vid(adapter->netdev, vid); | |
9a799d71 AK |
3281 | } |
3282 | ||
2850062a AD |
3283 | /** |
3284 | * ixgbe_write_uc_addr_list - write unicast addresses to RAR table | |
3285 | * @netdev: network interface device structure | |
3286 | * | |
3287 | * Writes unicast address list to the RAR table. | |
3288 | * Returns: -ENOMEM on failure/insufficient address space | |
3289 | * 0 on no addresses written | |
3290 | * X on writing X addresses to the RAR table | |
3291 | **/ | |
3292 | static int ixgbe_write_uc_addr_list(struct net_device *netdev) | |
3293 | { | |
3294 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3295 | struct ixgbe_hw *hw = &adapter->hw; | |
3296 | unsigned int vfn = adapter->num_vfs; | |
a1cbb15c | 3297 | unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS; |
2850062a AD |
3298 | int count = 0; |
3299 | ||
3300 | /* return ENOMEM indicating insufficient memory for addresses */ | |
3301 | if (netdev_uc_count(netdev) > rar_entries) | |
3302 | return -ENOMEM; | |
3303 | ||
3304 | if (!netdev_uc_empty(netdev) && rar_entries) { | |
3305 | struct netdev_hw_addr *ha; | |
3306 | /* return error if we do not support writing to RAR table */ | |
3307 | if (!hw->mac.ops.set_rar) | |
3308 | return -ENOMEM; | |
3309 | ||
3310 | netdev_for_each_uc_addr(ha, netdev) { | |
3311 | if (!rar_entries) | |
3312 | break; | |
3313 | hw->mac.ops.set_rar(hw, rar_entries--, ha->addr, | |
3314 | vfn, IXGBE_RAH_AV); | |
3315 | count++; | |
3316 | } | |
3317 | } | |
3318 | /* write the addresses in reverse order to avoid write combining */ | |
3319 | for (; rar_entries > 0 ; rar_entries--) | |
3320 | hw->mac.ops.clear_rar(hw, rar_entries); | |
3321 | ||
3322 | return count; | |
3323 | } | |
3324 | ||
9a799d71 | 3325 | /** |
2c5645cf | 3326 | * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set |
9a799d71 AK |
3327 | * @netdev: network interface device structure |
3328 | * | |
2c5645cf CL |
3329 | * The set_rx_method entry point is called whenever the unicast/multicast |
3330 | * address list or the network interface flags are updated. This routine is | |
3331 | * responsible for configuring the hardware for proper unicast, multicast and | |
3332 | * promiscuous mode. | |
9a799d71 | 3333 | **/ |
7f870475 | 3334 | void ixgbe_set_rx_mode(struct net_device *netdev) |
9a799d71 AK |
3335 | { |
3336 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3337 | struct ixgbe_hw *hw = &adapter->hw; | |
2850062a AD |
3338 | u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE; |
3339 | int count; | |
9a799d71 AK |
3340 | |
3341 | /* Check for Promiscuous and All Multicast modes */ | |
3342 | ||
3343 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
3344 | ||
f5dc442b | 3345 | /* set all bits that we expect to always be set */ |
3f2d1c0f | 3346 | fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */ |
f5dc442b AD |
3347 | fctrl |= IXGBE_FCTRL_BAM; |
3348 | fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */ | |
3349 | fctrl |= IXGBE_FCTRL_PMCF; | |
3350 | ||
2850062a AD |
3351 | /* clear the bits we are changing the status of */ |
3352 | fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); | |
3353 | ||
9a799d71 | 3354 | if (netdev->flags & IFF_PROMISC) { |
e433ea1f | 3355 | hw->addr_ctrl.user_set_promisc = true; |
9a799d71 | 3356 | fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE); |
2850062a | 3357 | vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE); |
5f6c0181 JB |
3358 | /* don't hardware filter vlans in promisc mode */ |
3359 | ixgbe_vlan_filter_disable(adapter); | |
9a799d71 | 3360 | } else { |
746b9f02 PM |
3361 | if (netdev->flags & IFF_ALLMULTI) { |
3362 | fctrl |= IXGBE_FCTRL_MPE; | |
2850062a AD |
3363 | vmolr |= IXGBE_VMOLR_MPE; |
3364 | } else { | |
3365 | /* | |
3366 | * Write addresses to the MTA, if the attempt fails | |
25985edc | 3367 | * then we should just turn on promiscuous mode so |
2850062a AD |
3368 | * that we can at least receive multicast traffic |
3369 | */ | |
3370 | hw->mac.ops.update_mc_addr_list(hw, netdev); | |
3371 | vmolr |= IXGBE_VMOLR_ROMPE; | |
746b9f02 | 3372 | } |
5f6c0181 | 3373 | ixgbe_vlan_filter_enable(adapter); |
e433ea1f | 3374 | hw->addr_ctrl.user_set_promisc = false; |
2850062a AD |
3375 | /* |
3376 | * Write addresses to available RAR registers, if there is not | |
3377 | * sufficient space to store all the addresses then enable | |
25985edc | 3378 | * unicast promiscuous mode |
2850062a AD |
3379 | */ |
3380 | count = ixgbe_write_uc_addr_list(netdev); | |
3381 | if (count < 0) { | |
3382 | fctrl |= IXGBE_FCTRL_UPE; | |
3383 | vmolr |= IXGBE_VMOLR_ROPE; | |
3384 | } | |
9a799d71 AK |
3385 | } |
3386 | ||
2850062a | 3387 | if (adapter->num_vfs) { |
1cdd1ec8 | 3388 | ixgbe_restore_vf_multicasts(adapter); |
2850062a AD |
3389 | vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) & |
3390 | ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE | | |
3391 | IXGBE_VMOLR_ROPE); | |
3392 | IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr); | |
3393 | } | |
3394 | ||
3f2d1c0f BG |
3395 | /* This is useful for sniffing bad packets. */ |
3396 | if (adapter->netdev->features & NETIF_F_RXALL) { | |
3397 | /* UPE and MPE will be handled by normal PROMISC logic | |
3398 | * in e1000e_set_rx_mode */ | |
3399 | fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */ | |
3400 | IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */ | |
3401 | IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */ | |
3402 | ||
3403 | fctrl &= ~(IXGBE_FCTRL_DPF); | |
3404 | /* NOTE: VLAN filtering is disabled by setting PROMISC */ | |
3405 | } | |
3406 | ||
2850062a | 3407 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); |
f62bbb5e JG |
3408 | |
3409 | if (netdev->features & NETIF_F_HW_VLAN_RX) | |
3410 | ixgbe_vlan_strip_enable(adapter); | |
3411 | else | |
3412 | ixgbe_vlan_strip_disable(adapter); | |
9a799d71 AK |
3413 | } |
3414 | ||
021230d4 AV |
3415 | static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter) |
3416 | { | |
3417 | int q_idx; | |
3418 | struct ixgbe_q_vector *q_vector; | |
3419 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3420 | ||
3421 | /* legacy and MSI only use one vector */ | |
3422 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3423 | q_vectors = 1; | |
3424 | ||
3425 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3426 | q_vector = adapter->q_vector[q_idx]; |
4ff7fb12 | 3427 | napi_enable(&q_vector->napi); |
021230d4 AV |
3428 | } |
3429 | } | |
3430 | ||
3431 | static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter) | |
3432 | { | |
3433 | int q_idx; | |
3434 | struct ixgbe_q_vector *q_vector; | |
3435 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
3436 | ||
3437 | /* legacy and MSI only use one vector */ | |
3438 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
3439 | q_vectors = 1; | |
3440 | ||
3441 | for (q_idx = 0; q_idx < q_vectors; q_idx++) { | |
7a921c93 | 3442 | q_vector = adapter->q_vector[q_idx]; |
021230d4 AV |
3443 | napi_disable(&q_vector->napi); |
3444 | } | |
3445 | } | |
3446 | ||
7a6b6f51 | 3447 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
3448 | /* |
3449 | * ixgbe_configure_dcb - Configure DCB hardware | |
3450 | * @adapter: ixgbe adapter struct | |
3451 | * | |
3452 | * This is called by the driver on open to configure the DCB hardware. | |
3453 | * This is also called by the gennetlink interface when reconfiguring | |
3454 | * the DCB state. | |
3455 | */ | |
3456 | static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter) | |
3457 | { | |
3458 | struct ixgbe_hw *hw = &adapter->hw; | |
9806307a | 3459 | int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN; |
2f90b865 | 3460 | |
67ebd791 AD |
3461 | if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) { |
3462 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3463 | netif_set_gso_max_size(adapter->netdev, 65536); | |
3464 | return; | |
3465 | } | |
3466 | ||
3467 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3468 | netif_set_gso_max_size(adapter->netdev, 32768); | |
3469 | ||
2f90b865 | 3470 | |
2f90b865 | 3471 | /* Enable VLAN tag insert/strip */ |
f62bbb5e | 3472 | adapter->netdev->features |= NETIF_F_HW_VLAN_RX; |
5f6c0181 | 3473 | |
2f90b865 | 3474 | hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true); |
01fa7d90 | 3475 | |
971060b1 | 3476 | #ifdef IXGBE_FCOE |
b120818e JF |
3477 | if (adapter->netdev->features & NETIF_F_FCOE_MTU) |
3478 | max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE); | |
c27931da | 3479 | #endif |
b120818e JF |
3480 | |
3481 | /* reconfigure the hardware */ | |
3482 | if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) { | |
c27931da JF |
3483 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, |
3484 | DCB_TX_CONFIG); | |
3485 | ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame, | |
3486 | DCB_RX_CONFIG); | |
3487 | ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg); | |
b120818e JF |
3488 | } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) { |
3489 | ixgbe_dcb_hw_ets(&adapter->hw, | |
3490 | adapter->ixgbe_ieee_ets, | |
3491 | max_frame); | |
3492 | ixgbe_dcb_hw_pfc_config(&adapter->hw, | |
3493 | adapter->ixgbe_ieee_pfc->pfc_en, | |
3494 | adapter->ixgbe_ieee_ets->prio_tc); | |
c27931da | 3495 | } |
8187cd48 JF |
3496 | |
3497 | /* Enable RSS Hash per TC */ | |
3498 | if (hw->mac.type != ixgbe_mac_82598EB) { | |
3499 | int i; | |
3500 | u32 reg = 0; | |
3501 | ||
3502 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
3503 | u8 msb = 0; | |
3504 | u8 cnt = adapter->netdev->tc_to_txq[i].count; | |
3505 | ||
3506 | while (cnt >>= 1) | |
3507 | msb++; | |
3508 | ||
3509 | reg |= msb << IXGBE_RQTC_SHIFT_TC(i); | |
3510 | } | |
3511 | IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg); | |
3512 | } | |
2f90b865 | 3513 | } |
9da712d2 JF |
3514 | #endif |
3515 | ||
3516 | /* Additional bittime to account for IXGBE framing */ | |
3517 | #define IXGBE_ETH_FRAMING 20 | |
3518 | ||
3519 | /* | |
3520 | * ixgbe_hpbthresh - calculate high water mark for flow control | |
3521 | * | |
3522 | * @adapter: board private structure to calculate for | |
3523 | * @pb - packet buffer to calculate | |
3524 | */ | |
3525 | static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb) | |
3526 | { | |
3527 | struct ixgbe_hw *hw = &adapter->hw; | |
3528 | struct net_device *dev = adapter->netdev; | |
3529 | int link, tc, kb, marker; | |
3530 | u32 dv_id, rx_pba; | |
3531 | ||
3532 | /* Calculate max LAN frame size */ | |
3533 | tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING; | |
3534 | ||
3535 | #ifdef IXGBE_FCOE | |
3536 | /* FCoE traffic class uses FCOE jumbo frames */ | |
3537 | if (dev->features & NETIF_F_FCOE_MTU) { | |
3538 | int fcoe_pb = 0; | |
2f90b865 | 3539 | |
9da712d2 JF |
3540 | #ifdef CONFIG_IXGBE_DCB |
3541 | fcoe_pb = netdev_get_prio_tc_map(dev, adapter->fcoe.up); | |
3542 | ||
3543 | #endif | |
3544 | if (fcoe_pb == pb && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE) | |
3545 | tc = IXGBE_FCOE_JUMBO_FRAME_SIZE; | |
3546 | } | |
2f90b865 | 3547 | #endif |
80605c65 | 3548 | |
9da712d2 JF |
3549 | /* Calculate delay value for device */ |
3550 | switch (hw->mac.type) { | |
3551 | case ixgbe_mac_X540: | |
3552 | dv_id = IXGBE_DV_X540(link, tc); | |
3553 | break; | |
3554 | default: | |
3555 | dv_id = IXGBE_DV(link, tc); | |
3556 | break; | |
3557 | } | |
3558 | ||
3559 | /* Loopback switch introduces additional latency */ | |
3560 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3561 | dv_id += IXGBE_B2BT(tc); | |
3562 | ||
3563 | /* Delay value is calculated in bit times convert to KB */ | |
3564 | kb = IXGBE_BT2KB(dv_id); | |
3565 | rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10; | |
3566 | ||
3567 | marker = rx_pba - kb; | |
3568 | ||
3569 | /* It is possible that the packet buffer is not large enough | |
3570 | * to provide required headroom. In this case throw an error | |
3571 | * to user and a do the best we can. | |
3572 | */ | |
3573 | if (marker < 0) { | |
3574 | e_warn(drv, "Packet Buffer(%i) can not provide enough" | |
3575 | "headroom to support flow control." | |
3576 | "Decrease MTU or number of traffic classes\n", pb); | |
3577 | marker = tc + 1; | |
3578 | } | |
3579 | ||
3580 | return marker; | |
3581 | } | |
3582 | ||
3583 | /* | |
3584 | * ixgbe_lpbthresh - calculate low water mark for for flow control | |
3585 | * | |
3586 | * @adapter: board private structure to calculate for | |
3587 | * @pb - packet buffer to calculate | |
3588 | */ | |
3589 | static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter) | |
3590 | { | |
3591 | struct ixgbe_hw *hw = &adapter->hw; | |
3592 | struct net_device *dev = adapter->netdev; | |
3593 | int tc; | |
3594 | u32 dv_id; | |
3595 | ||
3596 | /* Calculate max LAN frame size */ | |
3597 | tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; | |
3598 | ||
3599 | /* Calculate delay value for device */ | |
3600 | switch (hw->mac.type) { | |
3601 | case ixgbe_mac_X540: | |
3602 | dv_id = IXGBE_LOW_DV_X540(tc); | |
3603 | break; | |
3604 | default: | |
3605 | dv_id = IXGBE_LOW_DV(tc); | |
3606 | break; | |
3607 | } | |
3608 | ||
3609 | /* Delay value is calculated in bit times convert to KB */ | |
3610 | return IXGBE_BT2KB(dv_id); | |
3611 | } | |
3612 | ||
3613 | /* | |
3614 | * ixgbe_pbthresh_setup - calculate and setup high low water marks | |
3615 | */ | |
3616 | static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter) | |
3617 | { | |
3618 | struct ixgbe_hw *hw = &adapter->hw; | |
3619 | int num_tc = netdev_get_num_tc(adapter->netdev); | |
3620 | int i; | |
3621 | ||
3622 | if (!num_tc) | |
3623 | num_tc = 1; | |
3624 | ||
3625 | hw->fc.low_water = ixgbe_lpbthresh(adapter); | |
3626 | ||
3627 | for (i = 0; i < num_tc; i++) { | |
3628 | hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i); | |
3629 | ||
3630 | /* Low water marks must not be larger than high water marks */ | |
3631 | if (hw->fc.low_water > hw->fc.high_water[i]) | |
3632 | hw->fc.low_water = 0; | |
3633 | } | |
3634 | } | |
3635 | ||
80605c65 JF |
3636 | static void ixgbe_configure_pb(struct ixgbe_adapter *adapter) |
3637 | { | |
80605c65 | 3638 | struct ixgbe_hw *hw = &adapter->hw; |
f7e1027f AD |
3639 | int hdrm; |
3640 | u8 tc = netdev_get_num_tc(adapter->netdev); | |
80605c65 JF |
3641 | |
3642 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE || | |
3643 | adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) | |
f7e1027f AD |
3644 | hdrm = 32 << adapter->fdir_pballoc; |
3645 | else | |
3646 | hdrm = 0; | |
80605c65 | 3647 | |
f7e1027f | 3648 | hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL); |
9da712d2 | 3649 | ixgbe_pbthresh_setup(adapter); |
80605c65 JF |
3650 | } |
3651 | ||
e4911d57 AD |
3652 | static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter) |
3653 | { | |
3654 | struct ixgbe_hw *hw = &adapter->hw; | |
3655 | struct hlist_node *node, *node2; | |
3656 | struct ixgbe_fdir_filter *filter; | |
3657 | ||
3658 | spin_lock(&adapter->fdir_perfect_lock); | |
3659 | ||
3660 | if (!hlist_empty(&adapter->fdir_filter_list)) | |
3661 | ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask); | |
3662 | ||
3663 | hlist_for_each_entry_safe(filter, node, node2, | |
3664 | &adapter->fdir_filter_list, fdir_node) { | |
3665 | ixgbe_fdir_write_perfect_filter_82599(hw, | |
1f4d5183 AD |
3666 | &filter->filter, |
3667 | filter->sw_idx, | |
3668 | (filter->action == IXGBE_FDIR_DROP_QUEUE) ? | |
3669 | IXGBE_FDIR_DROP_QUEUE : | |
3670 | adapter->rx_ring[filter->action]->reg_idx); | |
e4911d57 AD |
3671 | } |
3672 | ||
3673 | spin_unlock(&adapter->fdir_perfect_lock); | |
3674 | } | |
3675 | ||
9a799d71 AK |
3676 | static void ixgbe_configure(struct ixgbe_adapter *adapter) |
3677 | { | |
d2f5e7f3 AS |
3678 | struct ixgbe_hw *hw = &adapter->hw; |
3679 | ||
80605c65 | 3680 | ixgbe_configure_pb(adapter); |
7a6b6f51 | 3681 | #ifdef CONFIG_IXGBE_DCB |
67ebd791 | 3682 | ixgbe_configure_dcb(adapter); |
2f90b865 | 3683 | #endif |
9a799d71 | 3684 | |
4c1d7b4b | 3685 | ixgbe_set_rx_mode(adapter->netdev); |
f62bbb5e JG |
3686 | ixgbe_restore_vlan(adapter); |
3687 | ||
eacd73f7 YZ |
3688 | #ifdef IXGBE_FCOE |
3689 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
3690 | ixgbe_configure_fcoe(adapter); | |
3691 | ||
3692 | #endif /* IXGBE_FCOE */ | |
d2f5e7f3 AS |
3693 | |
3694 | switch (hw->mac.type) { | |
3695 | case ixgbe_mac_82599EB: | |
3696 | case ixgbe_mac_X540: | |
3697 | hw->mac.ops.disable_rx_buff(hw); | |
3698 | break; | |
3699 | default: | |
3700 | break; | |
3701 | } | |
3702 | ||
c4cf55e5 | 3703 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
4c1d7b4b AD |
3704 | ixgbe_init_fdir_signature_82599(&adapter->hw, |
3705 | adapter->fdir_pballoc); | |
e4911d57 AD |
3706 | } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) { |
3707 | ixgbe_init_fdir_perfect_82599(&adapter->hw, | |
3708 | adapter->fdir_pballoc); | |
3709 | ixgbe_fdir_filter_restore(adapter); | |
c4cf55e5 | 3710 | } |
4c1d7b4b | 3711 | |
d2f5e7f3 AS |
3712 | switch (hw->mac.type) { |
3713 | case ixgbe_mac_82599EB: | |
3714 | case ixgbe_mac_X540: | |
3715 | hw->mac.ops.enable_rx_buff(hw); | |
3716 | break; | |
3717 | default: | |
3718 | break; | |
3719 | } | |
3720 | ||
933d41f1 | 3721 | ixgbe_configure_virtualization(adapter); |
c4cf55e5 | 3722 | |
9a799d71 AK |
3723 | ixgbe_configure_tx(adapter); |
3724 | ixgbe_configure_rx(adapter); | |
9a799d71 AK |
3725 | } |
3726 | ||
e8e26350 PW |
3727 | static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw) |
3728 | { | |
3729 | switch (hw->phy.type) { | |
3730 | case ixgbe_phy_sfp_avago: | |
3731 | case ixgbe_phy_sfp_ftl: | |
3732 | case ixgbe_phy_sfp_intel: | |
3733 | case ixgbe_phy_sfp_unknown: | |
ea0a04df DS |
3734 | case ixgbe_phy_sfp_passive_tyco: |
3735 | case ixgbe_phy_sfp_passive_unknown: | |
3736 | case ixgbe_phy_sfp_active_unknown: | |
3737 | case ixgbe_phy_sfp_ftl_active: | |
e8e26350 | 3738 | return true; |
8917b447 AD |
3739 | case ixgbe_phy_nl: |
3740 | if (hw->mac.type == ixgbe_mac_82598EB) | |
3741 | return true; | |
e8e26350 PW |
3742 | default: |
3743 | return false; | |
3744 | } | |
3745 | } | |
3746 | ||
0ecc061d | 3747 | /** |
e8e26350 PW |
3748 | * ixgbe_sfp_link_config - set up SFP+ link |
3749 | * @adapter: pointer to private adapter struct | |
3750 | **/ | |
3751 | static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter) | |
3752 | { | |
7086400d | 3753 | /* |
52f33af8 | 3754 | * We are assuming the worst case scenario here, and that |
7086400d AD |
3755 | * is that an SFP was inserted/removed after the reset |
3756 | * but before SFP detection was enabled. As such the best | |
3757 | * solution is to just start searching as soon as we start | |
3758 | */ | |
3759 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
3760 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
e8e26350 | 3761 | |
7086400d | 3762 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; |
e8e26350 PW |
3763 | } |
3764 | ||
3765 | /** | |
3766 | * ixgbe_non_sfp_link_config - set up non-SFP+ link | |
0ecc061d PWJ |
3767 | * @hw: pointer to private hardware struct |
3768 | * | |
3769 | * Returns 0 on success, negative on failure | |
3770 | **/ | |
e8e26350 | 3771 | static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw) |
0ecc061d PWJ |
3772 | { |
3773 | u32 autoneg; | |
8620a103 | 3774 | bool negotiation, link_up = false; |
0ecc061d PWJ |
3775 | u32 ret = IXGBE_ERR_LINK_SETUP; |
3776 | ||
3777 | if (hw->mac.ops.check_link) | |
3778 | ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false); | |
3779 | ||
3780 | if (ret) | |
3781 | goto link_cfg_out; | |
3782 | ||
0b0c2b31 ET |
3783 | autoneg = hw->phy.autoneg_advertised; |
3784 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
e8e9f696 JP |
3785 | ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, |
3786 | &negotiation); | |
0ecc061d PWJ |
3787 | if (ret) |
3788 | goto link_cfg_out; | |
3789 | ||
8620a103 MC |
3790 | if (hw->mac.ops.setup_link) |
3791 | ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up); | |
0ecc061d PWJ |
3792 | link_cfg_out: |
3793 | return ret; | |
3794 | } | |
3795 | ||
a34bcfff | 3796 | static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter) |
9a799d71 | 3797 | { |
9a799d71 | 3798 | struct ixgbe_hw *hw = &adapter->hw; |
a34bcfff | 3799 | u32 gpie = 0; |
9a799d71 | 3800 | |
9b471446 | 3801 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
a34bcfff AD |
3802 | gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT | |
3803 | IXGBE_GPIE_OCD; | |
3804 | gpie |= IXGBE_GPIE_EIAME; | |
9b471446 JB |
3805 | /* |
3806 | * use EIAM to auto-mask when MSI-X interrupt is asserted | |
3807 | * this saves a register write for every interrupt | |
3808 | */ | |
3809 | switch (hw->mac.type) { | |
3810 | case ixgbe_mac_82598EB: | |
3811 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3812 | break; | |
9b471446 | 3813 | case ixgbe_mac_82599EB: |
b93a2226 DS |
3814 | case ixgbe_mac_X540: |
3815 | default: | |
9b471446 JB |
3816 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF); |
3817 | IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF); | |
3818 | break; | |
3819 | } | |
3820 | } else { | |
021230d4 AV |
3821 | /* legacy interrupts, use EIAM to auto-mask when reading EICR, |
3822 | * specifically only auto mask tx and rx interrupts */ | |
3823 | IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE); | |
3824 | } | |
9a799d71 | 3825 | |
a34bcfff AD |
3826 | /* XXX: to interrupt immediately for EICS writes, enable this */ |
3827 | /* gpie |= IXGBE_GPIE_EIMEN; */ | |
3828 | ||
3829 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { | |
3830 | gpie &= ~IXGBE_GPIE_VTMODE_MASK; | |
3831 | gpie |= IXGBE_GPIE_VTMODE_64; | |
119fc60a MC |
3832 | } |
3833 | ||
5fdd31f9 | 3834 | /* Enable Thermal over heat sensor interrupt */ |
f3df98ec DS |
3835 | if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) { |
3836 | switch (adapter->hw.mac.type) { | |
3837 | case ixgbe_mac_82599EB: | |
3838 | gpie |= IXGBE_SDP0_GPIEN; | |
3839 | break; | |
3840 | case ixgbe_mac_X540: | |
3841 | gpie |= IXGBE_EIMS_TS; | |
3842 | break; | |
3843 | default: | |
3844 | break; | |
3845 | } | |
3846 | } | |
5fdd31f9 | 3847 | |
a34bcfff AD |
3848 | /* Enable fan failure interrupt */ |
3849 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) | |
0befdb3e | 3850 | gpie |= IXGBE_SDP1_GPIEN; |
0befdb3e | 3851 | |
2698b208 | 3852 | if (hw->mac.type == ixgbe_mac_82599EB) { |
e8e26350 PW |
3853 | gpie |= IXGBE_SDP1_GPIEN; |
3854 | gpie |= IXGBE_SDP2_GPIEN; | |
2698b208 | 3855 | } |
a34bcfff AD |
3856 | |
3857 | IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie); | |
3858 | } | |
3859 | ||
c7ccde0f | 3860 | static void ixgbe_up_complete(struct ixgbe_adapter *adapter) |
a34bcfff AD |
3861 | { |
3862 | struct ixgbe_hw *hw = &adapter->hw; | |
a34bcfff | 3863 | int err; |
a34bcfff AD |
3864 | u32 ctrl_ext; |
3865 | ||
3866 | ixgbe_get_hw_control(adapter); | |
3867 | ixgbe_setup_gpie(adapter); | |
e8e26350 | 3868 | |
9a799d71 AK |
3869 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
3870 | ixgbe_configure_msix(adapter); | |
3871 | else | |
3872 | ixgbe_configure_msi_and_legacy(adapter); | |
3873 | ||
c6ecf39a DS |
3874 | /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */ |
3875 | if (hw->mac.ops.enable_tx_laser && | |
3876 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 3877 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a | 3878 | (hw->mac.type == ixgbe_mac_82599EB)))) |
61fac744 PW |
3879 | hw->mac.ops.enable_tx_laser(hw); |
3880 | ||
9a799d71 | 3881 | clear_bit(__IXGBE_DOWN, &adapter->state); |
021230d4 AV |
3882 | ixgbe_napi_enable_all(adapter); |
3883 | ||
73c4b7cd AD |
3884 | if (ixgbe_is_sfp(hw)) { |
3885 | ixgbe_sfp_link_config(adapter); | |
3886 | } else { | |
3887 | err = ixgbe_non_sfp_link_config(hw); | |
3888 | if (err) | |
3889 | e_err(probe, "link_config FAILED %d\n", err); | |
3890 | } | |
3891 | ||
021230d4 AV |
3892 | /* clear any pending interrupts, may auto mask */ |
3893 | IXGBE_READ_REG(hw, IXGBE_EICR); | |
6af3b9eb | 3894 | ixgbe_irq_enable(adapter, true, true); |
9a799d71 | 3895 | |
bf069c97 DS |
3896 | /* |
3897 | * If this adapter has a fan, check to see if we had a failure | |
3898 | * before we enabled the interrupt. | |
3899 | */ | |
3900 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
3901 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
3902 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 3903 | e_crit(drv, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
3904 | } |
3905 | ||
1da100bb | 3906 | /* enable transmits */ |
477de6ed | 3907 | netif_tx_start_all_queues(adapter->netdev); |
1da100bb | 3908 | |
9a799d71 AK |
3909 | /* bring the link up in the watchdog, this could race with our first |
3910 | * link up interrupt but shouldn't be a problem */ | |
cf8280ee JB |
3911 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; |
3912 | adapter->link_check_timeout = jiffies; | |
7086400d | 3913 | mod_timer(&adapter->service_timer, jiffies); |
c9205697 GR |
3914 | |
3915 | /* Set PF Reset Done bit so PF/VF Mail Ops can work */ | |
3916 | ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); | |
3917 | ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD; | |
3918 | IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); | |
9a799d71 AK |
3919 | } |
3920 | ||
d4f80882 AV |
3921 | void ixgbe_reinit_locked(struct ixgbe_adapter *adapter) |
3922 | { | |
3923 | WARN_ON(in_interrupt()); | |
7086400d AD |
3924 | /* put off any impending NetWatchDogTimeout */ |
3925 | adapter->netdev->trans_start = jiffies; | |
3926 | ||
d4f80882 | 3927 | while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state)) |
032b4325 | 3928 | usleep_range(1000, 2000); |
d4f80882 | 3929 | ixgbe_down(adapter); |
5809a1ae GR |
3930 | /* |
3931 | * If SR-IOV enabled then wait a bit before bringing the adapter | |
3932 | * back up to give the VFs time to respond to the reset. The | |
3933 | * two second wait is based upon the watchdog timer cycle in | |
3934 | * the VF driver. | |
3935 | */ | |
3936 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
3937 | msleep(2000); | |
d4f80882 AV |
3938 | ixgbe_up(adapter); |
3939 | clear_bit(__IXGBE_RESETTING, &adapter->state); | |
3940 | } | |
3941 | ||
c7ccde0f | 3942 | void ixgbe_up(struct ixgbe_adapter *adapter) |
9a799d71 AK |
3943 | { |
3944 | /* hardware has been reset, we need to reload some things */ | |
3945 | ixgbe_configure(adapter); | |
3946 | ||
c7ccde0f | 3947 | ixgbe_up_complete(adapter); |
9a799d71 AK |
3948 | } |
3949 | ||
3950 | void ixgbe_reset(struct ixgbe_adapter *adapter) | |
3951 | { | |
c44ade9e | 3952 | struct ixgbe_hw *hw = &adapter->hw; |
8ca783ab DS |
3953 | int err; |
3954 | ||
7086400d AD |
3955 | /* lock SFP init bit to prevent race conditions with the watchdog */ |
3956 | while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
3957 | usleep_range(1000, 2000); | |
3958 | ||
3959 | /* clear all SFP and link config related flags while holding SFP_INIT */ | |
3960 | adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP | | |
3961 | IXGBE_FLAG2_SFP_NEEDS_RESET); | |
3962 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
3963 | ||
8ca783ab | 3964 | err = hw->mac.ops.init_hw(hw); |
da4dd0f7 PWJ |
3965 | switch (err) { |
3966 | case 0: | |
3967 | case IXGBE_ERR_SFP_NOT_PRESENT: | |
7086400d | 3968 | case IXGBE_ERR_SFP_NOT_SUPPORTED: |
da4dd0f7 PWJ |
3969 | break; |
3970 | case IXGBE_ERR_MASTER_REQUESTS_PENDING: | |
849c4542 | 3971 | e_dev_err("master disable timed out\n"); |
da4dd0f7 | 3972 | break; |
794caeb2 PWJ |
3973 | case IXGBE_ERR_EEPROM_VERSION: |
3974 | /* We are running on a pre-production device, log a warning */ | |
849c4542 | 3975 | e_dev_warn("This device is a pre-production adapter/LOM. " |
52f33af8 | 3976 | "Please be aware there may be issues associated with " |
849c4542 ET |
3977 | "your hardware. If you are experiencing problems " |
3978 | "please contact your Intel or hardware " | |
3979 | "representative who provided you with this " | |
3980 | "hardware.\n"); | |
794caeb2 | 3981 | break; |
da4dd0f7 | 3982 | default: |
849c4542 | 3983 | e_dev_err("Hardware Error: %d\n", err); |
da4dd0f7 | 3984 | } |
9a799d71 | 3985 | |
7086400d AD |
3986 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); |
3987 | ||
9a799d71 | 3988 | /* reprogram the RAR[0] in case user changed it. */ |
1cdd1ec8 GR |
3989 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
3990 | IXGBE_RAH_AV); | |
9a799d71 AK |
3991 | } |
3992 | ||
f800326d AD |
3993 | /** |
3994 | * ixgbe_init_rx_page_offset - initialize page offset values for Rx buffers | |
3995 | * @rx_ring: ring to setup | |
3996 | * | |
3997 | * On many IA platforms the L1 cache has a critical stride of 4K, this | |
3998 | * results in each receive buffer starting in the same cache set. To help | |
3999 | * reduce the pressure on this cache set we can interleave the offsets so | |
4000 | * that only every other buffer will be in the same cache set. | |
4001 | **/ | |
4002 | static void ixgbe_init_rx_page_offset(struct ixgbe_ring *rx_ring) | |
4003 | { | |
4004 | struct ixgbe_rx_buffer *rx_buffer = rx_ring->rx_buffer_info; | |
4005 | u16 i; | |
4006 | ||
4007 | for (i = 0; i < rx_ring->count; i += 2) { | |
4008 | rx_buffer[0].page_offset = 0; | |
4009 | rx_buffer[1].page_offset = ixgbe_rx_bufsz(rx_ring); | |
4010 | rx_buffer = &rx_buffer[2]; | |
4011 | } | |
4012 | } | |
4013 | ||
9a799d71 AK |
4014 | /** |
4015 | * ixgbe_clean_rx_ring - Free Rx Buffers per Queue | |
9a799d71 AK |
4016 | * @rx_ring: ring to free buffers from |
4017 | **/ | |
b6ec895e | 4018 | static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring) |
9a799d71 | 4019 | { |
b6ec895e | 4020 | struct device *dev = rx_ring->dev; |
9a799d71 | 4021 | unsigned long size; |
b6ec895e | 4022 | u16 i; |
9a799d71 | 4023 | |
84418e3b AD |
4024 | /* ring already cleared, nothing to do */ |
4025 | if (!rx_ring->rx_buffer_info) | |
4026 | return; | |
9a799d71 | 4027 | |
84418e3b | 4028 | /* Free all the Rx ring sk_buffs */ |
9a799d71 | 4029 | for (i = 0; i < rx_ring->count; i++) { |
f800326d AD |
4030 | struct ixgbe_rx_buffer *rx_buffer; |
4031 | ||
4032 | rx_buffer = &rx_ring->rx_buffer_info[i]; | |
4033 | if (rx_buffer->skb) { | |
4034 | struct sk_buff *skb = rx_buffer->skb; | |
4035 | if (IXGBE_CB(skb)->page_released) { | |
4036 | dma_unmap_page(dev, | |
4037 | IXGBE_CB(skb)->dma, | |
4038 | ixgbe_rx_bufsz(rx_ring), | |
4039 | DMA_FROM_DEVICE); | |
4040 | IXGBE_CB(skb)->page_released = false; | |
4c1975d7 AD |
4041 | } |
4042 | dev_kfree_skb(skb); | |
9a799d71 | 4043 | } |
f800326d AD |
4044 | rx_buffer->skb = NULL; |
4045 | if (rx_buffer->dma) | |
4046 | dma_unmap_page(dev, rx_buffer->dma, | |
4047 | ixgbe_rx_pg_size(rx_ring), | |
4048 | DMA_FROM_DEVICE); | |
4049 | rx_buffer->dma = 0; | |
4050 | if (rx_buffer->page) | |
4051 | put_page(rx_buffer->page); | |
4052 | rx_buffer->page = NULL; | |
9a799d71 AK |
4053 | } |
4054 | ||
4055 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; | |
4056 | memset(rx_ring->rx_buffer_info, 0, size); | |
4057 | ||
f800326d AD |
4058 | ixgbe_init_rx_page_offset(rx_ring); |
4059 | ||
9a799d71 AK |
4060 | /* Zero out the descriptor ring */ |
4061 | memset(rx_ring->desc, 0, rx_ring->size); | |
4062 | ||
f800326d | 4063 | rx_ring->next_to_alloc = 0; |
9a799d71 AK |
4064 | rx_ring->next_to_clean = 0; |
4065 | rx_ring->next_to_use = 0; | |
9a799d71 AK |
4066 | } |
4067 | ||
4068 | /** | |
4069 | * ixgbe_clean_tx_ring - Free Tx Buffers | |
9a799d71 AK |
4070 | * @tx_ring: ring to be cleaned |
4071 | **/ | |
b6ec895e | 4072 | static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring) |
9a799d71 AK |
4073 | { |
4074 | struct ixgbe_tx_buffer *tx_buffer_info; | |
4075 | unsigned long size; | |
b6ec895e | 4076 | u16 i; |
9a799d71 | 4077 | |
84418e3b AD |
4078 | /* ring already cleared, nothing to do */ |
4079 | if (!tx_ring->tx_buffer_info) | |
4080 | return; | |
9a799d71 | 4081 | |
84418e3b | 4082 | /* Free all the Tx ring sk_buffs */ |
9a799d71 AK |
4083 | for (i = 0; i < tx_ring->count; i++) { |
4084 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
b6ec895e | 4085 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
9a799d71 AK |
4086 | } |
4087 | ||
4088 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; | |
4089 | memset(tx_ring->tx_buffer_info, 0, size); | |
4090 | ||
4091 | /* Zero out the descriptor ring */ | |
4092 | memset(tx_ring->desc, 0, tx_ring->size); | |
4093 | ||
4094 | tx_ring->next_to_use = 0; | |
4095 | tx_ring->next_to_clean = 0; | |
9a799d71 AK |
4096 | } |
4097 | ||
4098 | /** | |
021230d4 | 4099 | * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues |
9a799d71 AK |
4100 | * @adapter: board private structure |
4101 | **/ | |
021230d4 | 4102 | static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4103 | { |
4104 | int i; | |
4105 | ||
021230d4 | 4106 | for (i = 0; i < adapter->num_rx_queues; i++) |
b6ec895e | 4107 | ixgbe_clean_rx_ring(adapter->rx_ring[i]); |
9a799d71 AK |
4108 | } |
4109 | ||
4110 | /** | |
021230d4 | 4111 | * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues |
9a799d71 AK |
4112 | * @adapter: board private structure |
4113 | **/ | |
021230d4 | 4114 | static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter) |
9a799d71 AK |
4115 | { |
4116 | int i; | |
4117 | ||
021230d4 | 4118 | for (i = 0; i < adapter->num_tx_queues; i++) |
b6ec895e | 4119 | ixgbe_clean_tx_ring(adapter->tx_ring[i]); |
9a799d71 AK |
4120 | } |
4121 | ||
e4911d57 AD |
4122 | static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter) |
4123 | { | |
4124 | struct hlist_node *node, *node2; | |
4125 | struct ixgbe_fdir_filter *filter; | |
4126 | ||
4127 | spin_lock(&adapter->fdir_perfect_lock); | |
4128 | ||
4129 | hlist_for_each_entry_safe(filter, node, node2, | |
4130 | &adapter->fdir_filter_list, fdir_node) { | |
4131 | hlist_del(&filter->fdir_node); | |
4132 | kfree(filter); | |
4133 | } | |
4134 | adapter->fdir_filter_count = 0; | |
4135 | ||
4136 | spin_unlock(&adapter->fdir_perfect_lock); | |
4137 | } | |
4138 | ||
9a799d71 AK |
4139 | void ixgbe_down(struct ixgbe_adapter *adapter) |
4140 | { | |
4141 | struct net_device *netdev = adapter->netdev; | |
7f821875 | 4142 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 | 4143 | u32 rxctrl; |
bf29ee6c | 4144 | int i; |
9a799d71 AK |
4145 | |
4146 | /* signal that we are down to the interrupt handler */ | |
4147 | set_bit(__IXGBE_DOWN, &adapter->state); | |
4148 | ||
4149 | /* disable receives */ | |
7f821875 JB |
4150 | rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); |
4151 | IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN); | |
9a799d71 | 4152 | |
2d39d576 YZ |
4153 | /* disable all enabled rx queues */ |
4154 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4155 | /* this call also flushes the previous write */ | |
4156 | ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]); | |
4157 | ||
032b4325 | 4158 | usleep_range(10000, 20000); |
9a799d71 | 4159 | |
7f821875 JB |
4160 | netif_tx_stop_all_queues(netdev); |
4161 | ||
7086400d | 4162 | /* call carrier off first to avoid false dev_watchdog timeouts */ |
c0dfb90e JF |
4163 | netif_carrier_off(netdev); |
4164 | netif_tx_disable(netdev); | |
4165 | ||
4166 | ixgbe_irq_disable(adapter); | |
4167 | ||
4168 | ixgbe_napi_disable_all(adapter); | |
4169 | ||
d034acf1 AD |
4170 | adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT | |
4171 | IXGBE_FLAG2_RESET_REQUESTED); | |
7086400d AD |
4172 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; |
4173 | ||
4174 | del_timer_sync(&adapter->service_timer); | |
4175 | ||
34cecbbf | 4176 | if (adapter->num_vfs) { |
8e34d1aa AD |
4177 | /* Clear EITR Select mapping */ |
4178 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0); | |
34cecbbf AD |
4179 | |
4180 | /* Mark all the VFs as inactive */ | |
4181 | for (i = 0 ; i < adapter->num_vfs; i++) | |
3db1cd5c | 4182 | adapter->vfinfo[i].clear_to_send = false; |
34cecbbf | 4183 | |
34cecbbf AD |
4184 | /* ping all the active vfs to let them know we are going down */ |
4185 | ixgbe_ping_all_vfs(adapter); | |
4186 | ||
4187 | /* Disable all VFTE/VFRE TX/RX */ | |
4188 | ixgbe_disable_tx_rx(adapter); | |
b25ebfd2 PW |
4189 | } |
4190 | ||
7f821875 JB |
4191 | /* disable transmits in the hardware now that interrupts are off */ |
4192 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
bf29ee6c | 4193 | u8 reg_idx = adapter->tx_ring[i]->reg_idx; |
34cecbbf | 4194 | IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); |
7f821875 | 4195 | } |
34cecbbf AD |
4196 | |
4197 | /* Disable the Tx DMA engine on 82599 and X540 */ | |
bd508178 AD |
4198 | switch (hw->mac.type) { |
4199 | case ixgbe_mac_82599EB: | |
b93a2226 | 4200 | case ixgbe_mac_X540: |
88512539 | 4201 | IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, |
e8e9f696 JP |
4202 | (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) & |
4203 | ~IXGBE_DMATXCTL_TE)); | |
bd508178 AD |
4204 | break; |
4205 | default: | |
4206 | break; | |
4207 | } | |
7f821875 | 4208 | |
6f4a0e45 PL |
4209 | if (!pci_channel_offline(adapter->pdev)) |
4210 | ixgbe_reset(adapter); | |
c6ecf39a DS |
4211 | |
4212 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ | |
4213 | if (hw->mac.ops.disable_tx_laser && | |
4214 | ((hw->phy.multispeed_fiber) || | |
9f911707 | 4215 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && |
c6ecf39a DS |
4216 | (hw->mac.type == ixgbe_mac_82599EB)))) |
4217 | hw->mac.ops.disable_tx_laser(hw); | |
4218 | ||
9a799d71 AK |
4219 | ixgbe_clean_all_tx_rings(adapter); |
4220 | ixgbe_clean_all_rx_rings(adapter); | |
4221 | ||
5dd2d332 | 4222 | #ifdef CONFIG_IXGBE_DCA |
96b0e0f6 | 4223 | /* since we reset the hardware DCA settings were cleared */ |
e35ec126 | 4224 | ixgbe_setup_dca(adapter); |
96b0e0f6 | 4225 | #endif |
9a799d71 AK |
4226 | } |
4227 | ||
9a799d71 | 4228 | /** |
021230d4 AV |
4229 | * ixgbe_poll - NAPI Rx polling callback |
4230 | * @napi: structure for representing this polling device | |
4231 | * @budget: how many packets driver is allowed to clean | |
4232 | * | |
4233 | * This function is used for legacy and MSI, NAPI mode | |
9a799d71 | 4234 | **/ |
021230d4 | 4235 | static int ixgbe_poll(struct napi_struct *napi, int budget) |
9a799d71 | 4236 | { |
9a1a69ad | 4237 | struct ixgbe_q_vector *q_vector = |
e8e9f696 | 4238 | container_of(napi, struct ixgbe_q_vector, napi); |
021230d4 | 4239 | struct ixgbe_adapter *adapter = q_vector->adapter; |
4ff7fb12 AD |
4240 | struct ixgbe_ring *ring; |
4241 | int per_ring_budget; | |
4242 | bool clean_complete = true; | |
9a799d71 | 4243 | |
5dd2d332 | 4244 | #ifdef CONFIG_IXGBE_DCA |
33cf09c9 AD |
4245 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) |
4246 | ixgbe_update_dca(q_vector); | |
bd0362dd JC |
4247 | #endif |
4248 | ||
a557928e | 4249 | ixgbe_for_each_ring(ring, q_vector->tx) |
4ff7fb12 | 4250 | clean_complete &= !!ixgbe_clean_tx_irq(q_vector, ring); |
9a799d71 | 4251 | |
4ff7fb12 AD |
4252 | /* attempt to distribute budget to each queue fairly, but don't allow |
4253 | * the budget to go below 1 because we'll exit polling */ | |
4254 | if (q_vector->rx.count > 1) | |
4255 | per_ring_budget = max(budget/q_vector->rx.count, 1); | |
4256 | else | |
4257 | per_ring_budget = budget; | |
d2c7ddd6 | 4258 | |
a557928e | 4259 | ixgbe_for_each_ring(ring, q_vector->rx) |
4ff7fb12 AD |
4260 | clean_complete &= ixgbe_clean_rx_irq(q_vector, ring, |
4261 | per_ring_budget); | |
4262 | ||
4263 | /* If all work not completed, return budget and keep polling */ | |
4264 | if (!clean_complete) | |
4265 | return budget; | |
4266 | ||
4267 | /* all work done, exit the polling mode */ | |
4268 | napi_complete(napi); | |
4269 | if (adapter->rx_itr_setting & 1) | |
4270 | ixgbe_set_itr(q_vector); | |
4271 | if (!test_bit(__IXGBE_DOWN, &adapter->state)) | |
4272 | ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx)); | |
4273 | ||
4274 | return 0; | |
9a799d71 AK |
4275 | } |
4276 | ||
4277 | /** | |
4278 | * ixgbe_tx_timeout - Respond to a Tx Hang | |
4279 | * @netdev: network interface device structure | |
4280 | **/ | |
4281 | static void ixgbe_tx_timeout(struct net_device *netdev) | |
4282 | { | |
4283 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
4284 | ||
4285 | /* Do the reset outside of interrupt context */ | |
c83c6cbd | 4286 | ixgbe_tx_timeout_reset(adapter); |
9a799d71 AK |
4287 | } |
4288 | ||
4df10466 JB |
4289 | /** |
4290 | * ixgbe_set_rss_queues: Allocate queues for RSS | |
4291 | * @adapter: board private structure to initialize | |
4292 | * | |
4293 | * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try | |
4294 | * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU. | |
4295 | * | |
4296 | **/ | |
bc97114d PWJ |
4297 | static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter) |
4298 | { | |
4299 | bool ret = false; | |
0cefafad | 4300 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS]; |
bc97114d PWJ |
4301 | |
4302 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { | |
0cefafad JB |
4303 | f->mask = 0xF; |
4304 | adapter->num_rx_queues = f->indices; | |
4305 | adapter->num_tx_queues = f->indices; | |
bc97114d PWJ |
4306 | ret = true; |
4307 | } else { | |
bc97114d | 4308 | ret = false; |
b9804972 JB |
4309 | } |
4310 | ||
bc97114d PWJ |
4311 | return ret; |
4312 | } | |
4313 | ||
c4cf55e5 PWJ |
4314 | /** |
4315 | * ixgbe_set_fdir_queues: Allocate queues for Flow Director | |
4316 | * @adapter: board private structure to initialize | |
4317 | * | |
4318 | * Flow Director is an advanced Rx filter, attempting to get Rx flows back | |
4319 | * to the original CPU that initiated the Tx session. This runs in addition | |
4320 | * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the | |
4321 | * Rx load across CPUs using RSS. | |
4322 | * | |
4323 | **/ | |
e8e9f696 | 4324 | static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4325 | { |
4326 | bool ret = false; | |
4327 | struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR]; | |
4328 | ||
4329 | f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices); | |
4330 | f_fdir->mask = 0; | |
4331 | ||
24ddd967 AD |
4332 | /* |
4333 | * Use RSS in addition to Flow Director to ensure the best | |
4334 | * distribution of flows across cores, even when an FDIR flow | |
4335 | * isn't matched. | |
4336 | */ | |
03ecf91a AD |
4337 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && |
4338 | (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) { | |
c4cf55e5 PWJ |
4339 | adapter->num_tx_queues = f_fdir->indices; |
4340 | adapter->num_rx_queues = f_fdir->indices; | |
4341 | ret = true; | |
4342 | } else { | |
4343 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
c4cf55e5 PWJ |
4344 | } |
4345 | return ret; | |
4346 | } | |
4347 | ||
0331a832 YZ |
4348 | #ifdef IXGBE_FCOE |
4349 | /** | |
4350 | * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE) | |
4351 | * @adapter: board private structure to initialize | |
4352 | * | |
4353 | * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges. | |
4354 | * The ring feature mask is not used as a mask for FCoE, as it can take any 8 | |
4355 | * rx queues out of the max number of rx queues, instead, it is used as the | |
4356 | * index of the first rx queue used by FCoE. | |
4357 | * | |
4358 | **/ | |
4359 | static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter) | |
4360 | { | |
0331a832 YZ |
4361 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
4362 | ||
e5b64635 JF |
4363 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) |
4364 | return false; | |
4365 | ||
3ed69d7e | 4366 | f->indices = min_t(int, num_online_cpus(), f->indices); |
e5b64635 | 4367 | |
e901acd6 JF |
4368 | adapter->num_rx_queues = 1; |
4369 | adapter->num_tx_queues = 1; | |
e5b64635 | 4370 | |
e901acd6 JF |
4371 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
4372 | e_info(probe, "FCoE enabled with RSS\n"); | |
03ecf91a | 4373 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
e901acd6 JF |
4374 | ixgbe_set_fdir_queues(adapter); |
4375 | else | |
4376 | ixgbe_set_rss_queues(adapter); | |
e5b64635 | 4377 | } |
03ecf91a | 4378 | |
e901acd6 JF |
4379 | /* adding FCoE rx rings to the end */ |
4380 | f->mask = adapter->num_rx_queues; | |
4381 | adapter->num_rx_queues += f->indices; | |
4382 | adapter->num_tx_queues += f->indices; | |
0331a832 | 4383 | |
e5b64635 JF |
4384 | return true; |
4385 | } | |
4386 | #endif /* IXGBE_FCOE */ | |
4387 | ||
e901acd6 JF |
4388 | /* Artificial max queue cap per traffic class in DCB mode */ |
4389 | #define DCB_QUEUE_CAP 8 | |
4390 | ||
e5b64635 JF |
4391 | #ifdef CONFIG_IXGBE_DCB |
4392 | static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter) | |
4393 | { | |
e901acd6 JF |
4394 | int per_tc_q, q, i, offset = 0; |
4395 | struct net_device *dev = adapter->netdev; | |
4396 | int tcs = netdev_get_num_tc(dev); | |
e5b64635 | 4397 | |
e901acd6 JF |
4398 | if (!tcs) |
4399 | return false; | |
e5b64635 | 4400 | |
e901acd6 | 4401 | /* Map queue offset and counts onto allocated tx queues */ |
3ed69d7e JB |
4402 | per_tc_q = min_t(unsigned int, dev->num_tx_queues / tcs, DCB_QUEUE_CAP); |
4403 | q = min_t(int, num_online_cpus(), per_tc_q); | |
8b1c0b24 | 4404 | |
8b1c0b24 | 4405 | for (i = 0; i < tcs; i++) { |
e901acd6 JF |
4406 | netdev_set_tc_queue(dev, i, q, offset); |
4407 | offset += q; | |
0331a832 YZ |
4408 | } |
4409 | ||
e901acd6 JF |
4410 | adapter->num_tx_queues = q * tcs; |
4411 | adapter->num_rx_queues = q * tcs; | |
e5b64635 JF |
4412 | |
4413 | #ifdef IXGBE_FCOE | |
e901acd6 JF |
4414 | /* FCoE enabled queues require special configuration indexed |
4415 | * by feature specific indices and mask. Here we map FCoE | |
4416 | * indices onto the DCB queue pairs allowing FCoE to own | |
4417 | * configuration later. | |
e5b64635 | 4418 | */ |
e901acd6 | 4419 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) { |
cdf485be | 4420 | u8 prio_tc[MAX_USER_PRIORITY] = {0}; |
e901acd6 JF |
4421 | int tc; |
4422 | struct ixgbe_ring_feature *f = | |
4423 | &adapter->ring_feature[RING_F_FCOE]; | |
4424 | ||
cdf485be JF |
4425 | ixgbe_dcb_unpack_map(&adapter->dcb_cfg, DCB_TX_CONFIG, prio_tc); |
4426 | tc = prio_tc[adapter->fcoe.up]; | |
e901acd6 JF |
4427 | f->indices = dev->tc_to_txq[tc].count; |
4428 | f->mask = dev->tc_to_txq[tc].offset; | |
4429 | } | |
e5b64635 JF |
4430 | #endif |
4431 | ||
e901acd6 | 4432 | return true; |
0331a832 | 4433 | } |
e5b64635 | 4434 | #endif |
0331a832 | 4435 | |
1cdd1ec8 GR |
4436 | /** |
4437 | * ixgbe_set_sriov_queues: Allocate queues for IOV use | |
4438 | * @adapter: board private structure to initialize | |
4439 | * | |
4440 | * IOV doesn't actually use anything, so just NAK the | |
4441 | * request for now and let the other queue routines | |
4442 | * figure out what to do. | |
4443 | */ | |
4444 | static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter) | |
4445 | { | |
4446 | return false; | |
4447 | } | |
4448 | ||
4df10466 | 4449 | /* |
25985edc | 4450 | * ixgbe_set_num_queues: Allocate queues for device, feature dependent |
4df10466 JB |
4451 | * @adapter: board private structure to initialize |
4452 | * | |
4453 | * This is the top level queue allocation routine. The order here is very | |
4454 | * important, starting with the "most" number of features turned on at once, | |
4455 | * and ending with the smallest set of features. This way large combinations | |
4456 | * can be allocated if they're turned on, and smaller combinations are the | |
4457 | * fallthrough conditions. | |
4458 | * | |
4459 | **/ | |
847f53ff | 4460 | static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter) |
bc97114d | 4461 | { |
1cdd1ec8 GR |
4462 | /* Start with base case */ |
4463 | adapter->num_rx_queues = 1; | |
4464 | adapter->num_tx_queues = 1; | |
4465 | adapter->num_rx_pools = adapter->num_rx_queues; | |
4466 | adapter->num_rx_queues_per_pool = 1; | |
4467 | ||
4468 | if (ixgbe_set_sriov_queues(adapter)) | |
847f53ff | 4469 | goto done; |
1cdd1ec8 | 4470 | |
bc97114d PWJ |
4471 | #ifdef CONFIG_IXGBE_DCB |
4472 | if (ixgbe_set_dcb_queues(adapter)) | |
af22ab1b | 4473 | goto done; |
bc97114d PWJ |
4474 | |
4475 | #endif | |
e5b64635 JF |
4476 | #ifdef IXGBE_FCOE |
4477 | if (ixgbe_set_fcoe_queues(adapter)) | |
4478 | goto done; | |
4479 | ||
4480 | #endif /* IXGBE_FCOE */ | |
c4cf55e5 PWJ |
4481 | if (ixgbe_set_fdir_queues(adapter)) |
4482 | goto done; | |
4483 | ||
bc97114d | 4484 | if (ixgbe_set_rss_queues(adapter)) |
af22ab1b WF |
4485 | goto done; |
4486 | ||
4487 | /* fallback to base case */ | |
4488 | adapter->num_rx_queues = 1; | |
4489 | adapter->num_tx_queues = 1; | |
4490 | ||
4491 | done: | |
9d837ea2 YZ |
4492 | if ((adapter->netdev->reg_state == NETREG_UNREGISTERED) || |
4493 | (adapter->netdev->reg_state == NETREG_UNREGISTERING)) | |
4494 | return 0; | |
4495 | ||
847f53ff | 4496 | /* Notify the stack of the (possibly) reduced queue counts. */ |
f0796d5c | 4497 | netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); |
847f53ff BH |
4498 | return netif_set_real_num_rx_queues(adapter->netdev, |
4499 | adapter->num_rx_queues); | |
b9804972 JB |
4500 | } |
4501 | ||
021230d4 | 4502 | static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter, |
e8e9f696 | 4503 | int vectors) |
021230d4 AV |
4504 | { |
4505 | int err, vector_threshold; | |
4506 | ||
8f15486d AD |
4507 | /* We'll want at least 2 (vector_threshold): |
4508 | * 1) TxQ[0] + RxQ[0] handler | |
4509 | * 2) Other (Link Status Change, etc.) | |
021230d4 AV |
4510 | */ |
4511 | vector_threshold = MIN_MSIX_COUNT; | |
4512 | ||
24ddd967 AD |
4513 | /* |
4514 | * The more we get, the more we will assign to Tx/Rx Cleanup | |
021230d4 AV |
4515 | * for the separate queues...where Rx Cleanup >= Tx Cleanup. |
4516 | * Right now, we simply care about how many we'll get; we'll | |
4517 | * set them up later while requesting irq's. | |
4518 | */ | |
4519 | while (vectors >= vector_threshold) { | |
4520 | err = pci_enable_msix(adapter->pdev, adapter->msix_entries, | |
e8e9f696 | 4521 | vectors); |
021230d4 AV |
4522 | if (!err) /* Success in acquiring all requested vectors. */ |
4523 | break; | |
4524 | else if (err < 0) | |
4525 | vectors = 0; /* Nasty failure, quit now */ | |
4526 | else /* err == number of vectors we should try again with */ | |
4527 | vectors = err; | |
4528 | } | |
4529 | ||
4530 | if (vectors < vector_threshold) { | |
4531 | /* Can't allocate enough MSI-X interrupts? Oh well. | |
4532 | * This just means we'll go with either a single MSI | |
4533 | * vector or fall back to legacy interrupts. | |
4534 | */ | |
849c4542 ET |
4535 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4536 | "Unable to allocate MSI-X interrupts\n"); | |
021230d4 AV |
4537 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; |
4538 | kfree(adapter->msix_entries); | |
4539 | adapter->msix_entries = NULL; | |
021230d4 AV |
4540 | } else { |
4541 | adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */ | |
eb7f139c PWJ |
4542 | /* |
4543 | * Adjust for only the vectors we'll use, which is minimum | |
4544 | * of max_msix_q_vectors + NON_Q_VECTORS, or the number of | |
4545 | * vectors we were allocated. | |
4546 | */ | |
4547 | adapter->num_msix_vectors = min(vectors, | |
e8e9f696 | 4548 | adapter->max_msix_q_vectors + NON_Q_VECTORS); |
021230d4 AV |
4549 | } |
4550 | } | |
4551 | ||
021230d4 | 4552 | /** |
bc97114d | 4553 | * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS |
021230d4 AV |
4554 | * @adapter: board private structure to initialize |
4555 | * | |
bc97114d PWJ |
4556 | * Cache the descriptor ring offsets for RSS to the assigned rings. |
4557 | * | |
021230d4 | 4558 | **/ |
bc97114d | 4559 | static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter) |
021230d4 | 4560 | { |
bc97114d | 4561 | int i; |
bc97114d | 4562 | |
9d6b758f AD |
4563 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) |
4564 | return false; | |
bc97114d | 4565 | |
9d6b758f AD |
4566 | for (i = 0; i < adapter->num_rx_queues; i++) |
4567 | adapter->rx_ring[i]->reg_idx = i; | |
4568 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4569 | adapter->tx_ring[i]->reg_idx = i; | |
4570 | ||
4571 | return true; | |
bc97114d PWJ |
4572 | } |
4573 | ||
4574 | #ifdef CONFIG_IXGBE_DCB | |
e5b64635 JF |
4575 | |
4576 | /* ixgbe_get_first_reg_idx - Return first register index associated with ring */ | |
b32c8dcc JF |
4577 | static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc, |
4578 | unsigned int *tx, unsigned int *rx) | |
e5b64635 JF |
4579 | { |
4580 | struct net_device *dev = adapter->netdev; | |
4581 | struct ixgbe_hw *hw = &adapter->hw; | |
4582 | u8 num_tcs = netdev_get_num_tc(dev); | |
4583 | ||
4584 | *tx = 0; | |
4585 | *rx = 0; | |
4586 | ||
4587 | switch (hw->mac.type) { | |
4588 | case ixgbe_mac_82598EB: | |
aba70d5e JF |
4589 | *tx = tc << 2; |
4590 | *rx = tc << 3; | |
e5b64635 JF |
4591 | break; |
4592 | case ixgbe_mac_82599EB: | |
4593 | case ixgbe_mac_X540: | |
4fa2e0e1 | 4594 | if (num_tcs > 4) { |
e5b64635 JF |
4595 | if (tc < 3) { |
4596 | *tx = tc << 5; | |
4597 | *rx = tc << 4; | |
4598 | } else if (tc < 5) { | |
4599 | *tx = ((tc + 2) << 4); | |
4600 | *rx = tc << 4; | |
4601 | } else if (tc < num_tcs) { | |
4602 | *tx = ((tc + 8) << 3); | |
4603 | *rx = tc << 4; | |
4604 | } | |
4fa2e0e1 | 4605 | } else { |
e5b64635 JF |
4606 | *rx = tc << 5; |
4607 | switch (tc) { | |
4608 | case 0: | |
4609 | *tx = 0; | |
4610 | break; | |
4611 | case 1: | |
4612 | *tx = 64; | |
4613 | break; | |
4614 | case 2: | |
4615 | *tx = 96; | |
4616 | break; | |
4617 | case 3: | |
4618 | *tx = 112; | |
4619 | break; | |
4620 | default: | |
4621 | break; | |
4622 | } | |
4623 | } | |
4624 | break; | |
4625 | default: | |
4626 | break; | |
4627 | } | |
4628 | } | |
4629 | ||
bc97114d PWJ |
4630 | /** |
4631 | * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB | |
4632 | * @adapter: board private structure to initialize | |
4633 | * | |
4634 | * Cache the descriptor ring offsets for DCB to the assigned rings. | |
4635 | * | |
4636 | **/ | |
4637 | static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter) | |
4638 | { | |
e5b64635 JF |
4639 | struct net_device *dev = adapter->netdev; |
4640 | int i, j, k; | |
4641 | u8 num_tcs = netdev_get_num_tc(dev); | |
bc97114d | 4642 | |
8b1c0b24 | 4643 | if (!num_tcs) |
bd508178 | 4644 | return false; |
f92ef202 | 4645 | |
e5b64635 JF |
4646 | for (i = 0, k = 0; i < num_tcs; i++) { |
4647 | unsigned int tx_s, rx_s; | |
4648 | u16 count = dev->tc_to_txq[i].count; | |
4649 | ||
4650 | ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s); | |
4651 | for (j = 0; j < count; j++, k++) { | |
4652 | adapter->tx_ring[k]->reg_idx = tx_s + j; | |
4653 | adapter->rx_ring[k]->reg_idx = rx_s + j; | |
4654 | adapter->tx_ring[k]->dcb_tc = i; | |
4655 | adapter->rx_ring[k]->dcb_tc = i; | |
021230d4 | 4656 | } |
021230d4 | 4657 | } |
e5b64635 JF |
4658 | |
4659 | return true; | |
bc97114d PWJ |
4660 | } |
4661 | #endif | |
4662 | ||
c4cf55e5 PWJ |
4663 | /** |
4664 | * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director | |
4665 | * @adapter: board private structure to initialize | |
4666 | * | |
4667 | * Cache the descriptor ring offsets for Flow Director to the assigned rings. | |
4668 | * | |
4669 | **/ | |
e8e9f696 | 4670 | static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter) |
c4cf55e5 PWJ |
4671 | { |
4672 | int i; | |
4673 | bool ret = false; | |
4674 | ||
03ecf91a AD |
4675 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && |
4676 | (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) { | |
c4cf55e5 | 4677 | for (i = 0; i < adapter->num_rx_queues; i++) |
4a0b9ca0 | 4678 | adapter->rx_ring[i]->reg_idx = i; |
c4cf55e5 | 4679 | for (i = 0; i < adapter->num_tx_queues; i++) |
4a0b9ca0 | 4680 | adapter->tx_ring[i]->reg_idx = i; |
c4cf55e5 PWJ |
4681 | ret = true; |
4682 | } | |
4683 | ||
4684 | return ret; | |
4685 | } | |
4686 | ||
0331a832 YZ |
4687 | #ifdef IXGBE_FCOE |
4688 | /** | |
4689 | * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE | |
4690 | * @adapter: board private structure to initialize | |
4691 | * | |
4692 | * Cache the descriptor ring offsets for FCoE mode to the assigned rings. | |
4693 | * | |
4694 | */ | |
4695 | static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter) | |
4696 | { | |
0331a832 | 4697 | struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE]; |
bf29ee6c AD |
4698 | int i; |
4699 | u8 fcoe_rx_i = 0, fcoe_tx_i = 0; | |
4700 | ||
4701 | if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) | |
4702 | return false; | |
0331a832 | 4703 | |
bf29ee6c | 4704 | if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) { |
03ecf91a | 4705 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) |
bf29ee6c AD |
4706 | ixgbe_cache_ring_fdir(adapter); |
4707 | else | |
4708 | ixgbe_cache_ring_rss(adapter); | |
8faa2a78 | 4709 | |
bf29ee6c AD |
4710 | fcoe_rx_i = f->mask; |
4711 | fcoe_tx_i = f->mask; | |
0331a832 | 4712 | } |
bf29ee6c AD |
4713 | for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) { |
4714 | adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i; | |
4715 | adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i; | |
4716 | } | |
4717 | return true; | |
0331a832 YZ |
4718 | } |
4719 | ||
4720 | #endif /* IXGBE_FCOE */ | |
1cdd1ec8 GR |
4721 | /** |
4722 | * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov | |
4723 | * @adapter: board private structure to initialize | |
4724 | * | |
4725 | * SR-IOV doesn't use any descriptor rings but changes the default if | |
4726 | * no other mapping is used. | |
4727 | * | |
4728 | */ | |
4729 | static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter) | |
4730 | { | |
4a0b9ca0 PW |
4731 | adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2; |
4732 | adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2; | |
1cdd1ec8 GR |
4733 | if (adapter->num_vfs) |
4734 | return true; | |
4735 | else | |
4736 | return false; | |
4737 | } | |
4738 | ||
bc97114d PWJ |
4739 | /** |
4740 | * ixgbe_cache_ring_register - Descriptor ring to register mapping | |
4741 | * @adapter: board private structure to initialize | |
4742 | * | |
4743 | * Once we know the feature-set enabled for the device, we'll cache | |
4744 | * the register offset the descriptor ring is assigned to. | |
4745 | * | |
4746 | * Note, the order the various feature calls is important. It must start with | |
4747 | * the "most" features enabled at the same time, then trickle down to the | |
4748 | * least amount of features turned on at once. | |
4749 | **/ | |
4750 | static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter) | |
4751 | { | |
4752 | /* start with default case */ | |
4a0b9ca0 PW |
4753 | adapter->rx_ring[0]->reg_idx = 0; |
4754 | adapter->tx_ring[0]->reg_idx = 0; | |
bc97114d | 4755 | |
1cdd1ec8 GR |
4756 | if (ixgbe_cache_ring_sriov(adapter)) |
4757 | return; | |
4758 | ||
e5b64635 JF |
4759 | #ifdef CONFIG_IXGBE_DCB |
4760 | if (ixgbe_cache_ring_dcb(adapter)) | |
4761 | return; | |
4762 | #endif | |
4763 | ||
0331a832 YZ |
4764 | #ifdef IXGBE_FCOE |
4765 | if (ixgbe_cache_ring_fcoe(adapter)) | |
4766 | return; | |
0331a832 | 4767 | #endif /* IXGBE_FCOE */ |
bc97114d | 4768 | |
c4cf55e5 PWJ |
4769 | if (ixgbe_cache_ring_fdir(adapter)) |
4770 | return; | |
4771 | ||
bc97114d PWJ |
4772 | if (ixgbe_cache_ring_rss(adapter)) |
4773 | return; | |
021230d4 AV |
4774 | } |
4775 | ||
021230d4 AV |
4776 | /** |
4777 | * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported | |
4778 | * @adapter: board private structure to initialize | |
4779 | * | |
4780 | * Attempt to configure the interrupts using the best available | |
4781 | * capabilities of the hardware and the kernel. | |
4782 | **/ | |
feea6a57 | 4783 | static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 | 4784 | { |
8be0e467 | 4785 | struct ixgbe_hw *hw = &adapter->hw; |
021230d4 AV |
4786 | int err = 0; |
4787 | int vector, v_budget; | |
4788 | ||
4789 | /* | |
4790 | * It's easy to be greedy for MSI-X vectors, but it really | |
4791 | * doesn't do us much good if we have a lot more vectors | |
4792 | * than CPU's. So let's be conservative and only ask for | |
342bde1b | 4793 | * (roughly) the same number of vectors as there are CPU's. |
8f15486d | 4794 | * The default is to use pairs of vectors. |
021230d4 | 4795 | */ |
8f15486d AD |
4796 | v_budget = max(adapter->num_rx_queues, adapter->num_tx_queues); |
4797 | v_budget = min_t(int, v_budget, num_online_cpus()); | |
4798 | v_budget += NON_Q_VECTORS; | |
021230d4 AV |
4799 | |
4800 | /* | |
4801 | * At the same time, hardware can only support a maximum of | |
8be0e467 PW |
4802 | * hw.mac->max_msix_vectors vectors. With features |
4803 | * such as RSS and VMDq, we can easily surpass the number of Rx and Tx | |
4804 | * descriptor queues supported by our device. Thus, we cap it off in | |
4805 | * those rare cases where the cpu count also exceeds our vector limit. | |
021230d4 | 4806 | */ |
de88eeeb | 4807 | v_budget = min_t(int, v_budget, hw->mac.max_msix_vectors); |
021230d4 AV |
4808 | |
4809 | /* A failure in MSI-X entry allocation isn't fatal, but it does | |
4810 | * mean we disable MSI-X capabilities of the adapter. */ | |
4811 | adapter->msix_entries = kcalloc(v_budget, | |
e8e9f696 | 4812 | sizeof(struct msix_entry), GFP_KERNEL); |
7a921c93 AD |
4813 | if (adapter->msix_entries) { |
4814 | for (vector = 0; vector < v_budget; vector++) | |
4815 | adapter->msix_entries[vector].entry = vector; | |
021230d4 | 4816 | |
7a921c93 | 4817 | ixgbe_acquire_msix_vectors(adapter, v_budget); |
021230d4 | 4818 | |
7a921c93 AD |
4819 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
4820 | goto out; | |
4821 | } | |
26d27844 | 4822 | |
7a921c93 AD |
4823 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; |
4824 | adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED; | |
03ecf91a | 4825 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
45b9f509 | 4826 | e_err(probe, |
03ecf91a | 4827 | "ATR is not supported while multiple " |
45b9f509 AD |
4828 | "queues are disabled. Disabling Flow Director\n"); |
4829 | } | |
c4cf55e5 | 4830 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; |
c4cf55e5 | 4831 | adapter->atr_sample_rate = 0; |
1cdd1ec8 GR |
4832 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
4833 | ixgbe_disable_sriov(adapter); | |
4834 | ||
847f53ff BH |
4835 | err = ixgbe_set_num_queues(adapter); |
4836 | if (err) | |
4837 | return err; | |
021230d4 | 4838 | |
021230d4 AV |
4839 | err = pci_enable_msi(adapter->pdev); |
4840 | if (!err) { | |
4841 | adapter->flags |= IXGBE_FLAG_MSI_ENABLED; | |
4842 | } else { | |
849c4542 ET |
4843 | netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev, |
4844 | "Unable to allocate MSI interrupt, " | |
4845 | "falling back to legacy. Error: %d\n", err); | |
021230d4 AV |
4846 | /* reset err */ |
4847 | err = 0; | |
4848 | } | |
4849 | ||
4850 | out: | |
021230d4 AV |
4851 | return err; |
4852 | } | |
4853 | ||
de88eeeb AD |
4854 | static void ixgbe_add_ring(struct ixgbe_ring *ring, |
4855 | struct ixgbe_ring_container *head) | |
4856 | { | |
4857 | ring->next = head->ring; | |
4858 | head->ring = ring; | |
4859 | head->count++; | |
4860 | } | |
4861 | ||
4862 | /** | |
4863 | * ixgbe_alloc_q_vector - Allocate memory for a single interrupt vector | |
4864 | * @adapter: board private structure to initialize | |
4865 | * @v_idx: index of vector in adapter struct | |
4866 | * | |
4867 | * We allocate one q_vector. If allocation fails we return -ENOMEM. | |
4868 | **/ | |
4869 | static int ixgbe_alloc_q_vector(struct ixgbe_adapter *adapter, int v_idx, | |
4870 | int txr_count, int txr_idx, | |
4871 | int rxr_count, int rxr_idx) | |
4872 | { | |
4873 | struct ixgbe_q_vector *q_vector; | |
4874 | struct ixgbe_ring *ring; | |
4875 | int node = -1; | |
4876 | int cpu = -1; | |
4877 | int ring_count, size; | |
4878 | ||
4879 | ring_count = txr_count + rxr_count; | |
4880 | size = sizeof(struct ixgbe_q_vector) + | |
4881 | (sizeof(struct ixgbe_ring) * ring_count); | |
4882 | ||
4883 | /* customize cpu for Flow Director mapping */ | |
4884 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { | |
4885 | if (cpu_online(v_idx)) { | |
4886 | cpu = v_idx; | |
4887 | node = cpu_to_node(cpu); | |
4888 | } | |
4889 | } | |
4890 | ||
4891 | /* allocate q_vector and rings */ | |
4892 | q_vector = kzalloc_node(size, GFP_KERNEL, node); | |
4893 | if (!q_vector) | |
4894 | q_vector = kzalloc(size, GFP_KERNEL); | |
4895 | if (!q_vector) | |
4896 | return -ENOMEM; | |
4897 | ||
4898 | /* setup affinity mask and node */ | |
4899 | if (cpu != -1) | |
4900 | cpumask_set_cpu(cpu, &q_vector->affinity_mask); | |
4901 | else | |
4902 | cpumask_copy(&q_vector->affinity_mask, cpu_online_mask); | |
4903 | q_vector->numa_node = node; | |
4904 | ||
4905 | /* initialize NAPI */ | |
4906 | netif_napi_add(adapter->netdev, &q_vector->napi, | |
4907 | ixgbe_poll, 64); | |
4908 | ||
4909 | /* tie q_vector and adapter together */ | |
4910 | adapter->q_vector[v_idx] = q_vector; | |
4911 | q_vector->adapter = adapter; | |
4912 | q_vector->v_idx = v_idx; | |
4913 | ||
4914 | /* initialize work limits */ | |
4915 | q_vector->tx.work_limit = adapter->tx_work_limit; | |
4916 | ||
4917 | /* initialize pointer to rings */ | |
4918 | ring = q_vector->ring; | |
4919 | ||
4920 | while (txr_count) { | |
4921 | /* assign generic ring traits */ | |
4922 | ring->dev = &adapter->pdev->dev; | |
4923 | ring->netdev = adapter->netdev; | |
4924 | ||
4925 | /* configure backlink on ring */ | |
4926 | ring->q_vector = q_vector; | |
4927 | ||
4928 | /* update q_vector Tx values */ | |
4929 | ixgbe_add_ring(ring, &q_vector->tx); | |
4930 | ||
4931 | /* apply Tx specific ring traits */ | |
4932 | ring->count = adapter->tx_ring_count; | |
4933 | ring->queue_index = txr_idx; | |
4934 | ||
4935 | /* assign ring to adapter */ | |
4936 | adapter->tx_ring[txr_idx] = ring; | |
4937 | ||
4938 | /* update count and index */ | |
4939 | txr_count--; | |
4940 | txr_idx++; | |
4941 | ||
4942 | /* push pointer to next ring */ | |
4943 | ring++; | |
4944 | } | |
4945 | ||
4946 | while (rxr_count) { | |
4947 | /* assign generic ring traits */ | |
4948 | ring->dev = &adapter->pdev->dev; | |
4949 | ring->netdev = adapter->netdev; | |
4950 | ||
4951 | /* configure backlink on ring */ | |
4952 | ring->q_vector = q_vector; | |
4953 | ||
4954 | /* update q_vector Rx values */ | |
4955 | ixgbe_add_ring(ring, &q_vector->rx); | |
4956 | ||
4957 | /* | |
4958 | * 82599 errata, UDP frames with a 0 checksum | |
4959 | * can be marked as checksum errors. | |
4960 | */ | |
4961 | if (adapter->hw.mac.type == ixgbe_mac_82599EB) | |
4962 | set_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state); | |
4963 | ||
4964 | /* apply Rx specific ring traits */ | |
4965 | ring->count = adapter->rx_ring_count; | |
4966 | ring->queue_index = rxr_idx; | |
4967 | ||
4968 | /* assign ring to adapter */ | |
4969 | adapter->rx_ring[rxr_idx] = ring; | |
4970 | ||
4971 | /* update count and index */ | |
4972 | rxr_count--; | |
4973 | rxr_idx++; | |
4974 | ||
4975 | /* push pointer to next ring */ | |
4976 | ring++; | |
4977 | } | |
4978 | ||
4979 | return 0; | |
4980 | } | |
4981 | ||
4982 | /** | |
4983 | * ixgbe_free_q_vector - Free memory allocated for specific interrupt vector | |
4984 | * @adapter: board private structure to initialize | |
4985 | * @v_idx: Index of vector to be freed | |
4986 | * | |
4987 | * This function frees the memory allocated to the q_vector. In addition if | |
4988 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
4989 | * to freeing the q_vector. | |
4990 | **/ | |
4991 | static void ixgbe_free_q_vector(struct ixgbe_adapter *adapter, int v_idx) | |
4992 | { | |
4993 | struct ixgbe_q_vector *q_vector = adapter->q_vector[v_idx]; | |
4994 | struct ixgbe_ring *ring; | |
4995 | ||
a557928e | 4996 | ixgbe_for_each_ring(ring, q_vector->tx) |
de88eeeb AD |
4997 | adapter->tx_ring[ring->queue_index] = NULL; |
4998 | ||
a557928e | 4999 | ixgbe_for_each_ring(ring, q_vector->rx) |
de88eeeb AD |
5000 | adapter->rx_ring[ring->queue_index] = NULL; |
5001 | ||
5002 | adapter->q_vector[v_idx] = NULL; | |
5003 | netif_napi_del(&q_vector->napi); | |
5004 | ||
5005 | /* | |
5006 | * ixgbe_get_stats64() might access the rings on this vector, | |
5007 | * we must wait a grace period before freeing it. | |
5008 | */ | |
5009 | kfree_rcu(q_vector, rcu); | |
5010 | } | |
5011 | ||
7a921c93 AD |
5012 | /** |
5013 | * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors | |
5014 | * @adapter: board private structure to initialize | |
5015 | * | |
5016 | * We allocate one q_vector per queue interrupt. If allocation fails we | |
5017 | * return -ENOMEM. | |
5018 | **/ | |
5019 | static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter) | |
5020 | { | |
de88eeeb AD |
5021 | int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
5022 | int rxr_remaining = adapter->num_rx_queues; | |
5023 | int txr_remaining = adapter->num_tx_queues; | |
5024 | int rxr_idx = 0, txr_idx = 0, v_idx = 0; | |
5025 | int err; | |
7a921c93 | 5026 | |
de88eeeb AD |
5027 | /* only one q_vector if MSI-X is disabled. */ |
5028 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) | |
5029 | q_vectors = 1; | |
7a921c93 | 5030 | |
de88eeeb AD |
5031 | if (q_vectors >= (rxr_remaining + txr_remaining)) { |
5032 | for (; rxr_remaining; v_idx++, q_vectors--) { | |
5033 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors); | |
5034 | err = ixgbe_alloc_q_vector(adapter, v_idx, | |
5035 | 0, 0, rqpv, rxr_idx); | |
4ff7fb12 | 5036 | |
de88eeeb AD |
5037 | if (err) |
5038 | goto err_out; | |
5039 | ||
5040 | /* update counts and index */ | |
5041 | rxr_remaining -= rqpv; | |
5042 | rxr_idx += rqpv; | |
5043 | } | |
5044 | } | |
4ff7fb12 | 5045 | |
de88eeeb AD |
5046 | for (; q_vectors; v_idx++, q_vectors--) { |
5047 | int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors); | |
5048 | int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors); | |
5049 | err = ixgbe_alloc_q_vector(adapter, v_idx, | |
5050 | tqpv, txr_idx, | |
5051 | rqpv, rxr_idx); | |
5052 | ||
5053 | if (err) | |
207867f5 | 5054 | goto err_out; |
de88eeeb AD |
5055 | |
5056 | /* update counts and index */ | |
5057 | rxr_remaining -= rqpv; | |
5058 | rxr_idx += rqpv; | |
5059 | txr_remaining -= tqpv; | |
5060 | txr_idx += tqpv; | |
7a921c93 AD |
5061 | } |
5062 | ||
5063 | return 0; | |
5064 | ||
5065 | err_out: | |
4ff7fb12 AD |
5066 | while (v_idx) { |
5067 | v_idx--; | |
de88eeeb | 5068 | ixgbe_free_q_vector(adapter, v_idx); |
7a921c93 | 5069 | } |
de88eeeb | 5070 | |
7a921c93 AD |
5071 | return -ENOMEM; |
5072 | } | |
5073 | ||
5074 | /** | |
5075 | * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors | |
5076 | * @adapter: board private structure to initialize | |
5077 | * | |
5078 | * This function frees the memory allocated to the q_vectors. In addition if | |
5079 | * NAPI is enabled it will delete any references to the NAPI struct prior | |
5080 | * to freeing the q_vector. | |
5081 | **/ | |
5082 | static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter) | |
5083 | { | |
de88eeeb | 5084 | int v_idx, q_vectors; |
7a921c93 | 5085 | |
91281fd3 | 5086 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) |
de88eeeb | 5087 | q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; |
91281fd3 | 5088 | else |
de88eeeb | 5089 | q_vectors = 1; |
7a921c93 | 5090 | |
de88eeeb AD |
5091 | for (v_idx = 0; v_idx < q_vectors; v_idx++) |
5092 | ixgbe_free_q_vector(adapter, v_idx); | |
7a921c93 AD |
5093 | } |
5094 | ||
7b25cdba | 5095 | static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter) |
021230d4 AV |
5096 | { |
5097 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { | |
5098 | adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED; | |
5099 | pci_disable_msix(adapter->pdev); | |
5100 | kfree(adapter->msix_entries); | |
5101 | adapter->msix_entries = NULL; | |
5102 | } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) { | |
5103 | adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED; | |
5104 | pci_disable_msi(adapter->pdev); | |
5105 | } | |
021230d4 AV |
5106 | } |
5107 | ||
5108 | /** | |
5109 | * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme | |
5110 | * @adapter: board private structure to initialize | |
5111 | * | |
5112 | * We determine which interrupt scheme to use based on... | |
5113 | * - Kernel support (MSI, MSI-X) | |
5114 | * - which can be user-defined (via MODULE_PARAM) | |
5115 | * - Hardware queue count (num_*_queues) | |
5116 | * - defined by miscellaneous hardware support/features (RSS, etc.) | |
5117 | **/ | |
2f90b865 | 5118 | int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter) |
021230d4 AV |
5119 | { |
5120 | int err; | |
5121 | ||
5122 | /* Number of supported queues */ | |
847f53ff BH |
5123 | err = ixgbe_set_num_queues(adapter); |
5124 | if (err) | |
5125 | return err; | |
021230d4 | 5126 | |
021230d4 AV |
5127 | err = ixgbe_set_interrupt_capability(adapter); |
5128 | if (err) { | |
849c4542 | 5129 | e_dev_err("Unable to setup interrupt capabilities\n"); |
021230d4 | 5130 | goto err_set_interrupt; |
9a799d71 AK |
5131 | } |
5132 | ||
7a921c93 AD |
5133 | err = ixgbe_alloc_q_vectors(adapter); |
5134 | if (err) { | |
849c4542 | 5135 | e_dev_err("Unable to allocate memory for queue vectors\n"); |
7a921c93 AD |
5136 | goto err_alloc_q_vectors; |
5137 | } | |
5138 | ||
de88eeeb | 5139 | ixgbe_cache_ring_register(adapter); |
7a921c93 | 5140 | |
849c4542 | 5141 | e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n", |
396e799c ET |
5142 | (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled", |
5143 | adapter->num_rx_queues, adapter->num_tx_queues); | |
021230d4 AV |
5144 | |
5145 | set_bit(__IXGBE_DOWN, &adapter->state); | |
5146 | ||
9a799d71 | 5147 | return 0; |
021230d4 | 5148 | |
7a921c93 AD |
5149 | err_alloc_q_vectors: |
5150 | ixgbe_reset_interrupt_capability(adapter); | |
021230d4 | 5151 | err_set_interrupt: |
7a921c93 AD |
5152 | return err; |
5153 | } | |
5154 | ||
5155 | /** | |
5156 | * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings | |
5157 | * @adapter: board private structure to clear interrupt scheme on | |
5158 | * | |
5159 | * We go through and clear interrupt specific resources and reset the structure | |
5160 | * to pre-load conditions | |
5161 | **/ | |
5162 | void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter) | |
5163 | { | |
b8eb3a10 DS |
5164 | adapter->num_tx_queues = 0; |
5165 | adapter->num_rx_queues = 0; | |
5166 | ||
7a921c93 AD |
5167 | ixgbe_free_q_vectors(adapter); |
5168 | ixgbe_reset_interrupt_capability(adapter); | |
9a799d71 AK |
5169 | } |
5170 | ||
5171 | /** | |
5172 | * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter) | |
5173 | * @adapter: board private structure to initialize | |
5174 | * | |
5175 | * ixgbe_sw_init initializes the Adapter private data structure. | |
5176 | * Fields are initialized based on PCI device information and | |
5177 | * OS network device settings (MTU size). | |
5178 | **/ | |
5179 | static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter) | |
5180 | { | |
5181 | struct ixgbe_hw *hw = &adapter->hw; | |
5182 | struct pci_dev *pdev = adapter->pdev; | |
021230d4 | 5183 | unsigned int rss; |
7a6b6f51 | 5184 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
5185 | int j; |
5186 | struct tc_configuration *tc; | |
5187 | #endif | |
021230d4 | 5188 | |
c44ade9e JB |
5189 | /* PCI config space info */ |
5190 | ||
5191 | hw->vendor_id = pdev->vendor; | |
5192 | hw->device_id = pdev->device; | |
5193 | hw->revision_id = pdev->revision; | |
5194 | hw->subsystem_vendor_id = pdev->subsystem_vendor; | |
5195 | hw->subsystem_device_id = pdev->subsystem_device; | |
5196 | ||
021230d4 | 5197 | /* Set capability flags */ |
3ed69d7e | 5198 | rss = min_t(int, IXGBE_MAX_RSS_INDICES, num_online_cpus()); |
021230d4 AV |
5199 | adapter->ring_feature[RING_F_RSS].indices = rss; |
5200 | adapter->flags |= IXGBE_FLAG_RSS_ENABLED; | |
bd508178 AD |
5201 | switch (hw->mac.type) { |
5202 | case ixgbe_mac_82598EB: | |
bf069c97 DS |
5203 | if (hw->device_id == IXGBE_DEV_ID_82598AT) |
5204 | adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE; | |
e8e26350 | 5205 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598; |
bd508178 | 5206 | break; |
b93a2226 | 5207 | case ixgbe_mac_X540: |
4f51bf70 JK |
5208 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; |
5209 | case ixgbe_mac_82599EB: | |
e8e26350 | 5210 | adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599; |
0c19d6af PWJ |
5211 | adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE; |
5212 | adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED; | |
119fc60a MC |
5213 | if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM) |
5214 | adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE; | |
45b9f509 AD |
5215 | /* Flow Director hash filters enabled */ |
5216 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
5217 | adapter->atr_sample_rate = 20; | |
c4cf55e5 | 5218 | adapter->ring_feature[RING_F_FDIR].indices = |
e8e9f696 | 5219 | IXGBE_MAX_FDIR_INDICES; |
c04f6ca8 | 5220 | adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K; |
eacd73f7 | 5221 | #ifdef IXGBE_FCOE |
0d551589 YZ |
5222 | adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE; |
5223 | adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED; | |
5224 | adapter->ring_feature[RING_F_FCOE].indices = 0; | |
61a0f421 | 5225 | #ifdef CONFIG_IXGBE_DCB |
6ee16520 | 5226 | /* Default traffic class to use for FCoE */ |
56075a98 | 5227 | adapter->fcoe.up = IXGBE_FCOE_DEFTC; |
61a0f421 | 5228 | #endif |
eacd73f7 | 5229 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5230 | break; |
5231 | default: | |
5232 | break; | |
f8212f97 | 5233 | } |
2f90b865 | 5234 | |
1fc5f038 AD |
5235 | /* n-tuple support exists, always init our spinlock */ |
5236 | spin_lock_init(&adapter->fdir_perfect_lock); | |
5237 | ||
7a6b6f51 | 5238 | #ifdef CONFIG_IXGBE_DCB |
4de2a022 JF |
5239 | switch (hw->mac.type) { |
5240 | case ixgbe_mac_X540: | |
5241 | adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS; | |
5242 | adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS; | |
5243 | break; | |
5244 | default: | |
5245 | adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS; | |
5246 | adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS; | |
5247 | break; | |
5248 | } | |
5249 | ||
2f90b865 AD |
5250 | /* Configure DCB traffic classes */ |
5251 | for (j = 0; j < MAX_TRAFFIC_CLASS; j++) { | |
5252 | tc = &adapter->dcb_cfg.tc_config[j]; | |
5253 | tc->path[DCB_TX_CONFIG].bwg_id = 0; | |
5254 | tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1); | |
5255 | tc->path[DCB_RX_CONFIG].bwg_id = 0; | |
5256 | tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1); | |
5257 | tc->dcb_pfc = pfc_disabled; | |
5258 | } | |
4de2a022 JF |
5259 | |
5260 | /* Initialize default user to priority mapping, UPx->TC0 */ | |
5261 | tc = &adapter->dcb_cfg.tc_config[0]; | |
5262 | tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5263 | tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF; | |
5264 | ||
2f90b865 AD |
5265 | adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100; |
5266 | adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100; | |
264857b8 | 5267 | adapter->dcb_cfg.pfc_mode_enable = false; |
2f90b865 | 5268 | adapter->dcb_set_bitmap = 0x00; |
3032309b | 5269 | adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE; |
2f90b865 | 5270 | ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg, |
e5b64635 | 5271 | MAX_TRAFFIC_CLASS); |
2f90b865 AD |
5272 | |
5273 | #endif | |
9a799d71 AK |
5274 | |
5275 | /* default flow control settings */ | |
cd7664f6 | 5276 | hw->fc.requested_mode = ixgbe_fc_full; |
71fd570b | 5277 | hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */ |
264857b8 PWJ |
5278 | #ifdef CONFIG_DCB |
5279 | adapter->last_lfc_mode = hw->fc.current_mode; | |
5280 | #endif | |
9da712d2 | 5281 | ixgbe_pbthresh_setup(adapter); |
2b9ade93 JB |
5282 | hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE; |
5283 | hw->fc.send_xon = true; | |
71fd570b | 5284 | hw->fc.disable_fc_autoneg = false; |
9a799d71 | 5285 | |
30efa5a3 | 5286 | /* enable itr by default in dynamic mode */ |
f7554a2b | 5287 | adapter->rx_itr_setting = 1; |
f7554a2b | 5288 | adapter->tx_itr_setting = 1; |
30efa5a3 | 5289 | |
30efa5a3 JB |
5290 | /* set default ring sizes */ |
5291 | adapter->tx_ring_count = IXGBE_DEFAULT_TXD; | |
5292 | adapter->rx_ring_count = IXGBE_DEFAULT_RXD; | |
5293 | ||
bd198058 | 5294 | /* set default work limits */ |
59224555 | 5295 | adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK; |
bd198058 | 5296 | |
9a799d71 | 5297 | /* initialize eeprom parameters */ |
c44ade9e | 5298 | if (ixgbe_init_eeprom_params_generic(hw)) { |
849c4542 | 5299 | e_dev_err("EEPROM initialization failed\n"); |
9a799d71 AK |
5300 | return -EIO; |
5301 | } | |
5302 | ||
9a799d71 AK |
5303 | set_bit(__IXGBE_DOWN, &adapter->state); |
5304 | ||
5305 | return 0; | |
5306 | } | |
5307 | ||
5308 | /** | |
5309 | * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors) | |
3a581073 | 5310 | * @tx_ring: tx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5311 | * |
5312 | * Return 0 on success, negative on failure | |
5313 | **/ | |
b6ec895e | 5314 | int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5315 | { |
b6ec895e | 5316 | struct device *dev = tx_ring->dev; |
de88eeeb AD |
5317 | int orig_node = dev_to_node(dev); |
5318 | int numa_node = -1; | |
9a799d71 AK |
5319 | int size; |
5320 | ||
3a581073 | 5321 | size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count; |
de88eeeb AD |
5322 | |
5323 | if (tx_ring->q_vector) | |
5324 | numa_node = tx_ring->q_vector->numa_node; | |
5325 | ||
5326 | tx_ring->tx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 5327 | if (!tx_ring->tx_buffer_info) |
89bf67f1 | 5328 | tx_ring->tx_buffer_info = vzalloc(size); |
e01c31a5 JB |
5329 | if (!tx_ring->tx_buffer_info) |
5330 | goto err; | |
9a799d71 AK |
5331 | |
5332 | /* round up to nearest 4K */ | |
12207e49 | 5333 | tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc); |
3a581073 | 5334 | tx_ring->size = ALIGN(tx_ring->size, 4096); |
9a799d71 | 5335 | |
de88eeeb AD |
5336 | set_dev_node(dev, numa_node); |
5337 | tx_ring->desc = dma_alloc_coherent(dev, | |
5338 | tx_ring->size, | |
5339 | &tx_ring->dma, | |
5340 | GFP_KERNEL); | |
5341 | set_dev_node(dev, orig_node); | |
5342 | if (!tx_ring->desc) | |
5343 | tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, | |
5344 | &tx_ring->dma, GFP_KERNEL); | |
e01c31a5 JB |
5345 | if (!tx_ring->desc) |
5346 | goto err; | |
9a799d71 | 5347 | |
3a581073 JB |
5348 | tx_ring->next_to_use = 0; |
5349 | tx_ring->next_to_clean = 0; | |
9a799d71 | 5350 | return 0; |
e01c31a5 JB |
5351 | |
5352 | err: | |
5353 | vfree(tx_ring->tx_buffer_info); | |
5354 | tx_ring->tx_buffer_info = NULL; | |
b6ec895e | 5355 | dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); |
e01c31a5 | 5356 | return -ENOMEM; |
9a799d71 AK |
5357 | } |
5358 | ||
69888674 AD |
5359 | /** |
5360 | * ixgbe_setup_all_tx_resources - allocate all queues Tx resources | |
5361 | * @adapter: board private structure | |
5362 | * | |
5363 | * If this function returns with an error, then it's possible one or | |
5364 | * more of the rings is populated (while the rest are not). It is the | |
5365 | * callers duty to clean those orphaned rings. | |
5366 | * | |
5367 | * Return 0 on success, negative on failure | |
5368 | **/ | |
5369 | static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter) | |
5370 | { | |
5371 | int i, err = 0; | |
5372 | ||
5373 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
b6ec895e | 5374 | err = ixgbe_setup_tx_resources(adapter->tx_ring[i]); |
69888674 AD |
5375 | if (!err) |
5376 | continue; | |
396e799c | 5377 | e_err(probe, "Allocation for Tx Queue %u failed\n", i); |
69888674 AD |
5378 | break; |
5379 | } | |
5380 | ||
5381 | return err; | |
5382 | } | |
5383 | ||
9a799d71 AK |
5384 | /** |
5385 | * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors) | |
3a581073 | 5386 | * @rx_ring: rx descriptor ring (for a specific queue) to setup |
9a799d71 AK |
5387 | * |
5388 | * Returns 0 on success, negative on failure | |
5389 | **/ | |
b6ec895e | 5390 | int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5391 | { |
b6ec895e | 5392 | struct device *dev = rx_ring->dev; |
de88eeeb AD |
5393 | int orig_node = dev_to_node(dev); |
5394 | int numa_node = -1; | |
021230d4 | 5395 | int size; |
9a799d71 | 5396 | |
3a581073 | 5397 | size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count; |
de88eeeb AD |
5398 | |
5399 | if (rx_ring->q_vector) | |
5400 | numa_node = rx_ring->q_vector->numa_node; | |
5401 | ||
5402 | rx_ring->rx_buffer_info = vzalloc_node(size, numa_node); | |
1a6c14a2 | 5403 | if (!rx_ring->rx_buffer_info) |
89bf67f1 | 5404 | rx_ring->rx_buffer_info = vzalloc(size); |
b6ec895e AD |
5405 | if (!rx_ring->rx_buffer_info) |
5406 | goto err; | |
9a799d71 | 5407 | |
9a799d71 | 5408 | /* Round up to nearest 4K */ |
3a581073 JB |
5409 | rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc); |
5410 | rx_ring->size = ALIGN(rx_ring->size, 4096); | |
9a799d71 | 5411 | |
de88eeeb AD |
5412 | set_dev_node(dev, numa_node); |
5413 | rx_ring->desc = dma_alloc_coherent(dev, | |
5414 | rx_ring->size, | |
5415 | &rx_ring->dma, | |
5416 | GFP_KERNEL); | |
5417 | set_dev_node(dev, orig_node); | |
5418 | if (!rx_ring->desc) | |
5419 | rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, | |
5420 | &rx_ring->dma, GFP_KERNEL); | |
b6ec895e AD |
5421 | if (!rx_ring->desc) |
5422 | goto err; | |
9a799d71 | 5423 | |
3a581073 JB |
5424 | rx_ring->next_to_clean = 0; |
5425 | rx_ring->next_to_use = 0; | |
9a799d71 | 5426 | |
f800326d AD |
5427 | ixgbe_init_rx_page_offset(rx_ring); |
5428 | ||
9a799d71 | 5429 | return 0; |
b6ec895e AD |
5430 | err: |
5431 | vfree(rx_ring->rx_buffer_info); | |
5432 | rx_ring->rx_buffer_info = NULL; | |
5433 | dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); | |
177db6ff | 5434 | return -ENOMEM; |
9a799d71 AK |
5435 | } |
5436 | ||
69888674 AD |
5437 | /** |
5438 | * ixgbe_setup_all_rx_resources - allocate all queues Rx resources | |
5439 | * @adapter: board private structure | |
5440 | * | |
5441 | * If this function returns with an error, then it's possible one or | |
5442 | * more of the rings is populated (while the rest are not). It is the | |
5443 | * callers duty to clean those orphaned rings. | |
5444 | * | |
5445 | * Return 0 on success, negative on failure | |
5446 | **/ | |
69888674 AD |
5447 | static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter) |
5448 | { | |
5449 | int i, err = 0; | |
5450 | ||
5451 | for (i = 0; i < adapter->num_rx_queues; i++) { | |
b6ec895e | 5452 | err = ixgbe_setup_rx_resources(adapter->rx_ring[i]); |
69888674 AD |
5453 | if (!err) |
5454 | continue; | |
396e799c | 5455 | e_err(probe, "Allocation for Rx Queue %u failed\n", i); |
69888674 AD |
5456 | break; |
5457 | } | |
5458 | ||
5459 | return err; | |
5460 | } | |
5461 | ||
9a799d71 AK |
5462 | /** |
5463 | * ixgbe_free_tx_resources - Free Tx Resources per Queue | |
9a799d71 AK |
5464 | * @tx_ring: Tx descriptor ring for a specific queue |
5465 | * | |
5466 | * Free all transmit software resources | |
5467 | **/ | |
b6ec895e | 5468 | void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring) |
9a799d71 | 5469 | { |
b6ec895e | 5470 | ixgbe_clean_tx_ring(tx_ring); |
9a799d71 AK |
5471 | |
5472 | vfree(tx_ring->tx_buffer_info); | |
5473 | tx_ring->tx_buffer_info = NULL; | |
5474 | ||
b6ec895e AD |
5475 | /* if not set, then don't free */ |
5476 | if (!tx_ring->desc) | |
5477 | return; | |
5478 | ||
5479 | dma_free_coherent(tx_ring->dev, tx_ring->size, | |
5480 | tx_ring->desc, tx_ring->dma); | |
9a799d71 AK |
5481 | |
5482 | tx_ring->desc = NULL; | |
5483 | } | |
5484 | ||
5485 | /** | |
5486 | * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues | |
5487 | * @adapter: board private structure | |
5488 | * | |
5489 | * Free all transmit software resources | |
5490 | **/ | |
5491 | static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter) | |
5492 | { | |
5493 | int i; | |
5494 | ||
5495 | for (i = 0; i < adapter->num_tx_queues; i++) | |
4a0b9ca0 | 5496 | if (adapter->tx_ring[i]->desc) |
b6ec895e | 5497 | ixgbe_free_tx_resources(adapter->tx_ring[i]); |
9a799d71 AK |
5498 | } |
5499 | ||
5500 | /** | |
b4617240 | 5501 | * ixgbe_free_rx_resources - Free Rx Resources |
9a799d71 AK |
5502 | * @rx_ring: ring to clean the resources from |
5503 | * | |
5504 | * Free all receive software resources | |
5505 | **/ | |
b6ec895e | 5506 | void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring) |
9a799d71 | 5507 | { |
b6ec895e | 5508 | ixgbe_clean_rx_ring(rx_ring); |
9a799d71 AK |
5509 | |
5510 | vfree(rx_ring->rx_buffer_info); | |
5511 | rx_ring->rx_buffer_info = NULL; | |
5512 | ||
b6ec895e AD |
5513 | /* if not set, then don't free */ |
5514 | if (!rx_ring->desc) | |
5515 | return; | |
5516 | ||
5517 | dma_free_coherent(rx_ring->dev, rx_ring->size, | |
5518 | rx_ring->desc, rx_ring->dma); | |
9a799d71 AK |
5519 | |
5520 | rx_ring->desc = NULL; | |
5521 | } | |
5522 | ||
5523 | /** | |
5524 | * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues | |
5525 | * @adapter: board private structure | |
5526 | * | |
5527 | * Free all receive software resources | |
5528 | **/ | |
5529 | static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter) | |
5530 | { | |
5531 | int i; | |
5532 | ||
5533 | for (i = 0; i < adapter->num_rx_queues; i++) | |
4a0b9ca0 | 5534 | if (adapter->rx_ring[i]->desc) |
b6ec895e | 5535 | ixgbe_free_rx_resources(adapter->rx_ring[i]); |
9a799d71 AK |
5536 | } |
5537 | ||
9a799d71 AK |
5538 | /** |
5539 | * ixgbe_change_mtu - Change the Maximum Transfer Unit | |
5540 | * @netdev: network interface device structure | |
5541 | * @new_mtu: new value for maximum frame size | |
5542 | * | |
5543 | * Returns 0 on success, negative on failure | |
5544 | **/ | |
5545 | static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu) | |
5546 | { | |
5547 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5548 | int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; | |
5549 | ||
42c783c5 | 5550 | /* MTU < 68 is an error and causes problems on some kernels */ |
655309e9 AD |
5551 | if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE)) |
5552 | return -EINVAL; | |
5553 | ||
5554 | /* | |
5555 | * For 82599EB we cannot allow PF to change MTU greater than 1500 | |
5556 | * in SR-IOV mode as it may cause buffer overruns in guest VFs that | |
5557 | * don't allocate and chain buffers correctly. | |
5558 | */ | |
5559 | if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && | |
5560 | (adapter->hw.mac.type == ixgbe_mac_82599EB) && | |
5561 | (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE)) | |
e9f98072 | 5562 | return -EINVAL; |
9a799d71 | 5563 | |
396e799c | 5564 | e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu); |
655309e9 | 5565 | |
021230d4 | 5566 | /* must set new MTU before calling down or up */ |
9a799d71 AK |
5567 | netdev->mtu = new_mtu; |
5568 | ||
d4f80882 AV |
5569 | if (netif_running(netdev)) |
5570 | ixgbe_reinit_locked(adapter); | |
9a799d71 AK |
5571 | |
5572 | return 0; | |
5573 | } | |
5574 | ||
5575 | /** | |
5576 | * ixgbe_open - Called when a network interface is made active | |
5577 | * @netdev: network interface device structure | |
5578 | * | |
5579 | * Returns 0 on success, negative value on failure | |
5580 | * | |
5581 | * The open entry point is called when a network interface is made | |
5582 | * active by the system (IFF_UP). At this point all resources needed | |
5583 | * for transmit and receive operations are allocated, the interrupt | |
5584 | * handler is registered with the OS, the watchdog timer is started, | |
5585 | * and the stack is notified that the interface is ready. | |
5586 | **/ | |
5587 | static int ixgbe_open(struct net_device *netdev) | |
5588 | { | |
5589 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
5590 | int err; | |
4bebfaa5 AK |
5591 | |
5592 | /* disallow open during test */ | |
5593 | if (test_bit(__IXGBE_TESTING, &adapter->state)) | |
5594 | return -EBUSY; | |
9a799d71 | 5595 | |
54386467 JB |
5596 | netif_carrier_off(netdev); |
5597 | ||
9a799d71 AK |
5598 | /* allocate transmit descriptors */ |
5599 | err = ixgbe_setup_all_tx_resources(adapter); | |
5600 | if (err) | |
5601 | goto err_setup_tx; | |
5602 | ||
9a799d71 AK |
5603 | /* allocate receive descriptors */ |
5604 | err = ixgbe_setup_all_rx_resources(adapter); | |
5605 | if (err) | |
5606 | goto err_setup_rx; | |
5607 | ||
5608 | ixgbe_configure(adapter); | |
5609 | ||
021230d4 | 5610 | err = ixgbe_request_irq(adapter); |
9a799d71 AK |
5611 | if (err) |
5612 | goto err_req_irq; | |
5613 | ||
c7ccde0f | 5614 | ixgbe_up_complete(adapter); |
9a799d71 AK |
5615 | |
5616 | return 0; | |
5617 | ||
9a799d71 | 5618 | err_req_irq: |
9a799d71 | 5619 | err_setup_rx: |
a20a1199 | 5620 | ixgbe_free_all_rx_resources(adapter); |
9a799d71 | 5621 | err_setup_tx: |
a20a1199 | 5622 | ixgbe_free_all_tx_resources(adapter); |
9a799d71 AK |
5623 | ixgbe_reset(adapter); |
5624 | ||
5625 | return err; | |
5626 | } | |
5627 | ||
5628 | /** | |
5629 | * ixgbe_close - Disables a network interface | |
5630 | * @netdev: network interface device structure | |
5631 | * | |
5632 | * Returns 0, this is not allowed to fail | |
5633 | * | |
5634 | * The close entry point is called when an interface is de-activated | |
5635 | * by the OS. The hardware is still under the drivers control, but | |
5636 | * needs to be disabled. A global MAC reset is issued to stop the | |
5637 | * hardware, and all transmit and receive resources are freed. | |
5638 | **/ | |
5639 | static int ixgbe_close(struct net_device *netdev) | |
5640 | { | |
5641 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
9a799d71 AK |
5642 | |
5643 | ixgbe_down(adapter); | |
5644 | ixgbe_free_irq(adapter); | |
5645 | ||
e4911d57 AD |
5646 | ixgbe_fdir_filter_exit(adapter); |
5647 | ||
9a799d71 AK |
5648 | ixgbe_free_all_tx_resources(adapter); |
5649 | ixgbe_free_all_rx_resources(adapter); | |
5650 | ||
5eba3699 | 5651 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
5652 | |
5653 | return 0; | |
5654 | } | |
5655 | ||
b3c8b4ba AD |
5656 | #ifdef CONFIG_PM |
5657 | static int ixgbe_resume(struct pci_dev *pdev) | |
5658 | { | |
c60fbb00 AD |
5659 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5660 | struct net_device *netdev = adapter->netdev; | |
b3c8b4ba AD |
5661 | u32 err; |
5662 | ||
5663 | pci_set_power_state(pdev, PCI_D0); | |
5664 | pci_restore_state(pdev); | |
656ab817 DS |
5665 | /* |
5666 | * pci_restore_state clears dev->state_saved so call | |
5667 | * pci_save_state to restore it. | |
5668 | */ | |
5669 | pci_save_state(pdev); | |
9ce77666 | 5670 | |
5671 | err = pci_enable_device_mem(pdev); | |
b3c8b4ba | 5672 | if (err) { |
849c4542 | 5673 | e_dev_err("Cannot enable PCI device from suspend\n"); |
b3c8b4ba AD |
5674 | return err; |
5675 | } | |
5676 | pci_set_master(pdev); | |
5677 | ||
dd4d8ca6 | 5678 | pci_wake_from_d3(pdev, false); |
b3c8b4ba AD |
5679 | |
5680 | err = ixgbe_init_interrupt_scheme(adapter); | |
5681 | if (err) { | |
849c4542 | 5682 | e_dev_err("Cannot initialize interrupts for device\n"); |
b3c8b4ba AD |
5683 | return err; |
5684 | } | |
5685 | ||
b3c8b4ba AD |
5686 | ixgbe_reset(adapter); |
5687 | ||
495dce12 WJP |
5688 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
5689 | ||
b3c8b4ba | 5690 | if (netif_running(netdev)) { |
c60fbb00 | 5691 | err = ixgbe_open(netdev); |
b3c8b4ba AD |
5692 | if (err) |
5693 | return err; | |
5694 | } | |
5695 | ||
5696 | netif_device_attach(netdev); | |
5697 | ||
5698 | return 0; | |
5699 | } | |
b3c8b4ba | 5700 | #endif /* CONFIG_PM */ |
9d8d05ae RW |
5701 | |
5702 | static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake) | |
b3c8b4ba | 5703 | { |
c60fbb00 AD |
5704 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
5705 | struct net_device *netdev = adapter->netdev; | |
e8e26350 PW |
5706 | struct ixgbe_hw *hw = &adapter->hw; |
5707 | u32 ctrl, fctrl; | |
5708 | u32 wufc = adapter->wol; | |
b3c8b4ba AD |
5709 | #ifdef CONFIG_PM |
5710 | int retval = 0; | |
5711 | #endif | |
5712 | ||
5713 | netif_device_detach(netdev); | |
5714 | ||
5715 | if (netif_running(netdev)) { | |
5716 | ixgbe_down(adapter); | |
5717 | ixgbe_free_irq(adapter); | |
5718 | ixgbe_free_all_tx_resources(adapter); | |
5719 | ixgbe_free_all_rx_resources(adapter); | |
5720 | } | |
b3c8b4ba | 5721 | |
5f5ae6fc | 5722 | ixgbe_clear_interrupt_scheme(adapter); |
d033d526 JF |
5723 | #ifdef CONFIG_DCB |
5724 | kfree(adapter->ixgbe_ieee_pfc); | |
5725 | kfree(adapter->ixgbe_ieee_ets); | |
5726 | #endif | |
5f5ae6fc | 5727 | |
b3c8b4ba AD |
5728 | #ifdef CONFIG_PM |
5729 | retval = pci_save_state(pdev); | |
5730 | if (retval) | |
5731 | return retval; | |
4df10466 | 5732 | |
b3c8b4ba | 5733 | #endif |
e8e26350 PW |
5734 | if (wufc) { |
5735 | ixgbe_set_rx_mode(netdev); | |
b3c8b4ba | 5736 | |
e8e26350 PW |
5737 | /* turn on all-multi mode if wake on multicast is enabled */ |
5738 | if (wufc & IXGBE_WUFC_MC) { | |
5739 | fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
5740 | fctrl |= IXGBE_FCTRL_MPE; | |
5741 | IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); | |
5742 | } | |
5743 | ||
5744 | ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); | |
5745 | ctrl |= IXGBE_CTRL_GIO_DIS; | |
5746 | IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); | |
5747 | ||
5748 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc); | |
5749 | } else { | |
5750 | IXGBE_WRITE_REG(hw, IXGBE_WUC, 0); | |
5751 | IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0); | |
5752 | } | |
5753 | ||
bd508178 AD |
5754 | switch (hw->mac.type) { |
5755 | case ixgbe_mac_82598EB: | |
dd4d8ca6 | 5756 | pci_wake_from_d3(pdev, false); |
bd508178 AD |
5757 | break; |
5758 | case ixgbe_mac_82599EB: | |
b93a2226 | 5759 | case ixgbe_mac_X540: |
bd508178 AD |
5760 | pci_wake_from_d3(pdev, !!wufc); |
5761 | break; | |
5762 | default: | |
5763 | break; | |
5764 | } | |
b3c8b4ba | 5765 | |
9d8d05ae RW |
5766 | *enable_wake = !!wufc; |
5767 | ||
b3c8b4ba AD |
5768 | ixgbe_release_hw_control(adapter); |
5769 | ||
5770 | pci_disable_device(pdev); | |
5771 | ||
9d8d05ae RW |
5772 | return 0; |
5773 | } | |
5774 | ||
5775 | #ifdef CONFIG_PM | |
5776 | static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state) | |
5777 | { | |
5778 | int retval; | |
5779 | bool wake; | |
5780 | ||
5781 | retval = __ixgbe_shutdown(pdev, &wake); | |
5782 | if (retval) | |
5783 | return retval; | |
5784 | ||
5785 | if (wake) { | |
5786 | pci_prepare_to_sleep(pdev); | |
5787 | } else { | |
5788 | pci_wake_from_d3(pdev, false); | |
5789 | pci_set_power_state(pdev, PCI_D3hot); | |
5790 | } | |
b3c8b4ba AD |
5791 | |
5792 | return 0; | |
5793 | } | |
9d8d05ae | 5794 | #endif /* CONFIG_PM */ |
b3c8b4ba AD |
5795 | |
5796 | static void ixgbe_shutdown(struct pci_dev *pdev) | |
5797 | { | |
9d8d05ae RW |
5798 | bool wake; |
5799 | ||
5800 | __ixgbe_shutdown(pdev, &wake); | |
5801 | ||
5802 | if (system_state == SYSTEM_POWER_OFF) { | |
5803 | pci_wake_from_d3(pdev, wake); | |
5804 | pci_set_power_state(pdev, PCI_D3hot); | |
5805 | } | |
b3c8b4ba AD |
5806 | } |
5807 | ||
9a799d71 AK |
5808 | /** |
5809 | * ixgbe_update_stats - Update the board statistics counters. | |
5810 | * @adapter: board private structure | |
5811 | **/ | |
5812 | void ixgbe_update_stats(struct ixgbe_adapter *adapter) | |
5813 | { | |
2d86f139 | 5814 | struct net_device *netdev = adapter->netdev; |
9a799d71 | 5815 | struct ixgbe_hw *hw = &adapter->hw; |
5b7da515 | 5816 | struct ixgbe_hw_stats *hwstats = &adapter->stats; |
6f11eef7 AV |
5817 | u64 total_mpc = 0; |
5818 | u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot; | |
5b7da515 AD |
5819 | u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0; |
5820 | u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0; | |
8a0da21b | 5821 | u64 bytes = 0, packets = 0, hw_csum_rx_error = 0; |
7b859ebc AH |
5822 | #ifdef IXGBE_FCOE |
5823 | struct ixgbe_fcoe *fcoe = &adapter->fcoe; | |
5824 | unsigned int cpu; | |
5825 | u64 fcoe_noddp_counts_sum = 0, fcoe_noddp_ext_buff_counts_sum = 0; | |
5826 | #endif /* IXGBE_FCOE */ | |
9a799d71 | 5827 | |
d08935c2 DS |
5828 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
5829 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
5830 | return; | |
5831 | ||
94b982b2 | 5832 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) { |
f8212f97 | 5833 | u64 rsc_count = 0; |
94b982b2 | 5834 | u64 rsc_flush = 0; |
d51019a4 PW |
5835 | for (i = 0; i < 16; i++) |
5836 | adapter->hw_rx_no_dma_resources += | |
7ca647bd | 5837 | IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); |
94b982b2 | 5838 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5b7da515 AD |
5839 | rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count; |
5840 | rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush; | |
94b982b2 MC |
5841 | } |
5842 | adapter->rsc_total_count = rsc_count; | |
5843 | adapter->rsc_total_flush = rsc_flush; | |
d51019a4 PW |
5844 | } |
5845 | ||
5b7da515 AD |
5846 | for (i = 0; i < adapter->num_rx_queues; i++) { |
5847 | struct ixgbe_ring *rx_ring = adapter->rx_ring[i]; | |
5848 | non_eop_descs += rx_ring->rx_stats.non_eop_descs; | |
5849 | alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed; | |
5850 | alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; | |
8a0da21b | 5851 | hw_csum_rx_error += rx_ring->rx_stats.csum_err; |
5b7da515 AD |
5852 | bytes += rx_ring->stats.bytes; |
5853 | packets += rx_ring->stats.packets; | |
5854 | } | |
5855 | adapter->non_eop_descs = non_eop_descs; | |
5856 | adapter->alloc_rx_page_failed = alloc_rx_page_failed; | |
5857 | adapter->alloc_rx_buff_failed = alloc_rx_buff_failed; | |
8a0da21b | 5858 | adapter->hw_csum_rx_error = hw_csum_rx_error; |
5b7da515 AD |
5859 | netdev->stats.rx_bytes = bytes; |
5860 | netdev->stats.rx_packets = packets; | |
5861 | ||
5862 | bytes = 0; | |
5863 | packets = 0; | |
7ca3bc58 | 5864 | /* gather some stats to the adapter struct that are per queue */ |
5b7da515 AD |
5865 | for (i = 0; i < adapter->num_tx_queues; i++) { |
5866 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; | |
5867 | restart_queue += tx_ring->tx_stats.restart_queue; | |
5868 | tx_busy += tx_ring->tx_stats.tx_busy; | |
5869 | bytes += tx_ring->stats.bytes; | |
5870 | packets += tx_ring->stats.packets; | |
5871 | } | |
eb985f09 | 5872 | adapter->restart_queue = restart_queue; |
5b7da515 AD |
5873 | adapter->tx_busy = tx_busy; |
5874 | netdev->stats.tx_bytes = bytes; | |
5875 | netdev->stats.tx_packets = packets; | |
7ca3bc58 | 5876 | |
7ca647bd | 5877 | hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS); |
1a70db4b ET |
5878 | |
5879 | /* 8 register reads */ | |
6f11eef7 AV |
5880 | for (i = 0; i < 8; i++) { |
5881 | /* for packet buffers not used, the register should read 0 */ | |
5882 | mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i)); | |
5883 | missed_rx += mpc; | |
7ca647bd JP |
5884 | hwstats->mpc[i] += mpc; |
5885 | total_mpc += hwstats->mpc[i]; | |
1a70db4b ET |
5886 | hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); |
5887 | hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); | |
bd508178 AD |
5888 | switch (hw->mac.type) { |
5889 | case ixgbe_mac_82598EB: | |
1a70db4b ET |
5890 | hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i)); |
5891 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i)); | |
5892 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i)); | |
7ca647bd JP |
5893 | hwstats->pxonrxc[i] += |
5894 | IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); | |
bd508178 AD |
5895 | break; |
5896 | case ixgbe_mac_82599EB: | |
b93a2226 | 5897 | case ixgbe_mac_X540: |
bd508178 AD |
5898 | hwstats->pxonrxc[i] += |
5899 | IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); | |
bd508178 AD |
5900 | break; |
5901 | default: | |
5902 | break; | |
e8e26350 | 5903 | } |
6f11eef7 | 5904 | } |
1a70db4b ET |
5905 | |
5906 | /*16 register reads */ | |
5907 | for (i = 0; i < 16; i++) { | |
5908 | hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i)); | |
5909 | hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i)); | |
5910 | if ((hw->mac.type == ixgbe_mac_82599EB) || | |
5911 | (hw->mac.type == ixgbe_mac_X540)) { | |
5912 | hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); | |
5913 | IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */ | |
5914 | hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); | |
5915 | IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */ | |
5916 | } | |
5917 | } | |
5918 | ||
7ca647bd | 5919 | hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC); |
6f11eef7 | 5920 | /* work around hardware counting issue */ |
7ca647bd | 5921 | hwstats->gprc -= missed_rx; |
6f11eef7 | 5922 | |
c84d324c JF |
5923 | ixgbe_update_xoff_received(adapter); |
5924 | ||
6f11eef7 | 5925 | /* 82598 hardware only has a 32 bit counter in the high register */ |
bd508178 AD |
5926 | switch (hw->mac.type) { |
5927 | case ixgbe_mac_82598EB: | |
5928 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC); | |
bd508178 AD |
5929 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH); |
5930 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH); | |
5931 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH); | |
5932 | break; | |
b93a2226 | 5933 | case ixgbe_mac_X540: |
58f6bcf9 ET |
5934 | /* OS2BMC stats are X540 only*/ |
5935 | hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC); | |
5936 | hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC); | |
5937 | hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC); | |
5938 | hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC); | |
5939 | case ixgbe_mac_82599EB: | |
7ca647bd | 5940 | hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL); |
bd508178 | 5941 | IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */ |
7ca647bd | 5942 | hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL); |
bd508178 | 5943 | IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */ |
7ca647bd | 5944 | hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL); |
bd508178 | 5945 | IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */ |
7ca647bd | 5946 | hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); |
7ca647bd JP |
5947 | hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH); |
5948 | hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS); | |
6d45522c | 5949 | #ifdef IXGBE_FCOE |
7ca647bd JP |
5950 | hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC); |
5951 | hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC); | |
5952 | hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC); | |
5953 | hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC); | |
5954 | hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC); | |
5955 | hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC); | |
7b859ebc AH |
5956 | /* Add up per cpu counters for total ddp aloc fail */ |
5957 | if (fcoe->pcpu_noddp && fcoe->pcpu_noddp_ext_buff) { | |
5958 | for_each_possible_cpu(cpu) { | |
5959 | fcoe_noddp_counts_sum += | |
5960 | *per_cpu_ptr(fcoe->pcpu_noddp, cpu); | |
5961 | fcoe_noddp_ext_buff_counts_sum += | |
5962 | *per_cpu_ptr(fcoe-> | |
5963 | pcpu_noddp_ext_buff, cpu); | |
5964 | } | |
5965 | } | |
5966 | hwstats->fcoe_noddp = fcoe_noddp_counts_sum; | |
5967 | hwstats->fcoe_noddp_ext_buff = fcoe_noddp_ext_buff_counts_sum; | |
6d45522c | 5968 | #endif /* IXGBE_FCOE */ |
bd508178 AD |
5969 | break; |
5970 | default: | |
5971 | break; | |
e8e26350 | 5972 | } |
9a799d71 | 5973 | bprc = IXGBE_READ_REG(hw, IXGBE_BPRC); |
7ca647bd JP |
5974 | hwstats->bprc += bprc; |
5975 | hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC); | |
e8e26350 | 5976 | if (hw->mac.type == ixgbe_mac_82598EB) |
7ca647bd JP |
5977 | hwstats->mprc -= bprc; |
5978 | hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC); | |
5979 | hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64); | |
5980 | hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127); | |
5981 | hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255); | |
5982 | hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511); | |
5983 | hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023); | |
5984 | hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522); | |
5985 | hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC); | |
6f11eef7 | 5986 | lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC); |
7ca647bd | 5987 | hwstats->lxontxc += lxon; |
6f11eef7 | 5988 | lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); |
7ca647bd | 5989 | hwstats->lxofftxc += lxoff; |
7ca647bd JP |
5990 | hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC); |
5991 | hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC); | |
6f11eef7 AV |
5992 | /* |
5993 | * 82598 errata - tx of flow control packets is included in tx counters | |
5994 | */ | |
5995 | xon_off_tot = lxon + lxoff; | |
7ca647bd JP |
5996 | hwstats->gptc -= xon_off_tot; |
5997 | hwstats->mptc -= xon_off_tot; | |
5998 | hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN)); | |
5999 | hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC); | |
6000 | hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC); | |
6001 | hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC); | |
6002 | hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR); | |
6003 | hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64); | |
6004 | hwstats->ptc64 -= xon_off_tot; | |
6005 | hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127); | |
6006 | hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255); | |
6007 | hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511); | |
6008 | hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023); | |
6009 | hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522); | |
6010 | hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC); | |
9a799d71 AK |
6011 | |
6012 | /* Fill out the OS statistics structure */ | |
7ca647bd | 6013 | netdev->stats.multicast = hwstats->mprc; |
9a799d71 AK |
6014 | |
6015 | /* Rx Errors */ | |
7ca647bd | 6016 | netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec; |
2d86f139 | 6017 | netdev->stats.rx_dropped = 0; |
7ca647bd JP |
6018 | netdev->stats.rx_length_errors = hwstats->rlec; |
6019 | netdev->stats.rx_crc_errors = hwstats->crcerrs; | |
2d86f139 | 6020 | netdev->stats.rx_missed_errors = total_mpc; |
9a799d71 AK |
6021 | } |
6022 | ||
6023 | /** | |
d034acf1 AD |
6024 | * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table |
6025 | * @adapter - pointer to the device adapter structure | |
9a799d71 | 6026 | **/ |
d034acf1 | 6027 | static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter) |
9a799d71 | 6028 | { |
cf8280ee | 6029 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a | 6030 | int i; |
cf8280ee | 6031 | |
d034acf1 AD |
6032 | if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT)) |
6033 | return; | |
6034 | ||
6035 | adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT; | |
22d5a71b | 6036 | |
d034acf1 | 6037 | /* if interface is down do nothing */ |
fe49f04a | 6038 | if (test_bit(__IXGBE_DOWN, &adapter->state)) |
d034acf1 AD |
6039 | return; |
6040 | ||
6041 | /* do nothing if we are not using signature filters */ | |
6042 | if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) | |
6043 | return; | |
6044 | ||
6045 | adapter->fdir_overflow++; | |
6046 | ||
93c52dd0 AD |
6047 | if (ixgbe_reinit_fdir_tables_82599(hw) == 0) { |
6048 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6049 | set_bit(__IXGBE_TX_FDIR_INIT_DONE, | |
f0f9778d | 6050 | &(adapter->tx_ring[i]->state)); |
d034acf1 AD |
6051 | /* re-enable flow director interrupts */ |
6052 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR); | |
93c52dd0 AD |
6053 | } else { |
6054 | e_err(probe, "failed to finish FDIR re-initialization, " | |
6055 | "ignored adding FDIR ATR filters\n"); | |
6056 | } | |
93c52dd0 AD |
6057 | } |
6058 | ||
6059 | /** | |
6060 | * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts | |
6061 | * @adapter - pointer to the device adapter structure | |
6062 | * | |
6063 | * This function serves two purposes. First it strobes the interrupt lines | |
52f33af8 | 6064 | * in order to make certain interrupts are occurring. Secondly it sets the |
93c52dd0 | 6065 | * bits needed to check for TX hangs. As a result we should immediately |
52f33af8 | 6066 | * determine if a hang has occurred. |
93c52dd0 AD |
6067 | */ |
6068 | static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter) | |
9a799d71 | 6069 | { |
cf8280ee | 6070 | struct ixgbe_hw *hw = &adapter->hw; |
fe49f04a AD |
6071 | u64 eics = 0; |
6072 | int i; | |
cf8280ee | 6073 | |
93c52dd0 AD |
6074 | /* If we're down or resetting, just bail */ |
6075 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6076 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6077 | return; | |
22d5a71b | 6078 | |
93c52dd0 AD |
6079 | /* Force detection of hung controller */ |
6080 | if (netif_carrier_ok(adapter->netdev)) { | |
6081 | for (i = 0; i < adapter->num_tx_queues; i++) | |
6082 | set_check_for_tx_hang(adapter->tx_ring[i]); | |
6083 | } | |
22d5a71b | 6084 | |
fe49f04a AD |
6085 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { |
6086 | /* | |
6087 | * for legacy and MSI interrupts don't set any bits | |
6088 | * that are enabled for EIAM, because this operation | |
6089 | * would set *both* EIMS and EICS for any bit in EIAM | |
6090 | */ | |
6091 | IXGBE_WRITE_REG(hw, IXGBE_EICS, | |
6092 | (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER)); | |
93c52dd0 AD |
6093 | } else { |
6094 | /* get one bit for every active tx/rx interrupt vector */ | |
6095 | for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) { | |
6096 | struct ixgbe_q_vector *qv = adapter->q_vector[i]; | |
efe3d3c8 | 6097 | if (qv->rx.ring || qv->tx.ring) |
93c52dd0 AD |
6098 | eics |= ((u64)1 << i); |
6099 | } | |
cf8280ee | 6100 | } |
9a799d71 | 6101 | |
93c52dd0 | 6102 | /* Cause software interrupt to ensure rings are cleaned */ |
fe49f04a AD |
6103 | ixgbe_irq_rearm_queues(adapter, eics); |
6104 | ||
cf8280ee JB |
6105 | } |
6106 | ||
e8e26350 | 6107 | /** |
93c52dd0 AD |
6108 | * ixgbe_watchdog_update_link - update the link status |
6109 | * @adapter - pointer to the device adapter structure | |
6110 | * @link_speed - pointer to a u32 to store the link_speed | |
e8e26350 | 6111 | **/ |
93c52dd0 | 6112 | static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter) |
e8e26350 | 6113 | { |
e8e26350 | 6114 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6115 | u32 link_speed = adapter->link_speed; |
6116 | bool link_up = adapter->link_up; | |
c4cf55e5 | 6117 | int i; |
e8e26350 | 6118 | |
93c52dd0 AD |
6119 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) |
6120 | return; | |
6121 | ||
6122 | if (hw->mac.ops.check_link) { | |
6123 | hw->mac.ops.check_link(hw, &link_speed, &link_up, false); | |
c4cf55e5 | 6124 | } else { |
93c52dd0 AD |
6125 | /* always assume link is up, if no check link function */ |
6126 | link_speed = IXGBE_LINK_SPEED_10GB_FULL; | |
6127 | link_up = true; | |
c4cf55e5 | 6128 | } |
93c52dd0 AD |
6129 | if (link_up) { |
6130 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) { | |
6131 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) | |
6132 | hw->mac.ops.fc_enable(hw, i); | |
6133 | } else { | |
6134 | hw->mac.ops.fc_enable(hw, 0); | |
6135 | } | |
6136 | } | |
6137 | ||
6138 | if (link_up || | |
6139 | time_after(jiffies, (adapter->link_check_timeout + | |
6140 | IXGBE_TRY_LINK_TIMEOUT))) { | |
6141 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE; | |
6142 | IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC); | |
6143 | IXGBE_WRITE_FLUSH(hw); | |
6144 | } | |
6145 | ||
6146 | adapter->link_up = link_up; | |
6147 | adapter->link_speed = link_speed; | |
e8e26350 PW |
6148 | } |
6149 | ||
6150 | /** | |
93c52dd0 AD |
6151 | * ixgbe_watchdog_link_is_up - update netif_carrier status and |
6152 | * print link up message | |
6153 | * @adapter - pointer to the device adapter structure | |
e8e26350 | 6154 | **/ |
93c52dd0 | 6155 | static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter) |
e8e26350 | 6156 | { |
93c52dd0 | 6157 | struct net_device *netdev = adapter->netdev; |
e8e26350 | 6158 | struct ixgbe_hw *hw = &adapter->hw; |
93c52dd0 AD |
6159 | u32 link_speed = adapter->link_speed; |
6160 | bool flow_rx, flow_tx; | |
e8e26350 | 6161 | |
93c52dd0 AD |
6162 | /* only continue if link was previously down */ |
6163 | if (netif_carrier_ok(netdev)) | |
a985b6c3 | 6164 | return; |
63d6e1d8 | 6165 | |
93c52dd0 | 6166 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
63d6e1d8 | 6167 | |
93c52dd0 AD |
6168 | switch (hw->mac.type) { |
6169 | case ixgbe_mac_82598EB: { | |
6170 | u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL); | |
6171 | u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS); | |
6172 | flow_rx = !!(frctl & IXGBE_FCTRL_RFCE); | |
6173 | flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X); | |
6174 | } | |
6175 | break; | |
6176 | case ixgbe_mac_X540: | |
6177 | case ixgbe_mac_82599EB: { | |
6178 | u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN); | |
6179 | u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG); | |
6180 | flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE); | |
6181 | flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X); | |
6182 | } | |
6183 | break; | |
6184 | default: | |
6185 | flow_tx = false; | |
6186 | flow_rx = false; | |
6187 | break; | |
e8e26350 | 6188 | } |
93c52dd0 AD |
6189 | e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", |
6190 | (link_speed == IXGBE_LINK_SPEED_10GB_FULL ? | |
6191 | "10 Gbps" : | |
6192 | (link_speed == IXGBE_LINK_SPEED_1GB_FULL ? | |
6193 | "1 Gbps" : | |
6194 | (link_speed == IXGBE_LINK_SPEED_100_FULL ? | |
6195 | "100 Mbps" : | |
6196 | "unknown speed"))), | |
6197 | ((flow_rx && flow_tx) ? "RX/TX" : | |
6198 | (flow_rx ? "RX" : | |
6199 | (flow_tx ? "TX" : "None")))); | |
e8e26350 | 6200 | |
93c52dd0 | 6201 | netif_carrier_on(netdev); |
93c52dd0 | 6202 | ixgbe_check_vf_rate_limit(adapter); |
e8e26350 PW |
6203 | } |
6204 | ||
c4cf55e5 | 6205 | /** |
93c52dd0 AD |
6206 | * ixgbe_watchdog_link_is_down - update netif_carrier status and |
6207 | * print link down message | |
6208 | * @adapter - pointer to the adapter structure | |
c4cf55e5 | 6209 | **/ |
93c52dd0 | 6210 | static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter) |
c4cf55e5 | 6211 | { |
cf8280ee | 6212 | struct net_device *netdev = adapter->netdev; |
c4cf55e5 | 6213 | struct ixgbe_hw *hw = &adapter->hw; |
10eec955 | 6214 | |
93c52dd0 AD |
6215 | adapter->link_up = false; |
6216 | adapter->link_speed = 0; | |
cf8280ee | 6217 | |
93c52dd0 AD |
6218 | /* only continue if link was up previously */ |
6219 | if (!netif_carrier_ok(netdev)) | |
6220 | return; | |
264857b8 | 6221 | |
93c52dd0 AD |
6222 | /* poll for SFP+ cable when link is down */ |
6223 | if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB) | |
6224 | adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP; | |
9a799d71 | 6225 | |
93c52dd0 AD |
6226 | e_info(drv, "NIC Link is Down\n"); |
6227 | netif_carrier_off(netdev); | |
6228 | } | |
e8e26350 | 6229 | |
93c52dd0 AD |
6230 | /** |
6231 | * ixgbe_watchdog_flush_tx - flush queues on link down | |
6232 | * @adapter - pointer to the device adapter structure | |
6233 | **/ | |
6234 | static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter) | |
6235 | { | |
c4cf55e5 | 6236 | int i; |
93c52dd0 | 6237 | int some_tx_pending = 0; |
c4cf55e5 | 6238 | |
93c52dd0 | 6239 | if (!netif_carrier_ok(adapter->netdev)) { |
bc59fcda | 6240 | for (i = 0; i < adapter->num_tx_queues; i++) { |
93c52dd0 | 6241 | struct ixgbe_ring *tx_ring = adapter->tx_ring[i]; |
bc59fcda NS |
6242 | if (tx_ring->next_to_use != tx_ring->next_to_clean) { |
6243 | some_tx_pending = 1; | |
6244 | break; | |
6245 | } | |
6246 | } | |
6247 | ||
6248 | if (some_tx_pending) { | |
6249 | /* We've lost link, so the controller stops DMA, | |
6250 | * but we've got queued Tx work that's never going | |
6251 | * to get done, so reset controller to flush Tx. | |
6252 | * (Do the reset outside of interrupt context). | |
6253 | */ | |
c83c6cbd | 6254 | adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED; |
bc59fcda | 6255 | } |
c4cf55e5 | 6256 | } |
c4cf55e5 PWJ |
6257 | } |
6258 | ||
a985b6c3 GR |
6259 | static void ixgbe_spoof_check(struct ixgbe_adapter *adapter) |
6260 | { | |
6261 | u32 ssvpc; | |
6262 | ||
6263 | /* Do not perform spoof check for 82598 */ | |
6264 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
6265 | return; | |
6266 | ||
6267 | ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC); | |
6268 | ||
6269 | /* | |
6270 | * ssvpc register is cleared on read, if zero then no | |
6271 | * spoofed packets in the last interval. | |
6272 | */ | |
6273 | if (!ssvpc) | |
6274 | return; | |
6275 | ||
6276 | e_warn(drv, "%d Spoofed packets detected\n", ssvpc); | |
6277 | } | |
6278 | ||
93c52dd0 AD |
6279 | /** |
6280 | * ixgbe_watchdog_subtask - check and bring link up | |
6281 | * @adapter - pointer to the device adapter structure | |
6282 | **/ | |
6283 | static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter) | |
6284 | { | |
6285 | /* if interface is down do nothing */ | |
7edebf9a ET |
6286 | if (test_bit(__IXGBE_DOWN, &adapter->state) || |
6287 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
93c52dd0 AD |
6288 | return; |
6289 | ||
6290 | ixgbe_watchdog_update_link(adapter); | |
6291 | ||
6292 | if (adapter->link_up) | |
6293 | ixgbe_watchdog_link_is_up(adapter); | |
6294 | else | |
6295 | ixgbe_watchdog_link_is_down(adapter); | |
bc59fcda | 6296 | |
a985b6c3 | 6297 | ixgbe_spoof_check(adapter); |
9a799d71 | 6298 | ixgbe_update_stats(adapter); |
93c52dd0 AD |
6299 | |
6300 | ixgbe_watchdog_flush_tx(adapter); | |
9a799d71 | 6301 | } |
10eec955 | 6302 | |
cf8280ee | 6303 | /** |
7086400d AD |
6304 | * ixgbe_sfp_detection_subtask - poll for SFP+ cable |
6305 | * @adapter - the ixgbe adapter structure | |
cf8280ee | 6306 | **/ |
7086400d | 6307 | static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter) |
cf8280ee | 6308 | { |
cf8280ee | 6309 | struct ixgbe_hw *hw = &adapter->hw; |
7086400d | 6310 | s32 err; |
cf8280ee | 6311 | |
7086400d AD |
6312 | /* not searching for SFP so there is nothing to do here */ |
6313 | if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) && | |
6314 | !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6315 | return; | |
10eec955 | 6316 | |
7086400d AD |
6317 | /* someone else is in init, wait until next service event */ |
6318 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6319 | return; | |
cf8280ee | 6320 | |
7086400d AD |
6321 | err = hw->phy.ops.identify_sfp(hw); |
6322 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6323 | goto sfp_out; | |
264857b8 | 6324 | |
7086400d AD |
6325 | if (err == IXGBE_ERR_SFP_NOT_PRESENT) { |
6326 | /* If no cable is present, then we need to reset | |
6327 | * the next time we find a good cable. */ | |
6328 | adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET; | |
cf8280ee | 6329 | } |
9a799d71 | 6330 | |
7086400d AD |
6331 | /* exit on error */ |
6332 | if (err) | |
6333 | goto sfp_out; | |
e8e26350 | 6334 | |
7086400d AD |
6335 | /* exit if reset not needed */ |
6336 | if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET)) | |
6337 | goto sfp_out; | |
9a799d71 | 6338 | |
7086400d | 6339 | adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET; |
bc59fcda | 6340 | |
7086400d AD |
6341 | /* |
6342 | * A module may be identified correctly, but the EEPROM may not have | |
6343 | * support for that module. setup_sfp() will fail in that case, so | |
6344 | * we should not allow that module to load. | |
6345 | */ | |
6346 | if (hw->mac.type == ixgbe_mac_82598EB) | |
6347 | err = hw->phy.ops.reset(hw); | |
6348 | else | |
6349 | err = hw->mac.ops.setup_sfp(hw); | |
6350 | ||
6351 | if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) | |
6352 | goto sfp_out; | |
6353 | ||
6354 | adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG; | |
6355 | e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type); | |
6356 | ||
6357 | sfp_out: | |
6358 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6359 | ||
6360 | if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) && | |
6361 | (adapter->netdev->reg_state == NETREG_REGISTERED)) { | |
6362 | e_dev_err("failed to initialize because an unsupported " | |
6363 | "SFP+ module type was detected.\n"); | |
6364 | e_dev_err("Reload the driver after installing a " | |
6365 | "supported module.\n"); | |
6366 | unregister_netdev(adapter->netdev); | |
bc59fcda | 6367 | } |
7086400d | 6368 | } |
bc59fcda | 6369 | |
7086400d AD |
6370 | /** |
6371 | * ixgbe_sfp_link_config_subtask - set up link SFP after module install | |
6372 | * @adapter - the ixgbe adapter structure | |
6373 | **/ | |
6374 | static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter) | |
6375 | { | |
6376 | struct ixgbe_hw *hw = &adapter->hw; | |
6377 | u32 autoneg; | |
6378 | bool negotiation; | |
6379 | ||
6380 | if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG)) | |
6381 | return; | |
6382 | ||
6383 | /* someone else is in init, wait until next service event */ | |
6384 | if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state)) | |
6385 | return; | |
6386 | ||
6387 | adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG; | |
6388 | ||
6389 | autoneg = hw->phy.autoneg_advertised; | |
6390 | if ((!autoneg) && (hw->mac.ops.get_link_capabilities)) | |
6391 | hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation); | |
7086400d AD |
6392 | if (hw->mac.ops.setup_link) |
6393 | hw->mac.ops.setup_link(hw, autoneg, negotiation, true); | |
6394 | ||
6395 | adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE; | |
6396 | adapter->link_check_timeout = jiffies; | |
6397 | clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state); | |
6398 | } | |
6399 | ||
83c61fa9 GR |
6400 | #ifdef CONFIG_PCI_IOV |
6401 | static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter) | |
6402 | { | |
6403 | int vf; | |
6404 | struct ixgbe_hw *hw = &adapter->hw; | |
6405 | struct net_device *netdev = adapter->netdev; | |
6406 | u32 gpc; | |
6407 | u32 ciaa, ciad; | |
6408 | ||
6409 | gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC); | |
6410 | if (gpc) /* If incrementing then no need for the check below */ | |
6411 | return; | |
6412 | /* | |
6413 | * Check to see if a bad DMA write target from an errant or | |
6414 | * malicious VF has caused a PCIe error. If so then we can | |
6415 | * issue a VFLR to the offending VF(s) and then resume without | |
6416 | * requesting a full slot reset. | |
6417 | */ | |
6418 | ||
6419 | for (vf = 0; vf < adapter->num_vfs; vf++) { | |
6420 | ciaa = (vf << 16) | 0x80000000; | |
6421 | /* 32 bit read so align, we really want status at offset 6 */ | |
6422 | ciaa |= PCI_COMMAND; | |
6423 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6424 | ciad = IXGBE_READ_REG(hw, IXGBE_CIAD_82599); | |
6425 | ciaa &= 0x7FFFFFFF; | |
6426 | /* disable debug mode asap after reading data */ | |
6427 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6428 | /* Get the upper 16 bits which will be the PCI status reg */ | |
6429 | ciad >>= 16; | |
6430 | if (ciad & PCI_STATUS_REC_MASTER_ABORT) { | |
6431 | netdev_err(netdev, "VF %d Hung DMA\n", vf); | |
6432 | /* Issue VFLR */ | |
6433 | ciaa = (vf << 16) | 0x80000000; | |
6434 | ciaa |= 0xA8; | |
6435 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6436 | ciad = 0x00008000; /* VFLR */ | |
6437 | IXGBE_WRITE_REG(hw, IXGBE_CIAD_82599, ciad); | |
6438 | ciaa &= 0x7FFFFFFF; | |
6439 | IXGBE_WRITE_REG(hw, IXGBE_CIAA_82599, ciaa); | |
6440 | } | |
6441 | } | |
6442 | } | |
6443 | ||
6444 | #endif | |
7086400d AD |
6445 | /** |
6446 | * ixgbe_service_timer - Timer Call-back | |
6447 | * @data: pointer to adapter cast into an unsigned long | |
6448 | **/ | |
6449 | static void ixgbe_service_timer(unsigned long data) | |
6450 | { | |
6451 | struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data; | |
6452 | unsigned long next_event_offset; | |
83c61fa9 | 6453 | bool ready = true; |
7086400d | 6454 | |
83c61fa9 GR |
6455 | #ifdef CONFIG_PCI_IOV |
6456 | ready = false; | |
6457 | ||
6458 | /* | |
6459 | * don't bother with SR-IOV VF DMA hang check if there are | |
6460 | * no VFs or the link is down | |
6461 | */ | |
6462 | if (!adapter->num_vfs || | |
6463 | (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)) { | |
6464 | ready = true; | |
6465 | goto normal_timer_service; | |
6466 | } | |
6467 | ||
6468 | /* If we have VFs allocated then we must check for DMA hangs */ | |
6469 | ixgbe_check_for_bad_vf(adapter); | |
6470 | next_event_offset = HZ / 50; | |
6471 | adapter->timer_event_accumulator++; | |
6472 | ||
6473 | if (adapter->timer_event_accumulator >= 100) { | |
6474 | ready = true; | |
6475 | adapter->timer_event_accumulator = 0; | |
6476 | } | |
6477 | ||
6478 | goto schedule_event; | |
6479 | ||
6480 | normal_timer_service: | |
6481 | #endif | |
7086400d AD |
6482 | /* poll faster when waiting for link */ |
6483 | if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) | |
6484 | next_event_offset = HZ / 10; | |
6485 | else | |
6486 | next_event_offset = HZ * 2; | |
6487 | ||
83c61fa9 GR |
6488 | #ifdef CONFIG_PCI_IOV |
6489 | schedule_event: | |
6490 | #endif | |
7086400d AD |
6491 | /* Reset the timer */ |
6492 | mod_timer(&adapter->service_timer, next_event_offset + jiffies); | |
6493 | ||
83c61fa9 GR |
6494 | if (ready) |
6495 | ixgbe_service_event_schedule(adapter); | |
7086400d AD |
6496 | } |
6497 | ||
c83c6cbd AD |
6498 | static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter) |
6499 | { | |
6500 | if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED)) | |
6501 | return; | |
6502 | ||
6503 | adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED; | |
6504 | ||
6505 | /* If we're already down or resetting, just bail */ | |
6506 | if (test_bit(__IXGBE_DOWN, &adapter->state) || | |
6507 | test_bit(__IXGBE_RESETTING, &adapter->state)) | |
6508 | return; | |
6509 | ||
6510 | ixgbe_dump(adapter); | |
6511 | netdev_err(adapter->netdev, "Reset adapter\n"); | |
6512 | adapter->tx_timeout_count++; | |
6513 | ||
6514 | ixgbe_reinit_locked(adapter); | |
6515 | } | |
6516 | ||
7086400d AD |
6517 | /** |
6518 | * ixgbe_service_task - manages and runs subtasks | |
6519 | * @work: pointer to work_struct containing our data | |
6520 | **/ | |
6521 | static void ixgbe_service_task(struct work_struct *work) | |
6522 | { | |
6523 | struct ixgbe_adapter *adapter = container_of(work, | |
6524 | struct ixgbe_adapter, | |
6525 | service_task); | |
6526 | ||
c83c6cbd | 6527 | ixgbe_reset_subtask(adapter); |
7086400d AD |
6528 | ixgbe_sfp_detection_subtask(adapter); |
6529 | ixgbe_sfp_link_config_subtask(adapter); | |
f0f9778d | 6530 | ixgbe_check_overtemp_subtask(adapter); |
93c52dd0 | 6531 | ixgbe_watchdog_subtask(adapter); |
d034acf1 | 6532 | ixgbe_fdir_reinit_subtask(adapter); |
93c52dd0 | 6533 | ixgbe_check_hang_subtask(adapter); |
7086400d AD |
6534 | |
6535 | ixgbe_service_event_complete(adapter); | |
9a799d71 AK |
6536 | } |
6537 | ||
897ab156 AD |
6538 | void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens, |
6539 | u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx) | |
9a799d71 AK |
6540 | { |
6541 | struct ixgbe_adv_tx_context_desc *context_desc; | |
897ab156 | 6542 | u16 i = tx_ring->next_to_use; |
9a799d71 | 6543 | |
e4f74028 | 6544 | context_desc = IXGBE_TX_CTXTDESC(tx_ring, i); |
9a799d71 | 6545 | |
897ab156 AD |
6546 | i++; |
6547 | tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; | |
9a799d71 | 6548 | |
897ab156 AD |
6549 | /* set bits to identify this as an advanced context descriptor */ |
6550 | type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT; | |
9a799d71 | 6551 | |
897ab156 AD |
6552 | context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); |
6553 | context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof); | |
6554 | context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); | |
6555 | context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); | |
6556 | } | |
9a799d71 | 6557 | |
fd0db0ed AD |
6558 | static int ixgbe_tso(struct ixgbe_ring *tx_ring, |
6559 | struct ixgbe_tx_buffer *first, | |
897ab156 AD |
6560 | u32 tx_flags, __be16 protocol, u8 *hdr_len) |
6561 | { | |
fd0db0ed | 6562 | struct sk_buff *skb = first->skb; |
897ab156 AD |
6563 | int err; |
6564 | u32 vlan_macip_lens, type_tucmd; | |
6565 | u32 mss_l4len_idx, l4len; | |
9a799d71 | 6566 | |
897ab156 AD |
6567 | if (!skb_is_gso(skb)) |
6568 | return 0; | |
9a799d71 | 6569 | |
897ab156 AD |
6570 | if (skb_header_cloned(skb)) { |
6571 | err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); | |
6572 | if (err) | |
6573 | return err; | |
9a799d71 | 6574 | } |
9a799d71 | 6575 | |
897ab156 AD |
6576 | /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ |
6577 | type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP; | |
6578 | ||
6579 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6580 | struct iphdr *iph = ip_hdr(skb); | |
6581 | iph->tot_len = 0; | |
6582 | iph->check = 0; | |
6583 | tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, | |
6584 | iph->daddr, 0, | |
6585 | IPPROTO_TCP, | |
6586 | 0); | |
6587 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6588 | } else if (skb_is_gso_v6(skb)) { | |
6589 | ipv6_hdr(skb)->payload_len = 0; | |
6590 | tcp_hdr(skb)->check = | |
6591 | ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, | |
6592 | &ipv6_hdr(skb)->daddr, | |
6593 | 0, IPPROTO_TCP, 0); | |
6594 | } | |
6595 | ||
6596 | l4len = tcp_hdrlen(skb); | |
6597 | *hdr_len = skb_transport_offset(skb) + l4len; | |
6598 | ||
6599 | /* mss_l4len_id: use 1 as index for TSO */ | |
6600 | mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT; | |
6601 | mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT; | |
6602 | mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT; | |
6603 | ||
6604 | /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */ | |
6605 | vlan_macip_lens = skb_network_header_len(skb); | |
6606 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; | |
6607 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
6608 | ||
6609 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd, | |
6610 | mss_l4len_idx); | |
6611 | ||
6612 | return 1; | |
6613 | } | |
6614 | ||
6615 | static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring, | |
fd0db0ed AD |
6616 | struct ixgbe_tx_buffer *first, |
6617 | u32 tx_flags, __be16 protocol) | |
7ca647bd | 6618 | { |
fd0db0ed | 6619 | struct sk_buff *skb = first->skb; |
897ab156 AD |
6620 | u32 vlan_macip_lens = 0; |
6621 | u32 mss_l4len_idx = 0; | |
6622 | u32 type_tucmd = 0; | |
7ca647bd | 6623 | |
897ab156 | 6624 | if (skb->ip_summed != CHECKSUM_PARTIAL) { |
7f9643fd AD |
6625 | if (!(tx_flags & IXGBE_TX_FLAGS_HW_VLAN) && |
6626 | !(tx_flags & IXGBE_TX_FLAGS_TXSW)) | |
897ab156 AD |
6627 | return false; |
6628 | } else { | |
6629 | u8 l4_hdr = 0; | |
6630 | switch (protocol) { | |
6631 | case __constant_htons(ETH_P_IP): | |
6632 | vlan_macip_lens |= skb_network_header_len(skb); | |
6633 | type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4; | |
6634 | l4_hdr = ip_hdr(skb)->protocol; | |
7ca647bd | 6635 | break; |
897ab156 AD |
6636 | case __constant_htons(ETH_P_IPV6): |
6637 | vlan_macip_lens |= skb_network_header_len(skb); | |
6638 | l4_hdr = ipv6_hdr(skb)->nexthdr; | |
6639 | break; | |
6640 | default: | |
6641 | if (unlikely(net_ratelimit())) { | |
6642 | dev_warn(tx_ring->dev, | |
6643 | "partial checksum but proto=%x!\n", | |
6644 | skb->protocol); | |
6645 | } | |
7ca647bd JP |
6646 | break; |
6647 | } | |
897ab156 AD |
6648 | |
6649 | switch (l4_hdr) { | |
7ca647bd | 6650 | case IPPROTO_TCP: |
897ab156 AD |
6651 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP; |
6652 | mss_l4len_idx = tcp_hdrlen(skb) << | |
6653 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
7ca647bd JP |
6654 | break; |
6655 | case IPPROTO_SCTP: | |
897ab156 AD |
6656 | type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP; |
6657 | mss_l4len_idx = sizeof(struct sctphdr) << | |
6658 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6659 | break; | |
6660 | case IPPROTO_UDP: | |
6661 | mss_l4len_idx = sizeof(struct udphdr) << | |
6662 | IXGBE_ADVTXD_L4LEN_SHIFT; | |
6663 | break; | |
6664 | default: | |
6665 | if (unlikely(net_ratelimit())) { | |
6666 | dev_warn(tx_ring->dev, | |
6667 | "partial checksum but l4 proto=%x!\n", | |
6668 | skb->protocol); | |
6669 | } | |
7ca647bd JP |
6670 | break; |
6671 | } | |
7ca647bd JP |
6672 | } |
6673 | ||
897ab156 AD |
6674 | vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT; |
6675 | vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK; | |
9a799d71 | 6676 | |
897ab156 AD |
6677 | ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, |
6678 | type_tucmd, mss_l4len_idx); | |
9a799d71 | 6679 | |
897ab156 | 6680 | return (skb->ip_summed == CHECKSUM_PARTIAL); |
9a799d71 AK |
6681 | } |
6682 | ||
d3d00239 | 6683 | static __le32 ixgbe_tx_cmd_type(u32 tx_flags) |
9a799d71 | 6684 | { |
d3d00239 AD |
6685 | /* set type for advanced descriptor with frame checksum insertion */ |
6686 | __le32 cmd_type = cpu_to_le32(IXGBE_ADVTXD_DTYP_DATA | | |
6687 | IXGBE_ADVTXD_DCMD_IFCS | | |
6688 | IXGBE_ADVTXD_DCMD_DEXT); | |
9a799d71 | 6689 | |
d3d00239 | 6690 | /* set HW vlan bit if vlan is present */ |
66f32a8b | 6691 | if (tx_flags & IXGBE_TX_FLAGS_HW_VLAN) |
d3d00239 | 6692 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_VLE); |
9a799d71 | 6693 | |
d3d00239 AD |
6694 | /* set segmentation enable bits for TSO/FSO */ |
6695 | #ifdef IXGBE_FCOE | |
93f5b3c1 | 6696 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FSO)) |
d3d00239 AD |
6697 | #else |
6698 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
6699 | #endif | |
6700 | cmd_type |= cpu_to_le32(IXGBE_ADVTXD_DCMD_TSE); | |
eacd73f7 | 6701 | |
d3d00239 AD |
6702 | return cmd_type; |
6703 | } | |
9a799d71 | 6704 | |
d3d00239 AD |
6705 | static __le32 ixgbe_tx_olinfo_status(u32 tx_flags, unsigned int paylen) |
6706 | { | |
93f5b3c1 | 6707 | __le32 olinfo_status = cpu_to_le32(paylen << IXGBE_ADVTXD_PAYLEN_SHIFT); |
9a799d71 | 6708 | |
d3d00239 AD |
6709 | /* enable L4 checksum for TSO and TX checksum offload */ |
6710 | if (tx_flags & IXGBE_TX_FLAGS_CSUM) | |
6711 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_TXSM); | |
9a799d71 | 6712 | |
93f5b3c1 AD |
6713 | /* enble IPv4 checksum for TSO */ |
6714 | if (tx_flags & IXGBE_TX_FLAGS_IPV4) | |
6715 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_POPTS_IXSM); | |
9a799d71 | 6716 | |
93f5b3c1 AD |
6717 | /* use index 1 context for TSO/FSO/FCOE */ |
6718 | #ifdef IXGBE_FCOE | |
6719 | if (tx_flags & (IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_FCOE)) | |
6720 | #else | |
6721 | if (tx_flags & IXGBE_TX_FLAGS_TSO) | |
d3d00239 | 6722 | #endif |
93f5b3c1 AD |
6723 | olinfo_status |= cpu_to_le32(1 << IXGBE_ADVTXD_IDX_SHIFT); |
6724 | ||
7f9643fd AD |
6725 | /* |
6726 | * Check Context must be set if Tx switch is enabled, which it | |
6727 | * always is for case where virtual functions are running | |
6728 | */ | |
93f5b3c1 AD |
6729 | #ifdef IXGBE_FCOE |
6730 | if (tx_flags & (IXGBE_TX_FLAGS_TXSW | IXGBE_TX_FLAGS_FCOE)) | |
6731 | #else | |
7f9643fd | 6732 | if (tx_flags & IXGBE_TX_FLAGS_TXSW) |
93f5b3c1 | 6733 | #endif |
7f9643fd AD |
6734 | olinfo_status |= cpu_to_le32(IXGBE_ADVTXD_CC); |
6735 | ||
d3d00239 AD |
6736 | return olinfo_status; |
6737 | } | |
44df32c5 | 6738 | |
d3d00239 AD |
6739 | #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \ |
6740 | IXGBE_TXD_CMD_RS) | |
6741 | ||
6742 | static void ixgbe_tx_map(struct ixgbe_ring *tx_ring, | |
d3d00239 AD |
6743 | struct ixgbe_tx_buffer *first, |
6744 | u32 tx_flags, | |
6745 | const u8 hdr_len) | |
6746 | { | |
fd0db0ed | 6747 | struct sk_buff *skb = first->skb; |
d3d00239 AD |
6748 | struct device *dev = tx_ring->dev; |
6749 | struct ixgbe_tx_buffer *tx_buffer_info; | |
6750 | union ixgbe_adv_tx_desc *tx_desc; | |
6751 | dma_addr_t dma; | |
6752 | __le32 cmd_type, olinfo_status; | |
6753 | struct skb_frag_struct *frag; | |
6754 | unsigned int f = 0; | |
6755 | unsigned int data_len = skb->data_len; | |
6756 | unsigned int size = skb_headlen(skb); | |
6757 | u32 offset = 0; | |
6758 | u32 paylen = skb->len - hdr_len; | |
6759 | u16 i = tx_ring->next_to_use; | |
6760 | u16 gso_segs; | |
6761 | ||
6762 | #ifdef IXGBE_FCOE | |
6763 | if (tx_flags & IXGBE_TX_FLAGS_FCOE) { | |
6764 | if (data_len >= sizeof(struct fcoe_crc_eof)) { | |
6765 | data_len -= sizeof(struct fcoe_crc_eof); | |
6766 | } else { | |
6767 | size -= sizeof(struct fcoe_crc_eof) - data_len; | |
6768 | data_len = 0; | |
9a799d71 AK |
6769 | } |
6770 | } | |
44df32c5 | 6771 | |
d3d00239 AD |
6772 | #endif |
6773 | dma = dma_map_single(dev, skb->data, size, DMA_TO_DEVICE); | |
6774 | if (dma_mapping_error(dev, dma)) | |
6775 | goto dma_error; | |
8ad494b0 | 6776 | |
d3d00239 AD |
6777 | cmd_type = ixgbe_tx_cmd_type(tx_flags); |
6778 | olinfo_status = ixgbe_tx_olinfo_status(tx_flags, paylen); | |
9a799d71 | 6779 | |
e4f74028 | 6780 | tx_desc = IXGBE_TX_DESC(tx_ring, i); |
e5a43549 | 6781 | |
d3d00239 AD |
6782 | for (;;) { |
6783 | while (size > IXGBE_MAX_DATA_PER_TXD) { | |
6784 | tx_desc->read.buffer_addr = cpu_to_le64(dma + offset); | |
6785 | tx_desc->read.cmd_type_len = | |
6786 | cmd_type | cpu_to_le32(IXGBE_MAX_DATA_PER_TXD); | |
6787 | tx_desc->read.olinfo_status = olinfo_status; | |
e5a43549 | 6788 | |
d3d00239 AD |
6789 | offset += IXGBE_MAX_DATA_PER_TXD; |
6790 | size -= IXGBE_MAX_DATA_PER_TXD; | |
e5a43549 | 6791 | |
d3d00239 AD |
6792 | tx_desc++; |
6793 | i++; | |
6794 | if (i == tx_ring->count) { | |
e4f74028 | 6795 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6796 | i = 0; |
6797 | } | |
6798 | } | |
e5a43549 | 6799 | |
e5a43549 | 6800 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; |
d3d00239 AD |
6801 | tx_buffer_info->length = offset + size; |
6802 | tx_buffer_info->tx_flags = tx_flags; | |
6803 | tx_buffer_info->dma = dma; | |
9a799d71 | 6804 | |
d3d00239 | 6805 | tx_desc->read.buffer_addr = cpu_to_le64(dma + offset); |
f43f313e BG |
6806 | if (unlikely(skb->no_fcs)) |
6807 | cmd_type &= ~(cpu_to_le32(IXGBE_ADVTXD_DCMD_IFCS)); | |
d3d00239 AD |
6808 | tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); |
6809 | tx_desc->read.olinfo_status = olinfo_status; | |
9a799d71 | 6810 | |
d3d00239 AD |
6811 | if (!data_len) |
6812 | break; | |
9a799d71 | 6813 | |
d3d00239 AD |
6814 | frag = &skb_shinfo(skb)->frags[f]; |
6815 | #ifdef IXGBE_FCOE | |
9e903e08 | 6816 | size = min_t(unsigned int, data_len, skb_frag_size(frag)); |
d3d00239 | 6817 | #else |
9e903e08 | 6818 | size = skb_frag_size(frag); |
d3d00239 AD |
6819 | #endif |
6820 | data_len -= size; | |
6821 | f++; | |
9a799d71 | 6822 | |
d3d00239 AD |
6823 | offset = 0; |
6824 | tx_flags |= IXGBE_TX_FLAGS_MAPPED_AS_PAGE; | |
9a799d71 | 6825 | |
877749bf | 6826 | dma = skb_frag_dma_map(dev, frag, 0, size, DMA_TO_DEVICE); |
d3d00239 AD |
6827 | if (dma_mapping_error(dev, dma)) |
6828 | goto dma_error; | |
9a799d71 | 6829 | |
d3d00239 AD |
6830 | tx_desc++; |
6831 | i++; | |
6832 | if (i == tx_ring->count) { | |
e4f74028 | 6833 | tx_desc = IXGBE_TX_DESC(tx_ring, 0); |
d3d00239 AD |
6834 | i = 0; |
6835 | } | |
6836 | } | |
9a799d71 | 6837 | |
d3d00239 | 6838 | tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD); |
9a799d71 | 6839 | |
d3d00239 AD |
6840 | i++; |
6841 | if (i == tx_ring->count) | |
6842 | i = 0; | |
9a799d71 | 6843 | |
d3d00239 | 6844 | tx_ring->next_to_use = i; |
eacd73f7 | 6845 | |
d3d00239 AD |
6846 | if (tx_flags & IXGBE_TX_FLAGS_TSO) |
6847 | gso_segs = skb_shinfo(skb)->gso_segs; | |
6848 | #ifdef IXGBE_FCOE | |
6849 | /* adjust for FCoE Sequence Offload */ | |
6850 | else if (tx_flags & IXGBE_TX_FLAGS_FSO) | |
6851 | gso_segs = DIV_ROUND_UP(skb->len - hdr_len, | |
6852 | skb_shinfo(skb)->gso_size); | |
6853 | #endif /* IXGBE_FCOE */ | |
6854 | else | |
6855 | gso_segs = 1; | |
9a799d71 | 6856 | |
d3d00239 AD |
6857 | /* multiply data chunks by size of headers */ |
6858 | tx_buffer_info->bytecount = paylen + (gso_segs * hdr_len); | |
6859 | tx_buffer_info->gso_segs = gso_segs; | |
9a799d71 | 6860 | |
b2d96e0a AD |
6861 | netdev_tx_sent_queue(txring_txq(tx_ring), tx_buffer_info->bytecount); |
6862 | ||
d3d00239 AD |
6863 | /* set the timestamp */ |
6864 | first->time_stamp = jiffies; | |
9a799d71 AK |
6865 | |
6866 | /* | |
6867 | * Force memory writes to complete before letting h/w | |
6868 | * know there are new descriptors to fetch. (Only | |
6869 | * applicable for weak-ordered memory model archs, | |
6870 | * such as IA-64). | |
6871 | */ | |
6872 | wmb(); | |
6873 | ||
d3d00239 AD |
6874 | /* set next_to_watch value indicating a packet is present */ |
6875 | first->next_to_watch = tx_desc; | |
6876 | ||
6877 | /* notify HW of packet */ | |
84ea2591 | 6878 | writel(i, tx_ring->tail); |
d3d00239 AD |
6879 | |
6880 | return; | |
6881 | dma_error: | |
6882 | dev_err(dev, "TX DMA map failed\n"); | |
6883 | ||
6884 | /* clear dma mappings for failed tx_buffer_info map */ | |
6885 | for (;;) { | |
6886 | tx_buffer_info = &tx_ring->tx_buffer_info[i]; | |
fd0db0ed | 6887 | ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); |
d3d00239 AD |
6888 | if (tx_buffer_info == first) |
6889 | break; | |
6890 | if (i == 0) | |
6891 | i = tx_ring->count; | |
6892 | i--; | |
6893 | } | |
6894 | ||
d3d00239 | 6895 | tx_ring->next_to_use = i; |
9a799d71 AK |
6896 | } |
6897 | ||
fd0db0ed AD |
6898 | static void ixgbe_atr(struct ixgbe_ring *ring, |
6899 | struct ixgbe_tx_buffer *first, | |
69830529 AD |
6900 | u32 tx_flags, __be16 protocol) |
6901 | { | |
6902 | struct ixgbe_q_vector *q_vector = ring->q_vector; | |
6903 | union ixgbe_atr_hash_dword input = { .dword = 0 }; | |
6904 | union ixgbe_atr_hash_dword common = { .dword = 0 }; | |
6905 | union { | |
6906 | unsigned char *network; | |
6907 | struct iphdr *ipv4; | |
6908 | struct ipv6hdr *ipv6; | |
6909 | } hdr; | |
ee9e0f0b | 6910 | struct tcphdr *th; |
905e4a41 | 6911 | __be16 vlan_id; |
c4cf55e5 | 6912 | |
69830529 AD |
6913 | /* if ring doesn't have a interrupt vector, cannot perform ATR */ |
6914 | if (!q_vector) | |
6915 | return; | |
6916 | ||
6917 | /* do nothing if sampling is disabled */ | |
6918 | if (!ring->atr_sample_rate) | |
d3ead241 | 6919 | return; |
c4cf55e5 | 6920 | |
69830529 | 6921 | ring->atr_count++; |
c4cf55e5 | 6922 | |
69830529 | 6923 | /* snag network header to get L4 type and address */ |
fd0db0ed | 6924 | hdr.network = skb_network_header(first->skb); |
69830529 AD |
6925 | |
6926 | /* Currently only IPv4/IPv6 with TCP is supported */ | |
6927 | if ((protocol != __constant_htons(ETH_P_IPV6) || | |
6928 | hdr.ipv6->nexthdr != IPPROTO_TCP) && | |
6929 | (protocol != __constant_htons(ETH_P_IP) || | |
6930 | hdr.ipv4->protocol != IPPROTO_TCP)) | |
6931 | return; | |
ee9e0f0b | 6932 | |
fd0db0ed | 6933 | th = tcp_hdr(first->skb); |
c4cf55e5 | 6934 | |
66f32a8b AD |
6935 | /* skip this packet since it is invalid or the socket is closing */ |
6936 | if (!th || th->fin) | |
69830529 AD |
6937 | return; |
6938 | ||
6939 | /* sample on all syn packets or once every atr sample count */ | |
6940 | if (!th->syn && (ring->atr_count < ring->atr_sample_rate)) | |
6941 | return; | |
6942 | ||
6943 | /* reset sample count */ | |
6944 | ring->atr_count = 0; | |
6945 | ||
6946 | vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT); | |
6947 | ||
6948 | /* | |
6949 | * src and dst are inverted, think how the receiver sees them | |
6950 | * | |
6951 | * The input is broken into two sections, a non-compressed section | |
6952 | * containing vm_pool, vlan_id, and flow_type. The rest of the data | |
6953 | * is XORed together and stored in the compressed dword. | |
6954 | */ | |
6955 | input.formatted.vlan_id = vlan_id; | |
6956 | ||
6957 | /* | |
6958 | * since src port and flex bytes occupy the same word XOR them together | |
6959 | * and write the value to source port portion of compressed dword | |
6960 | */ | |
66f32a8b | 6961 | if (tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN)) |
69830529 AD |
6962 | common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q); |
6963 | else | |
6964 | common.port.src ^= th->dest ^ protocol; | |
6965 | common.port.dst ^= th->source; | |
6966 | ||
6967 | if (protocol == __constant_htons(ETH_P_IP)) { | |
6968 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4; | |
6969 | common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr; | |
6970 | } else { | |
6971 | input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6; | |
6972 | common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^ | |
6973 | hdr.ipv6->saddr.s6_addr32[1] ^ | |
6974 | hdr.ipv6->saddr.s6_addr32[2] ^ | |
6975 | hdr.ipv6->saddr.s6_addr32[3] ^ | |
6976 | hdr.ipv6->daddr.s6_addr32[0] ^ | |
6977 | hdr.ipv6->daddr.s6_addr32[1] ^ | |
6978 | hdr.ipv6->daddr.s6_addr32[2] ^ | |
6979 | hdr.ipv6->daddr.s6_addr32[3]; | |
6980 | } | |
c4cf55e5 PWJ |
6981 | |
6982 | /* This assumes the Rx queue and Tx queue are bound to the same CPU */ | |
69830529 AD |
6983 | ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw, |
6984 | input, common, ring->queue_index); | |
c4cf55e5 PWJ |
6985 | } |
6986 | ||
63544e9c | 6987 | static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 6988 | { |
fc77dc3c | 6989 | netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index); |
e092be60 AV |
6990 | /* Herbert's original patch had: |
6991 | * smp_mb__after_netif_stop_queue(); | |
6992 | * but since that doesn't exist yet, just open code it. */ | |
6993 | smp_mb(); | |
6994 | ||
6995 | /* We need to check again in a case another CPU has just | |
6996 | * made room available. */ | |
7d4987de | 6997 | if (likely(ixgbe_desc_unused(tx_ring) < size)) |
e092be60 AV |
6998 | return -EBUSY; |
6999 | ||
7000 | /* A reprieve! - use start_queue because it doesn't call schedule */ | |
fc77dc3c | 7001 | netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index); |
5b7da515 | 7002 | ++tx_ring->tx_stats.restart_queue; |
e092be60 AV |
7003 | return 0; |
7004 | } | |
7005 | ||
82d4e46e | 7006 | static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size) |
e092be60 | 7007 | { |
7d4987de | 7008 | if (likely(ixgbe_desc_unused(tx_ring) >= size)) |
e092be60 | 7009 | return 0; |
fc77dc3c | 7010 | return __ixgbe_maybe_stop_tx(tx_ring, size); |
e092be60 AV |
7011 | } |
7012 | ||
09a3b1f8 SH |
7013 | static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb) |
7014 | { | |
7015 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
6440752c AD |
7016 | int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) : |
7017 | smp_processor_id(); | |
56075a98 | 7018 | #ifdef IXGBE_FCOE |
6440752c | 7019 | __be16 protocol = vlan_get_protocol(skb); |
5e09a105 | 7020 | |
e5b64635 JF |
7021 | if (((protocol == htons(ETH_P_FCOE)) || |
7022 | (protocol == htons(ETH_P_FIP))) && | |
7023 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
7024 | txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1); | |
7025 | txq += adapter->ring_feature[RING_F_FCOE].mask; | |
7026 | return txq; | |
56075a98 JF |
7027 | } |
7028 | #endif | |
7029 | ||
fdd3d631 KK |
7030 | if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) { |
7031 | while (unlikely(txq >= dev->real_num_tx_queues)) | |
7032 | txq -= dev->real_num_tx_queues; | |
5f715823 | 7033 | return txq; |
fdd3d631 | 7034 | } |
c4cf55e5 | 7035 | |
09a3b1f8 SH |
7036 | return skb_tx_hash(dev, skb); |
7037 | } | |
7038 | ||
fc77dc3c | 7039 | netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, |
84418e3b AD |
7040 | struct ixgbe_adapter *adapter, |
7041 | struct ixgbe_ring *tx_ring) | |
9a799d71 | 7042 | { |
d3d00239 | 7043 | struct ixgbe_tx_buffer *first; |
5f715823 | 7044 | int tso; |
d3d00239 | 7045 | u32 tx_flags = 0; |
a535c30e AD |
7046 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD |
7047 | unsigned short f; | |
7048 | #endif | |
a535c30e | 7049 | u16 count = TXD_USE_COUNT(skb_headlen(skb)); |
66f32a8b | 7050 | __be16 protocol = skb->protocol; |
63544e9c | 7051 | u8 hdr_len = 0; |
5e09a105 | 7052 | |
a535c30e AD |
7053 | /* |
7054 | * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD, | |
24ddd967 | 7055 | * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD, |
a535c30e AD |
7056 | * + 2 desc gap to keep tail from touching head, |
7057 | * + 1 desc for context descriptor, | |
7058 | * otherwise try next time | |
7059 | */ | |
7060 | #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD | |
7061 | for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) | |
7062 | count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); | |
7063 | #else | |
7064 | count += skb_shinfo(skb)->nr_frags; | |
7065 | #endif | |
7066 | if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) { | |
7067 | tx_ring->tx_stats.tx_busy++; | |
7068 | return NETDEV_TX_BUSY; | |
7069 | } | |
7070 | ||
fd0db0ed AD |
7071 | /* record the location of the first descriptor for this packet */ |
7072 | first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; | |
7073 | first->skb = skb; | |
7074 | ||
66f32a8b | 7075 | /* if we have a HW VLAN tag being added default to the HW one */ |
eab6d18d | 7076 | if (vlan_tx_tag_present(skb)) { |
66f32a8b AD |
7077 | tx_flags |= vlan_tx_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT; |
7078 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
7079 | /* else if it is a SW VLAN check the next protocol and store the tag */ | |
7080 | } else if (protocol == __constant_htons(ETH_P_8021Q)) { | |
7081 | struct vlan_hdr *vhdr, _vhdr; | |
7082 | vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr); | |
7083 | if (!vhdr) | |
7084 | goto out_drop; | |
7085 | ||
7086 | protocol = vhdr->h_vlan_encapsulated_proto; | |
9e0c5648 AD |
7087 | tx_flags |= ntohs(vhdr->h_vlan_TCI) << |
7088 | IXGBE_TX_FLAGS_VLAN_SHIFT; | |
66f32a8b AD |
7089 | tx_flags |= IXGBE_TX_FLAGS_SW_VLAN; |
7090 | } | |
7091 | ||
9e0c5648 AD |
7092 | #ifdef CONFIG_PCI_IOV |
7093 | /* | |
7094 | * Use the l2switch_enable flag - would be false if the DMA | |
7095 | * Tx switch had been disabled. | |
7096 | */ | |
7097 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) | |
7098 | tx_flags |= IXGBE_TX_FLAGS_TXSW; | |
7099 | ||
7100 | #endif | |
32701dc2 | 7101 | /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */ |
66f32a8b | 7102 | if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && |
09dca476 AD |
7103 | ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) || |
7104 | (skb->priority != TC_PRIO_CONTROL))) { | |
66f32a8b | 7105 | tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK; |
32701dc2 JF |
7106 | tx_flags |= (skb->priority & 0x7) << |
7107 | IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT; | |
66f32a8b AD |
7108 | if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) { |
7109 | struct vlan_ethhdr *vhdr; | |
7110 | if (skb_header_cloned(skb) && | |
7111 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) | |
7112 | goto out_drop; | |
7113 | vhdr = (struct vlan_ethhdr *)skb->data; | |
7114 | vhdr->h_vlan_TCI = htons(tx_flags >> | |
7115 | IXGBE_TX_FLAGS_VLAN_SHIFT); | |
7116 | } else { | |
7117 | tx_flags |= IXGBE_TX_FLAGS_HW_VLAN; | |
2f90b865 | 7118 | } |
9a799d71 | 7119 | } |
eacd73f7 | 7120 | |
eacd73f7 | 7121 | #ifdef IXGBE_FCOE |
66f32a8b AD |
7122 | /* setup tx offload for FCoE */ |
7123 | if ((protocol == __constant_htons(ETH_P_FCOE)) && | |
7124 | (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) { | |
fd0db0ed | 7125 | tso = ixgbe_fso(tx_ring, first, tx_flags, &hdr_len); |
897ab156 AD |
7126 | if (tso < 0) |
7127 | goto out_drop; | |
7128 | else if (tso) | |
66f32a8b AD |
7129 | tx_flags |= IXGBE_TX_FLAGS_FSO | |
7130 | IXGBE_TX_FLAGS_FCOE; | |
7131 | else | |
7132 | tx_flags |= IXGBE_TX_FLAGS_FCOE; | |
9a799d71 | 7133 | |
66f32a8b | 7134 | goto xmit_fcoe; |
eacd73f7 | 7135 | } |
9a799d71 | 7136 | |
66f32a8b AD |
7137 | #endif /* IXGBE_FCOE */ |
7138 | /* setup IPv4/IPv6 offloads */ | |
7139 | if (protocol == __constant_htons(ETH_P_IP)) | |
7140 | tx_flags |= IXGBE_TX_FLAGS_IPV4; | |
9a799d71 | 7141 | |
fd0db0ed | 7142 | tso = ixgbe_tso(tx_ring, first, tx_flags, protocol, &hdr_len); |
66f32a8b | 7143 | if (tso < 0) |
897ab156 | 7144 | goto out_drop; |
66f32a8b | 7145 | else if (tso) |
93f5b3c1 | 7146 | tx_flags |= IXGBE_TX_FLAGS_TSO | IXGBE_TX_FLAGS_CSUM; |
fd0db0ed | 7147 | else if (ixgbe_tx_csum(tx_ring, first, tx_flags, protocol)) |
66f32a8b AD |
7148 | tx_flags |= IXGBE_TX_FLAGS_CSUM; |
7149 | ||
7150 | /* add the ATR filter if ATR is on */ | |
7151 | if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state)) | |
fd0db0ed | 7152 | ixgbe_atr(tx_ring, first, tx_flags, protocol); |
66f32a8b AD |
7153 | |
7154 | #ifdef IXGBE_FCOE | |
7155 | xmit_fcoe: | |
7156 | #endif /* IXGBE_FCOE */ | |
fd0db0ed | 7157 | ixgbe_tx_map(tx_ring, first, tx_flags, hdr_len); |
d3d00239 AD |
7158 | |
7159 | ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED); | |
9a799d71 AK |
7160 | |
7161 | return NETDEV_TX_OK; | |
897ab156 AD |
7162 | |
7163 | out_drop: | |
fd0db0ed AD |
7164 | dev_kfree_skb_any(first->skb); |
7165 | first->skb = NULL; | |
7166 | ||
897ab156 | 7167 | return NETDEV_TX_OK; |
9a799d71 AK |
7168 | } |
7169 | ||
a50c29dd AD |
7170 | static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, |
7171 | struct net_device *netdev) | |
84418e3b AD |
7172 | { |
7173 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7174 | struct ixgbe_ring *tx_ring; | |
7175 | ||
a50c29dd AD |
7176 | if (skb->len <= 0) { |
7177 | dev_kfree_skb_any(skb); | |
7178 | return NETDEV_TX_OK; | |
7179 | } | |
7180 | ||
7181 | /* | |
7182 | * The minimum packet size for olinfo paylen is 17 so pad the skb | |
7183 | * in order to meet this minimum size requirement. | |
7184 | */ | |
7185 | if (skb->len < 17) { | |
7186 | if (skb_padto(skb, 17)) | |
7187 | return NETDEV_TX_OK; | |
7188 | skb->len = 17; | |
7189 | } | |
7190 | ||
84418e3b | 7191 | tx_ring = adapter->tx_ring[skb->queue_mapping]; |
fc77dc3c | 7192 | return ixgbe_xmit_frame_ring(skb, adapter, tx_ring); |
84418e3b AD |
7193 | } |
7194 | ||
9a799d71 AK |
7195 | /** |
7196 | * ixgbe_set_mac - Change the Ethernet Address of the NIC | |
7197 | * @netdev: network interface device structure | |
7198 | * @p: pointer to an address structure | |
7199 | * | |
7200 | * Returns 0 on success, negative on failure | |
7201 | **/ | |
7202 | static int ixgbe_set_mac(struct net_device *netdev, void *p) | |
7203 | { | |
7204 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
b4617240 | 7205 | struct ixgbe_hw *hw = &adapter->hw; |
9a799d71 AK |
7206 | struct sockaddr *addr = p; |
7207 | ||
7208 | if (!is_valid_ether_addr(addr->sa_data)) | |
7209 | return -EADDRNOTAVAIL; | |
7210 | ||
7211 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
b4617240 | 7212 | memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); |
9a799d71 | 7213 | |
1cdd1ec8 GR |
7214 | hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs, |
7215 | IXGBE_RAH_AV); | |
9a799d71 AK |
7216 | |
7217 | return 0; | |
7218 | } | |
7219 | ||
6b73e10d BH |
7220 | static int |
7221 | ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr) | |
7222 | { | |
7223 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7224 | struct ixgbe_hw *hw = &adapter->hw; | |
7225 | u16 value; | |
7226 | int rc; | |
7227 | ||
7228 | if (prtad != hw->phy.mdio.prtad) | |
7229 | return -EINVAL; | |
7230 | rc = hw->phy.ops.read_reg(hw, addr, devad, &value); | |
7231 | if (!rc) | |
7232 | rc = value; | |
7233 | return rc; | |
7234 | } | |
7235 | ||
7236 | static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad, | |
7237 | u16 addr, u16 value) | |
7238 | { | |
7239 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7240 | struct ixgbe_hw *hw = &adapter->hw; | |
7241 | ||
7242 | if (prtad != hw->phy.mdio.prtad) | |
7243 | return -EINVAL; | |
7244 | return hw->phy.ops.write_reg(hw, addr, devad, value); | |
7245 | } | |
7246 | ||
7247 | static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd) | |
7248 | { | |
7249 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7250 | ||
7251 | return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd); | |
7252 | } | |
7253 | ||
0365e6e4 PW |
7254 | /** |
7255 | * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding | |
31278e71 | 7256 | * netdev->dev_addrs |
0365e6e4 PW |
7257 | * @netdev: network interface device structure |
7258 | * | |
7259 | * Returns non-zero on failure | |
7260 | **/ | |
7261 | static int ixgbe_add_sanmac_netdev(struct net_device *dev) | |
7262 | { | |
7263 | int err = 0; | |
7264 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7265 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7266 | ||
7267 | if (is_valid_ether_addr(mac->san_addr)) { | |
7268 | rtnl_lock(); | |
7269 | err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
7270 | rtnl_unlock(); | |
7271 | } | |
7272 | return err; | |
7273 | } | |
7274 | ||
7275 | /** | |
7276 | * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding | |
31278e71 | 7277 | * netdev->dev_addrs |
0365e6e4 PW |
7278 | * @netdev: network interface device structure |
7279 | * | |
7280 | * Returns non-zero on failure | |
7281 | **/ | |
7282 | static int ixgbe_del_sanmac_netdev(struct net_device *dev) | |
7283 | { | |
7284 | int err = 0; | |
7285 | struct ixgbe_adapter *adapter = netdev_priv(dev); | |
7286 | struct ixgbe_mac_info *mac = &adapter->hw.mac; | |
7287 | ||
7288 | if (is_valid_ether_addr(mac->san_addr)) { | |
7289 | rtnl_lock(); | |
7290 | err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN); | |
7291 | rtnl_unlock(); | |
7292 | } | |
7293 | return err; | |
7294 | } | |
7295 | ||
9a799d71 AK |
7296 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7297 | /* | |
7298 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
7299 | * without having to re-enable interrupts. It's not called while | |
7300 | * the interrupt routine is executing. | |
7301 | */ | |
7302 | static void ixgbe_netpoll(struct net_device *netdev) | |
7303 | { | |
7304 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
8f9a7167 | 7305 | int i; |
9a799d71 | 7306 | |
1a647bd2 AD |
7307 | /* if interface is down do nothing */ |
7308 | if (test_bit(__IXGBE_DOWN, &adapter->state)) | |
7309 | return; | |
7310 | ||
9a799d71 | 7311 | adapter->flags |= IXGBE_FLAG_IN_NETPOLL; |
8f9a7167 PWJ |
7312 | if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) { |
7313 | int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS; | |
7314 | for (i = 0; i < num_q_vectors; i++) { | |
7315 | struct ixgbe_q_vector *q_vector = adapter->q_vector[i]; | |
4ff7fb12 | 7316 | ixgbe_msix_clean_rings(0, q_vector); |
8f9a7167 PWJ |
7317 | } |
7318 | } else { | |
7319 | ixgbe_intr(adapter->pdev->irq, netdev); | |
7320 | } | |
9a799d71 | 7321 | adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL; |
9a799d71 AK |
7322 | } |
7323 | #endif | |
7324 | ||
de1036b1 ED |
7325 | static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev, |
7326 | struct rtnl_link_stats64 *stats) | |
7327 | { | |
7328 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7329 | int i; | |
7330 | ||
1a51502b | 7331 | rcu_read_lock(); |
de1036b1 | 7332 | for (i = 0; i < adapter->num_rx_queues; i++) { |
1a51502b | 7333 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]); |
de1036b1 ED |
7334 | u64 bytes, packets; |
7335 | unsigned int start; | |
7336 | ||
1a51502b ED |
7337 | if (ring) { |
7338 | do { | |
7339 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7340 | packets = ring->stats.packets; | |
7341 | bytes = ring->stats.bytes; | |
7342 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7343 | stats->rx_packets += packets; | |
7344 | stats->rx_bytes += bytes; | |
7345 | } | |
de1036b1 | 7346 | } |
1ac9ad13 ED |
7347 | |
7348 | for (i = 0; i < adapter->num_tx_queues; i++) { | |
7349 | struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]); | |
7350 | u64 bytes, packets; | |
7351 | unsigned int start; | |
7352 | ||
7353 | if (ring) { | |
7354 | do { | |
7355 | start = u64_stats_fetch_begin_bh(&ring->syncp); | |
7356 | packets = ring->stats.packets; | |
7357 | bytes = ring->stats.bytes; | |
7358 | } while (u64_stats_fetch_retry_bh(&ring->syncp, start)); | |
7359 | stats->tx_packets += packets; | |
7360 | stats->tx_bytes += bytes; | |
7361 | } | |
7362 | } | |
1a51502b | 7363 | rcu_read_unlock(); |
de1036b1 ED |
7364 | /* following stats updated by ixgbe_watchdog_task() */ |
7365 | stats->multicast = netdev->stats.multicast; | |
7366 | stats->rx_errors = netdev->stats.rx_errors; | |
7367 | stats->rx_length_errors = netdev->stats.rx_length_errors; | |
7368 | stats->rx_crc_errors = netdev->stats.rx_crc_errors; | |
7369 | stats->rx_missed_errors = netdev->stats.rx_missed_errors; | |
7370 | return stats; | |
7371 | } | |
7372 | ||
8b1c0b24 JF |
7373 | /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid. |
7374 | * #adapter: pointer to ixgbe_adapter | |
7375 | * @tc: number of traffic classes currently enabled | |
7376 | * | |
7377 | * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm | |
7378 | * 802.1Q priority maps to a packet buffer that exists. | |
7379 | */ | |
7380 | static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc) | |
7381 | { | |
7382 | struct ixgbe_hw *hw = &adapter->hw; | |
7383 | u32 reg, rsave; | |
7384 | int i; | |
7385 | ||
7386 | /* 82598 have a static priority to TC mapping that can not | |
7387 | * be changed so no validation is needed. | |
7388 | */ | |
7389 | if (hw->mac.type == ixgbe_mac_82598EB) | |
7390 | return; | |
7391 | ||
7392 | reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); | |
7393 | rsave = reg; | |
7394 | ||
7395 | for (i = 0; i < MAX_TRAFFIC_CLASS; i++) { | |
7396 | u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT); | |
7397 | ||
7398 | /* If up2tc is out of bounds default to zero */ | |
7399 | if (up2tc > tc) | |
7400 | reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT); | |
7401 | } | |
7402 | ||
7403 | if (reg != rsave) | |
7404 | IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); | |
7405 | ||
7406 | return; | |
7407 | } | |
7408 | ||
7409 | ||
7410 | /* ixgbe_setup_tc - routine to configure net_device for multiple traffic | |
7411 | * classes. | |
7412 | * | |
7413 | * @netdev: net device to configure | |
7414 | * @tc: number of traffic classes to enable | |
7415 | */ | |
7416 | int ixgbe_setup_tc(struct net_device *dev, u8 tc) | |
7417 | { | |
8b1c0b24 JF |
7418 | struct ixgbe_adapter *adapter = netdev_priv(dev); |
7419 | struct ixgbe_hw *hw = &adapter->hw; | |
8b1c0b24 | 7420 | |
e7589eab JF |
7421 | /* Multiple traffic classes requires multiple queues */ |
7422 | if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) { | |
7423 | e_err(drv, "Enable failed, needs MSI-X\n"); | |
7424 | return -EINVAL; | |
7425 | } | |
8b1c0b24 JF |
7426 | |
7427 | /* Hardware supports up to 8 traffic classes */ | |
4de2a022 | 7428 | if (tc > adapter->dcb_cfg.num_tcs.pg_tcs || |
8b1c0b24 JF |
7429 | (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS)) |
7430 | return -EINVAL; | |
7431 | ||
7432 | /* Hardware has to reinitialize queues and interrupts to | |
52f33af8 | 7433 | * match packet buffer alignment. Unfortunately, the |
8b1c0b24 JF |
7434 | * hardware is not flexible enough to do this dynamically. |
7435 | */ | |
7436 | if (netif_running(dev)) | |
7437 | ixgbe_close(dev); | |
7438 | ixgbe_clear_interrupt_scheme(adapter); | |
7439 | ||
e7589eab | 7440 | if (tc) { |
8b1c0b24 | 7441 | netdev_set_num_tc(dev, tc); |
e7589eab JF |
7442 | adapter->last_lfc_mode = adapter->hw.fc.current_mode; |
7443 | ||
7444 | adapter->flags |= IXGBE_FLAG_DCB_ENABLED; | |
7445 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7446 | ||
7447 | if (adapter->hw.mac.type == ixgbe_mac_82598EB) | |
7448 | adapter->hw.fc.requested_mode = ixgbe_fc_none; | |
7449 | } else { | |
8b1c0b24 JF |
7450 | netdev_reset_tc(dev); |
7451 | ||
e7589eab JF |
7452 | adapter->hw.fc.requested_mode = adapter->last_lfc_mode; |
7453 | ||
7454 | adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED; | |
7455 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7456 | ||
7457 | adapter->temp_dcb_cfg.pfc_mode_enable = false; | |
7458 | adapter->dcb_cfg.pfc_mode_enable = false; | |
7459 | } | |
7460 | ||
8b1c0b24 JF |
7461 | ixgbe_init_interrupt_scheme(adapter); |
7462 | ixgbe_validate_rtr(adapter, tc); | |
7463 | if (netif_running(dev)) | |
7464 | ixgbe_open(dev); | |
7465 | ||
7466 | return 0; | |
7467 | } | |
de1036b1 | 7468 | |
082757af DS |
7469 | void ixgbe_do_reset(struct net_device *netdev) |
7470 | { | |
7471 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7472 | ||
7473 | if (netif_running(netdev)) | |
7474 | ixgbe_reinit_locked(adapter); | |
7475 | else | |
7476 | ixgbe_reset(adapter); | |
7477 | } | |
7478 | ||
c8f44aff MM |
7479 | static netdev_features_t ixgbe_fix_features(struct net_device *netdev, |
7480 | netdev_features_t data) | |
082757af DS |
7481 | { |
7482 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
7483 | ||
7484 | #ifdef CONFIG_DCB | |
7485 | if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) | |
7486 | data &= ~NETIF_F_HW_VLAN_RX; | |
7487 | #endif | |
7488 | ||
7489 | /* return error if RXHASH is being enabled when RSS is not supported */ | |
7490 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) | |
7491 | data &= ~NETIF_F_RXHASH; | |
7492 | ||
7493 | /* If Rx checksum is disabled, then RSC/LRO should also be disabled */ | |
7494 | if (!(data & NETIF_F_RXCSUM)) | |
7495 | data &= ~NETIF_F_LRO; | |
7496 | ||
7497 | /* Turn off LRO if not RSC capable or invalid ITR settings */ | |
7498 | if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)) { | |
7499 | data &= ~NETIF_F_LRO; | |
7500 | } else if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) && | |
7501 | (adapter->rx_itr_setting != 1 && | |
7502 | adapter->rx_itr_setting > IXGBE_MAX_RSC_INT_RATE)) { | |
7503 | data &= ~NETIF_F_LRO; | |
7504 | e_info(probe, "rx-usecs set too low, not enabling RSC\n"); | |
7505 | } | |
7506 | ||
7507 | return data; | |
7508 | } | |
7509 | ||
c8f44aff MM |
7510 | static int ixgbe_set_features(struct net_device *netdev, |
7511 | netdev_features_t data) | |
082757af DS |
7512 | { |
7513 | struct ixgbe_adapter *adapter = netdev_priv(netdev); | |
3f2d1c0f | 7514 | netdev_features_t changed = netdev->features ^ data; |
082757af DS |
7515 | bool need_reset = false; |
7516 | ||
082757af DS |
7517 | /* Make sure RSC matches LRO, reset if change */ |
7518 | if (!!(data & NETIF_F_LRO) != | |
7519 | !!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) { | |
7520 | adapter->flags2 ^= IXGBE_FLAG2_RSC_ENABLED; | |
7521 | switch (adapter->hw.mac.type) { | |
7522 | case ixgbe_mac_X540: | |
7523 | case ixgbe_mac_82599EB: | |
7524 | need_reset = true; | |
7525 | break; | |
7526 | default: | |
7527 | break; | |
7528 | } | |
7529 | } | |
7530 | ||
7531 | /* | |
7532 | * Check if Flow Director n-tuple support was enabled or disabled. If | |
7533 | * the state changed, we need to reset. | |
7534 | */ | |
7535 | if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) { | |
7536 | /* turn off ATR, enable perfect filters and reset */ | |
7537 | if (data & NETIF_F_NTUPLE) { | |
7538 | adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7539 | adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
7540 | need_reset = true; | |
7541 | } | |
7542 | } else if (!(data & NETIF_F_NTUPLE)) { | |
7543 | /* turn off Flow Director, set ATR and reset */ | |
7544 | adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE; | |
7545 | if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) && | |
7546 | !(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) | |
7547 | adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE; | |
7548 | need_reset = true; | |
7549 | } | |
7550 | ||
3f2d1c0f BG |
7551 | if (changed & NETIF_F_RXALL) |
7552 | need_reset = true; | |
7553 | ||
7554 | netdev->features = data; | |
082757af DS |
7555 | if (need_reset) |
7556 | ixgbe_do_reset(netdev); | |
7557 | ||
7558 | return 0; | |
7559 | ||
7560 | } | |
7561 | ||
0edc3527 | 7562 | static const struct net_device_ops ixgbe_netdev_ops = { |
e8e9f696 | 7563 | .ndo_open = ixgbe_open, |
0edc3527 | 7564 | .ndo_stop = ixgbe_close, |
00829823 | 7565 | .ndo_start_xmit = ixgbe_xmit_frame, |
09a3b1f8 | 7566 | .ndo_select_queue = ixgbe_select_queue, |
e90d400c | 7567 | .ndo_set_rx_mode = ixgbe_set_rx_mode, |
0edc3527 SH |
7568 | .ndo_validate_addr = eth_validate_addr, |
7569 | .ndo_set_mac_address = ixgbe_set_mac, | |
7570 | .ndo_change_mtu = ixgbe_change_mtu, | |
7571 | .ndo_tx_timeout = ixgbe_tx_timeout, | |
0edc3527 SH |
7572 | .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid, |
7573 | .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid, | |
6b73e10d | 7574 | .ndo_do_ioctl = ixgbe_ioctl, |
7f01648a GR |
7575 | .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac, |
7576 | .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan, | |
7577 | .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw, | |
de4c7f65 | 7578 | .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk, |
7f01648a | 7579 | .ndo_get_vf_config = ixgbe_ndo_get_vf_config, |
de1036b1 | 7580 | .ndo_get_stats64 = ixgbe_get_stats64, |
24095aa3 | 7581 | .ndo_setup_tc = ixgbe_setup_tc, |
0edc3527 SH |
7582 | #ifdef CONFIG_NET_POLL_CONTROLLER |
7583 | .ndo_poll_controller = ixgbe_netpoll, | |
7584 | #endif | |
332d4a7d YZ |
7585 | #ifdef IXGBE_FCOE |
7586 | .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get, | |
68a683cf | 7587 | .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target, |
332d4a7d | 7588 | .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put, |
8450ff8c YZ |
7589 | .ndo_fcoe_enable = ixgbe_fcoe_enable, |
7590 | .ndo_fcoe_disable = ixgbe_fcoe_disable, | |
61a1fa10 | 7591 | .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn, |
ea81875a | 7592 | .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo, |
332d4a7d | 7593 | #endif /* IXGBE_FCOE */ |
082757af DS |
7594 | .ndo_set_features = ixgbe_set_features, |
7595 | .ndo_fix_features = ixgbe_fix_features, | |
0edc3527 SH |
7596 | }; |
7597 | ||
1cdd1ec8 GR |
7598 | static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter, |
7599 | const struct ixgbe_info *ii) | |
7600 | { | |
7601 | #ifdef CONFIG_PCI_IOV | |
7602 | struct ixgbe_hw *hw = &adapter->hw; | |
1cdd1ec8 | 7603 | |
c6bda30a | 7604 | if (hw->mac.type == ixgbe_mac_82598EB) |
1cdd1ec8 GR |
7605 | return; |
7606 | ||
7607 | /* The 82599 supports up to 64 VFs per physical function | |
7608 | * but this implementation limits allocation to 63 so that | |
7609 | * basic networking resources are still available to the | |
7610 | * physical function | |
7611 | */ | |
7612 | adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs; | |
c6bda30a | 7613 | ixgbe_enable_sriov(adapter, ii); |
1cdd1ec8 GR |
7614 | #endif /* CONFIG_PCI_IOV */ |
7615 | } | |
7616 | ||
9a799d71 AK |
7617 | /** |
7618 | * ixgbe_probe - Device Initialization Routine | |
7619 | * @pdev: PCI device information struct | |
7620 | * @ent: entry in ixgbe_pci_tbl | |
7621 | * | |
7622 | * Returns 0 on success, negative on failure | |
7623 | * | |
7624 | * ixgbe_probe initializes an adapter identified by a pci_dev structure. | |
7625 | * The OS initialization, configuring of the adapter private structure, | |
7626 | * and a hardware reset occur. | |
7627 | **/ | |
7628 | static int __devinit ixgbe_probe(struct pci_dev *pdev, | |
e8e9f696 | 7629 | const struct pci_device_id *ent) |
9a799d71 AK |
7630 | { |
7631 | struct net_device *netdev; | |
7632 | struct ixgbe_adapter *adapter = NULL; | |
7633 | struct ixgbe_hw *hw; | |
7634 | const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data]; | |
9a799d71 AK |
7635 | static int cards_found; |
7636 | int i, err, pci_using_dac; | |
289700db | 7637 | u8 part_str[IXGBE_PBANUM_LENGTH]; |
c85a2618 | 7638 | unsigned int indices = num_possible_cpus(); |
eacd73f7 YZ |
7639 | #ifdef IXGBE_FCOE |
7640 | u16 device_caps; | |
7641 | #endif | |
289700db | 7642 | u32 eec; |
c23f5b6b | 7643 | u16 wol_cap; |
9a799d71 | 7644 | |
bded64a7 AG |
7645 | /* Catch broken hardware that put the wrong VF device ID in |
7646 | * the PCIe SR-IOV capability. | |
7647 | */ | |
7648 | if (pdev->is_virtfn) { | |
7649 | WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", | |
7650 | pci_name(pdev), pdev->vendor, pdev->device); | |
7651 | return -EINVAL; | |
7652 | } | |
7653 | ||
9ce77666 | 7654 | err = pci_enable_device_mem(pdev); |
9a799d71 AK |
7655 | if (err) |
7656 | return err; | |
7657 | ||
1b507730 NN |
7658 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) && |
7659 | !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
9a799d71 AK |
7660 | pci_using_dac = 1; |
7661 | } else { | |
1b507730 | 7662 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
9a799d71 | 7663 | if (err) { |
1b507730 NN |
7664 | err = dma_set_coherent_mask(&pdev->dev, |
7665 | DMA_BIT_MASK(32)); | |
9a799d71 | 7666 | if (err) { |
b8bc0421 DC |
7667 | dev_err(&pdev->dev, |
7668 | "No usable DMA configuration, aborting\n"); | |
9a799d71 AK |
7669 | goto err_dma; |
7670 | } | |
7671 | } | |
7672 | pci_using_dac = 0; | |
7673 | } | |
7674 | ||
9ce77666 | 7675 | err = pci_request_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 7676 | IORESOURCE_MEM), ixgbe_driver_name); |
9a799d71 | 7677 | if (err) { |
b8bc0421 DC |
7678 | dev_err(&pdev->dev, |
7679 | "pci_request_selected_regions failed 0x%x\n", err); | |
9a799d71 AK |
7680 | goto err_pci_reg; |
7681 | } | |
7682 | ||
19d5afd4 | 7683 | pci_enable_pcie_error_reporting(pdev); |
6fabd715 | 7684 | |
9a799d71 | 7685 | pci_set_master(pdev); |
fb3b27bc | 7686 | pci_save_state(pdev); |
9a799d71 | 7687 | |
e901acd6 JF |
7688 | #ifdef CONFIG_IXGBE_DCB |
7689 | indices *= MAX_TRAFFIC_CLASS; | |
7690 | #endif | |
7691 | ||
c85a2618 JF |
7692 | if (ii->mac == ixgbe_mac_82598EB) |
7693 | indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES); | |
7694 | else | |
7695 | indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES); | |
7696 | ||
e901acd6 | 7697 | #ifdef IXGBE_FCOE |
c85a2618 JF |
7698 | indices += min_t(unsigned int, num_possible_cpus(), |
7699 | IXGBE_MAX_FCOE_INDICES); | |
7700 | #endif | |
c85a2618 | 7701 | netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices); |
9a799d71 AK |
7702 | if (!netdev) { |
7703 | err = -ENOMEM; | |
7704 | goto err_alloc_etherdev; | |
7705 | } | |
7706 | ||
9a799d71 AK |
7707 | SET_NETDEV_DEV(netdev, &pdev->dev); |
7708 | ||
9a799d71 | 7709 | adapter = netdev_priv(netdev); |
c60fbb00 | 7710 | pci_set_drvdata(pdev, adapter); |
9a799d71 AK |
7711 | |
7712 | adapter->netdev = netdev; | |
7713 | adapter->pdev = pdev; | |
7714 | hw = &adapter->hw; | |
7715 | hw->back = adapter; | |
7716 | adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1; | |
7717 | ||
05857980 | 7718 | hw->hw_addr = ioremap(pci_resource_start(pdev, 0), |
e8e9f696 | 7719 | pci_resource_len(pdev, 0)); |
9a799d71 AK |
7720 | if (!hw->hw_addr) { |
7721 | err = -EIO; | |
7722 | goto err_ioremap; | |
7723 | } | |
7724 | ||
7725 | for (i = 1; i <= 5; i++) { | |
7726 | if (pci_resource_len(pdev, i) == 0) | |
7727 | continue; | |
7728 | } | |
7729 | ||
0edc3527 | 7730 | netdev->netdev_ops = &ixgbe_netdev_ops; |
9a799d71 | 7731 | ixgbe_set_ethtool_ops(netdev); |
9a799d71 | 7732 | netdev->watchdog_timeo = 5 * HZ; |
9fe93afd | 7733 | strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); |
9a799d71 | 7734 | |
9a799d71 AK |
7735 | adapter->bd_number = cards_found; |
7736 | ||
9a799d71 AK |
7737 | /* Setup hw api */ |
7738 | memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops)); | |
021230d4 | 7739 | hw->mac.type = ii->mac; |
9a799d71 | 7740 | |
c44ade9e JB |
7741 | /* EEPROM */ |
7742 | memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops)); | |
7743 | eec = IXGBE_READ_REG(hw, IXGBE_EEC); | |
7744 | /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */ | |
7745 | if (!(eec & (1 << 8))) | |
7746 | hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic; | |
7747 | ||
7748 | /* PHY */ | |
7749 | memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops)); | |
c4900be0 | 7750 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
6b73e10d BH |
7751 | /* ixgbe_identify_phy_generic will set prtad and mmds properly */ |
7752 | hw->phy.mdio.prtad = MDIO_PRTAD_NONE; | |
7753 | hw->phy.mdio.mmds = 0; | |
7754 | hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
7755 | hw->phy.mdio.dev = netdev; | |
7756 | hw->phy.mdio.mdio_read = ixgbe_mdio_read; | |
7757 | hw->phy.mdio.mdio_write = ixgbe_mdio_write; | |
c4900be0 | 7758 | |
8ca783ab | 7759 | ii->get_invariants(hw); |
9a799d71 AK |
7760 | |
7761 | /* setup the private structure */ | |
7762 | err = ixgbe_sw_init(adapter); | |
7763 | if (err) | |
7764 | goto err_sw_init; | |
7765 | ||
e86bff0e | 7766 | /* Make it possible the adapter to be woken up via WOL */ |
b93a2226 DS |
7767 | switch (adapter->hw.mac.type) { |
7768 | case ixgbe_mac_82599EB: | |
7769 | case ixgbe_mac_X540: | |
e86bff0e | 7770 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
b93a2226 DS |
7771 | break; |
7772 | default: | |
7773 | break; | |
7774 | } | |
e86bff0e | 7775 | |
bf069c97 DS |
7776 | /* |
7777 | * If there is a fan on this device and it has failed log the | |
7778 | * failure. | |
7779 | */ | |
7780 | if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) { | |
7781 | u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); | |
7782 | if (esdp & IXGBE_ESDP_SDP1) | |
396e799c | 7783 | e_crit(probe, "Fan has stopped, replace the adapter\n"); |
bf069c97 DS |
7784 | } |
7785 | ||
8ef78adc PWJ |
7786 | if (allow_unsupported_sfp) |
7787 | hw->allow_unsupported_sfp = allow_unsupported_sfp; | |
7788 | ||
c44ade9e | 7789 | /* reset_hw fills in the perm_addr as well */ |
119fc60a | 7790 | hw->phy.reset_if_overtemp = true; |
c44ade9e | 7791 | err = hw->mac.ops.reset_hw(hw); |
119fc60a | 7792 | hw->phy.reset_if_overtemp = false; |
8ca783ab DS |
7793 | if (err == IXGBE_ERR_SFP_NOT_PRESENT && |
7794 | hw->mac.type == ixgbe_mac_82598EB) { | |
8ca783ab DS |
7795 | err = 0; |
7796 | } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) { | |
7086400d | 7797 | e_dev_err("failed to load because an unsupported SFP+ " |
849c4542 ET |
7798 | "module type was detected.\n"); |
7799 | e_dev_err("Reload the driver after installing a supported " | |
7800 | "module.\n"); | |
04f165ef PW |
7801 | goto err_sw_init; |
7802 | } else if (err) { | |
849c4542 | 7803 | e_dev_err("HW Init failed: %d\n", err); |
c44ade9e JB |
7804 | goto err_sw_init; |
7805 | } | |
7806 | ||
1cdd1ec8 GR |
7807 | ixgbe_probe_vf(adapter, ii); |
7808 | ||
396e799c | 7809 | netdev->features = NETIF_F_SG | |
e8e9f696 | 7810 | NETIF_F_IP_CSUM | |
082757af | 7811 | NETIF_F_IPV6_CSUM | |
e8e9f696 JP |
7812 | NETIF_F_HW_VLAN_TX | |
7813 | NETIF_F_HW_VLAN_RX | | |
082757af DS |
7814 | NETIF_F_HW_VLAN_FILTER | |
7815 | NETIF_F_TSO | | |
7816 | NETIF_F_TSO6 | | |
082757af DS |
7817 | NETIF_F_RXHASH | |
7818 | NETIF_F_RXCSUM; | |
9a799d71 | 7819 | |
082757af | 7820 | netdev->hw_features = netdev->features; |
ad31c402 | 7821 | |
58be7666 DS |
7822 | switch (adapter->hw.mac.type) { |
7823 | case ixgbe_mac_82599EB: | |
7824 | case ixgbe_mac_X540: | |
45a5ead0 | 7825 | netdev->features |= NETIF_F_SCTP_CSUM; |
082757af DS |
7826 | netdev->hw_features |= NETIF_F_SCTP_CSUM | |
7827 | NETIF_F_NTUPLE; | |
58be7666 DS |
7828 | break; |
7829 | default: | |
7830 | break; | |
7831 | } | |
45a5ead0 | 7832 | |
3f2d1c0f BG |
7833 | netdev->hw_features |= NETIF_F_RXALL; |
7834 | ||
ad31c402 JK |
7835 | netdev->vlan_features |= NETIF_F_TSO; |
7836 | netdev->vlan_features |= NETIF_F_TSO6; | |
22f32b7a | 7837 | netdev->vlan_features |= NETIF_F_IP_CSUM; |
cd1da503 | 7838 | netdev->vlan_features |= NETIF_F_IPV6_CSUM; |
ad31c402 JK |
7839 | netdev->vlan_features |= NETIF_F_SG; |
7840 | ||
01789349 | 7841 | netdev->priv_flags |= IFF_UNICAST_FLT; |
f43f313e | 7842 | netdev->priv_flags |= IFF_SUPP_NOFCS; |
01789349 | 7843 | |
1cdd1ec8 GR |
7844 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
7845 | adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED | | |
7846 | IXGBE_FLAG_DCB_ENABLED); | |
2f90b865 | 7847 | |
7a6b6f51 | 7848 | #ifdef CONFIG_IXGBE_DCB |
2f90b865 AD |
7849 | netdev->dcbnl_ops = &dcbnl_ops; |
7850 | #endif | |
7851 | ||
eacd73f7 | 7852 | #ifdef IXGBE_FCOE |
0d551589 | 7853 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
eacd73f7 YZ |
7854 | if (hw->mac.ops.get_device_caps) { |
7855 | hw->mac.ops.get_device_caps(hw, &device_caps); | |
0d551589 YZ |
7856 | if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS) |
7857 | adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE; | |
eacd73f7 YZ |
7858 | } |
7859 | } | |
5e09d7f6 YZ |
7860 | if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) { |
7861 | netdev->vlan_features |= NETIF_F_FCOE_CRC; | |
7862 | netdev->vlan_features |= NETIF_F_FSO; | |
7863 | netdev->vlan_features |= NETIF_F_FCOE_MTU; | |
7864 | } | |
eacd73f7 | 7865 | #endif /* IXGBE_FCOE */ |
7b872a55 | 7866 | if (pci_using_dac) { |
9a799d71 | 7867 | netdev->features |= NETIF_F_HIGHDMA; |
7b872a55 YZ |
7868 | netdev->vlan_features |= NETIF_F_HIGHDMA; |
7869 | } | |
9a799d71 | 7870 | |
082757af DS |
7871 | if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) |
7872 | netdev->hw_features |= NETIF_F_LRO; | |
0c19d6af | 7873 | if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) |
f8212f97 AD |
7874 | netdev->features |= NETIF_F_LRO; |
7875 | ||
9a799d71 | 7876 | /* make sure the EEPROM is good */ |
c44ade9e | 7877 | if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) { |
849c4542 | 7878 | e_dev_err("The EEPROM Checksum Is Not Valid\n"); |
9a799d71 AK |
7879 | err = -EIO; |
7880 | goto err_eeprom; | |
7881 | } | |
7882 | ||
7883 | memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len); | |
7884 | memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len); | |
7885 | ||
c44ade9e | 7886 | if (ixgbe_validate_mac_addr(netdev->perm_addr)) { |
849c4542 | 7887 | e_dev_err("invalid MAC address\n"); |
9a799d71 AK |
7888 | err = -EIO; |
7889 | goto err_eeprom; | |
7890 | } | |
7891 | ||
7086400d AD |
7892 | setup_timer(&adapter->service_timer, &ixgbe_service_timer, |
7893 | (unsigned long) adapter); | |
9a799d71 | 7894 | |
7086400d AD |
7895 | INIT_WORK(&adapter->service_task, ixgbe_service_task); |
7896 | clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state); | |
9a799d71 | 7897 | |
021230d4 AV |
7898 | err = ixgbe_init_interrupt_scheme(adapter); |
7899 | if (err) | |
7900 | goto err_sw_init; | |
9a799d71 | 7901 | |
082757af DS |
7902 | if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED)) { |
7903 | netdev->hw_features &= ~NETIF_F_RXHASH; | |
67a74ee2 | 7904 | netdev->features &= ~NETIF_F_RXHASH; |
082757af | 7905 | } |
67a74ee2 | 7906 | |
c23f5b6b ET |
7907 | /* WOL not supported for all but the following */ |
7908 | adapter->wol = 0; | |
e8e26350 | 7909 | switch (pdev->device) { |
0b077fea | 7910 | case IXGBE_DEV_ID_82599_SFP: |
0e22d043 DS |
7911 | /* Only these subdevice supports WOL */ |
7912 | switch (pdev->subsystem_device) { | |
7913 | case IXGBE_SUBDEV_ID_82599_560FLR: | |
7914 | /* only support first port */ | |
7915 | if (hw->bus.func != 0) | |
7916 | break; | |
7917 | case IXGBE_SUBDEV_ID_82599_SFP: | |
9417c464 | 7918 | adapter->wol = IXGBE_WUFC_MAG; |
0e22d043 DS |
7919 | break; |
7920 | } | |
0b077fea | 7921 | break; |
50d6c681 AD |
7922 | case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: |
7923 | /* All except this subdevice support WOL */ | |
0b077fea | 7924 | if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ) |
9417c464 | 7925 | adapter->wol = IXGBE_WUFC_MAG; |
0b077fea | 7926 | break; |
e8e26350 | 7927 | case IXGBE_DEV_ID_82599_KX4: |
9417c464 | 7928 | adapter->wol = IXGBE_WUFC_MAG; |
e8e26350 | 7929 | break; |
c23f5b6b ET |
7930 | case IXGBE_DEV_ID_X540T: |
7931 | /* Check eeprom to see if it is enabled */ | |
7932 | hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap); | |
7933 | wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK; | |
7934 | ||
7935 | if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) || | |
7936 | ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) && | |
7937 | (hw->bus.func == 0))) | |
7938 | adapter->wol = IXGBE_WUFC_MAG; | |
e8e26350 PW |
7939 | break; |
7940 | } | |
e8e26350 PW |
7941 | device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); |
7942 | ||
15e5209f ET |
7943 | /* save off EEPROM version number */ |
7944 | hw->eeprom.ops.read(hw, 0x2e, &adapter->eeprom_verh); | |
7945 | hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl); | |
7946 | ||
04f165ef PW |
7947 | /* pick up the PCI bus settings for reporting later */ |
7948 | hw->mac.ops.get_bus_info(hw); | |
7949 | ||
9a799d71 | 7950 | /* print bus type/speed/width info */ |
849c4542 | 7951 | e_dev_info("(PCI Express:%s:%s) %pM\n", |
6716344c DS |
7952 | (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" : |
7953 | hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" : | |
e8e9f696 JP |
7954 | "Unknown"), |
7955 | (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" : | |
7956 | hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" : | |
7957 | hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" : | |
7958 | "Unknown"), | |
7959 | netdev->dev_addr); | |
289700db DS |
7960 | |
7961 | err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH); | |
7962 | if (err) | |
9fe93afd | 7963 | strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH); |
e8e26350 | 7964 | if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present) |
289700db | 7965 | e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n", |
849c4542 | 7966 | hw->mac.type, hw->phy.type, hw->phy.sfp_type, |
289700db | 7967 | part_str); |
e8e26350 | 7968 | else |
289700db DS |
7969 | e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n", |
7970 | hw->mac.type, hw->phy.type, part_str); | |
9a799d71 | 7971 | |
e8e26350 | 7972 | if (hw->bus.width <= ixgbe_bus_width_pcie_x4) { |
849c4542 ET |
7973 | e_dev_warn("PCI-Express bandwidth available for this card is " |
7974 | "not sufficient for optimal performance.\n"); | |
7975 | e_dev_warn("For optimal performance a x8 PCI-Express slot " | |
7976 | "is required.\n"); | |
0c254d86 AK |
7977 | } |
7978 | ||
9a799d71 | 7979 | /* reset the hardware with the new settings */ |
794caeb2 | 7980 | err = hw->mac.ops.start_hw(hw); |
c44ade9e | 7981 | |
794caeb2 PWJ |
7982 | if (err == IXGBE_ERR_EEPROM_VERSION) { |
7983 | /* We are running on a pre-production device, log a warning */ | |
849c4542 ET |
7984 | e_dev_warn("This device is a pre-production adapter/LOM. " |
7985 | "Please be aware there may be issues associated " | |
7986 | "with your hardware. If you are experiencing " | |
7987 | "problems please contact your Intel or hardware " | |
7988 | "representative who provided you with this " | |
7989 | "hardware.\n"); | |
794caeb2 | 7990 | } |
9a799d71 AK |
7991 | strcpy(netdev->name, "eth%d"); |
7992 | err = register_netdev(netdev); | |
7993 | if (err) | |
7994 | goto err_register; | |
7995 | ||
93d3ce8f ET |
7996 | /* power down the optics for multispeed fiber and 82599 SFP+ fiber */ |
7997 | if (hw->mac.ops.disable_tx_laser && | |
7998 | ((hw->phy.multispeed_fiber) || | |
7999 | ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) && | |
8000 | (hw->mac.type == ixgbe_mac_82599EB)))) | |
8001 | hw->mac.ops.disable_tx_laser(hw); | |
8002 | ||
54386467 JB |
8003 | /* carrier off reporting is important to ethtool even BEFORE open */ |
8004 | netif_carrier_off(netdev); | |
8005 | ||
5dd2d332 | 8006 | #ifdef CONFIG_IXGBE_DCA |
652f093f | 8007 | if (dca_add_requester(&pdev->dev) == 0) { |
bd0362dd | 8008 | adapter->flags |= IXGBE_FLAG_DCA_ENABLED; |
bd0362dd JC |
8009 | ixgbe_setup_dca(adapter); |
8010 | } | |
8011 | #endif | |
1cdd1ec8 | 8012 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
396e799c | 8013 | e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs); |
1cdd1ec8 GR |
8014 | for (i = 0; i < adapter->num_vfs; i++) |
8015 | ixgbe_vf_configuration(pdev, (i | 0x10000000)); | |
8016 | } | |
8017 | ||
2466dd9c JK |
8018 | /* firmware requires driver version to be 0xFFFFFFFF |
8019 | * since os does not support feature | |
8020 | */ | |
9612de92 | 8021 | if (hw->mac.ops.set_fw_drv_ver) |
2466dd9c JK |
8022 | hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, |
8023 | 0xFF); | |
9612de92 | 8024 | |
0365e6e4 PW |
8025 | /* add san mac addr to netdev */ |
8026 | ixgbe_add_sanmac_netdev(netdev); | |
9a799d71 | 8027 | |
ea81875a | 8028 | e_dev_info("%s\n", ixgbe_default_device_descr); |
9a799d71 AK |
8029 | cards_found++; |
8030 | return 0; | |
8031 | ||
8032 | err_register: | |
5eba3699 | 8033 | ixgbe_release_hw_control(adapter); |
7a921c93 | 8034 | ixgbe_clear_interrupt_scheme(adapter); |
9a799d71 AK |
8035 | err_sw_init: |
8036 | err_eeprom: | |
1cdd1ec8 GR |
8037 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) |
8038 | ixgbe_disable_sriov(adapter); | |
7086400d | 8039 | adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP; |
9a799d71 AK |
8040 | iounmap(hw->hw_addr); |
8041 | err_ioremap: | |
8042 | free_netdev(netdev); | |
8043 | err_alloc_etherdev: | |
e8e9f696 JP |
8044 | pci_release_selected_regions(pdev, |
8045 | pci_select_bars(pdev, IORESOURCE_MEM)); | |
9a799d71 AK |
8046 | err_pci_reg: |
8047 | err_dma: | |
8048 | pci_disable_device(pdev); | |
8049 | return err; | |
8050 | } | |
8051 | ||
8052 | /** | |
8053 | * ixgbe_remove - Device Removal Routine | |
8054 | * @pdev: PCI device information struct | |
8055 | * | |
8056 | * ixgbe_remove is called by the PCI subsystem to alert the driver | |
8057 | * that it should release a PCI device. The could be caused by a | |
8058 | * Hot-Plug event, or because the driver is going to be removed from | |
8059 | * memory. | |
8060 | **/ | |
8061 | static void __devexit ixgbe_remove(struct pci_dev *pdev) | |
8062 | { | |
c60fbb00 AD |
8063 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
8064 | struct net_device *netdev = adapter->netdev; | |
9a799d71 AK |
8065 | |
8066 | set_bit(__IXGBE_DOWN, &adapter->state); | |
7086400d | 8067 | cancel_work_sync(&adapter->service_task); |
9a799d71 | 8068 | |
5dd2d332 | 8069 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
8070 | if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) { |
8071 | adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED; | |
8072 | dca_remove_requester(&pdev->dev); | |
8073 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1); | |
8074 | } | |
8075 | ||
8076 | #endif | |
332d4a7d YZ |
8077 | #ifdef IXGBE_FCOE |
8078 | if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) | |
8079 | ixgbe_cleanup_fcoe(adapter); | |
8080 | ||
8081 | #endif /* IXGBE_FCOE */ | |
0365e6e4 PW |
8082 | |
8083 | /* remove the added san mac */ | |
8084 | ixgbe_del_sanmac_netdev(netdev); | |
8085 | ||
c4900be0 DS |
8086 | if (netdev->reg_state == NETREG_REGISTERED) |
8087 | unregister_netdev(netdev); | |
9a799d71 | 8088 | |
c6bda30a GR |
8089 | if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) { |
8090 | if (!(ixgbe_check_vf_assignment(adapter))) | |
8091 | ixgbe_disable_sriov(adapter); | |
8092 | else | |
8093 | e_dev_warn("Unloading driver while VFs are assigned " | |
8094 | "- VFs will not be deallocated\n"); | |
8095 | } | |
1cdd1ec8 | 8096 | |
7a921c93 | 8097 | ixgbe_clear_interrupt_scheme(adapter); |
5eba3699 | 8098 | |
021230d4 | 8099 | ixgbe_release_hw_control(adapter); |
9a799d71 AK |
8100 | |
8101 | iounmap(adapter->hw.hw_addr); | |
9ce77666 | 8102 | pci_release_selected_regions(pdev, pci_select_bars(pdev, |
e8e9f696 | 8103 | IORESOURCE_MEM)); |
9a799d71 | 8104 | |
849c4542 | 8105 | e_dev_info("complete\n"); |
021230d4 | 8106 | |
9a799d71 AK |
8107 | free_netdev(netdev); |
8108 | ||
19d5afd4 | 8109 | pci_disable_pcie_error_reporting(pdev); |
6fabd715 | 8110 | |
9a799d71 AK |
8111 | pci_disable_device(pdev); |
8112 | } | |
8113 | ||
8114 | /** | |
8115 | * ixgbe_io_error_detected - called when PCI error is detected | |
8116 | * @pdev: Pointer to PCI device | |
8117 | * @state: The current pci connection state | |
8118 | * | |
8119 | * This function is called after a PCI bus error affecting | |
8120 | * this device has been detected. | |
8121 | */ | |
8122 | static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev, | |
e8e9f696 | 8123 | pci_channel_state_t state) |
9a799d71 | 8124 | { |
c60fbb00 AD |
8125 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
8126 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 8127 | |
83c61fa9 GR |
8128 | #ifdef CONFIG_PCI_IOV |
8129 | struct pci_dev *bdev, *vfdev; | |
8130 | u32 dw0, dw1, dw2, dw3; | |
8131 | int vf, pos; | |
8132 | u16 req_id, pf_func; | |
8133 | ||
8134 | if (adapter->hw.mac.type == ixgbe_mac_82598EB || | |
8135 | adapter->num_vfs == 0) | |
8136 | goto skip_bad_vf_detection; | |
8137 | ||
8138 | bdev = pdev->bus->self; | |
8139 | while (bdev && (bdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT)) | |
8140 | bdev = bdev->bus->self; | |
8141 | ||
8142 | if (!bdev) | |
8143 | goto skip_bad_vf_detection; | |
8144 | ||
8145 | pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR); | |
8146 | if (!pos) | |
8147 | goto skip_bad_vf_detection; | |
8148 | ||
8149 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG, &dw0); | |
8150 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 4, &dw1); | |
8151 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 8, &dw2); | |
8152 | pci_read_config_dword(bdev, pos + PCI_ERR_HEADER_LOG + 12, &dw3); | |
8153 | ||
8154 | req_id = dw1 >> 16; | |
8155 | /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */ | |
8156 | if (!(req_id & 0x0080)) | |
8157 | goto skip_bad_vf_detection; | |
8158 | ||
8159 | pf_func = req_id & 0x01; | |
8160 | if ((pf_func & 1) == (pdev->devfn & 1)) { | |
8161 | unsigned int device_id; | |
8162 | ||
8163 | vf = (req_id & 0x7F) >> 1; | |
8164 | e_dev_err("VF %d has caused a PCIe error\n", vf); | |
8165 | e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: " | |
8166 | "%8.8x\tdw3: %8.8x\n", | |
8167 | dw0, dw1, dw2, dw3); | |
8168 | switch (adapter->hw.mac.type) { | |
8169 | case ixgbe_mac_82599EB: | |
8170 | device_id = IXGBE_82599_VF_DEVICE_ID; | |
8171 | break; | |
8172 | case ixgbe_mac_X540: | |
8173 | device_id = IXGBE_X540_VF_DEVICE_ID; | |
8174 | break; | |
8175 | default: | |
8176 | device_id = 0; | |
8177 | break; | |
8178 | } | |
8179 | ||
8180 | /* Find the pci device of the offending VF */ | |
8181 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, device_id, NULL); | |
8182 | while (vfdev) { | |
8183 | if (vfdev->devfn == (req_id & 0xFF)) | |
8184 | break; | |
8185 | vfdev = pci_get_device(IXGBE_INTEL_VENDOR_ID, | |
8186 | device_id, vfdev); | |
8187 | } | |
8188 | /* | |
8189 | * There's a slim chance the VF could have been hot plugged, | |
8190 | * so if it is no longer present we don't need to issue the | |
8191 | * VFLR. Just clean up the AER in that case. | |
8192 | */ | |
8193 | if (vfdev) { | |
8194 | e_dev_err("Issuing VFLR to VF %d\n", vf); | |
8195 | pci_write_config_dword(vfdev, 0xA8, 0x00008000); | |
8196 | } | |
8197 | ||
8198 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
8199 | } | |
8200 | ||
8201 | /* | |
8202 | * Even though the error may have occurred on the other port | |
8203 | * we still need to increment the vf error reference count for | |
8204 | * both ports because the I/O resume function will be called | |
8205 | * for both of them. | |
8206 | */ | |
8207 | adapter->vferr_refcount++; | |
8208 | ||
8209 | return PCI_ERS_RESULT_RECOVERED; | |
8210 | ||
8211 | skip_bad_vf_detection: | |
8212 | #endif /* CONFIG_PCI_IOV */ | |
9a799d71 AK |
8213 | netif_device_detach(netdev); |
8214 | ||
3044b8d1 BL |
8215 | if (state == pci_channel_io_perm_failure) |
8216 | return PCI_ERS_RESULT_DISCONNECT; | |
8217 | ||
9a799d71 AK |
8218 | if (netif_running(netdev)) |
8219 | ixgbe_down(adapter); | |
8220 | pci_disable_device(pdev); | |
8221 | ||
b4617240 | 8222 | /* Request a slot reset. */ |
9a799d71 AK |
8223 | return PCI_ERS_RESULT_NEED_RESET; |
8224 | } | |
8225 | ||
8226 | /** | |
8227 | * ixgbe_io_slot_reset - called after the pci bus has been reset. | |
8228 | * @pdev: Pointer to PCI device | |
8229 | * | |
8230 | * Restart the card from scratch, as if from a cold-boot. | |
8231 | */ | |
8232 | static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev) | |
8233 | { | |
c60fbb00 | 8234 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
6fabd715 PWJ |
8235 | pci_ers_result_t result; |
8236 | int err; | |
9a799d71 | 8237 | |
9ce77666 | 8238 | if (pci_enable_device_mem(pdev)) { |
396e799c | 8239 | e_err(probe, "Cannot re-enable PCI device after reset.\n"); |
6fabd715 PWJ |
8240 | result = PCI_ERS_RESULT_DISCONNECT; |
8241 | } else { | |
8242 | pci_set_master(pdev); | |
8243 | pci_restore_state(pdev); | |
c0e1f68b | 8244 | pci_save_state(pdev); |
9a799d71 | 8245 | |
dd4d8ca6 | 8246 | pci_wake_from_d3(pdev, false); |
9a799d71 | 8247 | |
6fabd715 | 8248 | ixgbe_reset(adapter); |
88512539 | 8249 | IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0); |
6fabd715 PWJ |
8250 | result = PCI_ERS_RESULT_RECOVERED; |
8251 | } | |
8252 | ||
8253 | err = pci_cleanup_aer_uncorrect_error_status(pdev); | |
8254 | if (err) { | |
849c4542 ET |
8255 | e_dev_err("pci_cleanup_aer_uncorrect_error_status " |
8256 | "failed 0x%0x\n", err); | |
6fabd715 PWJ |
8257 | /* non-fatal, continue */ |
8258 | } | |
9a799d71 | 8259 | |
6fabd715 | 8260 | return result; |
9a799d71 AK |
8261 | } |
8262 | ||
8263 | /** | |
8264 | * ixgbe_io_resume - called when traffic can start flowing again. | |
8265 | * @pdev: Pointer to PCI device | |
8266 | * | |
8267 | * This callback is called when the error recovery driver tells us that | |
8268 | * its OK to resume normal operation. | |
8269 | */ | |
8270 | static void ixgbe_io_resume(struct pci_dev *pdev) | |
8271 | { | |
c60fbb00 AD |
8272 | struct ixgbe_adapter *adapter = pci_get_drvdata(pdev); |
8273 | struct net_device *netdev = adapter->netdev; | |
9a799d71 | 8274 | |
83c61fa9 GR |
8275 | #ifdef CONFIG_PCI_IOV |
8276 | if (adapter->vferr_refcount) { | |
8277 | e_info(drv, "Resuming after VF err\n"); | |
8278 | adapter->vferr_refcount--; | |
8279 | return; | |
8280 | } | |
8281 | ||
8282 | #endif | |
c7ccde0f AD |
8283 | if (netif_running(netdev)) |
8284 | ixgbe_up(adapter); | |
9a799d71 AK |
8285 | |
8286 | netif_device_attach(netdev); | |
9a799d71 AK |
8287 | } |
8288 | ||
8289 | static struct pci_error_handlers ixgbe_err_handler = { | |
8290 | .error_detected = ixgbe_io_error_detected, | |
8291 | .slot_reset = ixgbe_io_slot_reset, | |
8292 | .resume = ixgbe_io_resume, | |
8293 | }; | |
8294 | ||
8295 | static struct pci_driver ixgbe_driver = { | |
8296 | .name = ixgbe_driver_name, | |
8297 | .id_table = ixgbe_pci_tbl, | |
8298 | .probe = ixgbe_probe, | |
8299 | .remove = __devexit_p(ixgbe_remove), | |
8300 | #ifdef CONFIG_PM | |
8301 | .suspend = ixgbe_suspend, | |
8302 | .resume = ixgbe_resume, | |
8303 | #endif | |
8304 | .shutdown = ixgbe_shutdown, | |
8305 | .err_handler = &ixgbe_err_handler | |
8306 | }; | |
8307 | ||
8308 | /** | |
8309 | * ixgbe_init_module - Driver Registration Routine | |
8310 | * | |
8311 | * ixgbe_init_module is the first routine called when the driver is | |
8312 | * loaded. All it does is register with the PCI subsystem. | |
8313 | **/ | |
8314 | static int __init ixgbe_init_module(void) | |
8315 | { | |
8316 | int ret; | |
c7689578 | 8317 | pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version); |
849c4542 | 8318 | pr_info("%s\n", ixgbe_copyright); |
9a799d71 | 8319 | |
5dd2d332 | 8320 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 8321 | dca_register_notify(&dca_notifier); |
bd0362dd | 8322 | #endif |
5dd2d332 | 8323 | |
9a799d71 AK |
8324 | ret = pci_register_driver(&ixgbe_driver); |
8325 | return ret; | |
8326 | } | |
b4617240 | 8327 | |
9a799d71 AK |
8328 | module_init(ixgbe_init_module); |
8329 | ||
8330 | /** | |
8331 | * ixgbe_exit_module - Driver Exit Cleanup Routine | |
8332 | * | |
8333 | * ixgbe_exit_module is called just before the driver is removed | |
8334 | * from memory. | |
8335 | **/ | |
8336 | static void __exit ixgbe_exit_module(void) | |
8337 | { | |
5dd2d332 | 8338 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd JC |
8339 | dca_unregister_notify(&dca_notifier); |
8340 | #endif | |
9a799d71 | 8341 | pci_unregister_driver(&ixgbe_driver); |
1a51502b | 8342 | rcu_barrier(); /* Wait for completion of call_rcu()'s */ |
9a799d71 | 8343 | } |
bd0362dd | 8344 | |
5dd2d332 | 8345 | #ifdef CONFIG_IXGBE_DCA |
bd0362dd | 8346 | static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event, |
e8e9f696 | 8347 | void *p) |
bd0362dd JC |
8348 | { |
8349 | int ret_val; | |
8350 | ||
8351 | ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event, | |
e8e9f696 | 8352 | __ixgbe_notify_dca); |
bd0362dd JC |
8353 | |
8354 | return ret_val ? NOTIFY_BAD : NOTIFY_DONE; | |
8355 | } | |
b453368d | 8356 | |
5dd2d332 | 8357 | #endif /* CONFIG_IXGBE_DCA */ |
849c4542 | 8358 | |
9a799d71 AK |
8359 | module_exit(ixgbe_exit_module); |
8360 | ||
8361 | /* ixgbe_main.c */ |