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igb: Add device support for flashless SKU of i210 device
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
e1befd77 42static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
11afc1b1
PW		 43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
037c6d0a 60 u16 ext_ability = 0;
9a799d71 61
c44ade9e
JB		 62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 64 hw->phy.mdio.prtad = phy_addr;
6b73e10d 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 66 ixgbe_get_phy_id(hw);
67 hw->phy.type =
68 ixgbe_get_phy_type_from_id(hw->phy.id);
037c6d0a
ET		 69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
c44ade9e
JB		 85 status = 0;
86 break;
87 }
9a799d71 88 }
63d6e1d8 89 /* clear value if nothing found */
037c6d0a
ET		 90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 92 } else {
93 status = 0;
9a799d71 94 }
c44ade9e 95
9a799d71
AK		 96 return status;
97}
98
9a799d71
AK		 99/**
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
102 *
103 **/
104static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
105{
106 u32 status;
107 u16 phy_id_high = 0;
108 u16 phy_id_low = 0;
109
6b73e10d 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 111 &phy_id_high);
9a799d71
AK		 112
113 if (status == 0) {
114 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 116 &phy_id_low);
9a799d71
AK		 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
119 }
9a799d71
AK		 120 return status;
121}
122
123/**
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
126 *
127 **/
128static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
129{
130 enum ixgbe_phy_type phy_type;
131
132 switch (phy_id) {
0befdb3e
JB		 133 case TN1010_PHY_ID:
134 phy_type = ixgbe_phy_tn;
135 break;
2b264909 136 case X540_PHY_ID:
fe15e8e1
DS		 137 phy_type = ixgbe_phy_aq;
138 break;
9a799d71
AK		 139 case QT2022_PHY_ID:
140 phy_type = ixgbe_phy_qt;
141 break;
c4900be0
DS		 142 case ATH_PHY_ID:
143 phy_type = ixgbe_phy_nl;
144 break;
9a799d71
AK		 145 default:
146 phy_type = ixgbe_phy_unknown;
147 break;
148 }
149
150 return phy_type;
151}
152
153/**
c44ade9e 154 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 155 * @hw: pointer to hardware structure
156 **/
c44ade9e 157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 158{
1783575c
ET		 159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
119fc60a
MC		 169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
1783575c 172 goto out;
119fc60a 173
9a799d71
AK		 174 /*
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
177 */
1783575c
ET		 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
9a799d71
AK		 204}
205
3dcc2f41
ET		 206/**
207 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
208 * the SWFW lock
209 * @hw: pointer to hardware structure
210 * @reg_addr: 32 bit address of PHY register to read
211 * @phy_data: Pointer to read data from PHY register
212 **/
213s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
214 u16 *phy_data)
215{
216 u32 i, data, command;
217
218 /* Setup and write the address cycle command */
219 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
220 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
221 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
222 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
223
224 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
225
226 /* Check every 10 usec to see if the address cycle completed.
227 * The MDI Command bit will clear when the operation is
228 * complete
229 */
230 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
231 udelay(10);
232
233 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
234 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
235 break;
236 }
237
238
239 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
240 hw_dbg(hw, "PHY address command did not complete.\n");
241 return IXGBE_ERR_PHY;
242 }
243
244 /* Address cycle complete, setup and write the read
245 * command
246 */
247 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
248 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
249 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
250 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
251
252 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
253
254 /* Check every 10 usec to see if the address cycle
255 * completed. The MDI Command bit will clear when the
256 * operation is complete
257 */
258 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
259 udelay(10);
260
261 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
262 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
263 break;
264 }
265
266 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
267 hw_dbg(hw, "PHY read command didn't complete\n");
268 return IXGBE_ERR_PHY;
269 }
270
271 /* Read operation is complete. Get the data
272 * from MSRWD
273 */
274 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
275 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
276 *phy_data = (u16)(data);
277
278 return 0;
279}
280
9a799d71 281/**
c44ade9e 282 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
3dcc2f41 283 * using the SWFW lock - this function is needed in most cases
9a799d71
AK		 284 * @hw: pointer to hardware structure
285 * @reg_addr: 32 bit address of PHY register to read
286 * @phy_data: Pointer to read data from PHY register
287 **/
c44ade9e
JB		 288s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
289 u32 device_type, u16 *phy_data)
9a799d71 290{
3dcc2f41 291 s32 status;
9a799d71
AK		 292 u16 gssr;
293
294 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
295 gssr = IXGBE_GSSR_PHY1_SM;
296 else
297 gssr = IXGBE_GSSR_PHY0_SM;
298
3dcc2f41
ET		 299 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
300 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
301 phy_data);
302 hw->mac.ops.release_swfw_sync(hw, gssr);
303 } else {
9a799d71 304 status = IXGBE_ERR_SWFW_SYNC;
3dcc2f41 305 }
9a799d71 306
3dcc2f41
ET		 307 return status;
308}
309
310/**
311 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
312 * without SWFW lock
313 * @hw: pointer to hardware structure
314 * @reg_addr: 32 bit PHY register to write
315 * @device_type: 5 bit device type
316 * @phy_data: Data to write to the PHY register
317 **/
318s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
319 u32 device_type, u16 phy_data)
320{
321 u32 i, command;
9a799d71 322
3dcc2f41
ET		 323 /* Put the data in the MDI single read and write data register*/
324 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
9a799d71 325
3dcc2f41
ET		 326 /* Setup and write the address cycle command */
327 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
328 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
329 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
330 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71 331
3dcc2f41 332 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
9a799d71 333
3dcc2f41
ET		 334 /*
335 * Check every 10 usec to see if the address cycle completed.
336 * The MDI Command bit will clear when the operation is
337 * complete
338 */
339 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
340 udelay(10);
9a799d71 341
3dcc2f41
ET		 342 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
343 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
344 break;
345 }
9a799d71 346
3dcc2f41
ET		 347 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
348 hw_dbg(hw, "PHY address cmd didn't complete\n");
349 return IXGBE_ERR_PHY;
350 }
9a799d71 351
3dcc2f41
ET		 352 /*
353 * Address cycle complete, setup and write the write
354 * command
355 */
356 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
357 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
358 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
359 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71 360
3dcc2f41
ET		 361 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
362
363 /* Check every 10 usec to see if the address cycle
364 * completed. The MDI Command bit will clear when the
365 * operation is complete
366 */
367 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
368 udelay(10);
369
370 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
371 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
372 break;
9a799d71 373 }
c44ade9e 374
3dcc2f41
ET		 375 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
376 hw_dbg(hw, "PHY write cmd didn't complete\n");
377 return IXGBE_ERR_PHY;
378 }
379
380 return 0;
9a799d71
AK		 381}
382
383/**
c44ade9e 384 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
3dcc2f41 385 * using SWFW lock- this function is needed in most cases
9a799d71
AK		 386 * @hw: pointer to hardware structure
387 * @reg_addr: 32 bit PHY register to write
388 * @device_type: 5 bit device type
389 * @phy_data: Data to write to the PHY register
390 **/
c44ade9e
JB		 391s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
392 u32 device_type, u16 phy_data)
9a799d71 393{
3dcc2f41 394 s32 status;
9a799d71
AK		 395 u16 gssr;
396
397 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
398 gssr = IXGBE_GSSR_PHY1_SM;
399 else
400 gssr = IXGBE_GSSR_PHY0_SM;
401
3dcc2f41
ET		 402 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
403 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
404 phy_data);
5e655105 405 hw->mac.ops.release_swfw_sync(hw, gssr);
3dcc2f41
ET		 406 } else {
407 status = IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 408 }
409
410 return status;
411}
412
413/**
c44ade9e 414 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 415 * @hw: pointer to hardware structure
416 *
417 * Restart autonegotiation and PHY and waits for completion.
418 **/
c44ade9e 419s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 420{
9dda1736 421 s32 status = 0;
9a799d71
AK		 422 u32 time_out;
423 u32 max_time_out = 10;
9dda1736
ET		 424 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
425 bool autoneg = false;
426 ixgbe_link_speed speed;
9a799d71 427
9dda1736
ET		 428 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
429
430 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
431 /* Set or unset auto-negotiation 10G advertisement */
432 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
433 MDIO_MMD_AN,
434 &autoneg_reg);
9a799d71 435
6b73e10d 436 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9dda1736
ET		 437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
438 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 439
9dda1736
ET		 440 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
441 MDIO_MMD_AN,
442 autoneg_reg);
443 }
444
445 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
446 /* Set or unset auto-negotiation 1G advertisement */
447 hw->phy.ops.read_reg(hw,
448 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
452 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
453 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
454 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
455
456 hw->phy.ops.write_reg(hw,
457 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
458 MDIO_MMD_AN,
459 autoneg_reg);
460 }
461
462 if (speed & IXGBE_LINK_SPEED_100_FULL) {
463 /* Set or unset auto-negotiation 100M advertisement */
464 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
465 MDIO_MMD_AN,
466 &autoneg_reg);
467
a59e8a1a
ET		 468 autoneg_reg &= ~(ADVERTISE_100FULL |
469 ADVERTISE_100HALF);
9dda1736
ET		 470 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
471 autoneg_reg |= ADVERTISE_100FULL;
472
473 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
474 MDIO_MMD_AN,
475 autoneg_reg);
476 }
9a799d71
AK		 477
478 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 479 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
480 MDIO_MMD_AN, &autoneg_reg);
9a799d71 481
6b73e10d 482 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 483
9dda1736
ET		 484 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
485 MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 486
487 /* Wait for autonegotiation to finish */
488 for (time_out = 0; time_out < max_time_out; time_out++) {
489 udelay(10);
490 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 491 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
492 MDIO_MMD_AN,
493 &autoneg_reg);
9a799d71 494
6b73e10d
BH		 495 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
496 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 497 break;
498 }
499 }
500
9dda1736 501 if (time_out == max_time_out) {
9a799d71 502 status = IXGBE_ERR_LINK_SETUP;
9dda1736
ET		 503 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
504 }
9a799d71
AK		 505
506 return status;
507}
508
509/**
c44ade9e 510 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 511 * @hw: pointer to hardware structure
512 * @speed: new link speed
9a799d71 513 **/
c44ade9e
JB		 514s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
515 ixgbe_link_speed speed,
c44ade9e 516 bool autoneg_wait_to_complete)
9a799d71 517{
c44ade9e 518
9a799d71
AK		 519 /*
520 * Clear autoneg_advertised and set new values based on input link
521 * speed.
522 */
523 hw->phy.autoneg_advertised = 0;
524
525 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
526 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 527
9a799d71
AK		 528 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
529 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
530
9dda1736
ET		 531 if (speed & IXGBE_LINK_SPEED_100_FULL)
532 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
533
9a799d71 534 /* Setup link based on the new speed settings */
c44ade9e 535 hw->phy.ops.setup_link(hw);
9a799d71
AK		 536
537 return 0;
538}
c44ade9e 539
a391f1d5
DS		 540/**
541 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
542 * @hw: pointer to hardware structure
543 * @speed: pointer to link speed
544 * @autoneg: boolean auto-negotiation value
545 *
546 * Determines the link capabilities by reading the AUTOC register.
547 */
548s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 549 ixgbe_link_speed *speed,
550 bool *autoneg)
a391f1d5
DS		 551{
552 s32 status = IXGBE_ERR_LINK_SETUP;
553 u16 speed_ability;
554
555 *speed = 0;
556 *autoneg = true;
557
558 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
559 &speed_ability);
560
561 if (status == 0) {
562 if (speed_ability & MDIO_SPEED_10G)
563 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
564 if (speed_ability & MDIO_PMA_SPEED_1000)
565 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
566 if (speed_ability & MDIO_PMA_SPEED_100)
567 *speed |= IXGBE_LINK_SPEED_100_FULL;
568 }
569
570 return status;
571}
572
9dda1736
ET		 573/**
574 * ixgbe_check_phy_link_tnx - Determine link and speed status
575 * @hw: pointer to hardware structure
576 *
577 * Reads the VS1 register to determine if link is up and the current speed for
578 * the PHY.
579 **/
580s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
581 bool *link_up)
582{
583 s32 status = 0;
584 u32 time_out;
585 u32 max_time_out = 10;
586 u16 phy_link = 0;
587 u16 phy_speed = 0;
588 u16 phy_data = 0;
589
590 /* Initialize speed and link to default case */
591 *link_up = false;
592 *speed = IXGBE_LINK_SPEED_10GB_FULL;
593
594 /*
595 * Check current speed and link status of the PHY register.
596 * This is a vendor specific register and may have to
597 * be changed for other copper PHYs.
598 */
599 for (time_out = 0; time_out < max_time_out; time_out++) {
600 udelay(10);
601 status = hw->phy.ops.read_reg(hw,
602 MDIO_STAT1,
603 MDIO_MMD_VEND1,
604 &phy_data);
605 phy_link = phy_data &
606 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
607 phy_speed = phy_data &
608 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
609 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
610 *link_up = true;
611 if (phy_speed ==
612 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
613 *speed = IXGBE_LINK_SPEED_1GB_FULL;
614 break;
615 }
616 }
617
618 return status;
619}
620
621/**
622 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
623 * @hw: pointer to hardware structure
624 *
625 * Restart autonegotiation and PHY and waits for completion.
626 **/
627s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
628{
629 s32 status = 0;
630 u32 time_out;
631 u32 max_time_out = 10;
632 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
633 bool autoneg = false;
634 ixgbe_link_speed speed;
635
636 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
637
638 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
639 /* Set or unset auto-negotiation 10G advertisement */
640 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
641 MDIO_MMD_AN,
642 &autoneg_reg);
643
644 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
645 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
646 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
647
648 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
649 MDIO_MMD_AN,
650 autoneg_reg);
651 }
652
653 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
654 /* Set or unset auto-negotiation 1G advertisement */
655 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
656 MDIO_MMD_AN,
657 &autoneg_reg);
658
659 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
661 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
662
663 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
664 MDIO_MMD_AN,
665 autoneg_reg);
666 }
667
668 if (speed & IXGBE_LINK_SPEED_100_FULL) {
669 /* Set or unset auto-negotiation 100M advertisement */
670 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
671 MDIO_MMD_AN,
672 &autoneg_reg);
673
50c022e7
ET		 674 autoneg_reg &= ~(ADVERTISE_100FULL |
675 ADVERTISE_100HALF);
9dda1736
ET		 676 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
677 autoneg_reg |= ADVERTISE_100FULL;
678
679 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
680 MDIO_MMD_AN,
681 autoneg_reg);
682 }
683
684 /* Restart PHY autonegotiation and wait for completion */
685 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
686 MDIO_MMD_AN, &autoneg_reg);
687
688 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
689
690 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
691 MDIO_MMD_AN, autoneg_reg);
692
693 /* Wait for autonegotiation to finish */
694 for (time_out = 0; time_out < max_time_out; time_out++) {
695 udelay(10);
696 /* Restart PHY autonegotiation and wait for completion */
697 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
698 MDIO_MMD_AN,
699 &autoneg_reg);
700
701 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
702 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
703 break;
704 }
705
706 if (time_out == max_time_out) {
707 status = IXGBE_ERR_LINK_SETUP;
708 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
709 }
710
711 return status;
712}
713
714/**
715 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
716 * @hw: pointer to hardware structure
717 * @firmware_version: pointer to the PHY Firmware Version
718 **/
719s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
720 u16 *firmware_version)
721{
722 s32 status = 0;
723
724 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
725 MDIO_MMD_VEND1,
726 firmware_version);
727
728 return status;
729}
730
731/**
732 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
733 * @hw: pointer to hardware structure
734 * @firmware_version: pointer to the PHY Firmware Version
735 **/
736s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
737 u16 *firmware_version)
738{
739 s32 status = 0;
740
741 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
742 MDIO_MMD_VEND1,
743 firmware_version);
744
745 return status;
746}
747
c4900be0
DS		 748/**
749 * ixgbe_reset_phy_nl - Performs a PHY reset
750 * @hw: pointer to hardware structure
751 **/
752s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
753{
754 u16 phy_offset, control, eword, edata, block_crc;
755 bool end_data = false;
756 u16 list_offset, data_offset;
757 u16 phy_data = 0;
758 s32 ret_val = 0;
759 u32 i;
760
6b73e10d 761 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 762
763 /* reset the PHY and poll for completion */
6b73e10d
BH		 764 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
765 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 766
767 for (i = 0; i < 100; i++) {
6b73e10d
BH		 768 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
769 &phy_data);
770 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0 771 break;
032b4325 772 usleep_range(10000, 20000);
c4900be0
DS		 773 }
774
6b73e10d 775 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 776 hw_dbg(hw, "PHY reset did not complete.\n");
777 ret_val = IXGBE_ERR_PHY;
778 goto out;
779 }
780
781 /* Get init offsets */
782 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
783 &data_offset);
784 if (ret_val != 0)
785 goto out;
786
787 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
788 data_offset++;
789 while (!end_data) {
790 /*
791 * Read control word from PHY init contents offset
792 */
793 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
794 control = (eword & IXGBE_CONTROL_MASK_NL) >>
795 IXGBE_CONTROL_SHIFT_NL;
796 edata = eword & IXGBE_DATA_MASK_NL;
797 switch (control) {
798 case IXGBE_DELAY_NL:
799 data_offset++;
800 hw_dbg(hw, "DELAY: %d MS\n", edata);
032b4325 801 usleep_range(edata * 1000, edata * 2000);
c4900be0
DS		 802 break;
803 case IXGBE_DATA_NL:
d6dbee86 804 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 805 data_offset++;
806 hw->eeprom.ops.read(hw, data_offset++,
807 &phy_offset);
808 for (i = 0; i < edata; i++) {
809 hw->eeprom.ops.read(hw, data_offset, &eword);
810 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 811 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 812 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
813 phy_offset);
814 data_offset++;
815 phy_offset++;
816 }
817 break;
818 case IXGBE_CONTROL_NL:
819 data_offset++;
d6dbee86 820 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 821 if (edata == IXGBE_CONTROL_EOL_NL) {
822 hw_dbg(hw, "EOL\n");
823 end_data = true;
824 } else if (edata == IXGBE_CONTROL_SOL_NL) {
825 hw_dbg(hw, "SOL\n");
826 } else {
827 hw_dbg(hw, "Bad control value\n");
828 ret_val = IXGBE_ERR_PHY;
829 goto out;
830 }
831 break;
832 default:
833 hw_dbg(hw, "Bad control type\n");
834 ret_val = IXGBE_ERR_PHY;
835 goto out;
836 }
837 }
838
839out:
840 return ret_val;
841}
842
843/**
8f58332b 844 * ixgbe_identify_module_generic - Identifies module type
c4900be0
DS		 845 * @hw: pointer to hardware structure
846 *
8f58332b
DS		 847 * Determines HW type and calls appropriate function.
848 **/
849s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
850{
851 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
852
853 switch (hw->mac.ops.get_media_type(hw)) {
854 case ixgbe_media_type_fiber:
855 status = ixgbe_identify_sfp_module_generic(hw);
856 break;
857 case ixgbe_media_type_fiber_qsfp:
858 status = ixgbe_identify_qsfp_module_generic(hw);
859 break;
860 default:
861 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
862 status = IXGBE_ERR_SFP_NOT_PRESENT;
863 break;
864 }
865
866 return status;
867}
868
869/**
870 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
871 * @hw: pointer to hardware structure
872*
76d97dd4 873 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 874 **/
875s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
876{
8ef78adc 877 struct ixgbe_adapter *adapter = hw->back;
c4900be0
DS		 878 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
879 u32 vendor_oui = 0;
553b4497 880 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 881 u8 identifier = 0;
882 u8 comp_codes_1g = 0;
883 u8 comp_codes_10g = 0;
11afc1b1 884 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 885 u8 cable_tech = 0;
ea0a04df 886 u8 cable_spec = 0;
11afc1b1 887 u16 enforce_sfp = 0;
c4900be0 888
8ca783ab
DS		 889 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
890 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
891 status = IXGBE_ERR_SFP_NOT_PRESENT;
892 goto out;
893 }
894
76d97dd4
ET		 895 status = hw->phy.ops.read_i2c_eeprom(hw,
896 IXGBE_SFF_IDENTIFIER,
51d0420b 897 &identifier);
c4900be0 898
51d0420b 899 if (status != 0)
76d97dd4 900 goto err_read_i2c_eeprom;
c4900be0 901
76d97dd4
ET		 902 /* LAN ID is needed for sfp_type determination */
903 hw->mac.ops.set_lan_id(hw);
904
905 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
906 hw->phy.type = ixgbe_phy_sfp_unsupported;
907 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
908 } else {
909 status = hw->phy.ops.read_i2c_eeprom(hw,
910 IXGBE_SFF_1GBE_COMP_CODES,
911 &comp_codes_1g);
912
51d0420b 913 if (status != 0)
76d97dd4
ET		 914 goto err_read_i2c_eeprom;
915
916 status = hw->phy.ops.read_i2c_eeprom(hw,
917 IXGBE_SFF_10GBE_COMP_CODES,
918 &comp_codes_10g);
919
51d0420b 920 if (status != 0)
76d97dd4
ET		 921 goto err_read_i2c_eeprom;
922 status = hw->phy.ops.read_i2c_eeprom(hw,
923 IXGBE_SFF_CABLE_TECHNOLOGY,
924 &cable_tech);
925
51d0420b 926 if (status != 0)
76d97dd4
ET		 927 goto err_read_i2c_eeprom;
928
929 /* ID Module
930 * =========
931 * 0 SFP_DA_CU
932 * 1 SFP_SR
933 * 2 SFP_LR
934 * 3 SFP_DA_CORE0 - 82599-specific
935 * 4 SFP_DA_CORE1 - 82599-specific
936 * 5 SFP_SR/LR_CORE0 - 82599-specific
937 * 6 SFP_SR/LR_CORE1 - 82599-specific
938 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
939 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
940 * 9 SFP_1g_cu_CORE0 - 82599-specific
941 * 10 SFP_1g_cu_CORE1 - 82599-specific
a49fda3e
JK		 942 * 11 SFP_1g_sx_CORE0 - 82599-specific
943 * 12 SFP_1g_sx_CORE1 - 82599-specific
76d97dd4 944 */
11afc1b1 945 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 946 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 947 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
948 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
949 hw->phy.sfp_type = ixgbe_sfp_type_sr;
950 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
951 hw->phy.sfp_type = ixgbe_sfp_type_lr;
952 else
953 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
954 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 955 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 956 if (hw->bus.lan_id == 0)
957 hw->phy.sfp_type =
958 ixgbe_sfp_type_da_cu_core0;
959 else
960 hw->phy.sfp_type =
961 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 962 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
963 hw->phy.ops.read_i2c_eeprom(
964 hw, IXGBE_SFF_CABLE_SPEC_COMP,
965 &cable_spec);
966 if (cable_spec &
967 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
968 if (hw->bus.lan_id == 0)
969 hw->phy.sfp_type =
970 ixgbe_sfp_type_da_act_lmt_core0;
971 else
972 hw->phy.sfp_type =
973 ixgbe_sfp_type_da_act_lmt_core1;
974 } else {
975 hw->phy.sfp_type =
76d97dd4 976 ixgbe_sfp_type_unknown;
ea0a04df 977 }
76d97dd4
ET		 978 } else if (comp_codes_10g &
979 (IXGBE_SFF_10GBASESR_CAPABLE |
980 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 981 if (hw->bus.lan_id == 0)
982 hw->phy.sfp_type =
983 ixgbe_sfp_type_srlr_core0;
984 else
985 hw->phy.sfp_type =
986 ixgbe_sfp_type_srlr_core1;
76d97dd4 987 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 988 if (hw->bus.lan_id == 0)
989 hw->phy.sfp_type =
990 ixgbe_sfp_type_1g_cu_core0;
991 else
992 hw->phy.sfp_type =
993 ixgbe_sfp_type_1g_cu_core1;
a49fda3e
JK		 994 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
995 if (hw->bus.lan_id == 0)
996 hw->phy.sfp_type =
997 ixgbe_sfp_type_1g_sx_core0;
998 else
999 hw->phy.sfp_type =
1000 ixgbe_sfp_type_1g_sx_core1;
345be204
DS		 1001 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1002 if (hw->bus.lan_id == 0)
1003 hw->phy.sfp_type =
1004 ixgbe_sfp_type_1g_lx_core0;
1005 else
1006 hw->phy.sfp_type =
1007 ixgbe_sfp_type_1g_lx_core1;
76d97dd4 1008 } else {
11afc1b1 1009 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 1010 }
11afc1b1 1011 }
c4900be0 1012
553b4497
PW		 1013 if (hw->phy.sfp_type != stored_sfp_type)
1014 hw->phy.sfp_setup_needed = true;
1015
1016 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 1017 hw->phy.multispeed_fiber = false;
553b4497
PW		 1018 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1019 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1020 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1021 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1022 hw->phy.multispeed_fiber = true;
1023
c4900be0 1024 /* Determine PHY vendor */
04193058 1025 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 1026 hw->phy.id = identifier;
76d97dd4 1027 status = hw->phy.ops.read_i2c_eeprom(hw,
51d0420b
ET		 1028 IXGBE_SFF_VENDOR_OUI_BYTE0,
1029 &oui_bytes[0]);
76d97dd4 1030
51d0420b 1031 if (status != 0)
76d97dd4
ET		 1032 goto err_read_i2c_eeprom;
1033
1034 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 1035 IXGBE_SFF_VENDOR_OUI_BYTE1,
1036 &oui_bytes[1]);
76d97dd4 1037
51d0420b 1038 if (status != 0)
76d97dd4
ET		 1039 goto err_read_i2c_eeprom;
1040
1041 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 1042 IXGBE_SFF_VENDOR_OUI_BYTE2,
1043 &oui_bytes[2]);
1044
51d0420b 1045 if (status != 0)
76d97dd4
ET		 1046 goto err_read_i2c_eeprom;
1047
c4900be0
DS		 1048 vendor_oui =
1049 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1050 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1051 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1052
1053 switch (vendor_oui) {
1054 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 1055 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1056 hw->phy.type =
76d97dd4 1057 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 1058 break;
1059 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 1060 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1061 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1062 else
1063 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 1064 break;
1065 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1066 hw->phy.type = ixgbe_phy_sfp_avago;
1067 break;
11afc1b1
PW		 1068 case IXGBE_SFF_VENDOR_OUI_INTEL:
1069 hw->phy.type = ixgbe_phy_sfp_intel;
1070 break;
c4900be0 1071 default:
537d58a0 1072 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1073 hw->phy.type =
76d97dd4 1074 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 1075 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1076 hw->phy.type =
1077 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 1078 else
1079 hw->phy.type = ixgbe_phy_sfp_unknown;
1080 break;
1081 }
1082 }
fa466e91 1083
76d97dd4 1084 /* Allow any DA cable vendor */
ea0a04df
DS		 1085 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1086 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 1087 status = 0;
1088 goto out;
1089 }
1090
cb836a97
DS		 1091 /* Verify supported 1G SFP modules */
1092 if (comp_codes_10g == 0 &&
1093 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
a49fda3e 1094 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
345be204
DS		 1095 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1096 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 1097 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1098 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
fa466e91
WJP		 1099 hw->phy.type = ixgbe_phy_sfp_unsupported;
1100 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1101 goto out;
1102 }
1103
1104 /* Anything else 82598-based is supported */
1105 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 1106 status = 0;
1107 goto out;
1108 }
1109
04193058 1110 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97 1111 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
345be204
DS		 1112 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1113 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1114 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1115 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1116 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1117 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
11afc1b1
PW		 1118 /* Make sure we're a supported PHY type */
1119 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1120 status = 0;
1121 } else {
8ef78adc
PWJ		 1122 if (hw->allow_unsupported_sfp) {
1123 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1124 status = 0;
1125 } else {
1126 hw_dbg(hw,
1127 "SFP+ module not supported\n");
1128 hw->phy.type =
1129 ixgbe_phy_sfp_unsupported;
1130 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1131 }
11afc1b1
PW		 1132 }
1133 } else {
1134 status = 0;
1135 }
c4900be0
DS		 1136 }
1137
1138out:
1139 return status;
76d97dd4
ET		 1140
1141err_read_i2c_eeprom:
1142 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1143 if (hw->phy.type != ixgbe_phy_nl) {
1144 hw->phy.id = 0;
1145 hw->phy.type = ixgbe_phy_unknown;
1146 }
1147 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 1148}
1149
8f58332b
DS		 1150/**
1151 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1152 * @hw: pointer to hardware structure
1153 *
1154 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1155 **/
1156s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1157{
1158 struct ixgbe_adapter *adapter = hw->back;
1159 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1160 u32 vendor_oui = 0;
1161 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1162 u8 identifier = 0;
1163 u8 comp_codes_1g = 0;
1164 u8 comp_codes_10g = 0;
1165 u8 oui_bytes[3] = {0, 0, 0};
1166 u16 enforce_sfp = 0;
1167
1168 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1169 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1170 status = IXGBE_ERR_SFP_NOT_PRESENT;
1171 goto out;
1172 }
1173
1174 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1175 &identifier);
1176
1177 if (status != 0)
1178 goto err_read_i2c_eeprom;
1179
1180 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1181 hw->phy.type = ixgbe_phy_sfp_unsupported;
1182 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1183 goto out;
1184 }
1185
1186 hw->phy.id = identifier;
1187
1188 /* LAN ID is needed for sfp_type determination */
1189 hw->mac.ops.set_lan_id(hw);
1190
1191 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1192 &comp_codes_10g);
1193
1194 if (status != 0)
1195 goto err_read_i2c_eeprom;
1196
1197 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1198 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1199 if (hw->bus.lan_id == 0)
1200 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1201 else
1202 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1203 } else if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) {
1204 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1205 if (hw->bus.lan_id == 0)
1206 hw->phy.sfp_type = ixgbe_sfp_type_da_act_lmt_core0;
1207 else
1208 hw->phy.sfp_type = ixgbe_sfp_type_da_act_lmt_core1;
1209 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1210 IXGBE_SFF_10GBASELR_CAPABLE)) {
1211 if (hw->bus.lan_id == 0)
1212 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1213 else
1214 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1215 } else {
1216 /* unsupported module type */
1217 hw->phy.type = ixgbe_phy_sfp_unsupported;
1218 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1219 goto out;
1220 }
1221
1222 if (hw->phy.sfp_type != stored_sfp_type)
1223 hw->phy.sfp_setup_needed = true;
1224
1225 /* Determine if the QSFP+ PHY is dual speed or not. */
1226 hw->phy.multispeed_fiber = false;
1227 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1228 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1229 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1230 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1231 hw->phy.multispeed_fiber = true;
1232
1233 /* Determine PHY vendor for optical modules */
1234 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1235 IXGBE_SFF_10GBASELR_CAPABLE)) {
1236 status = hw->phy.ops.read_i2c_eeprom(hw,
1237 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1238 &oui_bytes[0]);
1239
1240 if (status != 0)
1241 goto err_read_i2c_eeprom;
1242
1243 status = hw->phy.ops.read_i2c_eeprom(hw,
1244 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1245 &oui_bytes[1]);
1246
1247 if (status != 0)
1248 goto err_read_i2c_eeprom;
1249
1250 status = hw->phy.ops.read_i2c_eeprom(hw,
1251 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1252 &oui_bytes[2]);
1253
1254 if (status != 0)
1255 goto err_read_i2c_eeprom;
1256
1257 vendor_oui =
1258 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1259 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1260 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1261
1262 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1263 hw->phy.type = ixgbe_phy_qsfp_intel;
1264 else
1265 hw->phy.type = ixgbe_phy_qsfp_unknown;
1266
1267 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1268 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1269 /* Make sure we're a supported PHY type */
1270 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1271 status = 0;
1272 } else {
1273 if (hw->allow_unsupported_sfp == true) {
1274 e_warn(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1275 status = 0;
1276 } else {
1277 hw_dbg(hw,
1278 "QSFP module not supported\n");
1279 hw->phy.type =
1280 ixgbe_phy_sfp_unsupported;
1281 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1282 }
1283 }
1284 } else {
1285 status = 0;
1286 }
1287 }
1288
1289out:
1290 return status;
1291
1292err_read_i2c_eeprom:
1293 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1294 hw->phy.id = 0;
1295 hw->phy.type = ixgbe_phy_unknown;
1296
1297 return IXGBE_ERR_SFP_NOT_PRESENT;
1298}
1299
c4900be0 1300/**
76d97dd4 1301 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 1302 * @hw: pointer to hardware structure
1303 * @list_offset: offset to the SFP ID list
1304 * @data_offset: offset to the SFP data block
75f19c3c
ET		 1305 *
1306 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1307 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 1308 **/
1309s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1310 u16 *list_offset,
1311 u16 *data_offset)
1312{
1313 u16 sfp_id;
cb836a97 1314 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 1315
1316 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1317 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1318
1319 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1320 return IXGBE_ERR_SFP_NOT_PRESENT;
1321
1322 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1323 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1324 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1325
cb836a97
DS		 1326 /*
1327 * Limiting active cables and 1G Phys must be initialized as
1328 * SR modules
1329 */
1330 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
345be204 1331 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
a49fda3e
JK		 1332 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1333 sfp_type == ixgbe_sfp_type_1g_sx_core0)
cb836a97
DS		 1334 sfp_type = ixgbe_sfp_type_srlr_core0;
1335 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
345be204 1336 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 1337 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1338 sfp_type == ixgbe_sfp_type_1g_sx_core1)
cb836a97
DS		 1339 sfp_type = ixgbe_sfp_type_srlr_core1;
1340
c4900be0
DS		 1341 /* Read offset to PHY init contents */
1342 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1343
1344 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 1345 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 1346
1347 /* Shift offset to first ID word */
1348 (*list_offset)++;
1349
1350 /*
1351 * Find the matching SFP ID in the EEPROM
1352 * and program the init sequence
1353 */
1354 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1355
1356 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 1357 if (sfp_id == sfp_type) {
c4900be0
DS		 1358 (*list_offset)++;
1359 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1360 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1361 hw_dbg(hw, "SFP+ module not supported\n");
1362 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1363 } else {
1364 break;
1365 }
1366 } else {
1367 (*list_offset) += 2;
1368 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1369 return IXGBE_ERR_PHY;
1370 }
1371 }
1372
1373 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1374 hw_dbg(hw, "No matching SFP+ module found\n");
1375 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1376 }
1377
1378 return 0;
1379}
1380
11afc1b1
PW		 1381/**
1382 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1383 * @hw: pointer to hardware structure
1384 * @byte_offset: EEPROM byte offset to read
1385 * @eeprom_data: value read
1386 *
1387 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1388 **/
1389s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1390 u8 *eeprom_data)
1391{
1392 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1393 IXGBE_I2C_EEPROM_DEV_ADDR,
1394 eeprom_data);
1395}
1396
07ce870b
ET		 1397/**
1398 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1399 * @hw: pointer to hardware structure
1400 * @byte_offset: byte offset at address 0xA2
1401 * @eeprom_data: value read
1402 *
1403 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1404 **/
1405s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1406 u8 *sff8472_data)
1407{
1408 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1409 IXGBE_I2C_EEPROM_DEV_ADDR2,
1410 sff8472_data);
1411}
1412
11afc1b1
PW		 1413/**
1414 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1415 * @hw: pointer to hardware structure
1416 * @byte_offset: EEPROM byte offset to write
1417 * @eeprom_data: value to write
1418 *
1419 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1420 **/
1421s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1422 u8 eeprom_data)
1423{
1424 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1425 IXGBE_I2C_EEPROM_DEV_ADDR,
1426 eeprom_data);
1427}
1428
1429/**
1430 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1431 * @hw: pointer to hardware structure
1432 * @byte_offset: byte offset to read
1433 * @data: value read
1434 *
1435 * Performs byte read operation to SFP module's EEPROM over I2C interface at
3fbaa3ac 1436 * a specified device address.
11afc1b1
PW		 1437 **/
1438s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1439 u8 dev_addr, u8 *data)
1440{
1441 s32 status = 0;
75f19c3c 1442 u32 max_retry = 10;
11afc1b1 1443 u32 retry = 0;
75f19c3c 1444 u16 swfw_mask = 0;
3db1cd5c 1445 bool nack = true;
3fbaa3ac 1446 *data = 0;
11afc1b1 1447
75f19c3c
ET		 1448 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1449 swfw_mask = IXGBE_GSSR_PHY1_SM;
1450 else
1451 swfw_mask = IXGBE_GSSR_PHY0_SM;
1452
11afc1b1 1453 do {
6d980c3e 1454 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1455 status = IXGBE_ERR_SWFW_SYNC;
1456 goto read_byte_out;
1457 }
1458
11afc1b1
PW		 1459 ixgbe_i2c_start(hw);
1460
1461 /* Device Address and write indication */
1462 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1463 if (status != 0)
1464 goto fail;
1465
1466 status = ixgbe_get_i2c_ack(hw);
1467 if (status != 0)
1468 goto fail;
1469
1470 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1471 if (status != 0)
1472 goto fail;
1473
1474 status = ixgbe_get_i2c_ack(hw);
1475 if (status != 0)
1476 goto fail;
1477
1478 ixgbe_i2c_start(hw);
1479
1480 /* Device Address and read indication */
1481 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1482 if (status != 0)
1483 goto fail;
1484
1485 status = ixgbe_get_i2c_ack(hw);
1486 if (status != 0)
1487 goto fail;
1488
1489 status = ixgbe_clock_in_i2c_byte(hw, data);
1490 if (status != 0)
1491 goto fail;
1492
1493 status = ixgbe_clock_out_i2c_bit(hw, nack);
1494 if (status != 0)
1495 goto fail;
1496
1497 ixgbe_i2c_stop(hw);
1498 break;
1499
1500fail:
d0310dc4 1501 ixgbe_i2c_bus_clear(hw);
6d980c3e 1502 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1503 msleep(100);
11afc1b1
PW		 1504 retry++;
1505 if (retry < max_retry)
1506 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1507 else
1508 hw_dbg(hw, "I2C byte read error.\n");
1509
1510 } while (retry < max_retry);
1511
6d980c3e 1512 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1513
1514read_byte_out:
11afc1b1
PW		 1515 return status;
1516}
1517
1518/**
1519 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1520 * @hw: pointer to hardware structure
1521 * @byte_offset: byte offset to write
1522 * @data: value to write
1523 *
1524 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1525 * a specified device address.
1526 **/
1527s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1528 u8 dev_addr, u8 data)
1529{
1530 s32 status = 0;
1531 u32 max_retry = 1;
1532 u32 retry = 0;
75f19c3c
ET		 1533 u16 swfw_mask = 0;
1534
1535 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1536 swfw_mask = IXGBE_GSSR_PHY1_SM;
1537 else
1538 swfw_mask = IXGBE_GSSR_PHY0_SM;
1539
6d980c3e 1540 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1541 status = IXGBE_ERR_SWFW_SYNC;
1542 goto write_byte_out;
1543 }
11afc1b1
PW		 1544
1545 do {
1546 ixgbe_i2c_start(hw);
1547
1548 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1549 if (status != 0)
1550 goto fail;
1551
1552 status = ixgbe_get_i2c_ack(hw);
1553 if (status != 0)
1554 goto fail;
1555
1556 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1557 if (status != 0)
1558 goto fail;
1559
1560 status = ixgbe_get_i2c_ack(hw);
1561 if (status != 0)
1562 goto fail;
1563
1564 status = ixgbe_clock_out_i2c_byte(hw, data);
1565 if (status != 0)
1566 goto fail;
1567
1568 status = ixgbe_get_i2c_ack(hw);
1569 if (status != 0)
1570 goto fail;
1571
1572 ixgbe_i2c_stop(hw);
1573 break;
1574
1575fail:
1576 ixgbe_i2c_bus_clear(hw);
1577 retry++;
1578 if (retry < max_retry)
1579 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1580 else
1581 hw_dbg(hw, "I2C byte write error.\n");
1582 } while (retry < max_retry);
1583
6d980c3e 1584 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1585
1586write_byte_out:
11afc1b1
PW		 1587 return status;
1588}
1589
1590/**
1591 * ixgbe_i2c_start - Sets I2C start condition
1592 * @hw: pointer to hardware structure
1593 *
1594 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1595 **/
1596static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1597{
1598 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1599
1600 /* Start condition must begin with data and clock high */
1601 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1602 ixgbe_raise_i2c_clk(hw, &i2cctl);
1603
1604 /* Setup time for start condition (4.7us) */
1605 udelay(IXGBE_I2C_T_SU_STA);
1606
1607 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1608
1609 /* Hold time for start condition (4us) */
1610 udelay(IXGBE_I2C_T_HD_STA);
1611
1612 ixgbe_lower_i2c_clk(hw, &i2cctl);
1613
1614 /* Minimum low period of clock is 4.7 us */
1615 udelay(IXGBE_I2C_T_LOW);
1616
1617}
1618
1619/**
1620 * ixgbe_i2c_stop - Sets I2C stop condition
1621 * @hw: pointer to hardware structure
1622 *
1623 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1624 **/
1625static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1626{
1627 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1628
1629 /* Stop condition must begin with data low and clock high */
1630 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1631 ixgbe_raise_i2c_clk(hw, &i2cctl);
1632
1633 /* Setup time for stop condition (4us) */
1634 udelay(IXGBE_I2C_T_SU_STO);
1635
1636 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1637
1638 /* bus free time between stop and start (4.7us)*/
1639 udelay(IXGBE_I2C_T_BUF);
1640}
1641
1642/**
1643 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1644 * @hw: pointer to hardware structure
1645 * @data: data byte to clock in
1646 *
1647 * Clocks in one byte data via I2C data/clock
1648 **/
1649static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1650{
11afc1b1 1651 s32 i;
3db1cd5c 1652 bool bit = false;
11afc1b1
PW		 1653
1654 for (i = 7; i >= 0; i--) {
e1befd77 1655 ixgbe_clock_in_i2c_bit(hw, &bit);
11afc1b1 1656 *data |= bit << i;
11afc1b1
PW		 1657 }
1658
e1befd77 1659 return 0;
11afc1b1
PW		 1660}
1661
1662/**
1663 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1664 * @hw: pointer to hardware structure
1665 * @data: data byte clocked out
1666 *
1667 * Clocks out one byte data via I2C data/clock
1668 **/
1669static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1670{
1671 s32 status = 0;
1672 s32 i;
1673 u32 i2cctl;
3db1cd5c 1674 bool bit = false;
11afc1b1
PW		 1675
1676 for (i = 7; i >= 0; i--) {
1677 bit = (data >> i) & 0x1;
1678 status = ixgbe_clock_out_i2c_bit(hw, bit);
1679
1680 if (status != 0)
1681 break;
1682 }
1683
1684 /* Release SDA line (set high) */
1685 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1686 i2cctl |= IXGBE_I2C_DATA_OUT;
1687 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
176f950d 1688 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1689
1690 return status;
1691}
1692
1693/**
1694 * ixgbe_get_i2c_ack - Polls for I2C ACK
1695 * @hw: pointer to hardware structure
1696 *
1697 * Clocks in/out one bit via I2C data/clock
1698 **/
1699static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1700{
e1befd77 1701 s32 status = 0;
11afc1b1
PW		 1702 u32 i = 0;
1703 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1704 u32 timeout = 10;
3db1cd5c 1705 bool ack = true;
11afc1b1 1706
e1befd77 1707 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1 1708
11afc1b1
PW		 1709
1710 /* Minimum high period of clock is 4us */
1711 udelay(IXGBE_I2C_T_HIGH);
1712
1713 /* Poll for ACK. Note that ACK in I2C spec is
1714 * transition from 1 to 0 */
1715 for (i = 0; i < timeout; i++) {
1716 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1717 ack = ixgbe_get_i2c_data(&i2cctl);
1718
1719 udelay(1);
1720 if (ack == 0)
1721 break;
1722 }
1723
1724 if (ack == 1) {
1725 hw_dbg(hw, "I2C ack was not received.\n");
1726 status = IXGBE_ERR_I2C;
1727 }
1728
1729 ixgbe_lower_i2c_clk(hw, &i2cctl);
1730
1731 /* Minimum low period of clock is 4.7 us */
1732 udelay(IXGBE_I2C_T_LOW);
1733
11afc1b1
PW		 1734 return status;
1735}
1736
1737/**
1738 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1739 * @hw: pointer to hardware structure
1740 * @data: read data value
1741 *
1742 * Clocks in one bit via I2C data/clock
1743 **/
1744static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1745{
11afc1b1
PW		 1746 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1747
e1befd77 1748 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1749
1750 /* Minimum high period of clock is 4us */
1751 udelay(IXGBE_I2C_T_HIGH);
1752
1753 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1754 *data = ixgbe_get_i2c_data(&i2cctl);
1755
1756 ixgbe_lower_i2c_clk(hw, &i2cctl);
1757
1758 /* Minimum low period of clock is 4.7 us */
1759 udelay(IXGBE_I2C_T_LOW);
1760
e1befd77 1761 return 0;
11afc1b1
PW		 1762}
1763
1764/**
1765 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1766 * @hw: pointer to hardware structure
1767 * @data: data value to write
1768 *
1769 * Clocks out one bit via I2C data/clock
1770 **/
1771static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1772{
1773 s32 status;
1774 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1775
1776 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1777 if (status == 0) {
e1befd77 1778 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1779
1780 /* Minimum high period of clock is 4us */
1781 udelay(IXGBE_I2C_T_HIGH);
1782
1783 ixgbe_lower_i2c_clk(hw, &i2cctl);
1784
1785 /* Minimum low period of clock is 4.7 us.
1786 * This also takes care of the data hold time.
1787 */
1788 udelay(IXGBE_I2C_T_LOW);
1789 } else {
1790 status = IXGBE_ERR_I2C;
1791 hw_dbg(hw, "I2C data was not set to %X\n", data);
1792 }
1793
1794 return status;
1795}
1796/**
1797 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1798 * @hw: pointer to hardware structure
1799 * @i2cctl: Current value of I2CCTL register
1800 *
1801 * Raises the I2C clock line '0'->'1'
1802 **/
e1befd77 1803static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
11afc1b1 1804{
8f56e4b9
DS		 1805 u32 i = 0;
1806 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1807 u32 i2cctl_r = 0;
11afc1b1 1808
8f56e4b9
DS		 1809 for (i = 0; i < timeout; i++) {
1810 *i2cctl |= IXGBE_I2C_CLK_OUT;
1811 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1812 IXGBE_WRITE_FLUSH(hw);
1813 /* SCL rise time (1000ns) */
1814 udelay(IXGBE_I2C_T_RISE);
1815
1816 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1817 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1818 break;
1819 }
11afc1b1
PW		 1820}
1821
1822/**
1823 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1824 * @hw: pointer to hardware structure
1825 * @i2cctl: Current value of I2CCTL register
1826 *
1827 * Lowers the I2C clock line '1'->'0'
1828 **/
1829static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1830{
1831
1832 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1833
1834 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1835 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1836
1837 /* SCL fall time (300ns) */
1838 udelay(IXGBE_I2C_T_FALL);
1839}
1840
1841/**
1842 * ixgbe_set_i2c_data - Sets the I2C data bit
1843 * @hw: pointer to hardware structure
1844 * @i2cctl: Current value of I2CCTL register
1845 * @data: I2C data value (0 or 1) to set
1846 *
1847 * Sets the I2C data bit
1848 **/
1849static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1850{
1851 s32 status = 0;
1852
1853 if (data)
1854 *i2cctl |= IXGBE_I2C_DATA_OUT;
1855 else
1856 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1857
1858 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1859 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1860
1861 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1862 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1863
1864 /* Verify data was set correctly */
1865 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1866 if (data != ixgbe_get_i2c_data(i2cctl)) {
1867 status = IXGBE_ERR_I2C;
1868 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1869 }
1870
1871 return status;
1872}
1873
1874/**
1875 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1876 * @hw: pointer to hardware structure
1877 * @i2cctl: Current value of I2CCTL register
1878 *
1879 * Returns the I2C data bit value
1880 **/
1881static bool ixgbe_get_i2c_data(u32 *i2cctl)
1882{
1883 bool data;
1884
1885 if (*i2cctl & IXGBE_I2C_DATA_IN)
3db1cd5c 1886 data = true;
11afc1b1 1887 else
3db1cd5c 1888 data = false;
11afc1b1
PW		 1889
1890 return data;
1891}
1892
1893/**
1894 * ixgbe_i2c_bus_clear - Clears the I2C bus
1895 * @hw: pointer to hardware structure
1896 *
1897 * Clears the I2C bus by sending nine clock pulses.
1898 * Used when data line is stuck low.
1899 **/
1900static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1901{
1902 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1903 u32 i;
1904
75f19c3c
ET		 1905 ixgbe_i2c_start(hw);
1906
11afc1b1
PW		 1907 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1908
1909 for (i = 0; i < 9; i++) {
1910 ixgbe_raise_i2c_clk(hw, &i2cctl);
1911
1912 /* Min high period of clock is 4us */
1913 udelay(IXGBE_I2C_T_HIGH);
1914
1915 ixgbe_lower_i2c_clk(hw, &i2cctl);
1916
1917 /* Min low period of clock is 4.7us*/
1918 udelay(IXGBE_I2C_T_LOW);
1919 }
1920
75f19c3c
ET		 1921 ixgbe_i2c_start(hw);
1922
11afc1b1
PW		 1923 /* Put the i2c bus back to default state */
1924 ixgbe_i2c_stop(hw);
1925}
1926
119fc60a 1927/**
25985edc 1928 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
119fc60a
MC		 1929 * @hw: pointer to hardware structure
1930 *
1931 * Checks if the LASI temp alarm status was triggered due to overtemp
1932 **/
1933s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1934{
1935 s32 status = 0;
1936 u16 phy_data = 0;
1937
1938 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1939 goto out;
1940
1941 /* Check that the LASI temp alarm status was triggered */
1942 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1943 MDIO_MMD_PMAPMD, &phy_data);
1944
1945 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1946 goto out;
1947
1948 status = IXGBE_ERR_OVERTEMP;
1949out:
1950 return status;
1951}
Linux kernel - Deliverables
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