projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ixgbe: clear semaphore bits on timeouts
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
434c5e39 4 Copyright(c) 1999 - 2013 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
e1befd77 42static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
11afc1b1
PW		 43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
037c6d0a 60 u16 ext_ability = 0;
9a799d71 61
c44ade9e
JB		 62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 64 hw->phy.mdio.prtad = phy_addr;
6b73e10d 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 66 ixgbe_get_phy_id(hw);
67 hw->phy.type =
68 ixgbe_get_phy_type_from_id(hw->phy.id);
037c6d0a
ET		 69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
c44ade9e
JB		 85 status = 0;
86 break;
87 }
9a799d71 88 }
63d6e1d8 89 /* clear value if nothing found */
037c6d0a
ET		 90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 92 } else {
93 status = 0;
9a799d71 94 }
c44ade9e 95
9a799d71
AK		 96 return status;
97}
98
9a799d71
AK		 99/**
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
102 *
103 **/
104static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
105{
106 u32 status;
107 u16 phy_id_high = 0;
108 u16 phy_id_low = 0;
109
6b73e10d 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 111 &phy_id_high);
9a799d71
AK		 112
113 if (status == 0) {
114 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 116 &phy_id_low);
9a799d71
AK		 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
119 }
9a799d71
AK		 120 return status;
121}
122
123/**
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
126 *
127 **/
128static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
129{
130 enum ixgbe_phy_type phy_type;
131
132 switch (phy_id) {
0befdb3e
JB		 133 case TN1010_PHY_ID:
134 phy_type = ixgbe_phy_tn;
135 break;
2b264909 136 case X540_PHY_ID:
fe15e8e1
DS		 137 phy_type = ixgbe_phy_aq;
138 break;
9a799d71
AK		 139 case QT2022_PHY_ID:
140 phy_type = ixgbe_phy_qt;
141 break;
c4900be0
DS		 142 case ATH_PHY_ID:
143 phy_type = ixgbe_phy_nl;
144 break;
9a799d71
AK		 145 default:
146 phy_type = ixgbe_phy_unknown;
147 break;
148 }
149
150 return phy_type;
151}
152
153/**
c44ade9e 154 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 155 * @hw: pointer to hardware structure
156 **/
c44ade9e 157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 158{
1783575c
ET		 159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
119fc60a
MC		 169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
1783575c 172 goto out;
119fc60a 173
9a799d71
AK		 174 /*
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
177 */
1783575c
ET		 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
9a799d71
AK		 204}
205
3dcc2f41
ET		 206/**
207 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
208 * the SWFW lock
209 * @hw: pointer to hardware structure
210 * @reg_addr: 32 bit address of PHY register to read
211 * @phy_data: Pointer to read data from PHY register
212 **/
213s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
214 u16 *phy_data)
215{
216 u32 i, data, command;
217
218 /* Setup and write the address cycle command */
219 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
220 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
221 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
222 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
223
224 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
225
226 /* Check every 10 usec to see if the address cycle completed.
227 * The MDI Command bit will clear when the operation is
228 * complete
229 */
230 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
231 udelay(10);
232
233 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
234 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
235 break;
236 }
237
238
239 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
240 hw_dbg(hw, "PHY address command did not complete.\n");
241 return IXGBE_ERR_PHY;
242 }
243
244 /* Address cycle complete, setup and write the read
245 * command
246 */
247 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
248 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
249 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
250 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
251
252 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
253
254 /* Check every 10 usec to see if the address cycle
255 * completed. The MDI Command bit will clear when the
256 * operation is complete
257 */
258 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
259 udelay(10);
260
261 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
262 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
263 break;
264 }
265
266 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
267 hw_dbg(hw, "PHY read command didn't complete\n");
268 return IXGBE_ERR_PHY;
269 }
270
271 /* Read operation is complete. Get the data
272 * from MSRWD
273 */
274 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
275 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
276 *phy_data = (u16)(data);
277
278 return 0;
279}
280
9a799d71 281/**
c44ade9e 282 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
3dcc2f41 283 * using the SWFW lock - this function is needed in most cases
9a799d71
AK		 284 * @hw: pointer to hardware structure
285 * @reg_addr: 32 bit address of PHY register to read
286 * @phy_data: Pointer to read data from PHY register
287 **/
c44ade9e
JB		 288s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
289 u32 device_type, u16 *phy_data)
9a799d71 290{
3dcc2f41 291 s32 status;
9a799d71
AK		 292 u16 gssr;
293
294 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
295 gssr = IXGBE_GSSR_PHY1_SM;
296 else
297 gssr = IXGBE_GSSR_PHY0_SM;
298
3dcc2f41
ET		 299 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
300 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
301 phy_data);
302 hw->mac.ops.release_swfw_sync(hw, gssr);
303 } else {
9a799d71 304 status = IXGBE_ERR_SWFW_SYNC;
3dcc2f41 305 }
9a799d71 306
3dcc2f41
ET		 307 return status;
308}
309
310/**
311 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
312 * without SWFW lock
313 * @hw: pointer to hardware structure
314 * @reg_addr: 32 bit PHY register to write
315 * @device_type: 5 bit device type
316 * @phy_data: Data to write to the PHY register
317 **/
318s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
319 u32 device_type, u16 phy_data)
320{
321 u32 i, command;
9a799d71 322
3dcc2f41
ET		 323 /* Put the data in the MDI single read and write data register*/
324 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
9a799d71 325
3dcc2f41
ET		 326 /* Setup and write the address cycle command */
327 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
328 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
329 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
330 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71 331
3dcc2f41 332 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
9a799d71 333
3dcc2f41
ET		 334 /*
335 * Check every 10 usec to see if the address cycle completed.
336 * The MDI Command bit will clear when the operation is
337 * complete
338 */
339 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
340 udelay(10);
9a799d71 341
3dcc2f41
ET		 342 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
343 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
344 break;
345 }
9a799d71 346
3dcc2f41
ET		 347 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
348 hw_dbg(hw, "PHY address cmd didn't complete\n");
349 return IXGBE_ERR_PHY;
350 }
9a799d71 351
3dcc2f41
ET		 352 /*
353 * Address cycle complete, setup and write the write
354 * command
355 */
356 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
357 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
358 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
359 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71 360
3dcc2f41
ET		 361 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
362
363 /* Check every 10 usec to see if the address cycle
364 * completed. The MDI Command bit will clear when the
365 * operation is complete
366 */
367 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
368 udelay(10);
369
370 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
371 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
372 break;
9a799d71 373 }
c44ade9e 374
3dcc2f41
ET		 375 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
376 hw_dbg(hw, "PHY write cmd didn't complete\n");
377 return IXGBE_ERR_PHY;
378 }
379
380 return 0;
9a799d71
AK		 381}
382
383/**
c44ade9e 384 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
3dcc2f41 385 * using SWFW lock- this function is needed in most cases
9a799d71
AK		 386 * @hw: pointer to hardware structure
387 * @reg_addr: 32 bit PHY register to write
388 * @device_type: 5 bit device type
389 * @phy_data: Data to write to the PHY register
390 **/
c44ade9e
JB		 391s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
392 u32 device_type, u16 phy_data)
9a799d71 393{
3dcc2f41 394 s32 status;
9a799d71
AK		 395 u16 gssr;
396
397 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
398 gssr = IXGBE_GSSR_PHY1_SM;
399 else
400 gssr = IXGBE_GSSR_PHY0_SM;
401
3dcc2f41
ET		 402 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
403 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
404 phy_data);
5e655105 405 hw->mac.ops.release_swfw_sync(hw, gssr);
3dcc2f41
ET		 406 } else {
407 status = IXGBE_ERR_SWFW_SYNC;
9a799d71
AK		 408 }
409
410 return status;
411}
412
413/**
c44ade9e 414 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 415 * @hw: pointer to hardware structure
416 *
417 * Restart autonegotiation and PHY and waits for completion.
418 **/
c44ade9e 419s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 420{
9dda1736 421 s32 status = 0;
9a799d71
AK		 422 u32 time_out;
423 u32 max_time_out = 10;
9dda1736
ET		 424 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
425 bool autoneg = false;
426 ixgbe_link_speed speed;
9a799d71 427
9dda1736
ET		 428 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
429
430 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
431 /* Set or unset auto-negotiation 10G advertisement */
432 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
433 MDIO_MMD_AN,
434 &autoneg_reg);
9a799d71 435
6b73e10d 436 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9dda1736
ET		 437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
438 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 439
9dda1736
ET		 440 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
441 MDIO_MMD_AN,
442 autoneg_reg);
443 }
444
445 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
446 /* Set or unset auto-negotiation 1G advertisement */
447 hw->phy.ops.read_reg(hw,
448 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
452 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
453 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
454 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
455
456 hw->phy.ops.write_reg(hw,
457 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
458 MDIO_MMD_AN,
459 autoneg_reg);
460 }
461
462 if (speed & IXGBE_LINK_SPEED_100_FULL) {
463 /* Set or unset auto-negotiation 100M advertisement */
464 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
465 MDIO_MMD_AN,
466 &autoneg_reg);
467
a59e8a1a
ET		 468 autoneg_reg &= ~(ADVERTISE_100FULL |
469 ADVERTISE_100HALF);
9dda1736
ET		 470 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
471 autoneg_reg |= ADVERTISE_100FULL;
472
473 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
474 MDIO_MMD_AN,
475 autoneg_reg);
476 }
9a799d71
AK		 477
478 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 479 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
480 MDIO_MMD_AN, &autoneg_reg);
9a799d71 481
6b73e10d 482 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 483
9dda1736
ET		 484 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
485 MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 486
487 /* Wait for autonegotiation to finish */
488 for (time_out = 0; time_out < max_time_out; time_out++) {
489 udelay(10);
490 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 491 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
492 MDIO_MMD_AN,
493 &autoneg_reg);
9a799d71 494
6b73e10d
BH		 495 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
496 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 497 break;
498 }
499 }
500
9dda1736 501 if (time_out == max_time_out) {
9a799d71 502 status = IXGBE_ERR_LINK_SETUP;
9dda1736
ET		 503 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
504 }
9a799d71
AK		 505
506 return status;
507}
508
509/**
c44ade9e 510 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 511 * @hw: pointer to hardware structure
512 * @speed: new link speed
9a799d71 513 **/
c44ade9e
JB		 514s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
515 ixgbe_link_speed speed,
c44ade9e 516 bool autoneg_wait_to_complete)
9a799d71 517{
c44ade9e 518
9a799d71
AK		 519 /*
520 * Clear autoneg_advertised and set new values based on input link
521 * speed.
522 */
523 hw->phy.autoneg_advertised = 0;
524
525 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
526 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 527
9a799d71
AK		 528 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
529 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
530
9dda1736
ET		 531 if (speed & IXGBE_LINK_SPEED_100_FULL)
532 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
533
9a799d71 534 /* Setup link based on the new speed settings */
c44ade9e 535 hw->phy.ops.setup_link(hw);
9a799d71
AK		 536
537 return 0;
538}
c44ade9e 539
a391f1d5
DS		 540/**
541 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
542 * @hw: pointer to hardware structure
543 * @speed: pointer to link speed
544 * @autoneg: boolean auto-negotiation value
545 *
546 * Determines the link capabilities by reading the AUTOC register.
547 */
548s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 549 ixgbe_link_speed *speed,
550 bool *autoneg)
a391f1d5
DS		 551{
552 s32 status = IXGBE_ERR_LINK_SETUP;
553 u16 speed_ability;
554
555 *speed = 0;
556 *autoneg = true;
557
558 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
559 &speed_ability);
560
561 if (status == 0) {
562 if (speed_ability & MDIO_SPEED_10G)
563 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
564 if (speed_ability & MDIO_PMA_SPEED_1000)
565 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
566 if (speed_ability & MDIO_PMA_SPEED_100)
567 *speed |= IXGBE_LINK_SPEED_100_FULL;
568 }
569
570 return status;
571}
572
9dda1736
ET		 573/**
574 * ixgbe_check_phy_link_tnx - Determine link and speed status
575 * @hw: pointer to hardware structure
576 *
577 * Reads the VS1 register to determine if link is up and the current speed for
578 * the PHY.
579 **/
580s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
581 bool *link_up)
582{
583 s32 status = 0;
584 u32 time_out;
585 u32 max_time_out = 10;
586 u16 phy_link = 0;
587 u16 phy_speed = 0;
588 u16 phy_data = 0;
589
590 /* Initialize speed and link to default case */
591 *link_up = false;
592 *speed = IXGBE_LINK_SPEED_10GB_FULL;
593
594 /*
595 * Check current speed and link status of the PHY register.
596 * This is a vendor specific register and may have to
597 * be changed for other copper PHYs.
598 */
599 for (time_out = 0; time_out < max_time_out; time_out++) {
600 udelay(10);
601 status = hw->phy.ops.read_reg(hw,
602 MDIO_STAT1,
603 MDIO_MMD_VEND1,
604 &phy_data);
605 phy_link = phy_data &
606 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
607 phy_speed = phy_data &
608 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
609 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
610 *link_up = true;
611 if (phy_speed ==
612 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
613 *speed = IXGBE_LINK_SPEED_1GB_FULL;
614 break;
615 }
616 }
617
618 return status;
619}
620
621/**
622 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
623 * @hw: pointer to hardware structure
624 *
625 * Restart autonegotiation and PHY and waits for completion.
626 **/
627s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
628{
629 s32 status = 0;
630 u32 time_out;
631 u32 max_time_out = 10;
632 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
633 bool autoneg = false;
634 ixgbe_link_speed speed;
635
636 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
637
638 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
639 /* Set or unset auto-negotiation 10G advertisement */
640 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
641 MDIO_MMD_AN,
642 &autoneg_reg);
643
644 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
645 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
646 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
647
648 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
649 MDIO_MMD_AN,
650 autoneg_reg);
651 }
652
653 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
654 /* Set or unset auto-negotiation 1G advertisement */
655 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
656 MDIO_MMD_AN,
657 &autoneg_reg);
658
659 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
661 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
662
663 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
664 MDIO_MMD_AN,
665 autoneg_reg);
666 }
667
668 if (speed & IXGBE_LINK_SPEED_100_FULL) {
669 /* Set or unset auto-negotiation 100M advertisement */
670 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
671 MDIO_MMD_AN,
672 &autoneg_reg);
673
50c022e7
ET		 674 autoneg_reg &= ~(ADVERTISE_100FULL |
675 ADVERTISE_100HALF);
9dda1736
ET		 676 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
677 autoneg_reg |= ADVERTISE_100FULL;
678
679 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
680 MDIO_MMD_AN,
681 autoneg_reg);
682 }
683
684 /* Restart PHY autonegotiation and wait for completion */
685 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
686 MDIO_MMD_AN, &autoneg_reg);
687
688 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
689
690 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
691 MDIO_MMD_AN, autoneg_reg);
692
693 /* Wait for autonegotiation to finish */
694 for (time_out = 0; time_out < max_time_out; time_out++) {
695 udelay(10);
696 /* Restart PHY autonegotiation and wait for completion */
697 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
698 MDIO_MMD_AN,
699 &autoneg_reg);
700
701 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
702 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
703 break;
704 }
705
706 if (time_out == max_time_out) {
707 status = IXGBE_ERR_LINK_SETUP;
708 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
709 }
710
711 return status;
712}
713
714/**
715 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
716 * @hw: pointer to hardware structure
717 * @firmware_version: pointer to the PHY Firmware Version
718 **/
719s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
720 u16 *firmware_version)
721{
722 s32 status = 0;
723
724 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
725 MDIO_MMD_VEND1,
726 firmware_version);
727
728 return status;
729}
730
731/**
732 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
733 * @hw: pointer to hardware structure
734 * @firmware_version: pointer to the PHY Firmware Version
735 **/
736s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
737 u16 *firmware_version)
738{
739 s32 status = 0;
740
741 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
742 MDIO_MMD_VEND1,
743 firmware_version);
744
745 return status;
746}
747
c4900be0
DS		 748/**
749 * ixgbe_reset_phy_nl - Performs a PHY reset
750 * @hw: pointer to hardware structure
751 **/
752s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
753{
754 u16 phy_offset, control, eword, edata, block_crc;
755 bool end_data = false;
756 u16 list_offset, data_offset;
757 u16 phy_data = 0;
758 s32 ret_val = 0;
759 u32 i;
760
6b73e10d 761 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 762
763 /* reset the PHY and poll for completion */
6b73e10d
BH		 764 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
765 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 766
767 for (i = 0; i < 100; i++) {
6b73e10d
BH		 768 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
769 &phy_data);
770 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0 771 break;
032b4325 772 usleep_range(10000, 20000);
c4900be0
DS		 773 }
774
6b73e10d 775 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 776 hw_dbg(hw, "PHY reset did not complete.\n");
777 ret_val = IXGBE_ERR_PHY;
778 goto out;
779 }
780
781 /* Get init offsets */
782 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
783 &data_offset);
784 if (ret_val != 0)
785 goto out;
786
787 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
788 data_offset++;
789 while (!end_data) {
790 /*
791 * Read control word from PHY init contents offset
792 */
793 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
794 control = (eword & IXGBE_CONTROL_MASK_NL) >>
795 IXGBE_CONTROL_SHIFT_NL;
796 edata = eword & IXGBE_DATA_MASK_NL;
797 switch (control) {
798 case IXGBE_DELAY_NL:
799 data_offset++;
800 hw_dbg(hw, "DELAY: %d MS\n", edata);
032b4325 801 usleep_range(edata * 1000, edata * 2000);
c4900be0
DS		 802 break;
803 case IXGBE_DATA_NL:
d6dbee86 804 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 805 data_offset++;
806 hw->eeprom.ops.read(hw, data_offset++,
807 &phy_offset);
808 for (i = 0; i < edata; i++) {
809 hw->eeprom.ops.read(hw, data_offset, &eword);
810 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 811 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 812 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
813 phy_offset);
814 data_offset++;
815 phy_offset++;
816 }
817 break;
818 case IXGBE_CONTROL_NL:
819 data_offset++;
d6dbee86 820 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 821 if (edata == IXGBE_CONTROL_EOL_NL) {
822 hw_dbg(hw, "EOL\n");
823 end_data = true;
824 } else if (edata == IXGBE_CONTROL_SOL_NL) {
825 hw_dbg(hw, "SOL\n");
826 } else {
827 hw_dbg(hw, "Bad control value\n");
828 ret_val = IXGBE_ERR_PHY;
829 goto out;
830 }
831 break;
832 default:
833 hw_dbg(hw, "Bad control type\n");
834 ret_val = IXGBE_ERR_PHY;
835 goto out;
836 }
837 }
838
839out:
840 return ret_val;
841}
842
843/**
76d97dd4 844 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
c4900be0
DS		 845 * @hw: pointer to hardware structure
846 *
76d97dd4 847 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 848 **/
849s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
850{
8ef78adc 851 struct ixgbe_adapter *adapter = hw->back;
c4900be0
DS		 852 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
853 u32 vendor_oui = 0;
553b4497 854 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 855 u8 identifier = 0;
856 u8 comp_codes_1g = 0;
857 u8 comp_codes_10g = 0;
11afc1b1 858 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 859 u8 cable_tech = 0;
ea0a04df 860 u8 cable_spec = 0;
11afc1b1 861 u16 enforce_sfp = 0;
c4900be0 862
8ca783ab
DS		 863 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
864 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
865 status = IXGBE_ERR_SFP_NOT_PRESENT;
866 goto out;
867 }
868
76d97dd4
ET		 869 status = hw->phy.ops.read_i2c_eeprom(hw,
870 IXGBE_SFF_IDENTIFIER,
51d0420b 871 &identifier);
c4900be0 872
51d0420b 873 if (status != 0)
76d97dd4 874 goto err_read_i2c_eeprom;
c4900be0 875
76d97dd4
ET		 876 /* LAN ID is needed for sfp_type determination */
877 hw->mac.ops.set_lan_id(hw);
878
879 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
880 hw->phy.type = ixgbe_phy_sfp_unsupported;
881 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
882 } else {
883 status = hw->phy.ops.read_i2c_eeprom(hw,
884 IXGBE_SFF_1GBE_COMP_CODES,
885 &comp_codes_1g);
886
51d0420b 887 if (status != 0)
76d97dd4
ET		 888 goto err_read_i2c_eeprom;
889
890 status = hw->phy.ops.read_i2c_eeprom(hw,
891 IXGBE_SFF_10GBE_COMP_CODES,
892 &comp_codes_10g);
893
51d0420b 894 if (status != 0)
76d97dd4
ET		 895 goto err_read_i2c_eeprom;
896 status = hw->phy.ops.read_i2c_eeprom(hw,
897 IXGBE_SFF_CABLE_TECHNOLOGY,
898 &cable_tech);
899
51d0420b 900 if (status != 0)
76d97dd4
ET		 901 goto err_read_i2c_eeprom;
902
903 /* ID Module
904 * =========
905 * 0 SFP_DA_CU
906 * 1 SFP_SR
907 * 2 SFP_LR
908 * 3 SFP_DA_CORE0 - 82599-specific
909 * 4 SFP_DA_CORE1 - 82599-specific
910 * 5 SFP_SR/LR_CORE0 - 82599-specific
911 * 6 SFP_SR/LR_CORE1 - 82599-specific
912 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
913 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
914 * 9 SFP_1g_cu_CORE0 - 82599-specific
915 * 10 SFP_1g_cu_CORE1 - 82599-specific
a49fda3e
JK		 916 * 11 SFP_1g_sx_CORE0 - 82599-specific
917 * 12 SFP_1g_sx_CORE1 - 82599-specific
76d97dd4 918 */
11afc1b1 919 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 920 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 921 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
922 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
923 hw->phy.sfp_type = ixgbe_sfp_type_sr;
924 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
925 hw->phy.sfp_type = ixgbe_sfp_type_lr;
926 else
927 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
928 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 929 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 930 if (hw->bus.lan_id == 0)
931 hw->phy.sfp_type =
932 ixgbe_sfp_type_da_cu_core0;
933 else
934 hw->phy.sfp_type =
935 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 936 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
937 hw->phy.ops.read_i2c_eeprom(
938 hw, IXGBE_SFF_CABLE_SPEC_COMP,
939 &cable_spec);
940 if (cable_spec &
941 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
942 if (hw->bus.lan_id == 0)
943 hw->phy.sfp_type =
944 ixgbe_sfp_type_da_act_lmt_core0;
945 else
946 hw->phy.sfp_type =
947 ixgbe_sfp_type_da_act_lmt_core1;
948 } else {
949 hw->phy.sfp_type =
76d97dd4 950 ixgbe_sfp_type_unknown;
ea0a04df 951 }
76d97dd4
ET		 952 } else if (comp_codes_10g &
953 (IXGBE_SFF_10GBASESR_CAPABLE |
954 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 955 if (hw->bus.lan_id == 0)
956 hw->phy.sfp_type =
957 ixgbe_sfp_type_srlr_core0;
958 else
959 hw->phy.sfp_type =
960 ixgbe_sfp_type_srlr_core1;
76d97dd4 961 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 962 if (hw->bus.lan_id == 0)
963 hw->phy.sfp_type =
964 ixgbe_sfp_type_1g_cu_core0;
965 else
966 hw->phy.sfp_type =
967 ixgbe_sfp_type_1g_cu_core1;
a49fda3e
JK		 968 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
969 if (hw->bus.lan_id == 0)
970 hw->phy.sfp_type =
971 ixgbe_sfp_type_1g_sx_core0;
972 else
973 hw->phy.sfp_type =
974 ixgbe_sfp_type_1g_sx_core1;
345be204
DS		 975 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
976 if (hw->bus.lan_id == 0)
977 hw->phy.sfp_type =
978 ixgbe_sfp_type_1g_lx_core0;
979 else
980 hw->phy.sfp_type =
981 ixgbe_sfp_type_1g_lx_core1;
76d97dd4 982 } else {
11afc1b1 983 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 984 }
11afc1b1 985 }
c4900be0 986
553b4497
PW		 987 if (hw->phy.sfp_type != stored_sfp_type)
988 hw->phy.sfp_setup_needed = true;
989
990 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 991 hw->phy.multispeed_fiber = false;
553b4497
PW		 992 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
993 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
994 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
995 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
996 hw->phy.multispeed_fiber = true;
997
c4900be0 998 /* Determine PHY vendor */
04193058 999 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 1000 hw->phy.id = identifier;
76d97dd4 1001 status = hw->phy.ops.read_i2c_eeprom(hw,
51d0420b
ET		 1002 IXGBE_SFF_VENDOR_OUI_BYTE0,
1003 &oui_bytes[0]);
76d97dd4 1004
51d0420b 1005 if (status != 0)
76d97dd4
ET		 1006 goto err_read_i2c_eeprom;
1007
1008 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 1009 IXGBE_SFF_VENDOR_OUI_BYTE1,
1010 &oui_bytes[1]);
76d97dd4 1011
51d0420b 1012 if (status != 0)
76d97dd4
ET		 1013 goto err_read_i2c_eeprom;
1014
1015 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 1016 IXGBE_SFF_VENDOR_OUI_BYTE2,
1017 &oui_bytes[2]);
1018
51d0420b 1019 if (status != 0)
76d97dd4
ET		 1020 goto err_read_i2c_eeprom;
1021
c4900be0
DS		 1022 vendor_oui =
1023 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1024 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1025 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1026
1027 switch (vendor_oui) {
1028 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 1029 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1030 hw->phy.type =
76d97dd4 1031 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 1032 break;
1033 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 1034 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1035 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1036 else
1037 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 1038 break;
1039 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1040 hw->phy.type = ixgbe_phy_sfp_avago;
1041 break;
11afc1b1
PW		 1042 case IXGBE_SFF_VENDOR_OUI_INTEL:
1043 hw->phy.type = ixgbe_phy_sfp_intel;
1044 break;
c4900be0 1045 default:
537d58a0 1046 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1047 hw->phy.type =
76d97dd4 1048 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 1049 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1050 hw->phy.type =
1051 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 1052 else
1053 hw->phy.type = ixgbe_phy_sfp_unknown;
1054 break;
1055 }
1056 }
fa466e91 1057
76d97dd4 1058 /* Allow any DA cable vendor */
ea0a04df
DS		 1059 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1060 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 1061 status = 0;
1062 goto out;
1063 }
1064
cb836a97
DS		 1065 /* Verify supported 1G SFP modules */
1066 if (comp_codes_10g == 0 &&
1067 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
a49fda3e 1068 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
345be204
DS		 1069 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1070 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 1071 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1072 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
fa466e91
WJP		 1073 hw->phy.type = ixgbe_phy_sfp_unsupported;
1074 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1075 goto out;
1076 }
1077
1078 /* Anything else 82598-based is supported */
1079 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 1080 status = 0;
1081 goto out;
1082 }
1083
04193058 1084 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97 1085 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
345be204
DS		 1086 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1087 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1088 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1089 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1090 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1091 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
11afc1b1
PW		 1092 /* Make sure we're a supported PHY type */
1093 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1094 status = 0;
1095 } else {
8ef78adc
PWJ		 1096 if (hw->allow_unsupported_sfp) {
1097 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1098 status = 0;
1099 } else {
1100 hw_dbg(hw,
1101 "SFP+ module not supported\n");
1102 hw->phy.type =
1103 ixgbe_phy_sfp_unsupported;
1104 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1105 }
11afc1b1
PW		 1106 }
1107 } else {
1108 status = 0;
1109 }
c4900be0
DS		 1110 }
1111
1112out:
1113 return status;
76d97dd4
ET		 1114
1115err_read_i2c_eeprom:
1116 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1117 if (hw->phy.type != ixgbe_phy_nl) {
1118 hw->phy.id = 0;
1119 hw->phy.type = ixgbe_phy_unknown;
1120 }
1121 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 1122}
1123
1124/**
76d97dd4 1125 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 1126 * @hw: pointer to hardware structure
1127 * @list_offset: offset to the SFP ID list
1128 * @data_offset: offset to the SFP data block
75f19c3c
ET		 1129 *
1130 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1131 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 1132 **/
1133s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1134 u16 *list_offset,
1135 u16 *data_offset)
1136{
1137 u16 sfp_id;
cb836a97 1138 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 1139
1140 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1141 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1142
1143 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1144 return IXGBE_ERR_SFP_NOT_PRESENT;
1145
1146 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1147 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1148 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1149
cb836a97
DS		 1150 /*
1151 * Limiting active cables and 1G Phys must be initialized as
1152 * SR modules
1153 */
1154 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
345be204 1155 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
a49fda3e
JK		 1156 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1157 sfp_type == ixgbe_sfp_type_1g_sx_core0)
cb836a97
DS		 1158 sfp_type = ixgbe_sfp_type_srlr_core0;
1159 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
345be204 1160 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
a49fda3e
JK		 1161 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1162 sfp_type == ixgbe_sfp_type_1g_sx_core1)
cb836a97
DS		 1163 sfp_type = ixgbe_sfp_type_srlr_core1;
1164
c4900be0
DS		 1165 /* Read offset to PHY init contents */
1166 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1167
1168 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 1169 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 1170
1171 /* Shift offset to first ID word */
1172 (*list_offset)++;
1173
1174 /*
1175 * Find the matching SFP ID in the EEPROM
1176 * and program the init sequence
1177 */
1178 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1179
1180 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 1181 if (sfp_id == sfp_type) {
c4900be0
DS		 1182 (*list_offset)++;
1183 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1184 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1185 hw_dbg(hw, "SFP+ module not supported\n");
1186 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1187 } else {
1188 break;
1189 }
1190 } else {
1191 (*list_offset) += 2;
1192 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1193 return IXGBE_ERR_PHY;
1194 }
1195 }
1196
1197 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1198 hw_dbg(hw, "No matching SFP+ module found\n");
1199 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1200 }
1201
1202 return 0;
1203}
1204
11afc1b1
PW		 1205/**
1206 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1207 * @hw: pointer to hardware structure
1208 * @byte_offset: EEPROM byte offset to read
1209 * @eeprom_data: value read
1210 *
1211 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1212 **/
1213s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1214 u8 *eeprom_data)
1215{
1216 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1217 IXGBE_I2C_EEPROM_DEV_ADDR,
1218 eeprom_data);
1219}
1220
07ce870b
ET		 1221/**
1222 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1223 * @hw: pointer to hardware structure
1224 * @byte_offset: byte offset at address 0xA2
1225 * @eeprom_data: value read
1226 *
1227 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1228 **/
1229s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1230 u8 *sff8472_data)
1231{
1232 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1233 IXGBE_I2C_EEPROM_DEV_ADDR2,
1234 sff8472_data);
1235}
1236
11afc1b1
PW		 1237/**
1238 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1239 * @hw: pointer to hardware structure
1240 * @byte_offset: EEPROM byte offset to write
1241 * @eeprom_data: value to write
1242 *
1243 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1244 **/
1245s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1246 u8 eeprom_data)
1247{
1248 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1249 IXGBE_I2C_EEPROM_DEV_ADDR,
1250 eeprom_data);
1251}
1252
1253/**
1254 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1255 * @hw: pointer to hardware structure
1256 * @byte_offset: byte offset to read
1257 * @data: value read
1258 *
1259 * Performs byte read operation to SFP module's EEPROM over I2C interface at
3fbaa3ac 1260 * a specified device address.
11afc1b1
PW		 1261 **/
1262s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1263 u8 dev_addr, u8 *data)
1264{
1265 s32 status = 0;
75f19c3c 1266 u32 max_retry = 10;
11afc1b1 1267 u32 retry = 0;
75f19c3c 1268 u16 swfw_mask = 0;
3db1cd5c 1269 bool nack = true;
3fbaa3ac 1270 *data = 0;
11afc1b1 1271
75f19c3c
ET		 1272 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1273 swfw_mask = IXGBE_GSSR_PHY1_SM;
1274 else
1275 swfw_mask = IXGBE_GSSR_PHY0_SM;
1276
11afc1b1 1277 do {
6d980c3e 1278 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1279 status = IXGBE_ERR_SWFW_SYNC;
1280 goto read_byte_out;
1281 }
1282
11afc1b1
PW		 1283 ixgbe_i2c_start(hw);
1284
1285 /* Device Address and write indication */
1286 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1287 if (status != 0)
1288 goto fail;
1289
1290 status = ixgbe_get_i2c_ack(hw);
1291 if (status != 0)
1292 goto fail;
1293
1294 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1295 if (status != 0)
1296 goto fail;
1297
1298 status = ixgbe_get_i2c_ack(hw);
1299 if (status != 0)
1300 goto fail;
1301
1302 ixgbe_i2c_start(hw);
1303
1304 /* Device Address and read indication */
1305 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1306 if (status != 0)
1307 goto fail;
1308
1309 status = ixgbe_get_i2c_ack(hw);
1310 if (status != 0)
1311 goto fail;
1312
1313 status = ixgbe_clock_in_i2c_byte(hw, data);
1314 if (status != 0)
1315 goto fail;
1316
1317 status = ixgbe_clock_out_i2c_bit(hw, nack);
1318 if (status != 0)
1319 goto fail;
1320
1321 ixgbe_i2c_stop(hw);
1322 break;
1323
1324fail:
d0310dc4 1325 ixgbe_i2c_bus_clear(hw);
6d980c3e 1326 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1327 msleep(100);
11afc1b1
PW		 1328 retry++;
1329 if (retry < max_retry)
1330 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1331 else
1332 hw_dbg(hw, "I2C byte read error.\n");
1333
1334 } while (retry < max_retry);
1335
6d980c3e 1336 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1337
1338read_byte_out:
11afc1b1
PW		 1339 return status;
1340}
1341
1342/**
1343 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1344 * @hw: pointer to hardware structure
1345 * @byte_offset: byte offset to write
1346 * @data: value to write
1347 *
1348 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1349 * a specified device address.
1350 **/
1351s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1352 u8 dev_addr, u8 data)
1353{
1354 s32 status = 0;
1355 u32 max_retry = 1;
1356 u32 retry = 0;
75f19c3c
ET		 1357 u16 swfw_mask = 0;
1358
1359 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1360 swfw_mask = IXGBE_GSSR_PHY1_SM;
1361 else
1362 swfw_mask = IXGBE_GSSR_PHY0_SM;
1363
6d980c3e 1364 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1365 status = IXGBE_ERR_SWFW_SYNC;
1366 goto write_byte_out;
1367 }
11afc1b1
PW		 1368
1369 do {
1370 ixgbe_i2c_start(hw);
1371
1372 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1373 if (status != 0)
1374 goto fail;
1375
1376 status = ixgbe_get_i2c_ack(hw);
1377 if (status != 0)
1378 goto fail;
1379
1380 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1381 if (status != 0)
1382 goto fail;
1383
1384 status = ixgbe_get_i2c_ack(hw);
1385 if (status != 0)
1386 goto fail;
1387
1388 status = ixgbe_clock_out_i2c_byte(hw, data);
1389 if (status != 0)
1390 goto fail;
1391
1392 status = ixgbe_get_i2c_ack(hw);
1393 if (status != 0)
1394 goto fail;
1395
1396 ixgbe_i2c_stop(hw);
1397 break;
1398
1399fail:
1400 ixgbe_i2c_bus_clear(hw);
1401 retry++;
1402 if (retry < max_retry)
1403 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1404 else
1405 hw_dbg(hw, "I2C byte write error.\n");
1406 } while (retry < max_retry);
1407
6d980c3e 1408 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1409
1410write_byte_out:
11afc1b1
PW		 1411 return status;
1412}
1413
1414/**
1415 * ixgbe_i2c_start - Sets I2C start condition
1416 * @hw: pointer to hardware structure
1417 *
1418 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1419 **/
1420static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1421{
1422 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1423
1424 /* Start condition must begin with data and clock high */
1425 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1426 ixgbe_raise_i2c_clk(hw, &i2cctl);
1427
1428 /* Setup time for start condition (4.7us) */
1429 udelay(IXGBE_I2C_T_SU_STA);
1430
1431 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1432
1433 /* Hold time for start condition (4us) */
1434 udelay(IXGBE_I2C_T_HD_STA);
1435
1436 ixgbe_lower_i2c_clk(hw, &i2cctl);
1437
1438 /* Minimum low period of clock is 4.7 us */
1439 udelay(IXGBE_I2C_T_LOW);
1440
1441}
1442
1443/**
1444 * ixgbe_i2c_stop - Sets I2C stop condition
1445 * @hw: pointer to hardware structure
1446 *
1447 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1448 **/
1449static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1450{
1451 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1452
1453 /* Stop condition must begin with data low and clock high */
1454 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1455 ixgbe_raise_i2c_clk(hw, &i2cctl);
1456
1457 /* Setup time for stop condition (4us) */
1458 udelay(IXGBE_I2C_T_SU_STO);
1459
1460 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1461
1462 /* bus free time between stop and start (4.7us)*/
1463 udelay(IXGBE_I2C_T_BUF);
1464}
1465
1466/**
1467 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1468 * @hw: pointer to hardware structure
1469 * @data: data byte to clock in
1470 *
1471 * Clocks in one byte data via I2C data/clock
1472 **/
1473static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1474{
11afc1b1 1475 s32 i;
3db1cd5c 1476 bool bit = false;
11afc1b1
PW		 1477
1478 for (i = 7; i >= 0; i--) {
e1befd77 1479 ixgbe_clock_in_i2c_bit(hw, &bit);
11afc1b1 1480 *data |= bit << i;
11afc1b1
PW		 1481 }
1482
e1befd77 1483 return 0;
11afc1b1
PW		 1484}
1485
1486/**
1487 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1488 * @hw: pointer to hardware structure
1489 * @data: data byte clocked out
1490 *
1491 * Clocks out one byte data via I2C data/clock
1492 **/
1493static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1494{
1495 s32 status = 0;
1496 s32 i;
1497 u32 i2cctl;
3db1cd5c 1498 bool bit = false;
11afc1b1
PW		 1499
1500 for (i = 7; i >= 0; i--) {
1501 bit = (data >> i) & 0x1;
1502 status = ixgbe_clock_out_i2c_bit(hw, bit);
1503
1504 if (status != 0)
1505 break;
1506 }
1507
1508 /* Release SDA line (set high) */
1509 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1510 i2cctl |= IXGBE_I2C_DATA_OUT;
1511 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
176f950d 1512 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1513
1514 return status;
1515}
1516
1517/**
1518 * ixgbe_get_i2c_ack - Polls for I2C ACK
1519 * @hw: pointer to hardware structure
1520 *
1521 * Clocks in/out one bit via I2C data/clock
1522 **/
1523static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1524{
e1befd77 1525 s32 status = 0;
11afc1b1
PW		 1526 u32 i = 0;
1527 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1528 u32 timeout = 10;
3db1cd5c 1529 bool ack = true;
11afc1b1 1530
e1befd77 1531 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1 1532
11afc1b1
PW		 1533
1534 /* Minimum high period of clock is 4us */
1535 udelay(IXGBE_I2C_T_HIGH);
1536
1537 /* Poll for ACK. Note that ACK in I2C spec is
1538 * transition from 1 to 0 */
1539 for (i = 0; i < timeout; i++) {
1540 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1541 ack = ixgbe_get_i2c_data(&i2cctl);
1542
1543 udelay(1);
1544 if (ack == 0)
1545 break;
1546 }
1547
1548 if (ack == 1) {
1549 hw_dbg(hw, "I2C ack was not received.\n");
1550 status = IXGBE_ERR_I2C;
1551 }
1552
1553 ixgbe_lower_i2c_clk(hw, &i2cctl);
1554
1555 /* Minimum low period of clock is 4.7 us */
1556 udelay(IXGBE_I2C_T_LOW);
1557
11afc1b1
PW		 1558 return status;
1559}
1560
1561/**
1562 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1563 * @hw: pointer to hardware structure
1564 * @data: read data value
1565 *
1566 * Clocks in one bit via I2C data/clock
1567 **/
1568static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1569{
11afc1b1
PW		 1570 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1571
e1befd77 1572 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1573
1574 /* Minimum high period of clock is 4us */
1575 udelay(IXGBE_I2C_T_HIGH);
1576
1577 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1578 *data = ixgbe_get_i2c_data(&i2cctl);
1579
1580 ixgbe_lower_i2c_clk(hw, &i2cctl);
1581
1582 /* Minimum low period of clock is 4.7 us */
1583 udelay(IXGBE_I2C_T_LOW);
1584
e1befd77 1585 return 0;
11afc1b1
PW		 1586}
1587
1588/**
1589 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1590 * @hw: pointer to hardware structure
1591 * @data: data value to write
1592 *
1593 * Clocks out one bit via I2C data/clock
1594 **/
1595static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1596{
1597 s32 status;
1598 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1599
1600 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1601 if (status == 0) {
e1befd77 1602 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1603
1604 /* Minimum high period of clock is 4us */
1605 udelay(IXGBE_I2C_T_HIGH);
1606
1607 ixgbe_lower_i2c_clk(hw, &i2cctl);
1608
1609 /* Minimum low period of clock is 4.7 us.
1610 * This also takes care of the data hold time.
1611 */
1612 udelay(IXGBE_I2C_T_LOW);
1613 } else {
1614 status = IXGBE_ERR_I2C;
1615 hw_dbg(hw, "I2C data was not set to %X\n", data);
1616 }
1617
1618 return status;
1619}
1620/**
1621 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1622 * @hw: pointer to hardware structure
1623 * @i2cctl: Current value of I2CCTL register
1624 *
1625 * Raises the I2C clock line '0'->'1'
1626 **/
e1befd77 1627static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
11afc1b1 1628{
8f56e4b9
DS		 1629 u32 i = 0;
1630 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1631 u32 i2cctl_r = 0;
11afc1b1 1632
8f56e4b9
DS		 1633 for (i = 0; i < timeout; i++) {
1634 *i2cctl |= IXGBE_I2C_CLK_OUT;
1635 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1636 IXGBE_WRITE_FLUSH(hw);
1637 /* SCL rise time (1000ns) */
1638 udelay(IXGBE_I2C_T_RISE);
1639
1640 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1641 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1642 break;
1643 }
11afc1b1
PW		 1644}
1645
1646/**
1647 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1648 * @hw: pointer to hardware structure
1649 * @i2cctl: Current value of I2CCTL register
1650 *
1651 * Lowers the I2C clock line '1'->'0'
1652 **/
1653static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1654{
1655
1656 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1657
1658 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1659 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1660
1661 /* SCL fall time (300ns) */
1662 udelay(IXGBE_I2C_T_FALL);
1663}
1664
1665/**
1666 * ixgbe_set_i2c_data - Sets the I2C data bit
1667 * @hw: pointer to hardware structure
1668 * @i2cctl: Current value of I2CCTL register
1669 * @data: I2C data value (0 or 1) to set
1670 *
1671 * Sets the I2C data bit
1672 **/
1673static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1674{
1675 s32 status = 0;
1676
1677 if (data)
1678 *i2cctl |= IXGBE_I2C_DATA_OUT;
1679 else
1680 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1681
1682 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1683 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1684
1685 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1686 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1687
1688 /* Verify data was set correctly */
1689 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1690 if (data != ixgbe_get_i2c_data(i2cctl)) {
1691 status = IXGBE_ERR_I2C;
1692 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1693 }
1694
1695 return status;
1696}
1697
1698/**
1699 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1700 * @hw: pointer to hardware structure
1701 * @i2cctl: Current value of I2CCTL register
1702 *
1703 * Returns the I2C data bit value
1704 **/
1705static bool ixgbe_get_i2c_data(u32 *i2cctl)
1706{
1707 bool data;
1708
1709 if (*i2cctl & IXGBE_I2C_DATA_IN)
3db1cd5c 1710 data = true;
11afc1b1 1711 else
3db1cd5c 1712 data = false;
11afc1b1
PW		 1713
1714 return data;
1715}
1716
1717/**
1718 * ixgbe_i2c_bus_clear - Clears the I2C bus
1719 * @hw: pointer to hardware structure
1720 *
1721 * Clears the I2C bus by sending nine clock pulses.
1722 * Used when data line is stuck low.
1723 **/
1724static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1725{
1726 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1727 u32 i;
1728
75f19c3c
ET		 1729 ixgbe_i2c_start(hw);
1730
11afc1b1
PW		 1731 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1732
1733 for (i = 0; i < 9; i++) {
1734 ixgbe_raise_i2c_clk(hw, &i2cctl);
1735
1736 /* Min high period of clock is 4us */
1737 udelay(IXGBE_I2C_T_HIGH);
1738
1739 ixgbe_lower_i2c_clk(hw, &i2cctl);
1740
1741 /* Min low period of clock is 4.7us*/
1742 udelay(IXGBE_I2C_T_LOW);
1743 }
1744
75f19c3c
ET		 1745 ixgbe_i2c_start(hw);
1746
11afc1b1
PW		 1747 /* Put the i2c bus back to default state */
1748 ixgbe_i2c_stop(hw);
1749}
1750
119fc60a 1751/**
25985edc 1752 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
119fc60a
MC		 1753 * @hw: pointer to hardware structure
1754 *
1755 * Checks if the LASI temp alarm status was triggered due to overtemp
1756 **/
1757s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1758{
1759 s32 status = 0;
1760 u16 phy_data = 0;
1761
1762 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1763 goto out;
1764
1765 /* Check that the LASI temp alarm status was triggered */
1766 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1767 MDIO_MMD_PMAPMD, &phy_data);
1768
1769 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1770 goto out;
1771
1772 status = IXGBE_ERR_OVERTEMP;
1773out:
1774 return status;
1775}
Linux kernel - Deliverables
This page took 0.700111 seconds and 5 git commands to generate.