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e1000e: cleanup checkpatch braces checks
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_phy.c
CommitLineData
9a799d71
AK		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
9a799d71
AK		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
9a799d71
AK		 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe_common.h"
33#include "ixgbe_phy.h"
34
11afc1b1
PW		 35static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
e1befd77 42static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
11afc1b1
PW		 43static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45static bool ixgbe_get_i2c_data(u32 *i2cctl);
46static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
9a799d71
AK		 47static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
9a799d71
AK		 49
50/**
c44ade9e 51 * ixgbe_identify_phy_generic - Get physical layer module
9a799d71
AK		 52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
c44ade9e 56s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
9a799d71
AK		 57{
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
037c6d0a 60 u16 ext_ability = 0;
9a799d71 61
c44ade9e
JB		 62 if (hw->phy.type == ixgbe_phy_unknown) {
63 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63d6e1d8 64 hw->phy.mdio.prtad = phy_addr;
6b73e10d 65 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
c44ade9e
JB		 66 ixgbe_get_phy_id(hw);
67 hw->phy.type =
68 ixgbe_get_phy_type_from_id(hw->phy.id);
037c6d0a
ET		 69
70 if (hw->phy.type == ixgbe_phy_unknown) {
71 hw->phy.ops.read_reg(hw,
72 MDIO_PMA_EXTABLE,
73 MDIO_MMD_PMAPMD,
74 &ext_ability);
75 if (ext_ability &
76 (MDIO_PMA_EXTABLE_10GBT |
77 MDIO_PMA_EXTABLE_1000BT))
78 hw->phy.type =
79 ixgbe_phy_cu_unknown;
80 else
81 hw->phy.type =
82 ixgbe_phy_generic;
83 }
84
c44ade9e
JB		 85 status = 0;
86 break;
87 }
9a799d71 88 }
63d6e1d8 89 /* clear value if nothing found */
037c6d0a
ET		 90 if (status != 0)
91 hw->phy.mdio.prtad = 0;
c44ade9e
JB		 92 } else {
93 status = 0;
9a799d71 94 }
c44ade9e 95
9a799d71
AK		 96 return status;
97}
98
9a799d71
AK		 99/**
100 * ixgbe_get_phy_id - Get the phy type
101 * @hw: pointer to hardware structure
102 *
103 **/
104static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
105{
106 u32 status;
107 u16 phy_id_high = 0;
108 u16 phy_id_low = 0;
109
6b73e10d 110 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
c44ade9e 111 &phy_id_high);
9a799d71
AK		 112
113 if (status == 0) {
114 hw->phy.id = (u32)(phy_id_high << 16);
6b73e10d 115 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
c44ade9e 116 &phy_id_low);
9a799d71
AK		 117 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
118 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
119 }
9a799d71
AK		 120 return status;
121}
122
123/**
124 * ixgbe_get_phy_type_from_id - Get the phy type
125 * @hw: pointer to hardware structure
126 *
127 **/
128static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
129{
130 enum ixgbe_phy_type phy_type;
131
132 switch (phy_id) {
0befdb3e
JB		 133 case TN1010_PHY_ID:
134 phy_type = ixgbe_phy_tn;
135 break;
2b264909 136 case X540_PHY_ID:
fe15e8e1
DS		 137 phy_type = ixgbe_phy_aq;
138 break;
9a799d71
AK		 139 case QT2022_PHY_ID:
140 phy_type = ixgbe_phy_qt;
141 break;
c4900be0
DS		 142 case ATH_PHY_ID:
143 phy_type = ixgbe_phy_nl;
144 break;
9a799d71
AK		 145 default:
146 phy_type = ixgbe_phy_unknown;
147 break;
148 }
149
150 return phy_type;
151}
152
153/**
c44ade9e 154 * ixgbe_reset_phy_generic - Performs a PHY reset
9a799d71
AK		 155 * @hw: pointer to hardware structure
156 **/
c44ade9e 157s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
9a799d71 158{
1783575c
ET		 159 u32 i;
160 u16 ctrl = 0;
161 s32 status = 0;
162
163 if (hw->phy.type == ixgbe_phy_unknown)
164 status = ixgbe_identify_phy_generic(hw);
165
166 if (status != 0 || hw->phy.type == ixgbe_phy_none)
167 goto out;
168
119fc60a
MC		 169 /* Don't reset PHY if it's shut down due to overtemp. */
170 if (!hw->phy.reset_if_overtemp &&
171 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
1783575c 172 goto out;
119fc60a 173
9a799d71
AK		 174 /*
175 * Perform soft PHY reset to the PHY_XS.
176 * This will cause a soft reset to the PHY
177 */
1783575c
ET		 178 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
179 MDIO_MMD_PHYXS,
180 MDIO_CTRL1_RESET);
181
182 /*
183 * Poll for reset bit to self-clear indicating reset is complete.
184 * Some PHYs could take up to 3 seconds to complete and need about
185 * 1.7 usec delay after the reset is complete.
186 */
187 for (i = 0; i < 30; i++) {
188 msleep(100);
189 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
190 MDIO_MMD_PHYXS, &ctrl);
191 if (!(ctrl & MDIO_CTRL1_RESET)) {
192 udelay(2);
193 break;
194 }
195 }
196
197 if (ctrl & MDIO_CTRL1_RESET) {
198 status = IXGBE_ERR_RESET_FAILED;
199 hw_dbg(hw, "PHY reset polling failed to complete.\n");
200 }
201
202out:
203 return status;
9a799d71
AK		 204}
205
206/**
c44ade9e 207 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
9a799d71
AK		 208 * @hw: pointer to hardware structure
209 * @reg_addr: 32 bit address of PHY register to read
210 * @phy_data: Pointer to read data from PHY register
211 **/
c44ade9e
JB		 212s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
213 u32 device_type, u16 *phy_data)
9a799d71
AK		 214{
215 u32 command;
216 u32 i;
9a799d71
AK		 217 u32 data;
218 s32 status = 0;
219 u16 gssr;
220
221 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
222 gssr = IXGBE_GSSR_PHY1_SM;
223 else
224 gssr = IXGBE_GSSR_PHY0_SM;
225
5e655105 226 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
9a799d71
AK		 227 status = IXGBE_ERR_SWFW_SYNC;
228
229 if (status == 0) {
230 /* Setup and write the address cycle command */
231 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 232 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 233 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 234 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 235
236 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
237
238 /*
239 * Check every 10 usec to see if the address cycle completed.
240 * The MDI Command bit will clear when the operation is
241 * complete
242 */
c44ade9e 243 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 244 udelay(10);
245
246 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
247
248 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
249 break;
250 }
251
252 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
253 hw_dbg(hw, "PHY address command did not complete.\n");
254 status = IXGBE_ERR_PHY;
255 }
256
257 if (status == 0) {
258 /*
259 * Address cycle complete, setup and write the read
260 * command
261 */
262 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 263 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 264 (hw->phy.mdio.prtad <<
265 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 266 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 267
268 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
269
270 /*
271 * Check every 10 usec to see if the address cycle
272 * completed. The MDI Command bit will clear when the
273 * operation is complete
274 */
c44ade9e 275 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 276 udelay(10);
277
278 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
279
280 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
281 break;
282 }
283
284 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
c44ade9e 285 hw_dbg(hw, "PHY read command didn't complete\n");
9a799d71
AK		 286 status = IXGBE_ERR_PHY;
287 } else {
288 /*
289 * Read operation is complete. Get the data
290 * from MSRWD
291 */
292 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
293 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
294 *phy_data = (u16)(data);
295 }
296 }
297
5e655105 298 hw->mac.ops.release_swfw_sync(hw, gssr);
9a799d71 299 }
c44ade9e 300
9a799d71
AK		 301 return status;
302}
303
304/**
c44ade9e 305 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
9a799d71
AK		 306 * @hw: pointer to hardware structure
307 * @reg_addr: 32 bit PHY register to write
308 * @device_type: 5 bit device type
309 * @phy_data: Data to write to the PHY register
310 **/
c44ade9e
JB		 311s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
312 u32 device_type, u16 phy_data)
9a799d71
AK		 313{
314 u32 command;
315 u32 i;
9a799d71
AK		 316 s32 status = 0;
317 u16 gssr;
318
319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
320 gssr = IXGBE_GSSR_PHY1_SM;
321 else
322 gssr = IXGBE_GSSR_PHY0_SM;
323
5e655105 324 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
9a799d71
AK		 325 status = IXGBE_ERR_SWFW_SYNC;
326
327 if (status == 0) {
328 /* Put the data in the MDI single read and write data register*/
329 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
330
331 /* Setup and write the address cycle command */
332 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 333 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d 334 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 335 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 336
337 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
338
339 /*
340 * Check every 10 usec to see if the address cycle completed.
341 * The MDI Command bit will clear when the operation is
342 * complete
343 */
c44ade9e 344 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 345 udelay(10);
346
347 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
348
c44ade9e 349 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 350 break;
9a799d71
AK		 351 }
352
c44ade9e
JB		 353 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
354 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 355 status = IXGBE_ERR_PHY;
c44ade9e 356 }
9a799d71
AK		 357
358 if (status == 0) {
359 /*
360 * Address cycle complete, setup and write the write
361 * command
362 */
363 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
c44ade9e 364 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
6b73e10d
BH		 365 (hw->phy.mdio.prtad <<
366 IXGBE_MSCA_PHY_ADDR_SHIFT) |
c44ade9e 367 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
9a799d71
AK		 368
369 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
370
371 /*
372 * Check every 10 usec to see if the address cycle
373 * completed. The MDI Command bit will clear when the
374 * operation is complete
375 */
c44ade9e 376 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
9a799d71
AK		 377 udelay(10);
378
379 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
380
c44ade9e 381 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
9a799d71 382 break;
9a799d71
AK		 383 }
384
c44ade9e
JB		 385 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
386 hw_dbg(hw, "PHY address cmd didn't complete\n");
9a799d71 387 status = IXGBE_ERR_PHY;
c44ade9e 388 }
9a799d71
AK		 389 }
390
5e655105 391 hw->mac.ops.release_swfw_sync(hw, gssr);
9a799d71
AK		 392 }
393
394 return status;
395}
396
397/**
c44ade9e 398 * ixgbe_setup_phy_link_generic - Set and restart autoneg
9a799d71
AK		 399 * @hw: pointer to hardware structure
400 *
401 * Restart autonegotiation and PHY and waits for completion.
402 **/
c44ade9e 403s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
9a799d71 404{
9dda1736 405 s32 status = 0;
9a799d71
AK		 406 u32 time_out;
407 u32 max_time_out = 10;
9dda1736
ET		 408 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
409 bool autoneg = false;
410 ixgbe_link_speed speed;
9a799d71 411
9dda1736
ET		 412 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
413
414 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
415 /* Set or unset auto-negotiation 10G advertisement */
416 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
417 MDIO_MMD_AN,
418 &autoneg_reg);
9a799d71 419
6b73e10d 420 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
9dda1736
ET		 421 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
422 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
9a799d71 423
9dda1736
ET		 424 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
425 MDIO_MMD_AN,
426 autoneg_reg);
427 }
428
429 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
430 /* Set or unset auto-negotiation 1G advertisement */
431 hw->phy.ops.read_reg(hw,
432 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
433 MDIO_MMD_AN,
434 &autoneg_reg);
435
436 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
437 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
438 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
439
440 hw->phy.ops.write_reg(hw,
441 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
442 MDIO_MMD_AN,
443 autoneg_reg);
444 }
445
446 if (speed & IXGBE_LINK_SPEED_100_FULL) {
447 /* Set or unset auto-negotiation 100M advertisement */
448 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
449 MDIO_MMD_AN,
450 &autoneg_reg);
451
a59e8a1a
ET		 452 autoneg_reg &= ~(ADVERTISE_100FULL |
453 ADVERTISE_100HALF);
9dda1736
ET		 454 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
455 autoneg_reg |= ADVERTISE_100FULL;
456
457 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
458 MDIO_MMD_AN,
459 autoneg_reg);
460 }
9a799d71
AK		 461
462 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 463 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
464 MDIO_MMD_AN, &autoneg_reg);
9a799d71 465
6b73e10d 466 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
9a799d71 467
9dda1736
ET		 468 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
469 MDIO_MMD_AN, autoneg_reg);
9a799d71
AK		 470
471 /* Wait for autonegotiation to finish */
472 for (time_out = 0; time_out < max_time_out; time_out++) {
473 udelay(10);
474 /* Restart PHY autonegotiation and wait for completion */
9dda1736
ET		 475 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
476 MDIO_MMD_AN,
477 &autoneg_reg);
9a799d71 478
6b73e10d
BH		 479 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
480 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
9a799d71
AK		 481 break;
482 }
483 }
484
9dda1736 485 if (time_out == max_time_out) {
9a799d71 486 status = IXGBE_ERR_LINK_SETUP;
9dda1736
ET		 487 hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out");
488 }
9a799d71
AK		 489
490 return status;
491}
492
493/**
c44ade9e 494 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
9a799d71
AK		 495 * @hw: pointer to hardware structure
496 * @speed: new link speed
9a799d71 497 **/
c44ade9e
JB		 498s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
499 ixgbe_link_speed speed,
c44ade9e 500 bool autoneg_wait_to_complete)
9a799d71 501{
c44ade9e 502
9a799d71
AK		 503 /*
504 * Clear autoneg_advertised and set new values based on input link
505 * speed.
506 */
507 hw->phy.autoneg_advertised = 0;
508
509 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
510 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
c44ade9e 511
9a799d71
AK		 512 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
513 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
514
9dda1736
ET		 515 if (speed & IXGBE_LINK_SPEED_100_FULL)
516 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
517
9a799d71 518 /* Setup link based on the new speed settings */
c44ade9e 519 hw->phy.ops.setup_link(hw);
9a799d71
AK		 520
521 return 0;
522}
c44ade9e 523
a391f1d5
DS		 524/**
525 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
526 * @hw: pointer to hardware structure
527 * @speed: pointer to link speed
528 * @autoneg: boolean auto-negotiation value
529 *
530 * Determines the link capabilities by reading the AUTOC register.
531 */
532s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
fe15e8e1
DS		 533 ixgbe_link_speed *speed,
534 bool *autoneg)
a391f1d5
DS		 535{
536 s32 status = IXGBE_ERR_LINK_SETUP;
537 u16 speed_ability;
538
539 *speed = 0;
540 *autoneg = true;
541
542 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
543 &speed_ability);
544
545 if (status == 0) {
546 if (speed_ability & MDIO_SPEED_10G)
547 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
548 if (speed_ability & MDIO_PMA_SPEED_1000)
549 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
550 if (speed_ability & MDIO_PMA_SPEED_100)
551 *speed |= IXGBE_LINK_SPEED_100_FULL;
552 }
553
554 return status;
555}
556
9dda1736
ET		 557/**
558 * ixgbe_check_phy_link_tnx - Determine link and speed status
559 * @hw: pointer to hardware structure
560 *
561 * Reads the VS1 register to determine if link is up and the current speed for
562 * the PHY.
563 **/
564s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
565 bool *link_up)
566{
567 s32 status = 0;
568 u32 time_out;
569 u32 max_time_out = 10;
570 u16 phy_link = 0;
571 u16 phy_speed = 0;
572 u16 phy_data = 0;
573
574 /* Initialize speed and link to default case */
575 *link_up = false;
576 *speed = IXGBE_LINK_SPEED_10GB_FULL;
577
578 /*
579 * Check current speed and link status of the PHY register.
580 * This is a vendor specific register and may have to
581 * be changed for other copper PHYs.
582 */
583 for (time_out = 0; time_out < max_time_out; time_out++) {
584 udelay(10);
585 status = hw->phy.ops.read_reg(hw,
586 MDIO_STAT1,
587 MDIO_MMD_VEND1,
588 &phy_data);
589 phy_link = phy_data &
590 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
591 phy_speed = phy_data &
592 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
593 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
594 *link_up = true;
595 if (phy_speed ==
596 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
597 *speed = IXGBE_LINK_SPEED_1GB_FULL;
598 break;
599 }
600 }
601
602 return status;
603}
604
605/**
606 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
607 * @hw: pointer to hardware structure
608 *
609 * Restart autonegotiation and PHY and waits for completion.
610 **/
611s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
612{
613 s32 status = 0;
614 u32 time_out;
615 u32 max_time_out = 10;
616 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
617 bool autoneg = false;
618 ixgbe_link_speed speed;
619
620 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
621
622 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
623 /* Set or unset auto-negotiation 10G advertisement */
624 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
625 MDIO_MMD_AN,
626 &autoneg_reg);
627
628 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
629 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
630 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
631
632 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
633 MDIO_MMD_AN,
634 autoneg_reg);
635 }
636
637 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
638 /* Set or unset auto-negotiation 1G advertisement */
639 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
640 MDIO_MMD_AN,
641 &autoneg_reg);
642
643 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
644 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
645 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
646
647 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
648 MDIO_MMD_AN,
649 autoneg_reg);
650 }
651
652 if (speed & IXGBE_LINK_SPEED_100_FULL) {
653 /* Set or unset auto-negotiation 100M advertisement */
654 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
655 MDIO_MMD_AN,
656 &autoneg_reg);
657
50c022e7
ET		 658 autoneg_reg &= ~(ADVERTISE_100FULL |
659 ADVERTISE_100HALF);
9dda1736
ET		 660 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
661 autoneg_reg |= ADVERTISE_100FULL;
662
663 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
664 MDIO_MMD_AN,
665 autoneg_reg);
666 }
667
668 /* Restart PHY autonegotiation and wait for completion */
669 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
670 MDIO_MMD_AN, &autoneg_reg);
671
672 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
673
674 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
675 MDIO_MMD_AN, autoneg_reg);
676
677 /* Wait for autonegotiation to finish */
678 for (time_out = 0; time_out < max_time_out; time_out++) {
679 udelay(10);
680 /* Restart PHY autonegotiation and wait for completion */
681 status = hw->phy.ops.read_reg(hw, MDIO_STAT1,
682 MDIO_MMD_AN,
683 &autoneg_reg);
684
685 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
686 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE)
687 break;
688 }
689
690 if (time_out == max_time_out) {
691 status = IXGBE_ERR_LINK_SETUP;
692 hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out");
693 }
694
695 return status;
696}
697
698/**
699 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
700 * @hw: pointer to hardware structure
701 * @firmware_version: pointer to the PHY Firmware Version
702 **/
703s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
704 u16 *firmware_version)
705{
706 s32 status = 0;
707
708 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
709 MDIO_MMD_VEND1,
710 firmware_version);
711
712 return status;
713}
714
715/**
716 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
717 * @hw: pointer to hardware structure
718 * @firmware_version: pointer to the PHY Firmware Version
719 **/
720s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
721 u16 *firmware_version)
722{
723 s32 status = 0;
724
725 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
726 MDIO_MMD_VEND1,
727 firmware_version);
728
729 return status;
730}
731
c4900be0
DS		 732/**
733 * ixgbe_reset_phy_nl - Performs a PHY reset
734 * @hw: pointer to hardware structure
735 **/
736s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
737{
738 u16 phy_offset, control, eword, edata, block_crc;
739 bool end_data = false;
740 u16 list_offset, data_offset;
741 u16 phy_data = 0;
742 s32 ret_val = 0;
743 u32 i;
744
6b73e10d 745 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
c4900be0
DS		 746
747 /* reset the PHY and poll for completion */
6b73e10d
BH		 748 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
749 (phy_data | MDIO_CTRL1_RESET));
c4900be0
DS		 750
751 for (i = 0; i < 100; i++) {
6b73e10d
BH		 752 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
753 &phy_data);
754 if ((phy_data & MDIO_CTRL1_RESET) == 0)
c4900be0 755 break;
032b4325 756 usleep_range(10000, 20000);
c4900be0
DS		 757 }
758
6b73e10d 759 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
c4900be0
DS		 760 hw_dbg(hw, "PHY reset did not complete.\n");
761 ret_val = IXGBE_ERR_PHY;
762 goto out;
763 }
764
765 /* Get init offsets */
766 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
767 &data_offset);
768 if (ret_val != 0)
769 goto out;
770
771 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
772 data_offset++;
773 while (!end_data) {
774 /*
775 * Read control word from PHY init contents offset
776 */
777 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
778 control = (eword & IXGBE_CONTROL_MASK_NL) >>
779 IXGBE_CONTROL_SHIFT_NL;
780 edata = eword & IXGBE_DATA_MASK_NL;
781 switch (control) {
782 case IXGBE_DELAY_NL:
783 data_offset++;
784 hw_dbg(hw, "DELAY: %d MS\n", edata);
032b4325 785 usleep_range(edata * 1000, edata * 2000);
c4900be0
DS		 786 break;
787 case IXGBE_DATA_NL:
d6dbee86 788 hw_dbg(hw, "DATA:\n");
c4900be0
DS		 789 data_offset++;
790 hw->eeprom.ops.read(hw, data_offset++,
791 &phy_offset);
792 for (i = 0; i < edata; i++) {
793 hw->eeprom.ops.read(hw, data_offset, &eword);
794 hw->phy.ops.write_reg(hw, phy_offset,
6b73e10d 795 MDIO_MMD_PMAPMD, eword);
c4900be0
DS		 796 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
797 phy_offset);
798 data_offset++;
799 phy_offset++;
800 }
801 break;
802 case IXGBE_CONTROL_NL:
803 data_offset++;
d6dbee86 804 hw_dbg(hw, "CONTROL:\n");
c4900be0
DS		 805 if (edata == IXGBE_CONTROL_EOL_NL) {
806 hw_dbg(hw, "EOL\n");
807 end_data = true;
808 } else if (edata == IXGBE_CONTROL_SOL_NL) {
809 hw_dbg(hw, "SOL\n");
810 } else {
811 hw_dbg(hw, "Bad control value\n");
812 ret_val = IXGBE_ERR_PHY;
813 goto out;
814 }
815 break;
816 default:
817 hw_dbg(hw, "Bad control type\n");
818 ret_val = IXGBE_ERR_PHY;
819 goto out;
820 }
821 }
822
823out:
824 return ret_val;
825}
826
827/**
76d97dd4 828 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
c4900be0
DS		 829 * @hw: pointer to hardware structure
830 *
76d97dd4 831 * Searches for and identifies the SFP module and assigns appropriate PHY type.
c4900be0
DS		 832 **/
833s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
834{
8ef78adc 835 struct ixgbe_adapter *adapter = hw->back;
c4900be0
DS		 836 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
837 u32 vendor_oui = 0;
553b4497 838 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
c4900be0
DS		 839 u8 identifier = 0;
840 u8 comp_codes_1g = 0;
841 u8 comp_codes_10g = 0;
11afc1b1 842 u8 oui_bytes[3] = {0, 0, 0};
537d58a0 843 u8 cable_tech = 0;
ea0a04df 844 u8 cable_spec = 0;
11afc1b1 845 u16 enforce_sfp = 0;
c4900be0 846
8ca783ab
DS		 847 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
848 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
849 status = IXGBE_ERR_SFP_NOT_PRESENT;
850 goto out;
851 }
852
76d97dd4
ET		 853 status = hw->phy.ops.read_i2c_eeprom(hw,
854 IXGBE_SFF_IDENTIFIER,
c4900be0
DS		 855 &identifier);
856
76d97dd4
ET		 857 if (status == IXGBE_ERR_SWFW_SYNC ||
858 status == IXGBE_ERR_I2C ||
859 status == IXGBE_ERR_SFP_NOT_PRESENT)
860 goto err_read_i2c_eeprom;
c4900be0 861
76d97dd4
ET		 862 /* LAN ID is needed for sfp_type determination */
863 hw->mac.ops.set_lan_id(hw);
864
865 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
866 hw->phy.type = ixgbe_phy_sfp_unsupported;
867 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
868 } else {
869 status = hw->phy.ops.read_i2c_eeprom(hw,
870 IXGBE_SFF_1GBE_COMP_CODES,
871 &comp_codes_1g);
872
873 if (status == IXGBE_ERR_SWFW_SYNC ||
874 status == IXGBE_ERR_I2C ||
875 status == IXGBE_ERR_SFP_NOT_PRESENT)
876 goto err_read_i2c_eeprom;
877
878 status = hw->phy.ops.read_i2c_eeprom(hw,
879 IXGBE_SFF_10GBE_COMP_CODES,
880 &comp_codes_10g);
881
882 if (status == IXGBE_ERR_SWFW_SYNC ||
883 status == IXGBE_ERR_I2C ||
884 status == IXGBE_ERR_SFP_NOT_PRESENT)
885 goto err_read_i2c_eeprom;
886 status = hw->phy.ops.read_i2c_eeprom(hw,
887 IXGBE_SFF_CABLE_TECHNOLOGY,
888 &cable_tech);
889
890 if (status == IXGBE_ERR_SWFW_SYNC ||
891 status == IXGBE_ERR_I2C ||
892 status == IXGBE_ERR_SFP_NOT_PRESENT)
893 goto err_read_i2c_eeprom;
894
895 /* ID Module
896 * =========
897 * 0 SFP_DA_CU
898 * 1 SFP_SR
899 * 2 SFP_LR
900 * 3 SFP_DA_CORE0 - 82599-specific
901 * 4 SFP_DA_CORE1 - 82599-specific
902 * 5 SFP_SR/LR_CORE0 - 82599-specific
903 * 6 SFP_SR/LR_CORE1 - 82599-specific
904 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
905 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
906 * 9 SFP_1g_cu_CORE0 - 82599-specific
907 * 10 SFP_1g_cu_CORE1 - 82599-specific
a49fda3e
JK		 908 * 11 SFP_1g_sx_CORE0 - 82599-specific
909 * 12 SFP_1g_sx_CORE1 - 82599-specific
76d97dd4 910 */
11afc1b1 911 if (hw->mac.type == ixgbe_mac_82598EB) {
537d58a0 912 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
11afc1b1
PW		 913 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
914 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
915 hw->phy.sfp_type = ixgbe_sfp_type_sr;
916 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
917 hw->phy.sfp_type = ixgbe_sfp_type_lr;
918 else
919 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
920 } else if (hw->mac.type == ixgbe_mac_82599EB) {
ea0a04df 921 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
11afc1b1
PW		 922 if (hw->bus.lan_id == 0)
923 hw->phy.sfp_type =
924 ixgbe_sfp_type_da_cu_core0;
925 else
926 hw->phy.sfp_type =
927 ixgbe_sfp_type_da_cu_core1;
ea0a04df
DS		 928 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
929 hw->phy.ops.read_i2c_eeprom(
930 hw, IXGBE_SFF_CABLE_SPEC_COMP,
931 &cable_spec);
932 if (cable_spec &
933 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
934 if (hw->bus.lan_id == 0)
935 hw->phy.sfp_type =
936 ixgbe_sfp_type_da_act_lmt_core0;
937 else
938 hw->phy.sfp_type =
939 ixgbe_sfp_type_da_act_lmt_core1;
940 } else {
941 hw->phy.sfp_type =
76d97dd4 942 ixgbe_sfp_type_unknown;
ea0a04df 943 }
76d97dd4
ET		 944 } else if (comp_codes_10g &
945 (IXGBE_SFF_10GBASESR_CAPABLE |
946 IXGBE_SFF_10GBASELR_CAPABLE)) {
11afc1b1
PW		 947 if (hw->bus.lan_id == 0)
948 hw->phy.sfp_type =
949 ixgbe_sfp_type_srlr_core0;
950 else
951 hw->phy.sfp_type =
952 ixgbe_sfp_type_srlr_core1;
76d97dd4 953 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
cb836a97
DS		 954 if (hw->bus.lan_id == 0)
955 hw->phy.sfp_type =
956 ixgbe_sfp_type_1g_cu_core0;
957 else
958 hw->phy.sfp_type =
959 ixgbe_sfp_type_1g_cu_core1;
a49fda3e
JK		 960 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
961 if (hw->bus.lan_id == 0)
962 hw->phy.sfp_type =
963 ixgbe_sfp_type_1g_sx_core0;
964 else
965 hw->phy.sfp_type =
966 ixgbe_sfp_type_1g_sx_core1;
76d97dd4 967 } else {
11afc1b1 968 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
76d97dd4 969 }
11afc1b1 970 }
c4900be0 971
553b4497
PW		 972 if (hw->phy.sfp_type != stored_sfp_type)
973 hw->phy.sfp_setup_needed = true;
974
975 /* Determine if the SFP+ PHY is dual speed or not. */
50ac58ba 976 hw->phy.multispeed_fiber = false;
553b4497
PW		 977 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
978 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
979 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
980 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
981 hw->phy.multispeed_fiber = true;
982
c4900be0 983 /* Determine PHY vendor */
04193058 984 if (hw->phy.type != ixgbe_phy_nl) {
c4900be0 985 hw->phy.id = identifier;
76d97dd4 986 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 987 IXGBE_SFF_VENDOR_OUI_BYTE0,
988 &oui_bytes[0]);
76d97dd4
ET		 989
990 if (status == IXGBE_ERR_SWFW_SYNC ||
991 status == IXGBE_ERR_I2C ||
992 status == IXGBE_ERR_SFP_NOT_PRESENT)
993 goto err_read_i2c_eeprom;
994
995 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 996 IXGBE_SFF_VENDOR_OUI_BYTE1,
997 &oui_bytes[1]);
76d97dd4
ET		 998
999 if (status == IXGBE_ERR_SWFW_SYNC ||
1000 status == IXGBE_ERR_I2C ||
1001 status == IXGBE_ERR_SFP_NOT_PRESENT)
1002 goto err_read_i2c_eeprom;
1003
1004 status = hw->phy.ops.read_i2c_eeprom(hw,
c4900be0
DS		 1005 IXGBE_SFF_VENDOR_OUI_BYTE2,
1006 &oui_bytes[2]);
1007
76d97dd4
ET		 1008 if (status == IXGBE_ERR_SWFW_SYNC ||
1009 status == IXGBE_ERR_I2C ||
1010 status == IXGBE_ERR_SFP_NOT_PRESENT)
1011 goto err_read_i2c_eeprom;
1012
c4900be0
DS		 1013 vendor_oui =
1014 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1015 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1016 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1017
1018 switch (vendor_oui) {
1019 case IXGBE_SFF_VENDOR_OUI_TYCO:
537d58a0 1020 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1021 hw->phy.type =
76d97dd4 1022 ixgbe_phy_sfp_passive_tyco;
c4900be0
DS		 1023 break;
1024 case IXGBE_SFF_VENDOR_OUI_FTL:
ea0a04df
DS		 1025 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1026 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1027 else
1028 hw->phy.type = ixgbe_phy_sfp_ftl;
c4900be0
DS		 1029 break;
1030 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1031 hw->phy.type = ixgbe_phy_sfp_avago;
1032 break;
11afc1b1
PW		 1033 case IXGBE_SFF_VENDOR_OUI_INTEL:
1034 hw->phy.type = ixgbe_phy_sfp_intel;
1035 break;
c4900be0 1036 default:
537d58a0 1037 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
ea0a04df 1038 hw->phy.type =
76d97dd4 1039 ixgbe_phy_sfp_passive_unknown;
ea0a04df
DS		 1040 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1041 hw->phy.type =
1042 ixgbe_phy_sfp_active_unknown;
c4900be0
DS		 1043 else
1044 hw->phy.type = ixgbe_phy_sfp_unknown;
1045 break;
1046 }
1047 }
fa466e91 1048
76d97dd4 1049 /* Allow any DA cable vendor */
ea0a04df
DS		 1050 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1051 IXGBE_SFF_DA_ACTIVE_CABLE)) {
fa466e91
WJP		 1052 status = 0;
1053 goto out;
1054 }
1055
cb836a97
DS		 1056 /* Verify supported 1G SFP modules */
1057 if (comp_codes_10g == 0 &&
1058 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
a49fda3e
JK		 1059 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1060 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1061 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
fa466e91
WJP		 1062 hw->phy.type = ixgbe_phy_sfp_unsupported;
1063 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1064 goto out;
1065 }
1066
1067 /* Anything else 82598-based is supported */
1068 if (hw->mac.type == ixgbe_mac_82598EB) {
11afc1b1
PW		 1069 status = 0;
1070 goto out;
1071 }
1072
04193058 1073 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
cb836a97
DS		 1074 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1075 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
a49fda3e
JK		 1076 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1077 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) ||
1078 (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
11afc1b1
PW		 1079 /* Make sure we're a supported PHY type */
1080 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1081 status = 0;
1082 } else {
8ef78adc
PWJ		 1083 if (hw->allow_unsupported_sfp) {
1084 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.");
1085 status = 0;
1086 } else {
1087 hw_dbg(hw,
1088 "SFP+ module not supported\n");
1089 hw->phy.type =
1090 ixgbe_phy_sfp_unsupported;
1091 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1092 }
11afc1b1
PW		 1093 }
1094 } else {
1095 status = 0;
1096 }
c4900be0
DS		 1097 }
1098
1099out:
1100 return status;
76d97dd4
ET		 1101
1102err_read_i2c_eeprom:
1103 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1104 if (hw->phy.type != ixgbe_phy_nl) {
1105 hw->phy.id = 0;
1106 hw->phy.type = ixgbe_phy_unknown;
1107 }
1108 return IXGBE_ERR_SFP_NOT_PRESENT;
c4900be0
DS		 1109}
1110
1111/**
76d97dd4 1112 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
c4900be0
DS		 1113 * @hw: pointer to hardware structure
1114 * @list_offset: offset to the SFP ID list
1115 * @data_offset: offset to the SFP data block
75f19c3c
ET		 1116 *
1117 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1118 * so it returns the offsets to the phy init sequence block.
c4900be0
DS		 1119 **/
1120s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1121 u16 *list_offset,
1122 u16 *data_offset)
1123{
1124 u16 sfp_id;
cb836a97 1125 u16 sfp_type = hw->phy.sfp_type;
c4900be0
DS		 1126
1127 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1128 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1129
1130 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1131 return IXGBE_ERR_SFP_NOT_PRESENT;
1132
1133 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1134 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1135 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1136
cb836a97
DS		 1137 /*
1138 * Limiting active cables and 1G Phys must be initialized as
1139 * SR modules
1140 */
1141 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
a49fda3e
JK		 1142 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1143 sfp_type == ixgbe_sfp_type_1g_sx_core0)
cb836a97
DS		 1144 sfp_type = ixgbe_sfp_type_srlr_core0;
1145 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
a49fda3e
JK		 1146 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1147 sfp_type == ixgbe_sfp_type_1g_sx_core1)
cb836a97
DS		 1148 sfp_type = ixgbe_sfp_type_srlr_core1;
1149
c4900be0
DS		 1150 /* Read offset to PHY init contents */
1151 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1152
1153 if ((!*list_offset) || (*list_offset == 0xFFFF))
11afc1b1 1154 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
c4900be0
DS		 1155
1156 /* Shift offset to first ID word */
1157 (*list_offset)++;
1158
1159 /*
1160 * Find the matching SFP ID in the EEPROM
1161 * and program the init sequence
1162 */
1163 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1164
1165 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
cb836a97 1166 if (sfp_id == sfp_type) {
c4900be0
DS		 1167 (*list_offset)++;
1168 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1169 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1170 hw_dbg(hw, "SFP+ module not supported\n");
1171 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1172 } else {
1173 break;
1174 }
1175 } else {
1176 (*list_offset) += 2;
1177 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1178 return IXGBE_ERR_PHY;
1179 }
1180 }
1181
1182 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1183 hw_dbg(hw, "No matching SFP+ module found\n");
1184 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1185 }
1186
1187 return 0;
1188}
1189
11afc1b1
PW		 1190/**
1191 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1192 * @hw: pointer to hardware structure
1193 * @byte_offset: EEPROM byte offset to read
1194 * @eeprom_data: value read
1195 *
1196 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1197 **/
1198s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1199 u8 *eeprom_data)
1200{
1201 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1202 IXGBE_I2C_EEPROM_DEV_ADDR,
1203 eeprom_data);
1204}
1205
1206/**
1207 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1208 * @hw: pointer to hardware structure
1209 * @byte_offset: EEPROM byte offset to write
1210 * @eeprom_data: value to write
1211 *
1212 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1213 **/
1214s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1215 u8 eeprom_data)
1216{
1217 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1218 IXGBE_I2C_EEPROM_DEV_ADDR,
1219 eeprom_data);
1220}
1221
1222/**
1223 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1224 * @hw: pointer to hardware structure
1225 * @byte_offset: byte offset to read
1226 * @data: value read
1227 *
1228 * Performs byte read operation to SFP module's EEPROM over I2C interface at
3fbaa3ac 1229 * a specified device address.
11afc1b1
PW		 1230 **/
1231s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1232 u8 dev_addr, u8 *data)
1233{
1234 s32 status = 0;
75f19c3c 1235 u32 max_retry = 10;
11afc1b1 1236 u32 retry = 0;
75f19c3c 1237 u16 swfw_mask = 0;
3db1cd5c 1238 bool nack = true;
3fbaa3ac 1239 *data = 0;
11afc1b1 1240
75f19c3c
ET		 1241 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1242 swfw_mask = IXGBE_GSSR_PHY1_SM;
1243 else
1244 swfw_mask = IXGBE_GSSR_PHY0_SM;
1245
11afc1b1 1246 do {
6d980c3e 1247 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1248 status = IXGBE_ERR_SWFW_SYNC;
1249 goto read_byte_out;
1250 }
1251
11afc1b1
PW		 1252 ixgbe_i2c_start(hw);
1253
1254 /* Device Address and write indication */
1255 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1256 if (status != 0)
1257 goto fail;
1258
1259 status = ixgbe_get_i2c_ack(hw);
1260 if (status != 0)
1261 goto fail;
1262
1263 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1264 if (status != 0)
1265 goto fail;
1266
1267 status = ixgbe_get_i2c_ack(hw);
1268 if (status != 0)
1269 goto fail;
1270
1271 ixgbe_i2c_start(hw);
1272
1273 /* Device Address and read indication */
1274 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1275 if (status != 0)
1276 goto fail;
1277
1278 status = ixgbe_get_i2c_ack(hw);
1279 if (status != 0)
1280 goto fail;
1281
1282 status = ixgbe_clock_in_i2c_byte(hw, data);
1283 if (status != 0)
1284 goto fail;
1285
1286 status = ixgbe_clock_out_i2c_bit(hw, nack);
1287 if (status != 0)
1288 goto fail;
1289
1290 ixgbe_i2c_stop(hw);
1291 break;
1292
1293fail:
6d980c3e 1294 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c 1295 msleep(100);
11afc1b1
PW		 1296 ixgbe_i2c_bus_clear(hw);
1297 retry++;
1298 if (retry < max_retry)
1299 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1300 else
1301 hw_dbg(hw, "I2C byte read error.\n");
1302
1303 } while (retry < max_retry);
1304
6d980c3e 1305 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1306
1307read_byte_out:
11afc1b1
PW		 1308 return status;
1309}
1310
1311/**
1312 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1313 * @hw: pointer to hardware structure
1314 * @byte_offset: byte offset to write
1315 * @data: value to write
1316 *
1317 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1318 * a specified device address.
1319 **/
1320s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1321 u8 dev_addr, u8 data)
1322{
1323 s32 status = 0;
1324 u32 max_retry = 1;
1325 u32 retry = 0;
75f19c3c
ET		 1326 u16 swfw_mask = 0;
1327
1328 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1329 swfw_mask = IXGBE_GSSR_PHY1_SM;
1330 else
1331 swfw_mask = IXGBE_GSSR_PHY0_SM;
1332
6d980c3e 1333 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) {
75f19c3c
ET		 1334 status = IXGBE_ERR_SWFW_SYNC;
1335 goto write_byte_out;
1336 }
11afc1b1
PW		 1337
1338 do {
1339 ixgbe_i2c_start(hw);
1340
1341 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1342 if (status != 0)
1343 goto fail;
1344
1345 status = ixgbe_get_i2c_ack(hw);
1346 if (status != 0)
1347 goto fail;
1348
1349 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1350 if (status != 0)
1351 goto fail;
1352
1353 status = ixgbe_get_i2c_ack(hw);
1354 if (status != 0)
1355 goto fail;
1356
1357 status = ixgbe_clock_out_i2c_byte(hw, data);
1358 if (status != 0)
1359 goto fail;
1360
1361 status = ixgbe_get_i2c_ack(hw);
1362 if (status != 0)
1363 goto fail;
1364
1365 ixgbe_i2c_stop(hw);
1366 break;
1367
1368fail:
1369 ixgbe_i2c_bus_clear(hw);
1370 retry++;
1371 if (retry < max_retry)
1372 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1373 else
1374 hw_dbg(hw, "I2C byte write error.\n");
1375 } while (retry < max_retry);
1376
6d980c3e 1377 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
75f19c3c
ET		 1378
1379write_byte_out:
11afc1b1
PW		 1380 return status;
1381}
1382
1383/**
1384 * ixgbe_i2c_start - Sets I2C start condition
1385 * @hw: pointer to hardware structure
1386 *
1387 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1388 **/
1389static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1390{
1391 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1392
1393 /* Start condition must begin with data and clock high */
1394 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1395 ixgbe_raise_i2c_clk(hw, &i2cctl);
1396
1397 /* Setup time for start condition (4.7us) */
1398 udelay(IXGBE_I2C_T_SU_STA);
1399
1400 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1401
1402 /* Hold time for start condition (4us) */
1403 udelay(IXGBE_I2C_T_HD_STA);
1404
1405 ixgbe_lower_i2c_clk(hw, &i2cctl);
1406
1407 /* Minimum low period of clock is 4.7 us */
1408 udelay(IXGBE_I2C_T_LOW);
1409
1410}
1411
1412/**
1413 * ixgbe_i2c_stop - Sets I2C stop condition
1414 * @hw: pointer to hardware structure
1415 *
1416 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1417 **/
1418static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1419{
1420 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1421
1422 /* Stop condition must begin with data low and clock high */
1423 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1424 ixgbe_raise_i2c_clk(hw, &i2cctl);
1425
1426 /* Setup time for stop condition (4us) */
1427 udelay(IXGBE_I2C_T_SU_STO);
1428
1429 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1430
1431 /* bus free time between stop and start (4.7us)*/
1432 udelay(IXGBE_I2C_T_BUF);
1433}
1434
1435/**
1436 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1437 * @hw: pointer to hardware structure
1438 * @data: data byte to clock in
1439 *
1440 * Clocks in one byte data via I2C data/clock
1441 **/
1442static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1443{
11afc1b1 1444 s32 i;
3db1cd5c 1445 bool bit = false;
11afc1b1
PW		 1446
1447 for (i = 7; i >= 0; i--) {
e1befd77 1448 ixgbe_clock_in_i2c_bit(hw, &bit);
11afc1b1 1449 *data |= bit << i;
11afc1b1
PW		 1450 }
1451
e1befd77 1452 return 0;
11afc1b1
PW		 1453}
1454
1455/**
1456 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1457 * @hw: pointer to hardware structure
1458 * @data: data byte clocked out
1459 *
1460 * Clocks out one byte data via I2C data/clock
1461 **/
1462static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1463{
1464 s32 status = 0;
1465 s32 i;
1466 u32 i2cctl;
3db1cd5c 1467 bool bit = false;
11afc1b1
PW		 1468
1469 for (i = 7; i >= 0; i--) {
1470 bit = (data >> i) & 0x1;
1471 status = ixgbe_clock_out_i2c_bit(hw, bit);
1472
1473 if (status != 0)
1474 break;
1475 }
1476
1477 /* Release SDA line (set high) */
1478 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1479 i2cctl |= IXGBE_I2C_DATA_OUT;
1480 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
176f950d 1481 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1482
1483 return status;
1484}
1485
1486/**
1487 * ixgbe_get_i2c_ack - Polls for I2C ACK
1488 * @hw: pointer to hardware structure
1489 *
1490 * Clocks in/out one bit via I2C data/clock
1491 **/
1492static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1493{
e1befd77 1494 s32 status = 0;
11afc1b1
PW		 1495 u32 i = 0;
1496 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1497 u32 timeout = 10;
3db1cd5c 1498 bool ack = true;
11afc1b1 1499
e1befd77 1500 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1 1501
11afc1b1
PW		 1502
1503 /* Minimum high period of clock is 4us */
1504 udelay(IXGBE_I2C_T_HIGH);
1505
1506 /* Poll for ACK. Note that ACK in I2C spec is
1507 * transition from 1 to 0 */
1508 for (i = 0; i < timeout; i++) {
1509 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1510 ack = ixgbe_get_i2c_data(&i2cctl);
1511
1512 udelay(1);
1513 if (ack == 0)
1514 break;
1515 }
1516
1517 if (ack == 1) {
1518 hw_dbg(hw, "I2C ack was not received.\n");
1519 status = IXGBE_ERR_I2C;
1520 }
1521
1522 ixgbe_lower_i2c_clk(hw, &i2cctl);
1523
1524 /* Minimum low period of clock is 4.7 us */
1525 udelay(IXGBE_I2C_T_LOW);
1526
11afc1b1
PW		 1527 return status;
1528}
1529
1530/**
1531 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1532 * @hw: pointer to hardware structure
1533 * @data: read data value
1534 *
1535 * Clocks in one bit via I2C data/clock
1536 **/
1537static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1538{
11afc1b1
PW		 1539 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1540
e1befd77 1541 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1542
1543 /* Minimum high period of clock is 4us */
1544 udelay(IXGBE_I2C_T_HIGH);
1545
1546 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1547 *data = ixgbe_get_i2c_data(&i2cctl);
1548
1549 ixgbe_lower_i2c_clk(hw, &i2cctl);
1550
1551 /* Minimum low period of clock is 4.7 us */
1552 udelay(IXGBE_I2C_T_LOW);
1553
e1befd77 1554 return 0;
11afc1b1
PW		 1555}
1556
1557/**
1558 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1559 * @hw: pointer to hardware structure
1560 * @data: data value to write
1561 *
1562 * Clocks out one bit via I2C data/clock
1563 **/
1564static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1565{
1566 s32 status;
1567 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1568
1569 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1570 if (status == 0) {
e1befd77 1571 ixgbe_raise_i2c_clk(hw, &i2cctl);
11afc1b1
PW		 1572
1573 /* Minimum high period of clock is 4us */
1574 udelay(IXGBE_I2C_T_HIGH);
1575
1576 ixgbe_lower_i2c_clk(hw, &i2cctl);
1577
1578 /* Minimum low period of clock is 4.7 us.
1579 * This also takes care of the data hold time.
1580 */
1581 udelay(IXGBE_I2C_T_LOW);
1582 } else {
1583 status = IXGBE_ERR_I2C;
1584 hw_dbg(hw, "I2C data was not set to %X\n", data);
1585 }
1586
1587 return status;
1588}
1589/**
1590 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1591 * @hw: pointer to hardware structure
1592 * @i2cctl: Current value of I2CCTL register
1593 *
1594 * Raises the I2C clock line '0'->'1'
1595 **/
e1befd77 1596static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
11afc1b1 1597{
8f56e4b9
DS		 1598 u32 i = 0;
1599 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1600 u32 i2cctl_r = 0;
11afc1b1 1601
8f56e4b9
DS		 1602 for (i = 0; i < timeout; i++) {
1603 *i2cctl |= IXGBE_I2C_CLK_OUT;
1604 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1605 IXGBE_WRITE_FLUSH(hw);
1606 /* SCL rise time (1000ns) */
1607 udelay(IXGBE_I2C_T_RISE);
1608
1609 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1610 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1611 break;
1612 }
11afc1b1
PW		 1613}
1614
1615/**
1616 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1617 * @hw: pointer to hardware structure
1618 * @i2cctl: Current value of I2CCTL register
1619 *
1620 * Lowers the I2C clock line '1'->'0'
1621 **/
1622static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1623{
1624
1625 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1626
1627 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1628 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1629
1630 /* SCL fall time (300ns) */
1631 udelay(IXGBE_I2C_T_FALL);
1632}
1633
1634/**
1635 * ixgbe_set_i2c_data - Sets the I2C data bit
1636 * @hw: pointer to hardware structure
1637 * @i2cctl: Current value of I2CCTL register
1638 * @data: I2C data value (0 or 1) to set
1639 *
1640 * Sets the I2C data bit
1641 **/
1642static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1643{
1644 s32 status = 0;
1645
1646 if (data)
1647 *i2cctl |= IXGBE_I2C_DATA_OUT;
1648 else
1649 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1650
1651 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
945a5151 1652 IXGBE_WRITE_FLUSH(hw);
11afc1b1
PW		 1653
1654 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1655 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1656
1657 /* Verify data was set correctly */
1658 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1659 if (data != ixgbe_get_i2c_data(i2cctl)) {
1660 status = IXGBE_ERR_I2C;
1661 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1662 }
1663
1664 return status;
1665}
1666
1667/**
1668 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1669 * @hw: pointer to hardware structure
1670 * @i2cctl: Current value of I2CCTL register
1671 *
1672 * Returns the I2C data bit value
1673 **/
1674static bool ixgbe_get_i2c_data(u32 *i2cctl)
1675{
1676 bool data;
1677
1678 if (*i2cctl & IXGBE_I2C_DATA_IN)
3db1cd5c 1679 data = true;
11afc1b1 1680 else
3db1cd5c 1681 data = false;
11afc1b1
PW		 1682
1683 return data;
1684}
1685
1686/**
1687 * ixgbe_i2c_bus_clear - Clears the I2C bus
1688 * @hw: pointer to hardware structure
1689 *
1690 * Clears the I2C bus by sending nine clock pulses.
1691 * Used when data line is stuck low.
1692 **/
1693static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1694{
1695 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1696 u32 i;
1697
75f19c3c
ET		 1698 ixgbe_i2c_start(hw);
1699
11afc1b1
PW		 1700 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1701
1702 for (i = 0; i < 9; i++) {
1703 ixgbe_raise_i2c_clk(hw, &i2cctl);
1704
1705 /* Min high period of clock is 4us */
1706 udelay(IXGBE_I2C_T_HIGH);
1707
1708 ixgbe_lower_i2c_clk(hw, &i2cctl);
1709
1710 /* Min low period of clock is 4.7us*/
1711 udelay(IXGBE_I2C_T_LOW);
1712 }
1713
75f19c3c
ET		 1714 ixgbe_i2c_start(hw);
1715
11afc1b1
PW		 1716 /* Put the i2c bus back to default state */
1717 ixgbe_i2c_stop(hw);
1718}
1719
119fc60a 1720/**
25985edc 1721 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
119fc60a
MC		 1722 * @hw: pointer to hardware structure
1723 *
1724 * Checks if the LASI temp alarm status was triggered due to overtemp
1725 **/
1726s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1727{
1728 s32 status = 0;
1729 u16 phy_data = 0;
1730
1731 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1732 goto out;
1733
1734 /* Check that the LASI temp alarm status was triggered */
1735 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1736 MDIO_MMD_PMAPMD, &phy_data);
1737
1738 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1739 goto out;
1740
1741 status = IXGBE_ERR_OVERTEMP;
1742out:
1743 return status;
1744}
Linux kernel - Deliverables
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