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ixgbe: Add function for obtaining FCoE TC based on FCoE user priority
[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_x540.c
CommitLineData
fe15e8e1
DS		 1/*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
94971820 4 Copyright(c) 1999 - 2012 Intel Corporation.
fe15e8e1
DS		 5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include <linux/pci.h>
29#include <linux/delay.h>
30#include <linux/sched.h>
31
32#include "ixgbe.h"
33#include "ixgbe_phy.h"
fe15e8e1
DS		 34
35#define IXGBE_X540_MAX_TX_QUEUES 128
36#define IXGBE_X540_MAX_RX_QUEUES 128
37#define IXGBE_X540_RAR_ENTRIES 128
38#define IXGBE_X540_MC_TBL_SIZE 128
39#define IXGBE_X540_VFT_TBL_SIZE 128
e09ad236 40#define IXGBE_X540_RX_PB_SIZE 384
fe15e8e1
DS		 41
42static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
43static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
44static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
45static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
46static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
b93a2226 49static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 50{
51 return ixgbe_media_type_copper;
52}
53
54static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55{
56 struct ixgbe_mac_info *mac = &hw->mac;
57
58 /* Call PHY identify routine to get the phy type */
59 ixgbe_identify_phy_generic(hw);
60
61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
64 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
65 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
66 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
67
68 return 0;
69}
70
71/**
72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
73 * @hw: pointer to hardware structure
74 * @speed: new link speed
75 * @autoneg: true if autonegotiation enabled
76 * @autoneg_wait_to_complete: true when waiting for completion is needed
77 **/
b93a2226
DS		 78static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
79 ixgbe_link_speed speed, bool autoneg,
80 bool autoneg_wait_to_complete)
fe15e8e1
DS		 81{
82 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
83 autoneg_wait_to_complete);
84}
85
86/**
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
89 *
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
92 * reset.
93 **/
b93a2226 94static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
fe15e8e1 95{
8132b54e
AD		 96 s32 status;
97 u32 ctrl, i;
fe15e8e1
DS		 98
99 /* Call adapter stop to disable tx/rx and clear interrupts */
ff9d1a5a
ET		 100 status = hw->mac.ops.stop_adapter(hw);
101 if (status != 0)
102 goto reset_hw_out;
fe15e8e1 103
ff9d1a5a
ET		 104 /* flush pending Tx transactions */
105 ixgbe_clear_tx_pending(hw);
fe15e8e1 106
a4297dc2 107mac_reset_top:
8c838d73 108 ctrl = IXGBE_CTRL_RST;
8132b54e
AD		 109 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
110 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
fe15e8e1
DS		 111 IXGBE_WRITE_FLUSH(hw);
112
113 /* Poll for reset bit to self-clear indicating reset is complete */
114 for (i = 0; i < 10; i++) {
115 udelay(1);
116 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
8132b54e 117 if (!(ctrl & IXGBE_CTRL_RST_MASK))
fe15e8e1
DS		 118 break;
119 }
8132b54e
AD		 120
121 if (ctrl & IXGBE_CTRL_RST_MASK) {
fe15e8e1
DS		 122 status = IXGBE_ERR_RESET_FAILED;
123 hw_dbg(hw, "Reset polling failed to complete.\n");
124 }
8c838d73 125 msleep(100);
8132b54e 126
a4297dc2
ET		 127 /*
128 * Double resets are required for recovery from certain error
129 * conditions. Between resets, it is necessary to stall to allow time
8132b54e 130 * for any pending HW events to complete.
a4297dc2
ET		 131 */
132 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
133 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
a4297dc2
ET		 134 goto mac_reset_top;
135 }
136
fe15e8e1
DS		 137 /* Set the Rx packet buffer size. */
138 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
139
140 /* Store the permanent mac address */
141 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
142
fe15e8e1
DS		 143 /*
144 * Store MAC address from RAR0, clear receive address registers, and
145 * clear the multicast table. Also reset num_rar_entries to 128,
146 * since we modify this value when programming the SAN MAC address.
147 */
93cb38dc 148 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
fe15e8e1
DS		 149 hw->mac.ops.init_rx_addrs(hw);
150
fe15e8e1
DS		 151 /* Store the permanent SAN mac address */
152 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
153
154 /* Add the SAN MAC address to the RAR only if it's a valid address */
155 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
156 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
157 hw->mac.san_addr, 0, IXGBE_RAH_AV);
158
159 /* Reserve the last RAR for the SAN MAC address */
160 hw->mac.num_rar_entries--;
161 }
162
163 /* Store the alternative WWNN/WWPN prefix */
164 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
165 &hw->mac.wwpn_prefix);
166
ff9d1a5a 167reset_hw_out:
fe15e8e1
DS		 168 return status;
169}
170
7184b7cf
ET		 171/**
172 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
173 * @hw: pointer to hardware structure
174 *
175 * Starts the hardware using the generic start_hw function
176 * and the generation start_hw function.
177 * Then performs revision-specific operations, if any.
178 **/
179static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
180{
181 s32 ret_val = 0;
182
183 ret_val = ixgbe_start_hw_generic(hw);
184 if (ret_val != 0)
185 goto out;
186
187 ret_val = ixgbe_start_hw_gen2(hw);
e09ad236 188 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
7184b7cf
ET		 189out:
190 return ret_val;
191}
192
fe15e8e1
DS		 193/**
194 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
195 * @hw: pointer to hardware structure
196 *
197 * Determines physical layer capabilities of the current configuration.
198 **/
b93a2226 199static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 200{
201 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
202 u16 ext_ability = 0;
203
204 hw->phy.ops.identify(hw);
205
206 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
207 &ext_ability);
208 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
209 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
210 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
211 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
212 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
213 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
214
215 return physical_layer;
216}
217
218/**
77ed18f3
ET		 219 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
220 * @hw: pointer to hardware structure
221 *
222 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
223 * ixgbe_hw struct in order to set up EEPROM access.
fe15e8e1 224 **/
b93a2226 225static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 226{
227 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
228 u32 eec;
229 u16 eeprom_size;
230
231 if (eeprom->type == ixgbe_eeprom_uninitialized) {
232 eeprom->semaphore_delay = 10;
233 eeprom->type = ixgbe_flash;
234
235 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
236 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
237 IXGBE_EEC_SIZE_SHIFT);
238 eeprom->word_size = 1 << (eeprom_size +
239 IXGBE_EEPROM_WORD_SIZE_SHIFT);
240
241 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
77ed18f3 242 eeprom->type, eeprom->word_size);
fe15e8e1
DS		 243 }
244
245 return 0;
246}
247
248/**
68c7005d
ET		 249 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
250 * @hw: pointer to hardware structure
251 * @offset: offset of word in the EEPROM to read
252 * @data: word read from the EEPROM
253 *
254 * Reads a 16 bit word from the EEPROM using the EERD register.
fe15e8e1 255 **/
b93a2226 256static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
fe15e8e1 257{
68c7005d 258 s32 status = 0;
fe15e8e1 259
68c7005d
ET		 260 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
261 0)
fe15e8e1
DS		 262 status = ixgbe_read_eerd_generic(hw, offset, data);
263 else
264 status = IXGBE_ERR_SWFW_SYNC;
265
6d980c3e 266 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
fe15e8e1
DS		 267 return status;
268}
269
68c7005d
ET		 270/**
271 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
272 * @hw: pointer to hardware structure
273 * @offset: offset of word in the EEPROM to read
274 * @words: number of words
275 * @data: word(s) read from the EEPROM
276 *
277 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
278 **/
279static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
280 u16 offset, u16 words, u16 *data)
281{
282 s32 status = 0;
283
284 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
285 0)
286 status = ixgbe_read_eerd_buffer_generic(hw, offset,
287 words, data);
288 else
289 status = IXGBE_ERR_SWFW_SYNC;
290
291 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
292 return status;
293}
294
fe15e8e1 295/**
eb9c3e3e
ET		 296 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
297 * @hw: pointer to hardware structure
298 * @offset: offset of word in the EEPROM to write
299 * @data: word write to the EEPROM
fe15e8e1 300 *
eb9c3e3e 301 * Write a 16 bit word to the EEPROM using the EEWR register.
fe15e8e1 302 **/
b93a2226 303static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
fe15e8e1 304{
eb9c3e3e 305 s32 status = 0;
fe15e8e1 306
eb9c3e3e
ET		 307 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
308 status = ixgbe_write_eewr_generic(hw, offset, data);
309 else
fe15e8e1 310 status = IXGBE_ERR_SWFW_SYNC;
fe15e8e1 311
eb9c3e3e 312 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
fe15e8e1
DS		 313 return status;
314}
315
68c7005d
ET		 316/**
317 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
318 * @hw: pointer to hardware structure
319 * @offset: offset of word in the EEPROM to write
320 * @words: number of words
321 * @data: word(s) write to the EEPROM
322 *
323 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
324 **/
325static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
326 u16 offset, u16 words, u16 *data)
327{
328 s32 status = 0;
329
330 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
331 0)
332 status = ixgbe_write_eewr_buffer_generic(hw, offset,
333 words, data);
334 else
335 status = IXGBE_ERR_SWFW_SYNC;
336
337 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
338 return status;
339}
340
fe15e8e1 341/**
eb9c3e3e
ET		 342 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
343 *
344 * This function does not use synchronization for EERD and EEWR. It can
345 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
346 *
347 * @hw: pointer to hardware structure
fe15e8e1
DS		 348 **/
349static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
350{
351 u16 i;
352 u16 j;
353 u16 checksum = 0;
354 u16 length = 0;
355 u16 pointer = 0;
356 u16 word = 0;
357
eb9c3e3e
ET		 358 /*
359 * Do not use hw->eeprom.ops.read because we do not want to take
360 * the synchronization semaphores here. Instead use
361 * ixgbe_read_eerd_generic
362 */
363
fe15e8e1
DS		 364 /* Include 0x0-0x3F in the checksum */
365 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
eb9c3e3e 366 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
fe15e8e1
DS		 367 hw_dbg(hw, "EEPROM read failed\n");
368 break;
369 }
370 checksum += word;
371 }
372
373 /*
374 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
375 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
376 */
377 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
378 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
379 continue;
380
eb9c3e3e 381 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
fe15e8e1
DS		 382 hw_dbg(hw, "EEPROM read failed\n");
383 break;
384 }
385
386 /* Skip pointer section if the pointer is invalid. */
387 if (pointer == 0xFFFF || pointer == 0 ||
388 pointer >= hw->eeprom.word_size)
389 continue;
390
eb9c3e3e 391 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
fe15e8e1
DS		 392 hw_dbg(hw, "EEPROM read failed\n");
393 break;
394 }
395
396 /* Skip pointer section if length is invalid. */
397 if (length == 0xFFFF || length == 0 ||
398 (pointer + length) >= hw->eeprom.word_size)
399 continue;
400
401 for (j = pointer+1; j <= pointer+length; j++) {
eb9c3e3e 402 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
fe15e8e1
DS		 403 hw_dbg(hw, "EEPROM read failed\n");
404 break;
405 }
406 checksum += word;
407 }
408 }
409
410 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
411
412 return checksum;
413}
414
eb9c3e3e
ET		 415/**
416 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
417 * @hw: pointer to hardware structure
418 * @checksum_val: calculated checksum
419 *
420 * Performs checksum calculation and validates the EEPROM checksum. If the
421 * caller does not need checksum_val, the value can be NULL.
422 **/
423static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
424 u16 *checksum_val)
425{
426 s32 status;
427 u16 checksum;
428 u16 read_checksum = 0;
429
430 /*
431 * Read the first word from the EEPROM. If this times out or fails, do
432 * not continue or we could be in for a very long wait while every
433 * EEPROM read fails
434 */
435 status = hw->eeprom.ops.read(hw, 0, &checksum);
436
437 if (status != 0) {
438 hw_dbg(hw, "EEPROM read failed\n");
439 goto out;
440 }
441
442 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
443 checksum = hw->eeprom.ops.calc_checksum(hw);
444
445 /*
446 * Do not use hw->eeprom.ops.read because we do not want to take
447 * the synchronization semaphores twice here.
448 */
449 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
450 &read_checksum);
451
452 /*
453 * Verify read checksum from EEPROM is the same as
454 * calculated checksum
455 */
456 if (read_checksum != checksum)
457 status = IXGBE_ERR_EEPROM_CHECKSUM;
458
459 /* If the user cares, return the calculated checksum */
460 if (checksum_val)
461 *checksum_val = checksum;
462 } else {
463 status = IXGBE_ERR_SWFW_SYNC;
464 }
465
466 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
467out:
468 return status;
469}
470
fe15e8e1
DS		 471/**
472 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
473 * @hw: pointer to hardware structure
474 *
475 * After writing EEPROM to shadow RAM using EEWR register, software calculates
476 * checksum and updates the EEPROM and instructs the hardware to update
477 * the flash.
478 **/
b93a2226 479static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
fe15e8e1
DS		 480{
481 s32 status;
eb9c3e3e 482 u16 checksum;
fe15e8e1 483
eb9c3e3e
ET		 484 /*
485 * Read the first word from the EEPROM. If this times out or fails, do
486 * not continue or we could be in for a very long wait while every
487 * EEPROM read fails
488 */
489 status = hw->eeprom.ops.read(hw, 0, &checksum);
490
491 if (status != 0)
492 hw_dbg(hw, "EEPROM read failed\n");
493
494 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
495 checksum = hw->eeprom.ops.calc_checksum(hw);
fe15e8e1 496
eb9c3e3e
ET		 497 /*
498 * Do not use hw->eeprom.ops.write because we do not want to
499 * take the synchronization semaphores twice here.
500 */
501 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
502 checksum);
503
504 if (status == 0)
fe15e8e1 505 status = ixgbe_update_flash_X540(hw);
eb9c3e3e
ET		 506 else
507 status = IXGBE_ERR_SWFW_SYNC;
508 }
509
510 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
fe15e8e1
DS		 511
512 return status;
513}
514
515/**
516 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
517 * @hw: pointer to hardware structure
518 *
519 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
520 * EEPROM from shadow RAM to the flash device.
521 **/
522static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
523{
524 u32 flup;
525 s32 status = IXGBE_ERR_EEPROM;
526
527 status = ixgbe_poll_flash_update_done_X540(hw);
528 if (status == IXGBE_ERR_EEPROM) {
529 hw_dbg(hw, "Flash update time out\n");
530 goto out;
531 }
532
533 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
534 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
535
536 status = ixgbe_poll_flash_update_done_X540(hw);
2ea5ea5f 537 if (status == 0)
fe15e8e1
DS		 538 hw_dbg(hw, "Flash update complete\n");
539 else
540 hw_dbg(hw, "Flash update time out\n");
541
542 if (hw->revision_id == 0) {
543 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
544
545 if (flup & IXGBE_EEC_SEC1VAL) {
546 flup |= IXGBE_EEC_FLUP;
547 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
548 }
549
550 status = ixgbe_poll_flash_update_done_X540(hw);
2ea5ea5f 551 if (status == 0)
fe15e8e1
DS		 552 hw_dbg(hw, "Flash update complete\n");
553 else
554 hw_dbg(hw, "Flash update time out\n");
fe15e8e1
DS		 555 }
556out:
557 return status;
558}
559
560/**
561 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
562 * @hw: pointer to hardware structure
563 *
564 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
565 * flash update is done.
566 **/
567static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
568{
569 u32 i;
570 u32 reg;
571 s32 status = IXGBE_ERR_EEPROM;
572
573 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
574 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
575 if (reg & IXGBE_EEC_FLUDONE) {
576 status = 0;
577 break;
578 }
579 udelay(5);
580 }
581 return status;
582}
583
584/**
585 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
586 * @hw: pointer to hardware structure
587 * @mask: Mask to specify which semaphore to acquire
588 *
589 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
590 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
591 **/
592static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
593{
594 u32 swfw_sync;
595 u32 swmask = mask;
596 u32 fwmask = mask << 5;
597 u32 hwmask = 0;
598 u32 timeout = 200;
599 u32 i;
600
601 if (swmask == IXGBE_GSSR_EEP_SM)
602 hwmask = IXGBE_GSSR_FLASH_SM;
603
604 for (i = 0; i < timeout; i++) {
605 /*
606 * SW NVM semaphore bit is used for access to all
607 * SW_FW_SYNC bits (not just NVM)
608 */
609 if (ixgbe_get_swfw_sync_semaphore(hw))
610 return IXGBE_ERR_SWFW_SYNC;
611
612 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
613 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
614 swfw_sync |= swmask;
615 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
616 ixgbe_release_swfw_sync_semaphore(hw);
617 break;
618 } else {
619 /*
620 * Firmware currently using resource (fwmask),
621 * hardware currently using resource (hwmask),
622 * or other software thread currently using
623 * resource (swmask)
624 */
625 ixgbe_release_swfw_sync_semaphore(hw);
032b4325 626 usleep_range(5000, 10000);
fe15e8e1
DS		 627 }
628 }
629
630 /*
631 * If the resource is not released by the FW/HW the SW can assume that
632 * the FW/HW malfunctions. In that case the SW should sets the
633 * SW bit(s) of the requested resource(s) while ignoring the
634 * corresponding FW/HW bits in the SW_FW_SYNC register.
635 */
636 if (i >= timeout) {
637 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
638 if (swfw_sync & (fwmask | hwmask)) {
639 if (ixgbe_get_swfw_sync_semaphore(hw))
640 return IXGBE_ERR_SWFW_SYNC;
641
642 swfw_sync |= swmask;
643 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
644 ixgbe_release_swfw_sync_semaphore(hw);
645 }
646 }
647
032b4325 648 usleep_range(5000, 10000);
fe15e8e1
DS		 649 return 0;
650}
651
652/**
653 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
654 * @hw: pointer to hardware structure
655 * @mask: Mask to specify which semaphore to release
656 *
25985edc 657 * Releases the SWFW semaphore through the SW_FW_SYNC register
fe15e8e1
DS		 658 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
659 **/
660static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
661{
662 u32 swfw_sync;
663 u32 swmask = mask;
664
665 ixgbe_get_swfw_sync_semaphore(hw);
666
667 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
668 swfw_sync &= ~swmask;
669 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
670
671 ixgbe_release_swfw_sync_semaphore(hw);
032b4325 672 usleep_range(5000, 10000);
fe15e8e1
DS		 673}
674
675/**
676 * ixgbe_get_nvm_semaphore - Get hardware semaphore
677 * @hw: pointer to hardware structure
678 *
679 * Sets the hardware semaphores so SW/FW can gain control of shared resources
680 **/
681static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
682{
683 s32 status = IXGBE_ERR_EEPROM;
684 u32 timeout = 2000;
685 u32 i;
686 u32 swsm;
687
688 /* Get SMBI software semaphore between device drivers first */
689 for (i = 0; i < timeout; i++) {
690 /*
691 * If the SMBI bit is 0 when we read it, then the bit will be
692 * set and we have the semaphore
693 */
694 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
695 if (!(swsm & IXGBE_SWSM_SMBI)) {
696 status = 0;
697 break;
698 }
699 udelay(50);
700 }
701
702 /* Now get the semaphore between SW/FW through the REGSMP bit */
703 if (status) {
704 for (i = 0; i < timeout; i++) {
705 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
706 if (!(swsm & IXGBE_SWFW_REGSMP))
707 break;
708
709 udelay(50);
710 }
711 } else {
712 hw_dbg(hw, "Software semaphore SMBI between device drivers "
713 "not granted.\n");
714 }
715
716 return status;
717}
718
719/**
720 * ixgbe_release_nvm_semaphore - Release hardware semaphore
721 * @hw: pointer to hardware structure
722 *
723 * This function clears hardware semaphore bits.
724 **/
725static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
726{
727 u32 swsm;
728
729 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
730
731 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
732 swsm &= ~IXGBE_SWSM_SMBI;
733 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
734
735 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
736 swsm &= ~IXGBE_SWFW_REGSMP;
737 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
738
739 IXGBE_WRITE_FLUSH(hw);
740}
741
98508c93
ET		 742/**
743 * ixgbe_blink_led_start_X540 - Blink LED based on index.
744 * @hw: pointer to hardware structure
745 * @index: led number to blink
746 *
747 * Devices that implement the version 2 interface:
748 * X540
749 **/
750static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
751{
752 u32 macc_reg;
753 u32 ledctl_reg;
8d233633
ET		 754 ixgbe_link_speed speed;
755 bool link_up;
98508c93
ET		 756
757 /*
8d233633
ET		 758 * Link should be up in order for the blink bit in the LED control
759 * register to work. Force link and speed in the MAC if link is down.
760 * This will be reversed when we stop the blinking.
98508c93 761 */
8d233633 762 hw->mac.ops.check_link(hw, &speed, &link_up, false);
23677ce3 763 if (!link_up) {
8d233633
ET		 764 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
765 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
766 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
767 }
98508c93
ET		 768 /* Set the LED to LINK_UP + BLINK. */
769 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
770 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
771 ledctl_reg |= IXGBE_LED_BLINK(index);
772 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
773 IXGBE_WRITE_FLUSH(hw);
774
775 return 0;
776}
777
778/**
779 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
780 * @hw: pointer to hardware structure
781 * @index: led number to stop blinking
782 *
783 * Devices that implement the version 2 interface:
784 * X540
785 **/
786static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
787{
788 u32 macc_reg;
789 u32 ledctl_reg;
790
791 /* Restore the LED to its default value. */
792 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
793 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
794 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
795 ledctl_reg &= ~IXGBE_LED_BLINK(index);
796 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
797
798 /* Unforce link and speed in the MAC. */
799 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
800 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
801 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
802 IXGBE_WRITE_FLUSH(hw);
803
804 return 0;
805}
fe15e8e1
DS		 806static struct ixgbe_mac_operations mac_ops_X540 = {
807 .init_hw = &ixgbe_init_hw_generic,
808 .reset_hw = &ixgbe_reset_hw_X540,
7184b7cf 809 .start_hw = &ixgbe_start_hw_X540,
fe15e8e1
DS		 810 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
811 .get_media_type = &ixgbe_get_media_type_X540,
812 .get_supported_physical_layer =
813 &ixgbe_get_supported_physical_layer_X540,
814 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
815 .get_mac_addr = &ixgbe_get_mac_addr_generic,
816 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
b776d104 817 .get_device_caps = &ixgbe_get_device_caps_generic,
fe15e8e1
DS		 818 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
819 .stop_adapter = &ixgbe_stop_adapter_generic,
820 .get_bus_info = &ixgbe_get_bus_info_generic,
821 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
822 .read_analog_reg8 = NULL,
823 .write_analog_reg8 = NULL,
824 .setup_link = &ixgbe_setup_mac_link_X540,
80605c65 825 .set_rxpba = &ixgbe_set_rxpba_generic,
fe15e8e1
DS		 826 .check_link = &ixgbe_check_mac_link_generic,
827 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
828 .led_on = &ixgbe_led_on_generic,
829 .led_off = &ixgbe_led_off_generic,
98508c93
ET		 830 .blink_led_start = &ixgbe_blink_led_start_X540,
831 .blink_led_stop = &ixgbe_blink_led_stop_X540,
fe15e8e1
DS		 832 .set_rar = &ixgbe_set_rar_generic,
833 .clear_rar = &ixgbe_clear_rar_generic,
834 .set_vmdq = &ixgbe_set_vmdq_generic,
835 .clear_vmdq = &ixgbe_clear_vmdq_generic,
836 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
fe15e8e1
DS		 837 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
838 .enable_mc = &ixgbe_enable_mc_generic,
839 .disable_mc = &ixgbe_disable_mc_generic,
840 .clear_vfta = &ixgbe_clear_vfta_generic,
841 .set_vfta = &ixgbe_set_vfta_generic,
842 .fc_enable = &ixgbe_fc_enable_generic,
9612de92 843 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
fe15e8e1
DS		 844 .init_uta_tables = &ixgbe_init_uta_tables_generic,
845 .setup_sfp = NULL,
3377eba7
GR		 846 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
847 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
5e655105
DS		 848 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
849 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
d2f5e7f3
AS		 850 .disable_rx_buff = &ixgbe_disable_rx_buff_generic,
851 .enable_rx_buff = &ixgbe_enable_rx_buff_generic,
3ca8bc6d
DS		 852 .get_thermal_sensor_data = NULL,
853 .init_thermal_sensor_thresh = NULL,
fe15e8e1
DS		 854};
855
856static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
857 .init_params = &ixgbe_init_eeprom_params_X540,
858 .read = &ixgbe_read_eerd_X540,
68c7005d 859 .read_buffer = &ixgbe_read_eerd_buffer_X540,
fe15e8e1 860 .write = &ixgbe_write_eewr_X540,
68c7005d 861 .write_buffer = &ixgbe_write_eewr_buffer_X540,
fe15e8e1 862 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
eb9c3e3e 863 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
fe15e8e1
DS		 864 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
865};
866
867static struct ixgbe_phy_operations phy_ops_X540 = {
868 .identify = &ixgbe_identify_phy_generic,
869 .identify_sfp = &ixgbe_identify_sfp_module_generic,
870 .init = NULL,
b60c5dd3 871 .reset = NULL,
fe15e8e1
DS		 872 .read_reg = &ixgbe_read_phy_reg_generic,
873 .write_reg = &ixgbe_write_phy_reg_generic,
874 .setup_link = &ixgbe_setup_phy_link_generic,
875 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
876 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
877 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
878 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
879 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
880 .check_overtemp = &ixgbe_tn_check_overtemp,
3e7307fc 881 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
fe15e8e1
DS		 882};
883
884struct ixgbe_info ixgbe_X540_info = {
885 .mac = ixgbe_mac_X540,
886 .get_invariants = &ixgbe_get_invariants_X540,
887 .mac_ops = &mac_ops_X540,
888 .eeprom_ops = &eeprom_ops_X540,
889 .phy_ops = &phy_ops_X540,
890 .mbx_ops = &mbx_ops_generic,
891};
Linux kernel - Deliverables
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