[deliverable/linux.git] / drivers / net / ethernet / intel / ixgbevf / ixgbevf.h

/*******************************************************************************

  Intel 82599 Virtual Function driver
  Copyright(c) 1999 - 2014 Intel Corporation.

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#ifndef _IXGBEVF_H_
#define _IXGBEVF_H_

#include <linux/types.h>
#include <linux/bitops.h>
#include <linux/timer.h>
#include <linux/io.h>
#include <linux/netdevice.h>
#include <linux/if_vlan.h>
#include <linux/u64_stats_sync.h>

#include "vf.h"

#ifdef CONFIG_NET_RX_BUSY_POLL
#include <net/busy_poll.h>
#define BP_EXTENDED_STATS
#endif

/* wrapper around a pointer to a socket buffer,
 * so a DMA handle can be stored along with the buffer */
struct ixgbevf_tx_buffer {
	union ixgbe_adv_tx_desc *next_to_watch;
	unsigned long time_stamp;
	struct sk_buff *skb;
	unsigned int bytecount;
	unsigned short gso_segs;
	__be16 protocol;
	DEFINE_DMA_UNMAP_ADDR(dma);
	DEFINE_DMA_UNMAP_LEN(len);
	u32 tx_flags;
};

struct ixgbevf_rx_buffer {
	dma_addr_t dma;
	struct page *page;
	unsigned int page_offset;
};

struct ixgbevf_stats {
	u64 packets;
	u64 bytes;
#ifdef BP_EXTENDED_STATS
	u64 yields;
	u64 misses;
	u64 cleaned;
#endif
};

struct ixgbevf_tx_queue_stats {
	u64 restart_queue;
	u64 tx_busy;
	u64 tx_done_old;
};

struct ixgbevf_rx_queue_stats {
	u64 alloc_rx_page_failed;
	u64 alloc_rx_buff_failed;
	u64 csum_err;
};

struct ixgbevf_ring {
	struct ixgbevf_ring *next;
	struct net_device *netdev;
	struct device *dev;
	void *desc;			/* descriptor ring memory */
	dma_addr_t dma;			/* phys. address of descriptor ring */
	unsigned int size;		/* length in bytes */
	u16 count;			/* amount of descriptors */
	u16 next_to_use;
	u16 next_to_clean;
	u16 next_to_alloc;

	union {
		struct ixgbevf_tx_buffer *tx_buffer_info;
		struct ixgbevf_rx_buffer *rx_buffer_info;
	};

	struct ixgbevf_stats stats;
	struct u64_stats_sync syncp;
	union {
		struct ixgbevf_tx_queue_stats tx_stats;
		struct ixgbevf_rx_queue_stats rx_stats;
	};

	u64 hw_csum_rx_error;
	u8 __iomem *tail;
	struct sk_buff *skb;

	u16 reg_idx; /* holds the special value that gets the hardware register
		      * offset associated with this ring, which is different
		      * for DCB and RSS modes */
	int queue_index; /* needed for multiqueue queue management */
};

/* How many Rx Buffers do we bundle into one write to the hardware ? */
#define IXGBEVF_RX_BUFFER_WRITE	16	/* Must be power of 2 */

#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES

#define IXGBEVF_DEFAULT_TXD   1024
#define IXGBEVF_DEFAULT_RXD   512
#define IXGBEVF_MAX_TXD       4096
#define IXGBEVF_MIN_TXD       64
#define IXGBEVF_MAX_RXD       4096
#define IXGBEVF_MIN_RXD       64

/* Supported Rx Buffer Sizes */
#define IXGBEVF_RXBUFFER_256   256    /* Used for packet split */
#define IXGBEVF_RXBUFFER_2048  2048

#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
#define IXGBEVF_RX_BUFSZ    IXGBEVF_RXBUFFER_2048

#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)

#define IXGBE_TX_FLAGS_CSUM		(u32)(1)
#define IXGBE_TX_FLAGS_VLAN		(u32)(1 << 1)
#define IXGBE_TX_FLAGS_TSO		(u32)(1 << 2)
#define IXGBE_TX_FLAGS_IPV4		(u32)(1 << 3)
#define IXGBE_TX_FLAGS_VLAN_MASK	0xffff0000
#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK	0x0000e000
#define IXGBE_TX_FLAGS_VLAN_SHIFT	16

struct ixgbevf_ring_container {
	struct ixgbevf_ring *ring;	/* pointer to linked list of rings */
	unsigned int total_bytes;	/* total bytes processed this int */
	unsigned int total_packets;	/* total packets processed this int */
	u8 count;			/* total number of rings in vector */
	u8 itr;				/* current ITR setting for ring */
};

/* iterator for handling rings in ring container */
#define ixgbevf_for_each_ring(pos, head) \
	for (pos = (head).ring; pos != NULL; pos = pos->next)

/* MAX_MSIX_Q_VECTORS of these are allocated,
 * but we only use one per queue-specific vector.
 */
struct ixgbevf_q_vector {
	struct ixgbevf_adapter *adapter;
	u16 v_idx;		/* index of q_vector within array, also used for
				 * finding the bit in EICR and friends that
				 * represents the vector for this ring */
	u16 itr;		/* Interrupt throttle rate written to EITR */
	struct napi_struct napi;
	struct ixgbevf_ring_container rx, tx;
	char name[IFNAMSIZ + 9];
#ifdef CONFIG_NET_RX_BUSY_POLL
	unsigned int state;
#define IXGBEVF_QV_STATE_IDLE		0
#define IXGBEVF_QV_STATE_NAPI		1    /* NAPI owns this QV */
#define IXGBEVF_QV_STATE_POLL		2    /* poll owns this QV */
#define IXGBEVF_QV_STATE_DISABLED	4    /* QV is disabled */
#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI | IXGBEVF_QV_STATE_POLL)
#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED | IXGBEVF_QV_STATE_DISABLED)
#define IXGBEVF_QV_STATE_NAPI_YIELD	8    /* NAPI yielded this QV */
#define IXGBEVF_QV_STATE_POLL_YIELD	16   /* poll yielded this QV */
#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD | IXGBEVF_QV_STATE_POLL_YIELD)
#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL | IXGBEVF_QV_STATE_POLL_YIELD)
	spinlock_t lock;
#endif /* CONFIG_NET_RX_BUSY_POLL */
};
#ifdef CONFIG_NET_RX_BUSY_POLL
static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
{

	spin_lock_init(&q_vector->lock);
	q_vector->state = IXGBEVF_QV_STATE_IDLE;
}

/* called from the device poll routine to get ownership of a q_vector */
static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
{
	int rc = true;
	spin_lock_bh(&q_vector->lock);
	if (q_vector->state & IXGBEVF_QV_LOCKED) {
		WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
		q_vector->state |= IXGBEVF_QV_STATE_NAPI_YIELD;
		rc = false;
#ifdef BP_EXTENDED_STATS
		q_vector->tx.ring->stats.yields++;
#endif
	} else {
		/* we don't care if someone yielded */
		q_vector->state = IXGBEVF_QV_STATE_NAPI;
	}
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* returns true is someone tried to get the qv while napi had it */
static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
{
	int rc = false;
	spin_lock_bh(&q_vector->lock);
	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL |
				   IXGBEVF_QV_STATE_NAPI_YIELD));

	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
		rc = true;
	/* reset state to idle, unless QV is disabled */
	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* called from ixgbevf_low_latency_poll() */
static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
{
	int rc = true;
	spin_lock_bh(&q_vector->lock);
	if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
		q_vector->state |= IXGBEVF_QV_STATE_POLL_YIELD;
		rc = false;
#ifdef BP_EXTENDED_STATS
		q_vector->rx.ring->stats.yields++;
#endif
	} else {
		/* preserve yield marks */
		q_vector->state |= IXGBEVF_QV_STATE_POLL;
	}
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* returns true if someone tried to get the qv while it was locked */
static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
{
	int rc = false;
	spin_lock_bh(&q_vector->lock);
	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));

	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
		rc = true;
	/* reset state to idle, unless QV is disabled */
	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

/* true if a socket is polling, even if it did not get the lock */
static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
{
	WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
	return q_vector->state & IXGBEVF_QV_USER_PEND;
}

/* false if QV is currently owned */
static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
{
	int rc = true;
	spin_lock_bh(&q_vector->lock);
	if (q_vector->state & IXGBEVF_QV_OWNED)
		rc = false;
	q_vector->state |= IXGBEVF_QV_STATE_DISABLED;
	spin_unlock_bh(&q_vector->lock);
	return rc;
}

#endif /* CONFIG_NET_RX_BUSY_POLL */

/*
 * microsecond values for various ITR rates shifted by 2 to fit itr register
 * with the first 3 bits reserved 0
 */
#define IXGBE_MIN_RSC_ITR	24
#define IXGBE_100K_ITR		40
#define IXGBE_20K_ITR		200
#define IXGBE_10K_ITR		400
#define IXGBE_8K_ITR		500

/* Helper macros to switch between ints/sec and what the register uses.
 * And yes, it's the same math going both ways.  The lowest value
 * supported by all of the ixgbe hardware is 8.
 */
#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG

/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
					  const u32 stat_err_bits)
{
	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
}

static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
{
	u16 ntc = ring->next_to_clean;
	u16 ntu = ring->next_to_use;

	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
}

static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
{
	writel(value, ring->tail);
}

#define IXGBEVF_RX_DESC(R, i)	    \
	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
#define IXGBEVF_TX_DESC(R, i)	    \
	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
#define IXGBEVF_TX_CTXTDESC(R, i)	    \
	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))

#define IXGBE_MAX_JUMBO_FRAME_SIZE	9728 /* Maximum Supported Size 9.5KB */

#define OTHER_VECTOR 1
#define NON_Q_VECTORS (OTHER_VECTOR)

#define MAX_MSIX_Q_VECTORS 2

#define MIN_MSIX_Q_VECTORS 1
#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)

/* board specific private data structure */
struct ixgbevf_adapter {
	/* this field must be first, see ixgbevf_process_skb_fields */
	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];

	struct timer_list watchdog_timer;
	struct work_struct reset_task;
	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];

	/* Interrupt Throttle Rate */
	u16 rx_itr_setting;
	u16 tx_itr_setting;

	/* interrupt masks */
	u32 eims_enable_mask;
	u32 eims_other;

	/* TX */
	int num_tx_queues;
	struct ixgbevf_ring *tx_ring[MAX_TX_QUEUES]; /* One per active queue */
	u64 restart_queue;
	u32 tx_timeout_count;

	/* RX */
	int num_rx_queues;
	struct ixgbevf_ring *rx_ring[MAX_TX_QUEUES]; /* One per active queue */
	u64 hw_csum_rx_error;
	u64 hw_rx_no_dma_resources;
	int num_msix_vectors;
	u32 alloc_rx_page_failed;
	u32 alloc_rx_buff_failed;

	/* Some features need tri-state capability,
	 * thus the additional *_CAPABLE flags.
	 */
	u32 flags;
#define IXGBE_FLAG_IN_WATCHDOG_TASK             (u32)(1)

#define IXGBEVF_FLAG_QUEUE_RESET_REQUESTED	(u32)(1 << 2)

	struct msix_entry *msix_entries;

	/* OS defined structs */
	struct net_device *netdev;
	struct pci_dev *pdev;

	/* structs defined in ixgbe_vf.h */
	struct ixgbe_hw hw;
	u16 msg_enable;
	/* Interrupt Throttle Rate */
	u32 eitr_param;

	struct ixgbevf_hw_stats stats;

	unsigned long state;
	u64 tx_busy;
	unsigned int tx_ring_count;
	unsigned int rx_ring_count;

#ifdef BP_EXTENDED_STATS
	u64 bp_rx_yields;
	u64 bp_rx_cleaned;
	u64 bp_rx_missed;

	u64 bp_tx_yields;
	u64 bp_tx_cleaned;
	u64 bp_tx_missed;
#endif

	u8 __iomem *io_addr; /* Mainly for iounmap use */
	u32 link_speed;
	bool link_up;

	spinlock_t mbx_lock;

	struct work_struct watchdog_task;
};

enum ixbgevf_state_t {
	__IXGBEVF_TESTING,
	__IXGBEVF_RESETTING,
	__IXGBEVF_DOWN,
	__IXGBEVF_DISABLED,
	__IXGBEVF_REMOVING,
	__IXGBEVF_WORK_INIT,
};

enum ixgbevf_boards {
	board_82599_vf,
	board_X540_vf,
	board_X550_vf,
	board_X550EM_x_vf,
};

extern const struct ixgbevf_info ixgbevf_82599_vf_info;
extern const struct ixgbevf_info ixgbevf_X540_vf_info;
extern const struct ixgbevf_info ixgbevf_X550_vf_info;
extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;

/* needed by ethtool.c */
extern const char ixgbevf_driver_name[];
extern const char ixgbevf_driver_version[];

void ixgbevf_up(struct ixgbevf_adapter *adapter);
void ixgbevf_down(struct ixgbevf_adapter *adapter);
void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
void ixgbevf_reset(struct ixgbevf_adapter *adapter);
void ixgbevf_set_ethtool_ops(struct net_device *netdev);
int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
int ethtool_ioctl(struct ifreq *ifr);

extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);

void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);

#ifdef DEBUG
char *ixgbevf_get_hw_dev_name(struct ixgbe_hw *hw);
#define hw_dbg(hw, format, arg...) \
	printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
#else
#define hw_dbg(hw, format, arg...) do {} while (0)
#endif

#endif /* _IXGBEVF_H_ */
Commit	Line	Data
92915f71 GR	1	/*******************************************************************************
	2
	3	Intel 82599 Virtual Function driver
2e7cfbdd	4	Copyright(c) 1999 - 2014 Intel Corporation.
92915f71 GR	5
	6	This program is free software; you can redistribute it and/or modify it
	7	under the terms and conditions of the GNU General Public License,
	8	version 2, as published by the Free Software Foundation.
	9
	10	This program is distributed in the hope it will be useful, but WITHOUT
	11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	more details.
	14
	15	You should have received a copy of the GNU General Public License along with
	16	this program; if not, write to the Free Software Foundation, Inc.,
	17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	18
	19	The full GNU General Public License is included in this distribution in
	20	the file called "COPYING".
	21
	22	Contact Information:
	23	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
	24	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
	25
	26	*******************************************************************************/
	27
	28	#ifndef _IXGBEVF_H_
	29	#define _IXGBEVF_H_
	30
	31	#include <linux/types.h>
dadcd65f	32	#include <linux/bitops.h>
92915f71 GR	33	#include <linux/timer.h>
	34	#include <linux/io.h>
	35	#include <linux/netdevice.h>
dadcd65f	36	#include <linux/if_vlan.h>
4197aa7b	37	#include <linux/u64_stats_sync.h>
92915f71 GR	38
	39	#include "vf.h"
	40
c777cdfa JK	41	#ifdef CONFIG_NET_RX_BUSY_POLL
c777cdfa JK	42	#include <net/busy_poll.h>
3b5dca26	43	#define BP_EXTENDED_STATS
c777cdfa JK	44	#endif
c777cdfa JK	45
92915f71 GR	46	/* wrapper around a pointer to a socket buffer,
	47	* so a DMA handle can be stored along with the buffer */
	48	struct ixgbevf_tx_buffer {
7ad1a093 ET	49	union ixgbe_adv_tx_desc *next_to_watch;
7ad1a093 ET	50	unsigned long time_stamp;
92915f71	51	struct sk_buff *skb;
7ad1a093 ET	52	unsigned int bytecount;
	53	unsigned short gso_segs;
	54	__be16 protocol;
9bdfefd2 ET	55	DEFINE_DMA_UNMAP_ADDR(dma);
9bdfefd2 ET	56	DEFINE_DMA_UNMAP_LEN(len);
7ad1a093	57	u32 tx_flags;
92915f71 GR	58	};
	59
	60	struct ixgbevf_rx_buffer {
92915f71	61	dma_addr_t dma;
bad17234 ET	62	struct page *page;
bad17234 ET	63	unsigned int page_offset;
92915f71 GR	64	};
92915f71 GR	65
095e2617 ET	66	struct ixgbevf_stats {
	67	u64 packets;
	68	u64 bytes;
	69	#ifdef BP_EXTENDED_STATS
	70	u64 yields;
	71	u64 misses;
	72	u64 cleaned;
	73	#endif
	74	};
	75
	76	struct ixgbevf_tx_queue_stats {
	77	u64 restart_queue;
	78	u64 tx_busy;
	79	u64 tx_done_old;
	80	};
	81
	82	struct ixgbevf_rx_queue_stats {
095e2617 ET	83	u64 alloc_rx_page_failed;
	84	u64 alloc_rx_buff_failed;
	85	u64 csum_err;
	86	};
	87
92915f71	88	struct ixgbevf_ring {
6b43c446	89	struct ixgbevf_ring *next;
fb40195c AD	90	struct net_device *netdev;
fb40195c AD	91	struct device *dev;
92915f71 GR	92	void desc; / descriptor ring memory */
	93	dma_addr_t dma; /* phys. address of descriptor ring */
	94	unsigned int size; /* length in bytes */
bad17234 ET	95	u16 count; /* amount of descriptors */
	96	u16 next_to_use;
	97	u16 next_to_clean;
	98	u16 next_to_alloc;
92915f71	99
92915f71 GR	100	union {
	101	struct ixgbevf_tx_buffer *tx_buffer_info;
	102	struct ixgbevf_rx_buffer *rx_buffer_info;
	103	};
	104
095e2617 ET	105	struct ixgbevf_stats stats;
	106	struct u64_stats_sync syncp;
	107	union {
	108	struct ixgbevf_tx_queue_stats tx_stats;
	109	struct ixgbevf_rx_queue_stats rx_stats;
	110	};
	111
55fb277c	112	u64 hw_csum_rx_error;
5cdab2f6	113	u8 __iomem *tail;
bad17234	114	struct sk_buff *skb;
92915f71	115
92915f71 GR	116	u16 reg_idx; /* holds the special value that gets the hardware register
	117	* offset associated with this ring, which is different
	118	* for DCB and RSS modes */
095e2617	119	int queue_index; /* needed for multiqueue queue management */
92915f71 GR	120	};
92915f71 GR	121
92915f71 GR	122	/* How many Rx Buffers do we bundle into one write to the hardware ? */
	123	#define IXGBEVF_RX_BUFFER_WRITE 16 /* Must be power of 2 */
	124
56e94095 AD	125	#define MAX_RX_QUEUES IXGBE_VF_MAX_RX_QUEUES
56e94095 AD	126	#define MAX_TX_QUEUES IXGBE_VF_MAX_TX_QUEUES
92915f71 GR	127
	128	#define IXGBEVF_DEFAULT_TXD 1024
	129	#define IXGBEVF_DEFAULT_RXD 512
	130	#define IXGBEVF_MAX_TXD 4096
	131	#define IXGBEVF_MIN_TXD 64
	132	#define IXGBEVF_MAX_RXD 4096
	133	#define IXGBEVF_MIN_RXD 64
	134
	135	/* Supported Rx Buffer Sizes */
92915f71	136	#define IXGBEVF_RXBUFFER_256 256 /* Used for packet split */
bad17234	137	#define IXGBEVF_RXBUFFER_2048 2048
92915f71 GR	138
92915f71 GR	139	#define IXGBEVF_RX_HDR_SIZE IXGBEVF_RXBUFFER_256
bad17234	140	#define IXGBEVF_RX_BUFSZ IXGBEVF_RXBUFFER_2048
92915f71 GR	141
	142	#define MAXIMUM_ETHERNET_VLAN_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
	143
	144	#define IXGBE_TX_FLAGS_CSUM (u32)(1)
	145	#define IXGBE_TX_FLAGS_VLAN (u32)(1 << 1)
	146	#define IXGBE_TX_FLAGS_TSO (u32)(1 << 2)
	147	#define IXGBE_TX_FLAGS_IPV4 (u32)(1 << 3)
92915f71 GR	148	#define IXGBE_TX_FLAGS_VLAN_MASK 0xffff0000
	149	#define IXGBE_TX_FLAGS_VLAN_PRIO_MASK 0x0000e000
	150	#define IXGBE_TX_FLAGS_VLAN_SHIFT 16
	151
6b43c446 AD	152	struct ixgbevf_ring_container {
6b43c446 AD	153	struct ixgbevf_ring ring; / pointer to linked list of rings */
5f3600eb AD	154	unsigned int total_bytes; /* total bytes processed this int */
5f3600eb AD	155	unsigned int total_packets; /* total packets processed this int */
6b43c446 AD	156	u8 count; /* total number of rings in vector */
	157	u8 itr; /* current ITR setting for ring */
	158	};
	159
	160	/* iterator for handling rings in ring container */
	161	#define ixgbevf_for_each_ring(pos, head) \
	162	for (pos = (head).ring; pos != NULL; pos = pos->next)
	163
92915f71 GR	164	/* MAX_MSIX_Q_VECTORS of these are allocated,
	165	* but we only use one per queue-specific vector.
	166	*/
	167	struct ixgbevf_q_vector {
	168	struct ixgbevf_adapter *adapter;
5f3600eb AD	169	u16 v_idx; /* index of q_vector within array, also used for
	170	* finding the bit in EICR and friends that
	171	* represents the vector for this ring */
	172	u16 itr; /* Interrupt throttle rate written to EITR */
92915f71	173	struct napi_struct napi;
6b43c446	174	struct ixgbevf_ring_container rx, tx;
fa71ae27	175	char name[IFNAMSIZ + 9];
c777cdfa JK	176	#ifdef CONFIG_NET_RX_BUSY_POLL
	177	unsigned int state;
	178	#define IXGBEVF_QV_STATE_IDLE 0
	179	#define IXGBEVF_QV_STATE_NAPI 1 /* NAPI owns this QV */
	180	#define IXGBEVF_QV_STATE_POLL 2 /* poll owns this QV */
	181	#define IXGBEVF_QV_STATE_DISABLED 4 /* QV is disabled */
	182	#define IXGBEVF_QV_OWNED (IXGBEVF_QV_STATE_NAPI \| IXGBEVF_QV_STATE_POLL)
	183	#define IXGBEVF_QV_LOCKED (IXGBEVF_QV_OWNED \| IXGBEVF_QV_STATE_DISABLED)
	184	#define IXGBEVF_QV_STATE_NAPI_YIELD 8 /* NAPI yielded this QV */
	185	#define IXGBEVF_QV_STATE_POLL_YIELD 16 /* poll yielded this QV */
	186	#define IXGBEVF_QV_YIELD (IXGBEVF_QV_STATE_NAPI_YIELD \| IXGBEVF_QV_STATE_POLL_YIELD)
	187	#define IXGBEVF_QV_USER_PEND (IXGBEVF_QV_STATE_POLL \| IXGBEVF_QV_STATE_POLL_YIELD)
	188	spinlock_t lock;
	189	#endif /* CONFIG_NET_RX_BUSY_POLL */
92915f71	190	};
c777cdfa JK	191	#ifdef CONFIG_NET_RX_BUSY_POLL
	192	static inline void ixgbevf_qv_init_lock(struct ixgbevf_q_vector *q_vector)
	193	{
	194
	195	spin_lock_init(&q_vector->lock);
	196	q_vector->state = IXGBEVF_QV_STATE_IDLE;
	197	}
	198
	199	/* called from the device poll routine to get ownership of a q_vector */
	200	static inline bool ixgbevf_qv_lock_napi(struct ixgbevf_q_vector *q_vector)
	201	{
	202	int rc = true;
	203	spin_lock_bh(&q_vector->lock);
	204	if (q_vector->state & IXGBEVF_QV_LOCKED) {
	205	WARN_ON(q_vector->state & IXGBEVF_QV_STATE_NAPI);
	206	q_vector->state \|= IXGBEVF_QV_STATE_NAPI_YIELD;
	207	rc = false;
3b5dca26	208	#ifdef BP_EXTENDED_STATS
095e2617	209	q_vector->tx.ring->stats.yields++;
3b5dca26	210	#endif
c777cdfa JK	211	} else {
	212	/* we don't care if someone yielded */
	213	q_vector->state = IXGBEVF_QV_STATE_NAPI;
	214	}
	215	spin_unlock_bh(&q_vector->lock);
	216	return rc;
	217	}
	218
	219	/* returns true is someone tried to get the qv while napi had it */
	220	static inline bool ixgbevf_qv_unlock_napi(struct ixgbevf_q_vector *q_vector)
	221	{
	222	int rc = false;
	223	spin_lock_bh(&q_vector->lock);
	224	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_POLL \|
	225	IXGBEVF_QV_STATE_NAPI_YIELD));
	226
	227	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
	228	rc = true;
	229	/* reset state to idle, unless QV is disabled */
	230	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	231	spin_unlock_bh(&q_vector->lock);
	232	return rc;
	233	}
	234
	235	/* called from ixgbevf_low_latency_poll() */
	236	static inline bool ixgbevf_qv_lock_poll(struct ixgbevf_q_vector *q_vector)
	237	{
	238	int rc = true;
	239	spin_lock_bh(&q_vector->lock);
	240	if ((q_vector->state & IXGBEVF_QV_LOCKED)) {
	241	q_vector->state \|= IXGBEVF_QV_STATE_POLL_YIELD;
	242	rc = false;
3b5dca26	243	#ifdef BP_EXTENDED_STATS
095e2617	244	q_vector->rx.ring->stats.yields++;
3b5dca26	245	#endif
c777cdfa JK	246	} else {
	247	/* preserve yield marks */
	248	q_vector->state \|= IXGBEVF_QV_STATE_POLL;
	249	}
	250	spin_unlock_bh(&q_vector->lock);
	251	return rc;
	252	}
	253
	254	/* returns true if someone tried to get the qv while it was locked */
	255	static inline bool ixgbevf_qv_unlock_poll(struct ixgbevf_q_vector *q_vector)
	256	{
	257	int rc = false;
	258	spin_lock_bh(&q_vector->lock);
	259	WARN_ON(q_vector->state & (IXGBEVF_QV_STATE_NAPI));
	260
	261	if (q_vector->state & IXGBEVF_QV_STATE_POLL_YIELD)
	262	rc = true;
	263	/* reset state to idle, unless QV is disabled */
	264	q_vector->state &= IXGBEVF_QV_STATE_DISABLED;
	265	spin_unlock_bh(&q_vector->lock);
	266	return rc;
	267	}
	268
	269	/* true if a socket is polling, even if it did not get the lock */
	270	static inline bool ixgbevf_qv_busy_polling(struct ixgbevf_q_vector *q_vector)
	271	{
	272	WARN_ON(!(q_vector->state & IXGBEVF_QV_OWNED));
	273	return q_vector->state & IXGBEVF_QV_USER_PEND;
	274	}
	275
	276	/* false if QV is currently owned */
	277	static inline bool ixgbevf_qv_disable(struct ixgbevf_q_vector *q_vector)
	278	{
	279	int rc = true;
	280	spin_lock_bh(&q_vector->lock);
	281	if (q_vector->state & IXGBEVF_QV_OWNED)
	282	rc = false;
e689e728	283	q_vector->state \|= IXGBEVF_QV_STATE_DISABLED;
c777cdfa JK	284	spin_unlock_bh(&q_vector->lock);
	285	return rc;
	286	}
	287
	288	#endif /* CONFIG_NET_RX_BUSY_POLL */
92915f71	289
5f3600eb AD	290	/*
	291	* microsecond values for various ITR rates shifted by 2 to fit itr register
	292	* with the first 3 bits reserved 0
	293	*/
	294	#define IXGBE_MIN_RSC_ITR 24
	295	#define IXGBE_100K_ITR 40
	296	#define IXGBE_20K_ITR 200
	297	#define IXGBE_10K_ITR 400
	298	#define IXGBE_8K_ITR 500
	299
92915f71 GR	300	/* Helper macros to switch between ints/sec and what the register uses.
	301	* And yes, it's the same math going both ways. The lowest value
	302	* supported by all of the ixgbe hardware is 8.
	303	*/
	304	#define EITR_INTS_PER_SEC_TO_REG(_eitr) \
	305	((_eitr) ? (1000000000 / ((_eitr) * 256)) : 8)
	306	#define EITR_REG_TO_INTS_PER_SEC EITR_INTS_PER_SEC_TO_REG
	307
ec62fe26 ET	308	/* ixgbevf_test_staterr - tests bits in Rx descriptor status and error fields */
	309	static inline __le32 ixgbevf_test_staterr(union ixgbe_adv_rx_desc *rx_desc,
	310	const u32 stat_err_bits)
	311	{
	312	return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
	313	}
	314
f880d07b DS	315	static inline u16 ixgbevf_desc_unused(struct ixgbevf_ring *ring)
	316	{
	317	u16 ntc = ring->next_to_clean;
	318	u16 ntu = ring->next_to_use;
	319
	320	return ((ntc > ntu) ? 0 : ring->count) + ntc - ntu - 1;
	321	}
92915f71	322
06380db6 MR	323	static inline void ixgbevf_write_tail(struct ixgbevf_ring *ring, u32 value)
	324	{
	325	writel(value, ring->tail);
	326	}
	327
908421f6 AD	328	#define IXGBEVF_RX_DESC(R, i) \
	329	(&(((union ixgbe_adv_rx_desc *)((R)->desc))[i]))
	330	#define IXGBEVF_TX_DESC(R, i) \
	331	(&(((union ixgbe_adv_tx_desc *)((R)->desc))[i]))
	332	#define IXGBEVF_TX_CTXTDESC(R, i) \
	333	(&(((struct ixgbe_adv_tx_context_desc *)((R)->desc))[i]))
92915f71	334
c88887e0	335	#define IXGBE_MAX_JUMBO_FRAME_SIZE 9728 /* Maximum Supported Size 9.5KB */
92915f71 GR	336
	337	#define OTHER_VECTOR 1
	338	#define NON_Q_VECTORS (OTHER_VECTOR)
	339
	340	#define MAX_MSIX_Q_VECTORS 2
92915f71	341
fa71ae27	342	#define MIN_MSIX_Q_VECTORS 1
92915f71 GR	343	#define MIN_MSIX_COUNT (MIN_MSIX_Q_VECTORS + NON_Q_VECTORS)
	344
	345	/* board specific private data structure */
	346	struct ixgbevf_adapter {
dff80520	347	/* this field must be first, see ixgbevf_process_skb_fields */
dadcd65f	348	unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
dff80520 ET	349
dff80520 ET	350	struct timer_list watchdog_timer;
92915f71 GR	351	struct work_struct reset_task;
92915f71 GR	352	struct ixgbevf_q_vector *q_vector[MAX_MSIX_Q_VECTORS];
92915f71 GR	353
92915f71 GR	354	/* Interrupt Throttle Rate */
5f3600eb AD	355	u16 rx_itr_setting;
	356	u16 tx_itr_setting;
	357
	358	/* interrupt masks */
	359	u32 eims_enable_mask;
	360	u32 eims_other;
92915f71 GR	361
92915f71 GR	362	/* TX */
92915f71	363	int num_tx_queues;
97031922	364	struct ixgbevf_ring tx_ring[MAX_TX_QUEUES]; / One per active queue */
92915f71	365	u64 restart_queue;
92915f71	366	u32 tx_timeout_count;
92915f71 GR	367
92915f71 GR	368	/* RX */
92915f71	369	int num_rx_queues;
97031922	370	struct ixgbevf_ring rx_ring[MAX_TX_QUEUES]; / One per active queue */
92915f71 GR	371	u64 hw_csum_rx_error;
92915f71 GR	372	u64 hw_rx_no_dma_resources;
92915f71	373	int num_msix_vectors;
92915f71 GR	374	u32 alloc_rx_page_failed;
	375	u32 alloc_rx_buff_failed;
	376
	377	/* Some features need tri-state capability,
	378	* thus the additional *_CAPABLE flags.
	379	*/
	380	u32 flags;
525a940c	381	#define IXGBE_FLAG_IN_WATCHDOG_TASK (u32)(1)
688ff32d	382
220fe050	383	#define IXGBEVF_FLAG_QUEUE_RESET_REQUESTED (u32)(1 << 2)
77d5dfca	384
97031922 ET	385	struct msix_entry *msix_entries;
97031922 ET	386
92915f71 GR	387	/* OS defined structs */
	388	struct net_device *netdev;
	389	struct pci_dev *pdev;
92915f71 GR	390
	391	/* structs defined in ixgbe_vf.h */
	392	struct ixgbe_hw hw;
	393	u16 msg_enable;
92915f71 GR	394	/* Interrupt Throttle Rate */
	395	u32 eitr_param;
	396
97031922 ET	397	struct ixgbevf_hw_stats stats;
97031922 ET	398
92915f71	399	unsigned long state;
92915f71 GR	400	u64 tx_busy;
	401	unsigned int tx_ring_count;
	402	unsigned int rx_ring_count;
	403
3b5dca26 JK	404	#ifdef BP_EXTENDED_STATS
	405	u64 bp_rx_yields;
	406	u64 bp_rx_cleaned;
	407	u64 bp_rx_missed;
	408
	409	u64 bp_tx_yields;
	410	u64 bp_tx_cleaned;
	411	u64 bp_tx_missed;
	412	#endif
	413
dbf8b0d8	414	u8 __iomem io_addr; / Mainly for iounmap use */
92915f71 GR	415	u32 link_speed;
92915f71 GR	416	bool link_up;
92915f71	417
1c55ed76	418	spinlock_t mbx_lock;
97031922 ET	419
97031922 ET	420	struct work_struct watchdog_task;
92915f71 GR	421	};
	422
	423	enum ixbgevf_state_t {
	424	__IXGBEVF_TESTING,
	425	__IXGBEVF_RESETTING,
2e7cfbdd	426	__IXGBEVF_DOWN,
bc0c7151	427	__IXGBEVF_DISABLED,
2e7cfbdd	428	__IXGBEVF_REMOVING,
ea699569	429	__IXGBEVF_WORK_INIT,
92915f71 GR	430	};
	431
	432	enum ixgbevf_boards {
	433	board_82599_vf,
2316aa2a	434	board_X540_vf,
47068b0d ET	435	board_X550_vf,
47068b0d ET	436	board_X550EM_x_vf,
92915f71 GR	437	};
92915f71 GR	438
3d8fe98f SH	439	extern const struct ixgbevf_info ixgbevf_82599_vf_info;
3d8fe98f SH	440	extern const struct ixgbevf_info ixgbevf_X540_vf_info;
47068b0d ET	441	extern const struct ixgbevf_info ixgbevf_X550_vf_info;
47068b0d ET	442	extern const struct ixgbevf_info ixgbevf_X550EM_x_vf_info;
b5417bf8	443	extern const struct ixgbe_mbx_operations ixgbevf_mbx_ops;
92915f71 GR	444
92915f71 GR	445	/* needed by ethtool.c */
3d8fe98f	446	extern const char ixgbevf_driver_name[];
92915f71 GR	447	extern const char ixgbevf_driver_version[];
92915f71 GR	448
5ccc921a JP	449	void ixgbevf_up(struct ixgbevf_adapter *adapter);
	450	void ixgbevf_down(struct ixgbevf_adapter *adapter);
	451	void ixgbevf_reinit_locked(struct ixgbevf_adapter *adapter);
	452	void ixgbevf_reset(struct ixgbevf_adapter *adapter);
	453	void ixgbevf_set_ethtool_ops(struct net_device *netdev);
05d063aa ET	454	int ixgbevf_setup_rx_resources(struct ixgbevf_ring *);
	455	int ixgbevf_setup_tx_resources(struct ixgbevf_ring *);
	456	void ixgbevf_free_rx_resources(struct ixgbevf_ring *);
	457	void ixgbevf_free_tx_resources(struct ixgbevf_ring *);
5ccc921a JP	458	void ixgbevf_update_stats(struct ixgbevf_adapter *adapter);
	459	int ethtool_ioctl(struct ifreq *ifr);
	460
3849623e JK	461	extern void ixgbevf_write_eitr(struct ixgbevf_q_vector *q_vector);
3849623e JK	462
5ccc921a JP	463	void ixgbe_napi_add_all(struct ixgbevf_adapter *adapter);
5ccc921a JP	464	void ixgbe_napi_del_all(struct ixgbevf_adapter *adapter);
92915f71 GR	465
92915f71 GR	466	#ifdef DEBUG
5ccc921a	467	char ixgbevf_get_hw_dev_name(struct ixgbe_hw hw);
92915f71 GR	468	#define hw_dbg(hw, format, arg...) \
	469	printk(KERN_DEBUG "%s: " format, ixgbevf_get_hw_dev_name(hw), ##arg)
	470	#else
	471	#define hw_dbg(hw, format, arg...) do {} while (0)
	472	#endif
	473
	474	#endif /* _IXGBEVF_H_ */