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95252236 GFT |
1 | /* |
2 | * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver | |
3 | * | |
4 | * Copyright 2008 JMicron Technology Corporation | |
5 | * http://www.jmicron.com/ | |
e47dfcd8 | 6 | * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org> |
95252236 GFT |
7 | * |
8 | * Author: Guo-Fu Tseng <cooldavid@cooldavid.org> | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; either version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef __JME_H_INCLUDED__ | |
2fccd281 | 26 | #define __JME_H_INCLUDED__ |
a6b7a407 | 27 | #include <linux/interrupt.h> |
95252236 GFT |
28 | |
29 | #define DRV_NAME "jme" | |
c9060414 | 30 | #define DRV_VERSION "1.0.8" |
95252236 GFT |
31 | |
32 | #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250 | |
33 | #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260 | |
34 | ||
35 | /* | |
36 | * Message related definitions | |
37 | */ | |
38 | #define JME_DEF_MSG_ENABLE \ | |
39 | (NETIF_MSG_PROBE | \ | |
40 | NETIF_MSG_LINK | \ | |
41 | NETIF_MSG_RX_ERR | \ | |
42 | NETIF_MSG_TX_ERR | \ | |
43 | NETIF_MSG_HW) | |
44 | ||
95252236 | 45 | #ifdef TX_DEBUG |
f8502ce4 JP |
46 | #define tx_dbg(priv, fmt, args...) \ |
47 | printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args) | |
95252236 | 48 | #else |
f8502ce4 JP |
49 | #define tx_dbg(priv, fmt, args...) \ |
50 | do { \ | |
51 | if (0) \ | |
52 | printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \ | |
53 | } while (0) | |
95252236 GFT |
54 | #endif |
55 | ||
95252236 GFT |
56 | /* |
57 | * Extra PCI Configuration space interface | |
58 | */ | |
59 | #define PCI_DCSR_MRRS 0x59 | |
60 | #define PCI_DCSR_MRRS_MASK 0x70 | |
61 | ||
62 | enum pci_dcsr_mrrs_vals { | |
63 | MRRS_128B = 0x00, | |
64 | MRRS_256B = 0x10, | |
65 | MRRS_512B = 0x20, | |
66 | MRRS_1024B = 0x30, | |
67 | MRRS_2048B = 0x40, | |
68 | MRRS_4096B = 0x50, | |
69 | }; | |
70 | ||
71 | #define PCI_SPI 0xB0 | |
72 | ||
73 | enum pci_spi_bits { | |
74 | SPI_EN = 0x10, | |
75 | SPI_MISO = 0x08, | |
76 | SPI_MOSI = 0x04, | |
77 | SPI_SCLK = 0x02, | |
78 | SPI_CS = 0x01, | |
79 | }; | |
80 | ||
81 | struct jme_spi_op { | |
82 | void __user *uwbuf; | |
83 | void __user *urbuf; | |
84 | __u8 wn; /* Number of write actions */ | |
85 | __u8 rn; /* Number of read actions */ | |
86 | __u8 bitn; /* Number of bits per action */ | |
87 | __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/ | |
88 | __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */ | |
89 | ||
90 | /* Internal use only */ | |
91 | u8 *kwbuf; | |
92 | u8 *krbuf; | |
93 | u8 sr; | |
94 | u16 halfclk; /* Half of clock cycle calculated from spd, in ns */ | |
95 | }; | |
96 | ||
97 | enum jme_spi_op_bits { | |
98 | SPI_MODE_CPHA = 0x01, | |
99 | SPI_MODE_CPOL = 0x02, | |
100 | SPI_MODE_DUP = 0x80, | |
101 | }; | |
102 | ||
103 | #define HALF_US 500 /* 500 ns */ | |
95252236 | 104 | |
4872b11f GFT |
105 | #define PCI_PRIV_PE1 0xE4 |
106 | ||
107 | enum pci_priv_pe1_bit_masks { | |
108 | PE1_ASPMSUPRT = 0x00000003, /* | |
109 | * RW: | |
110 | * Aspm_support[1:0] | |
111 | * (R/W Port of 5C[11:10]) | |
112 | */ | |
113 | PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */ | |
114 | PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */ | |
115 | PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */ | |
116 | PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */ | |
117 | PE1_GPREG0 = 0x0000FF00, /* | |
118 | * SRW: | |
119 | * Cfg_gp_reg0 | |
120 | * [7:6] phy_giga BG control | |
121 | * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#) | |
122 | * [4:0] Reserved | |
123 | */ | |
124 | PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */ | |
125 | PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */ | |
126 | PE1_REVID = 0xFF000000, /* RO: Rev ID */ | |
127 | }; | |
128 | ||
129 | enum pci_priv_pe1_values { | |
130 | PE1_GPREG0_ENBG = 0x00000000, /* en BG */ | |
131 | PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */ | |
132 | PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */ | |
133 | PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */ | |
134 | }; | |
135 | ||
95252236 GFT |
136 | /* |
137 | * Dynamic(adaptive)/Static PCC values | |
138 | */ | |
139 | enum dynamic_pcc_values { | |
140 | PCC_OFF = 0, | |
141 | PCC_P1 = 1, | |
142 | PCC_P2 = 2, | |
143 | PCC_P3 = 3, | |
144 | ||
145 | PCC_OFF_TO = 0, | |
146 | PCC_P1_TO = 1, | |
147 | PCC_P2_TO = 64, | |
148 | PCC_P3_TO = 128, | |
149 | ||
150 | PCC_OFF_CNT = 0, | |
151 | PCC_P1_CNT = 1, | |
152 | PCC_P2_CNT = 16, | |
153 | PCC_P3_CNT = 32, | |
154 | }; | |
155 | struct dynpcc_info { | |
156 | unsigned long last_bytes; | |
157 | unsigned long last_pkts; | |
158 | unsigned long intr_cnt; | |
159 | unsigned char cur; | |
160 | unsigned char attempt; | |
161 | unsigned char cnt; | |
162 | }; | |
163 | #define PCC_INTERVAL_US 100000 | |
164 | #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US)) | |
165 | #define PCC_P3_THRESHOLD (2 * 1024 * 1024) | |
166 | #define PCC_P2_THRESHOLD 800 | |
167 | #define PCC_INTR_THRESHOLD 800 | |
168 | #define PCC_TX_TO 1000 | |
169 | #define PCC_TX_CNT 8 | |
170 | ||
171 | /* | |
172 | * TX/RX Descriptors | |
173 | * | |
174 | * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024 | |
175 | */ | |
176 | #define RING_DESC_ALIGN 16 /* Descriptor alignment */ | |
177 | #define TX_DESC_SIZE 16 | |
178 | #define TX_RING_NR 8 | |
179 | #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN) | |
180 | ||
181 | struct txdesc { | |
182 | union { | |
183 | __u8 all[16]; | |
184 | __le32 dw[4]; | |
185 | struct { | |
186 | /* DW0 */ | |
187 | __le16 vlan; | |
188 | __u8 rsv1; | |
189 | __u8 flags; | |
190 | ||
191 | /* DW1 */ | |
192 | __le16 datalen; | |
193 | __le16 mss; | |
194 | ||
195 | /* DW2 */ | |
196 | __le16 pktsize; | |
197 | __le16 rsv2; | |
198 | ||
199 | /* DW3 */ | |
200 | __le32 bufaddr; | |
201 | } desc1; | |
202 | struct { | |
203 | /* DW0 */ | |
204 | __le16 rsv1; | |
205 | __u8 rsv2; | |
206 | __u8 flags; | |
207 | ||
208 | /* DW1 */ | |
209 | __le16 datalen; | |
210 | __le16 rsv3; | |
211 | ||
212 | /* DW2 */ | |
213 | __le32 bufaddrh; | |
214 | ||
215 | /* DW3 */ | |
216 | __le32 bufaddrl; | |
217 | } desc2; | |
218 | struct { | |
219 | /* DW0 */ | |
220 | __u8 ehdrsz; | |
221 | __u8 rsv1; | |
222 | __u8 rsv2; | |
223 | __u8 flags; | |
224 | ||
225 | /* DW1 */ | |
226 | __le16 trycnt; | |
227 | __le16 segcnt; | |
228 | ||
229 | /* DW2 */ | |
230 | __le16 pktsz; | |
231 | __le16 rsv3; | |
232 | ||
233 | /* DW3 */ | |
234 | __le32 bufaddrl; | |
235 | } descwb; | |
236 | }; | |
237 | }; | |
238 | ||
239 | enum jme_txdesc_flags_bits { | |
240 | TXFLAG_OWN = 0x80, | |
241 | TXFLAG_INT = 0x40, | |
242 | TXFLAG_64BIT = 0x20, | |
243 | TXFLAG_TCPCS = 0x10, | |
244 | TXFLAG_UDPCS = 0x08, | |
245 | TXFLAG_IPCS = 0x04, | |
246 | TXFLAG_LSEN = 0x02, | |
247 | TXFLAG_TAGON = 0x01, | |
248 | }; | |
249 | ||
250 | #define TXDESC_MSS_SHIFT 2 | |
44d8d2e9 | 251 | enum jme_txwbdesc_flags_bits { |
95252236 GFT |
252 | TXWBFLAG_OWN = 0x80, |
253 | TXWBFLAG_INT = 0x40, | |
254 | TXWBFLAG_TMOUT = 0x20, | |
255 | TXWBFLAG_TRYOUT = 0x10, | |
256 | TXWBFLAG_COL = 0x08, | |
257 | ||
258 | TXWBFLAG_ALLERR = TXWBFLAG_TMOUT | | |
259 | TXWBFLAG_TRYOUT | | |
260 | TXWBFLAG_COL, | |
261 | }; | |
262 | ||
263 | #define RX_DESC_SIZE 16 | |
264 | #define RX_RING_NR 4 | |
265 | #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN) | |
266 | #define RX_BUF_DMA_ALIGN 8 | |
267 | #define RX_PREPAD_SIZE 10 | |
268 | #define ETH_CRC_LEN 2 | |
269 | #define RX_VLANHDR_LEN 2 | |
270 | #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \ | |
271 | ETH_HLEN + \ | |
272 | ETH_CRC_LEN + \ | |
273 | RX_VLANHDR_LEN + \ | |
274 | RX_BUF_DMA_ALIGN) | |
275 | ||
276 | struct rxdesc { | |
277 | union { | |
278 | __u8 all[16]; | |
279 | __le32 dw[4]; | |
280 | struct { | |
281 | /* DW0 */ | |
282 | __le16 rsv2; | |
283 | __u8 rsv1; | |
284 | __u8 flags; | |
285 | ||
286 | /* DW1 */ | |
287 | __le16 datalen; | |
288 | __le16 wbcpl; | |
289 | ||
290 | /* DW2 */ | |
291 | __le32 bufaddrh; | |
292 | ||
293 | /* DW3 */ | |
294 | __le32 bufaddrl; | |
295 | } desc1; | |
296 | struct { | |
297 | /* DW0 */ | |
298 | __le16 vlan; | |
299 | __le16 flags; | |
300 | ||
301 | /* DW1 */ | |
302 | __le16 framesize; | |
303 | __u8 errstat; | |
304 | __u8 desccnt; | |
305 | ||
306 | /* DW2 */ | |
307 | __le32 rsshash; | |
308 | ||
309 | /* DW3 */ | |
310 | __u8 hashfun; | |
311 | __u8 hashtype; | |
312 | __le16 resrv; | |
313 | } descwb; | |
314 | }; | |
315 | }; | |
316 | ||
317 | enum jme_rxdesc_flags_bits { | |
318 | RXFLAG_OWN = 0x80, | |
319 | RXFLAG_INT = 0x40, | |
320 | RXFLAG_64BIT = 0x20, | |
321 | }; | |
322 | ||
323 | enum jme_rxwbdesc_flags_bits { | |
324 | RXWBFLAG_OWN = 0x8000, | |
325 | RXWBFLAG_INT = 0x4000, | |
326 | RXWBFLAG_MF = 0x2000, | |
327 | RXWBFLAG_64BIT = 0x2000, | |
328 | RXWBFLAG_TCPON = 0x1000, | |
329 | RXWBFLAG_UDPON = 0x0800, | |
330 | RXWBFLAG_IPCS = 0x0400, | |
331 | RXWBFLAG_TCPCS = 0x0200, | |
332 | RXWBFLAG_UDPCS = 0x0100, | |
333 | RXWBFLAG_TAGON = 0x0080, | |
334 | RXWBFLAG_IPV4 = 0x0040, | |
335 | RXWBFLAG_IPV6 = 0x0020, | |
336 | RXWBFLAG_PAUSE = 0x0010, | |
337 | RXWBFLAG_MAGIC = 0x0008, | |
338 | RXWBFLAG_WAKEUP = 0x0004, | |
339 | RXWBFLAG_DEST = 0x0003, | |
340 | RXWBFLAG_DEST_UNI = 0x0001, | |
341 | RXWBFLAG_DEST_MUL = 0x0002, | |
342 | RXWBFLAG_DEST_BRO = 0x0003, | |
343 | }; | |
344 | ||
345 | enum jme_rxwbdesc_desccnt_mask { | |
346 | RXWBDCNT_WBCPL = 0x80, | |
347 | RXWBDCNT_DCNT = 0x7F, | |
348 | }; | |
349 | ||
350 | enum jme_rxwbdesc_errstat_bits { | |
351 | RXWBERR_LIMIT = 0x80, | |
352 | RXWBERR_MIIER = 0x40, | |
353 | RXWBERR_NIBON = 0x20, | |
354 | RXWBERR_COLON = 0x10, | |
355 | RXWBERR_ABORT = 0x08, | |
356 | RXWBERR_SHORT = 0x04, | |
357 | RXWBERR_OVERUN = 0x02, | |
358 | RXWBERR_CRCERR = 0x01, | |
359 | RXWBERR_ALLERR = 0xFF, | |
360 | }; | |
361 | ||
362 | /* | |
363 | * Buffer information corresponding to ring descriptors. | |
364 | */ | |
365 | struct jme_buffer_info { | |
366 | struct sk_buff *skb; | |
367 | dma_addr_t mapping; | |
368 | int len; | |
369 | int nr_desc; | |
370 | unsigned long start_xmit; | |
371 | }; | |
372 | ||
373 | /* | |
374 | * The structure holding buffer information and ring descriptors all together. | |
375 | */ | |
95252236 GFT |
376 | struct jme_ring { |
377 | void *alloc; /* pointer to allocated memory */ | |
378 | void *desc; /* pointer to ring memory */ | |
379 | dma_addr_t dmaalloc; /* phys address of ring alloc */ | |
380 | dma_addr_t dma; /* phys address for ring dma */ | |
381 | ||
382 | /* Buffer information corresponding to each descriptor */ | |
47bd10d1 | 383 | struct jme_buffer_info *bufinf; |
95252236 GFT |
384 | |
385 | int next_to_use; | |
386 | atomic_t next_to_clean; | |
387 | atomic_t nr_free; | |
388 | }; | |
389 | ||
390 | #define NET_STAT(priv) (priv->dev->stats) | |
391 | #define NETDEV_GET_STATS(netdev, fun_ptr) | |
392 | #define DECLARE_NET_DEVICE_STATS | |
393 | ||
394 | #define DECLARE_NAPI_STRUCT struct napi_struct napi; | |
395 | #define NETIF_NAPI_SET(dev, napis, pollfn, q) \ | |
396 | netif_napi_add(dev, napis, pollfn, q); | |
397 | #define JME_NAPI_HOLDER(holder) struct napi_struct *holder | |
398 | #define JME_NAPI_WEIGHT(w) int w | |
399 | #define JME_NAPI_WEIGHT_VAL(w) w | |
400 | #define JME_NAPI_WEIGHT_SET(w, r) | |
288379f0 | 401 | #define JME_RX_COMPLETE(dev, napis) napi_complete(napis) |
95252236 GFT |
402 | #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi); |
403 | #define JME_NAPI_DISABLE(priv) \ | |
404 | if (!napi_disable_pending(&priv->napi)) \ | |
405 | napi_disable(&priv->napi); | |
406 | #define JME_RX_SCHEDULE_PREP(priv) \ | |
288379f0 | 407 | napi_schedule_prep(&priv->napi) |
95252236 | 408 | #define JME_RX_SCHEDULE(priv) \ |
288379f0 | 409 | __napi_schedule(&priv->napi); |
95252236 GFT |
410 | |
411 | /* | |
412 | * Jmac Adapter Private data | |
413 | */ | |
95252236 GFT |
414 | struct jme_adapter { |
415 | struct pci_dev *pdev; | |
416 | struct net_device *dev; | |
417 | void __iomem *regs; | |
95252236 GFT |
418 | struct mii_if_info mii_if; |
419 | struct jme_ring rxring[RX_RING_NR]; | |
420 | struct jme_ring txring[TX_RING_NR]; | |
421 | spinlock_t phy_lock; | |
422 | spinlock_t macaddr_lock; | |
423 | spinlock_t rxmcs_lock; | |
424 | struct tasklet_struct rxempty_task; | |
425 | struct tasklet_struct rxclean_task; | |
426 | struct tasklet_struct txclean_task; | |
427 | struct tasklet_struct linkch_task; | |
428 | struct tasklet_struct pcc_task; | |
429 | unsigned long flags; | |
430 | u32 reg_txcs; | |
431 | u32 reg_txpfc; | |
432 | u32 reg_rxcs; | |
433 | u32 reg_rxmcs; | |
434 | u32 reg_ghc; | |
435 | u32 reg_pmcs; | |
854a2e7c | 436 | u32 reg_gpreg1; |
95252236 GFT |
437 | u32 phylink; |
438 | u32 tx_ring_size; | |
439 | u32 tx_ring_mask; | |
440 | u32 tx_wake_threshold; | |
441 | u32 rx_ring_size; | |
442 | u32 rx_ring_mask; | |
443 | u8 mrrs; | |
444 | unsigned int fpgaver; | |
19d96017 GFT |
445 | u8 chiprev; |
446 | u8 chip_main_rev; | |
447 | u8 chip_sub_rev; | |
448 | u8 pcirev; | |
95252236 GFT |
449 | u32 msg_enable; |
450 | struct ethtool_cmd old_ecmd; | |
451 | unsigned int old_mtu; | |
95252236 GFT |
452 | struct dynpcc_info dpi; |
453 | atomic_t intr_sem; | |
454 | atomic_t link_changing; | |
455 | atomic_t tx_cleaning; | |
456 | atomic_t rx_cleaning; | |
457 | atomic_t rx_empty; | |
458 | int (*jme_rx)(struct sk_buff *skb); | |
95252236 GFT |
459 | DECLARE_NAPI_STRUCT |
460 | DECLARE_NET_DEVICE_STATS | |
461 | }; | |
462 | ||
95252236 GFT |
463 | enum jme_flags_bits { |
464 | JME_FLAG_MSI = 1, | |
465 | JME_FLAG_SSET = 2, | |
95252236 GFT |
466 | JME_FLAG_POLL = 5, |
467 | JME_FLAG_SHUTDOWN = 6, | |
468 | }; | |
469 | ||
470 | #define TX_TIMEOUT (5 * HZ) | |
471 | #define JME_REG_LEN 0x500 | |
472 | #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216 | |
473 | ||
474 | static inline struct jme_adapter* | |
475 | jme_napi_priv(struct napi_struct *napi) | |
476 | { | |
477 | struct jme_adapter *jme; | |
478 | jme = container_of(napi, struct jme_adapter, napi); | |
479 | return jme; | |
480 | } | |
481 | ||
482 | /* | |
483 | * MMaped I/O Resters | |
484 | */ | |
485 | enum jme_iomap_offsets { | |
486 | JME_MAC = 0x0000, | |
487 | JME_PHY = 0x0400, | |
488 | JME_MISC = 0x0800, | |
489 | JME_RSS = 0x0C00, | |
490 | }; | |
491 | ||
492 | enum jme_iomap_lens { | |
493 | JME_MAC_LEN = 0x80, | |
494 | JME_PHY_LEN = 0x58, | |
495 | JME_MISC_LEN = 0x98, | |
496 | JME_RSS_LEN = 0xFF, | |
497 | }; | |
498 | ||
499 | enum jme_iomap_regs { | |
500 | JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */ | |
501 | JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */ | |
502 | JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */ | |
503 | JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */ | |
504 | JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */ | |
505 | JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */ | |
506 | JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */ | |
507 | JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */ | |
508 | ||
509 | JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */ | |
510 | JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */ | |
511 | JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */ | |
512 | JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */ | |
513 | JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */ | |
514 | JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */ | |
515 | JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */ | |
516 | JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */ | |
517 | JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */ | |
518 | JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */ | |
519 | JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */ | |
520 | JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */ | |
521 | ||
522 | JME_SMI = JME_MAC | 0x50, /* Station Management Interface */ | |
523 | JME_GHC = JME_MAC | 0x54, /* Global Host Control */ | |
524 | JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */ | |
525 | ||
526 | ||
4872b11f | 527 | JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */ |
95252236 GFT |
528 | JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */ |
529 | JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */ | |
530 | JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */ | |
531 | JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */ | |
532 | ||
533 | ||
534 | JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */ | |
535 | JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */ | |
536 | JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */ | |
537 | JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */ | |
538 | JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */ | |
539 | JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */ | |
540 | JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */ | |
541 | JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */ | |
542 | JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */ | |
543 | JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */ | |
544 | JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */ | |
545 | JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */ | |
546 | JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */ | |
547 | JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */ | |
548 | JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */ | |
549 | JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */ | |
550 | }; | |
551 | ||
552 | /* | |
553 | * TX Control/Status Bits | |
554 | */ | |
555 | enum jme_txcs_bits { | |
556 | TXCS_QUEUE7S = 0x00008000, | |
557 | TXCS_QUEUE6S = 0x00004000, | |
558 | TXCS_QUEUE5S = 0x00002000, | |
559 | TXCS_QUEUE4S = 0x00001000, | |
560 | TXCS_QUEUE3S = 0x00000800, | |
561 | TXCS_QUEUE2S = 0x00000400, | |
562 | TXCS_QUEUE1S = 0x00000200, | |
563 | TXCS_QUEUE0S = 0x00000100, | |
564 | TXCS_FIFOTH = 0x000000C0, | |
565 | TXCS_DMASIZE = 0x00000030, | |
566 | TXCS_BURST = 0x00000004, | |
567 | TXCS_ENABLE = 0x00000001, | |
568 | }; | |
569 | ||
570 | enum jme_txcs_value { | |
571 | TXCS_FIFOTH_16QW = 0x000000C0, | |
572 | TXCS_FIFOTH_12QW = 0x00000080, | |
573 | TXCS_FIFOTH_8QW = 0x00000040, | |
574 | TXCS_FIFOTH_4QW = 0x00000000, | |
575 | ||
576 | TXCS_DMASIZE_64B = 0x00000000, | |
577 | TXCS_DMASIZE_128B = 0x00000010, | |
578 | TXCS_DMASIZE_256B = 0x00000020, | |
579 | TXCS_DMASIZE_512B = 0x00000030, | |
580 | ||
581 | TXCS_SELECT_QUEUE0 = 0x00000000, | |
582 | TXCS_SELECT_QUEUE1 = 0x00010000, | |
583 | TXCS_SELECT_QUEUE2 = 0x00020000, | |
584 | TXCS_SELECT_QUEUE3 = 0x00030000, | |
585 | TXCS_SELECT_QUEUE4 = 0x00040000, | |
586 | TXCS_SELECT_QUEUE5 = 0x00050000, | |
587 | TXCS_SELECT_QUEUE6 = 0x00060000, | |
588 | TXCS_SELECT_QUEUE7 = 0x00070000, | |
589 | ||
590 | TXCS_DEFAULT = TXCS_FIFOTH_4QW | | |
591 | TXCS_BURST, | |
592 | }; | |
593 | ||
594 | #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */ | |
595 | ||
596 | /* | |
597 | * TX MAC Control/Status Bits | |
598 | */ | |
599 | enum jme_txmcs_bit_masks { | |
600 | TXMCS_IFG2 = 0xC0000000, | |
601 | TXMCS_IFG1 = 0x30000000, | |
602 | TXMCS_TTHOLD = 0x00000300, | |
603 | TXMCS_FBURST = 0x00000080, | |
604 | TXMCS_CARRIEREXT = 0x00000040, | |
605 | TXMCS_DEFER = 0x00000020, | |
606 | TXMCS_BACKOFF = 0x00000010, | |
607 | TXMCS_CARRIERSENSE = 0x00000008, | |
608 | TXMCS_COLLISION = 0x00000004, | |
609 | TXMCS_CRC = 0x00000002, | |
610 | TXMCS_PADDING = 0x00000001, | |
611 | }; | |
612 | ||
613 | enum jme_txmcs_values { | |
614 | TXMCS_IFG2_6_4 = 0x00000000, | |
615 | TXMCS_IFG2_8_5 = 0x40000000, | |
616 | TXMCS_IFG2_10_6 = 0x80000000, | |
617 | TXMCS_IFG2_12_7 = 0xC0000000, | |
618 | ||
619 | TXMCS_IFG1_8_4 = 0x00000000, | |
620 | TXMCS_IFG1_12_6 = 0x10000000, | |
621 | TXMCS_IFG1_16_8 = 0x20000000, | |
622 | TXMCS_IFG1_20_10 = 0x30000000, | |
623 | ||
624 | TXMCS_TTHOLD_1_8 = 0x00000000, | |
625 | TXMCS_TTHOLD_1_4 = 0x00000100, | |
626 | TXMCS_TTHOLD_1_2 = 0x00000200, | |
627 | TXMCS_TTHOLD_FULL = 0x00000300, | |
628 | ||
629 | TXMCS_DEFAULT = TXMCS_IFG2_8_5 | | |
630 | TXMCS_IFG1_16_8 | | |
631 | TXMCS_TTHOLD_FULL | | |
632 | TXMCS_DEFER | | |
633 | TXMCS_CRC | | |
634 | TXMCS_PADDING, | |
635 | }; | |
636 | ||
637 | enum jme_txpfc_bits_masks { | |
638 | TXPFC_VLAN_TAG = 0xFFFF0000, | |
639 | TXPFC_VLAN_EN = 0x00008000, | |
640 | TXPFC_PF_EN = 0x00000001, | |
641 | }; | |
642 | ||
643 | enum jme_txtrhd_bits_masks { | |
644 | TXTRHD_TXPEN = 0x80000000, | |
645 | TXTRHD_TXP = 0x7FFFFF00, | |
646 | TXTRHD_TXREN = 0x00000080, | |
647 | TXTRHD_TXRL = 0x0000007F, | |
648 | }; | |
649 | ||
650 | enum jme_txtrhd_shifts { | |
651 | TXTRHD_TXP_SHIFT = 8, | |
652 | TXTRHD_TXRL_SHIFT = 0, | |
653 | }; | |
654 | ||
3903c023 GFT |
655 | enum jme_txtrhd_values { |
656 | TXTRHD_FULLDUPLEX = 0x00000000, | |
657 | TXTRHD_HALFDUPLEX = TXTRHD_TXPEN | | |
658 | ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) | | |
659 | TXTRHD_TXREN | | |
660 | ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL), | |
661 | }; | |
662 | ||
95252236 GFT |
663 | /* |
664 | * RX Control/Status Bits | |
665 | */ | |
666 | enum jme_rxcs_bit_masks { | |
667 | /* FIFO full threshold for transmitting Tx Pause Packet */ | |
668 | RXCS_FIFOTHTP = 0x30000000, | |
669 | /* FIFO threshold for processing next packet */ | |
670 | RXCS_FIFOTHNP = 0x0C000000, | |
671 | RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */ | |
672 | RXCS_QUEUESEL = 0x00030000, /* Queue selection */ | |
673 | RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */ | |
674 | RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */ | |
675 | RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */ | |
676 | RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */ | |
677 | RXCS_SHORT = 0x00000010, /* Enable receive short packet */ | |
678 | RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */ | |
679 | RXCS_QST = 0x00000004, /* Receive queue start */ | |
680 | RXCS_SUSPEND = 0x00000002, | |
681 | RXCS_ENABLE = 0x00000001, | |
682 | }; | |
683 | ||
684 | enum jme_rxcs_values { | |
685 | RXCS_FIFOTHTP_16T = 0x00000000, | |
686 | RXCS_FIFOTHTP_32T = 0x10000000, | |
687 | RXCS_FIFOTHTP_64T = 0x20000000, | |
688 | RXCS_FIFOTHTP_128T = 0x30000000, | |
689 | ||
690 | RXCS_FIFOTHNP_16QW = 0x00000000, | |
691 | RXCS_FIFOTHNP_32QW = 0x04000000, | |
692 | RXCS_FIFOTHNP_64QW = 0x08000000, | |
693 | RXCS_FIFOTHNP_128QW = 0x0C000000, | |
694 | ||
695 | RXCS_DMAREQSZ_16B = 0x00000000, | |
696 | RXCS_DMAREQSZ_32B = 0x01000000, | |
697 | RXCS_DMAREQSZ_64B = 0x02000000, | |
698 | RXCS_DMAREQSZ_128B = 0x03000000, | |
699 | ||
700 | RXCS_QUEUESEL_Q0 = 0x00000000, | |
701 | RXCS_QUEUESEL_Q1 = 0x00010000, | |
702 | RXCS_QUEUESEL_Q2 = 0x00020000, | |
703 | RXCS_QUEUESEL_Q3 = 0x00030000, | |
704 | ||
705 | RXCS_RETRYGAP_256ns = 0x00000000, | |
706 | RXCS_RETRYGAP_512ns = 0x00001000, | |
707 | RXCS_RETRYGAP_1024ns = 0x00002000, | |
708 | RXCS_RETRYGAP_2048ns = 0x00003000, | |
709 | RXCS_RETRYGAP_4096ns = 0x00004000, | |
710 | RXCS_RETRYGAP_8192ns = 0x00005000, | |
711 | RXCS_RETRYGAP_16384ns = 0x00006000, | |
712 | RXCS_RETRYGAP_32768ns = 0x00007000, | |
713 | ||
714 | RXCS_RETRYCNT_0 = 0x00000000, | |
715 | RXCS_RETRYCNT_4 = 0x00000100, | |
716 | RXCS_RETRYCNT_8 = 0x00000200, | |
717 | RXCS_RETRYCNT_12 = 0x00000300, | |
718 | RXCS_RETRYCNT_16 = 0x00000400, | |
719 | RXCS_RETRYCNT_20 = 0x00000500, | |
720 | RXCS_RETRYCNT_24 = 0x00000600, | |
721 | RXCS_RETRYCNT_28 = 0x00000700, | |
722 | RXCS_RETRYCNT_32 = 0x00000800, | |
723 | RXCS_RETRYCNT_36 = 0x00000900, | |
724 | RXCS_RETRYCNT_40 = 0x00000A00, | |
725 | RXCS_RETRYCNT_44 = 0x00000B00, | |
726 | RXCS_RETRYCNT_48 = 0x00000C00, | |
727 | RXCS_RETRYCNT_52 = 0x00000D00, | |
728 | RXCS_RETRYCNT_56 = 0x00000E00, | |
729 | RXCS_RETRYCNT_60 = 0x00000F00, | |
730 | ||
731 | RXCS_DEFAULT = RXCS_FIFOTHTP_128T | | |
ba9adbe6 | 732 | RXCS_FIFOTHNP_16QW | |
95252236 GFT |
733 | RXCS_DMAREQSZ_128B | |
734 | RXCS_RETRYGAP_256ns | | |
735 | RXCS_RETRYCNT_32, | |
736 | }; | |
737 | ||
738 | #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */ | |
739 | ||
740 | /* | |
741 | * RX MAC Control/Status Bits | |
742 | */ | |
743 | enum jme_rxmcs_bits { | |
744 | RXMCS_ALLFRAME = 0x00000800, | |
745 | RXMCS_BRDFRAME = 0x00000400, | |
746 | RXMCS_MULFRAME = 0x00000200, | |
747 | RXMCS_UNIFRAME = 0x00000100, | |
748 | RXMCS_ALLMULFRAME = 0x00000080, | |
749 | RXMCS_MULFILTERED = 0x00000040, | |
750 | RXMCS_RXCOLLDEC = 0x00000020, | |
751 | RXMCS_FLOWCTRL = 0x00000008, | |
752 | RXMCS_VTAGRM = 0x00000004, | |
753 | RXMCS_PREPAD = 0x00000002, | |
754 | RXMCS_CHECKSUM = 0x00000001, | |
755 | ||
756 | RXMCS_DEFAULT = RXMCS_VTAGRM | | |
757 | RXMCS_PREPAD | | |
758 | RXMCS_FLOWCTRL | | |
759 | RXMCS_CHECKSUM, | |
760 | }; | |
761 | ||
c4860ba2 AL |
762 | /* Extern PHY common register 2 */ |
763 | ||
764 | #define PHY_GAD_TEST_MODE_1 0x00002000 | |
765 | #define PHY_GAD_TEST_MODE_MSK 0x0000E000 | |
766 | #define JM_PHY_SPEC_REG_READ 0x00004000 | |
767 | #define JM_PHY_SPEC_REG_WRITE 0x00008000 | |
768 | #define PHY_CALIBRATION_DELAY 20 | |
769 | #define JM_PHY_SPEC_ADDR_REG 0x1E | |
770 | #define JM_PHY_SPEC_DATA_REG 0x1F | |
771 | ||
772 | #define JM_PHY_EXT_COMM_0_REG 0x30 | |
773 | #define JM_PHY_EXT_COMM_1_REG 0x31 | |
774 | #define JM_PHY_EXT_COMM_2_REG 0x32 | |
775 | #define JM_PHY_EXT_COMM_2_CALI_ENABLE 0x01 | |
776 | #define JM_PHY_EXT_COMM_2_CALI_MODE_0 0x02 | |
777 | #define JM_PHY_EXT_COMM_2_CALI_LATCH 0x10 | |
778 | #define PCI_PRIV_SHARE_NICCTRL 0xF5 | |
779 | #define JME_FLAG_PHYEA_ENABLE 0x2 | |
780 | ||
95252236 GFT |
781 | /* |
782 | * Wakeup Frame setup interface registers | |
783 | */ | |
784 | #define WAKEUP_FRAME_NR 8 | |
785 | #define WAKEUP_FRAME_MASK_DWNR 4 | |
786 | ||
787 | enum jme_wfoi_bit_masks { | |
788 | WFOI_MASK_SEL = 0x00000070, | |
789 | WFOI_CRC_SEL = 0x00000008, | |
790 | WFOI_FRAME_SEL = 0x00000007, | |
791 | }; | |
792 | ||
793 | enum jme_wfoi_shifts { | |
794 | WFOI_MASK_SHIFT = 4, | |
795 | }; | |
796 | ||
797 | /* | |
798 | * SMI Related definitions | |
799 | */ | |
800 | enum jme_smi_bit_mask { | |
801 | SMI_DATA_MASK = 0xFFFF0000, | |
802 | SMI_REG_ADDR_MASK = 0x0000F800, | |
803 | SMI_PHY_ADDR_MASK = 0x000007C0, | |
804 | SMI_OP_WRITE = 0x00000020, | |
805 | /* Set to 1, after req done it'll be cleared to 0 */ | |
806 | SMI_OP_REQ = 0x00000010, | |
807 | SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */ | |
808 | SMI_OP_MDOE = 0x00000004, /* Software Output Enable */ | |
809 | SMI_OP_MDC = 0x00000002, /* Software CLK Control */ | |
810 | SMI_OP_MDEN = 0x00000001, /* Software access Enable */ | |
811 | }; | |
812 | ||
813 | enum jme_smi_bit_shift { | |
814 | SMI_DATA_SHIFT = 16, | |
815 | SMI_REG_ADDR_SHIFT = 11, | |
816 | SMI_PHY_ADDR_SHIFT = 6, | |
817 | }; | |
818 | ||
819 | static inline u32 smi_reg_addr(int x) | |
820 | { | |
821 | return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK; | |
822 | } | |
823 | ||
824 | static inline u32 smi_phy_addr(int x) | |
825 | { | |
826 | return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK; | |
827 | } | |
828 | ||
829 | #define JME_PHY_TIMEOUT 100 /* 100 msec */ | |
830 | #define JME_PHY_REG_NR 32 | |
831 | ||
832 | /* | |
833 | * Global Host Control | |
834 | */ | |
835 | enum jme_ghc_bit_mask { | |
4f40bf46 | 836 | GHC_SWRST = 0x40000000, |
854a2e7c GFT |
837 | GHC_TO_CLK_SRC = 0x00C00000, |
838 | GHC_TXMAC_CLK_SRC = 0x00300000, | |
4f40bf46 | 839 | GHC_DPX = 0x00000040, |
840 | GHC_SPEED = 0x00000030, | |
841 | GHC_LINK_POLL = 0x00000001, | |
95252236 GFT |
842 | }; |
843 | ||
844 | enum jme_ghc_speed_val { | |
4f40bf46 | 845 | GHC_SPEED_10M = 0x00000010, |
846 | GHC_SPEED_100M = 0x00000020, | |
847 | GHC_SPEED_1000M = 0x00000030, | |
848 | }; | |
849 | ||
850 | enum jme_ghc_to_clk { | |
851 | GHC_TO_CLK_OFF = 0x00000000, | |
852 | GHC_TO_CLK_GPHY = 0x00400000, | |
853 | GHC_TO_CLK_PCIE = 0x00800000, | |
854 | GHC_TO_CLK_INVALID = 0x00C00000, | |
855 | }; | |
856 | ||
857 | enum jme_ghc_txmac_clk { | |
858 | GHC_TXMAC_CLK_OFF = 0x00000000, | |
859 | GHC_TXMAC_CLK_GPHY = 0x00100000, | |
860 | GHC_TXMAC_CLK_PCIE = 0x00200000, | |
861 | GHC_TXMAC_CLK_INVALID = 0x00300000, | |
95252236 GFT |
862 | }; |
863 | ||
864 | /* | |
865 | * Power management control and status register | |
866 | */ | |
867 | enum jme_pmcs_bit_masks { | |
bc057e03 | 868 | PMCS_STMASK = 0xFFFF0000, |
95252236 GFT |
869 | PMCS_WF7DET = 0x80000000, |
870 | PMCS_WF6DET = 0x40000000, | |
871 | PMCS_WF5DET = 0x20000000, | |
872 | PMCS_WF4DET = 0x10000000, | |
873 | PMCS_WF3DET = 0x08000000, | |
874 | PMCS_WF2DET = 0x04000000, | |
875 | PMCS_WF1DET = 0x02000000, | |
876 | PMCS_WF0DET = 0x01000000, | |
877 | PMCS_LFDET = 0x00040000, | |
878 | PMCS_LRDET = 0x00020000, | |
879 | PMCS_MFDET = 0x00010000, | |
bc057e03 | 880 | PMCS_ENMASK = 0x0000FFFF, |
95252236 GFT |
881 | PMCS_WF7EN = 0x00008000, |
882 | PMCS_WF6EN = 0x00004000, | |
883 | PMCS_WF5EN = 0x00002000, | |
884 | PMCS_WF4EN = 0x00001000, | |
885 | PMCS_WF3EN = 0x00000800, | |
886 | PMCS_WF2EN = 0x00000400, | |
887 | PMCS_WF1EN = 0x00000200, | |
888 | PMCS_WF0EN = 0x00000100, | |
889 | PMCS_LFEN = 0x00000004, | |
890 | PMCS_LREN = 0x00000002, | |
891 | PMCS_MFEN = 0x00000001, | |
892 | }; | |
893 | ||
4872b11f GFT |
894 | /* |
895 | * New PHY Power Control Register | |
896 | */ | |
897 | enum jme_phy_pwr_bit_masks { | |
898 | PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */ | |
899 | PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */ | |
900 | PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */ | |
901 | PHY_PWR_CLKSEL = 0x08000000, /* | |
902 | * XTL_OUT Clock select | |
903 | * (an internal free-running clock) | |
904 | * 0: xtl_out = phy_giga.A_XTL25_O | |
905 | * 1: xtl_out = phy_giga.PD_OSC | |
906 | */ | |
907 | }; | |
908 | ||
95252236 GFT |
909 | /* |
910 | * Giga PHY Status Registers | |
911 | */ | |
912 | enum jme_phy_link_bit_mask { | |
913 | PHY_LINK_SPEED_MASK = 0x0000C000, | |
914 | PHY_LINK_DUPLEX = 0x00002000, | |
915 | PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800, | |
916 | PHY_LINK_UP = 0x00000400, | |
917 | PHY_LINK_AUTONEG_COMPLETE = 0x00000200, | |
918 | PHY_LINK_MDI_STAT = 0x00000040, | |
919 | }; | |
920 | ||
921 | enum jme_phy_link_speed_val { | |
922 | PHY_LINK_SPEED_10M = 0x00000000, | |
923 | PHY_LINK_SPEED_100M = 0x00004000, | |
924 | PHY_LINK_SPEED_1000M = 0x00008000, | |
925 | }; | |
926 | ||
927 | #define JME_SPDRSV_TIMEOUT 500 /* 500 us */ | |
928 | ||
929 | /* | |
930 | * SMB Control and Status | |
931 | */ | |
932 | enum jme_smbcsr_bit_mask { | |
933 | SMBCSR_CNACK = 0x00020000, | |
934 | SMBCSR_RELOAD = 0x00010000, | |
935 | SMBCSR_EEPROMD = 0x00000020, | |
936 | SMBCSR_INITDONE = 0x00000010, | |
937 | SMBCSR_BUSY = 0x0000000F, | |
938 | }; | |
939 | ||
940 | enum jme_smbintf_bit_mask { | |
941 | SMBINTF_HWDATR = 0xFF000000, | |
942 | SMBINTF_HWDATW = 0x00FF0000, | |
943 | SMBINTF_HWADDR = 0x0000FF00, | |
944 | SMBINTF_HWRWN = 0x00000020, | |
945 | SMBINTF_HWCMD = 0x00000010, | |
946 | SMBINTF_FASTM = 0x00000008, | |
947 | SMBINTF_GPIOSCL = 0x00000004, | |
948 | SMBINTF_GPIOSDA = 0x00000002, | |
949 | SMBINTF_GPIOEN = 0x00000001, | |
950 | }; | |
951 | ||
952 | enum jme_smbintf_vals { | |
953 | SMBINTF_HWRWN_READ = 0x00000020, | |
954 | SMBINTF_HWRWN_WRITE = 0x00000000, | |
955 | }; | |
956 | ||
957 | enum jme_smbintf_shifts { | |
958 | SMBINTF_HWDATR_SHIFT = 24, | |
959 | SMBINTF_HWDATW_SHIFT = 16, | |
960 | SMBINTF_HWADDR_SHIFT = 8, | |
961 | }; | |
962 | ||
963 | #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */ | |
964 | #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */ | |
965 | #define JME_SMB_LEN 256 | |
966 | #define JME_EEPROM_MAGIC 0x250 | |
967 | ||
968 | /* | |
969 | * Timer Control/Status Register | |
970 | */ | |
971 | enum jme_tmcsr_bit_masks { | |
972 | TMCSR_SWIT = 0x80000000, | |
973 | TMCSR_EN = 0x01000000, | |
974 | TMCSR_CNT = 0x00FFFFFF, | |
975 | }; | |
976 | ||
977 | /* | |
978 | * General Purpose REG-0 | |
979 | */ | |
980 | enum jme_gpreg0_masks { | |
981 | GPREG0_DISSH = 0xFF000000, | |
982 | GPREG0_PCIRLMT = 0x00300000, | |
983 | GPREG0_PCCNOMUTCLR = 0x00040000, | |
984 | GPREG0_LNKINTPOLL = 0x00001000, | |
985 | GPREG0_PCCTMR = 0x00000300, | |
986 | GPREG0_PHYADDR = 0x0000001F, | |
987 | }; | |
988 | ||
989 | enum jme_gpreg0_vals { | |
990 | GPREG0_DISSH_DW7 = 0x80000000, | |
991 | GPREG0_DISSH_DW6 = 0x40000000, | |
992 | GPREG0_DISSH_DW5 = 0x20000000, | |
993 | GPREG0_DISSH_DW4 = 0x10000000, | |
994 | GPREG0_DISSH_DW3 = 0x08000000, | |
995 | GPREG0_DISSH_DW2 = 0x04000000, | |
996 | GPREG0_DISSH_DW1 = 0x02000000, | |
997 | GPREG0_DISSH_DW0 = 0x01000000, | |
998 | GPREG0_DISSH_ALL = 0xFF000000, | |
999 | ||
1000 | GPREG0_PCIRLMT_8 = 0x00000000, | |
1001 | GPREG0_PCIRLMT_6 = 0x00100000, | |
1002 | GPREG0_PCIRLMT_5 = 0x00200000, | |
1003 | GPREG0_PCIRLMT_4 = 0x00300000, | |
1004 | ||
1005 | GPREG0_PCCTMR_16ns = 0x00000000, | |
1006 | GPREG0_PCCTMR_256ns = 0x00000100, | |
1007 | GPREG0_PCCTMR_1us = 0x00000200, | |
1008 | GPREG0_PCCTMR_1ms = 0x00000300, | |
1009 | ||
1010 | GPREG0_PHYADDR_1 = 0x00000001, | |
1011 | ||
1012 | GPREG0_DEFAULT = GPREG0_PCIRLMT_4 | | |
1013 | GPREG0_PCCTMR_1us | | |
1014 | GPREG0_PHYADDR_1, | |
1015 | }; | |
1016 | ||
a821ebe5 GFT |
1017 | /* |
1018 | * General Purpose REG-1 | |
a821ebe5 | 1019 | */ |
854a2e7c GFT |
1020 | enum jme_gpreg1_bit_masks { |
1021 | GPREG1_RXCLKOFF = 0x04000000, | |
1022 | GPREG1_PCREQN = 0x00020000, | |
1023 | GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */ | |
1024 | GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */ | |
a821ebe5 GFT |
1025 | GPREG1_INTRDELAYUNIT = 0x00000018, |
1026 | GPREG1_INTRDELAYENABLE = 0x00000007, | |
1027 | }; | |
1028 | ||
1029 | enum jme_gpreg1_vals { | |
a821ebe5 GFT |
1030 | GPREG1_INTDLYUNIT_16NS = 0x00000000, |
1031 | GPREG1_INTDLYUNIT_256NS = 0x00000008, | |
1032 | GPREG1_INTDLYUNIT_1US = 0x00000010, | |
1033 | GPREG1_INTDLYUNIT_16US = 0x00000018, | |
1034 | ||
1035 | GPREG1_INTDLYEN_1U = 0x00000001, | |
1036 | GPREG1_INTDLYEN_2U = 0x00000002, | |
1037 | GPREG1_INTDLYEN_3U = 0x00000003, | |
1038 | GPREG1_INTDLYEN_4U = 0x00000004, | |
1039 | GPREG1_INTDLYEN_5U = 0x00000005, | |
1040 | GPREG1_INTDLYEN_6U = 0x00000006, | |
1041 | GPREG1_INTDLYEN_7U = 0x00000007, | |
1042 | ||
854a2e7c | 1043 | GPREG1_DEFAULT = GPREG1_PCREQN, |
a821ebe5 GFT |
1044 | }; |
1045 | ||
95252236 GFT |
1046 | /* |
1047 | * Interrupt Status Bits | |
1048 | */ | |
1049 | enum jme_interrupt_bits { | |
1050 | INTR_SWINTR = 0x80000000, | |
1051 | INTR_TMINTR = 0x40000000, | |
1052 | INTR_LINKCH = 0x20000000, | |
1053 | INTR_PAUSERCV = 0x10000000, | |
1054 | INTR_MAGICRCV = 0x08000000, | |
1055 | INTR_WAKERCV = 0x04000000, | |
1056 | INTR_PCCRX0TO = 0x02000000, | |
1057 | INTR_PCCRX1TO = 0x01000000, | |
1058 | INTR_PCCRX2TO = 0x00800000, | |
1059 | INTR_PCCRX3TO = 0x00400000, | |
1060 | INTR_PCCTXTO = 0x00200000, | |
1061 | INTR_PCCRX0 = 0x00100000, | |
1062 | INTR_PCCRX1 = 0x00080000, | |
1063 | INTR_PCCRX2 = 0x00040000, | |
1064 | INTR_PCCRX3 = 0x00020000, | |
1065 | INTR_PCCTX = 0x00010000, | |
1066 | INTR_RX3EMP = 0x00008000, | |
1067 | INTR_RX2EMP = 0x00004000, | |
1068 | INTR_RX1EMP = 0x00002000, | |
1069 | INTR_RX0EMP = 0x00001000, | |
1070 | INTR_RX3 = 0x00000800, | |
1071 | INTR_RX2 = 0x00000400, | |
1072 | INTR_RX1 = 0x00000200, | |
1073 | INTR_RX0 = 0x00000100, | |
1074 | INTR_TX7 = 0x00000080, | |
1075 | INTR_TX6 = 0x00000040, | |
1076 | INTR_TX5 = 0x00000020, | |
1077 | INTR_TX4 = 0x00000010, | |
1078 | INTR_TX3 = 0x00000008, | |
1079 | INTR_TX2 = 0x00000004, | |
1080 | INTR_TX1 = 0x00000002, | |
1081 | INTR_TX0 = 0x00000001, | |
1082 | }; | |
1083 | ||
1084 | static const u32 INTR_ENABLE = INTR_SWINTR | | |
1085 | INTR_TMINTR | | |
1086 | INTR_LINKCH | | |
1087 | INTR_PCCRX0TO | | |
1088 | INTR_PCCRX0 | | |
1089 | INTR_PCCTXTO | | |
1090 | INTR_PCCTX | | |
1091 | INTR_RX0EMP; | |
1092 | ||
1093 | /* | |
1094 | * PCC Control Registers | |
1095 | */ | |
1096 | enum jme_pccrx_masks { | |
1097 | PCCRXTO_MASK = 0xFFFF0000, | |
1098 | PCCRX_MASK = 0x0000FF00, | |
1099 | }; | |
1100 | ||
1101 | enum jme_pcctx_masks { | |
1102 | PCCTXTO_MASK = 0xFFFF0000, | |
1103 | PCCTX_MASK = 0x0000FF00, | |
1104 | PCCTX_QS_MASK = 0x000000FF, | |
1105 | }; | |
1106 | ||
1107 | enum jme_pccrx_shifts { | |
1108 | PCCRXTO_SHIFT = 16, | |
1109 | PCCRX_SHIFT = 8, | |
1110 | }; | |
1111 | ||
1112 | enum jme_pcctx_shifts { | |
1113 | PCCTXTO_SHIFT = 16, | |
1114 | PCCTX_SHIFT = 8, | |
1115 | }; | |
1116 | ||
1117 | enum jme_pcctx_bits { | |
1118 | PCCTXQ0_EN = 0x00000001, | |
1119 | PCCTXQ1_EN = 0x00000002, | |
1120 | PCCTXQ2_EN = 0x00000004, | |
1121 | PCCTXQ3_EN = 0x00000008, | |
1122 | PCCTXQ4_EN = 0x00000010, | |
1123 | PCCTXQ5_EN = 0x00000020, | |
1124 | PCCTXQ6_EN = 0x00000040, | |
1125 | PCCTXQ7_EN = 0x00000080, | |
1126 | }; | |
1127 | ||
1128 | /* | |
1129 | * Chip Mode Register | |
1130 | */ | |
1131 | enum jme_chipmode_bit_masks { | |
1132 | CM_FPGAVER_MASK = 0xFFFF0000, | |
1133 | CM_CHIPREV_MASK = 0x0000FF00, | |
1134 | CM_CHIPMODE_MASK = 0x0000000F, | |
1135 | }; | |
1136 | ||
1137 | enum jme_chipmode_shifts { | |
1138 | CM_FPGAVER_SHIFT = 16, | |
1139 | CM_CHIPREV_SHIFT = 8, | |
1140 | }; | |
1141 | ||
95252236 GFT |
1142 | /* |
1143 | * Aggressive Power Mode Control | |
1144 | */ | |
1145 | enum jme_apmc_bits { | |
1146 | JME_APMC_PCIE_SD_EN = 0x40000000, | |
1147 | JME_APMC_PSEUDO_HP_EN = 0x20000000, | |
1148 | JME_APMC_EPIEN = 0x04000000, | |
1149 | JME_APMC_EPIEN_CTRL = 0x03000000, | |
1150 | }; | |
1151 | ||
1152 | enum jme_apmc_values { | |
1153 | JME_APMC_EPIEN_CTRL_EN = 0x02000000, | |
1154 | JME_APMC_EPIEN_CTRL_DIS = 0x01000000, | |
1155 | }; | |
1156 | ||
1157 | #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000) | |
1158 | ||
1159 | #ifdef REG_DEBUG | |
1160 | static char *MAC_REG_NAME[] = { | |
1161 | "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC", | |
1162 | "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD", | |
1163 | "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC", | |
1164 | "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI", | |
1165 | "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI", | |
1166 | "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN", | |
1167 | "JME_PMCS"}; | |
1168 | ||
1169 | static char *PE_REG_NAME[] = { | |
1170 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1171 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1172 | "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN", | |
1173 | "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1174 | "JME_SMBCSR", "JME_SMBINTF"}; | |
1175 | ||
1176 | static char *MISC_REG_NAME[] = { | |
1177 | "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1", | |
1178 | "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC", | |
1179 | "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3", | |
1180 | "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO", | |
1181 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1182 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1183 | "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN", | |
1184 | "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC", | |
1185 | "JME_PCCSRX0"}; | |
1186 | ||
1187 | static inline void reg_dbg(const struct jme_adapter *jme, | |
1188 | const char *msg, u32 val, u32 reg) | |
1189 | { | |
1190 | const char *regname; | |
1191 | switch (reg & 0xF00) { | |
1192 | case 0x000: | |
1193 | regname = MAC_REG_NAME[(reg & 0xFF) >> 2]; | |
1194 | break; | |
1195 | case 0x400: | |
1196 | regname = PE_REG_NAME[(reg & 0xFF) >> 2]; | |
1197 | break; | |
1198 | case 0x800: | |
1199 | regname = MISC_REG_NAME[(reg & 0xFF) >> 2]; | |
1200 | break; | |
1201 | default: | |
1202 | regname = PE_REG_NAME[0]; | |
1203 | } | |
1204 | printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name, | |
1205 | msg, val, regname); | |
1206 | } | |
1207 | #else | |
1208 | static inline void reg_dbg(const struct jme_adapter *jme, | |
1209 | const char *msg, u32 val, u32 reg) {} | |
1210 | #endif | |
1211 | ||
1212 | /* | |
1213 | * Read/Write MMaped I/O Registers | |
1214 | */ | |
1215 | static inline u32 jread32(struct jme_adapter *jme, u32 reg) | |
1216 | { | |
1217 | return readl(jme->regs + reg); | |
1218 | } | |
1219 | ||
1220 | static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val) | |
1221 | { | |
1222 | reg_dbg(jme, "REG WRITE", val, reg); | |
1223 | writel(val, jme->regs + reg); | |
1224 | reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); | |
1225 | } | |
1226 | ||
1227 | static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val) | |
1228 | { | |
1229 | /* | |
1230 | * Read after write should cause flush | |
1231 | */ | |
1232 | reg_dbg(jme, "REG WRITE FLUSH", val, reg); | |
1233 | writel(val, jme->regs + reg); | |
1234 | readl(jme->regs + reg); | |
1235 | reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg); | |
1236 | } | |
1237 | ||
1238 | /* | |
1239 | * PHY Regs | |
1240 | */ | |
1241 | enum jme_phy_reg17_bit_masks { | |
1242 | PREG17_SPEED = 0xC000, | |
1243 | PREG17_DUPLEX = 0x2000, | |
1244 | PREG17_SPDRSV = 0x0800, | |
1245 | PREG17_LNKUP = 0x0400, | |
1246 | PREG17_MDI = 0x0040, | |
1247 | }; | |
1248 | ||
1249 | enum jme_phy_reg17_vals { | |
1250 | PREG17_SPEED_10M = 0x0000, | |
1251 | PREG17_SPEED_100M = 0x4000, | |
1252 | PREG17_SPEED_1000M = 0x8000, | |
1253 | }; | |
1254 | ||
1255 | #define BMSR_ANCOMP 0x0020 | |
1256 | ||
1257 | /* | |
1258 | * Workaround | |
1259 | */ | |
19d96017 | 1260 | static inline int is_buggy250(unsigned short device, u8 chiprev) |
95252236 GFT |
1261 | { |
1262 | return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11; | |
1263 | } | |
1264 | ||
4872b11f GFT |
1265 | static inline int new_phy_power_ctrl(u8 chip_main_rev) |
1266 | { | |
1267 | return chip_main_rev >= 5; | |
1268 | } | |
1269 | ||
95252236 GFT |
1270 | /* |
1271 | * Function prototypes | |
1272 | */ | |
1273 | static int jme_set_settings(struct net_device *netdev, | |
1274 | struct ethtool_cmd *ecmd); | |
8b53abae | 1275 | static void jme_set_unicastaddr(struct net_device *netdev); |
95252236 GFT |
1276 | static void jme_set_multi(struct net_device *netdev); |
1277 | ||
1278 | #endif |