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ef11291b FF |
1 | /* |
2 | * Driver for the IDT RC32434 (Korina) on-chip ethernet controller. | |
3 | * | |
4 | * Copyright 2004 IDT Inc. (rischelp@idt.com) | |
5 | * Copyright 2006 Felix Fietkau <nbd@openwrt.org> | |
6 | * Copyright 2008 Florian Fainelli <florian@openwrt.org> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
14 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
15 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
16 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
17 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
18 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
19 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
20 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
21 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
22 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
23 | * | |
24 | * You should have received a copy of the GNU General Public License along | |
25 | * with this program; if not, write to the Free Software Foundation, Inc., | |
26 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
27 | * | |
28 | * Writing to a DMA status register: | |
29 | * | |
30 | * When writing to the status register, you should mask the bit you have | |
31 | * been testing the status register with. Both Tx and Rx DMA registers | |
32 | * should stick to this procedure. | |
33 | */ | |
34 | ||
35 | #include <linux/module.h> | |
36 | #include <linux/kernel.h> | |
37 | #include <linux/moduleparam.h> | |
38 | #include <linux/sched.h> | |
39 | #include <linux/ctype.h> | |
40 | #include <linux/types.h> | |
41 | #include <linux/interrupt.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/ioport.h> | |
44 | #include <linux/in.h> | |
45 | #include <linux/slab.h> | |
46 | #include <linux/string.h> | |
47 | #include <linux/delay.h> | |
48 | #include <linux/netdevice.h> | |
49 | #include <linux/etherdevice.h> | |
50 | #include <linux/skbuff.h> | |
51 | #include <linux/errno.h> | |
52 | #include <linux/platform_device.h> | |
53 | #include <linux/mii.h> | |
54 | #include <linux/ethtool.h> | |
55 | #include <linux/crc32.h> | |
56 | ||
57 | #include <asm/bootinfo.h> | |
ef11291b FF |
58 | #include <asm/bitops.h> |
59 | #include <asm/pgtable.h> | |
ef11291b FF |
60 | #include <asm/io.h> |
61 | #include <asm/dma.h> | |
62 | ||
63 | #include <asm/mach-rc32434/rb.h> | |
64 | #include <asm/mach-rc32434/rc32434.h> | |
65 | #include <asm/mach-rc32434/eth.h> | |
66 | #include <asm/mach-rc32434/dma_v.h> | |
67 | ||
68 | #define DRV_NAME "korina" | |
69 | #define DRV_VERSION "0.10" | |
70 | #define DRV_RELDATE "04Mar2008" | |
71 | ||
72 | #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \ | |
73 | ((dev)->dev_addr[1])) | |
74 | #define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \ | |
75 | ((dev)->dev_addr[3] << 16) | \ | |
76 | ((dev)->dev_addr[4] << 8) | \ | |
77 | ((dev)->dev_addr[5])) | |
78 | ||
79 | #define MII_CLOCK 1250000 /* no more than 2.5MHz */ | |
80 | ||
81 | /* the following must be powers of two */ | |
82 | #define KORINA_NUM_RDS 64 /* number of receive descriptors */ | |
83 | #define KORINA_NUM_TDS 64 /* number of transmit descriptors */ | |
84 | ||
a13b2782 PS |
85 | /* KORINA_RBSIZE is the hardware's default maximum receive |
86 | * frame size in bytes. Having this hardcoded means that there | |
87 | * is no support for MTU sizes greater than 1500. */ | |
88 | #define KORINA_RBSIZE 1536 /* size of one resource buffer = Ether MTU */ | |
ef11291b FF |
89 | #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1) |
90 | #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1) | |
91 | #define RD_RING_SIZE (KORINA_NUM_RDS * sizeof(struct dma_desc)) | |
92 | #define TD_RING_SIZE (KORINA_NUM_TDS * sizeof(struct dma_desc)) | |
93 | ||
94 | #define TX_TIMEOUT (6000 * HZ / 1000) | |
95 | ||
96 | enum chain_status { desc_filled, desc_empty }; | |
97 | #define IS_DMA_FINISHED(X) (((X) & (DMA_DESC_FINI)) != 0) | |
98 | #define IS_DMA_DONE(X) (((X) & (DMA_DESC_DONE)) != 0) | |
99 | #define RCVPKT_LENGTH(X) (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT) | |
100 | ||
101 | /* Information that need to be kept for each board. */ | |
102 | struct korina_private { | |
103 | struct eth_regs *eth_regs; | |
104 | struct dma_reg *rx_dma_regs; | |
105 | struct dma_reg *tx_dma_regs; | |
106 | struct dma_desc *td_ring; /* transmit descriptor ring */ | |
107 | struct dma_desc *rd_ring; /* receive descriptor ring */ | |
108 | ||
109 | struct sk_buff *tx_skb[KORINA_NUM_TDS]; | |
110 | struct sk_buff *rx_skb[KORINA_NUM_RDS]; | |
111 | ||
112 | int rx_next_done; | |
113 | int rx_chain_head; | |
114 | int rx_chain_tail; | |
115 | enum chain_status rx_chain_status; | |
116 | ||
117 | int tx_next_done; | |
118 | int tx_chain_head; | |
119 | int tx_chain_tail; | |
120 | enum chain_status tx_chain_status; | |
121 | int tx_count; | |
122 | int tx_full; | |
123 | ||
124 | int rx_irq; | |
125 | int tx_irq; | |
126 | int ovr_irq; | |
127 | int und_irq; | |
128 | ||
129 | spinlock_t lock; /* NIC xmit lock */ | |
130 | ||
131 | int dma_halt_cnt; | |
132 | int dma_run_cnt; | |
133 | struct napi_struct napi; | |
4d5ef9f0 | 134 | struct timer_list media_check_timer; |
ef11291b | 135 | struct mii_if_info mii_if; |
ceb3d239 | 136 | struct work_struct restart_task; |
ef11291b FF |
137 | struct net_device *dev; |
138 | int phy_addr; | |
139 | }; | |
140 | ||
141 | extern unsigned int idt_cpu_freq; | |
142 | ||
143 | static inline void korina_start_dma(struct dma_reg *ch, u32 dma_addr) | |
144 | { | |
145 | writel(0, &ch->dmandptr); | |
146 | writel(dma_addr, &ch->dmadptr); | |
147 | } | |
148 | ||
149 | static inline void korina_abort_dma(struct net_device *dev, | |
150 | struct dma_reg *ch) | |
151 | { | |
152 | if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) { | |
153 | writel(0x10, &ch->dmac); | |
154 | ||
155 | while (!(readl(&ch->dmas) & DMA_STAT_HALT)) | |
156 | dev->trans_start = jiffies; | |
157 | ||
158 | writel(0, &ch->dmas); | |
159 | } | |
160 | ||
161 | writel(0, &ch->dmadptr); | |
162 | writel(0, &ch->dmandptr); | |
163 | } | |
164 | ||
165 | static inline void korina_chain_dma(struct dma_reg *ch, u32 dma_addr) | |
166 | { | |
167 | writel(dma_addr, &ch->dmandptr); | |
168 | } | |
169 | ||
170 | static void korina_abort_tx(struct net_device *dev) | |
171 | { | |
172 | struct korina_private *lp = netdev_priv(dev); | |
173 | ||
174 | korina_abort_dma(dev, lp->tx_dma_regs); | |
175 | } | |
176 | ||
177 | static void korina_abort_rx(struct net_device *dev) | |
178 | { | |
179 | struct korina_private *lp = netdev_priv(dev); | |
180 | ||
181 | korina_abort_dma(dev, lp->rx_dma_regs); | |
182 | } | |
183 | ||
184 | static void korina_start_rx(struct korina_private *lp, | |
185 | struct dma_desc *rd) | |
186 | { | |
187 | korina_start_dma(lp->rx_dma_regs, CPHYSADDR(rd)); | |
188 | } | |
189 | ||
190 | static void korina_chain_rx(struct korina_private *lp, | |
191 | struct dma_desc *rd) | |
192 | { | |
193 | korina_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd)); | |
194 | } | |
195 | ||
196 | /* transmit packet */ | |
197 | static int korina_send_packet(struct sk_buff *skb, struct net_device *dev) | |
198 | { | |
199 | struct korina_private *lp = netdev_priv(dev); | |
200 | unsigned long flags; | |
201 | u32 length; | |
97bc477c | 202 | u32 chain_prev, chain_next; |
ef11291b FF |
203 | struct dma_desc *td; |
204 | ||
205 | spin_lock_irqsave(&lp->lock, flags); | |
206 | ||
207 | td = &lp->td_ring[lp->tx_chain_tail]; | |
208 | ||
209 | /* stop queue when full, drop pkts if queue already full */ | |
210 | if (lp->tx_count >= (KORINA_NUM_TDS - 2)) { | |
211 | lp->tx_full = 1; | |
212 | ||
213 | if (lp->tx_count == (KORINA_NUM_TDS - 2)) | |
214 | netif_stop_queue(dev); | |
215 | else { | |
216 | dev->stats.tx_dropped++; | |
217 | dev_kfree_skb_any(skb); | |
218 | spin_unlock_irqrestore(&lp->lock, flags); | |
219 | ||
220 | return NETDEV_TX_BUSY; | |
221 | } | |
222 | } | |
223 | ||
224 | lp->tx_count++; | |
225 | ||
226 | lp->tx_skb[lp->tx_chain_tail] = skb; | |
227 | ||
228 | length = skb->len; | |
229 | dma_cache_wback((u32)skb->data, skb->len); | |
230 | ||
231 | /* Setup the transmit descriptor. */ | |
232 | dma_cache_inv((u32) td, sizeof(*td)); | |
233 | td->ca = CPHYSADDR(skb->data); | |
97bc477c PS |
234 | chain_prev = (lp->tx_chain_tail - 1) & KORINA_TDS_MASK; |
235 | chain_next = (lp->tx_chain_tail + 1) & KORINA_TDS_MASK; | |
ef11291b FF |
236 | |
237 | if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) { | |
238 | if (lp->tx_chain_status == desc_empty) { | |
239 | /* Update tail */ | |
240 | td->control = DMA_COUNT(length) | | |
241 | DMA_DESC_COF | DMA_DESC_IOF; | |
242 | /* Move tail */ | |
97bc477c | 243 | lp->tx_chain_tail = chain_next; |
ef11291b FF |
244 | /* Write to NDPTR */ |
245 | writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), | |
246 | &lp->tx_dma_regs->dmandptr); | |
247 | /* Move head to tail */ | |
248 | lp->tx_chain_head = lp->tx_chain_tail; | |
249 | } else { | |
250 | /* Update tail */ | |
251 | td->control = DMA_COUNT(length) | | |
252 | DMA_DESC_COF | DMA_DESC_IOF; | |
253 | /* Link to prev */ | |
97bc477c | 254 | lp->td_ring[chain_prev].control &= |
ef11291b FF |
255 | ~DMA_DESC_COF; |
256 | /* Link to prev */ | |
97bc477c | 257 | lp->td_ring[chain_prev].link = CPHYSADDR(td); |
ef11291b | 258 | /* Move tail */ |
97bc477c | 259 | lp->tx_chain_tail = chain_next; |
ef11291b FF |
260 | /* Write to NDPTR */ |
261 | writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), | |
262 | &(lp->tx_dma_regs->dmandptr)); | |
263 | /* Move head to tail */ | |
264 | lp->tx_chain_head = lp->tx_chain_tail; | |
265 | lp->tx_chain_status = desc_empty; | |
266 | } | |
267 | } else { | |
268 | if (lp->tx_chain_status == desc_empty) { | |
269 | /* Update tail */ | |
270 | td->control = DMA_COUNT(length) | | |
271 | DMA_DESC_COF | DMA_DESC_IOF; | |
272 | /* Move tail */ | |
97bc477c | 273 | lp->tx_chain_tail = chain_next; |
ef11291b | 274 | lp->tx_chain_status = desc_filled; |
ef11291b FF |
275 | } else { |
276 | /* Update tail */ | |
277 | td->control = DMA_COUNT(length) | | |
278 | DMA_DESC_COF | DMA_DESC_IOF; | |
97bc477c | 279 | lp->td_ring[chain_prev].control &= |
ef11291b | 280 | ~DMA_DESC_COF; |
97bc477c PS |
281 | lp->td_ring[chain_prev].link = CPHYSADDR(td); |
282 | lp->tx_chain_tail = chain_next; | |
ef11291b FF |
283 | } |
284 | } | |
285 | dma_cache_wback((u32) td, sizeof(*td)); | |
286 | ||
287 | dev->trans_start = jiffies; | |
288 | spin_unlock_irqrestore(&lp->lock, flags); | |
289 | ||
290 | return NETDEV_TX_OK; | |
291 | } | |
292 | ||
293 | static int mdio_read(struct net_device *dev, int mii_id, int reg) | |
294 | { | |
295 | struct korina_private *lp = netdev_priv(dev); | |
296 | int ret; | |
297 | ||
298 | mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8); | |
299 | ||
300 | writel(0, &lp->eth_regs->miimcfg); | |
301 | writel(0, &lp->eth_regs->miimcmd); | |
302 | writel(mii_id | reg, &lp->eth_regs->miimaddr); | |
303 | writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); | |
304 | ||
305 | ret = (int)(readl(&lp->eth_regs->miimrdd)); | |
306 | return ret; | |
307 | } | |
308 | ||
309 | static void mdio_write(struct net_device *dev, int mii_id, int reg, int val) | |
310 | { | |
311 | struct korina_private *lp = netdev_priv(dev); | |
312 | ||
313 | mii_id = ((lp->rx_irq == 0x2c ? 1 : 0) << 8); | |
314 | ||
315 | writel(0, &lp->eth_regs->miimcfg); | |
316 | writel(1, &lp->eth_regs->miimcmd); | |
317 | writel(mii_id | reg, &lp->eth_regs->miimaddr); | |
318 | writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); | |
319 | writel(val, &lp->eth_regs->miimwtd); | |
320 | } | |
321 | ||
322 | /* Ethernet Rx DMA interrupt */ | |
323 | static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id) | |
324 | { | |
325 | struct net_device *dev = dev_id; | |
326 | struct korina_private *lp = netdev_priv(dev); | |
327 | u32 dmas, dmasm; | |
328 | irqreturn_t retval; | |
329 | ||
330 | dmas = readl(&lp->rx_dma_regs->dmas); | |
331 | if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) { | |
ef11291b FF |
332 | dmasm = readl(&lp->rx_dma_regs->dmasm); |
333 | writel(dmasm | (DMA_STAT_DONE | | |
334 | DMA_STAT_HALT | DMA_STAT_ERR), | |
335 | &lp->rx_dma_regs->dmasm); | |
336 | ||
288379f0 | 337 | napi_schedule(&lp->napi); |
60d3f982 | 338 | |
ef11291b | 339 | if (dmas & DMA_STAT_ERR) |
f16aea4d | 340 | printk(KERN_ERR "%s: DMA error\n", dev->name); |
ef11291b FF |
341 | |
342 | retval = IRQ_HANDLED; | |
343 | } else | |
344 | retval = IRQ_NONE; | |
345 | ||
346 | return retval; | |
347 | } | |
348 | ||
349 | static int korina_rx(struct net_device *dev, int limit) | |
350 | { | |
351 | struct korina_private *lp = netdev_priv(dev); | |
352 | struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done]; | |
353 | struct sk_buff *skb, *skb_new; | |
354 | u8 *pkt_buf; | |
4cf83b66 | 355 | u32 devcs, pkt_len, dmas; |
ef11291b FF |
356 | int count; |
357 | ||
358 | dma_cache_inv((u32)rd, sizeof(*rd)); | |
359 | ||
360 | for (count = 0; count < limit; count++) { | |
4cf83b66 PS |
361 | skb = lp->rx_skb[lp->rx_next_done]; |
362 | skb_new = NULL; | |
ef11291b FF |
363 | |
364 | devcs = rd->devcs; | |
365 | ||
4cf83b66 PS |
366 | if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0) |
367 | break; | |
368 | ||
ef11291b FF |
369 | /* Update statistics counters */ |
370 | if (devcs & ETH_RX_CRC) | |
371 | dev->stats.rx_crc_errors++; | |
372 | if (devcs & ETH_RX_LOR) | |
373 | dev->stats.rx_length_errors++; | |
374 | if (devcs & ETH_RX_LE) | |
375 | dev->stats.rx_length_errors++; | |
376 | if (devcs & ETH_RX_OVR) | |
b1011b37 | 377 | dev->stats.rx_fifo_errors++; |
ef11291b FF |
378 | if (devcs & ETH_RX_CV) |
379 | dev->stats.rx_frame_errors++; | |
380 | if (devcs & ETH_RX_CES) | |
381 | dev->stats.rx_length_errors++; | |
382 | if (devcs & ETH_RX_MP) | |
383 | dev->stats.multicast++; | |
384 | ||
385 | if ((devcs & ETH_RX_LD) != ETH_RX_LD) { | |
386 | /* check that this is a whole packet | |
387 | * WARNING: DMA_FD bit incorrectly set | |
388 | * in Rc32434 (errata ref #077) */ | |
389 | dev->stats.rx_errors++; | |
390 | dev->stats.rx_dropped++; | |
4cf83b66 | 391 | } else if ((devcs & ETH_RX_ROK)) { |
ef11291b | 392 | pkt_len = RCVPKT_LENGTH(devcs); |
4cf83b66 PS |
393 | |
394 | /* must be the (first and) last | |
395 | * descriptor then */ | |
396 | pkt_buf = (u8 *)lp->rx_skb[lp->rx_next_done]->data; | |
397 | ||
398 | /* invalidate the cache */ | |
399 | dma_cache_inv((unsigned long)pkt_buf, pkt_len - 4); | |
400 | ||
401 | /* Malloc up new buffer. */ | |
89d71a66 | 402 | skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE); |
4cf83b66 PS |
403 | |
404 | if (!skb_new) | |
405 | break; | |
406 | /* Do not count the CRC */ | |
407 | skb_put(skb, pkt_len - 4); | |
408 | skb->protocol = eth_type_trans(skb, dev); | |
409 | ||
410 | /* Pass the packet to upper layers */ | |
411 | netif_receive_skb(skb); | |
412 | dev->stats.rx_packets++; | |
413 | dev->stats.rx_bytes += pkt_len; | |
414 | ||
415 | /* Update the mcast stats */ | |
416 | if (devcs & ETH_RX_MP) | |
417 | dev->stats.multicast++; | |
418 | ||
419 | lp->rx_skb[lp->rx_next_done] = skb_new; | |
ef11291b | 420 | } |
4cf83b66 PS |
421 | |
422 | rd->devcs = 0; | |
423 | ||
424 | /* Restore descriptor's curr_addr */ | |
425 | if (skb_new) | |
426 | rd->ca = CPHYSADDR(skb_new->data); | |
427 | else | |
428 | rd->ca = CPHYSADDR(skb->data); | |
429 | ||
430 | rd->control = DMA_COUNT(KORINA_RBSIZE) | | |
431 | DMA_DESC_COD | DMA_DESC_IOD; | |
432 | lp->rd_ring[(lp->rx_next_done - 1) & | |
433 | KORINA_RDS_MASK].control &= | |
434 | ~DMA_DESC_COD; | |
435 | ||
436 | lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK; | |
437 | dma_cache_wback((u32)rd, sizeof(*rd)); | |
438 | rd = &lp->rd_ring[lp->rx_next_done]; | |
439 | writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas); | |
ef11291b FF |
440 | } |
441 | ||
442 | dmas = readl(&lp->rx_dma_regs->dmas); | |
443 | ||
444 | if (dmas & DMA_STAT_HALT) { | |
445 | writel(~(DMA_STAT_HALT | DMA_STAT_ERR), | |
446 | &lp->rx_dma_regs->dmas); | |
447 | ||
448 | lp->dma_halt_cnt++; | |
449 | rd->devcs = 0; | |
450 | skb = lp->rx_skb[lp->rx_next_done]; | |
451 | rd->ca = CPHYSADDR(skb->data); | |
452 | dma_cache_wback((u32)rd, sizeof(*rd)); | |
453 | korina_chain_rx(lp, rd); | |
454 | } | |
455 | ||
456 | return count; | |
457 | } | |
458 | ||
459 | static int korina_poll(struct napi_struct *napi, int budget) | |
460 | { | |
461 | struct korina_private *lp = | |
462 | container_of(napi, struct korina_private, napi); | |
463 | struct net_device *dev = lp->dev; | |
464 | int work_done; | |
465 | ||
466 | work_done = korina_rx(dev, budget); | |
467 | if (work_done < budget) { | |
288379f0 | 468 | napi_complete(napi); |
ef11291b FF |
469 | |
470 | writel(readl(&lp->rx_dma_regs->dmasm) & | |
471 | ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), | |
472 | &lp->rx_dma_regs->dmasm); | |
473 | } | |
474 | return work_done; | |
475 | } | |
476 | ||
477 | /* | |
478 | * Set or clear the multicast filter for this adaptor. | |
479 | */ | |
480 | static void korina_multicast_list(struct net_device *dev) | |
481 | { | |
482 | struct korina_private *lp = netdev_priv(dev); | |
483 | unsigned long flags; | |
22bedad3 | 484 | struct netdev_hw_addr *ha; |
ef11291b | 485 | u32 recognise = ETH_ARC_AB; /* always accept broadcasts */ |
ef11291b FF |
486 | |
487 | /* Set promiscuous mode */ | |
488 | if (dev->flags & IFF_PROMISC) | |
489 | recognise |= ETH_ARC_PRO; | |
490 | ||
4cd24eaf | 491 | else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4)) |
ef11291b FF |
492 | /* All multicast and broadcast */ |
493 | recognise |= ETH_ARC_AM; | |
494 | ||
495 | /* Build the hash table */ | |
4cd24eaf | 496 | if (netdev_mc_count(dev) > 4) { |
e998fd41 | 497 | u16 hash_table[4] = { 0 }; |
ef11291b FF |
498 | u32 crc; |
499 | ||
22bedad3 | 500 | netdev_for_each_mc_addr(ha, dev) { |
498d8e23 | 501 | crc = ether_crc_le(6, ha->addr); |
ef11291b FF |
502 | crc >>= 26; |
503 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
504 | } | |
505 | /* Accept filtered multicast */ | |
506 | recognise |= ETH_ARC_AFM; | |
507 | ||
508 | /* Fill the MAC hash tables with their values */ | |
509 | writel((u32)(hash_table[1] << 16 | hash_table[0]), | |
510 | &lp->eth_regs->ethhash0); | |
511 | writel((u32)(hash_table[3] << 16 | hash_table[2]), | |
512 | &lp->eth_regs->ethhash1); | |
513 | } | |
514 | ||
515 | spin_lock_irqsave(&lp->lock, flags); | |
516 | writel(recognise, &lp->eth_regs->etharc); | |
517 | spin_unlock_irqrestore(&lp->lock, flags); | |
518 | } | |
519 | ||
520 | static void korina_tx(struct net_device *dev) | |
521 | { | |
522 | struct korina_private *lp = netdev_priv(dev); | |
523 | struct dma_desc *td = &lp->td_ring[lp->tx_next_done]; | |
524 | u32 devcs; | |
525 | u32 dmas; | |
526 | ||
527 | spin_lock(&lp->lock); | |
528 | ||
529 | /* Process all desc that are done */ | |
530 | while (IS_DMA_FINISHED(td->control)) { | |
531 | if (lp->tx_full == 1) { | |
532 | netif_wake_queue(dev); | |
533 | lp->tx_full = 0; | |
534 | } | |
535 | ||
536 | devcs = lp->td_ring[lp->tx_next_done].devcs; | |
537 | if ((devcs & (ETH_TX_FD | ETH_TX_LD)) != | |
538 | (ETH_TX_FD | ETH_TX_LD)) { | |
539 | dev->stats.tx_errors++; | |
540 | dev->stats.tx_dropped++; | |
541 | ||
542 | /* Should never happen */ | |
f16aea4d | 543 | printk(KERN_ERR "%s: split tx ignored\n", |
ef11291b FF |
544 | dev->name); |
545 | } else if (devcs & ETH_TX_TOK) { | |
546 | dev->stats.tx_packets++; | |
547 | dev->stats.tx_bytes += | |
548 | lp->tx_skb[lp->tx_next_done]->len; | |
549 | } else { | |
550 | dev->stats.tx_errors++; | |
551 | dev->stats.tx_dropped++; | |
552 | ||
553 | /* Underflow */ | |
554 | if (devcs & ETH_TX_UND) | |
555 | dev->stats.tx_fifo_errors++; | |
556 | ||
557 | /* Oversized frame */ | |
558 | if (devcs & ETH_TX_OF) | |
559 | dev->stats.tx_aborted_errors++; | |
560 | ||
561 | /* Excessive deferrals */ | |
562 | if (devcs & ETH_TX_ED) | |
563 | dev->stats.tx_carrier_errors++; | |
564 | ||
565 | /* Collisions: medium busy */ | |
566 | if (devcs & ETH_TX_EC) | |
567 | dev->stats.collisions++; | |
568 | ||
569 | /* Late collision */ | |
570 | if (devcs & ETH_TX_LC) | |
571 | dev->stats.tx_window_errors++; | |
572 | } | |
573 | ||
574 | /* We must always free the original skb */ | |
575 | if (lp->tx_skb[lp->tx_next_done]) { | |
576 | dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]); | |
577 | lp->tx_skb[lp->tx_next_done] = NULL; | |
578 | } | |
579 | ||
580 | lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF; | |
581 | lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD; | |
582 | lp->td_ring[lp->tx_next_done].link = 0; | |
583 | lp->td_ring[lp->tx_next_done].ca = 0; | |
584 | lp->tx_count--; | |
585 | ||
586 | /* Go on to next transmission */ | |
587 | lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK; | |
588 | td = &lp->td_ring[lp->tx_next_done]; | |
589 | ||
590 | } | |
591 | ||
592 | /* Clear the DMA status register */ | |
593 | dmas = readl(&lp->tx_dma_regs->dmas); | |
594 | writel(~dmas, &lp->tx_dma_regs->dmas); | |
595 | ||
596 | writel(readl(&lp->tx_dma_regs->dmasm) & | |
597 | ~(DMA_STAT_FINI | DMA_STAT_ERR), | |
598 | &lp->tx_dma_regs->dmasm); | |
599 | ||
600 | spin_unlock(&lp->lock); | |
601 | } | |
602 | ||
603 | static irqreturn_t | |
604 | korina_tx_dma_interrupt(int irq, void *dev_id) | |
605 | { | |
606 | struct net_device *dev = dev_id; | |
607 | struct korina_private *lp = netdev_priv(dev); | |
608 | u32 dmas, dmasm; | |
609 | irqreturn_t retval; | |
610 | ||
611 | dmas = readl(&lp->tx_dma_regs->dmas); | |
612 | ||
613 | if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) { | |
ef11291b FF |
614 | dmasm = readl(&lp->tx_dma_regs->dmasm); |
615 | writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR), | |
616 | &lp->tx_dma_regs->dmasm); | |
617 | ||
60d3f982 PS |
618 | korina_tx(dev); |
619 | ||
ef11291b FF |
620 | if (lp->tx_chain_status == desc_filled && |
621 | (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) { | |
622 | writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), | |
623 | &(lp->tx_dma_regs->dmandptr)); | |
624 | lp->tx_chain_status = desc_empty; | |
625 | lp->tx_chain_head = lp->tx_chain_tail; | |
626 | dev->trans_start = jiffies; | |
627 | } | |
628 | if (dmas & DMA_STAT_ERR) | |
f16aea4d | 629 | printk(KERN_ERR "%s: DMA error\n", dev->name); |
ef11291b FF |
630 | |
631 | retval = IRQ_HANDLED; | |
632 | } else | |
633 | retval = IRQ_NONE; | |
634 | ||
635 | return retval; | |
636 | } | |
637 | ||
638 | ||
639 | static void korina_check_media(struct net_device *dev, unsigned int init_media) | |
640 | { | |
641 | struct korina_private *lp = netdev_priv(dev); | |
642 | ||
643 | mii_check_media(&lp->mii_if, 0, init_media); | |
644 | ||
645 | if (lp->mii_if.full_duplex) | |
646 | writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD, | |
647 | &lp->eth_regs->ethmac2); | |
648 | else | |
649 | writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD, | |
650 | &lp->eth_regs->ethmac2); | |
651 | } | |
652 | ||
4d5ef9f0 FF |
653 | static void korina_poll_media(unsigned long data) |
654 | { | |
655 | struct net_device *dev = (struct net_device *) data; | |
656 | struct korina_private *lp = netdev_priv(dev); | |
657 | ||
658 | korina_check_media(dev, 0); | |
659 | mod_timer(&lp->media_check_timer, jiffies + HZ); | |
660 | } | |
661 | ||
ef11291b FF |
662 | static void korina_set_carrier(struct mii_if_info *mii) |
663 | { | |
664 | if (mii->force_media) { | |
665 | /* autoneg is off: Link is always assumed to be up */ | |
666 | if (!netif_carrier_ok(mii->dev)) | |
667 | netif_carrier_on(mii->dev); | |
668 | } else /* Let MMI library update carrier status */ | |
669 | korina_check_media(mii->dev, 0); | |
670 | } | |
671 | ||
672 | static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
673 | { | |
674 | struct korina_private *lp = netdev_priv(dev); | |
675 | struct mii_ioctl_data *data = if_mii(rq); | |
676 | int rc; | |
677 | ||
678 | if (!netif_running(dev)) | |
679 | return -EINVAL; | |
680 | spin_lock_irq(&lp->lock); | |
681 | rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL); | |
682 | spin_unlock_irq(&lp->lock); | |
683 | korina_set_carrier(&lp->mii_if); | |
684 | ||
685 | return rc; | |
686 | } | |
687 | ||
688 | /* ethtool helpers */ | |
689 | static void netdev_get_drvinfo(struct net_device *dev, | |
690 | struct ethtool_drvinfo *info) | |
691 | { | |
692 | struct korina_private *lp = netdev_priv(dev); | |
693 | ||
7826d43f JP |
694 | strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); |
695 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); | |
696 | strlcpy(info->bus_info, lp->dev->name, sizeof(info->bus_info)); | |
ef11291b FF |
697 | } |
698 | ||
699 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
700 | { | |
701 | struct korina_private *lp = netdev_priv(dev); | |
702 | int rc; | |
703 | ||
704 | spin_lock_irq(&lp->lock); | |
705 | rc = mii_ethtool_gset(&lp->mii_if, cmd); | |
706 | spin_unlock_irq(&lp->lock); | |
707 | ||
708 | return rc; | |
709 | } | |
710 | ||
711 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
712 | { | |
713 | struct korina_private *lp = netdev_priv(dev); | |
714 | int rc; | |
715 | ||
716 | spin_lock_irq(&lp->lock); | |
717 | rc = mii_ethtool_sset(&lp->mii_if, cmd); | |
718 | spin_unlock_irq(&lp->lock); | |
719 | korina_set_carrier(&lp->mii_if); | |
720 | ||
721 | return rc; | |
722 | } | |
723 | ||
724 | static u32 netdev_get_link(struct net_device *dev) | |
725 | { | |
726 | struct korina_private *lp = netdev_priv(dev); | |
727 | ||
728 | return mii_link_ok(&lp->mii_if); | |
729 | } | |
730 | ||
0fc0b732 | 731 | static const struct ethtool_ops netdev_ethtool_ops = { |
ef11291b FF |
732 | .get_drvinfo = netdev_get_drvinfo, |
733 | .get_settings = netdev_get_settings, | |
734 | .set_settings = netdev_set_settings, | |
735 | .get_link = netdev_get_link, | |
736 | }; | |
737 | ||
7010837a | 738 | static int korina_alloc_ring(struct net_device *dev) |
ef11291b FF |
739 | { |
740 | struct korina_private *lp = netdev_priv(dev); | |
e85bf47e | 741 | struct sk_buff *skb; |
ef11291b FF |
742 | int i; |
743 | ||
744 | /* Initialize the transmit descriptors */ | |
745 | for (i = 0; i < KORINA_NUM_TDS; i++) { | |
746 | lp->td_ring[i].control = DMA_DESC_IOF; | |
747 | lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD; | |
748 | lp->td_ring[i].ca = 0; | |
749 | lp->td_ring[i].link = 0; | |
750 | } | |
751 | lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = | |
752 | lp->tx_full = lp->tx_count = 0; | |
753 | lp->tx_chain_status = desc_empty; | |
754 | ||
755 | /* Initialize the receive descriptors */ | |
756 | for (i = 0; i < KORINA_NUM_RDS; i++) { | |
53ee490a | 757 | skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE); |
ef11291b | 758 | if (!skb) |
7010837a | 759 | return -ENOMEM; |
ef11291b FF |
760 | lp->rx_skb[i] = skb; |
761 | lp->rd_ring[i].control = DMA_DESC_IOD | | |
762 | DMA_COUNT(KORINA_RBSIZE); | |
763 | lp->rd_ring[i].devcs = 0; | |
764 | lp->rd_ring[i].ca = CPHYSADDR(skb->data); | |
765 | lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]); | |
766 | } | |
767 | ||
6a2fe983 PS |
768 | /* loop back receive descriptors, so the last |
769 | * descriptor points to the first one */ | |
770 | lp->rd_ring[i - 1].link = CPHYSADDR(&lp->rd_ring[0]); | |
771 | lp->rd_ring[i - 1].control |= DMA_DESC_COD; | |
ef11291b | 772 | |
6a2fe983 | 773 | lp->rx_next_done = 0; |
ef11291b FF |
774 | lp->rx_chain_head = 0; |
775 | lp->rx_chain_tail = 0; | |
776 | lp->rx_chain_status = desc_empty; | |
7010837a PS |
777 | |
778 | return 0; | |
ef11291b FF |
779 | } |
780 | ||
781 | static void korina_free_ring(struct net_device *dev) | |
782 | { | |
783 | struct korina_private *lp = netdev_priv(dev); | |
784 | int i; | |
785 | ||
786 | for (i = 0; i < KORINA_NUM_RDS; i++) { | |
787 | lp->rd_ring[i].control = 0; | |
788 | if (lp->rx_skb[i]) | |
789 | dev_kfree_skb_any(lp->rx_skb[i]); | |
790 | lp->rx_skb[i] = NULL; | |
791 | } | |
792 | ||
793 | for (i = 0; i < KORINA_NUM_TDS; i++) { | |
794 | lp->td_ring[i].control = 0; | |
795 | if (lp->tx_skb[i]) | |
796 | dev_kfree_skb_any(lp->tx_skb[i]); | |
797 | lp->tx_skb[i] = NULL; | |
798 | } | |
799 | } | |
800 | ||
801 | /* | |
802 | * Initialize the RC32434 ethernet controller. | |
803 | */ | |
804 | static int korina_init(struct net_device *dev) | |
805 | { | |
806 | struct korina_private *lp = netdev_priv(dev); | |
807 | ||
808 | /* Disable DMA */ | |
809 | korina_abort_tx(dev); | |
810 | korina_abort_rx(dev); | |
811 | ||
812 | /* reset ethernet logic */ | |
813 | writel(0, &lp->eth_regs->ethintfc); | |
814 | while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP)) | |
815 | dev->trans_start = jiffies; | |
816 | ||
817 | /* Enable Ethernet Interface */ | |
818 | writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc); | |
819 | ||
820 | /* Allocate rings */ | |
7010837a PS |
821 | if (korina_alloc_ring(dev)) { |
822 | printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name); | |
823 | korina_free_ring(dev); | |
824 | return -ENOMEM; | |
825 | } | |
ef11291b FF |
826 | |
827 | writel(0, &lp->rx_dma_regs->dmas); | |
828 | /* Start Rx DMA */ | |
829 | korina_start_rx(lp, &lp->rd_ring[0]); | |
830 | ||
831 | writel(readl(&lp->tx_dma_regs->dmasm) & | |
832 | ~(DMA_STAT_FINI | DMA_STAT_ERR), | |
833 | &lp->tx_dma_regs->dmasm); | |
834 | writel(readl(&lp->rx_dma_regs->dmasm) & | |
835 | ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR), | |
836 | &lp->rx_dma_regs->dmasm); | |
837 | ||
838 | /* Accept only packets destined for this Ethernet device address */ | |
839 | writel(ETH_ARC_AB, &lp->eth_regs->etharc); | |
840 | ||
841 | /* Set all Ether station address registers to their initial values */ | |
842 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); | |
843 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0); | |
844 | ||
845 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); | |
846 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1); | |
847 | ||
848 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); | |
849 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2); | |
850 | ||
851 | writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); | |
852 | writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); | |
853 | ||
854 | ||
855 | /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */ | |
856 | writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD, | |
857 | &lp->eth_regs->ethmac2); | |
858 | ||
859 | /* Back to back inter-packet-gap */ | |
860 | writel(0x15, &lp->eth_regs->ethipgt); | |
861 | /* Non - Back to back inter-packet-gap */ | |
862 | writel(0x12, &lp->eth_regs->ethipgr); | |
863 | ||
864 | /* Management Clock Prescaler Divisor | |
865 | * Clock independent setting */ | |
866 | writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1, | |
867 | &lp->eth_regs->ethmcp); | |
868 | ||
869 | /* don't transmit until fifo contains 48b */ | |
870 | writel(48, &lp->eth_regs->ethfifott); | |
871 | ||
872 | writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1); | |
873 | ||
874 | napi_enable(&lp->napi); | |
875 | netif_start_queue(dev); | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | /* | |
881 | * Restart the RC32434 ethernet controller. | |
ef11291b | 882 | */ |
ceb3d239 | 883 | static void korina_restart_task(struct work_struct *work) |
ef11291b | 884 | { |
ceb3d239 PS |
885 | struct korina_private *lp = container_of(work, |
886 | struct korina_private, restart_task); | |
887 | struct net_device *dev = lp->dev; | |
ef11291b FF |
888 | |
889 | /* | |
890 | * Disable interrupts | |
891 | */ | |
892 | disable_irq(lp->rx_irq); | |
893 | disable_irq(lp->tx_irq); | |
894 | disable_irq(lp->ovr_irq); | |
895 | disable_irq(lp->und_irq); | |
896 | ||
897 | writel(readl(&lp->tx_dma_regs->dmasm) | | |
898 | DMA_STAT_FINI | DMA_STAT_ERR, | |
899 | &lp->tx_dma_regs->dmasm); | |
900 | writel(readl(&lp->rx_dma_regs->dmasm) | | |
901 | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR, | |
902 | &lp->rx_dma_regs->dmasm); | |
903 | ||
904 | korina_free_ring(dev); | |
905 | ||
beb0babf PS |
906 | napi_disable(&lp->napi); |
907 | ||
ceb3d239 | 908 | if (korina_init(dev) < 0) { |
f16aea4d | 909 | printk(KERN_ERR "%s: cannot restart device\n", dev->name); |
ceb3d239 | 910 | return; |
ef11291b FF |
911 | } |
912 | korina_multicast_list(dev); | |
913 | ||
914 | enable_irq(lp->und_irq); | |
915 | enable_irq(lp->ovr_irq); | |
916 | enable_irq(lp->tx_irq); | |
917 | enable_irq(lp->rx_irq); | |
ef11291b FF |
918 | } |
919 | ||
920 | static void korina_clear_and_restart(struct net_device *dev, u32 value) | |
921 | { | |
922 | struct korina_private *lp = netdev_priv(dev); | |
923 | ||
924 | netif_stop_queue(dev); | |
925 | writel(value, &lp->eth_regs->ethintfc); | |
ceb3d239 | 926 | schedule_work(&lp->restart_task); |
ef11291b FF |
927 | } |
928 | ||
929 | /* Ethernet Tx Underflow interrupt */ | |
930 | static irqreturn_t korina_und_interrupt(int irq, void *dev_id) | |
931 | { | |
932 | struct net_device *dev = dev_id; | |
933 | struct korina_private *lp = netdev_priv(dev); | |
934 | unsigned int und; | |
935 | ||
936 | spin_lock(&lp->lock); | |
937 | ||
938 | und = readl(&lp->eth_regs->ethintfc); | |
939 | ||
940 | if (und & ETH_INT_FC_UND) | |
941 | korina_clear_and_restart(dev, und & ~ETH_INT_FC_UND); | |
942 | ||
943 | spin_unlock(&lp->lock); | |
944 | ||
945 | return IRQ_HANDLED; | |
946 | } | |
947 | ||
948 | static void korina_tx_timeout(struct net_device *dev) | |
949 | { | |
950 | struct korina_private *lp = netdev_priv(dev); | |
ef11291b | 951 | |
ceb3d239 | 952 | schedule_work(&lp->restart_task); |
ef11291b FF |
953 | } |
954 | ||
955 | /* Ethernet Rx Overflow interrupt */ | |
956 | static irqreturn_t | |
957 | korina_ovr_interrupt(int irq, void *dev_id) | |
958 | { | |
959 | struct net_device *dev = dev_id; | |
960 | struct korina_private *lp = netdev_priv(dev); | |
961 | unsigned int ovr; | |
962 | ||
963 | spin_lock(&lp->lock); | |
964 | ovr = readl(&lp->eth_regs->ethintfc); | |
965 | ||
966 | if (ovr & ETH_INT_FC_OVR) | |
967 | korina_clear_and_restart(dev, ovr & ~ETH_INT_FC_OVR); | |
968 | ||
969 | spin_unlock(&lp->lock); | |
970 | ||
971 | return IRQ_HANDLED; | |
972 | } | |
973 | ||
974 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
975 | static void korina_poll_controller(struct net_device *dev) | |
976 | { | |
977 | disable_irq(dev->irq); | |
978 | korina_tx_dma_interrupt(dev->irq, dev); | |
979 | enable_irq(dev->irq); | |
980 | } | |
981 | #endif | |
982 | ||
983 | static int korina_open(struct net_device *dev) | |
984 | { | |
985 | struct korina_private *lp = netdev_priv(dev); | |
e3152ab9 | 986 | int ret; |
ef11291b FF |
987 | |
988 | /* Initialize */ | |
989 | ret = korina_init(dev); | |
990 | if (ret < 0) { | |
f16aea4d | 991 | printk(KERN_ERR "%s: cannot open device\n", dev->name); |
ef11291b FF |
992 | goto out; |
993 | } | |
994 | ||
995 | /* Install the interrupt handler | |
996 | * that handles the Done Finished | |
997 | * Ovr and Und Events */ | |
a0607fd3 | 998 | ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt, |
1c5625cf | 999 | IRQF_DISABLED, "Korina ethernet Rx", dev); |
ef11291b | 1000 | if (ret < 0) { |
f16aea4d | 1001 | printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n", |
ef11291b FF |
1002 | dev->name, lp->rx_irq); |
1003 | goto err_release; | |
1004 | } | |
a0607fd3 | 1005 | ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt, |
1c5625cf | 1006 | IRQF_DISABLED, "Korina ethernet Tx", dev); |
ef11291b | 1007 | if (ret < 0) { |
f16aea4d | 1008 | printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n", |
ef11291b FF |
1009 | dev->name, lp->tx_irq); |
1010 | goto err_free_rx_irq; | |
1011 | } | |
1012 | ||
1013 | /* Install handler for overrun error. */ | |
a0607fd3 | 1014 | ret = request_irq(lp->ovr_irq, korina_ovr_interrupt, |
1c5625cf | 1015 | IRQF_DISABLED, "Ethernet Overflow", dev); |
ef11291b | 1016 | if (ret < 0) { |
f16aea4d | 1017 | printk(KERN_ERR "%s: unable to get OVR IRQ %d\n", |
ef11291b FF |
1018 | dev->name, lp->ovr_irq); |
1019 | goto err_free_tx_irq; | |
1020 | } | |
1021 | ||
1022 | /* Install handler for underflow error. */ | |
a0607fd3 | 1023 | ret = request_irq(lp->und_irq, korina_und_interrupt, |
1c5625cf | 1024 | IRQF_DISABLED, "Ethernet Underflow", dev); |
ef11291b | 1025 | if (ret < 0) { |
f16aea4d | 1026 | printk(KERN_ERR "%s: unable to get UND IRQ %d\n", |
ef11291b FF |
1027 | dev->name, lp->und_irq); |
1028 | goto err_free_ovr_irq; | |
1029 | } | |
4d5ef9f0 | 1030 | mod_timer(&lp->media_check_timer, jiffies + 1); |
751c2e47 FR |
1031 | out: |
1032 | return ret; | |
ef11291b FF |
1033 | |
1034 | err_free_ovr_irq: | |
1035 | free_irq(lp->ovr_irq, dev); | |
1036 | err_free_tx_irq: | |
1037 | free_irq(lp->tx_irq, dev); | |
1038 | err_free_rx_irq: | |
1039 | free_irq(lp->rx_irq, dev); | |
1040 | err_release: | |
1041 | korina_free_ring(dev); | |
1042 | goto out; | |
ef11291b FF |
1043 | } |
1044 | ||
1045 | static int korina_close(struct net_device *dev) | |
1046 | { | |
1047 | struct korina_private *lp = netdev_priv(dev); | |
1048 | u32 tmp; | |
1049 | ||
4d5ef9f0 FF |
1050 | del_timer(&lp->media_check_timer); |
1051 | ||
ef11291b FF |
1052 | /* Disable interrupts */ |
1053 | disable_irq(lp->rx_irq); | |
1054 | disable_irq(lp->tx_irq); | |
1055 | disable_irq(lp->ovr_irq); | |
1056 | disable_irq(lp->und_irq); | |
1057 | ||
1058 | korina_abort_tx(dev); | |
1059 | tmp = readl(&lp->tx_dma_regs->dmasm); | |
1060 | tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR; | |
1061 | writel(tmp, &lp->tx_dma_regs->dmasm); | |
1062 | ||
1063 | korina_abort_rx(dev); | |
1064 | tmp = readl(&lp->rx_dma_regs->dmasm); | |
1065 | tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR; | |
1066 | writel(tmp, &lp->rx_dma_regs->dmasm); | |
1067 | ||
1068 | korina_free_ring(dev); | |
1069 | ||
beb0babf PS |
1070 | napi_disable(&lp->napi); |
1071 | ||
ceb3d239 PS |
1072 | cancel_work_sync(&lp->restart_task); |
1073 | ||
ef11291b FF |
1074 | free_irq(lp->rx_irq, dev); |
1075 | free_irq(lp->tx_irq, dev); | |
1076 | free_irq(lp->ovr_irq, dev); | |
1077 | free_irq(lp->und_irq, dev); | |
1078 | ||
1079 | return 0; | |
1080 | } | |
1081 | ||
52b031ff AB |
1082 | static const struct net_device_ops korina_netdev_ops = { |
1083 | .ndo_open = korina_open, | |
1084 | .ndo_stop = korina_close, | |
1085 | .ndo_start_xmit = korina_send_packet, | |
afc4b13d | 1086 | .ndo_set_rx_mode = korina_multicast_list, |
52b031ff AB |
1087 | .ndo_tx_timeout = korina_tx_timeout, |
1088 | .ndo_do_ioctl = korina_ioctl, | |
1089 | .ndo_change_mtu = eth_change_mtu, | |
1090 | .ndo_validate_addr = eth_validate_addr, | |
1091 | .ndo_set_mac_address = eth_mac_addr, | |
1092 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1093 | .ndo_poll_controller = korina_poll_controller, | |
1094 | #endif | |
1095 | }; | |
1096 | ||
ef11291b FF |
1097 | static int korina_probe(struct platform_device *pdev) |
1098 | { | |
1099 | struct korina_device *bif = platform_get_drvdata(pdev); | |
1100 | struct korina_private *lp; | |
1101 | struct net_device *dev; | |
1102 | struct resource *r; | |
e3152ab9 | 1103 | int rc; |
ef11291b FF |
1104 | |
1105 | dev = alloc_etherdev(sizeof(struct korina_private)); | |
41de8d4c | 1106 | if (!dev) |
ef11291b | 1107 | return -ENOMEM; |
41de8d4c | 1108 | |
ef11291b | 1109 | SET_NETDEV_DEV(dev, &pdev->dev); |
ef11291b FF |
1110 | lp = netdev_priv(dev); |
1111 | ||
1112 | bif->dev = dev; | |
1113 | memcpy(dev->dev_addr, bif->mac, 6); | |
1114 | ||
1115 | lp->rx_irq = platform_get_irq_byname(pdev, "korina_rx"); | |
1116 | lp->tx_irq = platform_get_irq_byname(pdev, "korina_tx"); | |
1117 | lp->ovr_irq = platform_get_irq_byname(pdev, "korina_ovr"); | |
1118 | lp->und_irq = platform_get_irq_byname(pdev, "korina_und"); | |
1119 | ||
1120 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_regs"); | |
1121 | dev->base_addr = r->start; | |
38013262 | 1122 | lp->eth_regs = ioremap_nocache(r->start, resource_size(r)); |
ef11291b | 1123 | if (!lp->eth_regs) { |
f16aea4d | 1124 | printk(KERN_ERR DRV_NAME ": cannot remap registers\n"); |
e3152ab9 | 1125 | rc = -ENXIO; |
ef11291b FF |
1126 | goto probe_err_out; |
1127 | } | |
1128 | ||
1129 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_rx"); | |
38013262 | 1130 | lp->rx_dma_regs = ioremap_nocache(r->start, resource_size(r)); |
ef11291b | 1131 | if (!lp->rx_dma_regs) { |
f16aea4d | 1132 | printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n"); |
e3152ab9 | 1133 | rc = -ENXIO; |
ef11291b FF |
1134 | goto probe_err_dma_rx; |
1135 | } | |
1136 | ||
1137 | r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "korina_dma_tx"); | |
38013262 | 1138 | lp->tx_dma_regs = ioremap_nocache(r->start, resource_size(r)); |
ef11291b | 1139 | if (!lp->tx_dma_regs) { |
f16aea4d | 1140 | printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n"); |
e3152ab9 | 1141 | rc = -ENXIO; |
ef11291b FF |
1142 | goto probe_err_dma_tx; |
1143 | } | |
1144 | ||
1145 | lp->td_ring = kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL); | |
1146 | if (!lp->td_ring) { | |
e3152ab9 | 1147 | rc = -ENXIO; |
ef11291b FF |
1148 | goto probe_err_td_ring; |
1149 | } | |
1150 | ||
1151 | dma_cache_inv((unsigned long)(lp->td_ring), | |
1152 | TD_RING_SIZE + RD_RING_SIZE); | |
1153 | ||
1154 | /* now convert TD_RING pointer to KSEG1 */ | |
1155 | lp->td_ring = (struct dma_desc *)KSEG1ADDR(lp->td_ring); | |
1156 | lp->rd_ring = &lp->td_ring[KORINA_NUM_TDS]; | |
1157 | ||
1158 | spin_lock_init(&lp->lock); | |
1159 | /* just use the rx dma irq */ | |
1160 | dev->irq = lp->rx_irq; | |
1161 | lp->dev = dev; | |
1162 | ||
52b031ff | 1163 | dev->netdev_ops = &korina_netdev_ops; |
ef11291b | 1164 | dev->ethtool_ops = &netdev_ethtool_ops; |
ef11291b | 1165 | dev->watchdog_timeo = TX_TIMEOUT; |
ef11291b FF |
1166 | netif_napi_add(dev, &lp->napi, korina_poll, 64); |
1167 | ||
1168 | lp->phy_addr = (((lp->rx_irq == 0x2c? 1:0) << 8) | 0x05); | |
1169 | lp->mii_if.dev = dev; | |
1170 | lp->mii_if.mdio_read = mdio_read; | |
1171 | lp->mii_if.mdio_write = mdio_write; | |
1172 | lp->mii_if.phy_id = lp->phy_addr; | |
1173 | lp->mii_if.phy_id_mask = 0x1f; | |
1174 | lp->mii_if.reg_num_mask = 0x1f; | |
1175 | ||
e3152ab9 FR |
1176 | rc = register_netdev(dev); |
1177 | if (rc < 0) { | |
ef11291b | 1178 | printk(KERN_ERR DRV_NAME |
f16aea4d | 1179 | ": cannot register net device: %d\n", rc); |
ef11291b FF |
1180 | goto probe_err_register; |
1181 | } | |
4d5ef9f0 | 1182 | setup_timer(&lp->media_check_timer, korina_poll_media, (unsigned long) dev); |
f16aea4d | 1183 | |
ceb3d239 PS |
1184 | INIT_WORK(&lp->restart_task, korina_restart_task); |
1185 | ||
f16aea4d PS |
1186 | printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n", |
1187 | dev->name); | |
e3152ab9 FR |
1188 | out: |
1189 | return rc; | |
ef11291b FF |
1190 | |
1191 | probe_err_register: | |
1192 | kfree(lp->td_ring); | |
1193 | probe_err_td_ring: | |
1194 | iounmap(lp->tx_dma_regs); | |
1195 | probe_err_dma_tx: | |
1196 | iounmap(lp->rx_dma_regs); | |
1197 | probe_err_dma_rx: | |
1198 | iounmap(lp->eth_regs); | |
1199 | probe_err_out: | |
1200 | free_netdev(dev); | |
e3152ab9 | 1201 | goto out; |
ef11291b FF |
1202 | } |
1203 | ||
1204 | static int korina_remove(struct platform_device *pdev) | |
1205 | { | |
1206 | struct korina_device *bif = platform_get_drvdata(pdev); | |
1207 | struct korina_private *lp = netdev_priv(bif->dev); | |
1208 | ||
e3152ab9 FR |
1209 | iounmap(lp->eth_regs); |
1210 | iounmap(lp->rx_dma_regs); | |
1211 | iounmap(lp->tx_dma_regs); | |
ef11291b | 1212 | |
ef11291b FF |
1213 | unregister_netdev(bif->dev); |
1214 | free_netdev(bif->dev); | |
1215 | ||
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static struct platform_driver korina_driver = { | |
1220 | .driver.name = "korina", | |
1221 | .probe = korina_probe, | |
1222 | .remove = korina_remove, | |
1223 | }; | |
1224 | ||
db62f684 | 1225 | module_platform_driver(korina_driver); |
ef11291b FF |
1226 | |
1227 | MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>"); | |
1228 | MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>"); | |
1229 | MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>"); | |
1230 | MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver"); | |
1231 | MODULE_LICENSE("GPL"); |