projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
net: ethernet: lantiq_etop: use phydev from struct net_device
[deliverable/linux.git] / drivers / net / ethernet / lantiq_etop.c
CommitLineData
504d4721
JC		 1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
0ab75ae8 12 * along with this program; if not, see <http://www.gnu.org/licenses/>.
504d4721
JC		 13 *
14 * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
15 */
16
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/errno.h>
20#include <linux/types.h>
21#include <linux/interrupt.h>
22#include <linux/uaccess.h>
23#include <linux/in.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/phy.h>
27#include <linux/ip.h>
28#include <linux/tcp.h>
29#include <linux/skbuff.h>
30#include <linux/mm.h>
31#include <linux/platform_device.h>
32#include <linux/ethtool.h>
33#include <linux/init.h>
34#include <linux/delay.h>
35#include <linux/io.h>
a32fd63d
JC		 36#include <linux/dma-mapping.h>
37#include <linux/module.h>
504d4721
JC		 38
39#include <asm/checksum.h>
40
41#include <lantiq_soc.h>
42#include <xway_dma.h>
43#include <lantiq_platform.h>
44
45#define LTQ_ETOP_MDIO 0x11804
46#define MDIO_REQUEST 0x80000000
47#define MDIO_READ 0x40000000
48#define MDIO_ADDR_MASK 0x1f
49#define MDIO_ADDR_OFFSET 0x15
50#define MDIO_REG_MASK 0x1f
51#define MDIO_REG_OFFSET 0x10
52#define MDIO_VAL_MASK 0xffff
53
54#define PPE32_CGEN 0x800
55#define LQ_PPE32_ENET_MAC_CFG 0x1840
56
57#define LTQ_ETOP_ENETS0 0x11850
58#define LTQ_ETOP_MAC_DA0 0x1186C
59#define LTQ_ETOP_MAC_DA1 0x11870
60#define LTQ_ETOP_CFG 0x16020
61#define LTQ_ETOP_IGPLEN 0x16080
62
63#define MAX_DMA_CHAN 0x8
64#define MAX_DMA_CRC_LEN 0x4
65#define MAX_DMA_DATA_LEN 0x600
66
67#define ETOP_FTCU BIT(28)
68#define ETOP_MII_MASK 0xf
69#define ETOP_MII_NORMAL 0xd
70#define ETOP_MII_REVERSE 0xe
71#define ETOP_PLEN_UNDER 0x40
72#define ETOP_CGEN 0x800
73
74/* use 2 static channels for TX/RX */
75#define LTQ_ETOP_TX_CHANNEL 1
76#define LTQ_ETOP_RX_CHANNEL 6
77#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
78#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
79
80#define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
81#define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
82#define ltq_etop_w32_mask(x, y, z) \
83 ltq_w32_mask(x, y, ltq_etop_membase + (z))
84
85#define DRV_VERSION "1.0"
86
87static void __iomem *ltq_etop_membase;
88
89struct ltq_etop_chan {
90 int idx;
91 int tx_free;
92 struct net_device *netdev;
93 struct napi_struct napi;
94 struct ltq_dma_channel dma;
95 struct sk_buff *skb[LTQ_DESC_NUM];
96};
97
98struct ltq_etop_priv {
99 struct net_device *netdev;
d1b86507 100 struct platform_device *pdev;
504d4721
JC		 101 struct ltq_eth_data *pldata;
102 struct resource *res;
103
104 struct mii_bus *mii_bus;
504d4721
JC		 105
106 struct ltq_etop_chan ch[MAX_DMA_CHAN];
107 int tx_free[MAX_DMA_CHAN >> 1];
108
109 spinlock_t lock;
110};
111
112static int
113ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
114{
c056b734 115 ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
504d4721
JC		 116 if (!ch->skb[ch->dma.desc])
117 return -ENOMEM;
118 ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
119 ch->skb[ch->dma.desc]->data, MAX_DMA_DATA_LEN,
120 DMA_FROM_DEVICE);
121 ch->dma.desc_base[ch->dma.desc].addr =
122 CPHYSADDR(ch->skb[ch->dma.desc]->data);
123 ch->dma.desc_base[ch->dma.desc].ctl =
124 LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
125 MAX_DMA_DATA_LEN;
126 skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
127 return 0;
128}
129
130static void
131ltq_etop_hw_receive(struct ltq_etop_chan *ch)
132{
133 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
134 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
135 struct sk_buff *skb = ch->skb[ch->dma.desc];
136 int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
137 unsigned long flags;
138
139 spin_lock_irqsave(&priv->lock, flags);
140 if (ltq_etop_alloc_skb(ch)) {
141 netdev_err(ch->netdev,
142 "failed to allocate new rx buffer, stopping DMA\n");
143 ltq_dma_close(&ch->dma);
144 }
145 ch->dma.desc++;
146 ch->dma.desc %= LTQ_DESC_NUM;
147 spin_unlock_irqrestore(&priv->lock, flags);
148
149 skb_put(skb, len);
504d4721
JC		 150 skb->protocol = eth_type_trans(skb, ch->netdev);
151 netif_receive_skb(skb);
152}
153
154static int
155ltq_etop_poll_rx(struct napi_struct *napi, int budget)
156{
157 struct ltq_etop_chan *ch = container_of(napi,
158 struct ltq_etop_chan, napi);
159 int rx = 0;
160 int complete = 0;
161
162 while ((rx < budget) && !complete) {
163 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
164
165 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
166 ltq_etop_hw_receive(ch);
167 rx++;
168 } else {
169 complete = 1;
170 }
171 }
172 if (complete || !rx) {
173 napi_complete(&ch->napi);
174 ltq_dma_ack_irq(&ch->dma);
175 }
176 return rx;
177}
178
179static int
180ltq_etop_poll_tx(struct napi_struct *napi, int budget)
181{
182 struct ltq_etop_chan *ch =
183 container_of(napi, struct ltq_etop_chan, napi);
184 struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
185 struct netdev_queue *txq =
186 netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
187 unsigned long flags;
188
189 spin_lock_irqsave(&priv->lock, flags);
190 while ((ch->dma.desc_base[ch->tx_free].ctl &
191 (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
192 dev_kfree_skb_any(ch->skb[ch->tx_free]);
193 ch->skb[ch->tx_free] = NULL;
194 memset(&ch->dma.desc_base[ch->tx_free], 0,
195 sizeof(struct ltq_dma_desc));
196 ch->tx_free++;
197 ch->tx_free %= LTQ_DESC_NUM;
198 }
199 spin_unlock_irqrestore(&priv->lock, flags);
200
201 if (netif_tx_queue_stopped(txq))
202 netif_tx_start_queue(txq);
203 napi_complete(&ch->napi);
204 ltq_dma_ack_irq(&ch->dma);
205 return 1;
206}
207
208static irqreturn_t
209ltq_etop_dma_irq(int irq, void *_priv)
210{
211 struct ltq_etop_priv *priv = _priv;
212 int ch = irq - LTQ_DMA_CH0_INT;
213
214 napi_schedule(&priv->ch[ch].napi);
215 return IRQ_HANDLED;
216}
217
218static void
219ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
220{
221 struct ltq_etop_priv *priv = netdev_priv(dev);
222
223 ltq_dma_free(&ch->dma);
224 if (ch->dma.irq)
225 free_irq(ch->dma.irq, priv);
226 if (IS_RX(ch->idx)) {
227 int desc;
228 for (desc = 0; desc < LTQ_DESC_NUM; desc++)
229 dev_kfree_skb_any(ch->skb[ch->dma.desc]);
230 }
231}
232
233static void
234ltq_etop_hw_exit(struct net_device *dev)
235{
236 struct ltq_etop_priv *priv = netdev_priv(dev);
237 int i;
238
239 ltq_pmu_disable(PMU_PPE);
240 for (i = 0; i < MAX_DMA_CHAN; i++)
241 if (IS_TX(i) || IS_RX(i))
242 ltq_etop_free_channel(dev, &priv->ch[i]);
243}
244
245static int
246ltq_etop_hw_init(struct net_device *dev)
247{
248 struct ltq_etop_priv *priv = netdev_priv(dev);
249 int i;
250
251 ltq_pmu_enable(PMU_PPE);
252
253 switch (priv->pldata->mii_mode) {
254 case PHY_INTERFACE_MODE_RMII:
255 ltq_etop_w32_mask(ETOP_MII_MASK,
256 ETOP_MII_REVERSE, LTQ_ETOP_CFG);
257 break;
258
259 case PHY_INTERFACE_MODE_MII:
260 ltq_etop_w32_mask(ETOP_MII_MASK,
261 ETOP_MII_NORMAL, LTQ_ETOP_CFG);
262 break;
263
264 default:
265 netdev_err(dev, "unknown mii mode %d\n",
266 priv->pldata->mii_mode);
267 return -ENOTSUPP;
268 }
269
270 /* enable crc generation */
271 ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
272
273 ltq_dma_init_port(DMA_PORT_ETOP);
274
275 for (i = 0; i < MAX_DMA_CHAN; i++) {
276 int irq = LTQ_DMA_CH0_INT + i;
277 struct ltq_etop_chan *ch = &priv->ch[i];
278
279 ch->idx = ch->dma.nr = i;
280
281 if (IS_TX(i)) {
282 ltq_dma_alloc_tx(&ch->dma);
dddb29e4 283 request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
504d4721
JC		 284 } else if (IS_RX(i)) {
285 ltq_dma_alloc_rx(&ch->dma);
286 for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
287 ch->dma.desc++)
288 if (ltq_etop_alloc_skb(ch))
289 return -ENOMEM;
290 ch->dma.desc = 0;
dddb29e4 291 request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
504d4721
JC		 292 }
293 ch->dma.irq = irq;
294 }
295 return 0;
296}
297
298static void
299ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
300{
7826d43f
JP		 301 strlcpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
302 strlcpy(info->bus_info, "internal", sizeof(info->bus_info));
303 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
504d4721
JC		 304}
305
306static int
307ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
308{
d1e3a356 309 return phy_ethtool_gset(dev->phydev, cmd);
504d4721
JC		 310}
311
312static int
313ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
314{
d1e3a356 315 return phy_ethtool_sset(dev->phydev, cmd);
504d4721
JC		 316}
317
318static int
319ltq_etop_nway_reset(struct net_device *dev)
320{
d1e3a356 321 return phy_start_aneg(dev->phydev);
504d4721
JC		 322}
323
324static const struct ethtool_ops ltq_etop_ethtool_ops = {
325 .get_drvinfo = ltq_etop_get_drvinfo,
326 .get_settings = ltq_etop_get_settings,
327 .set_settings = ltq_etop_set_settings,
328 .nway_reset = ltq_etop_nway_reset,
329};
330
331static int
332ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
333{
334 u32 val = MDIO_REQUEST |
335 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
336 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
337 phy_data;
338
339 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
340 ;
341 ltq_etop_w32(val, LTQ_ETOP_MDIO);
342 return 0;
343}
344
345static int
346ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
347{
348 u32 val = MDIO_REQUEST | MDIO_READ |
349 ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
350 ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
351
352 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
353 ;
354 ltq_etop_w32(val, LTQ_ETOP_MDIO);
355 while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
356 ;
357 val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
358 return val;
359}
360
361static void
362ltq_etop_mdio_link(struct net_device *dev)
363{
364 /* nothing to do */
365}
366
367static int
368ltq_etop_mdio_probe(struct net_device *dev)
369{
370 struct ltq_etop_priv *priv = netdev_priv(dev);
2a4fc4ea 371 struct phy_device *phydev;
504d4721 372
2a4fc4ea 373 phydev = phy_find_first(priv->mii_bus);
504d4721
JC		 374
375 if (!phydev) {
376 netdev_err(dev, "no PHY found\n");
377 return -ENODEV;
378 }
379
84eff6d1 380 phydev = phy_connect(dev, phydev_name(phydev),
f9a8f83b 381 &ltq_etop_mdio_link, priv->pldata->mii_mode);
504d4721
JC		 382
383 if (IS_ERR(phydev)) {
384 netdev_err(dev, "Could not attach to PHY\n");
385 return PTR_ERR(phydev);
386 }
387
388 phydev->supported &= (SUPPORTED_10baseT_Half
389 | SUPPORTED_10baseT_Full
390 | SUPPORTED_100baseT_Half
391 | SUPPORTED_100baseT_Full
392 | SUPPORTED_Autoneg
393 | SUPPORTED_MII
394 | SUPPORTED_TP);
395
396 phydev->advertising = phydev->supported;
2220943a 397 phy_attached_info(phydev);
504d4721
JC		 398
399 return 0;
400}
401
402static int
403ltq_etop_mdio_init(struct net_device *dev)
404{
405 struct ltq_etop_priv *priv = netdev_priv(dev);
504d4721
JC		 406 int err;
407
408 priv->mii_bus = mdiobus_alloc();
409 if (!priv->mii_bus) {
410 netdev_err(dev, "failed to allocate mii bus\n");
411 err = -ENOMEM;
412 goto err_out;
413 }
414
415 priv->mii_bus->priv = dev;
416 priv->mii_bus->read = ltq_etop_mdio_rd;
417 priv->mii_bus->write = ltq_etop_mdio_wr;
418 priv->mii_bus->name = "ltq_mii";
d1b86507
FF		 419 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
420 priv->pdev->name, priv->pdev->id);
504d4721
JC		 421 if (mdiobus_register(priv->mii_bus)) {
422 err = -ENXIO;
e7f4dc35 423 goto err_out_free_mdiobus;
504d4721
JC		 424 }
425
426 if (ltq_etop_mdio_probe(dev)) {
427 err = -ENXIO;
428 goto err_out_unregister_bus;
429 }
430 return 0;
431
432err_out_unregister_bus:
433 mdiobus_unregister(priv->mii_bus);
504d4721
JC		 434err_out_free_mdiobus:
435 mdiobus_free(priv->mii_bus);
436err_out:
437 return err;
438}
439
440static void
441ltq_etop_mdio_cleanup(struct net_device *dev)
442{
443 struct ltq_etop_priv *priv = netdev_priv(dev);
444
d1e3a356 445 phy_disconnect(dev->phydev);
504d4721 446 mdiobus_unregister(priv->mii_bus);
504d4721
JC		 447 mdiobus_free(priv->mii_bus);
448}
449
450static int
451ltq_etop_open(struct net_device *dev)
452{
453 struct ltq_etop_priv *priv = netdev_priv(dev);
454 int i;
455
456 for (i = 0; i < MAX_DMA_CHAN; i++) {
457 struct ltq_etop_chan *ch = &priv->ch[i];
458
459 if (!IS_TX(i) && (!IS_RX(i)))
460 continue;
461 ltq_dma_open(&ch->dma);
462 napi_enable(&ch->napi);
463 }
d1e3a356 464 phy_start(dev->phydev);
504d4721
JC		 465 netif_tx_start_all_queues(dev);
466 return 0;
467}
468
469static int
470ltq_etop_stop(struct net_device *dev)
471{
472 struct ltq_etop_priv *priv = netdev_priv(dev);
473 int i;
474
475 netif_tx_stop_all_queues(dev);
d1e3a356 476 phy_stop(dev->phydev);
504d4721
JC		 477 for (i = 0; i < MAX_DMA_CHAN; i++) {
478 struct ltq_etop_chan *ch = &priv->ch[i];
479
480 if (!IS_RX(i) && !IS_TX(i))
481 continue;
482 napi_disable(&ch->napi);
483 ltq_dma_close(&ch->dma);
484 }
485 return 0;
486}
487
488static int
489ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
490{
491 int queue = skb_get_queue_mapping(skb);
492 struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
493 struct ltq_etop_priv *priv = netdev_priv(dev);
494 struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
495 struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
496 int len;
497 unsigned long flags;
498 u32 byte_offset;
499
500 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
501
502 if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
503 dev_kfree_skb_any(skb);
504 netdev_err(dev, "tx ring full\n");
505 netif_tx_stop_queue(txq);
506 return NETDEV_TX_BUSY;
507 }
508
509 /* dma needs to start on a 16 byte aligned address */
510 byte_offset = CPHYSADDR(skb->data) % 16;
511 ch->skb[ch->dma.desc] = skb;
512
860e9538 513 netif_trans_update(dev);
504d4721
JC		 514
515 spin_lock_irqsave(&priv->lock, flags);
516 desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
517 DMA_TO_DEVICE)) - byte_offset;
518 wmb();
519 desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
520 LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
521 ch->dma.desc++;
522 ch->dma.desc %= LTQ_DESC_NUM;
523 spin_unlock_irqrestore(&priv->lock, flags);
524
525 if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
526 netif_tx_stop_queue(txq);
527
528 return NETDEV_TX_OK;
529}
530
531static int
532ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
533{
534 int ret = eth_change_mtu(dev, new_mtu);
535
536 if (!ret) {
537 struct ltq_etop_priv *priv = netdev_priv(dev);
538 unsigned long flags;
539
540 spin_lock_irqsave(&priv->lock, flags);
541 ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu,
542 LTQ_ETOP_IGPLEN);
543 spin_unlock_irqrestore(&priv->lock, flags);
544 }
545 return ret;
546}
547
548static int
549ltq_etop_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
550{
504d4721 551 /* TODO: mii-toll reports "No MII transceiver present!." ?!*/
d1e3a356 552 return phy_mii_ioctl(dev->phydev, rq, cmd);
504d4721
JC		 553}
554
555static int
556ltq_etop_set_mac_address(struct net_device *dev, void *p)
557{
558 int ret = eth_mac_addr(dev, p);
559
560 if (!ret) {
561 struct ltq_etop_priv *priv = netdev_priv(dev);
562 unsigned long flags;
563
564 /* store the mac for the unicast filter */
565 spin_lock_irqsave(&priv->lock, flags);
566 ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
567 ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
568 LTQ_ETOP_MAC_DA1);
569 spin_unlock_irqrestore(&priv->lock, flags);
570 }
571 return ret;
572}
573
574static void
575ltq_etop_set_multicast_list(struct net_device *dev)
576{
577 struct ltq_etop_priv *priv = netdev_priv(dev);
578 unsigned long flags;
579
580 /* ensure that the unicast filter is not enabled in promiscious mode */
581 spin_lock_irqsave(&priv->lock, flags);
582 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
583 ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
584 else
585 ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
586 spin_unlock_irqrestore(&priv->lock, flags);
587}
588
589static u16
f663dd9a 590ltq_etop_select_queue(struct net_device *dev, struct sk_buff *skb,
99932d4f 591 void *accel_priv, select_queue_fallback_t fallback)
504d4721
JC		 592{
593 /* we are currently only using the first queue */
594 return 0;
595}
596
597static int
598ltq_etop_init(struct net_device *dev)
599{
600 struct ltq_etop_priv *priv = netdev_priv(dev);
601 struct sockaddr mac;
602 int err;
43aabec5 603 bool random_mac = false;
504d4721 604
504d4721
JC		 605 dev->watchdog_timeo = 10 * HZ;
606 err = ltq_etop_hw_init(dev);
607 if (err)
608 goto err_hw;
609 ltq_etop_change_mtu(dev, 1500);
610
611 memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
612 if (!is_valid_ether_addr(mac.sa_data)) {
613 pr_warn("etop: invalid MAC, using random\n");
7efd26d0 614 eth_random_addr(mac.sa_data);
43aabec5 615 random_mac = true;
504d4721
JC		 616 }
617
618 err = ltq_etop_set_mac_address(dev, &mac);
619 if (err)
620 goto err_netdev;
43aabec5
DK		 621
622 /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
623 if (random_mac)
e41b2d7f 624 dev->addr_assign_type = NET_ADDR_RANDOM;
43aabec5 625
504d4721
JC		 626 ltq_etop_set_multicast_list(dev);
627 err = ltq_etop_mdio_init(dev);
628 if (err)
629 goto err_netdev;
630 return 0;
631
632err_netdev:
633 unregister_netdev(dev);
634 free_netdev(dev);
635err_hw:
636 ltq_etop_hw_exit(dev);
637 return err;
638}
639
640static void
641ltq_etop_tx_timeout(struct net_device *dev)
642{
643 int err;
644
645 ltq_etop_hw_exit(dev);
646 err = ltq_etop_hw_init(dev);
647 if (err)
648 goto err_hw;
860e9538 649 netif_trans_update(dev);
504d4721
JC		 650 netif_wake_queue(dev);
651 return;
652
653err_hw:
654 ltq_etop_hw_exit(dev);
655 netdev_err(dev, "failed to restart etop after TX timeout\n");
656}
657
658static const struct net_device_ops ltq_eth_netdev_ops = {
659 .ndo_open = ltq_etop_open,
660 .ndo_stop = ltq_etop_stop,
661 .ndo_start_xmit = ltq_etop_tx,
662 .ndo_change_mtu = ltq_etop_change_mtu,
663 .ndo_do_ioctl = ltq_etop_ioctl,
664 .ndo_set_mac_address = ltq_etop_set_mac_address,
665 .ndo_validate_addr = eth_validate_addr,
afc4b13d 666 .ndo_set_rx_mode = ltq_etop_set_multicast_list,
504d4721
JC		 667 .ndo_select_queue = ltq_etop_select_queue,
668 .ndo_init = ltq_etop_init,
669 .ndo_tx_timeout = ltq_etop_tx_timeout,
670};
671
672static int __init
673ltq_etop_probe(struct platform_device *pdev)
674{
675 struct net_device *dev;
676 struct ltq_etop_priv *priv;
677 struct resource *res;
678 int err;
679 int i;
680
681 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
682 if (!res) {
683 dev_err(&pdev->dev, "failed to get etop resource\n");
684 err = -ENOENT;
685 goto err_out;
686 }
687
688 res = devm_request_mem_region(&pdev->dev, res->start,
689 resource_size(res), dev_name(&pdev->dev));
690 if (!res) {
691 dev_err(&pdev->dev, "failed to request etop resource\n");
692 err = -EBUSY;
693 goto err_out;
694 }
695
696 ltq_etop_membase = devm_ioremap_nocache(&pdev->dev,
697 res->start, resource_size(res));
698 if (!ltq_etop_membase) {
699 dev_err(&pdev->dev, "failed to remap etop engine %d\n",
700 pdev->id);
701 err = -ENOMEM;
702 goto err_out;
703 }
704
705 dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
41de8d4c
JP		 706 if (!dev) {
707 err = -ENOMEM;
708 goto err_out;
709 }
504d4721
JC		 710 strcpy(dev->name, "eth%d");
711 dev->netdev_ops = &ltq_eth_netdev_ops;
712 dev->ethtool_ops = &ltq_etop_ethtool_ops;
713 priv = netdev_priv(dev);
714 priv->res = res;
d1b86507 715 priv->pdev = pdev;
504d4721
JC		 716 priv->pldata = dev_get_platdata(&pdev->dev);
717 priv->netdev = dev;
718 spin_lock_init(&priv->lock);
719
720 for (i = 0; i < MAX_DMA_CHAN; i++) {
721 if (IS_TX(i))
722 netif_napi_add(dev, &priv->ch[i].napi,
723 ltq_etop_poll_tx, 8);
724 else if (IS_RX(i))
725 netif_napi_add(dev, &priv->ch[i].napi,
726 ltq_etop_poll_rx, 32);
727 priv->ch[i].netdev = dev;
728 }
729
730 err = register_netdev(dev);
731 if (err)
732 goto err_free;
733
734 platform_set_drvdata(pdev, dev);
735 return 0;
736
737err_free:
cb0e51d8 738 free_netdev(dev);
504d4721
JC		 739err_out:
740 return err;
741}
742
a0a4efed 743static int
504d4721
JC		 744ltq_etop_remove(struct platform_device *pdev)
745{
746 struct net_device *dev = platform_get_drvdata(pdev);
747
748 if (dev) {
749 netif_tx_stop_all_queues(dev);
750 ltq_etop_hw_exit(dev);
751 ltq_etop_mdio_cleanup(dev);
752 unregister_netdev(dev);
753 }
754 return 0;
755}
756
757static struct platform_driver ltq_mii_driver = {
a0a4efed 758 .remove = ltq_etop_remove,
504d4721
JC		 759 .driver = {
760 .name = "ltq_etop",
504d4721
JC		 761 },
762};
763
764int __init
765init_ltq_etop(void)
766{
767 int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
768
769 if (ret)
772301b6 770 pr_err("ltq_etop: Error registering platform driver!");
504d4721
JC		 771 return ret;
772}
773
774static void __exit
775exit_ltq_etop(void)
776{
777 platform_driver_unregister(&ltq_mii_driver);
778}
779
780module_init(init_ltq_etop);
781module_exit(exit_ltq_etop);
782
783MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
784MODULE_DESCRIPTION("Lantiq SoC ETOP");
785MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.409767 seconds and 5 git commands to generate.