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Merge branch 'clk/mxs-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6...
[deliverable/linux.git] / drivers / net / ethernet / marvell / mv643xx_eth.c
CommitLineData
1da177e4 1/*
9c1bbdfe 2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
1da177e4
LT		 3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
4547fa61
LB		 6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
1da177e4
LT		 8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
3bb8a18a 10 * written by Manish Lachwani
1da177e4
LT		 11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
c8aaea25 14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
1da177e4
LT		 15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
4547fa61
LB		 20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
1da177e4
LT		 23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
a779d38c 37
7542db8b
JP		 38#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
39
1da177e4
LT		 40#include <linux/init.h>
41#include <linux/dma-mapping.h>
b6298c22 42#include <linux/in.h>
c3efab8e 43#include <linux/ip.h>
1da177e4
LT		 44#include <linux/tcp.h>
45#include <linux/udp.h>
46#include <linux/etherdevice.h>
1da177e4
LT		 47#include <linux/delay.h>
48#include <linux/ethtool.h>
d052d1be 49#include <linux/platform_device.h>
fbd6a754
LB		 50#include <linux/module.h>
51#include <linux/kernel.h>
52#include <linux/spinlock.h>
53#include <linux/workqueue.h>
ed94493f 54#include <linux/phy.h>
fbd6a754 55#include <linux/mv643xx_eth.h>
10a9948d
LB		 56#include <linux/io.h>
57#include <linux/types.h>
eaf5d590 58#include <linux/inet_lro.h>
5a0e3ad6 59#include <linux/slab.h>
452503eb 60#include <linux/clk.h>
fbd6a754 61
e5371493 62static char mv643xx_eth_driver_name[] = "mv643xx_eth";
042af53c 63static char mv643xx_eth_driver_version[] = "1.4";
c9df406f 64
fbd6a754 65
fbd6a754
LB		 66/*
67 * Registers shared between all ports.
68 */
3cb4667c
LB		 69#define PHY_ADDR 0x0000
70#define SMI_REG 0x0004
45c5d3bc
LB		 71#define SMI_BUSY 0x10000000
72#define SMI_READ_VALID 0x08000000
73#define SMI_OPCODE_READ 0x04000000
74#define SMI_OPCODE_WRITE 0x00000000
75#define ERR_INT_CAUSE 0x0080
76#define ERR_INT_SMI_DONE 0x00000010
77#define ERR_INT_MASK 0x0084
3cb4667c
LB		 78#define WINDOW_BASE(w) (0x0200 + ((w) << 3))
79#define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
80#define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
81#define WINDOW_BAR_ENABLE 0x0290
82#define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
fbd6a754
LB		 83
84/*
37a6084f
LB		 85 * Main per-port registers. These live at offset 0x0400 for
86 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
fbd6a754 87 */
37a6084f 88#define PORT_CONFIG 0x0000
d9a073ea 89#define UNICAST_PROMISCUOUS_MODE 0x00000001
37a6084f
LB		 90#define PORT_CONFIG_EXT 0x0004
91#define MAC_ADDR_LOW 0x0014
92#define MAC_ADDR_HIGH 0x0018
93#define SDMA_CONFIG 0x001c
becfad97
LB		 94#define TX_BURST_SIZE_16_64BIT 0x01000000
95#define TX_BURST_SIZE_4_64BIT 0x00800000
96#define BLM_TX_NO_SWAP 0x00000020
97#define BLM_RX_NO_SWAP 0x00000010
98#define RX_BURST_SIZE_16_64BIT 0x00000008
99#define RX_BURST_SIZE_4_64BIT 0x00000004
37a6084f 100#define PORT_SERIAL_CONTROL 0x003c
becfad97
LB		 101#define SET_MII_SPEED_TO_100 0x01000000
102#define SET_GMII_SPEED_TO_1000 0x00800000
103#define SET_FULL_DUPLEX_MODE 0x00200000
104#define MAX_RX_PACKET_9700BYTE 0x000a0000
105#define DISABLE_AUTO_NEG_SPEED_GMII 0x00002000
106#define DO_NOT_FORCE_LINK_FAIL 0x00000400
107#define SERIAL_PORT_CONTROL_RESERVED 0x00000200
108#define DISABLE_AUTO_NEG_FOR_FLOW_CTRL 0x00000008
109#define DISABLE_AUTO_NEG_FOR_DUPLEX 0x00000004
110#define FORCE_LINK_PASS 0x00000002
111#define SERIAL_PORT_ENABLE 0x00000001
37a6084f 112#define PORT_STATUS 0x0044
a2a41689 113#define TX_FIFO_EMPTY 0x00000400
ae9ae064 114#define TX_IN_PROGRESS 0x00000080
2f7eb47a
LB		 115#define PORT_SPEED_MASK 0x00000030
116#define PORT_SPEED_1000 0x00000010
117#define PORT_SPEED_100 0x00000020
118#define PORT_SPEED_10 0x00000000
119#define FLOW_CONTROL_ENABLED 0x00000008
120#define FULL_DUPLEX 0x00000004
81600eea 121#define LINK_UP 0x00000002
37a6084f
LB		 122#define TXQ_COMMAND 0x0048
123#define TXQ_FIX_PRIO_CONF 0x004c
124#define TX_BW_RATE 0x0050
125#define TX_BW_MTU 0x0058
126#define TX_BW_BURST 0x005c
127#define INT_CAUSE 0x0060
226bb6b7 128#define INT_TX_END 0x07f80000
e0ca8410 129#define INT_TX_END_0 0x00080000
befefe21 130#define INT_RX 0x000003fc
e0ca8410 131#define INT_RX_0 0x00000004
073a345c 132#define INT_EXT 0x00000002
37a6084f 133#define INT_CAUSE_EXT 0x0064
befefe21
LB		 134#define INT_EXT_LINK_PHY 0x00110000
135#define INT_EXT_TX 0x000000ff
37a6084f
LB		 136#define INT_MASK 0x0068
137#define INT_MASK_EXT 0x006c
138#define TX_FIFO_URGENT_THRESHOLD 0x0074
302476c9
PZ		 139#define RX_DISCARD_FRAME_CNT 0x0084
140#define RX_OVERRUN_FRAME_CNT 0x0088
37a6084f
LB		 141#define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
142#define TX_BW_RATE_MOVED 0x00e0
143#define TX_BW_MTU_MOVED 0x00e8
144#define TX_BW_BURST_MOVED 0x00ec
145#define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
146#define RXQ_COMMAND 0x0280
147#define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
148#define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
149#define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
150#define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
151
152/*
153 * Misc per-port registers.
154 */
3cb4667c
LB		 155#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
156#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
157#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
158#define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
fbd6a754 159
2679a550
LB		 160
161/*
becfad97 162 * SDMA configuration register default value.
2679a550 163 */
fbd6a754
LB		 164#if defined(__BIG_ENDIAN)
165#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 166 (RX_BURST_SIZE_4_64BIT | \
167 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 168#elif defined(__LITTLE_ENDIAN)
169#define PORT_SDMA_CONFIG_DEFAULT_VALUE \
e0c6ef93
LB		 170 (RX_BURST_SIZE_4_64BIT | \
171 BLM_RX_NO_SWAP | \
172 BLM_TX_NO_SWAP | \
173 TX_BURST_SIZE_4_64BIT)
fbd6a754
LB		 174#else
175#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
176#endif
177
2beff77b
LB		 178
179/*
becfad97 180 * Misc definitions.
2beff77b 181 */
becfad97
LB		 182#define DEFAULT_RX_QUEUE_SIZE 128
183#define DEFAULT_TX_QUEUE_SIZE 256
7fd96ce4 184#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
fbd6a754 185
fbd6a754 186
7ca72a3b
LB		 187/*
188 * RX/TX descriptors.
fbd6a754
LB		 189 */
190#if defined(__BIG_ENDIAN)
cc9754b3 191struct rx_desc {
fbd6a754
LB		 192 u16 byte_cnt; /* Descriptor buffer byte count */
193 u16 buf_size; /* Buffer size */
194 u32 cmd_sts; /* Descriptor command status */
195 u32 next_desc_ptr; /* Next descriptor pointer */
196 u32 buf_ptr; /* Descriptor buffer pointer */
197};
198
cc9754b3 199struct tx_desc {
fbd6a754
LB		 200 u16 byte_cnt; /* buffer byte count */
201 u16 l4i_chk; /* CPU provided TCP checksum */
202 u32 cmd_sts; /* Command/status field */
203 u32 next_desc_ptr; /* Pointer to next descriptor */
204 u32 buf_ptr; /* pointer to buffer for this descriptor*/
205};
206#elif defined(__LITTLE_ENDIAN)
cc9754b3 207struct rx_desc {
fbd6a754
LB		 208 u32 cmd_sts; /* Descriptor command status */
209 u16 buf_size; /* Buffer size */
210 u16 byte_cnt; /* Descriptor buffer byte count */
211 u32 buf_ptr; /* Descriptor buffer pointer */
212 u32 next_desc_ptr; /* Next descriptor pointer */
213};
214
cc9754b3 215struct tx_desc {
fbd6a754
LB		 216 u32 cmd_sts; /* Command/status field */
217 u16 l4i_chk; /* CPU provided TCP checksum */
218 u16 byte_cnt; /* buffer byte count */
219 u32 buf_ptr; /* pointer to buffer for this descriptor*/
220 u32 next_desc_ptr; /* Pointer to next descriptor */
221};
222#else
223#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
224#endif
225
7ca72a3b 226/* RX & TX descriptor command */
cc9754b3 227#define BUFFER_OWNED_BY_DMA 0x80000000
7ca72a3b
LB		 228
229/* RX & TX descriptor status */
cc9754b3 230#define ERROR_SUMMARY 0x00000001
7ca72a3b
LB		 231
232/* RX descriptor status */
cc9754b3
LB		 233#define LAYER_4_CHECKSUM_OK 0x40000000
234#define RX_ENABLE_INTERRUPT 0x20000000
235#define RX_FIRST_DESC 0x08000000
236#define RX_LAST_DESC 0x04000000
eaf5d590
LB		 237#define RX_IP_HDR_OK 0x02000000
238#define RX_PKT_IS_IPV4 0x01000000
239#define RX_PKT_IS_ETHERNETV2 0x00800000
240#define RX_PKT_LAYER4_TYPE_MASK 0x00600000
241#define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
242#define RX_PKT_IS_VLAN_TAGGED 0x00080000
7ca72a3b
LB		 243
244/* TX descriptor command */
cc9754b3
LB		 245#define TX_ENABLE_INTERRUPT 0x00800000
246#define GEN_CRC 0x00400000
247#define TX_FIRST_DESC 0x00200000
248#define TX_LAST_DESC 0x00100000
249#define ZERO_PADDING 0x00080000
250#define GEN_IP_V4_CHECKSUM 0x00040000
251#define GEN_TCP_UDP_CHECKSUM 0x00020000
252#define UDP_FRAME 0x00010000
e32b6617
LB		 253#define MAC_HDR_EXTRA_4_BYTES 0x00008000
254#define MAC_HDR_EXTRA_8_BYTES 0x00000200
7ca72a3b 255
cc9754b3 256#define TX_IHL_SHIFT 11
7ca72a3b
LB		 257
258
c9df406f 259/* global *******************************************************************/
e5371493 260struct mv643xx_eth_shared_private {
fc32b0e2
LB		 261 /*
262 * Ethernet controller base address.
263 */
cc9754b3 264 void __iomem *base;
c9df406f 265
fc0eb9f2
LB		 266 /*
267 * Points at the right SMI instance to use.
268 */
269 struct mv643xx_eth_shared_private *smi;
270
fc32b0e2 271 /*
ed94493f 272 * Provides access to local SMI interface.
fc32b0e2 273 */
298cf9be 274 struct mii_bus *smi_bus;
c9df406f 275
45c5d3bc
LB		 276 /*
277 * If we have access to the error interrupt pin (which is
278 * somewhat misnamed as it not only reflects internal errors
279 * but also reflects SMI completion), use that to wait for
280 * SMI access completion instead of polling the SMI busy bit.
281 */
282 int err_interrupt;
283 wait_queue_head_t smi_busy_wait;
284
fc32b0e2
LB		 285 /*
286 * Per-port MBUS window access register value.
287 */
c9df406f
LB		 288 u32 win_protect;
289
fc32b0e2
LB		 290 /*
291 * Hardware-specific parameters.
292 */
773fc3ee 293 int extended_rx_coal_limit;
457b1d5a 294 int tx_bw_control;
9b2c2ff7 295 int tx_csum_limit;
452503eb 296
c9df406f
LB		 297};
298
457b1d5a
LB		 299#define TX_BW_CONTROL_ABSENT 0
300#define TX_BW_CONTROL_OLD_LAYOUT 1
301#define TX_BW_CONTROL_NEW_LAYOUT 2
302
e7d2f4db
LB		 303static int mv643xx_eth_open(struct net_device *dev);
304static int mv643xx_eth_stop(struct net_device *dev);
305
c9df406f
LB		 306
307/* per-port *****************************************************************/
e5371493 308struct mib_counters {
fbd6a754
LB		 309 u64 good_octets_received;
310 u32 bad_octets_received;
311 u32 internal_mac_transmit_err;
312 u32 good_frames_received;
313 u32 bad_frames_received;
314 u32 broadcast_frames_received;
315 u32 multicast_frames_received;
316 u32 frames_64_octets;
317 u32 frames_65_to_127_octets;
318 u32 frames_128_to_255_octets;
319 u32 frames_256_to_511_octets;
320 u32 frames_512_to_1023_octets;
321 u32 frames_1024_to_max_octets;
322 u64 good_octets_sent;
323 u32 good_frames_sent;
324 u32 excessive_collision;
325 u32 multicast_frames_sent;
326 u32 broadcast_frames_sent;
327 u32 unrec_mac_control_received;
328 u32 fc_sent;
329 u32 good_fc_received;
330 u32 bad_fc_received;
331 u32 undersize_received;
332 u32 fragments_received;
333 u32 oversize_received;
334 u32 jabber_received;
335 u32 mac_receive_error;
336 u32 bad_crc_event;
337 u32 collision;
338 u32 late_collision;
302476c9
PZ		 339 /* Non MIB hardware counters */
340 u32 rx_discard;
341 u32 rx_overrun;
fbd6a754
LB		 342};
343
eaf5d590
LB		 344struct lro_counters {
345 u32 lro_aggregated;
346 u32 lro_flushed;
347 u32 lro_no_desc;
348};
349
8a578111 350struct rx_queue {
64da80a2
LB		 351 int index;
352
8a578111
LB		 353 int rx_ring_size;
354
355 int rx_desc_count;
356 int rx_curr_desc;
357 int rx_used_desc;
358
359 struct rx_desc *rx_desc_area;
360 dma_addr_t rx_desc_dma;
361 int rx_desc_area_size;
362 struct sk_buff **rx_skb;
eaf5d590 363
eaf5d590
LB		 364 struct net_lro_mgr lro_mgr;
365 struct net_lro_desc lro_arr[8];
8a578111
LB		 366};
367
13d64285 368struct tx_queue {
3d6b35bc
LB		 369 int index;
370
13d64285 371 int tx_ring_size;
fbd6a754 372
13d64285
LB		 373 int tx_desc_count;
374 int tx_curr_desc;
375 int tx_used_desc;
fbd6a754 376
5daffe94 377 struct tx_desc *tx_desc_area;
fbd6a754
LB		 378 dma_addr_t tx_desc_dma;
379 int tx_desc_area_size;
99ab08e0
LB		 380
381 struct sk_buff_head tx_skb;
8fd89211
LB		 382
383 unsigned long tx_packets;
384 unsigned long tx_bytes;
385 unsigned long tx_dropped;
13d64285
LB		 386};
387
388struct mv643xx_eth_private {
389 struct mv643xx_eth_shared_private *shared;
37a6084f 390 void __iomem *base;
fc32b0e2 391 int port_num;
13d64285 392
fc32b0e2 393 struct net_device *dev;
fbd6a754 394
ed94493f 395 struct phy_device *phy;
fbd6a754 396
4ff3495a
LB		 397 struct timer_list mib_counters_timer;
398 spinlock_t mib_counters_lock;
fc32b0e2 399 struct mib_counters mib_counters;
4ff3495a 400
eaf5d590
LB		 401 struct lro_counters lro_counters;
402
fc32b0e2 403 struct work_struct tx_timeout_task;
8a578111 404
1fa38c58 405 struct napi_struct napi;
e0ca8410 406 u32 int_mask;
1319ebad 407 u8 oom;
1fa38c58
LB		 408 u8 work_link;
409 u8 work_tx;
410 u8 work_tx_end;
411 u8 work_rx;
412 u8 work_rx_refill;
1fa38c58 413
2bcb4b0f
LB		 414 int skb_size;
415 struct sk_buff_head rx_recycle;
416
8a578111
LB		 417 /*
418 * RX state.
419 */
e7d2f4db 420 int rx_ring_size;
8a578111
LB		 421 unsigned long rx_desc_sram_addr;
422 int rx_desc_sram_size;
f7981c1c 423 int rxq_count;
2257e05c 424 struct timer_list rx_oom;
64da80a2 425 struct rx_queue rxq[8];
13d64285
LB		 426
427 /*
428 * TX state.
429 */
e7d2f4db 430 int tx_ring_size;
13d64285
LB		 431 unsigned long tx_desc_sram_addr;
432 int tx_desc_sram_size;
f7981c1c 433 int txq_count;
3d6b35bc 434 struct tx_queue txq[8];
452503eb
AL		 435
436 /*
437 * Hardware-specific parameters.
438 */
9a43a026 439#if defined(CONFIG_HAVE_CLK)
452503eb 440 struct clk *clk;
9a43a026 441#endif
452503eb 442 unsigned int t_clk;
fbd6a754 443};
1da177e4 444
fbd6a754 445
c9df406f 446/* port register accessors **************************************************/
e5371493 447static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
c9df406f 448{
cc9754b3 449 return readl(mp->shared->base + offset);
c9df406f 450}
fbd6a754 451
37a6084f
LB		 452static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
453{
454 return readl(mp->base + offset);
455}
456
e5371493 457static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
c9df406f 458{
cc9754b3 459 writel(data, mp->shared->base + offset);
c9df406f 460}
fbd6a754 461
37a6084f
LB		 462static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
463{
464 writel(data, mp->base + offset);
465}
466
fbd6a754 467
c9df406f 468/* rxq/txq helper functions *************************************************/
8a578111 469static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
c9df406f 470{
64da80a2 471 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
c9df406f 472}
fbd6a754 473
13d64285
LB		 474static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
475{
3d6b35bc 476 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
13d64285
LB		 477}
478
8a578111 479static void rxq_enable(struct rx_queue *rxq)
c9df406f 480{
8a578111 481 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
37a6084f 482 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
8a578111 483}
1da177e4 484
8a578111
LB		 485static void rxq_disable(struct rx_queue *rxq)
486{
487 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
64da80a2 488 u8 mask = 1 << rxq->index;
1da177e4 489
37a6084f
LB		 490 wrlp(mp, RXQ_COMMAND, mask << 8);
491 while (rdlp(mp, RXQ_COMMAND) & mask)
8a578111 492 udelay(10);
c9df406f
LB		 493}
494
6b368f68
LB		 495static void txq_reset_hw_ptr(struct tx_queue *txq)
496{
497 struct mv643xx_eth_private *mp = txq_to_mp(txq);
6b368f68
LB		 498 u32 addr;
499
500 addr = (u32)txq->tx_desc_dma;
501 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
37a6084f 502 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
6b368f68
LB		 503}
504
13d64285 505static void txq_enable(struct tx_queue *txq)
1da177e4 506{
13d64285 507 struct mv643xx_eth_private *mp = txq_to_mp(txq);
37a6084f 508 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
1da177e4
LT		 509}
510
13d64285 511static void txq_disable(struct tx_queue *txq)
1da177e4 512{
13d64285 513 struct mv643xx_eth_private *mp = txq_to_mp(txq);
3d6b35bc 514 u8 mask = 1 << txq->index;
c9df406f 515
37a6084f
LB		 516 wrlp(mp, TXQ_COMMAND, mask << 8);
517 while (rdlp(mp, TXQ_COMMAND) & mask)
13d64285
LB		 518 udelay(10);
519}
520
1fa38c58 521static void txq_maybe_wake(struct tx_queue *txq)
13d64285
LB		 522{
523 struct mv643xx_eth_private *mp = txq_to_mp(txq);
e5ef1de1 524 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
3d6b35bc 525
8fd89211
LB		 526 if (netif_tx_queue_stopped(nq)) {
527 __netif_tx_lock(nq, smp_processor_id());
528 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
529 netif_tx_wake_queue(nq);
530 __netif_tx_unlock(nq);
531 }
1da177e4
LT		 532}
533
c9df406f 534
1fa38c58 535/* rx napi ******************************************************************/
eaf5d590
LB		 536static int
537mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
538 u64 *hdr_flags, void *priv)
539{
540 unsigned long cmd_sts = (unsigned long)priv;
541
542 /*
543 * Make sure that this packet is Ethernet II, is not VLAN
544 * tagged, is IPv4, has a valid IP header, and is TCP.
545 */
546 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
547 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
548 RX_PKT_IS_VLAN_TAGGED)) !=
549 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
550 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
551 return -1;
552
553 skb_reset_network_header(skb);
554 skb_set_transport_header(skb, ip_hdrlen(skb));
555 *iphdr = ip_hdr(skb);
556 *tcph = tcp_hdr(skb);
557 *hdr_flags = LRO_IPV4 | LRO_TCP;
558
559 return 0;
560}
eaf5d590 561
8a578111 562static int rxq_process(struct rx_queue *rxq, int budget)
1da177e4 563{
8a578111
LB		 564 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
565 struct net_device_stats *stats = &mp->dev->stats;
eaf5d590 566 int lro_flush_needed;
8a578111 567 int rx;
1da177e4 568
eaf5d590 569 lro_flush_needed = 0;
8a578111 570 rx = 0;
9e1f3772 571 while (rx < budget && rxq->rx_desc_count) {
fc32b0e2 572 struct rx_desc *rx_desc;
96587661 573 unsigned int cmd_sts;
fc32b0e2 574 struct sk_buff *skb;
6b8f90c2 575 u16 byte_cnt;
ff561eef 576
8a578111 577 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
1da177e4 578
96587661 579 cmd_sts = rx_desc->cmd_sts;
2257e05c 580 if (cmd_sts & BUFFER_OWNED_BY_DMA)
96587661 581 break;
96587661 582 rmb();
1da177e4 583
8a578111
LB		 584 skb = rxq->rx_skb[rxq->rx_curr_desc];
585 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
ff561eef 586
9da78745
LB		 587 rxq->rx_curr_desc++;
588 if (rxq->rx_curr_desc == rxq->rx_ring_size)
589 rxq->rx_curr_desc = 0;
ff561eef 590
eb0519b5 591 dma_unmap_single(mp->dev->dev.parent, rx_desc->buf_ptr,
abe78717 592 rx_desc->buf_size, DMA_FROM_DEVICE);
8a578111
LB		 593 rxq->rx_desc_count--;
594 rx++;
b1dd9ca1 595
1fa38c58
LB		 596 mp->work_rx_refill |= 1 << rxq->index;
597
6b8f90c2
LB		 598 byte_cnt = rx_desc->byte_cnt;
599
468d09f8
DF		 600 /*
601 * Update statistics.
fc32b0e2
LB		 602 *
603 * Note that the descriptor byte count includes 2 dummy
604 * bytes automatically inserted by the hardware at the
605 * start of the packet (which we don't count), and a 4
606 * byte CRC at the end of the packet (which we do count).
468d09f8 607 */
1da177e4 608 stats->rx_packets++;
6b8f90c2 609 stats->rx_bytes += byte_cnt - 2;
96587661 610
1da177e4 611 /*
fc32b0e2
LB		 612 * In case we received a packet without first / last bits
613 * on, or the error summary bit is set, the packet needs
614 * to be dropped.
1da177e4 615 */
f61e5547
LB		 616 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
617 != (RX_FIRST_DESC | RX_LAST_DESC))
618 goto err;
619
620 /*
621 * The -4 is for the CRC in the trailer of the
622 * received packet
623 */
624 skb_put(skb, byte_cnt - 2 - 4);
625
626 if (cmd_sts & LAYER_4_CHECKSUM_OK)
627 skb->ip_summed = CHECKSUM_UNNECESSARY;
628 skb->protocol = eth_type_trans(skb, mp->dev);
eaf5d590 629
eaf5d590
LB		 630 if (skb->dev->features & NETIF_F_LRO &&
631 skb->ip_summed == CHECKSUM_UNNECESSARY) {
632 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
633 lro_flush_needed = 1;
634 } else
eaf5d590 635 netif_receive_skb(skb);
f61e5547
LB		 636
637 continue;
638
639err:
640 stats->rx_dropped++;
641
642 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
643 (RX_FIRST_DESC | RX_LAST_DESC)) {
644 if (net_ratelimit())
7542db8b
JP		 645 netdev_err(mp->dev,
646 "received packet spanning multiple descriptors\n");
1da177e4 647 }
f61e5547
LB		 648
649 if (cmd_sts & ERROR_SUMMARY)
650 stats->rx_errors++;
651
652 dev_kfree_skb(skb);
1da177e4 653 }
fc32b0e2 654
eaf5d590
LB		 655 if (lro_flush_needed)
656 lro_flush_all(&rxq->lro_mgr);
eaf5d590 657
1fa38c58
LB		 658 if (rx < budget)
659 mp->work_rx &= ~(1 << rxq->index);
660
8a578111 661 return rx;
1da177e4
LT		 662}
663
1fa38c58 664static int rxq_refill(struct rx_queue *rxq, int budget)
d0412d96 665{
1fa38c58 666 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1fa38c58 667 int refilled;
8a578111 668
1fa38c58
LB		 669 refilled = 0;
670 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
671 struct sk_buff *skb;
1fa38c58 672 int rx;
53771522 673 struct rx_desc *rx_desc;
530e557a 674 int size;
d0412d96 675
2bcb4b0f
LB		 676 skb = __skb_dequeue(&mp->rx_recycle);
677 if (skb == NULL)
c056b734 678 skb = netdev_alloc_skb(mp->dev, mp->skb_size);
2bcb4b0f 679
1fa38c58 680 if (skb == NULL) {
1319ebad 681 mp->oom = 1;
1fa38c58
LB		 682 goto oom;
683 }
d0412d96 684
7fd96ce4
LB		 685 if (SKB_DMA_REALIGN)
686 skb_reserve(skb, SKB_DMA_REALIGN);
2257e05c 687
1fa38c58
LB		 688 refilled++;
689 rxq->rx_desc_count++;
c9df406f 690
1fa38c58
LB		 691 rx = rxq->rx_used_desc++;
692 if (rxq->rx_used_desc == rxq->rx_ring_size)
693 rxq->rx_used_desc = 0;
2257e05c 694
53771522
LB		 695 rx_desc = rxq->rx_desc_area + rx;
696
530e557a 697 size = skb->end - skb->data;
eb0519b5 698 rx_desc->buf_ptr = dma_map_single(mp->dev->dev.parent,
530e557a 699 skb->data, size,
eb0519b5 700 DMA_FROM_DEVICE);
530e557a 701 rx_desc->buf_size = size;
1fa38c58
LB		 702 rxq->rx_skb[rx] = skb;
703 wmb();
53771522 704 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
1fa38c58 705 wmb();
2257e05c 706
1fa38c58
LB		 707 /*
708 * The hardware automatically prepends 2 bytes of
709 * dummy data to each received packet, so that the
710 * IP header ends up 16-byte aligned.
711 */
712 skb_reserve(skb, 2);
713 }
714
715 if (refilled < budget)
716 mp->work_rx_refill &= ~(1 << rxq->index);
717
718oom:
719 return refilled;
d0412d96
JC		 720}
721
c9df406f
LB		 722
723/* tx ***********************************************************************/
c9df406f 724static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1da177e4 725{
13d64285 726 int frag;
1da177e4 727
c9df406f 728 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
9e903e08
ED		 729 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
730
731 if (skb_frag_size(fragp) <= 8 && fragp->page_offset & 7)
c9df406f 732 return 1;
1da177e4 733 }
13d64285 734
c9df406f
LB		 735 return 0;
736}
7303fde8 737
13d64285 738static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
c9df406f 739{
eb0519b5 740 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 741 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 742 int frag;
1da177e4 743
13d64285
LB		 744 for (frag = 0; frag < nr_frags; frag++) {
745 skb_frag_t *this_frag;
746 int tx_index;
747 struct tx_desc *desc;
748
749 this_frag = &skb_shinfo(skb)->frags[frag];
66823b92
LB		 750 tx_index = txq->tx_curr_desc++;
751 if (txq->tx_curr_desc == txq->tx_ring_size)
752 txq->tx_curr_desc = 0;
13d64285
LB		 753 desc = &txq->tx_desc_area[tx_index];
754
755 /*
756 * The last fragment will generate an interrupt
757 * which will free the skb on TX completion.
758 */
759 if (frag == nr_frags - 1) {
760 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
761 ZERO_PADDING | TX_LAST_DESC |
762 TX_ENABLE_INTERRUPT;
13d64285
LB		 763 } else {
764 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
13d64285
LB		 765 }
766
c9df406f 767 desc->l4i_chk = 0;
9e903e08 768 desc->byte_cnt = skb_frag_size(this_frag);
f106358b
IC		 769 desc->buf_ptr = skb_frag_dma_map(mp->dev->dev.parent,
770 this_frag, 0,
9e903e08 771 skb_frag_size(this_frag),
f106358b 772 DMA_TO_DEVICE);
c9df406f 773 }
1da177e4
LT		 774}
775
c9df406f
LB		 776static inline __be16 sum16_as_be(__sum16 sum)
777{
778 return (__force __be16)sum;
779}
1da177e4 780
4df89bd5 781static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
1da177e4 782{
8fa89bf5 783 struct mv643xx_eth_private *mp = txq_to_mp(txq);
13d64285 784 int nr_frags = skb_shinfo(skb)->nr_frags;
c9df406f 785 int tx_index;
cc9754b3 786 struct tx_desc *desc;
c9df406f 787 u32 cmd_sts;
4df89bd5 788 u16 l4i_chk;
c9df406f 789 int length;
1da177e4 790
cc9754b3 791 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
4df89bd5 792 l4i_chk = 0;
c9df406f
LB		 793
794 if (skb->ip_summed == CHECKSUM_PARTIAL) {
9b2c2ff7 795 int hdr_len;
4df89bd5 796 int tag_bytes;
e32b6617
LB		 797
798 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
799 skb->protocol != htons(ETH_P_8021Q));
c9df406f 800
9b2c2ff7
SB		 801 hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
802 tag_bytes = hdr_len - ETH_HLEN;
803 if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
804 unlikely(tag_bytes & ~12)) {
4df89bd5
LB		 805 if (skb_checksum_help(skb) == 0)
806 goto no_csum;
807 kfree_skb(skb);
808 return 1;
809 }
c9df406f 810
4df89bd5 811 if (tag_bytes & 4)
e32b6617 812 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
4df89bd5 813 if (tag_bytes & 8)
e32b6617 814 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
4df89bd5
LB		 815
816 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
817 GEN_IP_V4_CHECKSUM |
818 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
e32b6617 819
c9df406f
LB		 820 switch (ip_hdr(skb)->protocol) {
821 case IPPROTO_UDP:
cc9754b3 822 cmd_sts |= UDP_FRAME;
4df89bd5 823 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
c9df406f
LB		 824 break;
825 case IPPROTO_TCP:
4df89bd5 826 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
c9df406f
LB		 827 break;
828 default:
829 BUG();
830 }
831 } else {
4df89bd5 832no_csum:
c9df406f 833 /* Errata BTS #50, IHL must be 5 if no HW checksum */
cc9754b3 834 cmd_sts |= 5 << TX_IHL_SHIFT;
c9df406f
LB		 835 }
836
66823b92
LB		 837 tx_index = txq->tx_curr_desc++;
838 if (txq->tx_curr_desc == txq->tx_ring_size)
839 txq->tx_curr_desc = 0;
4df89bd5
LB		 840 desc = &txq->tx_desc_area[tx_index];
841
842 if (nr_frags) {
843 txq_submit_frag_skb(txq, skb);
844 length = skb_headlen(skb);
845 } else {
846 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
847 length = skb->len;
848 }
849
850 desc->l4i_chk = l4i_chk;
851 desc->byte_cnt = length;
eb0519b5
GP		 852 desc->buf_ptr = dma_map_single(mp->dev->dev.parent, skb->data,
853 length, DMA_TO_DEVICE);
4df89bd5 854
99ab08e0
LB		 855 __skb_queue_tail(&txq->tx_skb, skb);
856
3b182d7d
RC		 857 skb_tx_timestamp(skb);
858
c9df406f
LB		 859 /* ensure all other descriptors are written before first cmd_sts */
860 wmb();
861 desc->cmd_sts = cmd_sts;
862
1fa38c58
LB		 863 /* clear TX_END status */
864 mp->work_tx_end &= ~(1 << txq->index);
8fa89bf5 865
c9df406f
LB		 866 /* ensure all descriptors are written before poking hardware */
867 wmb();
13d64285 868 txq_enable(txq);
c9df406f 869
13d64285 870 txq->tx_desc_count += nr_frags + 1;
4df89bd5
LB		 871
872 return 0;
1da177e4 873}
1da177e4 874
0ccfe64d 875static netdev_tx_t mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 876{
e5371493 877 struct mv643xx_eth_private *mp = netdev_priv(dev);
73151ce3 878 int length, queue;
13d64285 879 struct tx_queue *txq;
e5ef1de1 880 struct netdev_queue *nq;
afdb57a2 881
8fd89211
LB		 882 queue = skb_get_queue_mapping(skb);
883 txq = mp->txq + queue;
884 nq = netdev_get_tx_queue(dev, queue);
885
c9df406f 886 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
8fd89211 887 txq->tx_dropped++;
7542db8b
JP		 888 netdev_printk(KERN_DEBUG, dev,
889 "failed to linearize skb with tiny unaligned fragment\n");
c9df406f
LB		 890 return NETDEV_TX_BUSY;
891 }
892
17cd0a59 893 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
e5ef1de1 894 if (net_ratelimit())
7542db8b 895 netdev_err(dev, "tx queue full?!\n");
3d6b35bc
LB		 896 kfree_skb(skb);
897 return NETDEV_TX_OK;
c9df406f
LB		 898 }
899
73151ce3
RC		 900 length = skb->len;
901
4df89bd5
LB		 902 if (!txq_submit_skb(txq, skb)) {
903 int entries_left;
904
73151ce3 905 txq->tx_bytes += length;
4df89bd5 906 txq->tx_packets++;
c9df406f 907
4df89bd5
LB		 908 entries_left = txq->tx_ring_size - txq->tx_desc_count;
909 if (entries_left < MAX_SKB_FRAGS + 1)
910 netif_tx_stop_queue(nq);
911 }
c9df406f 912
c9df406f 913 return NETDEV_TX_OK;
1da177e4
LT		 914}
915
c9df406f 916
1fa38c58
LB		 917/* tx napi ******************************************************************/
918static void txq_kick(struct tx_queue *txq)
919{
920 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 921 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 922 u32 hw_desc_ptr;
923 u32 expected_ptr;
924
8fd89211 925 __netif_tx_lock(nq, smp_processor_id());
1fa38c58 926
37a6084f 927 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
1fa38c58
LB		 928 goto out;
929
37a6084f 930 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
1fa38c58
LB		 931 expected_ptr = (u32)txq->tx_desc_dma +
932 txq->tx_curr_desc * sizeof(struct tx_desc);
933
934 if (hw_desc_ptr != expected_ptr)
935 txq_enable(txq);
936
937out:
8fd89211 938 __netif_tx_unlock(nq);
1fa38c58
LB		 939
940 mp->work_tx_end &= ~(1 << txq->index);
941}
942
943static int txq_reclaim(struct tx_queue *txq, int budget, int force)
944{
945 struct mv643xx_eth_private *mp = txq_to_mp(txq);
8fd89211 946 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
1fa38c58
LB		 947 int reclaimed;
948
8fd89211 949 __netif_tx_lock(nq, smp_processor_id());
1fa38c58
LB		 950
951 reclaimed = 0;
952 while (reclaimed < budget && txq->tx_desc_count > 0) {
953 int tx_index;
954 struct tx_desc *desc;
955 u32 cmd_sts;
956 struct sk_buff *skb;
1fa38c58
LB		 957
958 tx_index = txq->tx_used_desc;
959 desc = &txq->tx_desc_area[tx_index];
960 cmd_sts = desc->cmd_sts;
961
962 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
963 if (!force)
964 break;
965 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
966 }
967
968 txq->tx_used_desc = tx_index + 1;
969 if (txq->tx_used_desc == txq->tx_ring_size)
970 txq->tx_used_desc = 0;
971
972 reclaimed++;
973 txq->tx_desc_count--;
974
99ab08e0
LB		 975 skb = NULL;
976 if (cmd_sts & TX_LAST_DESC)
977 skb = __skb_dequeue(&txq->tx_skb);
1fa38c58
LB		 978
979 if (cmd_sts & ERROR_SUMMARY) {
7542db8b 980 netdev_info(mp->dev, "tx error\n");
1fa38c58
LB		 981 mp->dev->stats.tx_errors++;
982 }
983
a418950c 984 if (cmd_sts & TX_FIRST_DESC) {
eb0519b5 985 dma_unmap_single(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 986 desc->byte_cnt, DMA_TO_DEVICE);
987 } else {
eb0519b5 988 dma_unmap_page(mp->dev->dev.parent, desc->buf_ptr,
a418950c
LB		 989 desc->byte_cnt, DMA_TO_DEVICE);
990 }
1fa38c58 991
2bcb4b0f
LB		 992 if (skb != NULL) {
993 if (skb_queue_len(&mp->rx_recycle) <
e7d2f4db 994 mp->rx_ring_size &&
7fd96ce4 995 skb_recycle_check(skb, mp->skb_size))
2bcb4b0f
LB		 996 __skb_queue_head(&mp->rx_recycle, skb);
997 else
998 dev_kfree_skb(skb);
999 }
1fa38c58
LB		 1000 }
1001
8fd89211
LB		 1002 __netif_tx_unlock(nq);
1003
1fa38c58
LB		 1004 if (reclaimed < budget)
1005 mp->work_tx &= ~(1 << txq->index);
1006
1fa38c58
LB		 1007 return reclaimed;
1008}
1009
1010
89df5fdc
LB		 1011/* tx rate control **********************************************************/
1012/*
1013 * Set total maximum TX rate (shared by all TX queues for this port)
1014 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
1015 */
1016static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1017{
1018 int token_rate;
1019 int mtu;
1020 int bucket_size;
1021
452503eb 1022 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 1023 if (token_rate > 1023)
1024 token_rate = 1023;
1025
1026 mtu = (mp->dev->mtu + 255) >> 8;
1027 if (mtu > 63)
1028 mtu = 63;
1029
1030 bucket_size = (burst + 255) >> 8;
1031 if (bucket_size > 65535)
1032 bucket_size = 65535;
1033
457b1d5a
LB		 1034 switch (mp->shared->tx_bw_control) {
1035 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f
LB		 1036 wrlp(mp, TX_BW_RATE, token_rate);
1037 wrlp(mp, TX_BW_MTU, mtu);
1038 wrlp(mp, TX_BW_BURST, bucket_size);
457b1d5a
LB		 1039 break;
1040 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f
LB		 1041 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1042 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1043 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
457b1d5a 1044 break;
1e881592 1045 }
89df5fdc
LB		 1046}
1047
1048static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1049{
1050 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1051 int token_rate;
1052 int bucket_size;
1053
452503eb 1054 token_rate = ((rate / 1000) * 64) / (mp->t_clk / 1000);
89df5fdc
LB		 1055 if (token_rate > 1023)
1056 token_rate = 1023;
1057
1058 bucket_size = (burst + 255) >> 8;
1059 if (bucket_size > 65535)
1060 bucket_size = 65535;
1061
37a6084f
LB		 1062 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1063 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
89df5fdc
LB		 1064}
1065
1066static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1067{
1068 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1069 int off;
1070 u32 val;
1071
1072 /*
1073 * Turn on fixed priority mode.
1074 */
457b1d5a
LB		 1075 off = 0;
1076 switch (mp->shared->tx_bw_control) {
1077 case TX_BW_CONTROL_OLD_LAYOUT:
37a6084f 1078 off = TXQ_FIX_PRIO_CONF;
457b1d5a
LB		 1079 break;
1080 case TX_BW_CONTROL_NEW_LAYOUT:
37a6084f 1081 off = TXQ_FIX_PRIO_CONF_MOVED;
457b1d5a
LB		 1082 break;
1083 }
89df5fdc 1084
457b1d5a 1085 if (off) {
37a6084f 1086 val = rdlp(mp, off);
457b1d5a 1087 val |= 1 << txq->index;
37a6084f 1088 wrlp(mp, off, val);
457b1d5a 1089 }
89df5fdc
LB		 1090}
1091
89df5fdc 1092
c9df406f 1093/* mii management interface *************************************************/
45c5d3bc
LB		 1094static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1095{
1096 struct mv643xx_eth_shared_private *msp = dev_id;
1097
1098 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1099 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1100 wake_up(&msp->smi_busy_wait);
1101 return IRQ_HANDLED;
1102 }
1103
1104 return IRQ_NONE;
1105}
c9df406f 1106
45c5d3bc 1107static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1da177e4 1108{
45c5d3bc
LB		 1109 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1110}
1da177e4 1111
45c5d3bc
LB		 1112static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1113{
1114 if (msp->err_interrupt == NO_IRQ) {
1115 int i;
c9df406f 1116
45c5d3bc
LB		 1117 for (i = 0; !smi_is_done(msp); i++) {
1118 if (i == 10)
1119 return -ETIMEDOUT;
1120 msleep(10);
c9df406f 1121 }
45c5d3bc
LB		 1122
1123 return 0;
1124 }
1125
ee04448d
LB		 1126 if (!smi_is_done(msp)) {
1127 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1128 msecs_to_jiffies(100));
1129 if (!smi_is_done(msp))
1130 return -ETIMEDOUT;
1131 }
45c5d3bc
LB		 1132
1133 return 0;
1134}
1135
ed94493f 1136static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
45c5d3bc 1137{
ed94493f 1138 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc
LB		 1139 void __iomem *smi_reg = msp->base + SMI_REG;
1140 int ret;
1141
45c5d3bc 1142 if (smi_wait_ready(msp)) {
7542db8b 1143 pr_warn("SMI bus busy timeout\n");
ed94493f 1144 return -ETIMEDOUT;
1da177e4
LT		 1145 }
1146
fc32b0e2 1147 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1da177e4 1148
45c5d3bc 1149 if (smi_wait_ready(msp)) {
7542db8b 1150 pr_warn("SMI bus busy timeout\n");
ed94493f 1151 return -ETIMEDOUT;
45c5d3bc
LB		 1152 }
1153
1154 ret = readl(smi_reg);
1155 if (!(ret & SMI_READ_VALID)) {
7542db8b 1156 pr_warn("SMI bus read not valid\n");
ed94493f 1157 return -ENODEV;
c9df406f
LB		 1158 }
1159
ed94493f 1160 return ret & 0xffff;
1da177e4
LT		 1161}
1162
ed94493f 1163static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1da177e4 1164{
ed94493f 1165 struct mv643xx_eth_shared_private *msp = bus->priv;
45c5d3bc 1166 void __iomem *smi_reg = msp->base + SMI_REG;
1da177e4 1167
45c5d3bc 1168 if (smi_wait_ready(msp)) {
7542db8b 1169 pr_warn("SMI bus busy timeout\n");
45c5d3bc 1170 return -ETIMEDOUT;
1da177e4
LT		 1171 }
1172
fc32b0e2 1173 writel(SMI_OPCODE_WRITE | (reg << 21) |
ed94493f 1174 (addr << 16) | (val & 0xffff), smi_reg);
45c5d3bc 1175
ed94493f 1176 if (smi_wait_ready(msp)) {
7542db8b 1177 pr_warn("SMI bus busy timeout\n");
ed94493f
LB		 1178 return -ETIMEDOUT;
1179 }
45c5d3bc
LB		 1180
1181 return 0;
c9df406f 1182}
1da177e4 1183
c9df406f 1184
8fd89211
LB		 1185/* statistics ***************************************************************/
1186static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1187{
1188 struct mv643xx_eth_private *mp = netdev_priv(dev);
1189 struct net_device_stats *stats = &dev->stats;
1190 unsigned long tx_packets = 0;
1191 unsigned long tx_bytes = 0;
1192 unsigned long tx_dropped = 0;
1193 int i;
1194
1195 for (i = 0; i < mp->txq_count; i++) {
1196 struct tx_queue *txq = mp->txq + i;
1197
1198 tx_packets += txq->tx_packets;
1199 tx_bytes += txq->tx_bytes;
1200 tx_dropped += txq->tx_dropped;
1201 }
1202
1203 stats->tx_packets = tx_packets;
1204 stats->tx_bytes = tx_bytes;
1205 stats->tx_dropped = tx_dropped;
1206
1207 return stats;
1208}
1209
eaf5d590
LB		 1210static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1211{
1212 u32 lro_aggregated = 0;
1213 u32 lro_flushed = 0;
1214 u32 lro_no_desc = 0;
1215 int i;
1216
eaf5d590
LB		 1217 for (i = 0; i < mp->rxq_count; i++) {
1218 struct rx_queue *rxq = mp->rxq + i;
1219
1220 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1221 lro_flushed += rxq->lro_mgr.stats.flushed;
1222 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1223 }
eaf5d590
LB		 1224
1225 mp->lro_counters.lro_aggregated = lro_aggregated;
1226 mp->lro_counters.lro_flushed = lro_flushed;
1227 mp->lro_counters.lro_no_desc = lro_no_desc;
1228}
1229
fc32b0e2 1230static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
c9df406f 1231{
fc32b0e2 1232 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1da177e4
LT		 1233}
1234
fc32b0e2 1235static void mib_counters_clear(struct mv643xx_eth_private *mp)
d0412d96 1236{
fc32b0e2
LB		 1237 int i;
1238
1239 for (i = 0; i < 0x80; i += 4)
1240 mib_read(mp, i);
302476c9
PZ		 1241
1242 /* Clear non MIB hw counters also */
1243 rdlp(mp, RX_DISCARD_FRAME_CNT);
1244 rdlp(mp, RX_OVERRUN_FRAME_CNT);
c9df406f 1245}
d0412d96 1246
fc32b0e2 1247static void mib_counters_update(struct mv643xx_eth_private *mp)
c9df406f 1248{
e5371493 1249 struct mib_counters *p = &mp->mib_counters;
4b8e3655 1250
57e8f26a 1251 spin_lock_bh(&mp->mib_counters_lock);
fc32b0e2 1252 p->good_octets_received += mib_read(mp, 0x00);
fc32b0e2
LB		 1253 p->bad_octets_received += mib_read(mp, 0x08);
1254 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1255 p->good_frames_received += mib_read(mp, 0x10);
1256 p->bad_frames_received += mib_read(mp, 0x14);
1257 p->broadcast_frames_received += mib_read(mp, 0x18);
1258 p->multicast_frames_received += mib_read(mp, 0x1c);
1259 p->frames_64_octets += mib_read(mp, 0x20);
1260 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1261 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1262 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1263 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1264 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1265 p->good_octets_sent += mib_read(mp, 0x38);
fc32b0e2
LB		 1266 p->good_frames_sent += mib_read(mp, 0x40);
1267 p->excessive_collision += mib_read(mp, 0x44);
1268 p->multicast_frames_sent += mib_read(mp, 0x48);
1269 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1270 p->unrec_mac_control_received += mib_read(mp, 0x50);
1271 p->fc_sent += mib_read(mp, 0x54);
1272 p->good_fc_received += mib_read(mp, 0x58);
1273 p->bad_fc_received += mib_read(mp, 0x5c);
1274 p->undersize_received += mib_read(mp, 0x60);
1275 p->fragments_received += mib_read(mp, 0x64);
1276 p->oversize_received += mib_read(mp, 0x68);
1277 p->jabber_received += mib_read(mp, 0x6c);
1278 p->mac_receive_error += mib_read(mp, 0x70);
1279 p->bad_crc_event += mib_read(mp, 0x74);
1280 p->collision += mib_read(mp, 0x78);
1281 p->late_collision += mib_read(mp, 0x7c);
302476c9
PZ		 1282 /* Non MIB hardware counters */
1283 p->rx_discard += rdlp(mp, RX_DISCARD_FRAME_CNT);
1284 p->rx_overrun += rdlp(mp, RX_OVERRUN_FRAME_CNT);
57e8f26a 1285 spin_unlock_bh(&mp->mib_counters_lock);
4ff3495a
LB		 1286
1287 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1288}
1289
1290static void mib_counters_timer_wrapper(unsigned long _mp)
1291{
1292 struct mv643xx_eth_private *mp = (void *)_mp;
1293
1294 mib_counters_update(mp);
d0412d96
JC		 1295}
1296
c9df406f 1297
3e508034
LB		 1298/* interrupt coalescing *****************************************************/
1299/*
1300 * Hardware coalescing parameters are set in units of 64 t_clk
1301 * cycles. I.e.:
1302 *
1303 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1304 *
1305 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1306 *
1307 * In the ->set*() methods, we round the computed register value
1308 * to the nearest integer.
1309 */
1310static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1311{
1312 u32 val = rdlp(mp, SDMA_CONFIG);
1313 u64 temp;
1314
1315 if (mp->shared->extended_rx_coal_limit)
1316 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1317 else
1318 temp = (val & 0x003fff00) >> 8;
1319
1320 temp *= 64000000;
452503eb 1321 do_div(temp, mp->t_clk);
3e508034
LB		 1322
1323 return (unsigned int)temp;
1324}
1325
1326static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1327{
1328 u64 temp;
1329 u32 val;
1330
452503eb 1331 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1332 temp += 31999999;
1333 do_div(temp, 64000000);
1334
1335 val = rdlp(mp, SDMA_CONFIG);
1336 if (mp->shared->extended_rx_coal_limit) {
1337 if (temp > 0xffff)
1338 temp = 0xffff;
1339 val &= ~0x023fff80;
1340 val |= (temp & 0x8000) << 10;
1341 val |= (temp & 0x7fff) << 7;
1342 } else {
1343 if (temp > 0x3fff)
1344 temp = 0x3fff;
1345 val &= ~0x003fff00;
1346 val |= (temp & 0x3fff) << 8;
1347 }
1348 wrlp(mp, SDMA_CONFIG, val);
1349}
1350
1351static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1352{
1353 u64 temp;
1354
1355 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1356 temp *= 64000000;
452503eb 1357 do_div(temp, mp->t_clk);
3e508034
LB		 1358
1359 return (unsigned int)temp;
1360}
1361
1362static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1363{
1364 u64 temp;
1365
452503eb 1366 temp = (u64)usec * mp->t_clk;
3e508034
LB		 1367 temp += 31999999;
1368 do_div(temp, 64000000);
1369
1370 if (temp > 0x3fff)
1371 temp = 0x3fff;
1372
1373 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1374}
1375
1376
c9df406f 1377/* ethtool ******************************************************************/
e5371493 1378struct mv643xx_eth_stats {
c9df406f
LB		 1379 char stat_string[ETH_GSTRING_LEN];
1380 int sizeof_stat;
16820054
LB		 1381 int netdev_off;
1382 int mp_off;
c9df406f
LB		 1383};
1384
16820054
LB		 1385#define SSTAT(m) \
1386 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1387 offsetof(struct net_device, stats.m), -1 }
1388
1389#define MIBSTAT(m) \
1390 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1391 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1392
eaf5d590
LB		 1393#define LROSTAT(m) \
1394 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1395 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1396
16820054
LB		 1397static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1398 SSTAT(rx_packets),
1399 SSTAT(tx_packets),
1400 SSTAT(rx_bytes),
1401 SSTAT(tx_bytes),
1402 SSTAT(rx_errors),
1403 SSTAT(tx_errors),
1404 SSTAT(rx_dropped),
1405 SSTAT(tx_dropped),
1406 MIBSTAT(good_octets_received),
1407 MIBSTAT(bad_octets_received),
1408 MIBSTAT(internal_mac_transmit_err),
1409 MIBSTAT(good_frames_received),
1410 MIBSTAT(bad_frames_received),
1411 MIBSTAT(broadcast_frames_received),
1412 MIBSTAT(multicast_frames_received),
1413 MIBSTAT(frames_64_octets),
1414 MIBSTAT(frames_65_to_127_octets),
1415 MIBSTAT(frames_128_to_255_octets),
1416 MIBSTAT(frames_256_to_511_octets),
1417 MIBSTAT(frames_512_to_1023_octets),
1418 MIBSTAT(frames_1024_to_max_octets),
1419 MIBSTAT(good_octets_sent),
1420 MIBSTAT(good_frames_sent),
1421 MIBSTAT(excessive_collision),
1422 MIBSTAT(multicast_frames_sent),
1423 MIBSTAT(broadcast_frames_sent),
1424 MIBSTAT(unrec_mac_control_received),
1425 MIBSTAT(fc_sent),
1426 MIBSTAT(good_fc_received),
1427 MIBSTAT(bad_fc_received),
1428 MIBSTAT(undersize_received),
1429 MIBSTAT(fragments_received),
1430 MIBSTAT(oversize_received),
1431 MIBSTAT(jabber_received),
1432 MIBSTAT(mac_receive_error),
1433 MIBSTAT(bad_crc_event),
1434 MIBSTAT(collision),
1435 MIBSTAT(late_collision),
302476c9
PZ		 1436 MIBSTAT(rx_discard),
1437 MIBSTAT(rx_overrun),
eaf5d590
LB		 1438 LROSTAT(lro_aggregated),
1439 LROSTAT(lro_flushed),
1440 LROSTAT(lro_no_desc),
c9df406f
LB		 1441};
1442
10a9948d 1443static int
6bdf576e
LB		 1444mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1445 struct ethtool_cmd *cmd)
d0412d96 1446{
d0412d96
JC		 1447 int err;
1448
ed94493f
LB		 1449 err = phy_read_status(mp->phy);
1450 if (err == 0)
1451 err = phy_ethtool_gset(mp->phy, cmd);
d0412d96 1452
fc32b0e2
LB		 1453 /*
1454 * The MAC does not support 1000baseT_Half.
1455 */
d0412d96
JC		 1456 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1457 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1458
1459 return err;
1460}
1461
10a9948d 1462static int
6bdf576e 1463mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
10a9948d 1464 struct ethtool_cmd *cmd)
bedfe324 1465{
81600eea
LB		 1466 u32 port_status;
1467
37a6084f 1468 port_status = rdlp(mp, PORT_STATUS);
81600eea 1469
bedfe324
LB		 1470 cmd->supported = SUPPORTED_MII;
1471 cmd->advertising = ADVERTISED_MII;
81600eea
LB		 1472 switch (port_status & PORT_SPEED_MASK) {
1473 case PORT_SPEED_10:
70739497 1474 ethtool_cmd_speed_set(cmd, SPEED_10);
81600eea
LB		 1475 break;
1476 case PORT_SPEED_100:
70739497 1477 ethtool_cmd_speed_set(cmd, SPEED_100);
81600eea
LB		 1478 break;
1479 case PORT_SPEED_1000:
70739497 1480 ethtool_cmd_speed_set(cmd, SPEED_1000);
81600eea
LB		 1481 break;
1482 default:
1483 cmd->speed = -1;
1484 break;
1485 }
1486 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
bedfe324
LB		 1487 cmd->port = PORT_MII;
1488 cmd->phy_address = 0;
1489 cmd->transceiver = XCVR_INTERNAL;
1490 cmd->autoneg = AUTONEG_DISABLE;
1491 cmd->maxtxpkt = 1;
1492 cmd->maxrxpkt = 1;
1493
1494 return 0;
1495}
1496
6bdf576e
LB		 1497static int
1498mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1499{
1500 struct mv643xx_eth_private *mp = netdev_priv(dev);
1501
1502 if (mp->phy != NULL)
1503 return mv643xx_eth_get_settings_phy(mp, cmd);
1504 else
1505 return mv643xx_eth_get_settings_phyless(mp, cmd);
1506}
1507
10a9948d
LB		 1508static int
1509mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4 1510{
e5371493 1511 struct mv643xx_eth_private *mp = netdev_priv(dev);
ab4384a6 1512
6bdf576e
LB		 1513 if (mp->phy == NULL)
1514 return -EINVAL;
1515
fc32b0e2
LB		 1516 /*
1517 * The MAC does not support 1000baseT_Half.
1518 */
1519 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1520
ed94493f 1521 return phy_ethtool_sset(mp->phy, cmd);
c9df406f 1522}
1da177e4 1523
fc32b0e2
LB		 1524static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1525 struct ethtool_drvinfo *drvinfo)
c9df406f 1526{
6f39da2c
AL		 1527 strlcpy(drvinfo->driver, mv643xx_eth_driver_name,
1528 sizeof(drvinfo->driver));
68aad78c 1529 strlcpy(drvinfo->version, mv643xx_eth_driver_version,
6f39da2c
AL		 1530 sizeof(drvinfo->version));
1531 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1532 strlcpy(drvinfo->bus_info, "platform", sizeof(drvinfo->bus_info));
16820054 1533 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
c9df406f 1534}
1da177e4 1535
fc32b0e2 1536static int mv643xx_eth_nway_reset(struct net_device *dev)
c9df406f 1537{
e5371493 1538 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 1539
6bdf576e
LB		 1540 if (mp->phy == NULL)
1541 return -EINVAL;
1da177e4 1542
6bdf576e 1543 return genphy_restart_aneg(mp->phy);
bedfe324
LB		 1544}
1545
3e508034
LB		 1546static int
1547mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1548{
1549 struct mv643xx_eth_private *mp = netdev_priv(dev);
1550
1551 ec->rx_coalesce_usecs = get_rx_coal(mp);
1552 ec->tx_coalesce_usecs = get_tx_coal(mp);
1553
1554 return 0;
1555}
1556
1557static int
1558mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1559{
1560 struct mv643xx_eth_private *mp = netdev_priv(dev);
1561
1562 set_rx_coal(mp, ec->rx_coalesce_usecs);
1563 set_tx_coal(mp, ec->tx_coalesce_usecs);
1564
1565 return 0;
1566}
1567
e7d2f4db
LB		 1568static void
1569mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1570{
1571 struct mv643xx_eth_private *mp = netdev_priv(dev);
1572
1573 er->rx_max_pending = 4096;
1574 er->tx_max_pending = 4096;
e7d2f4db
LB		 1575
1576 er->rx_pending = mp->rx_ring_size;
1577 er->tx_pending = mp->tx_ring_size;
e7d2f4db
LB		 1578}
1579
1580static int
1581mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1582{
1583 struct mv643xx_eth_private *mp = netdev_priv(dev);
1584
1585 if (er->rx_mini_pending || er->rx_jumbo_pending)
1586 return -EINVAL;
1587
1588 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1589 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1590
1591 if (netif_running(dev)) {
1592 mv643xx_eth_stop(dev);
1593 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 1594 netdev_err(dev,
1595 "fatal error on re-opening device after ring param change\n");
e7d2f4db
LB		 1596 return -ENOMEM;
1597 }
1598 }
1599
1600 return 0;
1601}
1602
d888b373
LB		 1603
1604static int
c8f44aff 1605mv643xx_eth_set_features(struct net_device *dev, netdev_features_t features)
d888b373
LB		 1606{
1607 struct mv643xx_eth_private *mp = netdev_priv(dev);
3ad9b358 1608 bool rx_csum = features & NETIF_F_RXCSUM;
d888b373
LB		 1609
1610 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1611
1612 return 0;
1613}
1614
fc32b0e2
LB		 1615static void mv643xx_eth_get_strings(struct net_device *dev,
1616 uint32_t stringset, uint8_t *data)
c9df406f
LB		 1617{
1618 int i;
1da177e4 1619
fc32b0e2
LB		 1620 if (stringset == ETH_SS_STATS) {
1621 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
c9df406f 1622 memcpy(data + i * ETH_GSTRING_LEN,
16820054 1623 mv643xx_eth_stats[i].stat_string,
e5371493 1624 ETH_GSTRING_LEN);
c9df406f 1625 }
c9df406f
LB		 1626 }
1627}
1da177e4 1628
fc32b0e2
LB		 1629static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1630 struct ethtool_stats *stats,
1631 uint64_t *data)
c9df406f 1632{
b9873841 1633 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 1634 int i;
1da177e4 1635
8fd89211 1636 mv643xx_eth_get_stats(dev);
fc32b0e2 1637 mib_counters_update(mp);
eaf5d590 1638 mv643xx_eth_grab_lro_stats(mp);
1da177e4 1639
16820054
LB		 1640 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1641 const struct mv643xx_eth_stats *stat;
1642 void *p;
1643
1644 stat = mv643xx_eth_stats + i;
1645
1646 if (stat->netdev_off >= 0)
1647 p = ((void *)mp->dev) + stat->netdev_off;
1648 else
1649 p = ((void *)mp) + stat->mp_off;
1650
1651 data[i] = (stat->sizeof_stat == 8) ?
1652 *(uint64_t *)p : *(uint32_t *)p;
1da177e4 1653 }
c9df406f 1654}
1da177e4 1655
fc32b0e2 1656static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
c9df406f 1657{
fc32b0e2 1658 if (sset == ETH_SS_STATS)
16820054 1659 return ARRAY_SIZE(mv643xx_eth_stats);
fc32b0e2
LB		 1660
1661 return -EOPNOTSUPP;
c9df406f 1662}
1da177e4 1663
e5371493 1664static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
fc32b0e2
LB		 1665 .get_settings = mv643xx_eth_get_settings,
1666 .set_settings = mv643xx_eth_set_settings,
1667 .get_drvinfo = mv643xx_eth_get_drvinfo,
1668 .nway_reset = mv643xx_eth_nway_reset,
ed4ba4b5 1669 .get_link = ethtool_op_get_link,
3e508034
LB		 1670 .get_coalesce = mv643xx_eth_get_coalesce,
1671 .set_coalesce = mv643xx_eth_set_coalesce,
e7d2f4db
LB		 1672 .get_ringparam = mv643xx_eth_get_ringparam,
1673 .set_ringparam = mv643xx_eth_set_ringparam,
fc32b0e2
LB		 1674 .get_strings = mv643xx_eth_get_strings,
1675 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
e5371493 1676 .get_sset_count = mv643xx_eth_get_sset_count,
ebad0a8d 1677 .get_ts_info = ethtool_op_get_ts_info,
c9df406f 1678};
1da177e4 1679
bea3348e 1680
c9df406f 1681/* address handling *********************************************************/
5daffe94 1682static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1683{
66e63ffb
LB		 1684 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1685 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1da177e4 1686
5daffe94
LB		 1687 addr[0] = (mac_h >> 24) & 0xff;
1688 addr[1] = (mac_h >> 16) & 0xff;
1689 addr[2] = (mac_h >> 8) & 0xff;
1690 addr[3] = mac_h & 0xff;
1691 addr[4] = (mac_l >> 8) & 0xff;
1692 addr[5] = mac_l & 0xff;
c9df406f 1693}
1da177e4 1694
66e63ffb 1695static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
c9df406f 1696{
66e63ffb
LB		 1697 wrlp(mp, MAC_ADDR_HIGH,
1698 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1699 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
c9df406f 1700}
d0412d96 1701
66e63ffb 1702static u32 uc_addr_filter_mask(struct net_device *dev)
c9df406f 1703{
ccffad25 1704 struct netdev_hw_addr *ha;
66e63ffb 1705 u32 nibbles;
1da177e4 1706
66e63ffb
LB		 1707 if (dev->flags & IFF_PROMISC)
1708 return 0;
1da177e4 1709
66e63ffb 1710 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
32e7bfc4 1711 netdev_for_each_uc_addr(ha, dev) {
ccffad25 1712 if (memcmp(dev->dev_addr, ha->addr, 5))
66e63ffb 1713 return 0;
ccffad25 1714 if ((dev->dev_addr[5] ^ ha->addr[5]) & 0xf0)
66e63ffb 1715 return 0;
ff561eef 1716
ccffad25 1717 nibbles |= 1 << (ha->addr[5] & 0x0f);
66e63ffb 1718 }
1da177e4 1719
66e63ffb 1720 return nibbles;
1da177e4
LT		 1721}
1722
66e63ffb 1723static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1da177e4 1724{
e5371493 1725 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1726 u32 port_config;
1727 u32 nibbles;
1728 int i;
1da177e4 1729
cc9754b3 1730 uc_addr_set(mp, dev->dev_addr);
1da177e4 1731
6877f54e
PS		 1732 port_config = rdlp(mp, PORT_CONFIG) & ~UNICAST_PROMISCUOUS_MODE;
1733
66e63ffb
LB		 1734 nibbles = uc_addr_filter_mask(dev);
1735 if (!nibbles) {
1736 port_config |= UNICAST_PROMISCUOUS_MODE;
6877f54e 1737 nibbles = 0xffff;
66e63ffb
LB		 1738 }
1739
1740 for (i = 0; i < 16; i += 4) {
1741 int off = UNICAST_TABLE(mp->port_num) + i;
1742 u32 v;
1743
1744 v = 0;
1745 if (nibbles & 1)
1746 v |= 0x00000001;
1747 if (nibbles & 2)
1748 v |= 0x00000100;
1749 if (nibbles & 4)
1750 v |= 0x00010000;
1751 if (nibbles & 8)
1752 v |= 0x01000000;
1753 nibbles >>= 4;
1754
1755 wrl(mp, off, v);
1756 }
1757
66e63ffb 1758 wrlp(mp, PORT_CONFIG, port_config);
1da177e4
LT		 1759}
1760
69876569
LB		 1761static int addr_crc(unsigned char *addr)
1762{
1763 int crc = 0;
1764 int i;
1765
1766 for (i = 0; i < 6; i++) {
1767 int j;
1768
1769 crc = (crc ^ addr[i]) << 8;
1770 for (j = 7; j >= 0; j--) {
1771 if (crc & (0x100 << j))
1772 crc ^= 0x107 << j;
1773 }
1774 }
1775
1776 return crc;
1777}
1778
66e63ffb 1779static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1da177e4 1780{
fc32b0e2 1781 struct mv643xx_eth_private *mp = netdev_priv(dev);
66e63ffb
LB		 1782 u32 *mc_spec;
1783 u32 *mc_other;
22bedad3 1784 struct netdev_hw_addr *ha;
fc32b0e2 1785 int i;
c8aaea25 1786
fc32b0e2 1787 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
66e63ffb
LB		 1788 int port_num;
1789 u32 accept;
c8aaea25 1790
66e63ffb
LB		 1791oom:
1792 port_num = mp->port_num;
1793 accept = 0x01010101;
fc32b0e2
LB		 1794 for (i = 0; i < 0x100; i += 4) {
1795 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1796 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
c9df406f
LB		 1797 }
1798 return;
1799 }
c8aaea25 1800
82a5bd6a 1801 mc_spec = kmalloc(0x200, GFP_ATOMIC);
66e63ffb
LB		 1802 if (mc_spec == NULL)
1803 goto oom;
1804 mc_other = mc_spec + (0x100 >> 2);
1805
1806 memset(mc_spec, 0, 0x100);
1807 memset(mc_other, 0, 0x100);
1da177e4 1808
22bedad3
JP		 1809 netdev_for_each_mc_addr(ha, dev) {
1810 u8 *a = ha->addr;
66e63ffb
LB		 1811 u32 *table;
1812 int entry;
1da177e4 1813
fc32b0e2 1814 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
66e63ffb
LB		 1815 table = mc_spec;
1816 entry = a[5];
fc32b0e2 1817 } else {
66e63ffb
LB		 1818 table = mc_other;
1819 entry = addr_crc(a);
fc32b0e2 1820 }
66e63ffb 1821
2b448334 1822 table[entry >> 2] |= 1 << (8 * (entry & 3));
fc32b0e2 1823 }
66e63ffb
LB		 1824
1825 for (i = 0; i < 0x100; i += 4) {
1826 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1827 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1828 }
1829
1830 kfree(mc_spec);
1831}
1832
1833static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1834{
1835 mv643xx_eth_program_unicast_filter(dev);
1836 mv643xx_eth_program_multicast_filter(dev);
1837}
1838
1839static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1840{
1841 struct sockaddr *sa = addr;
1842
a29ec08a 1843 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 1844 return -EADDRNOTAVAIL;
a29ec08a 1845
66e63ffb
LB		 1846 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1847
1848 netif_addr_lock_bh(dev);
1849 mv643xx_eth_program_unicast_filter(dev);
1850 netif_addr_unlock_bh(dev);
1851
1852 return 0;
c9df406f 1853}
c8aaea25 1854
c8aaea25 1855
c9df406f 1856/* rx/tx queue initialisation ***********************************************/
64da80a2 1857static int rxq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1858{
64da80a2 1859 struct rx_queue *rxq = mp->rxq + index;
8a578111
LB		 1860 struct rx_desc *rx_desc;
1861 int size;
c9df406f
LB		 1862 int i;
1863
64da80a2
LB		 1864 rxq->index = index;
1865
e7d2f4db 1866 rxq->rx_ring_size = mp->rx_ring_size;
8a578111
LB		 1867
1868 rxq->rx_desc_count = 0;
1869 rxq->rx_curr_desc = 0;
1870 rxq->rx_used_desc = 0;
1871
1872 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1873
f7981c1c 1874 if (index == 0 && size <= mp->rx_desc_sram_size) {
8a578111
LB		 1875 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1876 mp->rx_desc_sram_size);
1877 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1878 } else {
eb0519b5
GP		 1879 rxq->rx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1880 size, &rxq->rx_desc_dma,
1881 GFP_KERNEL);
f7ea3337
PJ		 1882 }
1883
8a578111 1884 if (rxq->rx_desc_area == NULL) {
7542db8b 1885 netdev_err(mp->dev,
8a578111
LB		 1886 "can't allocate rx ring (%d bytes)\n", size);
1887 goto out;
1888 }
1889 memset(rxq->rx_desc_area, 0, size);
1da177e4 1890
8a578111
LB		 1891 rxq->rx_desc_area_size = size;
1892 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1893 GFP_KERNEL);
1894 if (rxq->rx_skb == NULL) {
7542db8b 1895 netdev_err(mp->dev, "can't allocate rx skb ring\n");
8a578111
LB		 1896 goto out_free;
1897 }
1898
1899 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1900 for (i = 0; i < rxq->rx_ring_size; i++) {
9da78745
LB		 1901 int nexti;
1902
1903 nexti = i + 1;
1904 if (nexti == rxq->rx_ring_size)
1905 nexti = 0;
1906
8a578111
LB		 1907 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1908 nexti * sizeof(struct rx_desc);
1909 }
1910
eaf5d590
LB		 1911 rxq->lro_mgr.dev = mp->dev;
1912 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1913 rxq->lro_mgr.features = LRO_F_NAPI;
1914 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1915 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1916 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1917 rxq->lro_mgr.max_aggr = 32;
1918 rxq->lro_mgr.frag_align_pad = 0;
1919 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1920 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1921
1922 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
eaf5d590 1923
8a578111
LB		 1924 return 0;
1925
1926
1927out_free:
f7981c1c 1928 if (index == 0 && size <= mp->rx_desc_sram_size)
8a578111
LB		 1929 iounmap(rxq->rx_desc_area);
1930 else
eb0519b5 1931 dma_free_coherent(mp->dev->dev.parent, size,
8a578111
LB		 1932 rxq->rx_desc_area,
1933 rxq->rx_desc_dma);
1934
1935out:
1936 return -ENOMEM;
c9df406f 1937}
c8aaea25 1938
8a578111 1939static void rxq_deinit(struct rx_queue *rxq)
c9df406f 1940{
8a578111
LB		 1941 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1942 int i;
1943
1944 rxq_disable(rxq);
c8aaea25 1945
8a578111
LB		 1946 for (i = 0; i < rxq->rx_ring_size; i++) {
1947 if (rxq->rx_skb[i]) {
1948 dev_kfree_skb(rxq->rx_skb[i]);
1949 rxq->rx_desc_count--;
1da177e4 1950 }
c8aaea25 1951 }
1da177e4 1952
8a578111 1953 if (rxq->rx_desc_count) {
7542db8b 1954 netdev_err(mp->dev, "error freeing rx ring -- %d skbs stuck\n",
8a578111
LB		 1955 rxq->rx_desc_count);
1956 }
1957
f7981c1c 1958 if (rxq->index == 0 &&
64da80a2 1959 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
8a578111 1960 iounmap(rxq->rx_desc_area);
c9df406f 1961 else
eb0519b5 1962 dma_free_coherent(mp->dev->dev.parent, rxq->rx_desc_area_size,
8a578111
LB		 1963 rxq->rx_desc_area, rxq->rx_desc_dma);
1964
1965 kfree(rxq->rx_skb);
c9df406f 1966}
1da177e4 1967
3d6b35bc 1968static int txq_init(struct mv643xx_eth_private *mp, int index)
c9df406f 1969{
3d6b35bc 1970 struct tx_queue *txq = mp->txq + index;
13d64285
LB		 1971 struct tx_desc *tx_desc;
1972 int size;
c9df406f 1973 int i;
1da177e4 1974
3d6b35bc
LB		 1975 txq->index = index;
1976
e7d2f4db 1977 txq->tx_ring_size = mp->tx_ring_size;
13d64285
LB		 1978
1979 txq->tx_desc_count = 0;
1980 txq->tx_curr_desc = 0;
1981 txq->tx_used_desc = 0;
1982
1983 size = txq->tx_ring_size * sizeof(struct tx_desc);
1984
f7981c1c 1985 if (index == 0 && size <= mp->tx_desc_sram_size) {
13d64285
LB		 1986 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1987 mp->tx_desc_sram_size);
1988 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1989 } else {
eb0519b5
GP		 1990 txq->tx_desc_area = dma_alloc_coherent(mp->dev->dev.parent,
1991 size, &txq->tx_desc_dma,
1992 GFP_KERNEL);
13d64285
LB		 1993 }
1994
1995 if (txq->tx_desc_area == NULL) {
7542db8b 1996 netdev_err(mp->dev,
13d64285 1997 "can't allocate tx ring (%d bytes)\n", size);
99ab08e0 1998 return -ENOMEM;
c9df406f 1999 }
13d64285
LB		 2000 memset(txq->tx_desc_area, 0, size);
2001
2002 txq->tx_desc_area_size = size;
13d64285
LB		 2003
2004 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2005 for (i = 0; i < txq->tx_ring_size; i++) {
6b368f68 2006 struct tx_desc *txd = tx_desc + i;
9da78745
LB		 2007 int nexti;
2008
2009 nexti = i + 1;
2010 if (nexti == txq->tx_ring_size)
2011 nexti = 0;
6b368f68
LB		 2012
2013 txd->cmd_sts = 0;
2014 txd->next_desc_ptr = txq->tx_desc_dma +
13d64285
LB		 2015 nexti * sizeof(struct tx_desc);
2016 }
2017
99ab08e0 2018 skb_queue_head_init(&txq->tx_skb);
c9df406f 2019
99ab08e0 2020 return 0;
c8aaea25 2021}
1da177e4 2022
13d64285 2023static void txq_deinit(struct tx_queue *txq)
c9df406f 2024{
13d64285 2025 struct mv643xx_eth_private *mp = txq_to_mp(txq);
fa3959f4 2026
13d64285 2027 txq_disable(txq);
1fa38c58 2028 txq_reclaim(txq, txq->tx_ring_size, 1);
1da177e4 2029
13d64285 2030 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1da177e4 2031
f7981c1c 2032 if (txq->index == 0 &&
3d6b35bc 2033 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
13d64285 2034 iounmap(txq->tx_desc_area);
c9df406f 2035 else
eb0519b5 2036 dma_free_coherent(mp->dev->dev.parent, txq->tx_desc_area_size,
13d64285 2037 txq->tx_desc_area, txq->tx_desc_dma);
c9df406f 2038}
1da177e4 2039
1da177e4 2040
c9df406f 2041/* netdev ops and related ***************************************************/
1fa38c58
LB		 2042static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2043{
2044 u32 int_cause;
2045 u32 int_cause_ext;
2046
e0ca8410 2047 int_cause = rdlp(mp, INT_CAUSE) & mp->int_mask;
1fa38c58
LB		 2048 if (int_cause == 0)
2049 return 0;
2050
2051 int_cause_ext = 0;
e0ca8410
SB		 2052 if (int_cause & INT_EXT) {
2053 int_cause &= ~INT_EXT;
37a6084f 2054 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
e0ca8410 2055 }
1fa38c58 2056
1fa38c58 2057 if (int_cause) {
37a6084f 2058 wrlp(mp, INT_CAUSE, ~int_cause);
1fa38c58 2059 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
37a6084f 2060 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1fa38c58
LB		 2061 mp->work_rx |= (int_cause & INT_RX) >> 2;
2062 }
2063
2064 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2065 if (int_cause_ext) {
37a6084f 2066 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1fa38c58
LB		 2067 if (int_cause_ext & INT_EXT_LINK_PHY)
2068 mp->work_link = 1;
2069 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2070 }
2071
2072 return 1;
2073}
2074
2075static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2076{
2077 struct net_device *dev = (struct net_device *)dev_id;
2078 struct mv643xx_eth_private *mp = netdev_priv(dev);
2079
2080 if (unlikely(!mv643xx_eth_collect_events(mp)))
2081 return IRQ_NONE;
2082
37a6084f 2083 wrlp(mp, INT_MASK, 0);
1fa38c58
LB		 2084 napi_schedule(&mp->napi);
2085
2086 return IRQ_HANDLED;
2087}
2088
2f7eb47a
LB		 2089static void handle_link_event(struct mv643xx_eth_private *mp)
2090{
2091 struct net_device *dev = mp->dev;
2092 u32 port_status;
2093 int speed;
2094 int duplex;
2095 int fc;
2096
37a6084f 2097 port_status = rdlp(mp, PORT_STATUS);
2f7eb47a
LB		 2098 if (!(port_status & LINK_UP)) {
2099 if (netif_carrier_ok(dev)) {
2100 int i;
2101
7542db8b 2102 netdev_info(dev, "link down\n");
2f7eb47a
LB		 2103
2104 netif_carrier_off(dev);
2f7eb47a 2105
f7981c1c 2106 for (i = 0; i < mp->txq_count; i++) {
2f7eb47a
LB		 2107 struct tx_queue *txq = mp->txq + i;
2108
1fa38c58 2109 txq_reclaim(txq, txq->tx_ring_size, 1);
f7981c1c 2110 txq_reset_hw_ptr(txq);
2f7eb47a
LB		 2111 }
2112 }
2113 return;
2114 }
2115
2116 switch (port_status & PORT_SPEED_MASK) {
2117 case PORT_SPEED_10:
2118 speed = 10;
2119 break;
2120 case PORT_SPEED_100:
2121 speed = 100;
2122 break;
2123 case PORT_SPEED_1000:
2124 speed = 1000;
2125 break;
2126 default:
2127 speed = -1;
2128 break;
2129 }
2130 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2131 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2132
7542db8b
JP		 2133 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
2134 speed, duplex ? "full" : "half", fc ? "en" : "dis");
2f7eb47a 2135
4fdeca3f 2136 if (!netif_carrier_ok(dev))
2f7eb47a 2137 netif_carrier_on(dev);
2f7eb47a
LB		 2138}
2139
1fa38c58 2140static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
c9df406f 2141{
1fa38c58
LB		 2142 struct mv643xx_eth_private *mp;
2143 int work_done;
ce4e2e45 2144
1fa38c58 2145 mp = container_of(napi, struct mv643xx_eth_private, napi);
fc32b0e2 2146
1319ebad
LB		 2147 if (unlikely(mp->oom)) {
2148 mp->oom = 0;
2149 del_timer(&mp->rx_oom);
2150 }
1da177e4 2151
1fa38c58
LB		 2152 work_done = 0;
2153 while (work_done < budget) {
2154 u8 queue_mask;
2155 int queue;
2156 int work_tbd;
2157
2158 if (mp->work_link) {
2159 mp->work_link = 0;
2160 handle_link_event(mp);
26ef1f17 2161 work_done++;
1fa38c58
LB		 2162 continue;
2163 }
1da177e4 2164
1319ebad
LB		 2165 queue_mask = mp->work_tx | mp->work_tx_end | mp->work_rx;
2166 if (likely(!mp->oom))
2167 queue_mask |= mp->work_rx_refill;
2168
1fa38c58
LB		 2169 if (!queue_mask) {
2170 if (mv643xx_eth_collect_events(mp))
2171 continue;
2172 break;
2173 }
1da177e4 2174
1fa38c58
LB		 2175 queue = fls(queue_mask) - 1;
2176 queue_mask = 1 << queue;
2177
2178 work_tbd = budget - work_done;
2179 if (work_tbd > 16)
2180 work_tbd = 16;
2181
2182 if (mp->work_tx_end & queue_mask) {
2183 txq_kick(mp->txq + queue);
2184 } else if (mp->work_tx & queue_mask) {
2185 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2186 txq_maybe_wake(mp->txq + queue);
2187 } else if (mp->work_rx & queue_mask) {
2188 work_done += rxq_process(mp->rxq + queue, work_tbd);
1319ebad 2189 } else if (!mp->oom && (mp->work_rx_refill & queue_mask)) {
1fa38c58
LB		 2190 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2191 } else {
2192 BUG();
2193 }
84dd619e 2194 }
fc32b0e2 2195
1fa38c58 2196 if (work_done < budget) {
1319ebad 2197 if (mp->oom)
1fa38c58
LB		 2198 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2199 napi_complete(napi);
e0ca8410 2200 wrlp(mp, INT_MASK, mp->int_mask);
226bb6b7 2201 }
3d6b35bc 2202
1fa38c58
LB		 2203 return work_done;
2204}
8fa89bf5 2205
1fa38c58
LB		 2206static inline void oom_timer_wrapper(unsigned long data)
2207{
2208 struct mv643xx_eth_private *mp = (void *)data;
1da177e4 2209
1fa38c58 2210 napi_schedule(&mp->napi);
1da177e4
LT		 2211}
2212
e5371493 2213static void phy_reset(struct mv643xx_eth_private *mp)
1da177e4 2214{
45c5d3bc
LB		 2215 int data;
2216
ed94493f 2217 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc
LB		 2218 if (data < 0)
2219 return;
1da177e4 2220
7f106c1d 2221 data |= BMCR_RESET;
ed94493f 2222 if (phy_write(mp->phy, MII_BMCR, data) < 0)
45c5d3bc 2223 return;
1da177e4 2224
c9df406f 2225 do {
ed94493f 2226 data = phy_read(mp->phy, MII_BMCR);
45c5d3bc 2227 } while (data >= 0 && data & BMCR_RESET);
1da177e4
LT		 2228}
2229
fc32b0e2 2230static void port_start(struct mv643xx_eth_private *mp)
1da177e4 2231{
d0412d96 2232 u32 pscr;
8a578111 2233 int i;
1da177e4 2234
bedfe324
LB		 2235 /*
2236 * Perform PHY reset, if there is a PHY.
2237 */
ed94493f 2238 if (mp->phy != NULL) {
bedfe324
LB		 2239 struct ethtool_cmd cmd;
2240
2241 mv643xx_eth_get_settings(mp->dev, &cmd);
2242 phy_reset(mp);
2243 mv643xx_eth_set_settings(mp->dev, &cmd);
2244 }
1da177e4 2245
81600eea
LB		 2246 /*
2247 * Configure basic link parameters.
2248 */
37a6084f 2249 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2250
2251 pscr |= SERIAL_PORT_ENABLE;
37a6084f 2252 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2253
2254 pscr |= DO_NOT_FORCE_LINK_FAIL;
ed94493f 2255 if (mp->phy == NULL)
81600eea 2256 pscr |= FORCE_LINK_PASS;
37a6084f 2257 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea 2258
13d64285
LB		 2259 /*
2260 * Configure TX path and queues.
2261 */
89df5fdc 2262 tx_set_rate(mp, 1000000000, 16777216);
f7981c1c 2263 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc 2264 struct tx_queue *txq = mp->txq + i;
13d64285 2265
6b368f68 2266 txq_reset_hw_ptr(txq);
89df5fdc
LB		 2267 txq_set_rate(txq, 1000000000, 16777216);
2268 txq_set_fixed_prio_mode(txq);
13d64285
LB		 2269 }
2270
d9a073ea
LB		 2271 /*
2272 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
170e7108
LB		 2273 * frames to RX queue #0, and include the pseudo-header when
2274 * calculating receive checksums.
d9a073ea 2275 */
e138f96b 2276 mv643xx_eth_set_features(mp->dev, mp->dev->features);
01999873 2277
376489a2
LB		 2278 /*
2279 * Treat BPDUs as normal multicasts, and disable partition mode.
2280 */
37a6084f 2281 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
01999873 2282
5a893922
LB		 2283 /*
2284 * Add configured unicast addresses to address filter table.
2285 */
2286 mv643xx_eth_program_unicast_filter(mp->dev);
2287
8a578111 2288 /*
64da80a2 2289 * Enable the receive queues.
8a578111 2290 */
f7981c1c 2291 for (i = 0; i < mp->rxq_count; i++) {
64da80a2 2292 struct rx_queue *rxq = mp->rxq + i;
8a578111 2293 u32 addr;
1da177e4 2294
8a578111
LB		 2295 addr = (u32)rxq->rx_desc_dma;
2296 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
37a6084f 2297 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
1da177e4 2298
8a578111
LB		 2299 rxq_enable(rxq);
2300 }
1da177e4
LT		 2301}
2302
2bcb4b0f
LB		 2303static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2304{
2305 int skb_size;
2306
2307 /*
2308 * Reserve 2+14 bytes for an ethernet header (the hardware
2309 * automatically prepends 2 bytes of dummy data to each
2310 * received packet), 16 bytes for up to four VLAN tags, and
2311 * 4 bytes for the trailing FCS -- 36 bytes total.
2312 */
2313 skb_size = mp->dev->mtu + 36;
2314
2315 /*
2316 * Make sure that the skb size is a multiple of 8 bytes, as
2317 * the lower three bits of the receive descriptor's buffer
2318 * size field are ignored by the hardware.
2319 */
2320 mp->skb_size = (skb_size + 7) & ~7;
7fd96ce4
LB		 2321
2322 /*
2323 * If NET_SKB_PAD is smaller than a cache line,
2324 * netdev_alloc_skb() will cause skb->data to be misaligned
2325 * to a cache line boundary. If this is the case, include
2326 * some extra space to allow re-aligning the data area.
2327 */
2328 mp->skb_size += SKB_DMA_REALIGN;
2bcb4b0f
LB		 2329}
2330
c9df406f 2331static int mv643xx_eth_open(struct net_device *dev)
16e03018 2332{
e5371493 2333 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2334 int err;
64da80a2 2335 int i;
16e03018 2336
37a6084f
LB		 2337 wrlp(mp, INT_CAUSE, 0);
2338 wrlp(mp, INT_CAUSE_EXT, 0);
2339 rdlp(mp, INT_CAUSE_EXT);
c9df406f 2340
fc32b0e2 2341 err = request_irq(dev->irq, mv643xx_eth_irq,
2a1867a7 2342 IRQF_SHARED, dev->name, dev);
c9df406f 2343 if (err) {
7542db8b 2344 netdev_err(dev, "can't assign irq\n");
c9df406f 2345 return -EAGAIN;
16e03018
DF		 2346 }
2347
2bcb4b0f
LB		 2348 mv643xx_eth_recalc_skb_size(mp);
2349
2257e05c
LB		 2350 napi_enable(&mp->napi);
2351
2bcb4b0f
LB		 2352 skb_queue_head_init(&mp->rx_recycle);
2353
e0ca8410
SB		 2354 mp->int_mask = INT_EXT;
2355
f7981c1c 2356 for (i = 0; i < mp->rxq_count; i++) {
64da80a2
LB		 2357 err = rxq_init(mp, i);
2358 if (err) {
2359 while (--i >= 0)
f7981c1c 2360 rxq_deinit(mp->rxq + i);
64da80a2
LB		 2361 goto out;
2362 }
2363
1fa38c58 2364 rxq_refill(mp->rxq + i, INT_MAX);
e0ca8410 2365 mp->int_mask |= INT_RX_0 << i;
2257e05c
LB		 2366 }
2367
1319ebad 2368 if (mp->oom) {
2257e05c
LB		 2369 mp->rx_oom.expires = jiffies + (HZ / 10);
2370 add_timer(&mp->rx_oom);
64da80a2 2371 }
8a578111 2372
f7981c1c 2373 for (i = 0; i < mp->txq_count; i++) {
3d6b35bc
LB		 2374 err = txq_init(mp, i);
2375 if (err) {
2376 while (--i >= 0)
f7981c1c 2377 txq_deinit(mp->txq + i);
3d6b35bc
LB		 2378 goto out_free;
2379 }
e0ca8410 2380 mp->int_mask |= INT_TX_END_0 << i;
3d6b35bc 2381 }
16e03018 2382
fc32b0e2 2383 port_start(mp);
16e03018 2384
37a6084f 2385 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
e0ca8410 2386 wrlp(mp, INT_MASK, mp->int_mask);
16e03018 2387
c9df406f
LB		 2388 return 0;
2389
13d64285 2390
fc32b0e2 2391out_free:
f7981c1c
LB		 2392 for (i = 0; i < mp->rxq_count; i++)
2393 rxq_deinit(mp->rxq + i);
fc32b0e2 2394out:
c9df406f
LB		 2395 free_irq(dev->irq, dev);
2396
2397 return err;
16e03018
DF		 2398}
2399
e5371493 2400static void port_reset(struct mv643xx_eth_private *mp)
1da177e4 2401{
fc32b0e2 2402 unsigned int data;
64da80a2 2403 int i;
1da177e4 2404
f7981c1c
LB		 2405 for (i = 0; i < mp->rxq_count; i++)
2406 rxq_disable(mp->rxq + i);
2407 for (i = 0; i < mp->txq_count; i++)
2408 txq_disable(mp->txq + i);
ae9ae064
LB		 2409
2410 while (1) {
37a6084f 2411 u32 ps = rdlp(mp, PORT_STATUS);
ae9ae064
LB		 2412
2413 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2414 break;
13d64285 2415 udelay(10);
ae9ae064 2416 }
1da177e4 2417
c9df406f 2418 /* Reset the Enable bit in the Configuration Register */
37a6084f 2419 data = rdlp(mp, PORT_SERIAL_CONTROL);
fc32b0e2
LB		 2420 data &= ~(SERIAL_PORT_ENABLE |
2421 DO_NOT_FORCE_LINK_FAIL |
2422 FORCE_LINK_PASS);
37a6084f 2423 wrlp(mp, PORT_SERIAL_CONTROL, data);
1da177e4
LT		 2424}
2425
c9df406f 2426static int mv643xx_eth_stop(struct net_device *dev)
1da177e4 2427{
e5371493 2428 struct mv643xx_eth_private *mp = netdev_priv(dev);
64da80a2 2429 int i;
1da177e4 2430
fe65e704 2431 wrlp(mp, INT_MASK_EXT, 0x00000000);
37a6084f
LB		 2432 wrlp(mp, INT_MASK, 0x00000000);
2433 rdlp(mp, INT_MASK);
1da177e4 2434
c9df406f 2435 napi_disable(&mp->napi);
78fff83b 2436
2257e05c
LB		 2437 del_timer_sync(&mp->rx_oom);
2438
c9df406f 2439 netif_carrier_off(dev);
1da177e4 2440
fc32b0e2
LB		 2441 free_irq(dev->irq, dev);
2442
cc9754b3 2443 port_reset(mp);
8fd89211 2444 mv643xx_eth_get_stats(dev);
fc32b0e2 2445 mib_counters_update(mp);
57e8f26a 2446 del_timer_sync(&mp->mib_counters_timer);
1da177e4 2447
2bcb4b0f
LB		 2448 skb_queue_purge(&mp->rx_recycle);
2449
f7981c1c
LB		 2450 for (i = 0; i < mp->rxq_count; i++)
2451 rxq_deinit(mp->rxq + i);
2452 for (i = 0; i < mp->txq_count; i++)
2453 txq_deinit(mp->txq + i);
1da177e4 2454
c9df406f 2455 return 0;
1da177e4
LT		 2456}
2457
fc32b0e2 2458static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1da177e4 2459{
e5371493 2460 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2461
ed94493f 2462 if (mp->phy != NULL)
28b04113 2463 return phy_mii_ioctl(mp->phy, ifr, cmd);
bedfe324
LB		 2464
2465 return -EOPNOTSUPP;
1da177e4
LT		 2466}
2467
c9df406f 2468static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 2469{
89df5fdc
LB		 2470 struct mv643xx_eth_private *mp = netdev_priv(dev);
2471
fc32b0e2 2472 if (new_mtu < 64 || new_mtu > 9500)
c9df406f 2473 return -EINVAL;
1da177e4 2474
c9df406f 2475 dev->mtu = new_mtu;
2bcb4b0f 2476 mv643xx_eth_recalc_skb_size(mp);
89df5fdc
LB		 2477 tx_set_rate(mp, 1000000000, 16777216);
2478
c9df406f
LB		 2479 if (!netif_running(dev))
2480 return 0;
1da177e4 2481
c9df406f
LB		 2482 /*
2483 * Stop and then re-open the interface. This will allocate RX
2484 * skbs of the new MTU.
2485 * There is a possible danger that the open will not succeed,
fc32b0e2 2486 * due to memory being full.
c9df406f
LB		 2487 */
2488 mv643xx_eth_stop(dev);
2489 if (mv643xx_eth_open(dev)) {
7542db8b
JP		 2490 netdev_err(dev,
2491 "fatal error on re-opening device after MTU change\n");
c9df406f
LB		 2492 }
2493
2494 return 0;
1da177e4
LT		 2495}
2496
fc32b0e2 2497static void tx_timeout_task(struct work_struct *ugly)
1da177e4 2498{
fc32b0e2 2499 struct mv643xx_eth_private *mp;
1da177e4 2500
fc32b0e2
LB		 2501 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2502 if (netif_running(mp->dev)) {
e5ef1de1 2503 netif_tx_stop_all_queues(mp->dev);
fc32b0e2
LB		 2504 port_reset(mp);
2505 port_start(mp);
e5ef1de1 2506 netif_tx_wake_all_queues(mp->dev);
fc32b0e2 2507 }
c9df406f
LB		 2508}
2509
c9df406f 2510static void mv643xx_eth_tx_timeout(struct net_device *dev)
1da177e4 2511{
e5371493 2512 struct mv643xx_eth_private *mp = netdev_priv(dev);
1da177e4 2513
7542db8b 2514 netdev_info(dev, "tx timeout\n");
d0412d96 2515
c9df406f 2516 schedule_work(&mp->tx_timeout_task);
1da177e4
LT		 2517}
2518
c9df406f 2519#ifdef CONFIG_NET_POLL_CONTROLLER
fc32b0e2 2520static void mv643xx_eth_netpoll(struct net_device *dev)
9f8dd319 2521{
fc32b0e2 2522 struct mv643xx_eth_private *mp = netdev_priv(dev);
c9df406f 2523
37a6084f
LB		 2524 wrlp(mp, INT_MASK, 0x00000000);
2525 rdlp(mp, INT_MASK);
c9df406f 2526
fc32b0e2 2527 mv643xx_eth_irq(dev->irq, dev);
c9df406f 2528
e0ca8410 2529 wrlp(mp, INT_MASK, mp->int_mask);
9f8dd319 2530}
c9df406f 2531#endif
9f8dd319 2532
9f8dd319 2533
c9df406f 2534/* platform glue ************************************************************/
e5371493
LB		 2535static void
2536mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
63a9332b 2537 const struct mbus_dram_target_info *dram)
c9df406f 2538{
cc9754b3 2539 void __iomem *base = msp->base;
c9df406f
LB		 2540 u32 win_enable;
2541 u32 win_protect;
2542 int i;
9f8dd319 2543
c9df406f
LB		 2544 for (i = 0; i < 6; i++) {
2545 writel(0, base + WINDOW_BASE(i));
2546 writel(0, base + WINDOW_SIZE(i));
2547 if (i < 4)
2548 writel(0, base + WINDOW_REMAP_HIGH(i));
9f8dd319
DF		 2549 }
2550
c9df406f
LB		 2551 win_enable = 0x3f;
2552 win_protect = 0;
2553
2554 for (i = 0; i < dram->num_cs; i++) {
63a9332b 2555 const struct mbus_dram_window *cs = dram->cs + i;
c9df406f
LB		 2556
2557 writel((cs->base & 0xffff0000) |
2558 (cs->mbus_attr << 8) |
2559 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2560 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2561
2562 win_enable &= ~(1 << i);
2563 win_protect |= 3 << (2 * i);
2564 }
2565
2566 writel(win_enable, base + WINDOW_BAR_ENABLE);
2567 msp->win_protect = win_protect;
9f8dd319
DF		 2568}
2569
773fc3ee
LB		 2570static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2571{
2572 /*
2573 * Check whether we have a 14-bit coal limit field in bits
2574 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2575 * SDMA config register.
2576 */
37a6084f
LB		 2577 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2578 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
773fc3ee
LB		 2579 msp->extended_rx_coal_limit = 1;
2580 else
2581 msp->extended_rx_coal_limit = 0;
1e881592
LB		 2582
2583 /*
457b1d5a
LB		 2584 * Check whether the MAC supports TX rate control, and if
2585 * yes, whether its associated registers are in the old or
2586 * the new place.
1e881592 2587 */
37a6084f
LB		 2588 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2589 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
457b1d5a
LB		 2590 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2591 } else {
37a6084f
LB		 2592 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2593 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
457b1d5a
LB		 2594 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2595 else
2596 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2597 }
773fc3ee
LB		 2598}
2599
c9df406f 2600static int mv643xx_eth_shared_probe(struct platform_device *pdev)
9f8dd319 2601{
10a9948d 2602 static int mv643xx_eth_version_printed;
c9df406f 2603 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
e5371493 2604 struct mv643xx_eth_shared_private *msp;
63a9332b 2605 const struct mbus_dram_target_info *dram;
c9df406f
LB		 2606 struct resource *res;
2607 int ret;
9f8dd319 2608
e5371493 2609 if (!mv643xx_eth_version_printed++)
7542db8b
JP		 2610 pr_notice("MV-643xx 10/100/1000 ethernet driver version %s\n",
2611 mv643xx_eth_driver_version);
9f8dd319 2612
c9df406f
LB		 2613 ret = -EINVAL;
2614 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2615 if (res == NULL)
2616 goto out;
9f8dd319 2617
c9df406f 2618 ret = -ENOMEM;
beae22e6 2619 msp = kzalloc(sizeof(*msp), GFP_KERNEL);
c9df406f
LB		 2620 if (msp == NULL)
2621 goto out;
c9df406f 2622
28f65c11 2623 msp->base = ioremap(res->start, resource_size(res));
cc9754b3 2624 if (msp->base == NULL)
c9df406f
LB		 2625 goto out_free;
2626
ed94493f
LB		 2627 /*
2628 * Set up and register SMI bus.
2629 */
2630 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be
LB		 2631 msp->smi_bus = mdiobus_alloc();
2632 if (msp->smi_bus == NULL)
ed94493f 2633 goto out_unmap;
298cf9be
LB		 2634
2635 msp->smi_bus->priv = msp;
2636 msp->smi_bus->name = "mv643xx_eth smi";
2637 msp->smi_bus->read = smi_bus_read;
2638 msp->smi_bus->write = smi_bus_write,
12322431
FF		 2639 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
2640 pdev->name, pdev->id);
298cf9be
LB		 2641 msp->smi_bus->parent = &pdev->dev;
2642 msp->smi_bus->phy_mask = 0xffffffff;
2643 if (mdiobus_register(msp->smi_bus) < 0)
2644 goto out_free_mii_bus;
ed94493f
LB		 2645 msp->smi = msp;
2646 } else {
fc0eb9f2 2647 msp->smi = platform_get_drvdata(pd->shared_smi);
ed94493f 2648 }
c9df406f 2649
45c5d3bc
LB		 2650 msp->err_interrupt = NO_IRQ;
2651 init_waitqueue_head(&msp->smi_busy_wait);
2652
2653 /*
2654 * Check whether the error interrupt is hooked up.
2655 */
2656 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2657 if (res != NULL) {
2658 int err;
2659
2660 err = request_irq(res->start, mv643xx_eth_err_irq,
2661 IRQF_SHARED, "mv643xx_eth", msp);
2662 if (!err) {
2663 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2664 msp->err_interrupt = res->start;
2665 }
2666 }
2667
c9df406f
LB		 2668 /*
2669 * (Re-)program MBUS remapping windows if we are asked to.
2670 */
63a9332b
AL		 2671 dram = mv_mbus_dram_info();
2672 if (dram)
2673 mv643xx_eth_conf_mbus_windows(msp, dram);
c9df406f 2674
50a749c1
DC		 2675 msp->tx_csum_limit = (pd != NULL && pd->tx_csum_limit) ?
2676 pd->tx_csum_limit : 9 * 1024;
773fc3ee 2677 infer_hw_params(msp);
fc32b0e2
LB		 2678
2679 platform_set_drvdata(pdev, msp);
2680
c9df406f
LB		 2681 return 0;
2682
298cf9be
LB		 2683out_free_mii_bus:
2684 mdiobus_free(msp->smi_bus);
ed94493f
LB		 2685out_unmap:
2686 iounmap(msp->base);
c9df406f
LB		 2687out_free:
2688 kfree(msp);
2689out:
2690 return ret;
2691}
2692
2693static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2694{
e5371493 2695 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
ed94493f 2696 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
c9df406f 2697
298cf9be 2698 if (pd == NULL || pd->shared_smi == NULL) {
298cf9be 2699 mdiobus_unregister(msp->smi_bus);
bcb3336c 2700 mdiobus_free(msp->smi_bus);
298cf9be 2701 }
45c5d3bc
LB		 2702 if (msp->err_interrupt != NO_IRQ)
2703 free_irq(msp->err_interrupt, msp);
cc9754b3 2704 iounmap(msp->base);
c9df406f
LB		 2705 kfree(msp);
2706
2707 return 0;
9f8dd319
DF		 2708}
2709
c9df406f 2710static struct platform_driver mv643xx_eth_shared_driver = {
fc32b0e2
LB		 2711 .probe = mv643xx_eth_shared_probe,
2712 .remove = mv643xx_eth_shared_remove,
c9df406f 2713 .driver = {
fc32b0e2 2714 .name = MV643XX_ETH_SHARED_NAME,
c9df406f
LB		 2715 .owner = THIS_MODULE,
2716 },
2717};
2718
e5371493 2719static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
1da177e4 2720{
c9df406f 2721 int addr_shift = 5 * mp->port_num;
fc32b0e2 2722 u32 data;
1da177e4 2723
fc32b0e2
LB		 2724 data = rdl(mp, PHY_ADDR);
2725 data &= ~(0x1f << addr_shift);
2726 data |= (phy_addr & 0x1f) << addr_shift;
2727 wrl(mp, PHY_ADDR, data);
1da177e4
LT		 2728}
2729
e5371493 2730static int phy_addr_get(struct mv643xx_eth_private *mp)
1da177e4 2731{
fc32b0e2
LB		 2732 unsigned int data;
2733
2734 data = rdl(mp, PHY_ADDR);
2735
2736 return (data >> (5 * mp->port_num)) & 0x1f;
2737}
2738
2739static void set_params(struct mv643xx_eth_private *mp,
2740 struct mv643xx_eth_platform_data *pd)
2741{
2742 struct net_device *dev = mp->dev;
2743
2744 if (is_valid_ether_addr(pd->mac_addr))
2745 memcpy(dev->dev_addr, pd->mac_addr, 6);
2746 else
2747 uc_addr_get(mp, dev->dev_addr);
2748
e7d2f4db 2749 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
fc32b0e2 2750 if (pd->rx_queue_size)
e7d2f4db 2751 mp->rx_ring_size = pd->rx_queue_size;
fc32b0e2
LB		 2752 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2753 mp->rx_desc_sram_size = pd->rx_sram_size;
1da177e4 2754
f7981c1c 2755 mp->rxq_count = pd->rx_queue_count ? : 1;
64da80a2 2756
e7d2f4db 2757 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
fc32b0e2 2758 if (pd->tx_queue_size)
e7d2f4db 2759 mp->tx_ring_size = pd->tx_queue_size;
fc32b0e2
LB		 2760 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2761 mp->tx_desc_sram_size = pd->tx_sram_size;
3d6b35bc 2762
f7981c1c 2763 mp->txq_count = pd->tx_queue_count ? : 1;
1da177e4
LT		 2764}
2765
ed94493f
LB		 2766static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2767 int phy_addr)
1da177e4 2768{
298cf9be 2769 struct mii_bus *bus = mp->shared->smi->smi_bus;
ed94493f
LB		 2770 struct phy_device *phydev;
2771 int start;
2772 int num;
2773 int i;
45c5d3bc 2774
ed94493f
LB		 2775 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2776 start = phy_addr_get(mp) & 0x1f;
2777 num = 32;
2778 } else {
2779 start = phy_addr & 0x1f;
2780 num = 1;
2781 }
45c5d3bc 2782
ed94493f
LB		 2783 phydev = NULL;
2784 for (i = 0; i < num; i++) {
2785 int addr = (start + i) & 0x1f;
fc32b0e2 2786
ed94493f
LB		 2787 if (bus->phy_map[addr] == NULL)
2788 mdiobus_scan(bus, addr);
1da177e4 2789
ed94493f
LB		 2790 if (phydev == NULL) {
2791 phydev = bus->phy_map[addr];
2792 if (phydev != NULL)
2793 phy_addr_set(mp, addr);
2794 }
2795 }
1da177e4 2796
ed94493f 2797 return phydev;
1da177e4
LT		 2798}
2799
ed94493f 2800static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
c28a4f89 2801{
ed94493f 2802 struct phy_device *phy = mp->phy;
c28a4f89 2803
fc32b0e2
LB		 2804 phy_reset(mp);
2805
db1d7bf7 2806 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
ed94493f
LB		 2807
2808 if (speed == 0) {
2809 phy->autoneg = AUTONEG_ENABLE;
2810 phy->speed = 0;
2811 phy->duplex = 0;
2812 phy->advertising = phy->supported | ADVERTISED_Autoneg;
c9df406f 2813 } else {
ed94493f
LB		 2814 phy->autoneg = AUTONEG_DISABLE;
2815 phy->advertising = 0;
2816 phy->speed = speed;
2817 phy->duplex = duplex;
c9df406f 2818 }
ed94493f 2819 phy_start_aneg(phy);
c28a4f89
JC		 2820}
2821
81600eea
LB		 2822static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2823{
2824 u32 pscr;
2825
37a6084f 2826 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
81600eea
LB		 2827 if (pscr & SERIAL_PORT_ENABLE) {
2828 pscr &= ~SERIAL_PORT_ENABLE;
37a6084f 2829 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2830 }
2831
2832 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
ed94493f 2833 if (mp->phy == NULL) {
81600eea
LB		 2834 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2835 if (speed == SPEED_1000)
2836 pscr |= SET_GMII_SPEED_TO_1000;
2837 else if (speed == SPEED_100)
2838 pscr |= SET_MII_SPEED_TO_100;
2839
2840 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2841
2842 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2843 if (duplex == DUPLEX_FULL)
2844 pscr |= SET_FULL_DUPLEX_MODE;
2845 }
2846
37a6084f 2847 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
81600eea
LB		 2848}
2849
ea8a8642
LB		 2850static const struct net_device_ops mv643xx_eth_netdev_ops = {
2851 .ndo_open = mv643xx_eth_open,
2852 .ndo_stop = mv643xx_eth_stop,
2853 .ndo_start_xmit = mv643xx_eth_xmit,
2854 .ndo_set_rx_mode = mv643xx_eth_set_rx_mode,
2855 .ndo_set_mac_address = mv643xx_eth_set_mac_address,
1d4bd947 2856 .ndo_validate_addr = eth_validate_addr,
ea8a8642
LB		 2857 .ndo_do_ioctl = mv643xx_eth_ioctl,
2858 .ndo_change_mtu = mv643xx_eth_change_mtu,
aad59c43 2859 .ndo_set_features = mv643xx_eth_set_features,
ea8a8642
LB		 2860 .ndo_tx_timeout = mv643xx_eth_tx_timeout,
2861 .ndo_get_stats = mv643xx_eth_get_stats,
2862#ifdef CONFIG_NET_POLL_CONTROLLER
2863 .ndo_poll_controller = mv643xx_eth_netpoll,
2864#endif
2865};
2866
c9df406f 2867static int mv643xx_eth_probe(struct platform_device *pdev)
1da177e4 2868{
c9df406f 2869 struct mv643xx_eth_platform_data *pd;
e5371493 2870 struct mv643xx_eth_private *mp;
c9df406f 2871 struct net_device *dev;
c9df406f 2872 struct resource *res;
fc32b0e2 2873 int err;
1da177e4 2874
c9df406f
LB		 2875 pd = pdev->dev.platform_data;
2876 if (pd == NULL) {
7542db8b 2877 dev_err(&pdev->dev, "no mv643xx_eth_platform_data\n");
c9df406f
LB		 2878 return -ENODEV;
2879 }
1da177e4 2880
c9df406f 2881 if (pd->shared == NULL) {
7542db8b 2882 dev_err(&pdev->dev, "no mv643xx_eth_platform_data->shared\n");
c9df406f
LB		 2883 return -ENODEV;
2884 }
8f518703 2885
e5ef1de1 2886 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
c9df406f
LB		 2887 if (!dev)
2888 return -ENOMEM;
1da177e4 2889
c9df406f 2890 mp = netdev_priv(dev);
fc32b0e2
LB		 2891 platform_set_drvdata(pdev, mp);
2892
2893 mp->shared = platform_get_drvdata(pd->shared);
37a6084f 2894 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
fc32b0e2
LB		 2895 mp->port_num = pd->port_number;
2896
c9df406f 2897 mp->dev = dev;
78fff83b 2898
452503eb 2899 /*
9a43a026
AL		 2900 * Start with a default rate, and if there is a clock, allow
2901 * it to override the default.
452503eb 2902 */
9a43a026
AL		 2903 mp->t_clk = 133000000;
2904#if defined(CONFIG_HAVE_CLK)
452503eb
AL		 2905 mp->clk = clk_get(&pdev->dev, (pdev->id ? "1" : "0"));
2906 if (!IS_ERR(mp->clk)) {
2907 clk_prepare_enable(mp->clk);
2908 mp->t_clk = clk_get_rate(mp->clk);
452503eb 2909 }
9a43a026 2910#endif
fc32b0e2 2911 set_params(mp, pd);
206d6b32
BH		 2912 netif_set_real_num_tx_queues(dev, mp->txq_count);
2913 netif_set_real_num_rx_queues(dev, mp->rxq_count);
fc32b0e2 2914
ed94493f
LB		 2915 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2916 mp->phy = phy_scan(mp, pd->phy_addr);
bedfe324 2917
6bdf576e 2918 if (mp->phy != NULL)
ed94493f 2919 phy_init(mp, pd->speed, pd->duplex);
6bdf576e
LB		 2920
2921 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
ed94493f 2922
81600eea 2923 init_pscr(mp, pd->speed, pd->duplex);
fc32b0e2 2924
4ff3495a
LB		 2925
2926 mib_counters_clear(mp);
2927
2928 init_timer(&mp->mib_counters_timer);
2929 mp->mib_counters_timer.data = (unsigned long)mp;
2930 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2931 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2932 add_timer(&mp->mib_counters_timer);
2933
2934 spin_lock_init(&mp->mib_counters_lock);
2935
2936 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2937
2257e05c
LB		 2938 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2939
2940 init_timer(&mp->rx_oom);
2941 mp->rx_oom.data = (unsigned long)mp;
2942 mp->rx_oom.function = oom_timer_wrapper;
2943
fc32b0e2 2944
c9df406f
LB		 2945 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2946 BUG_ON(!res);
2947 dev->irq = res->start;
1da177e4 2948
ea8a8642
LB		 2949 dev->netdev_ops = &mv643xx_eth_netdev_ops;
2950
c9df406f
LB		 2951 dev->watchdog_timeo = 2 * HZ;
2952 dev->base_addr = 0;
1da177e4 2953
aad59c43
MM		 2954 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
2955 NETIF_F_RXCSUM | NETIF_F_LRO;
2956 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
e32b6617 2957 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
1da177e4 2958
01789349
JP		 2959 dev->priv_flags |= IFF_UNICAST_FLT;
2960
fc32b0e2 2961 SET_NETDEV_DEV(dev, &pdev->dev);
8f518703 2962
c9df406f 2963 if (mp->shared->win_protect)
fc32b0e2 2964 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
1da177e4 2965
a5fe3616
LB		 2966 netif_carrier_off(dev);
2967
b5e86db4
LB		 2968 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2969
4fb0a54a 2970 set_rx_coal(mp, 250);
a5fe3616
LB		 2971 set_tx_coal(mp, 0);
2972
c9df406f
LB		 2973 err = register_netdev(dev);
2974 if (err)
2975 goto out;
1da177e4 2976
7542db8b
JP		 2977 netdev_notice(dev, "port %d with MAC address %pM\n",
2978 mp->port_num, dev->dev_addr);
1da177e4 2979
13d64285 2980 if (mp->tx_desc_sram_size > 0)
7542db8b 2981 netdev_notice(dev, "configured with sram\n");
1da177e4 2982
c9df406f 2983 return 0;
1da177e4 2984
c9df406f
LB		 2985out:
2986 free_netdev(dev);
1da177e4 2987
c9df406f 2988 return err;
1da177e4
LT		 2989}
2990
c9df406f 2991static int mv643xx_eth_remove(struct platform_device *pdev)
1da177e4 2992{
fc32b0e2 2993 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
1da177e4 2994
fc32b0e2 2995 unregister_netdev(mp->dev);
ed94493f
LB		 2996 if (mp->phy != NULL)
2997 phy_detach(mp->phy);
23f333a2 2998 cancel_work_sync(&mp->tx_timeout_task);
452503eb 2999
9a43a026 3000#if defined(CONFIG_HAVE_CLK)
452503eb
AL		 3001 if (!IS_ERR(mp->clk)) {
3002 clk_disable_unprepare(mp->clk);
3003 clk_put(mp->clk);
3004 }
9a43a026
AL		 3005#endif
3006
fc32b0e2 3007 free_netdev(mp->dev);
c9df406f 3008
c9df406f 3009 platform_set_drvdata(pdev, NULL);
fc32b0e2 3010
c9df406f 3011 return 0;
1da177e4
LT		 3012}
3013
c9df406f 3014static void mv643xx_eth_shutdown(struct platform_device *pdev)
d0412d96 3015{
fc32b0e2 3016 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
d0412d96 3017
c9df406f 3018 /* Mask all interrupts on ethernet port */
37a6084f
LB		 3019 wrlp(mp, INT_MASK, 0);
3020 rdlp(mp, INT_MASK);
c9df406f 3021
fc32b0e2
LB		 3022 if (netif_running(mp->dev))
3023 port_reset(mp);
d0412d96
JC		 3024}
3025
c9df406f 3026static struct platform_driver mv643xx_eth_driver = {
fc32b0e2
LB		 3027 .probe = mv643xx_eth_probe,
3028 .remove = mv643xx_eth_remove,
3029 .shutdown = mv643xx_eth_shutdown,
c9df406f 3030 .driver = {
fc32b0e2 3031 .name = MV643XX_ETH_NAME,
c9df406f
LB		 3032 .owner = THIS_MODULE,
3033 },
3034};
3035
e5371493 3036static int __init mv643xx_eth_init_module(void)
d0412d96 3037{
c9df406f 3038 int rc;
d0412d96 3039
c9df406f
LB		 3040 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3041 if (!rc) {
3042 rc = platform_driver_register(&mv643xx_eth_driver);
3043 if (rc)
3044 platform_driver_unregister(&mv643xx_eth_shared_driver);
3045 }
fc32b0e2 3046
c9df406f 3047 return rc;
d0412d96 3048}
fc32b0e2 3049module_init(mv643xx_eth_init_module);
d0412d96 3050
e5371493 3051static void __exit mv643xx_eth_cleanup_module(void)
d0412d96 3052{
c9df406f
LB		 3053 platform_driver_unregister(&mv643xx_eth_driver);
3054 platform_driver_unregister(&mv643xx_eth_shared_driver);
d0412d96 3055}
e5371493 3056module_exit(mv643xx_eth_cleanup_module);
1da177e4 3057
45675bc6
LB		 3058MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3059 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
c9df406f 3060MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
fc32b0e2 3061MODULE_LICENSE("GPL");
c9df406f 3062MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
fc32b0e2 3063MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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