Commit | Line | Data |
---|---|---|
c5aff182 TP |
1 | /* |
2 | * Driver for Marvell NETA network card for Armada XP and Armada 370 SoCs. | |
3 | * | |
4 | * Copyright (C) 2012 Marvell | |
5 | * | |
6 | * Rami Rosen <rosenr@marvell.com> | |
7 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
8 | * | |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
c5aff182 TP |
15 | #include <linux/netdevice.h> |
16 | #include <linux/etherdevice.h> | |
17 | #include <linux/platform_device.h> | |
18 | #include <linux/skbuff.h> | |
19 | #include <linux/inetdevice.h> | |
20 | #include <linux/mbus.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/interrupt.h> | |
2d39d120 | 23 | #include <linux/if_vlan.h> |
c5aff182 TP |
24 | #include <net/ip.h> |
25 | #include <net/ipv6.h> | |
c3f0dd38 | 26 | #include <linux/io.h> |
2adb719d | 27 | #include <net/tso.h> |
c5aff182 TP |
28 | #include <linux/of.h> |
29 | #include <linux/of_irq.h> | |
30 | #include <linux/of_mdio.h> | |
31 | #include <linux/of_net.h> | |
32 | #include <linux/of_address.h> | |
33 | #include <linux/phy.h> | |
189dd626 | 34 | #include <linux/clk.h> |
f8642885 | 35 | #include <linux/cpu.h> |
c5aff182 TP |
36 | |
37 | /* Registers */ | |
38 | #define MVNETA_RXQ_CONFIG_REG(q) (0x1400 + ((q) << 2)) | |
e5bdf689 | 39 | #define MVNETA_RXQ_HW_BUF_ALLOC BIT(0) |
c5aff182 TP |
40 | #define MVNETA_RXQ_PKT_OFFSET_ALL_MASK (0xf << 8) |
41 | #define MVNETA_RXQ_PKT_OFFSET_MASK(offs) ((offs) << 8) | |
42 | #define MVNETA_RXQ_THRESHOLD_REG(q) (0x14c0 + ((q) << 2)) | |
43 | #define MVNETA_RXQ_NON_OCCUPIED(v) ((v) << 16) | |
44 | #define MVNETA_RXQ_BASE_ADDR_REG(q) (0x1480 + ((q) << 2)) | |
45 | #define MVNETA_RXQ_SIZE_REG(q) (0x14a0 + ((q) << 2)) | |
46 | #define MVNETA_RXQ_BUF_SIZE_SHIFT 19 | |
47 | #define MVNETA_RXQ_BUF_SIZE_MASK (0x1fff << 19) | |
48 | #define MVNETA_RXQ_STATUS_REG(q) (0x14e0 + ((q) << 2)) | |
49 | #define MVNETA_RXQ_OCCUPIED_ALL_MASK 0x3fff | |
50 | #define MVNETA_RXQ_STATUS_UPDATE_REG(q) (0x1500 + ((q) << 2)) | |
51 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT 16 | |
52 | #define MVNETA_RXQ_ADD_NON_OCCUPIED_MAX 255 | |
53 | #define MVNETA_PORT_RX_RESET 0x1cc0 | |
54 | #define MVNETA_PORT_RX_DMA_RESET BIT(0) | |
55 | #define MVNETA_PHY_ADDR 0x2000 | |
56 | #define MVNETA_PHY_ADDR_MASK 0x1f | |
57 | #define MVNETA_MBUS_RETRY 0x2010 | |
58 | #define MVNETA_UNIT_INTR_CAUSE 0x2080 | |
59 | #define MVNETA_UNIT_CONTROL 0x20B0 | |
60 | #define MVNETA_PHY_POLLING_ENABLE BIT(1) | |
61 | #define MVNETA_WIN_BASE(w) (0x2200 + ((w) << 3)) | |
62 | #define MVNETA_WIN_SIZE(w) (0x2204 + ((w) << 3)) | |
63 | #define MVNETA_WIN_REMAP(w) (0x2280 + ((w) << 2)) | |
64 | #define MVNETA_BASE_ADDR_ENABLE 0x2290 | |
db6ba9a5 | 65 | #define MVNETA_ACCESS_PROTECT_ENABLE 0x2294 |
c5aff182 TP |
66 | #define MVNETA_PORT_CONFIG 0x2400 |
67 | #define MVNETA_UNI_PROMISC_MODE BIT(0) | |
68 | #define MVNETA_DEF_RXQ(q) ((q) << 1) | |
69 | #define MVNETA_DEF_RXQ_ARP(q) ((q) << 4) | |
70 | #define MVNETA_TX_UNSET_ERR_SUM BIT(12) | |
71 | #define MVNETA_DEF_RXQ_TCP(q) ((q) << 16) | |
72 | #define MVNETA_DEF_RXQ_UDP(q) ((q) << 19) | |
73 | #define MVNETA_DEF_RXQ_BPDU(q) ((q) << 22) | |
74 | #define MVNETA_RX_CSUM_WITH_PSEUDO_HDR BIT(25) | |
75 | #define MVNETA_PORT_CONFIG_DEFL_VALUE(q) (MVNETA_DEF_RXQ(q) | \ | |
76 | MVNETA_DEF_RXQ_ARP(q) | \ | |
77 | MVNETA_DEF_RXQ_TCP(q) | \ | |
78 | MVNETA_DEF_RXQ_UDP(q) | \ | |
79 | MVNETA_DEF_RXQ_BPDU(q) | \ | |
80 | MVNETA_TX_UNSET_ERR_SUM | \ | |
81 | MVNETA_RX_CSUM_WITH_PSEUDO_HDR) | |
82 | #define MVNETA_PORT_CONFIG_EXTEND 0x2404 | |
83 | #define MVNETA_MAC_ADDR_LOW 0x2414 | |
84 | #define MVNETA_MAC_ADDR_HIGH 0x2418 | |
85 | #define MVNETA_SDMA_CONFIG 0x241c | |
86 | #define MVNETA_SDMA_BRST_SIZE_16 4 | |
c5aff182 TP |
87 | #define MVNETA_RX_BRST_SZ_MASK(burst) ((burst) << 1) |
88 | #define MVNETA_RX_NO_DATA_SWAP BIT(4) | |
89 | #define MVNETA_TX_NO_DATA_SWAP BIT(5) | |
9ad8fef6 | 90 | #define MVNETA_DESC_SWAP BIT(6) |
c5aff182 TP |
91 | #define MVNETA_TX_BRST_SZ_MASK(burst) ((burst) << 22) |
92 | #define MVNETA_PORT_STATUS 0x2444 | |
93 | #define MVNETA_TX_IN_PRGRS BIT(1) | |
94 | #define MVNETA_TX_FIFO_EMPTY BIT(8) | |
95 | #define MVNETA_RX_MIN_FRAME_SIZE 0x247c | |
3f1dd4bc | 96 | #define MVNETA_SERDES_CFG 0x24A0 |
5445eaf3 | 97 | #define MVNETA_SGMII_SERDES_PROTO 0x0cc7 |
3f1dd4bc | 98 | #define MVNETA_QSGMII_SERDES_PROTO 0x0667 |
c5aff182 TP |
99 | #define MVNETA_TYPE_PRIO 0x24bc |
100 | #define MVNETA_FORCE_UNI BIT(21) | |
101 | #define MVNETA_TXQ_CMD_1 0x24e4 | |
102 | #define MVNETA_TXQ_CMD 0x2448 | |
103 | #define MVNETA_TXQ_DISABLE_SHIFT 8 | |
104 | #define MVNETA_TXQ_ENABLE_MASK 0x000000ff | |
e483911f AL |
105 | #define MVNETA_RX_DISCARD_FRAME_COUNT 0x2484 |
106 | #define MVNETA_OVERRUN_FRAME_COUNT 0x2488 | |
898b2970 SS |
107 | #define MVNETA_GMAC_CLOCK_DIVIDER 0x24f4 |
108 | #define MVNETA_GMAC_1MS_CLOCK_ENABLE BIT(31) | |
c5aff182 TP |
109 | #define MVNETA_ACC_MODE 0x2500 |
110 | #define MVNETA_CPU_MAP(cpu) (0x2540 + ((cpu) << 2)) | |
111 | #define MVNETA_CPU_RXQ_ACCESS_ALL_MASK 0x000000ff | |
112 | #define MVNETA_CPU_TXQ_ACCESS_ALL_MASK 0x0000ff00 | |
2dcf75e2 | 113 | #define MVNETA_CPU_RXQ_ACCESS(rxq) BIT(rxq) |
50bf8cb6 | 114 | #define MVNETA_CPU_TXQ_ACCESS(txq) BIT(txq + 8) |
c5aff182 | 115 | #define MVNETA_RXQ_TIME_COAL_REG(q) (0x2580 + ((q) << 2)) |
40ba35e7 | 116 | |
2dcf75e2 GC |
117 | /* Exception Interrupt Port/Queue Cause register |
118 | * | |
119 | * Their behavior depend of the mapping done using the PCPX2Q | |
120 | * registers. For a given CPU if the bit associated to a queue is not | |
121 | * set, then for the register a read from this CPU will always return | |
122 | * 0 and a write won't do anything | |
123 | */ | |
40ba35e7 | 124 | |
c5aff182 | 125 | #define MVNETA_INTR_NEW_CAUSE 0x25a0 |
c5aff182 | 126 | #define MVNETA_INTR_NEW_MASK 0x25a4 |
40ba35e7 | 127 | |
128 | /* bits 0..7 = TXQ SENT, one bit per queue. | |
129 | * bits 8..15 = RXQ OCCUP, one bit per queue. | |
130 | * bits 16..23 = RXQ FREE, one bit per queue. | |
131 | * bit 29 = OLD_REG_SUM, see old reg ? | |
132 | * bit 30 = TX_ERR_SUM, one bit for 4 ports | |
133 | * bit 31 = MISC_SUM, one bit for 4 ports | |
134 | */ | |
135 | #define MVNETA_TX_INTR_MASK(nr_txqs) (((1 << nr_txqs) - 1) << 0) | |
136 | #define MVNETA_TX_INTR_MASK_ALL (0xff << 0) | |
137 | #define MVNETA_RX_INTR_MASK(nr_rxqs) (((1 << nr_rxqs) - 1) << 8) | |
138 | #define MVNETA_RX_INTR_MASK_ALL (0xff << 8) | |
898b2970 | 139 | #define MVNETA_MISCINTR_INTR_MASK BIT(31) |
40ba35e7 | 140 | |
c5aff182 TP |
141 | #define MVNETA_INTR_OLD_CAUSE 0x25a8 |
142 | #define MVNETA_INTR_OLD_MASK 0x25ac | |
40ba35e7 | 143 | |
144 | /* Data Path Port/Queue Cause Register */ | |
c5aff182 TP |
145 | #define MVNETA_INTR_MISC_CAUSE 0x25b0 |
146 | #define MVNETA_INTR_MISC_MASK 0x25b4 | |
40ba35e7 | 147 | |
148 | #define MVNETA_CAUSE_PHY_STATUS_CHANGE BIT(0) | |
149 | #define MVNETA_CAUSE_LINK_CHANGE BIT(1) | |
150 | #define MVNETA_CAUSE_PTP BIT(4) | |
151 | ||
152 | #define MVNETA_CAUSE_INTERNAL_ADDR_ERR BIT(7) | |
153 | #define MVNETA_CAUSE_RX_OVERRUN BIT(8) | |
154 | #define MVNETA_CAUSE_RX_CRC_ERROR BIT(9) | |
155 | #define MVNETA_CAUSE_RX_LARGE_PKT BIT(10) | |
156 | #define MVNETA_CAUSE_TX_UNDERUN BIT(11) | |
157 | #define MVNETA_CAUSE_PRBS_ERR BIT(12) | |
158 | #define MVNETA_CAUSE_PSC_SYNC_CHANGE BIT(13) | |
159 | #define MVNETA_CAUSE_SERDES_SYNC_ERR BIT(14) | |
160 | ||
161 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT 16 | |
162 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_ALL_MASK (0xF << MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT) | |
163 | #define MVNETA_CAUSE_BMU_ALLOC_ERR_MASK(pool) (1 << (MVNETA_CAUSE_BMU_ALLOC_ERR_SHIFT + (pool))) | |
164 | ||
165 | #define MVNETA_CAUSE_TXQ_ERROR_SHIFT 24 | |
166 | #define MVNETA_CAUSE_TXQ_ERROR_ALL_MASK (0xFF << MVNETA_CAUSE_TXQ_ERROR_SHIFT) | |
167 | #define MVNETA_CAUSE_TXQ_ERROR_MASK(q) (1 << (MVNETA_CAUSE_TXQ_ERROR_SHIFT + (q))) | |
168 | ||
c5aff182 TP |
169 | #define MVNETA_INTR_ENABLE 0x25b8 |
170 | #define MVNETA_TXQ_INTR_ENABLE_ALL_MASK 0x0000ff00 | |
dc1aadf6 | 171 | #define MVNETA_RXQ_INTR_ENABLE_ALL_MASK 0x000000ff |
40ba35e7 | 172 | |
c5aff182 TP |
173 | #define MVNETA_RXQ_CMD 0x2680 |
174 | #define MVNETA_RXQ_DISABLE_SHIFT 8 | |
175 | #define MVNETA_RXQ_ENABLE_MASK 0x000000ff | |
176 | #define MVETH_TXQ_TOKEN_COUNT_REG(q) (0x2700 + ((q) << 4)) | |
177 | #define MVETH_TXQ_TOKEN_CFG_REG(q) (0x2704 + ((q) << 4)) | |
178 | #define MVNETA_GMAC_CTRL_0 0x2c00 | |
179 | #define MVNETA_GMAC_MAX_RX_SIZE_SHIFT 2 | |
180 | #define MVNETA_GMAC_MAX_RX_SIZE_MASK 0x7ffc | |
181 | #define MVNETA_GMAC0_PORT_ENABLE BIT(0) | |
182 | #define MVNETA_GMAC_CTRL_2 0x2c08 | |
898b2970 | 183 | #define MVNETA_GMAC2_INBAND_AN_ENABLE BIT(0) |
a79121d3 | 184 | #define MVNETA_GMAC2_PCS_ENABLE BIT(3) |
c5aff182 TP |
185 | #define MVNETA_GMAC2_PORT_RGMII BIT(4) |
186 | #define MVNETA_GMAC2_PORT_RESET BIT(6) | |
187 | #define MVNETA_GMAC_STATUS 0x2c10 | |
188 | #define MVNETA_GMAC_LINK_UP BIT(0) | |
189 | #define MVNETA_GMAC_SPEED_1000 BIT(1) | |
190 | #define MVNETA_GMAC_SPEED_100 BIT(2) | |
191 | #define MVNETA_GMAC_FULL_DUPLEX BIT(3) | |
192 | #define MVNETA_GMAC_RX_FLOW_CTRL_ENABLE BIT(4) | |
193 | #define MVNETA_GMAC_TX_FLOW_CTRL_ENABLE BIT(5) | |
194 | #define MVNETA_GMAC_RX_FLOW_CTRL_ACTIVE BIT(6) | |
195 | #define MVNETA_GMAC_TX_FLOW_CTRL_ACTIVE BIT(7) | |
196 | #define MVNETA_GMAC_AUTONEG_CONFIG 0x2c0c | |
197 | #define MVNETA_GMAC_FORCE_LINK_DOWN BIT(0) | |
198 | #define MVNETA_GMAC_FORCE_LINK_PASS BIT(1) | |
898b2970 | 199 | #define MVNETA_GMAC_INBAND_AN_ENABLE BIT(2) |
c5aff182 TP |
200 | #define MVNETA_GMAC_CONFIG_MII_SPEED BIT(5) |
201 | #define MVNETA_GMAC_CONFIG_GMII_SPEED BIT(6) | |
71408602 | 202 | #define MVNETA_GMAC_AN_SPEED_EN BIT(7) |
898b2970 | 203 | #define MVNETA_GMAC_AN_FLOW_CTRL_EN BIT(11) |
c5aff182 | 204 | #define MVNETA_GMAC_CONFIG_FULL_DUPLEX BIT(12) |
71408602 | 205 | #define MVNETA_GMAC_AN_DUPLEX_EN BIT(13) |
e483911f | 206 | #define MVNETA_MIB_COUNTERS_BASE 0x3000 |
c5aff182 TP |
207 | #define MVNETA_MIB_LATE_COLLISION 0x7c |
208 | #define MVNETA_DA_FILT_SPEC_MCAST 0x3400 | |
209 | #define MVNETA_DA_FILT_OTH_MCAST 0x3500 | |
210 | #define MVNETA_DA_FILT_UCAST_BASE 0x3600 | |
211 | #define MVNETA_TXQ_BASE_ADDR_REG(q) (0x3c00 + ((q) << 2)) | |
212 | #define MVNETA_TXQ_SIZE_REG(q) (0x3c20 + ((q) << 2)) | |
213 | #define MVNETA_TXQ_SENT_THRESH_ALL_MASK 0x3fff0000 | |
214 | #define MVNETA_TXQ_SENT_THRESH_MASK(coal) ((coal) << 16) | |
215 | #define MVNETA_TXQ_UPDATE_REG(q) (0x3c60 + ((q) << 2)) | |
216 | #define MVNETA_TXQ_DEC_SENT_SHIFT 16 | |
217 | #define MVNETA_TXQ_STATUS_REG(q) (0x3c40 + ((q) << 2)) | |
218 | #define MVNETA_TXQ_SENT_DESC_SHIFT 16 | |
219 | #define MVNETA_TXQ_SENT_DESC_MASK 0x3fff0000 | |
220 | #define MVNETA_PORT_TX_RESET 0x3cf0 | |
221 | #define MVNETA_PORT_TX_DMA_RESET BIT(0) | |
222 | #define MVNETA_TX_MTU 0x3e0c | |
223 | #define MVNETA_TX_TOKEN_SIZE 0x3e14 | |
224 | #define MVNETA_TX_TOKEN_SIZE_MAX 0xffffffff | |
225 | #define MVNETA_TXQ_TOKEN_SIZE_REG(q) (0x3e40 + ((q) << 2)) | |
226 | #define MVNETA_TXQ_TOKEN_SIZE_MAX 0x7fffffff | |
227 | ||
228 | #define MVNETA_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff | |
229 | ||
230 | /* Descriptor ring Macros */ | |
231 | #define MVNETA_QUEUE_NEXT_DESC(q, index) \ | |
232 | (((index) < (q)->last_desc) ? ((index) + 1) : 0) | |
233 | ||
234 | /* Various constants */ | |
235 | ||
236 | /* Coalescing */ | |
aebea2ba | 237 | #define MVNETA_TXDONE_COAL_PKTS 1 |
c5aff182 TP |
238 | #define MVNETA_RX_COAL_PKTS 32 |
239 | #define MVNETA_RX_COAL_USEC 100 | |
240 | ||
6a20c175 | 241 | /* The two bytes Marvell header. Either contains a special value used |
c5aff182 TP |
242 | * by Marvell switches when a specific hardware mode is enabled (not |
243 | * supported by this driver) or is filled automatically by zeroes on | |
244 | * the RX side. Those two bytes being at the front of the Ethernet | |
245 | * header, they allow to have the IP header aligned on a 4 bytes | |
246 | * boundary automatically: the hardware skips those two bytes on its | |
247 | * own. | |
248 | */ | |
249 | #define MVNETA_MH_SIZE 2 | |
250 | ||
251 | #define MVNETA_VLAN_TAG_LEN 4 | |
252 | ||
253 | #define MVNETA_CPU_D_CACHE_LINE_SIZE 32 | |
9110ee07 | 254 | #define MVNETA_TX_CSUM_DEF_SIZE 1600 |
c5aff182 TP |
255 | #define MVNETA_TX_CSUM_MAX_SIZE 9800 |
256 | #define MVNETA_ACC_MODE_EXT 1 | |
257 | ||
258 | /* Timeout constants */ | |
259 | #define MVNETA_TX_DISABLE_TIMEOUT_MSEC 1000 | |
260 | #define MVNETA_RX_DISABLE_TIMEOUT_MSEC 1000 | |
261 | #define MVNETA_TX_FIFO_EMPTY_TIMEOUT 10000 | |
262 | ||
263 | #define MVNETA_TX_MTU_MAX 0x3ffff | |
264 | ||
9a401dea GC |
265 | /* The RSS lookup table actually has 256 entries but we do not use |
266 | * them yet | |
267 | */ | |
268 | #define MVNETA_RSS_LU_TABLE_SIZE 1 | |
269 | ||
2adb719d EG |
270 | /* TSO header size */ |
271 | #define TSO_HEADER_SIZE 128 | |
272 | ||
c5aff182 TP |
273 | /* Max number of Rx descriptors */ |
274 | #define MVNETA_MAX_RXD 128 | |
275 | ||
276 | /* Max number of Tx descriptors */ | |
277 | #define MVNETA_MAX_TXD 532 | |
278 | ||
8eef5f97 EG |
279 | /* Max number of allowed TCP segments for software TSO */ |
280 | #define MVNETA_MAX_TSO_SEGS 100 | |
281 | ||
282 | #define MVNETA_MAX_SKB_DESCS (MVNETA_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS) | |
283 | ||
c5aff182 TP |
284 | /* descriptor aligned size */ |
285 | #define MVNETA_DESC_ALIGNED_SIZE 32 | |
286 | ||
287 | #define MVNETA_RX_PKT_SIZE(mtu) \ | |
288 | ALIGN((mtu) + MVNETA_MH_SIZE + MVNETA_VLAN_TAG_LEN + \ | |
289 | ETH_HLEN + ETH_FCS_LEN, \ | |
290 | MVNETA_CPU_D_CACHE_LINE_SIZE) | |
291 | ||
2e3173a3 EG |
292 | #define IS_TSO_HEADER(txq, addr) \ |
293 | ((addr >= txq->tso_hdrs_phys) && \ | |
294 | (addr < txq->tso_hdrs_phys + txq->size * TSO_HEADER_SIZE)) | |
295 | ||
c5aff182 TP |
296 | #define MVNETA_RX_BUF_SIZE(pkt_size) ((pkt_size) + NET_SKB_PAD) |
297 | ||
9b0cdefa RK |
298 | struct mvneta_statistic { |
299 | unsigned short offset; | |
300 | unsigned short type; | |
301 | const char name[ETH_GSTRING_LEN]; | |
302 | }; | |
303 | ||
304 | #define T_REG_32 32 | |
305 | #define T_REG_64 64 | |
306 | ||
307 | static const struct mvneta_statistic mvneta_statistics[] = { | |
308 | { 0x3000, T_REG_64, "good_octets_received", }, | |
309 | { 0x3010, T_REG_32, "good_frames_received", }, | |
310 | { 0x3008, T_REG_32, "bad_octets_received", }, | |
311 | { 0x3014, T_REG_32, "bad_frames_received", }, | |
312 | { 0x3018, T_REG_32, "broadcast_frames_received", }, | |
313 | { 0x301c, T_REG_32, "multicast_frames_received", }, | |
314 | { 0x3050, T_REG_32, "unrec_mac_control_received", }, | |
315 | { 0x3058, T_REG_32, "good_fc_received", }, | |
316 | { 0x305c, T_REG_32, "bad_fc_received", }, | |
317 | { 0x3060, T_REG_32, "undersize_received", }, | |
318 | { 0x3064, T_REG_32, "fragments_received", }, | |
319 | { 0x3068, T_REG_32, "oversize_received", }, | |
320 | { 0x306c, T_REG_32, "jabber_received", }, | |
321 | { 0x3070, T_REG_32, "mac_receive_error", }, | |
322 | { 0x3074, T_REG_32, "bad_crc_event", }, | |
323 | { 0x3078, T_REG_32, "collision", }, | |
324 | { 0x307c, T_REG_32, "late_collision", }, | |
325 | { 0x2484, T_REG_32, "rx_discard", }, | |
326 | { 0x2488, T_REG_32, "rx_overrun", }, | |
327 | { 0x3020, T_REG_32, "frames_64_octets", }, | |
328 | { 0x3024, T_REG_32, "frames_65_to_127_octets", }, | |
329 | { 0x3028, T_REG_32, "frames_128_to_255_octets", }, | |
330 | { 0x302c, T_REG_32, "frames_256_to_511_octets", }, | |
331 | { 0x3030, T_REG_32, "frames_512_to_1023_octets", }, | |
332 | { 0x3034, T_REG_32, "frames_1024_to_max_octets", }, | |
333 | { 0x3038, T_REG_64, "good_octets_sent", }, | |
334 | { 0x3040, T_REG_32, "good_frames_sent", }, | |
335 | { 0x3044, T_REG_32, "excessive_collision", }, | |
336 | { 0x3048, T_REG_32, "multicast_frames_sent", }, | |
337 | { 0x304c, T_REG_32, "broadcast_frames_sent", }, | |
338 | { 0x3054, T_REG_32, "fc_sent", }, | |
339 | { 0x300c, T_REG_32, "internal_mac_transmit_err", }, | |
340 | }; | |
341 | ||
74c41b04 | 342 | struct mvneta_pcpu_stats { |
c5aff182 | 343 | struct u64_stats_sync syncp; |
74c41b04 | 344 | u64 rx_packets; |
345 | u64 rx_bytes; | |
346 | u64 tx_packets; | |
347 | u64 tx_bytes; | |
c5aff182 TP |
348 | }; |
349 | ||
12bb03b4 MR |
350 | struct mvneta_pcpu_port { |
351 | /* Pointer to the shared port */ | |
352 | struct mvneta_port *pp; | |
353 | ||
354 | /* Pointer to the CPU-local NAPI struct */ | |
355 | struct napi_struct napi; | |
356 | ||
357 | /* Cause of the previous interrupt */ | |
358 | u32 cause_rx_tx; | |
359 | }; | |
360 | ||
c5aff182 | 361 | struct mvneta_port { |
12bb03b4 MR |
362 | struct mvneta_pcpu_port __percpu *ports; |
363 | struct mvneta_pcpu_stats __percpu *stats; | |
364 | ||
c5aff182 | 365 | int pkt_size; |
8ec2cd48 | 366 | unsigned int frag_size; |
c5aff182 TP |
367 | void __iomem *base; |
368 | struct mvneta_rx_queue *rxqs; | |
369 | struct mvneta_tx_queue *txqs; | |
c5aff182 | 370 | struct net_device *dev; |
f8642885 | 371 | struct notifier_block cpu_notifier; |
90b74c01 | 372 | int rxq_def; |
c5aff182 | 373 | |
c5aff182 | 374 | /* Core clock */ |
189dd626 | 375 | struct clk *clk; |
c5aff182 TP |
376 | u8 mcast_count[256]; |
377 | u16 tx_ring_size; | |
378 | u16 rx_ring_size; | |
c5aff182 TP |
379 | |
380 | struct mii_bus *mii_bus; | |
381 | struct phy_device *phy_dev; | |
382 | phy_interface_t phy_interface; | |
383 | struct device_node *phy_node; | |
384 | unsigned int link; | |
385 | unsigned int duplex; | |
386 | unsigned int speed; | |
b65657fc | 387 | unsigned int tx_csum_limit; |
0c0744fc | 388 | unsigned int use_inband_status:1; |
9b0cdefa RK |
389 | |
390 | u64 ethtool_stats[ARRAY_SIZE(mvneta_statistics)]; | |
9a401dea GC |
391 | |
392 | u32 indir[MVNETA_RSS_LU_TABLE_SIZE]; | |
c5aff182 TP |
393 | }; |
394 | ||
6a20c175 | 395 | /* The mvneta_tx_desc and mvneta_rx_desc structures describe the |
c5aff182 TP |
396 | * layout of the transmit and reception DMA descriptors, and their |
397 | * layout is therefore defined by the hardware design | |
398 | */ | |
6083ed44 | 399 | |
c5aff182 TP |
400 | #define MVNETA_TX_L3_OFF_SHIFT 0 |
401 | #define MVNETA_TX_IP_HLEN_SHIFT 8 | |
402 | #define MVNETA_TX_L4_UDP BIT(16) | |
403 | #define MVNETA_TX_L3_IP6 BIT(17) | |
404 | #define MVNETA_TXD_IP_CSUM BIT(18) | |
405 | #define MVNETA_TXD_Z_PAD BIT(19) | |
406 | #define MVNETA_TXD_L_DESC BIT(20) | |
407 | #define MVNETA_TXD_F_DESC BIT(21) | |
408 | #define MVNETA_TXD_FLZ_DESC (MVNETA_TXD_Z_PAD | \ | |
409 | MVNETA_TXD_L_DESC | \ | |
410 | MVNETA_TXD_F_DESC) | |
411 | #define MVNETA_TX_L4_CSUM_FULL BIT(30) | |
412 | #define MVNETA_TX_L4_CSUM_NOT BIT(31) | |
413 | ||
c5aff182 TP |
414 | #define MVNETA_RXD_ERR_CRC 0x0 |
415 | #define MVNETA_RXD_ERR_SUMMARY BIT(16) | |
416 | #define MVNETA_RXD_ERR_OVERRUN BIT(17) | |
417 | #define MVNETA_RXD_ERR_LEN BIT(18) | |
418 | #define MVNETA_RXD_ERR_RESOURCE (BIT(17) | BIT(18)) | |
419 | #define MVNETA_RXD_ERR_CODE_MASK (BIT(17) | BIT(18)) | |
420 | #define MVNETA_RXD_L3_IP4 BIT(25) | |
421 | #define MVNETA_RXD_FIRST_LAST_DESC (BIT(26) | BIT(27)) | |
422 | #define MVNETA_RXD_L4_CSUM_OK BIT(30) | |
423 | ||
9ad8fef6 | 424 | #if defined(__LITTLE_ENDIAN) |
6083ed44 TP |
425 | struct mvneta_tx_desc { |
426 | u32 command; /* Options used by HW for packet transmitting.*/ | |
427 | u16 reserverd1; /* csum_l4 (for future use) */ | |
428 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
429 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
430 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
431 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
432 | }; | |
433 | ||
434 | struct mvneta_rx_desc { | |
435 | u32 status; /* Info about received packet */ | |
c5aff182 TP |
436 | u16 reserved1; /* pnc_info - (for future use, PnC) */ |
437 | u16 data_size; /* Size of received packet in bytes */ | |
6083ed44 | 438 | |
c5aff182 TP |
439 | u32 buf_phys_addr; /* Physical address of the buffer */ |
440 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
6083ed44 | 441 | |
c5aff182 TP |
442 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ |
443 | u16 reserved3; /* prefetch_cmd, for future use */ | |
444 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
6083ed44 | 445 | |
c5aff182 TP |
446 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ |
447 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
448 | }; | |
9ad8fef6 TP |
449 | #else |
450 | struct mvneta_tx_desc { | |
451 | u16 data_size; /* Data size of transmitted packet in bytes */ | |
452 | u16 reserverd1; /* csum_l4 (for future use) */ | |
453 | u32 command; /* Options used by HW for packet transmitting.*/ | |
454 | u32 reserved2; /* hw_cmd - (for future use, PMT) */ | |
455 | u32 buf_phys_addr; /* Physical addr of transmitted buffer */ | |
456 | u32 reserved3[4]; /* Reserved - (for future use) */ | |
457 | }; | |
458 | ||
459 | struct mvneta_rx_desc { | |
460 | u16 data_size; /* Size of received packet in bytes */ | |
461 | u16 reserved1; /* pnc_info - (for future use, PnC) */ | |
462 | u32 status; /* Info about received packet */ | |
463 | ||
464 | u32 reserved2; /* pnc_flow_id (for future use, PnC) */ | |
465 | u32 buf_phys_addr; /* Physical address of the buffer */ | |
466 | ||
467 | u16 reserved4; /* csum_l4 - (for future use, PnC) */ | |
468 | u16 reserved3; /* prefetch_cmd, for future use */ | |
469 | u32 buf_cookie; /* cookie for access to RX buffer in rx path */ | |
470 | ||
471 | u32 reserved5; /* pnc_extra PnC (for future use, PnC) */ | |
472 | u32 reserved6; /* hw_cmd (for future use, PnC and HWF) */ | |
473 | }; | |
474 | #endif | |
c5aff182 TP |
475 | |
476 | struct mvneta_tx_queue { | |
477 | /* Number of this TX queue, in the range 0-7 */ | |
478 | u8 id; | |
479 | ||
480 | /* Number of TX DMA descriptors in the descriptor ring */ | |
481 | int size; | |
482 | ||
483 | /* Number of currently used TX DMA descriptor in the | |
6a20c175 TP |
484 | * descriptor ring |
485 | */ | |
c5aff182 | 486 | int count; |
8eef5f97 EG |
487 | int tx_stop_threshold; |
488 | int tx_wake_threshold; | |
c5aff182 TP |
489 | |
490 | /* Array of transmitted skb */ | |
491 | struct sk_buff **tx_skb; | |
492 | ||
493 | /* Index of last TX DMA descriptor that was inserted */ | |
494 | int txq_put_index; | |
495 | ||
496 | /* Index of the TX DMA descriptor to be cleaned up */ | |
497 | int txq_get_index; | |
498 | ||
499 | u32 done_pkts_coal; | |
500 | ||
501 | /* Virtual address of the TX DMA descriptors array */ | |
502 | struct mvneta_tx_desc *descs; | |
503 | ||
504 | /* DMA address of the TX DMA descriptors array */ | |
505 | dma_addr_t descs_phys; | |
506 | ||
507 | /* Index of the last TX DMA descriptor */ | |
508 | int last_desc; | |
509 | ||
510 | /* Index of the next TX DMA descriptor to process */ | |
511 | int next_desc_to_proc; | |
2adb719d EG |
512 | |
513 | /* DMA buffers for TSO headers */ | |
514 | char *tso_hdrs; | |
515 | ||
516 | /* DMA address of TSO headers */ | |
517 | dma_addr_t tso_hdrs_phys; | |
50bf8cb6 GC |
518 | |
519 | /* Affinity mask for CPUs*/ | |
520 | cpumask_t affinity_mask; | |
c5aff182 TP |
521 | }; |
522 | ||
523 | struct mvneta_rx_queue { | |
524 | /* rx queue number, in the range 0-7 */ | |
525 | u8 id; | |
526 | ||
527 | /* num of rx descriptors in the rx descriptor ring */ | |
528 | int size; | |
529 | ||
530 | /* counter of times when mvneta_refill() failed */ | |
531 | int missed; | |
532 | ||
533 | u32 pkts_coal; | |
534 | u32 time_coal; | |
535 | ||
536 | /* Virtual address of the RX DMA descriptors array */ | |
537 | struct mvneta_rx_desc *descs; | |
538 | ||
539 | /* DMA address of the RX DMA descriptors array */ | |
540 | dma_addr_t descs_phys; | |
541 | ||
542 | /* Index of the last RX DMA descriptor */ | |
543 | int last_desc; | |
544 | ||
545 | /* Index of the next RX DMA descriptor to process */ | |
546 | int next_desc_to_proc; | |
547 | }; | |
548 | ||
edadb7fa EG |
549 | /* The hardware supports eight (8) rx queues, but we are only allowing |
550 | * the first one to be used. Therefore, let's just allocate one queue. | |
551 | */ | |
d8936657 | 552 | static int rxq_number = 8; |
c5aff182 TP |
553 | static int txq_number = 8; |
554 | ||
555 | static int rxq_def; | |
c5aff182 | 556 | |
f19fadfc | 557 | static int rx_copybreak __read_mostly = 256; |
558 | ||
c5aff182 TP |
559 | #define MVNETA_DRIVER_NAME "mvneta" |
560 | #define MVNETA_DRIVER_VERSION "1.0" | |
561 | ||
562 | /* Utility/helper methods */ | |
563 | ||
564 | /* Write helper method */ | |
565 | static void mvreg_write(struct mvneta_port *pp, u32 offset, u32 data) | |
566 | { | |
567 | writel(data, pp->base + offset); | |
568 | } | |
569 | ||
570 | /* Read helper method */ | |
571 | static u32 mvreg_read(struct mvneta_port *pp, u32 offset) | |
572 | { | |
573 | return readl(pp->base + offset); | |
574 | } | |
575 | ||
576 | /* Increment txq get counter */ | |
577 | static void mvneta_txq_inc_get(struct mvneta_tx_queue *txq) | |
578 | { | |
579 | txq->txq_get_index++; | |
580 | if (txq->txq_get_index == txq->size) | |
581 | txq->txq_get_index = 0; | |
582 | } | |
583 | ||
584 | /* Increment txq put counter */ | |
585 | static void mvneta_txq_inc_put(struct mvneta_tx_queue *txq) | |
586 | { | |
587 | txq->txq_put_index++; | |
588 | if (txq->txq_put_index == txq->size) | |
589 | txq->txq_put_index = 0; | |
590 | } | |
591 | ||
592 | ||
593 | /* Clear all MIB counters */ | |
594 | static void mvneta_mib_counters_clear(struct mvneta_port *pp) | |
595 | { | |
596 | int i; | |
597 | u32 dummy; | |
598 | ||
599 | /* Perform dummy reads from MIB counters */ | |
600 | for (i = 0; i < MVNETA_MIB_LATE_COLLISION; i += 4) | |
601 | dummy = mvreg_read(pp, (MVNETA_MIB_COUNTERS_BASE + i)); | |
e483911f AL |
602 | dummy = mvreg_read(pp, MVNETA_RX_DISCARD_FRAME_COUNT); |
603 | dummy = mvreg_read(pp, MVNETA_OVERRUN_FRAME_COUNT); | |
c5aff182 TP |
604 | } |
605 | ||
606 | /* Get System Network Statistics */ | |
607 | struct rtnl_link_stats64 *mvneta_get_stats64(struct net_device *dev, | |
608 | struct rtnl_link_stats64 *stats) | |
609 | { | |
610 | struct mvneta_port *pp = netdev_priv(dev); | |
611 | unsigned int start; | |
74c41b04 | 612 | int cpu; |
c5aff182 | 613 | |
74c41b04 | 614 | for_each_possible_cpu(cpu) { |
615 | struct mvneta_pcpu_stats *cpu_stats; | |
616 | u64 rx_packets; | |
617 | u64 rx_bytes; | |
618 | u64 tx_packets; | |
619 | u64 tx_bytes; | |
c5aff182 | 620 | |
74c41b04 | 621 | cpu_stats = per_cpu_ptr(pp->stats, cpu); |
622 | do { | |
57a7744e | 623 | start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); |
74c41b04 | 624 | rx_packets = cpu_stats->rx_packets; |
625 | rx_bytes = cpu_stats->rx_bytes; | |
626 | tx_packets = cpu_stats->tx_packets; | |
627 | tx_bytes = cpu_stats->tx_bytes; | |
57a7744e | 628 | } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); |
c5aff182 | 629 | |
74c41b04 | 630 | stats->rx_packets += rx_packets; |
631 | stats->rx_bytes += rx_bytes; | |
632 | stats->tx_packets += tx_packets; | |
633 | stats->tx_bytes += tx_bytes; | |
634 | } | |
c5aff182 TP |
635 | |
636 | stats->rx_errors = dev->stats.rx_errors; | |
637 | stats->rx_dropped = dev->stats.rx_dropped; | |
638 | ||
639 | stats->tx_dropped = dev->stats.tx_dropped; | |
640 | ||
641 | return stats; | |
642 | } | |
643 | ||
644 | /* Rx descriptors helper methods */ | |
645 | ||
5428213c | 646 | /* Checks whether the RX descriptor having this status is both the first |
647 | * and the last descriptor for the RX packet. Each RX packet is currently | |
c5aff182 TP |
648 | * received through a single RX descriptor, so not having each RX |
649 | * descriptor with its first and last bits set is an error | |
650 | */ | |
5428213c | 651 | static int mvneta_rxq_desc_is_first_last(u32 status) |
c5aff182 | 652 | { |
5428213c | 653 | return (status & MVNETA_RXD_FIRST_LAST_DESC) == |
c5aff182 TP |
654 | MVNETA_RXD_FIRST_LAST_DESC; |
655 | } | |
656 | ||
657 | /* Add number of descriptors ready to receive new packets */ | |
658 | static void mvneta_rxq_non_occup_desc_add(struct mvneta_port *pp, | |
659 | struct mvneta_rx_queue *rxq, | |
660 | int ndescs) | |
661 | { | |
662 | /* Only MVNETA_RXQ_ADD_NON_OCCUPIED_MAX (255) descriptors can | |
6a20c175 TP |
663 | * be added at once |
664 | */ | |
c5aff182 TP |
665 | while (ndescs > MVNETA_RXQ_ADD_NON_OCCUPIED_MAX) { |
666 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
667 | (MVNETA_RXQ_ADD_NON_OCCUPIED_MAX << | |
668 | MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
669 | ndescs -= MVNETA_RXQ_ADD_NON_OCCUPIED_MAX; | |
670 | } | |
671 | ||
672 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), | |
673 | (ndescs << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT)); | |
674 | } | |
675 | ||
676 | /* Get number of RX descriptors occupied by received packets */ | |
677 | static int mvneta_rxq_busy_desc_num_get(struct mvneta_port *pp, | |
678 | struct mvneta_rx_queue *rxq) | |
679 | { | |
680 | u32 val; | |
681 | ||
682 | val = mvreg_read(pp, MVNETA_RXQ_STATUS_REG(rxq->id)); | |
683 | return val & MVNETA_RXQ_OCCUPIED_ALL_MASK; | |
684 | } | |
685 | ||
6a20c175 | 686 | /* Update num of rx desc called upon return from rx path or |
c5aff182 TP |
687 | * from mvneta_rxq_drop_pkts(). |
688 | */ | |
689 | static void mvneta_rxq_desc_num_update(struct mvneta_port *pp, | |
690 | struct mvneta_rx_queue *rxq, | |
691 | int rx_done, int rx_filled) | |
692 | { | |
693 | u32 val; | |
694 | ||
695 | if ((rx_done <= 0xff) && (rx_filled <= 0xff)) { | |
696 | val = rx_done | | |
697 | (rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT); | |
698 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
699 | return; | |
700 | } | |
701 | ||
702 | /* Only 255 descriptors can be added at once */ | |
703 | while ((rx_done > 0) || (rx_filled > 0)) { | |
704 | if (rx_done <= 0xff) { | |
705 | val = rx_done; | |
706 | rx_done = 0; | |
707 | } else { | |
708 | val = 0xff; | |
709 | rx_done -= 0xff; | |
710 | } | |
711 | if (rx_filled <= 0xff) { | |
712 | val |= rx_filled << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
713 | rx_filled = 0; | |
714 | } else { | |
715 | val |= 0xff << MVNETA_RXQ_ADD_NON_OCCUPIED_SHIFT; | |
716 | rx_filled -= 0xff; | |
717 | } | |
718 | mvreg_write(pp, MVNETA_RXQ_STATUS_UPDATE_REG(rxq->id), val); | |
719 | } | |
720 | } | |
721 | ||
722 | /* Get pointer to next RX descriptor to be processed by SW */ | |
723 | static struct mvneta_rx_desc * | |
724 | mvneta_rxq_next_desc_get(struct mvneta_rx_queue *rxq) | |
725 | { | |
726 | int rx_desc = rxq->next_desc_to_proc; | |
727 | ||
728 | rxq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(rxq, rx_desc); | |
34e4179d | 729 | prefetch(rxq->descs + rxq->next_desc_to_proc); |
c5aff182 TP |
730 | return rxq->descs + rx_desc; |
731 | } | |
732 | ||
733 | /* Change maximum receive size of the port. */ | |
734 | static void mvneta_max_rx_size_set(struct mvneta_port *pp, int max_rx_size) | |
735 | { | |
736 | u32 val; | |
737 | ||
738 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
739 | val &= ~MVNETA_GMAC_MAX_RX_SIZE_MASK; | |
740 | val |= ((max_rx_size - MVNETA_MH_SIZE) / 2) << | |
741 | MVNETA_GMAC_MAX_RX_SIZE_SHIFT; | |
742 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
743 | } | |
744 | ||
745 | ||
746 | /* Set rx queue offset */ | |
747 | static void mvneta_rxq_offset_set(struct mvneta_port *pp, | |
748 | struct mvneta_rx_queue *rxq, | |
749 | int offset) | |
750 | { | |
751 | u32 val; | |
752 | ||
753 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
754 | val &= ~MVNETA_RXQ_PKT_OFFSET_ALL_MASK; | |
755 | ||
756 | /* Offset is in */ | |
757 | val |= MVNETA_RXQ_PKT_OFFSET_MASK(offset >> 3); | |
758 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
759 | } | |
760 | ||
761 | ||
762 | /* Tx descriptors helper methods */ | |
763 | ||
764 | /* Update HW with number of TX descriptors to be sent */ | |
765 | static void mvneta_txq_pend_desc_add(struct mvneta_port *pp, | |
766 | struct mvneta_tx_queue *txq, | |
767 | int pend_desc) | |
768 | { | |
769 | u32 val; | |
770 | ||
771 | /* Only 255 descriptors can be added at once ; Assume caller | |
6a20c175 TP |
772 | * process TX desriptors in quanta less than 256 |
773 | */ | |
c5aff182 TP |
774 | val = pend_desc; |
775 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
776 | } | |
777 | ||
778 | /* Get pointer to next TX descriptor to be processed (send) by HW */ | |
779 | static struct mvneta_tx_desc * | |
780 | mvneta_txq_next_desc_get(struct mvneta_tx_queue *txq) | |
781 | { | |
782 | int tx_desc = txq->next_desc_to_proc; | |
783 | ||
784 | txq->next_desc_to_proc = MVNETA_QUEUE_NEXT_DESC(txq, tx_desc); | |
785 | return txq->descs + tx_desc; | |
786 | } | |
787 | ||
788 | /* Release the last allocated TX descriptor. Useful to handle DMA | |
6a20c175 TP |
789 | * mapping failures in the TX path. |
790 | */ | |
c5aff182 TP |
791 | static void mvneta_txq_desc_put(struct mvneta_tx_queue *txq) |
792 | { | |
793 | if (txq->next_desc_to_proc == 0) | |
794 | txq->next_desc_to_proc = txq->last_desc - 1; | |
795 | else | |
796 | txq->next_desc_to_proc--; | |
797 | } | |
798 | ||
799 | /* Set rxq buf size */ | |
800 | static void mvneta_rxq_buf_size_set(struct mvneta_port *pp, | |
801 | struct mvneta_rx_queue *rxq, | |
802 | int buf_size) | |
803 | { | |
804 | u32 val; | |
805 | ||
806 | val = mvreg_read(pp, MVNETA_RXQ_SIZE_REG(rxq->id)); | |
807 | ||
808 | val &= ~MVNETA_RXQ_BUF_SIZE_MASK; | |
809 | val |= ((buf_size >> 3) << MVNETA_RXQ_BUF_SIZE_SHIFT); | |
810 | ||
811 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), val); | |
812 | } | |
813 | ||
814 | /* Disable buffer management (BM) */ | |
815 | static void mvneta_rxq_bm_disable(struct mvneta_port *pp, | |
816 | struct mvneta_rx_queue *rxq) | |
817 | { | |
818 | u32 val; | |
819 | ||
820 | val = mvreg_read(pp, MVNETA_RXQ_CONFIG_REG(rxq->id)); | |
821 | val &= ~MVNETA_RXQ_HW_BUF_ALLOC; | |
822 | mvreg_write(pp, MVNETA_RXQ_CONFIG_REG(rxq->id), val); | |
823 | } | |
824 | ||
c5aff182 TP |
825 | /* Start the Ethernet port RX and TX activity */ |
826 | static void mvneta_port_up(struct mvneta_port *pp) | |
827 | { | |
828 | int queue; | |
829 | u32 q_map; | |
830 | ||
831 | /* Enable all initialized TXs. */ | |
c5aff182 TP |
832 | q_map = 0; |
833 | for (queue = 0; queue < txq_number; queue++) { | |
834 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
835 | if (txq->descs != NULL) | |
836 | q_map |= (1 << queue); | |
837 | } | |
838 | mvreg_write(pp, MVNETA_TXQ_CMD, q_map); | |
839 | ||
840 | /* Enable all initialized RXQs. */ | |
2dcf75e2 GC |
841 | for (queue = 0; queue < rxq_number; queue++) { |
842 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
843 | ||
844 | if (rxq->descs != NULL) | |
845 | q_map |= (1 << queue); | |
846 | } | |
847 | mvreg_write(pp, MVNETA_RXQ_CMD, q_map); | |
c5aff182 TP |
848 | } |
849 | ||
850 | /* Stop the Ethernet port activity */ | |
851 | static void mvneta_port_down(struct mvneta_port *pp) | |
852 | { | |
853 | u32 val; | |
854 | int count; | |
855 | ||
856 | /* Stop Rx port activity. Check port Rx activity. */ | |
857 | val = mvreg_read(pp, MVNETA_RXQ_CMD) & MVNETA_RXQ_ENABLE_MASK; | |
858 | ||
859 | /* Issue stop command for active channels only */ | |
860 | if (val != 0) | |
861 | mvreg_write(pp, MVNETA_RXQ_CMD, | |
862 | val << MVNETA_RXQ_DISABLE_SHIFT); | |
863 | ||
864 | /* Wait for all Rx activity to terminate. */ | |
865 | count = 0; | |
866 | do { | |
867 | if (count++ >= MVNETA_RX_DISABLE_TIMEOUT_MSEC) { | |
868 | netdev_warn(pp->dev, | |
869 | "TIMEOUT for RX stopped ! rx_queue_cmd: 0x08%x\n", | |
870 | val); | |
871 | break; | |
872 | } | |
873 | mdelay(1); | |
874 | ||
875 | val = mvreg_read(pp, MVNETA_RXQ_CMD); | |
876 | } while (val & 0xff); | |
877 | ||
878 | /* Stop Tx port activity. Check port Tx activity. Issue stop | |
6a20c175 TP |
879 | * command for active channels only |
880 | */ | |
c5aff182 TP |
881 | val = (mvreg_read(pp, MVNETA_TXQ_CMD)) & MVNETA_TXQ_ENABLE_MASK; |
882 | ||
883 | if (val != 0) | |
884 | mvreg_write(pp, MVNETA_TXQ_CMD, | |
885 | (val << MVNETA_TXQ_DISABLE_SHIFT)); | |
886 | ||
887 | /* Wait for all Tx activity to terminate. */ | |
888 | count = 0; | |
889 | do { | |
890 | if (count++ >= MVNETA_TX_DISABLE_TIMEOUT_MSEC) { | |
891 | netdev_warn(pp->dev, | |
892 | "TIMEOUT for TX stopped status=0x%08x\n", | |
893 | val); | |
894 | break; | |
895 | } | |
896 | mdelay(1); | |
897 | ||
898 | /* Check TX Command reg that all Txqs are stopped */ | |
899 | val = mvreg_read(pp, MVNETA_TXQ_CMD); | |
900 | ||
901 | } while (val & 0xff); | |
902 | ||
903 | /* Double check to verify that TX FIFO is empty */ | |
904 | count = 0; | |
905 | do { | |
906 | if (count++ >= MVNETA_TX_FIFO_EMPTY_TIMEOUT) { | |
907 | netdev_warn(pp->dev, | |
908 | "TX FIFO empty timeout status=0x08%x\n", | |
909 | val); | |
910 | break; | |
911 | } | |
912 | mdelay(1); | |
913 | ||
914 | val = mvreg_read(pp, MVNETA_PORT_STATUS); | |
915 | } while (!(val & MVNETA_TX_FIFO_EMPTY) && | |
916 | (val & MVNETA_TX_IN_PRGRS)); | |
917 | ||
918 | udelay(200); | |
919 | } | |
920 | ||
921 | /* Enable the port by setting the port enable bit of the MAC control register */ | |
922 | static void mvneta_port_enable(struct mvneta_port *pp) | |
923 | { | |
924 | u32 val; | |
925 | ||
926 | /* Enable port */ | |
927 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
928 | val |= MVNETA_GMAC0_PORT_ENABLE; | |
929 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
930 | } | |
931 | ||
932 | /* Disable the port and wait for about 200 usec before retuning */ | |
933 | static void mvneta_port_disable(struct mvneta_port *pp) | |
934 | { | |
935 | u32 val; | |
936 | ||
937 | /* Reset the Enable bit in the Serial Control Register */ | |
938 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_0); | |
939 | val &= ~MVNETA_GMAC0_PORT_ENABLE; | |
940 | mvreg_write(pp, MVNETA_GMAC_CTRL_0, val); | |
941 | ||
942 | udelay(200); | |
943 | } | |
944 | ||
945 | /* Multicast tables methods */ | |
946 | ||
947 | /* Set all entries in Unicast MAC Table; queue==-1 means reject all */ | |
948 | static void mvneta_set_ucast_table(struct mvneta_port *pp, int queue) | |
949 | { | |
950 | int offset; | |
951 | u32 val; | |
952 | ||
953 | if (queue == -1) { | |
954 | val = 0; | |
955 | } else { | |
956 | val = 0x1 | (queue << 1); | |
957 | val |= (val << 24) | (val << 16) | (val << 8); | |
958 | } | |
959 | ||
960 | for (offset = 0; offset <= 0xc; offset += 4) | |
961 | mvreg_write(pp, MVNETA_DA_FILT_UCAST_BASE + offset, val); | |
962 | } | |
963 | ||
964 | /* Set all entries in Special Multicast MAC Table; queue==-1 means reject all */ | |
965 | static void mvneta_set_special_mcast_table(struct mvneta_port *pp, int queue) | |
966 | { | |
967 | int offset; | |
968 | u32 val; | |
969 | ||
970 | if (queue == -1) { | |
971 | val = 0; | |
972 | } else { | |
973 | val = 0x1 | (queue << 1); | |
974 | val |= (val << 24) | (val << 16) | (val << 8); | |
975 | } | |
976 | ||
977 | for (offset = 0; offset <= 0xfc; offset += 4) | |
978 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + offset, val); | |
979 | ||
980 | } | |
981 | ||
982 | /* Set all entries in Other Multicast MAC Table. queue==-1 means reject all */ | |
983 | static void mvneta_set_other_mcast_table(struct mvneta_port *pp, int queue) | |
984 | { | |
985 | int offset; | |
986 | u32 val; | |
987 | ||
988 | if (queue == -1) { | |
989 | memset(pp->mcast_count, 0, sizeof(pp->mcast_count)); | |
990 | val = 0; | |
991 | } else { | |
992 | memset(pp->mcast_count, 1, sizeof(pp->mcast_count)); | |
993 | val = 0x1 | (queue << 1); | |
994 | val |= (val << 24) | (val << 16) | (val << 8); | |
995 | } | |
996 | ||
997 | for (offset = 0; offset <= 0xfc; offset += 4) | |
998 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + offset, val); | |
999 | } | |
1000 | ||
0c0744fc SS |
1001 | static void mvneta_set_autoneg(struct mvneta_port *pp, int enable) |
1002 | { | |
1003 | u32 val; | |
1004 | ||
1005 | if (enable) { | |
1006 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1007 | val &= ~(MVNETA_GMAC_FORCE_LINK_PASS | | |
1008 | MVNETA_GMAC_FORCE_LINK_DOWN | | |
1009 | MVNETA_GMAC_AN_FLOW_CTRL_EN); | |
1010 | val |= MVNETA_GMAC_INBAND_AN_ENABLE | | |
1011 | MVNETA_GMAC_AN_SPEED_EN | | |
1012 | MVNETA_GMAC_AN_DUPLEX_EN; | |
1013 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1014 | ||
1015 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1016 | val |= MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1017 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1018 | ||
1019 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1020 | val |= MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1021 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1022 | } else { | |
1023 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
1024 | val &= ~(MVNETA_GMAC_INBAND_AN_ENABLE | | |
1025 | MVNETA_GMAC_AN_SPEED_EN | | |
1026 | MVNETA_GMAC_AN_DUPLEX_EN); | |
1027 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
1028 | ||
1029 | val = mvreg_read(pp, MVNETA_GMAC_CLOCK_DIVIDER); | |
1030 | val &= ~MVNETA_GMAC_1MS_CLOCK_ENABLE; | |
1031 | mvreg_write(pp, MVNETA_GMAC_CLOCK_DIVIDER, val); | |
1032 | ||
1033 | val = mvreg_read(pp, MVNETA_GMAC_CTRL_2); | |
1034 | val &= ~MVNETA_GMAC2_INBAND_AN_ENABLE; | |
1035 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, val); | |
1036 | } | |
1037 | } | |
1038 | ||
c5aff182 TP |
1039 | /* This method sets defaults to the NETA port: |
1040 | * Clears interrupt Cause and Mask registers. | |
1041 | * Clears all MAC tables. | |
1042 | * Sets defaults to all registers. | |
1043 | * Resets RX and TX descriptor rings. | |
1044 | * Resets PHY. | |
1045 | * This method can be called after mvneta_port_down() to return the port | |
1046 | * settings to defaults. | |
1047 | */ | |
1048 | static void mvneta_defaults_set(struct mvneta_port *pp) | |
1049 | { | |
1050 | int cpu; | |
1051 | int queue; | |
1052 | u32 val; | |
2dcf75e2 | 1053 | int max_cpu = num_present_cpus(); |
c5aff182 TP |
1054 | |
1055 | /* Clear all Cause registers */ | |
1056 | mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0); | |
1057 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
1058 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
1059 | ||
1060 | /* Mask all interrupts */ | |
1061 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
1062 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
1063 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
1064 | mvreg_write(pp, MVNETA_INTR_ENABLE, 0); | |
1065 | ||
1066 | /* Enable MBUS Retry bit16 */ | |
1067 | mvreg_write(pp, MVNETA_MBUS_RETRY, 0x20); | |
1068 | ||
50bf8cb6 GC |
1069 | /* Set CPU queue access map. CPUs are assigned to the RX and |
1070 | * TX queues modulo their number. If there is only one TX | |
1071 | * queue then it is assigned to the CPU associated to the | |
1072 | * default RX queue. | |
6a20c175 | 1073 | */ |
2dcf75e2 GC |
1074 | for_each_present_cpu(cpu) { |
1075 | int rxq_map = 0, txq_map = 0; | |
50bf8cb6 | 1076 | int rxq, txq; |
2dcf75e2 GC |
1077 | |
1078 | for (rxq = 0; rxq < rxq_number; rxq++) | |
1079 | if ((rxq % max_cpu) == cpu) | |
1080 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
1081 | ||
50bf8cb6 GC |
1082 | for (txq = 0; txq < txq_number; txq++) |
1083 | if ((txq % max_cpu) == cpu) | |
1084 | txq_map |= MVNETA_CPU_TXQ_ACCESS(txq); | |
1085 | ||
1086 | /* With only one TX queue we configure a special case | |
1087 | * which will allow to get all the irq on a single | |
1088 | * CPU | |
1089 | */ | |
1090 | if (txq_number == 1) | |
1091 | txq_map = (cpu == pp->rxq_def) ? | |
1092 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2dcf75e2 GC |
1093 | |
1094 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); | |
1095 | } | |
c5aff182 TP |
1096 | |
1097 | /* Reset RX and TX DMAs */ | |
1098 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
1099 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
1100 | ||
1101 | /* Disable Legacy WRR, Disable EJP, Release from reset */ | |
1102 | mvreg_write(pp, MVNETA_TXQ_CMD_1, 0); | |
1103 | for (queue = 0; queue < txq_number; queue++) { | |
1104 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(queue), 0); | |
1105 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(queue), 0); | |
1106 | } | |
1107 | ||
1108 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
1109 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
1110 | ||
1111 | /* Set Port Acceleration Mode */ | |
1112 | val = MVNETA_ACC_MODE_EXT; | |
1113 | mvreg_write(pp, MVNETA_ACC_MODE, val); | |
1114 | ||
1115 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
90b74c01 | 1116 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); |
c5aff182 TP |
1117 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); |
1118 | ||
1119 | val = 0; | |
1120 | mvreg_write(pp, MVNETA_PORT_CONFIG_EXTEND, val); | |
1121 | mvreg_write(pp, MVNETA_RX_MIN_FRAME_SIZE, 64); | |
1122 | ||
1123 | /* Build PORT_SDMA_CONFIG_REG */ | |
1124 | val = 0; | |
1125 | ||
1126 | /* Default burst size */ | |
1127 | val |= MVNETA_TX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
1128 | val |= MVNETA_RX_BRST_SZ_MASK(MVNETA_SDMA_BRST_SIZE_16); | |
9ad8fef6 | 1129 | val |= MVNETA_RX_NO_DATA_SWAP | MVNETA_TX_NO_DATA_SWAP; |
c5aff182 | 1130 | |
9ad8fef6 TP |
1131 | #if defined(__BIG_ENDIAN) |
1132 | val |= MVNETA_DESC_SWAP; | |
1133 | #endif | |
c5aff182 TP |
1134 | |
1135 | /* Assign port SDMA configuration */ | |
1136 | mvreg_write(pp, MVNETA_SDMA_CONFIG, val); | |
1137 | ||
71408602 TP |
1138 | /* Disable PHY polling in hardware, since we're using the |
1139 | * kernel phylib to do this. | |
1140 | */ | |
1141 | val = mvreg_read(pp, MVNETA_UNIT_CONTROL); | |
1142 | val &= ~MVNETA_PHY_POLLING_ENABLE; | |
1143 | mvreg_write(pp, MVNETA_UNIT_CONTROL, val); | |
1144 | ||
0c0744fc | 1145 | mvneta_set_autoneg(pp, pp->use_inband_status); |
c5aff182 TP |
1146 | mvneta_set_ucast_table(pp, -1); |
1147 | mvneta_set_special_mcast_table(pp, -1); | |
1148 | mvneta_set_other_mcast_table(pp, -1); | |
1149 | ||
1150 | /* Set port interrupt enable register - default enable all */ | |
1151 | mvreg_write(pp, MVNETA_INTR_ENABLE, | |
1152 | (MVNETA_RXQ_INTR_ENABLE_ALL_MASK | |
1153 | | MVNETA_TXQ_INTR_ENABLE_ALL_MASK)); | |
e483911f AL |
1154 | |
1155 | mvneta_mib_counters_clear(pp); | |
c5aff182 TP |
1156 | } |
1157 | ||
1158 | /* Set max sizes for tx queues */ | |
1159 | static void mvneta_txq_max_tx_size_set(struct mvneta_port *pp, int max_tx_size) | |
1160 | ||
1161 | { | |
1162 | u32 val, size, mtu; | |
1163 | int queue; | |
1164 | ||
1165 | mtu = max_tx_size * 8; | |
1166 | if (mtu > MVNETA_TX_MTU_MAX) | |
1167 | mtu = MVNETA_TX_MTU_MAX; | |
1168 | ||
1169 | /* Set MTU */ | |
1170 | val = mvreg_read(pp, MVNETA_TX_MTU); | |
1171 | val &= ~MVNETA_TX_MTU_MAX; | |
1172 | val |= mtu; | |
1173 | mvreg_write(pp, MVNETA_TX_MTU, val); | |
1174 | ||
1175 | /* TX token size and all TXQs token size must be larger that MTU */ | |
1176 | val = mvreg_read(pp, MVNETA_TX_TOKEN_SIZE); | |
1177 | ||
1178 | size = val & MVNETA_TX_TOKEN_SIZE_MAX; | |
1179 | if (size < mtu) { | |
1180 | size = mtu; | |
1181 | val &= ~MVNETA_TX_TOKEN_SIZE_MAX; | |
1182 | val |= size; | |
1183 | mvreg_write(pp, MVNETA_TX_TOKEN_SIZE, val); | |
1184 | } | |
1185 | for (queue = 0; queue < txq_number; queue++) { | |
1186 | val = mvreg_read(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue)); | |
1187 | ||
1188 | size = val & MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1189 | if (size < mtu) { | |
1190 | size = mtu; | |
1191 | val &= ~MVNETA_TXQ_TOKEN_SIZE_MAX; | |
1192 | val |= size; | |
1193 | mvreg_write(pp, MVNETA_TXQ_TOKEN_SIZE_REG(queue), val); | |
1194 | } | |
1195 | } | |
1196 | } | |
1197 | ||
1198 | /* Set unicast address */ | |
1199 | static void mvneta_set_ucast_addr(struct mvneta_port *pp, u8 last_nibble, | |
1200 | int queue) | |
1201 | { | |
1202 | unsigned int unicast_reg; | |
1203 | unsigned int tbl_offset; | |
1204 | unsigned int reg_offset; | |
1205 | ||
1206 | /* Locate the Unicast table entry */ | |
1207 | last_nibble = (0xf & last_nibble); | |
1208 | ||
1209 | /* offset from unicast tbl base */ | |
1210 | tbl_offset = (last_nibble / 4) * 4; | |
1211 | ||
1212 | /* offset within the above reg */ | |
1213 | reg_offset = last_nibble % 4; | |
1214 | ||
1215 | unicast_reg = mvreg_read(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset)); | |
1216 | ||
1217 | if (queue == -1) { | |
1218 | /* Clear accepts frame bit at specified unicast DA tbl entry */ | |
1219 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1220 | } else { | |
1221 | unicast_reg &= ~(0xff << (8 * reg_offset)); | |
1222 | unicast_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
1223 | } | |
1224 | ||
1225 | mvreg_write(pp, (MVNETA_DA_FILT_UCAST_BASE + tbl_offset), unicast_reg); | |
1226 | } | |
1227 | ||
1228 | /* Set mac address */ | |
1229 | static void mvneta_mac_addr_set(struct mvneta_port *pp, unsigned char *addr, | |
1230 | int queue) | |
1231 | { | |
1232 | unsigned int mac_h; | |
1233 | unsigned int mac_l; | |
1234 | ||
1235 | if (queue != -1) { | |
1236 | mac_l = (addr[4] << 8) | (addr[5]); | |
1237 | mac_h = (addr[0] << 24) | (addr[1] << 16) | | |
1238 | (addr[2] << 8) | (addr[3] << 0); | |
1239 | ||
1240 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, mac_l); | |
1241 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, mac_h); | |
1242 | } | |
1243 | ||
1244 | /* Accept frames of this address */ | |
1245 | mvneta_set_ucast_addr(pp, addr[5], queue); | |
1246 | } | |
1247 | ||
6a20c175 TP |
1248 | /* Set the number of packets that will be received before RX interrupt |
1249 | * will be generated by HW. | |
c5aff182 TP |
1250 | */ |
1251 | static void mvneta_rx_pkts_coal_set(struct mvneta_port *pp, | |
1252 | struct mvneta_rx_queue *rxq, u32 value) | |
1253 | { | |
1254 | mvreg_write(pp, MVNETA_RXQ_THRESHOLD_REG(rxq->id), | |
1255 | value | MVNETA_RXQ_NON_OCCUPIED(0)); | |
1256 | rxq->pkts_coal = value; | |
1257 | } | |
1258 | ||
6a20c175 TP |
1259 | /* Set the time delay in usec before RX interrupt will be generated by |
1260 | * HW. | |
c5aff182 TP |
1261 | */ |
1262 | static void mvneta_rx_time_coal_set(struct mvneta_port *pp, | |
1263 | struct mvneta_rx_queue *rxq, u32 value) | |
1264 | { | |
189dd626 TP |
1265 | u32 val; |
1266 | unsigned long clk_rate; | |
1267 | ||
1268 | clk_rate = clk_get_rate(pp->clk); | |
1269 | val = (clk_rate / 1000000) * value; | |
c5aff182 TP |
1270 | |
1271 | mvreg_write(pp, MVNETA_RXQ_TIME_COAL_REG(rxq->id), val); | |
1272 | rxq->time_coal = value; | |
1273 | } | |
1274 | ||
1275 | /* Set threshold for TX_DONE pkts coalescing */ | |
1276 | static void mvneta_tx_done_pkts_coal_set(struct mvneta_port *pp, | |
1277 | struct mvneta_tx_queue *txq, u32 value) | |
1278 | { | |
1279 | u32 val; | |
1280 | ||
1281 | val = mvreg_read(pp, MVNETA_TXQ_SIZE_REG(txq->id)); | |
1282 | ||
1283 | val &= ~MVNETA_TXQ_SENT_THRESH_ALL_MASK; | |
1284 | val |= MVNETA_TXQ_SENT_THRESH_MASK(value); | |
1285 | ||
1286 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), val); | |
1287 | ||
1288 | txq->done_pkts_coal = value; | |
1289 | } | |
1290 | ||
c5aff182 TP |
1291 | /* Handle rx descriptor fill by setting buf_cookie and buf_phys_addr */ |
1292 | static void mvneta_rx_desc_fill(struct mvneta_rx_desc *rx_desc, | |
1293 | u32 phys_addr, u32 cookie) | |
1294 | { | |
1295 | rx_desc->buf_cookie = cookie; | |
1296 | rx_desc->buf_phys_addr = phys_addr; | |
1297 | } | |
1298 | ||
1299 | /* Decrement sent descriptors counter */ | |
1300 | static void mvneta_txq_sent_desc_dec(struct mvneta_port *pp, | |
1301 | struct mvneta_tx_queue *txq, | |
1302 | int sent_desc) | |
1303 | { | |
1304 | u32 val; | |
1305 | ||
1306 | /* Only 255 TX descriptors can be updated at once */ | |
1307 | while (sent_desc > 0xff) { | |
1308 | val = 0xff << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1309 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1310 | sent_desc = sent_desc - 0xff; | |
1311 | } | |
1312 | ||
1313 | val = sent_desc << MVNETA_TXQ_DEC_SENT_SHIFT; | |
1314 | mvreg_write(pp, MVNETA_TXQ_UPDATE_REG(txq->id), val); | |
1315 | } | |
1316 | ||
1317 | /* Get number of TX descriptors already sent by HW */ | |
1318 | static int mvneta_txq_sent_desc_num_get(struct mvneta_port *pp, | |
1319 | struct mvneta_tx_queue *txq) | |
1320 | { | |
1321 | u32 val; | |
1322 | int sent_desc; | |
1323 | ||
1324 | val = mvreg_read(pp, MVNETA_TXQ_STATUS_REG(txq->id)); | |
1325 | sent_desc = (val & MVNETA_TXQ_SENT_DESC_MASK) >> | |
1326 | MVNETA_TXQ_SENT_DESC_SHIFT; | |
1327 | ||
1328 | return sent_desc; | |
1329 | } | |
1330 | ||
6a20c175 | 1331 | /* Get number of sent descriptors and decrement counter. |
c5aff182 TP |
1332 | * The number of sent descriptors is returned. |
1333 | */ | |
1334 | static int mvneta_txq_sent_desc_proc(struct mvneta_port *pp, | |
1335 | struct mvneta_tx_queue *txq) | |
1336 | { | |
1337 | int sent_desc; | |
1338 | ||
1339 | /* Get number of sent descriptors */ | |
1340 | sent_desc = mvneta_txq_sent_desc_num_get(pp, txq); | |
1341 | ||
1342 | /* Decrement sent descriptors counter */ | |
1343 | if (sent_desc) | |
1344 | mvneta_txq_sent_desc_dec(pp, txq, sent_desc); | |
1345 | ||
1346 | return sent_desc; | |
1347 | } | |
1348 | ||
1349 | /* Set TXQ descriptors fields relevant for CSUM calculation */ | |
1350 | static u32 mvneta_txq_desc_csum(int l3_offs, int l3_proto, | |
1351 | int ip_hdr_len, int l4_proto) | |
1352 | { | |
1353 | u32 command; | |
1354 | ||
1355 | /* Fields: L3_offset, IP_hdrlen, L3_type, G_IPv4_chk, | |
6a20c175 TP |
1356 | * G_L4_chk, L4_type; required only for checksum |
1357 | * calculation | |
1358 | */ | |
c5aff182 TP |
1359 | command = l3_offs << MVNETA_TX_L3_OFF_SHIFT; |
1360 | command |= ip_hdr_len << MVNETA_TX_IP_HLEN_SHIFT; | |
1361 | ||
0a198587 | 1362 | if (l3_proto == htons(ETH_P_IP)) |
c5aff182 TP |
1363 | command |= MVNETA_TXD_IP_CSUM; |
1364 | else | |
1365 | command |= MVNETA_TX_L3_IP6; | |
1366 | ||
1367 | if (l4_proto == IPPROTO_TCP) | |
1368 | command |= MVNETA_TX_L4_CSUM_FULL; | |
1369 | else if (l4_proto == IPPROTO_UDP) | |
1370 | command |= MVNETA_TX_L4_UDP | MVNETA_TX_L4_CSUM_FULL; | |
1371 | else | |
1372 | command |= MVNETA_TX_L4_CSUM_NOT; | |
1373 | ||
1374 | return command; | |
1375 | } | |
1376 | ||
1377 | ||
1378 | /* Display more error info */ | |
1379 | static void mvneta_rx_error(struct mvneta_port *pp, | |
1380 | struct mvneta_rx_desc *rx_desc) | |
1381 | { | |
1382 | u32 status = rx_desc->status; | |
1383 | ||
5428213c | 1384 | if (!mvneta_rxq_desc_is_first_last(status)) { |
c5aff182 TP |
1385 | netdev_err(pp->dev, |
1386 | "bad rx status %08x (buffer oversize), size=%d\n", | |
5428213c | 1387 | status, rx_desc->data_size); |
c5aff182 TP |
1388 | return; |
1389 | } | |
1390 | ||
1391 | switch (status & MVNETA_RXD_ERR_CODE_MASK) { | |
1392 | case MVNETA_RXD_ERR_CRC: | |
1393 | netdev_err(pp->dev, "bad rx status %08x (crc error), size=%d\n", | |
1394 | status, rx_desc->data_size); | |
1395 | break; | |
1396 | case MVNETA_RXD_ERR_OVERRUN: | |
1397 | netdev_err(pp->dev, "bad rx status %08x (overrun error), size=%d\n", | |
1398 | status, rx_desc->data_size); | |
1399 | break; | |
1400 | case MVNETA_RXD_ERR_LEN: | |
1401 | netdev_err(pp->dev, "bad rx status %08x (max frame length error), size=%d\n", | |
1402 | status, rx_desc->data_size); | |
1403 | break; | |
1404 | case MVNETA_RXD_ERR_RESOURCE: | |
1405 | netdev_err(pp->dev, "bad rx status %08x (resource error), size=%d\n", | |
1406 | status, rx_desc->data_size); | |
1407 | break; | |
1408 | } | |
1409 | } | |
1410 | ||
5428213c | 1411 | /* Handle RX checksum offload based on the descriptor's status */ |
1412 | static void mvneta_rx_csum(struct mvneta_port *pp, u32 status, | |
c5aff182 TP |
1413 | struct sk_buff *skb) |
1414 | { | |
5428213c | 1415 | if ((status & MVNETA_RXD_L3_IP4) && |
1416 | (status & MVNETA_RXD_L4_CSUM_OK)) { | |
c5aff182 TP |
1417 | skb->csum = 0; |
1418 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
1419 | return; | |
1420 | } | |
1421 | ||
1422 | skb->ip_summed = CHECKSUM_NONE; | |
1423 | } | |
1424 | ||
6c498974 | 1425 | /* Return tx queue pointer (find last set bit) according to <cause> returned |
1426 | * form tx_done reg. <cause> must not be null. The return value is always a | |
1427 | * valid queue for matching the first one found in <cause>. | |
1428 | */ | |
c5aff182 TP |
1429 | static struct mvneta_tx_queue *mvneta_tx_done_policy(struct mvneta_port *pp, |
1430 | u32 cause) | |
1431 | { | |
1432 | int queue = fls(cause) - 1; | |
1433 | ||
6c498974 | 1434 | return &pp->txqs[queue]; |
c5aff182 TP |
1435 | } |
1436 | ||
1437 | /* Free tx queue skbuffs */ | |
1438 | static void mvneta_txq_bufs_free(struct mvneta_port *pp, | |
1439 | struct mvneta_tx_queue *txq, int num) | |
1440 | { | |
1441 | int i; | |
1442 | ||
1443 | for (i = 0; i < num; i++) { | |
1444 | struct mvneta_tx_desc *tx_desc = txq->descs + | |
1445 | txq->txq_get_index; | |
1446 | struct sk_buff *skb = txq->tx_skb[txq->txq_get_index]; | |
1447 | ||
1448 | mvneta_txq_inc_get(txq); | |
1449 | ||
2e3173a3 EG |
1450 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
1451 | dma_unmap_single(pp->dev->dev.parent, | |
1452 | tx_desc->buf_phys_addr, | |
1453 | tx_desc->data_size, DMA_TO_DEVICE); | |
ba7e46ef EG |
1454 | if (!skb) |
1455 | continue; | |
c5aff182 TP |
1456 | dev_kfree_skb_any(skb); |
1457 | } | |
1458 | } | |
1459 | ||
1460 | /* Handle end of transmission */ | |
cd713199 | 1461 | static void mvneta_txq_done(struct mvneta_port *pp, |
c5aff182 TP |
1462 | struct mvneta_tx_queue *txq) |
1463 | { | |
1464 | struct netdev_queue *nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1465 | int tx_done; | |
1466 | ||
1467 | tx_done = mvneta_txq_sent_desc_proc(pp, txq); | |
cd713199 AE |
1468 | if (!tx_done) |
1469 | return; | |
1470 | ||
c5aff182 TP |
1471 | mvneta_txq_bufs_free(pp, txq, tx_done); |
1472 | ||
1473 | txq->count -= tx_done; | |
1474 | ||
1475 | if (netif_tx_queue_stopped(nq)) { | |
8eef5f97 | 1476 | if (txq->count <= txq->tx_wake_threshold) |
c5aff182 TP |
1477 | netif_tx_wake_queue(nq); |
1478 | } | |
c5aff182 TP |
1479 | } |
1480 | ||
8ec2cd48 | 1481 | static void *mvneta_frag_alloc(const struct mvneta_port *pp) |
1482 | { | |
1483 | if (likely(pp->frag_size <= PAGE_SIZE)) | |
1484 | return netdev_alloc_frag(pp->frag_size); | |
1485 | else | |
1486 | return kmalloc(pp->frag_size, GFP_ATOMIC); | |
1487 | } | |
1488 | ||
1489 | static void mvneta_frag_free(const struct mvneta_port *pp, void *data) | |
1490 | { | |
1491 | if (likely(pp->frag_size <= PAGE_SIZE)) | |
13dc0d2b | 1492 | skb_free_frag(data); |
8ec2cd48 | 1493 | else |
1494 | kfree(data); | |
1495 | } | |
1496 | ||
c5aff182 TP |
1497 | /* Refill processing */ |
1498 | static int mvneta_rx_refill(struct mvneta_port *pp, | |
1499 | struct mvneta_rx_desc *rx_desc) | |
1500 | ||
1501 | { | |
1502 | dma_addr_t phys_addr; | |
8ec2cd48 | 1503 | void *data; |
c5aff182 | 1504 | |
8ec2cd48 | 1505 | data = mvneta_frag_alloc(pp); |
1506 | if (!data) | |
c5aff182 TP |
1507 | return -ENOMEM; |
1508 | ||
8ec2cd48 | 1509 | phys_addr = dma_map_single(pp->dev->dev.parent, data, |
c5aff182 TP |
1510 | MVNETA_RX_BUF_SIZE(pp->pkt_size), |
1511 | DMA_FROM_DEVICE); | |
1512 | if (unlikely(dma_mapping_error(pp->dev->dev.parent, phys_addr))) { | |
8ec2cd48 | 1513 | mvneta_frag_free(pp, data); |
c5aff182 TP |
1514 | return -ENOMEM; |
1515 | } | |
1516 | ||
8ec2cd48 | 1517 | mvneta_rx_desc_fill(rx_desc, phys_addr, (u32)data); |
c5aff182 TP |
1518 | return 0; |
1519 | } | |
1520 | ||
1521 | /* Handle tx checksum */ | |
1522 | static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, struct sk_buff *skb) | |
1523 | { | |
1524 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1525 | int ip_hdr_len = 0; | |
817dbfa5 | 1526 | __be16 l3_proto = vlan_get_protocol(skb); |
c5aff182 TP |
1527 | u8 l4_proto; |
1528 | ||
817dbfa5 | 1529 | if (l3_proto == htons(ETH_P_IP)) { |
c5aff182 TP |
1530 | struct iphdr *ip4h = ip_hdr(skb); |
1531 | ||
1532 | /* Calculate IPv4 checksum and L4 checksum */ | |
1533 | ip_hdr_len = ip4h->ihl; | |
1534 | l4_proto = ip4h->protocol; | |
817dbfa5 | 1535 | } else if (l3_proto == htons(ETH_P_IPV6)) { |
c5aff182 TP |
1536 | struct ipv6hdr *ip6h = ipv6_hdr(skb); |
1537 | ||
1538 | /* Read l4_protocol from one of IPv6 extra headers */ | |
1539 | if (skb_network_header_len(skb) > 0) | |
1540 | ip_hdr_len = (skb_network_header_len(skb) >> 2); | |
1541 | l4_proto = ip6h->nexthdr; | |
1542 | } else | |
1543 | return MVNETA_TX_L4_CSUM_NOT; | |
1544 | ||
1545 | return mvneta_txq_desc_csum(skb_network_offset(skb), | |
817dbfa5 | 1546 | l3_proto, ip_hdr_len, l4_proto); |
c5aff182 TP |
1547 | } |
1548 | ||
1549 | return MVNETA_TX_L4_CSUM_NOT; | |
1550 | } | |
1551 | ||
c5aff182 TP |
1552 | /* Drop packets received by the RXQ and free buffers */ |
1553 | static void mvneta_rxq_drop_pkts(struct mvneta_port *pp, | |
1554 | struct mvneta_rx_queue *rxq) | |
1555 | { | |
1556 | int rx_done, i; | |
1557 | ||
1558 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1559 | for (i = 0; i < rxq->size; i++) { | |
1560 | struct mvneta_rx_desc *rx_desc = rxq->descs + i; | |
8ec2cd48 | 1561 | void *data = (void *)rx_desc->buf_cookie; |
c5aff182 | 1562 | |
c5aff182 | 1563 | dma_unmap_single(pp->dev->dev.parent, rx_desc->buf_phys_addr, |
a328f3a0 | 1564 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
8c94ddbc | 1565 | mvneta_frag_free(pp, data); |
c5aff182 TP |
1566 | } |
1567 | ||
1568 | if (rx_done) | |
1569 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); | |
1570 | } | |
1571 | ||
1572 | /* Main rx processing */ | |
1573 | static int mvneta_rx(struct mvneta_port *pp, int rx_todo, | |
1574 | struct mvneta_rx_queue *rxq) | |
1575 | { | |
12bb03b4 | 1576 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 | 1577 | struct net_device *dev = pp->dev; |
a84e3289 | 1578 | int rx_done; |
dc4277dd | 1579 | u32 rcvd_pkts = 0; |
1580 | u32 rcvd_bytes = 0; | |
c5aff182 TP |
1581 | |
1582 | /* Get number of received packets */ | |
1583 | rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq); | |
1584 | ||
1585 | if (rx_todo > rx_done) | |
1586 | rx_todo = rx_done; | |
1587 | ||
1588 | rx_done = 0; | |
c5aff182 TP |
1589 | |
1590 | /* Fairness NAPI loop */ | |
1591 | while (rx_done < rx_todo) { | |
1592 | struct mvneta_rx_desc *rx_desc = mvneta_rxq_next_desc_get(rxq); | |
1593 | struct sk_buff *skb; | |
8ec2cd48 | 1594 | unsigned char *data; |
daf158d0 | 1595 | dma_addr_t phys_addr; |
c5aff182 TP |
1596 | u32 rx_status; |
1597 | int rx_bytes, err; | |
1598 | ||
c5aff182 | 1599 | rx_done++; |
c5aff182 | 1600 | rx_status = rx_desc->status; |
f19fadfc | 1601 | rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + MVNETA_MH_SIZE); |
8ec2cd48 | 1602 | data = (unsigned char *)rx_desc->buf_cookie; |
daf158d0 | 1603 | phys_addr = rx_desc->buf_phys_addr; |
c5aff182 | 1604 | |
5428213c | 1605 | if (!mvneta_rxq_desc_is_first_last(rx_status) || |
f19fadfc | 1606 | (rx_status & MVNETA_RXD_ERR_SUMMARY)) { |
1607 | err_drop_frame: | |
c5aff182 TP |
1608 | dev->stats.rx_errors++; |
1609 | mvneta_rx_error(pp, rx_desc); | |
8ec2cd48 | 1610 | /* leave the descriptor untouched */ |
c5aff182 TP |
1611 | continue; |
1612 | } | |
1613 | ||
f19fadfc | 1614 | if (rx_bytes <= rx_copybreak) { |
1615 | /* better copy a small frame and not unmap the DMA region */ | |
1616 | skb = netdev_alloc_skb_ip_align(dev, rx_bytes); | |
1617 | if (unlikely(!skb)) | |
1618 | goto err_drop_frame; | |
1619 | ||
1620 | dma_sync_single_range_for_cpu(dev->dev.parent, | |
1621 | rx_desc->buf_phys_addr, | |
1622 | MVNETA_MH_SIZE + NET_SKB_PAD, | |
1623 | rx_bytes, | |
1624 | DMA_FROM_DEVICE); | |
1625 | memcpy(skb_put(skb, rx_bytes), | |
1626 | data + MVNETA_MH_SIZE + NET_SKB_PAD, | |
1627 | rx_bytes); | |
1628 | ||
1629 | skb->protocol = eth_type_trans(skb, dev); | |
1630 | mvneta_rx_csum(pp, rx_status, skb); | |
12bb03b4 | 1631 | napi_gro_receive(&port->napi, skb); |
f19fadfc | 1632 | |
1633 | rcvd_pkts++; | |
1634 | rcvd_bytes += rx_bytes; | |
1635 | ||
1636 | /* leave the descriptor and buffer untouched */ | |
1637 | continue; | |
1638 | } | |
1639 | ||
a84e3289 SG |
1640 | /* Refill processing */ |
1641 | err = mvneta_rx_refill(pp, rx_desc); | |
1642 | if (err) { | |
1643 | netdev_err(dev, "Linux processing - Can't refill\n"); | |
1644 | rxq->missed++; | |
1645 | goto err_drop_frame; | |
1646 | } | |
1647 | ||
f19fadfc | 1648 | skb = build_skb(data, pp->frag_size > PAGE_SIZE ? 0 : pp->frag_size); |
f19fadfc | 1649 | |
26c17a17 MW |
1650 | /* After refill old buffer has to be unmapped regardless |
1651 | * the skb is successfully built or not. | |
1652 | */ | |
daf158d0 | 1653 | dma_unmap_single(dev->dev.parent, phys_addr, |
a328f3a0 | 1654 | MVNETA_RX_BUF_SIZE(pp->pkt_size), DMA_FROM_DEVICE); |
c5aff182 | 1655 | |
26c17a17 MW |
1656 | if (!skb) |
1657 | goto err_drop_frame; | |
1658 | ||
dc4277dd | 1659 | rcvd_pkts++; |
1660 | rcvd_bytes += rx_bytes; | |
c5aff182 TP |
1661 | |
1662 | /* Linux processing */ | |
8ec2cd48 | 1663 | skb_reserve(skb, MVNETA_MH_SIZE + NET_SKB_PAD); |
c5aff182 TP |
1664 | skb_put(skb, rx_bytes); |
1665 | ||
1666 | skb->protocol = eth_type_trans(skb, dev); | |
1667 | ||
5428213c | 1668 | mvneta_rx_csum(pp, rx_status, skb); |
c5aff182 | 1669 | |
12bb03b4 | 1670 | napi_gro_receive(&port->napi, skb); |
c5aff182 TP |
1671 | } |
1672 | ||
dc4277dd | 1673 | if (rcvd_pkts) { |
74c41b04 | 1674 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
1675 | ||
1676 | u64_stats_update_begin(&stats->syncp); | |
1677 | stats->rx_packets += rcvd_pkts; | |
1678 | stats->rx_bytes += rcvd_bytes; | |
1679 | u64_stats_update_end(&stats->syncp); | |
dc4277dd | 1680 | } |
1681 | ||
c5aff182 | 1682 | /* Update rxq management counters */ |
a84e3289 | 1683 | mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done); |
c5aff182 TP |
1684 | |
1685 | return rx_done; | |
1686 | } | |
1687 | ||
2adb719d EG |
1688 | static inline void |
1689 | mvneta_tso_put_hdr(struct sk_buff *skb, | |
1690 | struct mvneta_port *pp, struct mvneta_tx_queue *txq) | |
1691 | { | |
1692 | struct mvneta_tx_desc *tx_desc; | |
1693 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1694 | ||
1695 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1696 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1697 | tx_desc->data_size = hdr_len; | |
1698 | tx_desc->command = mvneta_skb_tx_csum(pp, skb); | |
1699 | tx_desc->command |= MVNETA_TXD_F_DESC; | |
1700 | tx_desc->buf_phys_addr = txq->tso_hdrs_phys + | |
1701 | txq->txq_put_index * TSO_HEADER_SIZE; | |
1702 | mvneta_txq_inc_put(txq); | |
1703 | } | |
1704 | ||
1705 | static inline int | |
1706 | mvneta_tso_put_data(struct net_device *dev, struct mvneta_tx_queue *txq, | |
1707 | struct sk_buff *skb, char *data, int size, | |
1708 | bool last_tcp, bool is_last) | |
1709 | { | |
1710 | struct mvneta_tx_desc *tx_desc; | |
1711 | ||
1712 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1713 | tx_desc->data_size = size; | |
1714 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, data, | |
1715 | size, DMA_TO_DEVICE); | |
1716 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
1717 | tx_desc->buf_phys_addr))) { | |
1718 | mvneta_txq_desc_put(txq); | |
1719 | return -ENOMEM; | |
1720 | } | |
1721 | ||
1722 | tx_desc->command = 0; | |
1723 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1724 | ||
1725 | if (last_tcp) { | |
1726 | /* last descriptor in the TCP packet */ | |
1727 | tx_desc->command = MVNETA_TXD_L_DESC; | |
1728 | ||
1729 | /* last descriptor in SKB */ | |
1730 | if (is_last) | |
1731 | txq->tx_skb[txq->txq_put_index] = skb; | |
1732 | } | |
1733 | mvneta_txq_inc_put(txq); | |
1734 | return 0; | |
1735 | } | |
1736 | ||
1737 | static int mvneta_tx_tso(struct sk_buff *skb, struct net_device *dev, | |
1738 | struct mvneta_tx_queue *txq) | |
1739 | { | |
1740 | int total_len, data_left; | |
1741 | int desc_count = 0; | |
1742 | struct mvneta_port *pp = netdev_priv(dev); | |
1743 | struct tso_t tso; | |
1744 | int hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
1745 | int i; | |
1746 | ||
1747 | /* Count needed descriptors */ | |
1748 | if ((txq->count + tso_count_descs(skb)) >= txq->size) | |
1749 | return 0; | |
1750 | ||
1751 | if (skb_headlen(skb) < (skb_transport_offset(skb) + tcp_hdrlen(skb))) { | |
1752 | pr_info("*** Is this even possible???!?!?\n"); | |
1753 | return 0; | |
1754 | } | |
1755 | ||
1756 | /* Initialize the TSO handler, and prepare the first payload */ | |
1757 | tso_start(skb, &tso); | |
1758 | ||
1759 | total_len = skb->len - hdr_len; | |
1760 | while (total_len > 0) { | |
1761 | char *hdr; | |
1762 | ||
1763 | data_left = min_t(int, skb_shinfo(skb)->gso_size, total_len); | |
1764 | total_len -= data_left; | |
1765 | desc_count++; | |
1766 | ||
1767 | /* prepare packet headers: MAC + IP + TCP */ | |
1768 | hdr = txq->tso_hdrs + txq->txq_put_index * TSO_HEADER_SIZE; | |
1769 | tso_build_hdr(skb, hdr, &tso, data_left, total_len == 0); | |
1770 | ||
1771 | mvneta_tso_put_hdr(skb, pp, txq); | |
1772 | ||
1773 | while (data_left > 0) { | |
1774 | int size; | |
1775 | desc_count++; | |
1776 | ||
1777 | size = min_t(int, tso.size, data_left); | |
1778 | ||
1779 | if (mvneta_tso_put_data(dev, txq, skb, | |
1780 | tso.data, size, | |
1781 | size == data_left, | |
1782 | total_len == 0)) | |
1783 | goto err_release; | |
1784 | data_left -= size; | |
1785 | ||
1786 | tso_build_data(skb, &tso, size); | |
1787 | } | |
1788 | } | |
1789 | ||
1790 | return desc_count; | |
1791 | ||
1792 | err_release: | |
1793 | /* Release all used data descriptors; header descriptors must not | |
1794 | * be DMA-unmapped. | |
1795 | */ | |
1796 | for (i = desc_count - 1; i >= 0; i--) { | |
1797 | struct mvneta_tx_desc *tx_desc = txq->descs + i; | |
2e3173a3 | 1798 | if (!IS_TSO_HEADER(txq, tx_desc->buf_phys_addr)) |
2adb719d EG |
1799 | dma_unmap_single(pp->dev->dev.parent, |
1800 | tx_desc->buf_phys_addr, | |
1801 | tx_desc->data_size, | |
1802 | DMA_TO_DEVICE); | |
1803 | mvneta_txq_desc_put(txq); | |
1804 | } | |
1805 | return 0; | |
1806 | } | |
1807 | ||
c5aff182 TP |
1808 | /* Handle tx fragmentation processing */ |
1809 | static int mvneta_tx_frag_process(struct mvneta_port *pp, struct sk_buff *skb, | |
1810 | struct mvneta_tx_queue *txq) | |
1811 | { | |
1812 | struct mvneta_tx_desc *tx_desc; | |
3d4ea02f | 1813 | int i, nr_frags = skb_shinfo(skb)->nr_frags; |
c5aff182 | 1814 | |
3d4ea02f | 1815 | for (i = 0; i < nr_frags; i++) { |
c5aff182 TP |
1816 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; |
1817 | void *addr = page_address(frag->page.p) + frag->page_offset; | |
1818 | ||
1819 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1820 | tx_desc->data_size = frag->size; | |
1821 | ||
1822 | tx_desc->buf_phys_addr = | |
1823 | dma_map_single(pp->dev->dev.parent, addr, | |
1824 | tx_desc->data_size, DMA_TO_DEVICE); | |
1825 | ||
1826 | if (dma_mapping_error(pp->dev->dev.parent, | |
1827 | tx_desc->buf_phys_addr)) { | |
1828 | mvneta_txq_desc_put(txq); | |
1829 | goto error; | |
1830 | } | |
1831 | ||
3d4ea02f | 1832 | if (i == nr_frags - 1) { |
c5aff182 TP |
1833 | /* Last descriptor */ |
1834 | tx_desc->command = MVNETA_TXD_L_DESC | MVNETA_TXD_Z_PAD; | |
c5aff182 | 1835 | txq->tx_skb[txq->txq_put_index] = skb; |
c5aff182 TP |
1836 | } else { |
1837 | /* Descriptor in the middle: Not First, Not Last */ | |
1838 | tx_desc->command = 0; | |
c5aff182 | 1839 | txq->tx_skb[txq->txq_put_index] = NULL; |
c5aff182 | 1840 | } |
3d4ea02f | 1841 | mvneta_txq_inc_put(txq); |
c5aff182 TP |
1842 | } |
1843 | ||
1844 | return 0; | |
1845 | ||
1846 | error: | |
1847 | /* Release all descriptors that were used to map fragments of | |
6a20c175 TP |
1848 | * this packet, as well as the corresponding DMA mappings |
1849 | */ | |
c5aff182 TP |
1850 | for (i = i - 1; i >= 0; i--) { |
1851 | tx_desc = txq->descs + i; | |
1852 | dma_unmap_single(pp->dev->dev.parent, | |
1853 | tx_desc->buf_phys_addr, | |
1854 | tx_desc->data_size, | |
1855 | DMA_TO_DEVICE); | |
1856 | mvneta_txq_desc_put(txq); | |
1857 | } | |
1858 | ||
1859 | return -ENOMEM; | |
1860 | } | |
1861 | ||
1862 | /* Main tx processing */ | |
1863 | static int mvneta_tx(struct sk_buff *skb, struct net_device *dev) | |
1864 | { | |
1865 | struct mvneta_port *pp = netdev_priv(dev); | |
ee40a116 WT |
1866 | u16 txq_id = skb_get_queue_mapping(skb); |
1867 | struct mvneta_tx_queue *txq = &pp->txqs[txq_id]; | |
c5aff182 | 1868 | struct mvneta_tx_desc *tx_desc; |
5f478b41 | 1869 | int len = skb->len; |
c5aff182 TP |
1870 | int frags = 0; |
1871 | u32 tx_cmd; | |
1872 | ||
1873 | if (!netif_running(dev)) | |
1874 | goto out; | |
1875 | ||
2adb719d EG |
1876 | if (skb_is_gso(skb)) { |
1877 | frags = mvneta_tx_tso(skb, dev, txq); | |
1878 | goto out; | |
1879 | } | |
1880 | ||
c5aff182 | 1881 | frags = skb_shinfo(skb)->nr_frags + 1; |
c5aff182 TP |
1882 | |
1883 | /* Get a descriptor for the first part of the packet */ | |
1884 | tx_desc = mvneta_txq_next_desc_get(txq); | |
1885 | ||
1886 | tx_cmd = mvneta_skb_tx_csum(pp, skb); | |
1887 | ||
1888 | tx_desc->data_size = skb_headlen(skb); | |
1889 | ||
1890 | tx_desc->buf_phys_addr = dma_map_single(dev->dev.parent, skb->data, | |
1891 | tx_desc->data_size, | |
1892 | DMA_TO_DEVICE); | |
1893 | if (unlikely(dma_mapping_error(dev->dev.parent, | |
1894 | tx_desc->buf_phys_addr))) { | |
1895 | mvneta_txq_desc_put(txq); | |
1896 | frags = 0; | |
1897 | goto out; | |
1898 | } | |
1899 | ||
1900 | if (frags == 1) { | |
1901 | /* First and Last descriptor */ | |
1902 | tx_cmd |= MVNETA_TXD_FLZ_DESC; | |
1903 | tx_desc->command = tx_cmd; | |
1904 | txq->tx_skb[txq->txq_put_index] = skb; | |
1905 | mvneta_txq_inc_put(txq); | |
1906 | } else { | |
1907 | /* First but not Last */ | |
1908 | tx_cmd |= MVNETA_TXD_F_DESC; | |
1909 | txq->tx_skb[txq->txq_put_index] = NULL; | |
1910 | mvneta_txq_inc_put(txq); | |
1911 | tx_desc->command = tx_cmd; | |
1912 | /* Continue with other skb fragments */ | |
1913 | if (mvneta_tx_frag_process(pp, skb, txq)) { | |
1914 | dma_unmap_single(dev->dev.parent, | |
1915 | tx_desc->buf_phys_addr, | |
1916 | tx_desc->data_size, | |
1917 | DMA_TO_DEVICE); | |
1918 | mvneta_txq_desc_put(txq); | |
1919 | frags = 0; | |
1920 | goto out; | |
1921 | } | |
1922 | } | |
1923 | ||
c5aff182 TP |
1924 | out: |
1925 | if (frags > 0) { | |
74c41b04 | 1926 | struct mvneta_pcpu_stats *stats = this_cpu_ptr(pp->stats); |
e19d2dda EG |
1927 | struct netdev_queue *nq = netdev_get_tx_queue(dev, txq_id); |
1928 | ||
1929 | txq->count += frags; | |
1930 | mvneta_txq_pend_desc_add(pp, txq, frags); | |
1931 | ||
8eef5f97 | 1932 | if (txq->count >= txq->tx_stop_threshold) |
e19d2dda | 1933 | netif_tx_stop_queue(nq); |
c5aff182 | 1934 | |
74c41b04 | 1935 | u64_stats_update_begin(&stats->syncp); |
1936 | stats->tx_packets++; | |
5f478b41 | 1937 | stats->tx_bytes += len; |
74c41b04 | 1938 | u64_stats_update_end(&stats->syncp); |
c5aff182 TP |
1939 | } else { |
1940 | dev->stats.tx_dropped++; | |
1941 | dev_kfree_skb_any(skb); | |
1942 | } | |
1943 | ||
c5aff182 TP |
1944 | return NETDEV_TX_OK; |
1945 | } | |
1946 | ||
1947 | ||
1948 | /* Free tx resources, when resetting a port */ | |
1949 | static void mvneta_txq_done_force(struct mvneta_port *pp, | |
1950 | struct mvneta_tx_queue *txq) | |
1951 | ||
1952 | { | |
1953 | int tx_done = txq->count; | |
1954 | ||
1955 | mvneta_txq_bufs_free(pp, txq, tx_done); | |
1956 | ||
1957 | /* reset txq */ | |
1958 | txq->count = 0; | |
1959 | txq->txq_put_index = 0; | |
1960 | txq->txq_get_index = 0; | |
1961 | } | |
1962 | ||
6c498974 | 1963 | /* Handle tx done - called in softirq context. The <cause_tx_done> argument |
1964 | * must be a valid cause according to MVNETA_TXQ_INTR_MASK_ALL. | |
1965 | */ | |
0713a86a | 1966 | static void mvneta_tx_done_gbe(struct mvneta_port *pp, u32 cause_tx_done) |
c5aff182 TP |
1967 | { |
1968 | struct mvneta_tx_queue *txq; | |
c5aff182 TP |
1969 | struct netdev_queue *nq; |
1970 | ||
6c498974 | 1971 | while (cause_tx_done) { |
c5aff182 | 1972 | txq = mvneta_tx_done_policy(pp, cause_tx_done); |
c5aff182 TP |
1973 | |
1974 | nq = netdev_get_tx_queue(pp->dev, txq->id); | |
1975 | __netif_tx_lock(nq, smp_processor_id()); | |
1976 | ||
0713a86a AE |
1977 | if (txq->count) |
1978 | mvneta_txq_done(pp, txq); | |
c5aff182 TP |
1979 | |
1980 | __netif_tx_unlock(nq); | |
1981 | cause_tx_done &= ~((1 << txq->id)); | |
1982 | } | |
c5aff182 TP |
1983 | } |
1984 | ||
6a20c175 | 1985 | /* Compute crc8 of the specified address, using a unique algorithm , |
c5aff182 TP |
1986 | * according to hw spec, different than generic crc8 algorithm |
1987 | */ | |
1988 | static int mvneta_addr_crc(unsigned char *addr) | |
1989 | { | |
1990 | int crc = 0; | |
1991 | int i; | |
1992 | ||
1993 | for (i = 0; i < ETH_ALEN; i++) { | |
1994 | int j; | |
1995 | ||
1996 | crc = (crc ^ addr[i]) << 8; | |
1997 | for (j = 7; j >= 0; j--) { | |
1998 | if (crc & (0x100 << j)) | |
1999 | crc ^= 0x107 << j; | |
2000 | } | |
2001 | } | |
2002 | ||
2003 | return crc; | |
2004 | } | |
2005 | ||
2006 | /* This method controls the net device special MAC multicast support. | |
2007 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
2008 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2009 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2010 | * Table entries in the DA-Filter table. This method set the Special | |
2011 | * Multicast Table appropriate entry. | |
2012 | */ | |
2013 | static void mvneta_set_special_mcast_addr(struct mvneta_port *pp, | |
2014 | unsigned char last_byte, | |
2015 | int queue) | |
2016 | { | |
2017 | unsigned int smc_table_reg; | |
2018 | unsigned int tbl_offset; | |
2019 | unsigned int reg_offset; | |
2020 | ||
2021 | /* Register offset from SMC table base */ | |
2022 | tbl_offset = (last_byte / 4); | |
2023 | /* Entry offset within the above reg */ | |
2024 | reg_offset = last_byte % 4; | |
2025 | ||
2026 | smc_table_reg = mvreg_read(pp, (MVNETA_DA_FILT_SPEC_MCAST | |
2027 | + tbl_offset * 4)); | |
2028 | ||
2029 | if (queue == -1) | |
2030 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2031 | else { | |
2032 | smc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2033 | smc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2034 | } | |
2035 | ||
2036 | mvreg_write(pp, MVNETA_DA_FILT_SPEC_MCAST + tbl_offset * 4, | |
2037 | smc_table_reg); | |
2038 | } | |
2039 | ||
2040 | /* This method controls the network device Other MAC multicast support. | |
2041 | * The Other Multicast Table is used for multicast of another type. | |
2042 | * A CRC-8 is used as an index to the Other Multicast Table entries | |
2043 | * in the DA-Filter table. | |
2044 | * The method gets the CRC-8 value from the calling routine and | |
2045 | * sets the Other Multicast Table appropriate entry according to the | |
2046 | * specified CRC-8 . | |
2047 | */ | |
2048 | static void mvneta_set_other_mcast_addr(struct mvneta_port *pp, | |
2049 | unsigned char crc8, | |
2050 | int queue) | |
2051 | { | |
2052 | unsigned int omc_table_reg; | |
2053 | unsigned int tbl_offset; | |
2054 | unsigned int reg_offset; | |
2055 | ||
2056 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
2057 | reg_offset = crc8 % 4; /* Entry offset within the above reg */ | |
2058 | ||
2059 | omc_table_reg = mvreg_read(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset); | |
2060 | ||
2061 | if (queue == -1) { | |
2062 | /* Clear accepts frame bit at specified Other DA table entry */ | |
2063 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2064 | } else { | |
2065 | omc_table_reg &= ~(0xff << (8 * reg_offset)); | |
2066 | omc_table_reg |= ((0x01 | (queue << 1)) << (8 * reg_offset)); | |
2067 | } | |
2068 | ||
2069 | mvreg_write(pp, MVNETA_DA_FILT_OTH_MCAST + tbl_offset, omc_table_reg); | |
2070 | } | |
2071 | ||
2072 | /* The network device supports multicast using two tables: | |
2073 | * 1) Special Multicast Table for MAC addresses of the form | |
2074 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0xFF). | |
2075 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
2076 | * Table entries in the DA-Filter table. | |
2077 | * 2) Other Multicast Table for multicast of another type. A CRC-8 value | |
2078 | * is used as an index to the Other Multicast Table entries in the | |
2079 | * DA-Filter table. | |
2080 | */ | |
2081 | static int mvneta_mcast_addr_set(struct mvneta_port *pp, unsigned char *p_addr, | |
2082 | int queue) | |
2083 | { | |
2084 | unsigned char crc_result = 0; | |
2085 | ||
2086 | if (memcmp(p_addr, "\x01\x00\x5e\x00\x00", 5) == 0) { | |
2087 | mvneta_set_special_mcast_addr(pp, p_addr[5], queue); | |
2088 | return 0; | |
2089 | } | |
2090 | ||
2091 | crc_result = mvneta_addr_crc(p_addr); | |
2092 | if (queue == -1) { | |
2093 | if (pp->mcast_count[crc_result] == 0) { | |
2094 | netdev_info(pp->dev, "No valid Mcast for crc8=0x%02x\n", | |
2095 | crc_result); | |
2096 | return -EINVAL; | |
2097 | } | |
2098 | ||
2099 | pp->mcast_count[crc_result]--; | |
2100 | if (pp->mcast_count[crc_result] != 0) { | |
2101 | netdev_info(pp->dev, | |
2102 | "After delete there are %d valid Mcast for crc8=0x%02x\n", | |
2103 | pp->mcast_count[crc_result], crc_result); | |
2104 | return -EINVAL; | |
2105 | } | |
2106 | } else | |
2107 | pp->mcast_count[crc_result]++; | |
2108 | ||
2109 | mvneta_set_other_mcast_addr(pp, crc_result, queue); | |
2110 | ||
2111 | return 0; | |
2112 | } | |
2113 | ||
2114 | /* Configure Fitering mode of Ethernet port */ | |
2115 | static void mvneta_rx_unicast_promisc_set(struct mvneta_port *pp, | |
2116 | int is_promisc) | |
2117 | { | |
2118 | u32 port_cfg_reg, val; | |
2119 | ||
2120 | port_cfg_reg = mvreg_read(pp, MVNETA_PORT_CONFIG); | |
2121 | ||
2122 | val = mvreg_read(pp, MVNETA_TYPE_PRIO); | |
2123 | ||
2124 | /* Set / Clear UPM bit in port configuration register */ | |
2125 | if (is_promisc) { | |
2126 | /* Accept all Unicast addresses */ | |
2127 | port_cfg_reg |= MVNETA_UNI_PROMISC_MODE; | |
2128 | val |= MVNETA_FORCE_UNI; | |
2129 | mvreg_write(pp, MVNETA_MAC_ADDR_LOW, 0xffff); | |
2130 | mvreg_write(pp, MVNETA_MAC_ADDR_HIGH, 0xffffffff); | |
2131 | } else { | |
2132 | /* Reject all Unicast addresses */ | |
2133 | port_cfg_reg &= ~MVNETA_UNI_PROMISC_MODE; | |
2134 | val &= ~MVNETA_FORCE_UNI; | |
2135 | } | |
2136 | ||
2137 | mvreg_write(pp, MVNETA_PORT_CONFIG, port_cfg_reg); | |
2138 | mvreg_write(pp, MVNETA_TYPE_PRIO, val); | |
2139 | } | |
2140 | ||
2141 | /* register unicast and multicast addresses */ | |
2142 | static void mvneta_set_rx_mode(struct net_device *dev) | |
2143 | { | |
2144 | struct mvneta_port *pp = netdev_priv(dev); | |
2145 | struct netdev_hw_addr *ha; | |
2146 | ||
2147 | if (dev->flags & IFF_PROMISC) { | |
2148 | /* Accept all: Multicast + Unicast */ | |
2149 | mvneta_rx_unicast_promisc_set(pp, 1); | |
90b74c01 GC |
2150 | mvneta_set_ucast_table(pp, pp->rxq_def); |
2151 | mvneta_set_special_mcast_table(pp, pp->rxq_def); | |
2152 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2153 | } else { |
2154 | /* Accept single Unicast */ | |
2155 | mvneta_rx_unicast_promisc_set(pp, 0); | |
2156 | mvneta_set_ucast_table(pp, -1); | |
90b74c01 | 2157 | mvneta_mac_addr_set(pp, dev->dev_addr, pp->rxq_def); |
c5aff182 TP |
2158 | |
2159 | if (dev->flags & IFF_ALLMULTI) { | |
2160 | /* Accept all multicast */ | |
90b74c01 GC |
2161 | mvneta_set_special_mcast_table(pp, pp->rxq_def); |
2162 | mvneta_set_other_mcast_table(pp, pp->rxq_def); | |
c5aff182 TP |
2163 | } else { |
2164 | /* Accept only initialized multicast */ | |
2165 | mvneta_set_special_mcast_table(pp, -1); | |
2166 | mvneta_set_other_mcast_table(pp, -1); | |
2167 | ||
2168 | if (!netdev_mc_empty(dev)) { | |
2169 | netdev_for_each_mc_addr(ha, dev) { | |
2170 | mvneta_mcast_addr_set(pp, ha->addr, | |
90b74c01 | 2171 | pp->rxq_def); |
c5aff182 TP |
2172 | } |
2173 | } | |
2174 | } | |
2175 | } | |
2176 | } | |
2177 | ||
2178 | /* Interrupt handling - the callback for request_irq() */ | |
2179 | static irqreturn_t mvneta_isr(int irq, void *dev_id) | |
2180 | { | |
12bb03b4 | 2181 | struct mvneta_pcpu_port *port = (struct mvneta_pcpu_port *)dev_id; |
c5aff182 | 2182 | |
12bb03b4 | 2183 | disable_percpu_irq(port->pp->dev->irq); |
12bb03b4 | 2184 | napi_schedule(&port->napi); |
c5aff182 TP |
2185 | |
2186 | return IRQ_HANDLED; | |
2187 | } | |
2188 | ||
898b2970 SS |
2189 | static int mvneta_fixed_link_update(struct mvneta_port *pp, |
2190 | struct phy_device *phy) | |
2191 | { | |
2192 | struct fixed_phy_status status; | |
2193 | struct fixed_phy_status changed = {}; | |
2194 | u32 gmac_stat = mvreg_read(pp, MVNETA_GMAC_STATUS); | |
2195 | ||
2196 | status.link = !!(gmac_stat & MVNETA_GMAC_LINK_UP); | |
2197 | if (gmac_stat & MVNETA_GMAC_SPEED_1000) | |
2198 | status.speed = SPEED_1000; | |
2199 | else if (gmac_stat & MVNETA_GMAC_SPEED_100) | |
2200 | status.speed = SPEED_100; | |
2201 | else | |
2202 | status.speed = SPEED_10; | |
2203 | status.duplex = !!(gmac_stat & MVNETA_GMAC_FULL_DUPLEX); | |
2204 | changed.link = 1; | |
2205 | changed.speed = 1; | |
2206 | changed.duplex = 1; | |
2207 | fixed_phy_update_state(phy, &status, &changed); | |
2208 | return 0; | |
2209 | } | |
2210 | ||
c5aff182 TP |
2211 | /* NAPI handler |
2212 | * Bits 0 - 7 of the causeRxTx register indicate that are transmitted | |
2213 | * packets on the corresponding TXQ (Bit 0 is for TX queue 1). | |
2214 | * Bits 8 -15 of the cause Rx Tx register indicate that are received | |
2215 | * packets on the corresponding RXQ (Bit 8 is for RX queue 0). | |
2216 | * Each CPU has its own causeRxTx register | |
2217 | */ | |
2218 | static int mvneta_poll(struct napi_struct *napi, int budget) | |
2219 | { | |
2220 | int rx_done = 0; | |
2221 | u32 cause_rx_tx; | |
2dcf75e2 | 2222 | int rx_queue; |
c5aff182 | 2223 | struct mvneta_port *pp = netdev_priv(napi->dev); |
12bb03b4 | 2224 | struct mvneta_pcpu_port *port = this_cpu_ptr(pp->ports); |
c5aff182 TP |
2225 | |
2226 | if (!netif_running(pp->dev)) { | |
12bb03b4 | 2227 | napi_complete(&port->napi); |
c5aff182 TP |
2228 | return rx_done; |
2229 | } | |
2230 | ||
2231 | /* Read cause register */ | |
898b2970 SS |
2232 | cause_rx_tx = mvreg_read(pp, MVNETA_INTR_NEW_CAUSE); |
2233 | if (cause_rx_tx & MVNETA_MISCINTR_INTR_MASK) { | |
2234 | u32 cause_misc = mvreg_read(pp, MVNETA_INTR_MISC_CAUSE); | |
2235 | ||
2236 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2237 | if (pp->use_inband_status && (cause_misc & | |
2238 | (MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2239 | MVNETA_CAUSE_LINK_CHANGE | | |
2240 | MVNETA_CAUSE_PSC_SYNC_CHANGE))) { | |
2241 | mvneta_fixed_link_update(pp, pp->phy_dev); | |
2242 | } | |
2243 | } | |
71f6d1b3 | 2244 | |
2245 | /* Release Tx descriptors */ | |
2246 | if (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL) { | |
0713a86a | 2247 | mvneta_tx_done_gbe(pp, (cause_rx_tx & MVNETA_TX_INTR_MASK_ALL)); |
71f6d1b3 | 2248 | cause_rx_tx &= ~MVNETA_TX_INTR_MASK_ALL; |
2249 | } | |
c5aff182 | 2250 | |
6a20c175 | 2251 | /* For the case where the last mvneta_poll did not process all |
c5aff182 TP |
2252 | * RX packets |
2253 | */ | |
2dcf75e2 GC |
2254 | rx_queue = fls(((cause_rx_tx >> 8) & 0xff)); |
2255 | ||
12bb03b4 | 2256 | cause_rx_tx |= port->cause_rx_tx; |
2dcf75e2 GC |
2257 | |
2258 | if (rx_queue) { | |
2259 | rx_queue = rx_queue - 1; | |
2260 | rx_done = mvneta_rx(pp, budget, &pp->rxqs[rx_queue]); | |
2261 | } | |
2262 | ||
d8936657 | 2263 | budget -= rx_done; |
c5aff182 TP |
2264 | |
2265 | if (budget > 0) { | |
2266 | cause_rx_tx = 0; | |
12bb03b4 MR |
2267 | napi_complete(&port->napi); |
2268 | enable_percpu_irq(pp->dev->irq, 0); | |
c5aff182 TP |
2269 | } |
2270 | ||
12bb03b4 | 2271 | port->cause_rx_tx = cause_rx_tx; |
c5aff182 TP |
2272 | return rx_done; |
2273 | } | |
2274 | ||
c5aff182 TP |
2275 | /* Handle rxq fill: allocates rxq skbs; called when initializing a port */ |
2276 | static int mvneta_rxq_fill(struct mvneta_port *pp, struct mvneta_rx_queue *rxq, | |
2277 | int num) | |
2278 | { | |
c5aff182 TP |
2279 | int i; |
2280 | ||
2281 | for (i = 0; i < num; i++) { | |
a1a65ab1 | 2282 | memset(rxq->descs + i, 0, sizeof(struct mvneta_rx_desc)); |
2283 | if (mvneta_rx_refill(pp, rxq->descs + i) != 0) { | |
2284 | netdev_err(pp->dev, "%s:rxq %d, %d of %d buffs filled\n", | |
c5aff182 TP |
2285 | __func__, rxq->id, i, num); |
2286 | break; | |
2287 | } | |
c5aff182 TP |
2288 | } |
2289 | ||
2290 | /* Add this number of RX descriptors as non occupied (ready to | |
6a20c175 TP |
2291 | * get packets) |
2292 | */ | |
c5aff182 TP |
2293 | mvneta_rxq_non_occup_desc_add(pp, rxq, i); |
2294 | ||
2295 | return i; | |
2296 | } | |
2297 | ||
2298 | /* Free all packets pending transmit from all TXQs and reset TX port */ | |
2299 | static void mvneta_tx_reset(struct mvneta_port *pp) | |
2300 | { | |
2301 | int queue; | |
2302 | ||
9672850b | 2303 | /* free the skb's in the tx ring */ |
c5aff182 TP |
2304 | for (queue = 0; queue < txq_number; queue++) |
2305 | mvneta_txq_done_force(pp, &pp->txqs[queue]); | |
2306 | ||
2307 | mvreg_write(pp, MVNETA_PORT_TX_RESET, MVNETA_PORT_TX_DMA_RESET); | |
2308 | mvreg_write(pp, MVNETA_PORT_TX_RESET, 0); | |
2309 | } | |
2310 | ||
2311 | static void mvneta_rx_reset(struct mvneta_port *pp) | |
2312 | { | |
2313 | mvreg_write(pp, MVNETA_PORT_RX_RESET, MVNETA_PORT_RX_DMA_RESET); | |
2314 | mvreg_write(pp, MVNETA_PORT_RX_RESET, 0); | |
2315 | } | |
2316 | ||
2317 | /* Rx/Tx queue initialization/cleanup methods */ | |
2318 | ||
2319 | /* Create a specified RX queue */ | |
2320 | static int mvneta_rxq_init(struct mvneta_port *pp, | |
2321 | struct mvneta_rx_queue *rxq) | |
2322 | ||
2323 | { | |
2324 | rxq->size = pp->rx_ring_size; | |
2325 | ||
2326 | /* Allocate memory for RX descriptors */ | |
2327 | rxq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2328 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2329 | &rxq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2330 | if (rxq->descs == NULL) |
c5aff182 | 2331 | return -ENOMEM; |
c5aff182 TP |
2332 | |
2333 | BUG_ON(rxq->descs != | |
2334 | PTR_ALIGN(rxq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | |
2335 | ||
2336 | rxq->last_desc = rxq->size - 1; | |
2337 | ||
2338 | /* Set Rx descriptors queue starting address */ | |
2339 | mvreg_write(pp, MVNETA_RXQ_BASE_ADDR_REG(rxq->id), rxq->descs_phys); | |
2340 | mvreg_write(pp, MVNETA_RXQ_SIZE_REG(rxq->id), rxq->size); | |
2341 | ||
2342 | /* Set Offset */ | |
2343 | mvneta_rxq_offset_set(pp, rxq, NET_SKB_PAD); | |
2344 | ||
2345 | /* Set coalescing pkts and time */ | |
2346 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
2347 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
2348 | ||
2349 | /* Fill RXQ with buffers from RX pool */ | |
2350 | mvneta_rxq_buf_size_set(pp, rxq, MVNETA_RX_BUF_SIZE(pp->pkt_size)); | |
2351 | mvneta_rxq_bm_disable(pp, rxq); | |
2352 | mvneta_rxq_fill(pp, rxq, rxq->size); | |
2353 | ||
2354 | return 0; | |
2355 | } | |
2356 | ||
2357 | /* Cleanup Rx queue */ | |
2358 | static void mvneta_rxq_deinit(struct mvneta_port *pp, | |
2359 | struct mvneta_rx_queue *rxq) | |
2360 | { | |
2361 | mvneta_rxq_drop_pkts(pp, rxq); | |
2362 | ||
2363 | if (rxq->descs) | |
2364 | dma_free_coherent(pp->dev->dev.parent, | |
2365 | rxq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2366 | rxq->descs, | |
2367 | rxq->descs_phys); | |
2368 | ||
2369 | rxq->descs = NULL; | |
2370 | rxq->last_desc = 0; | |
2371 | rxq->next_desc_to_proc = 0; | |
2372 | rxq->descs_phys = 0; | |
2373 | } | |
2374 | ||
2375 | /* Create and initialize a tx queue */ | |
2376 | static int mvneta_txq_init(struct mvneta_port *pp, | |
2377 | struct mvneta_tx_queue *txq) | |
2378 | { | |
50bf8cb6 GC |
2379 | int cpu; |
2380 | ||
c5aff182 TP |
2381 | txq->size = pp->tx_ring_size; |
2382 | ||
8eef5f97 EG |
2383 | /* A queue must always have room for at least one skb. |
2384 | * Therefore, stop the queue when the free entries reaches | |
2385 | * the maximum number of descriptors per skb. | |
2386 | */ | |
2387 | txq->tx_stop_threshold = txq->size - MVNETA_MAX_SKB_DESCS; | |
2388 | txq->tx_wake_threshold = txq->tx_stop_threshold / 2; | |
2389 | ||
2390 | ||
c5aff182 TP |
2391 | /* Allocate memory for TX descriptors */ |
2392 | txq->descs = dma_alloc_coherent(pp->dev->dev.parent, | |
2393 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2394 | &txq->descs_phys, GFP_KERNEL); | |
d0320f75 | 2395 | if (txq->descs == NULL) |
c5aff182 | 2396 | return -ENOMEM; |
c5aff182 TP |
2397 | |
2398 | /* Make sure descriptor address is cache line size aligned */ | |
2399 | BUG_ON(txq->descs != | |
2400 | PTR_ALIGN(txq->descs, MVNETA_CPU_D_CACHE_LINE_SIZE)); | |
2401 | ||
2402 | txq->last_desc = txq->size - 1; | |
2403 | ||
2404 | /* Set maximum bandwidth for enabled TXQs */ | |
2405 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0x03ffffff); | |
2406 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0x3fffffff); | |
2407 | ||
2408 | /* Set Tx descriptors queue starting address */ | |
2409 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), txq->descs_phys); | |
2410 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), txq->size); | |
2411 | ||
2412 | txq->tx_skb = kmalloc(txq->size * sizeof(*txq->tx_skb), GFP_KERNEL); | |
2413 | if (txq->tx_skb == NULL) { | |
2414 | dma_free_coherent(pp->dev->dev.parent, | |
2415 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2416 | txq->descs, txq->descs_phys); | |
2417 | return -ENOMEM; | |
2418 | } | |
2adb719d EG |
2419 | |
2420 | /* Allocate DMA buffers for TSO MAC/IP/TCP headers */ | |
2421 | txq->tso_hdrs = dma_alloc_coherent(pp->dev->dev.parent, | |
2422 | txq->size * TSO_HEADER_SIZE, | |
2423 | &txq->tso_hdrs_phys, GFP_KERNEL); | |
2424 | if (txq->tso_hdrs == NULL) { | |
2425 | kfree(txq->tx_skb); | |
2426 | dma_free_coherent(pp->dev->dev.parent, | |
2427 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2428 | txq->descs, txq->descs_phys); | |
2429 | return -ENOMEM; | |
2430 | } | |
c5aff182 TP |
2431 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); |
2432 | ||
50bf8cb6 GC |
2433 | /* Setup XPS mapping */ |
2434 | if (txq_number > 1) | |
2435 | cpu = txq->id % num_present_cpus(); | |
2436 | else | |
2437 | cpu = pp->rxq_def % num_present_cpus(); | |
2438 | cpumask_set_cpu(cpu, &txq->affinity_mask); | |
2439 | netif_set_xps_queue(pp->dev, &txq->affinity_mask, txq->id); | |
2440 | ||
c5aff182 TP |
2441 | return 0; |
2442 | } | |
2443 | ||
2444 | /* Free allocated resources when mvneta_txq_init() fails to allocate memory*/ | |
2445 | static void mvneta_txq_deinit(struct mvneta_port *pp, | |
2446 | struct mvneta_tx_queue *txq) | |
2447 | { | |
2448 | kfree(txq->tx_skb); | |
2449 | ||
2adb719d EG |
2450 | if (txq->tso_hdrs) |
2451 | dma_free_coherent(pp->dev->dev.parent, | |
2452 | txq->size * TSO_HEADER_SIZE, | |
2453 | txq->tso_hdrs, txq->tso_hdrs_phys); | |
c5aff182 TP |
2454 | if (txq->descs) |
2455 | dma_free_coherent(pp->dev->dev.parent, | |
2456 | txq->size * MVNETA_DESC_ALIGNED_SIZE, | |
2457 | txq->descs, txq->descs_phys); | |
2458 | ||
2459 | txq->descs = NULL; | |
2460 | txq->last_desc = 0; | |
2461 | txq->next_desc_to_proc = 0; | |
2462 | txq->descs_phys = 0; | |
2463 | ||
2464 | /* Set minimum bandwidth for disabled TXQs */ | |
2465 | mvreg_write(pp, MVETH_TXQ_TOKEN_CFG_REG(txq->id), 0); | |
2466 | mvreg_write(pp, MVETH_TXQ_TOKEN_COUNT_REG(txq->id), 0); | |
2467 | ||
2468 | /* Set Tx descriptors queue starting address and size */ | |
2469 | mvreg_write(pp, MVNETA_TXQ_BASE_ADDR_REG(txq->id), 0); | |
2470 | mvreg_write(pp, MVNETA_TXQ_SIZE_REG(txq->id), 0); | |
2471 | } | |
2472 | ||
2473 | /* Cleanup all Tx queues */ | |
2474 | static void mvneta_cleanup_txqs(struct mvneta_port *pp) | |
2475 | { | |
2476 | int queue; | |
2477 | ||
2478 | for (queue = 0; queue < txq_number; queue++) | |
2479 | mvneta_txq_deinit(pp, &pp->txqs[queue]); | |
2480 | } | |
2481 | ||
2482 | /* Cleanup all Rx queues */ | |
2483 | static void mvneta_cleanup_rxqs(struct mvneta_port *pp) | |
2484 | { | |
2dcf75e2 GC |
2485 | int queue; |
2486 | ||
2487 | for (queue = 0; queue < txq_number; queue++) | |
2488 | mvneta_rxq_deinit(pp, &pp->rxqs[queue]); | |
c5aff182 TP |
2489 | } |
2490 | ||
2491 | ||
2492 | /* Init all Rx queues */ | |
2493 | static int mvneta_setup_rxqs(struct mvneta_port *pp) | |
2494 | { | |
2dcf75e2 GC |
2495 | int queue; |
2496 | ||
2497 | for (queue = 0; queue < rxq_number; queue++) { | |
2498 | int err = mvneta_rxq_init(pp, &pp->rxqs[queue]); | |
2499 | ||
2500 | if (err) { | |
2501 | netdev_err(pp->dev, "%s: can't create rxq=%d\n", | |
2502 | __func__, queue); | |
2503 | mvneta_cleanup_rxqs(pp); | |
2504 | return err; | |
2505 | } | |
c5aff182 TP |
2506 | } |
2507 | ||
2508 | return 0; | |
2509 | } | |
2510 | ||
2511 | /* Init all tx queues */ | |
2512 | static int mvneta_setup_txqs(struct mvneta_port *pp) | |
2513 | { | |
2514 | int queue; | |
2515 | ||
2516 | for (queue = 0; queue < txq_number; queue++) { | |
2517 | int err = mvneta_txq_init(pp, &pp->txqs[queue]); | |
2518 | if (err) { | |
2519 | netdev_err(pp->dev, "%s: can't create txq=%d\n", | |
2520 | __func__, queue); | |
2521 | mvneta_cleanup_txqs(pp); | |
2522 | return err; | |
2523 | } | |
2524 | } | |
2525 | ||
2526 | return 0; | |
2527 | } | |
2528 | ||
2dcf75e2 GC |
2529 | static void mvneta_percpu_unmask_interrupt(void *arg) |
2530 | { | |
2531 | struct mvneta_port *pp = arg; | |
2532 | ||
2533 | /* All the queue are unmasked, but actually only the ones | |
2534 | * maped to this CPU will be unmasked | |
2535 | */ | |
2536 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
2537 | MVNETA_RX_INTR_MASK_ALL | | |
2538 | MVNETA_TX_INTR_MASK_ALL | | |
2539 | MVNETA_MISCINTR_INTR_MASK); | |
2540 | } | |
2541 | ||
9a401dea GC |
2542 | static void mvneta_percpu_mask_interrupt(void *arg) |
2543 | { | |
2544 | struct mvneta_port *pp = arg; | |
2545 | ||
2546 | /* All the queue are masked, but actually only the ones | |
2547 | * maped to this CPU will be masked | |
2548 | */ | |
2549 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2550 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
2551 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
2552 | } | |
2553 | ||
c5aff182 TP |
2554 | static void mvneta_start_dev(struct mvneta_port *pp) |
2555 | { | |
12bb03b4 MR |
2556 | unsigned int cpu; |
2557 | ||
c5aff182 TP |
2558 | mvneta_max_rx_size_set(pp, pp->pkt_size); |
2559 | mvneta_txq_max_tx_size_set(pp, pp->pkt_size); | |
2560 | ||
2561 | /* start the Rx/Tx activity */ | |
2562 | mvneta_port_enable(pp); | |
2563 | ||
2564 | /* Enable polling on the port */ | |
12bb03b4 MR |
2565 | for_each_present_cpu(cpu) { |
2566 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
2567 | ||
2568 | napi_enable(&port->napi); | |
2569 | } | |
c5aff182 | 2570 | |
2dcf75e2 GC |
2571 | /* Unmask interrupts. It has to be done from each CPU */ |
2572 | for_each_online_cpu(cpu) | |
2573 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
2574 | pp, true); | |
898b2970 SS |
2575 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, |
2576 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2577 | MVNETA_CAUSE_LINK_CHANGE | | |
2578 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
c5aff182 TP |
2579 | |
2580 | phy_start(pp->phy_dev); | |
2581 | netif_tx_start_all_queues(pp->dev); | |
2582 | } | |
2583 | ||
2584 | static void mvneta_stop_dev(struct mvneta_port *pp) | |
2585 | { | |
12bb03b4 MR |
2586 | unsigned int cpu; |
2587 | ||
c5aff182 TP |
2588 | phy_stop(pp->phy_dev); |
2589 | ||
12bb03b4 MR |
2590 | for_each_present_cpu(cpu) { |
2591 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
2592 | ||
2593 | napi_disable(&port->napi); | |
2594 | } | |
c5aff182 TP |
2595 | |
2596 | netif_carrier_off(pp->dev); | |
2597 | ||
2598 | mvneta_port_down(pp); | |
2599 | netif_tx_stop_all_queues(pp->dev); | |
2600 | ||
2601 | /* Stop the port activity */ | |
2602 | mvneta_port_disable(pp); | |
2603 | ||
2604 | /* Clear all ethernet port interrupts */ | |
2605 | mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0); | |
2606 | mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0); | |
2607 | ||
2608 | /* Mask all ethernet port interrupts */ | |
2609 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2610 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
2611 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
2612 | ||
2613 | mvneta_tx_reset(pp); | |
2614 | mvneta_rx_reset(pp); | |
2615 | } | |
2616 | ||
c5aff182 TP |
2617 | /* Return positive if MTU is valid */ |
2618 | static int mvneta_check_mtu_valid(struct net_device *dev, int mtu) | |
2619 | { | |
2620 | if (mtu < 68) { | |
2621 | netdev_err(dev, "cannot change mtu to less than 68\n"); | |
2622 | return -EINVAL; | |
2623 | } | |
2624 | ||
6a20c175 | 2625 | /* 9676 == 9700 - 20 and rounding to 8 */ |
c5aff182 TP |
2626 | if (mtu > 9676) { |
2627 | netdev_info(dev, "Illegal MTU value %d, round to 9676\n", mtu); | |
2628 | mtu = 9676; | |
2629 | } | |
2630 | ||
2631 | if (!IS_ALIGNED(MVNETA_RX_PKT_SIZE(mtu), 8)) { | |
2632 | netdev_info(dev, "Illegal MTU value %d, rounding to %d\n", | |
2633 | mtu, ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8)); | |
2634 | mtu = ALIGN(MVNETA_RX_PKT_SIZE(mtu), 8); | |
2635 | } | |
2636 | ||
2637 | return mtu; | |
2638 | } | |
2639 | ||
2640 | /* Change the device mtu */ | |
2641 | static int mvneta_change_mtu(struct net_device *dev, int mtu) | |
2642 | { | |
2643 | struct mvneta_port *pp = netdev_priv(dev); | |
2644 | int ret; | |
2645 | ||
2646 | mtu = mvneta_check_mtu_valid(dev, mtu); | |
2647 | if (mtu < 0) | |
2648 | return -EINVAL; | |
2649 | ||
2650 | dev->mtu = mtu; | |
2651 | ||
b65657fc SG |
2652 | if (!netif_running(dev)) { |
2653 | netdev_update_features(dev); | |
c5aff182 | 2654 | return 0; |
b65657fc | 2655 | } |
c5aff182 | 2656 | |
6a20c175 | 2657 | /* The interface is running, so we have to force a |
a92dbd96 | 2658 | * reallocation of the queues |
c5aff182 TP |
2659 | */ |
2660 | mvneta_stop_dev(pp); | |
2661 | ||
2662 | mvneta_cleanup_txqs(pp); | |
2663 | mvneta_cleanup_rxqs(pp); | |
2664 | ||
a92dbd96 | 2665 | pp->pkt_size = MVNETA_RX_PKT_SIZE(dev->mtu); |
8ec2cd48 | 2666 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
2667 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
2668 | |
2669 | ret = mvneta_setup_rxqs(pp); | |
2670 | if (ret) { | |
a92dbd96 | 2671 | netdev_err(dev, "unable to setup rxqs after MTU change\n"); |
c5aff182 TP |
2672 | return ret; |
2673 | } | |
2674 | ||
a92dbd96 EG |
2675 | ret = mvneta_setup_txqs(pp); |
2676 | if (ret) { | |
2677 | netdev_err(dev, "unable to setup txqs after MTU change\n"); | |
2678 | return ret; | |
2679 | } | |
c5aff182 TP |
2680 | |
2681 | mvneta_start_dev(pp); | |
2682 | mvneta_port_up(pp); | |
2683 | ||
b65657fc SG |
2684 | netdev_update_features(dev); |
2685 | ||
c5aff182 TP |
2686 | return 0; |
2687 | } | |
2688 | ||
b65657fc SG |
2689 | static netdev_features_t mvneta_fix_features(struct net_device *dev, |
2690 | netdev_features_t features) | |
2691 | { | |
2692 | struct mvneta_port *pp = netdev_priv(dev); | |
2693 | ||
2694 | if (pp->tx_csum_limit && dev->mtu > pp->tx_csum_limit) { | |
2695 | features &= ~(NETIF_F_IP_CSUM | NETIF_F_TSO); | |
2696 | netdev_info(dev, | |
2697 | "Disable IP checksum for MTU greater than %dB\n", | |
2698 | pp->tx_csum_limit); | |
2699 | } | |
2700 | ||
2701 | return features; | |
2702 | } | |
2703 | ||
8cc3e439 TP |
2704 | /* Get mac address */ |
2705 | static void mvneta_get_mac_addr(struct mvneta_port *pp, unsigned char *addr) | |
2706 | { | |
2707 | u32 mac_addr_l, mac_addr_h; | |
2708 | ||
2709 | mac_addr_l = mvreg_read(pp, MVNETA_MAC_ADDR_LOW); | |
2710 | mac_addr_h = mvreg_read(pp, MVNETA_MAC_ADDR_HIGH); | |
2711 | addr[0] = (mac_addr_h >> 24) & 0xFF; | |
2712 | addr[1] = (mac_addr_h >> 16) & 0xFF; | |
2713 | addr[2] = (mac_addr_h >> 8) & 0xFF; | |
2714 | addr[3] = mac_addr_h & 0xFF; | |
2715 | addr[4] = (mac_addr_l >> 8) & 0xFF; | |
2716 | addr[5] = mac_addr_l & 0xFF; | |
2717 | } | |
2718 | ||
c5aff182 TP |
2719 | /* Handle setting mac address */ |
2720 | static int mvneta_set_mac_addr(struct net_device *dev, void *addr) | |
2721 | { | |
2722 | struct mvneta_port *pp = netdev_priv(dev); | |
e68de360 EG |
2723 | struct sockaddr *sockaddr = addr; |
2724 | int ret; | |
c5aff182 | 2725 | |
e68de360 EG |
2726 | ret = eth_prepare_mac_addr_change(dev, addr); |
2727 | if (ret < 0) | |
2728 | return ret; | |
c5aff182 TP |
2729 | /* Remove previous address table entry */ |
2730 | mvneta_mac_addr_set(pp, dev->dev_addr, -1); | |
2731 | ||
2732 | /* Set new addr in hw */ | |
90b74c01 | 2733 | mvneta_mac_addr_set(pp, sockaddr->sa_data, pp->rxq_def); |
c5aff182 | 2734 | |
e68de360 | 2735 | eth_commit_mac_addr_change(dev, addr); |
c5aff182 TP |
2736 | return 0; |
2737 | } | |
2738 | ||
2739 | static void mvneta_adjust_link(struct net_device *ndev) | |
2740 | { | |
2741 | struct mvneta_port *pp = netdev_priv(ndev); | |
2742 | struct phy_device *phydev = pp->phy_dev; | |
2743 | int status_change = 0; | |
2744 | ||
2745 | if (phydev->link) { | |
2746 | if ((pp->speed != phydev->speed) || | |
2747 | (pp->duplex != phydev->duplex)) { | |
2748 | u32 val; | |
2749 | ||
2750 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
2751 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
2752 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
898b2970 | 2753 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); |
c5aff182 TP |
2754 | |
2755 | if (phydev->duplex) | |
2756 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
2757 | ||
2758 | if (phydev->speed == SPEED_1000) | |
2759 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
4d12bc63 | 2760 | else if (phydev->speed == SPEED_100) |
c5aff182 TP |
2761 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; |
2762 | ||
2763 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
2764 | ||
2765 | pp->duplex = phydev->duplex; | |
2766 | pp->speed = phydev->speed; | |
2767 | } | |
2768 | } | |
2769 | ||
2770 | if (phydev->link != pp->link) { | |
2771 | if (!phydev->link) { | |
2772 | pp->duplex = -1; | |
2773 | pp->speed = 0; | |
2774 | } | |
2775 | ||
2776 | pp->link = phydev->link; | |
2777 | status_change = 1; | |
2778 | } | |
2779 | ||
2780 | if (status_change) { | |
2781 | if (phydev->link) { | |
898b2970 SS |
2782 | if (!pp->use_inband_status) { |
2783 | u32 val = mvreg_read(pp, | |
2784 | MVNETA_GMAC_AUTONEG_CONFIG); | |
2785 | val &= ~MVNETA_GMAC_FORCE_LINK_DOWN; | |
2786 | val |= MVNETA_GMAC_FORCE_LINK_PASS; | |
2787 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
2788 | val); | |
2789 | } | |
c5aff182 | 2790 | mvneta_port_up(pp); |
c5aff182 | 2791 | } else { |
898b2970 SS |
2792 | if (!pp->use_inband_status) { |
2793 | u32 val = mvreg_read(pp, | |
2794 | MVNETA_GMAC_AUTONEG_CONFIG); | |
2795 | val &= ~MVNETA_GMAC_FORCE_LINK_PASS; | |
2796 | val |= MVNETA_GMAC_FORCE_LINK_DOWN; | |
2797 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, | |
2798 | val); | |
2799 | } | |
c5aff182 | 2800 | mvneta_port_down(pp); |
c5aff182 | 2801 | } |
0089b745 | 2802 | phy_print_status(phydev); |
c5aff182 TP |
2803 | } |
2804 | } | |
2805 | ||
2806 | static int mvneta_mdio_probe(struct mvneta_port *pp) | |
2807 | { | |
2808 | struct phy_device *phy_dev; | |
2809 | ||
2810 | phy_dev = of_phy_connect(pp->dev, pp->phy_node, mvneta_adjust_link, 0, | |
2811 | pp->phy_interface); | |
2812 | if (!phy_dev) { | |
2813 | netdev_err(pp->dev, "could not find the PHY\n"); | |
2814 | return -ENODEV; | |
2815 | } | |
2816 | ||
2817 | phy_dev->supported &= PHY_GBIT_FEATURES; | |
2818 | phy_dev->advertising = phy_dev->supported; | |
2819 | ||
2820 | pp->phy_dev = phy_dev; | |
2821 | pp->link = 0; | |
2822 | pp->duplex = 0; | |
2823 | pp->speed = 0; | |
2824 | ||
2825 | return 0; | |
2826 | } | |
2827 | ||
2828 | static void mvneta_mdio_remove(struct mvneta_port *pp) | |
2829 | { | |
2830 | phy_disconnect(pp->phy_dev); | |
2831 | pp->phy_dev = NULL; | |
2832 | } | |
2833 | ||
f8642885 MR |
2834 | static void mvneta_percpu_enable(void *arg) |
2835 | { | |
2836 | struct mvneta_port *pp = arg; | |
2837 | ||
2838 | enable_percpu_irq(pp->dev->irq, IRQ_TYPE_NONE); | |
2839 | } | |
2840 | ||
2841 | static void mvneta_percpu_disable(void *arg) | |
2842 | { | |
2843 | struct mvneta_port *pp = arg; | |
2844 | ||
2845 | disable_percpu_irq(pp->dev->irq); | |
2846 | } | |
2847 | ||
2848 | static void mvneta_percpu_elect(struct mvneta_port *pp) | |
2849 | { | |
2dcf75e2 | 2850 | int online_cpu_idx, max_cpu, cpu, i = 0; |
f8642885 | 2851 | |
90b74c01 | 2852 | online_cpu_idx = pp->rxq_def % num_online_cpus(); |
2dcf75e2 | 2853 | max_cpu = num_present_cpus(); |
f8642885 MR |
2854 | |
2855 | for_each_online_cpu(cpu) { | |
2dcf75e2 GC |
2856 | int rxq_map = 0, txq_map = 0; |
2857 | int rxq; | |
2858 | ||
2859 | for (rxq = 0; rxq < rxq_number; rxq++) | |
2860 | if ((rxq % max_cpu) == cpu) | |
2861 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(rxq); | |
2862 | ||
50bf8cb6 GC |
2863 | if (i == online_cpu_idx) |
2864 | /* Map the default receive queue queue to the | |
2865 | * elected CPU | |
f8642885 | 2866 | */ |
2dcf75e2 | 2867 | rxq_map |= MVNETA_CPU_RXQ_ACCESS(pp->rxq_def); |
50bf8cb6 GC |
2868 | |
2869 | /* We update the TX queue map only if we have one | |
2870 | * queue. In this case we associate the TX queue to | |
2871 | * the CPU bound to the default RX queue | |
2872 | */ | |
2873 | if (txq_number == 1) | |
2874 | txq_map = (i == online_cpu_idx) ? | |
2875 | MVNETA_CPU_TXQ_ACCESS(1) : 0; | |
2876 | else | |
2877 | txq_map = mvreg_read(pp, MVNETA_CPU_MAP(cpu)) & | |
2878 | MVNETA_CPU_TXQ_ACCESS_ALL_MASK; | |
2879 | ||
2dcf75e2 GC |
2880 | mvreg_write(pp, MVNETA_CPU_MAP(cpu), rxq_map | txq_map); |
2881 | ||
2882 | /* Update the interrupt mask on each CPU according the | |
2883 | * new mapping | |
2884 | */ | |
2885 | smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt, | |
2886 | pp, true); | |
f8642885 | 2887 | i++; |
2dcf75e2 | 2888 | |
f8642885 MR |
2889 | } |
2890 | }; | |
2891 | ||
2892 | static int mvneta_percpu_notifier(struct notifier_block *nfb, | |
2893 | unsigned long action, void *hcpu) | |
2894 | { | |
2895 | struct mvneta_port *pp = container_of(nfb, struct mvneta_port, | |
2896 | cpu_notifier); | |
2897 | int cpu = (unsigned long)hcpu, other_cpu; | |
2898 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
2899 | ||
2900 | switch (action) { | |
2901 | case CPU_ONLINE: | |
2902 | case CPU_ONLINE_FROZEN: | |
2903 | netif_tx_stop_all_queues(pp->dev); | |
2904 | ||
2905 | /* We have to synchronise on tha napi of each CPU | |
2906 | * except the one just being waked up | |
2907 | */ | |
2908 | for_each_online_cpu(other_cpu) { | |
2909 | if (other_cpu != cpu) { | |
2910 | struct mvneta_pcpu_port *other_port = | |
2911 | per_cpu_ptr(pp->ports, other_cpu); | |
2912 | ||
2913 | napi_synchronize(&other_port->napi); | |
2914 | } | |
2915 | } | |
2916 | ||
2917 | /* Mask all ethernet port interrupts */ | |
2918 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2919 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
2920 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
2921 | napi_enable(&port->napi); | |
2922 | ||
2dcf75e2 GC |
2923 | |
2924 | /* Enable per-CPU interrupts on the CPU that is | |
2925 | * brought up. | |
2926 | */ | |
2927 | smp_call_function_single(cpu, mvneta_percpu_enable, | |
2928 | pp, true); | |
2929 | ||
f8642885 MR |
2930 | /* Enable per-CPU interrupt on the one CPU we care |
2931 | * about. | |
2932 | */ | |
2933 | mvneta_percpu_elect(pp); | |
2934 | ||
2dcf75e2 GC |
2935 | /* Unmask all ethernet port interrupts, as this |
2936 | * notifier is called for each CPU then the CPU to | |
2937 | * Queue mapping is applied | |
2938 | */ | |
f8642885 MR |
2939 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, |
2940 | MVNETA_RX_INTR_MASK(rxq_number) | | |
2941 | MVNETA_TX_INTR_MASK(txq_number) | | |
2942 | MVNETA_MISCINTR_INTR_MASK); | |
2943 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
2944 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2945 | MVNETA_CAUSE_LINK_CHANGE | | |
2946 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
2947 | netif_tx_start_all_queues(pp->dev); | |
2948 | break; | |
2949 | case CPU_DOWN_PREPARE: | |
2950 | case CPU_DOWN_PREPARE_FROZEN: | |
2951 | netif_tx_stop_all_queues(pp->dev); | |
2952 | /* Mask all ethernet port interrupts */ | |
2953 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0); | |
2954 | mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0); | |
2955 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0); | |
2956 | ||
2957 | napi_synchronize(&port->napi); | |
2958 | napi_disable(&port->napi); | |
2959 | /* Disable per-CPU interrupts on the CPU that is | |
2960 | * brought down. | |
2961 | */ | |
2962 | smp_call_function_single(cpu, mvneta_percpu_disable, | |
2963 | pp, true); | |
2964 | ||
2965 | break; | |
2966 | case CPU_DEAD: | |
2967 | case CPU_DEAD_FROZEN: | |
2968 | /* Check if a new CPU must be elected now this on is down */ | |
2969 | mvneta_percpu_elect(pp); | |
2970 | /* Unmask all ethernet port interrupts */ | |
2971 | mvreg_write(pp, MVNETA_INTR_NEW_MASK, | |
2972 | MVNETA_RX_INTR_MASK(rxq_number) | | |
2973 | MVNETA_TX_INTR_MASK(txq_number) | | |
2974 | MVNETA_MISCINTR_INTR_MASK); | |
2975 | mvreg_write(pp, MVNETA_INTR_MISC_MASK, | |
2976 | MVNETA_CAUSE_PHY_STATUS_CHANGE | | |
2977 | MVNETA_CAUSE_LINK_CHANGE | | |
2978 | MVNETA_CAUSE_PSC_SYNC_CHANGE); | |
2979 | netif_tx_start_all_queues(pp->dev); | |
2980 | break; | |
2981 | } | |
2982 | ||
2983 | return NOTIFY_OK; | |
2984 | } | |
2985 | ||
c5aff182 TP |
2986 | static int mvneta_open(struct net_device *dev) |
2987 | { | |
2988 | struct mvneta_port *pp = netdev_priv(dev); | |
2dcf75e2 | 2989 | int ret, cpu; |
c5aff182 | 2990 | |
c5aff182 | 2991 | pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu); |
8ec2cd48 | 2992 | pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) + |
2993 | SKB_DATA_ALIGN(sizeof(struct skb_shared_info)); | |
c5aff182 TP |
2994 | |
2995 | ret = mvneta_setup_rxqs(pp); | |
2996 | if (ret) | |
2997 | return ret; | |
2998 | ||
2999 | ret = mvneta_setup_txqs(pp); | |
3000 | if (ret) | |
3001 | goto err_cleanup_rxqs; | |
3002 | ||
3003 | /* Connect to port interrupt line */ | |
12bb03b4 MR |
3004 | ret = request_percpu_irq(pp->dev->irq, mvneta_isr, |
3005 | MVNETA_DRIVER_NAME, pp->ports); | |
c5aff182 TP |
3006 | if (ret) { |
3007 | netdev_err(pp->dev, "cannot request irq %d\n", pp->dev->irq); | |
3008 | goto err_cleanup_txqs; | |
3009 | } | |
3010 | ||
f8642885 MR |
3011 | /* Even though the documentation says that request_percpu_irq |
3012 | * doesn't enable the interrupts automatically, it actually | |
3013 | * does so on the local CPU. | |
3014 | * | |
3015 | * Make sure it's disabled. | |
3016 | */ | |
3017 | mvneta_percpu_disable(pp); | |
3018 | ||
2dcf75e2 GC |
3019 | /* Enable per-CPU interrupt on all the CPU to handle our RX |
3020 | * queue interrupts | |
3021 | */ | |
3022 | for_each_online_cpu(cpu) | |
3023 | smp_call_function_single(cpu, mvneta_percpu_enable, | |
3024 | pp, true); | |
3025 | ||
f8642885 MR |
3026 | |
3027 | /* Register a CPU notifier to handle the case where our CPU | |
3028 | * might be taken offline. | |
3029 | */ | |
3030 | register_cpu_notifier(&pp->cpu_notifier); | |
3031 | ||
c5aff182 TP |
3032 | /* In default link is down */ |
3033 | netif_carrier_off(pp->dev); | |
3034 | ||
3035 | ret = mvneta_mdio_probe(pp); | |
3036 | if (ret < 0) { | |
3037 | netdev_err(dev, "cannot probe MDIO bus\n"); | |
3038 | goto err_free_irq; | |
3039 | } | |
3040 | ||
3041 | mvneta_start_dev(pp); | |
3042 | ||
3043 | return 0; | |
3044 | ||
3045 | err_free_irq: | |
12bb03b4 | 3046 | free_percpu_irq(pp->dev->irq, pp->ports); |
c5aff182 TP |
3047 | err_cleanup_txqs: |
3048 | mvneta_cleanup_txqs(pp); | |
3049 | err_cleanup_rxqs: | |
3050 | mvneta_cleanup_rxqs(pp); | |
3051 | return ret; | |
3052 | } | |
3053 | ||
3054 | /* Stop the port, free port interrupt line */ | |
3055 | static int mvneta_stop(struct net_device *dev) | |
3056 | { | |
3057 | struct mvneta_port *pp = netdev_priv(dev); | |
f8642885 | 3058 | int cpu; |
c5aff182 TP |
3059 | |
3060 | mvneta_stop_dev(pp); | |
3061 | mvneta_mdio_remove(pp); | |
f8642885 MR |
3062 | unregister_cpu_notifier(&pp->cpu_notifier); |
3063 | for_each_present_cpu(cpu) | |
3064 | smp_call_function_single(cpu, mvneta_percpu_disable, pp, true); | |
12bb03b4 | 3065 | free_percpu_irq(dev->irq, pp->ports); |
c5aff182 TP |
3066 | mvneta_cleanup_rxqs(pp); |
3067 | mvneta_cleanup_txqs(pp); | |
c5aff182 TP |
3068 | |
3069 | return 0; | |
3070 | } | |
3071 | ||
15f59456 TP |
3072 | static int mvneta_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3073 | { | |
3074 | struct mvneta_port *pp = netdev_priv(dev); | |
15f59456 TP |
3075 | |
3076 | if (!pp->phy_dev) | |
3077 | return -ENOTSUPP; | |
3078 | ||
ecf7b361 | 3079 | return phy_mii_ioctl(pp->phy_dev, ifr, cmd); |
15f59456 TP |
3080 | } |
3081 | ||
c5aff182 TP |
3082 | /* Ethtool methods */ |
3083 | ||
3084 | /* Get settings (phy address, speed) for ethtools */ | |
3085 | int mvneta_ethtool_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3086 | { | |
3087 | struct mvneta_port *pp = netdev_priv(dev); | |
3088 | ||
3089 | if (!pp->phy_dev) | |
3090 | return -ENODEV; | |
3091 | ||
3092 | return phy_ethtool_gset(pp->phy_dev, cmd); | |
3093 | } | |
3094 | ||
3095 | /* Set settings (phy address, speed) for ethtools */ | |
3096 | int mvneta_ethtool_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3097 | { | |
3098 | struct mvneta_port *pp = netdev_priv(dev); | |
0c0744fc | 3099 | struct phy_device *phydev = pp->phy_dev; |
c5aff182 | 3100 | |
0c0744fc | 3101 | if (!phydev) |
c5aff182 TP |
3102 | return -ENODEV; |
3103 | ||
0c0744fc SS |
3104 | if ((cmd->autoneg == AUTONEG_ENABLE) != pp->use_inband_status) { |
3105 | u32 val; | |
3106 | ||
3107 | mvneta_set_autoneg(pp, cmd->autoneg == AUTONEG_ENABLE); | |
3108 | ||
3109 | if (cmd->autoneg == AUTONEG_DISABLE) { | |
3110 | val = mvreg_read(pp, MVNETA_GMAC_AUTONEG_CONFIG); | |
3111 | val &= ~(MVNETA_GMAC_CONFIG_MII_SPEED | | |
3112 | MVNETA_GMAC_CONFIG_GMII_SPEED | | |
3113 | MVNETA_GMAC_CONFIG_FULL_DUPLEX); | |
3114 | ||
3115 | if (phydev->duplex) | |
3116 | val |= MVNETA_GMAC_CONFIG_FULL_DUPLEX; | |
3117 | ||
3118 | if (phydev->speed == SPEED_1000) | |
3119 | val |= MVNETA_GMAC_CONFIG_GMII_SPEED; | |
3120 | else if (phydev->speed == SPEED_100) | |
3121 | val |= MVNETA_GMAC_CONFIG_MII_SPEED; | |
3122 | ||
3123 | mvreg_write(pp, MVNETA_GMAC_AUTONEG_CONFIG, val); | |
3124 | } | |
3125 | ||
3126 | pp->use_inband_status = (cmd->autoneg == AUTONEG_ENABLE); | |
3127 | netdev_info(pp->dev, "autoneg status set to %i\n", | |
3128 | pp->use_inband_status); | |
3129 | ||
3130 | if (netif_running(dev)) { | |
3131 | mvneta_port_down(pp); | |
3132 | mvneta_port_up(pp); | |
3133 | } | |
3134 | } | |
3135 | ||
c5aff182 TP |
3136 | return phy_ethtool_sset(pp->phy_dev, cmd); |
3137 | } | |
3138 | ||
3139 | /* Set interrupt coalescing for ethtools */ | |
3140 | static int mvneta_ethtool_set_coalesce(struct net_device *dev, | |
3141 | struct ethtool_coalesce *c) | |
3142 | { | |
3143 | struct mvneta_port *pp = netdev_priv(dev); | |
3144 | int queue; | |
3145 | ||
3146 | for (queue = 0; queue < rxq_number; queue++) { | |
3147 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3148 | rxq->time_coal = c->rx_coalesce_usecs; | |
3149 | rxq->pkts_coal = c->rx_max_coalesced_frames; | |
3150 | mvneta_rx_pkts_coal_set(pp, rxq, rxq->pkts_coal); | |
3151 | mvneta_rx_time_coal_set(pp, rxq, rxq->time_coal); | |
3152 | } | |
3153 | ||
3154 | for (queue = 0; queue < txq_number; queue++) { | |
3155 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3156 | txq->done_pkts_coal = c->tx_max_coalesced_frames; | |
3157 | mvneta_tx_done_pkts_coal_set(pp, txq, txq->done_pkts_coal); | |
3158 | } | |
3159 | ||
3160 | return 0; | |
3161 | } | |
3162 | ||
3163 | /* get coalescing for ethtools */ | |
3164 | static int mvneta_ethtool_get_coalesce(struct net_device *dev, | |
3165 | struct ethtool_coalesce *c) | |
3166 | { | |
3167 | struct mvneta_port *pp = netdev_priv(dev); | |
3168 | ||
3169 | c->rx_coalesce_usecs = pp->rxqs[0].time_coal; | |
3170 | c->rx_max_coalesced_frames = pp->rxqs[0].pkts_coal; | |
3171 | ||
3172 | c->tx_max_coalesced_frames = pp->txqs[0].done_pkts_coal; | |
3173 | return 0; | |
3174 | } | |
3175 | ||
3176 | ||
3177 | static void mvneta_ethtool_get_drvinfo(struct net_device *dev, | |
3178 | struct ethtool_drvinfo *drvinfo) | |
3179 | { | |
3180 | strlcpy(drvinfo->driver, MVNETA_DRIVER_NAME, | |
3181 | sizeof(drvinfo->driver)); | |
3182 | strlcpy(drvinfo->version, MVNETA_DRIVER_VERSION, | |
3183 | sizeof(drvinfo->version)); | |
3184 | strlcpy(drvinfo->bus_info, dev_name(&dev->dev), | |
3185 | sizeof(drvinfo->bus_info)); | |
3186 | } | |
3187 | ||
3188 | ||
3189 | static void mvneta_ethtool_get_ringparam(struct net_device *netdev, | |
3190 | struct ethtool_ringparam *ring) | |
3191 | { | |
3192 | struct mvneta_port *pp = netdev_priv(netdev); | |
3193 | ||
3194 | ring->rx_max_pending = MVNETA_MAX_RXD; | |
3195 | ring->tx_max_pending = MVNETA_MAX_TXD; | |
3196 | ring->rx_pending = pp->rx_ring_size; | |
3197 | ring->tx_pending = pp->tx_ring_size; | |
3198 | } | |
3199 | ||
3200 | static int mvneta_ethtool_set_ringparam(struct net_device *dev, | |
3201 | struct ethtool_ringparam *ring) | |
3202 | { | |
3203 | struct mvneta_port *pp = netdev_priv(dev); | |
3204 | ||
3205 | if ((ring->rx_pending == 0) || (ring->tx_pending == 0)) | |
3206 | return -EINVAL; | |
3207 | pp->rx_ring_size = ring->rx_pending < MVNETA_MAX_RXD ? | |
3208 | ring->rx_pending : MVNETA_MAX_RXD; | |
8eef5f97 EG |
3209 | |
3210 | pp->tx_ring_size = clamp_t(u16, ring->tx_pending, | |
3211 | MVNETA_MAX_SKB_DESCS * 2, MVNETA_MAX_TXD); | |
3212 | if (pp->tx_ring_size != ring->tx_pending) | |
3213 | netdev_warn(dev, "TX queue size set to %u (requested %u)\n", | |
3214 | pp->tx_ring_size, ring->tx_pending); | |
c5aff182 TP |
3215 | |
3216 | if (netif_running(dev)) { | |
3217 | mvneta_stop(dev); | |
3218 | if (mvneta_open(dev)) { | |
3219 | netdev_err(dev, | |
3220 | "error on opening device after ring param change\n"); | |
3221 | return -ENOMEM; | |
3222 | } | |
3223 | } | |
3224 | ||
3225 | return 0; | |
3226 | } | |
3227 | ||
9b0cdefa RK |
3228 | static void mvneta_ethtool_get_strings(struct net_device *netdev, u32 sset, |
3229 | u8 *data) | |
3230 | { | |
3231 | if (sset == ETH_SS_STATS) { | |
3232 | int i; | |
3233 | ||
3234 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3235 | memcpy(data + i * ETH_GSTRING_LEN, | |
3236 | mvneta_statistics[i].name, ETH_GSTRING_LEN); | |
3237 | } | |
3238 | } | |
3239 | ||
3240 | static void mvneta_ethtool_update_stats(struct mvneta_port *pp) | |
3241 | { | |
3242 | const struct mvneta_statistic *s; | |
3243 | void __iomem *base = pp->base; | |
3244 | u32 high, low, val; | |
3245 | int i; | |
3246 | ||
3247 | for (i = 0, s = mvneta_statistics; | |
3248 | s < mvneta_statistics + ARRAY_SIZE(mvneta_statistics); | |
3249 | s++, i++) { | |
3250 | val = 0; | |
3251 | ||
3252 | switch (s->type) { | |
3253 | case T_REG_32: | |
3254 | val = readl_relaxed(base + s->offset); | |
3255 | break; | |
3256 | case T_REG_64: | |
3257 | /* Docs say to read low 32-bit then high */ | |
3258 | low = readl_relaxed(base + s->offset); | |
3259 | high = readl_relaxed(base + s->offset + 4); | |
3260 | val = (u64)high << 32 | low; | |
3261 | break; | |
3262 | } | |
3263 | ||
3264 | pp->ethtool_stats[i] += val; | |
3265 | } | |
3266 | } | |
3267 | ||
3268 | static void mvneta_ethtool_get_stats(struct net_device *dev, | |
3269 | struct ethtool_stats *stats, u64 *data) | |
3270 | { | |
3271 | struct mvneta_port *pp = netdev_priv(dev); | |
3272 | int i; | |
3273 | ||
3274 | mvneta_ethtool_update_stats(pp); | |
3275 | ||
3276 | for (i = 0; i < ARRAY_SIZE(mvneta_statistics); i++) | |
3277 | *data++ = pp->ethtool_stats[i]; | |
3278 | } | |
3279 | ||
3280 | static int mvneta_ethtool_get_sset_count(struct net_device *dev, int sset) | |
3281 | { | |
3282 | if (sset == ETH_SS_STATS) | |
3283 | return ARRAY_SIZE(mvneta_statistics); | |
3284 | return -EOPNOTSUPP; | |
3285 | } | |
3286 | ||
9a401dea GC |
3287 | static u32 mvneta_ethtool_get_rxfh_indir_size(struct net_device *dev) |
3288 | { | |
3289 | return MVNETA_RSS_LU_TABLE_SIZE; | |
3290 | } | |
3291 | ||
3292 | static int mvneta_ethtool_get_rxnfc(struct net_device *dev, | |
3293 | struct ethtool_rxnfc *info, | |
3294 | u32 *rules __always_unused) | |
3295 | { | |
3296 | switch (info->cmd) { | |
3297 | case ETHTOOL_GRXRINGS: | |
3298 | info->data = rxq_number; | |
3299 | return 0; | |
3300 | case ETHTOOL_GRXFH: | |
3301 | return -EOPNOTSUPP; | |
3302 | default: | |
3303 | return -EOPNOTSUPP; | |
3304 | } | |
3305 | } | |
3306 | ||
3307 | static int mvneta_config_rss(struct mvneta_port *pp) | |
3308 | { | |
3309 | int cpu; | |
3310 | u32 val; | |
3311 | ||
3312 | netif_tx_stop_all_queues(pp->dev); | |
3313 | ||
3314 | for_each_online_cpu(cpu) | |
3315 | smp_call_function_single(cpu, mvneta_percpu_mask_interrupt, | |
3316 | pp, true); | |
3317 | ||
3318 | /* We have to synchronise on the napi of each CPU */ | |
3319 | for_each_online_cpu(cpu) { | |
3320 | struct mvneta_pcpu_port *pcpu_port = | |
3321 | per_cpu_ptr(pp->ports, cpu); | |
3322 | ||
3323 | napi_synchronize(&pcpu_port->napi); | |
3324 | napi_disable(&pcpu_port->napi); | |
3325 | } | |
3326 | ||
3327 | pp->rxq_def = pp->indir[0]; | |
3328 | ||
3329 | /* Update unicast mapping */ | |
3330 | mvneta_set_rx_mode(pp->dev); | |
3331 | ||
3332 | /* Update val of portCfg register accordingly with all RxQueue types */ | |
3333 | val = MVNETA_PORT_CONFIG_DEFL_VALUE(pp->rxq_def); | |
3334 | mvreg_write(pp, MVNETA_PORT_CONFIG, val); | |
3335 | ||
3336 | /* Update the elected CPU matching the new rxq_def */ | |
3337 | mvneta_percpu_elect(pp); | |
3338 | ||
3339 | /* We have to synchronise on the napi of each CPU */ | |
3340 | for_each_online_cpu(cpu) { | |
3341 | struct mvneta_pcpu_port *pcpu_port = | |
3342 | per_cpu_ptr(pp->ports, cpu); | |
3343 | ||
3344 | napi_enable(&pcpu_port->napi); | |
3345 | } | |
3346 | ||
3347 | netif_tx_start_all_queues(pp->dev); | |
3348 | ||
3349 | return 0; | |
3350 | } | |
3351 | ||
3352 | static int mvneta_ethtool_set_rxfh(struct net_device *dev, const u32 *indir, | |
3353 | const u8 *key, const u8 hfunc) | |
3354 | { | |
3355 | struct mvneta_port *pp = netdev_priv(dev); | |
3356 | /* We require at least one supported parameter to be changed | |
3357 | * and no change in any of the unsupported parameters | |
3358 | */ | |
3359 | if (key || | |
3360 | (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)) | |
3361 | return -EOPNOTSUPP; | |
3362 | ||
3363 | if (!indir) | |
3364 | return 0; | |
3365 | ||
3366 | memcpy(pp->indir, indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3367 | ||
3368 | return mvneta_config_rss(pp); | |
3369 | } | |
3370 | ||
3371 | static int mvneta_ethtool_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, | |
3372 | u8 *hfunc) | |
3373 | { | |
3374 | struct mvneta_port *pp = netdev_priv(dev); | |
3375 | ||
3376 | if (hfunc) | |
3377 | *hfunc = ETH_RSS_HASH_TOP; | |
3378 | ||
3379 | if (!indir) | |
3380 | return 0; | |
3381 | ||
3382 | memcpy(indir, pp->indir, MVNETA_RSS_LU_TABLE_SIZE); | |
3383 | ||
3384 | return 0; | |
3385 | } | |
3386 | ||
c5aff182 TP |
3387 | static const struct net_device_ops mvneta_netdev_ops = { |
3388 | .ndo_open = mvneta_open, | |
3389 | .ndo_stop = mvneta_stop, | |
3390 | .ndo_start_xmit = mvneta_tx, | |
3391 | .ndo_set_rx_mode = mvneta_set_rx_mode, | |
3392 | .ndo_set_mac_address = mvneta_set_mac_addr, | |
3393 | .ndo_change_mtu = mvneta_change_mtu, | |
b65657fc | 3394 | .ndo_fix_features = mvneta_fix_features, |
c5aff182 | 3395 | .ndo_get_stats64 = mvneta_get_stats64, |
15f59456 | 3396 | .ndo_do_ioctl = mvneta_ioctl, |
c5aff182 TP |
3397 | }; |
3398 | ||
3399 | const struct ethtool_ops mvneta_eth_tool_ops = { | |
3400 | .get_link = ethtool_op_get_link, | |
3401 | .get_settings = mvneta_ethtool_get_settings, | |
3402 | .set_settings = mvneta_ethtool_set_settings, | |
3403 | .set_coalesce = mvneta_ethtool_set_coalesce, | |
3404 | .get_coalesce = mvneta_ethtool_get_coalesce, | |
3405 | .get_drvinfo = mvneta_ethtool_get_drvinfo, | |
3406 | .get_ringparam = mvneta_ethtool_get_ringparam, | |
3407 | .set_ringparam = mvneta_ethtool_set_ringparam, | |
9b0cdefa RK |
3408 | .get_strings = mvneta_ethtool_get_strings, |
3409 | .get_ethtool_stats = mvneta_ethtool_get_stats, | |
3410 | .get_sset_count = mvneta_ethtool_get_sset_count, | |
9a401dea GC |
3411 | .get_rxfh_indir_size = mvneta_ethtool_get_rxfh_indir_size, |
3412 | .get_rxnfc = mvneta_ethtool_get_rxnfc, | |
3413 | .get_rxfh = mvneta_ethtool_get_rxfh, | |
3414 | .set_rxfh = mvneta_ethtool_set_rxfh, | |
c5aff182 TP |
3415 | }; |
3416 | ||
3417 | /* Initialize hw */ | |
9672850b | 3418 | static int mvneta_init(struct device *dev, struct mvneta_port *pp) |
c5aff182 TP |
3419 | { |
3420 | int queue; | |
3421 | ||
3422 | /* Disable port */ | |
3423 | mvneta_port_disable(pp); | |
3424 | ||
3425 | /* Set port default values */ | |
3426 | mvneta_defaults_set(pp); | |
3427 | ||
9672850b EG |
3428 | pp->txqs = devm_kcalloc(dev, txq_number, sizeof(struct mvneta_tx_queue), |
3429 | GFP_KERNEL); | |
c5aff182 TP |
3430 | if (!pp->txqs) |
3431 | return -ENOMEM; | |
3432 | ||
3433 | /* Initialize TX descriptor rings */ | |
3434 | for (queue = 0; queue < txq_number; queue++) { | |
3435 | struct mvneta_tx_queue *txq = &pp->txqs[queue]; | |
3436 | txq->id = queue; | |
3437 | txq->size = pp->tx_ring_size; | |
3438 | txq->done_pkts_coal = MVNETA_TXDONE_COAL_PKTS; | |
3439 | } | |
3440 | ||
9672850b EG |
3441 | pp->rxqs = devm_kcalloc(dev, rxq_number, sizeof(struct mvneta_rx_queue), |
3442 | GFP_KERNEL); | |
3443 | if (!pp->rxqs) | |
c5aff182 | 3444 | return -ENOMEM; |
c5aff182 TP |
3445 | |
3446 | /* Create Rx descriptor rings */ | |
3447 | for (queue = 0; queue < rxq_number; queue++) { | |
3448 | struct mvneta_rx_queue *rxq = &pp->rxqs[queue]; | |
3449 | rxq->id = queue; | |
3450 | rxq->size = pp->rx_ring_size; | |
3451 | rxq->pkts_coal = MVNETA_RX_COAL_PKTS; | |
3452 | rxq->time_coal = MVNETA_RX_COAL_USEC; | |
3453 | } | |
3454 | ||
3455 | return 0; | |
3456 | } | |
3457 | ||
c5aff182 | 3458 | /* platform glue : initialize decoding windows */ |
03ce758e GK |
3459 | static void mvneta_conf_mbus_windows(struct mvneta_port *pp, |
3460 | const struct mbus_dram_target_info *dram) | |
c5aff182 TP |
3461 | { |
3462 | u32 win_enable; | |
3463 | u32 win_protect; | |
3464 | int i; | |
3465 | ||
3466 | for (i = 0; i < 6; i++) { | |
3467 | mvreg_write(pp, MVNETA_WIN_BASE(i), 0); | |
3468 | mvreg_write(pp, MVNETA_WIN_SIZE(i), 0); | |
3469 | ||
3470 | if (i < 4) | |
3471 | mvreg_write(pp, MVNETA_WIN_REMAP(i), 0); | |
3472 | } | |
3473 | ||
3474 | win_enable = 0x3f; | |
3475 | win_protect = 0; | |
3476 | ||
3477 | for (i = 0; i < dram->num_cs; i++) { | |
3478 | const struct mbus_dram_window *cs = dram->cs + i; | |
3479 | mvreg_write(pp, MVNETA_WIN_BASE(i), (cs->base & 0xffff0000) | | |
3480 | (cs->mbus_attr << 8) | dram->mbus_dram_target_id); | |
3481 | ||
3482 | mvreg_write(pp, MVNETA_WIN_SIZE(i), | |
3483 | (cs->size - 1) & 0xffff0000); | |
3484 | ||
3485 | win_enable &= ~(1 << i); | |
3486 | win_protect |= 3 << (2 * i); | |
3487 | } | |
3488 | ||
3489 | mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable); | |
db6ba9a5 | 3490 | mvreg_write(pp, MVNETA_ACCESS_PROTECT_ENABLE, win_protect); |
c5aff182 TP |
3491 | } |
3492 | ||
3493 | /* Power up the port */ | |
3f1dd4bc | 3494 | static int mvneta_port_power_up(struct mvneta_port *pp, int phy_mode) |
c5aff182 | 3495 | { |
3f1dd4bc | 3496 | u32 ctrl; |
c5aff182 TP |
3497 | |
3498 | /* MAC Cause register should be cleared */ | |
3499 | mvreg_write(pp, MVNETA_UNIT_INTR_CAUSE, 0); | |
3500 | ||
3f1dd4bc | 3501 | ctrl = mvreg_read(pp, MVNETA_GMAC_CTRL_2); |
c5aff182 | 3502 | |
3f1dd4bc TP |
3503 | /* Even though it might look weird, when we're configured in |
3504 | * SGMII or QSGMII mode, the RGMII bit needs to be set. | |
3505 | */ | |
3506 | switch(phy_mode) { | |
3507 | case PHY_INTERFACE_MODE_QSGMII: | |
3508 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_QSGMII_SERDES_PROTO); | |
3509 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
3510 | break; | |
3511 | case PHY_INTERFACE_MODE_SGMII: | |
3512 | mvreg_write(pp, MVNETA_SERDES_CFG, MVNETA_SGMII_SERDES_PROTO); | |
3513 | ctrl |= MVNETA_GMAC2_PCS_ENABLE | MVNETA_GMAC2_PORT_RGMII; | |
3514 | break; | |
3515 | case PHY_INTERFACE_MODE_RGMII: | |
3516 | case PHY_INTERFACE_MODE_RGMII_ID: | |
3517 | ctrl |= MVNETA_GMAC2_PORT_RGMII; | |
3518 | break; | |
3519 | default: | |
3520 | return -EINVAL; | |
3521 | } | |
c5aff182 TP |
3522 | |
3523 | /* Cancel Port Reset */ | |
3f1dd4bc TP |
3524 | ctrl &= ~MVNETA_GMAC2_PORT_RESET; |
3525 | mvreg_write(pp, MVNETA_GMAC_CTRL_2, ctrl); | |
c5aff182 TP |
3526 | |
3527 | while ((mvreg_read(pp, MVNETA_GMAC_CTRL_2) & | |
3528 | MVNETA_GMAC2_PORT_RESET) != 0) | |
3529 | continue; | |
3f1dd4bc TP |
3530 | |
3531 | return 0; | |
c5aff182 TP |
3532 | } |
3533 | ||
3534 | /* Device initialization routine */ | |
03ce758e | 3535 | static int mvneta_probe(struct platform_device *pdev) |
c5aff182 TP |
3536 | { |
3537 | const struct mbus_dram_target_info *dram_target_info; | |
c3f0dd38 | 3538 | struct resource *res; |
c5aff182 TP |
3539 | struct device_node *dn = pdev->dev.of_node; |
3540 | struct device_node *phy_node; | |
c5aff182 TP |
3541 | struct mvneta_port *pp; |
3542 | struct net_device *dev; | |
8cc3e439 TP |
3543 | const char *dt_mac_addr; |
3544 | char hw_mac_addr[ETH_ALEN]; | |
3545 | const char *mac_from; | |
f8af8e6e | 3546 | const char *managed; |
9110ee07 | 3547 | int tx_csum_limit; |
c5aff182 TP |
3548 | int phy_mode; |
3549 | int err; | |
12bb03b4 | 3550 | int cpu; |
c5aff182 | 3551 | |
ee40a116 | 3552 | dev = alloc_etherdev_mqs(sizeof(struct mvneta_port), txq_number, rxq_number); |
c5aff182 TP |
3553 | if (!dev) |
3554 | return -ENOMEM; | |
3555 | ||
3556 | dev->irq = irq_of_parse_and_map(dn, 0); | |
3557 | if (dev->irq == 0) { | |
3558 | err = -EINVAL; | |
3559 | goto err_free_netdev; | |
3560 | } | |
3561 | ||
3562 | phy_node = of_parse_phandle(dn, "phy", 0); | |
3563 | if (!phy_node) { | |
83895bed TP |
3564 | if (!of_phy_is_fixed_link(dn)) { |
3565 | dev_err(&pdev->dev, "no PHY specified\n"); | |
3566 | err = -ENODEV; | |
3567 | goto err_free_irq; | |
3568 | } | |
3569 | ||
3570 | err = of_phy_register_fixed_link(dn); | |
3571 | if (err < 0) { | |
3572 | dev_err(&pdev->dev, "cannot register fixed PHY\n"); | |
3573 | goto err_free_irq; | |
3574 | } | |
3575 | ||
3576 | /* In the case of a fixed PHY, the DT node associated | |
3577 | * to the PHY is the Ethernet MAC DT node. | |
3578 | */ | |
c891c24c | 3579 | phy_node = of_node_get(dn); |
c5aff182 TP |
3580 | } |
3581 | ||
3582 | phy_mode = of_get_phy_mode(dn); | |
3583 | if (phy_mode < 0) { | |
3584 | dev_err(&pdev->dev, "incorrect phy-mode\n"); | |
3585 | err = -EINVAL; | |
c891c24c | 3586 | goto err_put_phy_node; |
c5aff182 TP |
3587 | } |
3588 | ||
c5aff182 TP |
3589 | dev->tx_queue_len = MVNETA_MAX_TXD; |
3590 | dev->watchdog_timeo = 5 * HZ; | |
3591 | dev->netdev_ops = &mvneta_netdev_ops; | |
3592 | ||
7ad24ea4 | 3593 | dev->ethtool_ops = &mvneta_eth_tool_ops; |
c5aff182 TP |
3594 | |
3595 | pp = netdev_priv(dev); | |
c5aff182 TP |
3596 | pp->phy_node = phy_node; |
3597 | pp->phy_interface = phy_mode; | |
f8af8e6e SS |
3598 | |
3599 | err = of_property_read_string(dn, "managed", &managed); | |
3600 | pp->use_inband_status = (err == 0 && | |
3601 | strcmp(managed, "in-band-status") == 0); | |
f8642885 | 3602 | pp->cpu_notifier.notifier_call = mvneta_percpu_notifier; |
c5aff182 | 3603 | |
90b74c01 GC |
3604 | pp->rxq_def = rxq_def; |
3605 | ||
9a401dea GC |
3606 | pp->indir[0] = rxq_def; |
3607 | ||
189dd626 TP |
3608 | pp->clk = devm_clk_get(&pdev->dev, NULL); |
3609 | if (IS_ERR(pp->clk)) { | |
3610 | err = PTR_ERR(pp->clk); | |
c891c24c | 3611 | goto err_put_phy_node; |
189dd626 TP |
3612 | } |
3613 | ||
3614 | clk_prepare_enable(pp->clk); | |
3615 | ||
c3f0dd38 TP |
3616 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
3617 | pp->base = devm_ioremap_resource(&pdev->dev, res); | |
3618 | if (IS_ERR(pp->base)) { | |
3619 | err = PTR_ERR(pp->base); | |
5445eaf3 APR |
3620 | goto err_clk; |
3621 | } | |
3622 | ||
12bb03b4 MR |
3623 | /* Alloc per-cpu port structure */ |
3624 | pp->ports = alloc_percpu(struct mvneta_pcpu_port); | |
3625 | if (!pp->ports) { | |
3626 | err = -ENOMEM; | |
3627 | goto err_clk; | |
3628 | } | |
3629 | ||
74c41b04 | 3630 | /* Alloc per-cpu stats */ |
1c213bd2 | 3631 | pp->stats = netdev_alloc_pcpu_stats(struct mvneta_pcpu_stats); |
74c41b04 | 3632 | if (!pp->stats) { |
3633 | err = -ENOMEM; | |
12bb03b4 | 3634 | goto err_free_ports; |
74c41b04 | 3635 | } |
3636 | ||
8cc3e439 | 3637 | dt_mac_addr = of_get_mac_address(dn); |
6c7a9a3c | 3638 | if (dt_mac_addr) { |
8cc3e439 TP |
3639 | mac_from = "device tree"; |
3640 | memcpy(dev->dev_addr, dt_mac_addr, ETH_ALEN); | |
3641 | } else { | |
3642 | mvneta_get_mac_addr(pp, hw_mac_addr); | |
3643 | if (is_valid_ether_addr(hw_mac_addr)) { | |
3644 | mac_from = "hardware"; | |
3645 | memcpy(dev->dev_addr, hw_mac_addr, ETH_ALEN); | |
3646 | } else { | |
3647 | mac_from = "random"; | |
3648 | eth_hw_addr_random(dev); | |
3649 | } | |
3650 | } | |
3651 | ||
9110ee07 MW |
3652 | if (!of_property_read_u32(dn, "tx-csum-limit", &tx_csum_limit)) { |
3653 | if (tx_csum_limit < 0 || | |
3654 | tx_csum_limit > MVNETA_TX_CSUM_MAX_SIZE) { | |
3655 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
3656 | dev_info(&pdev->dev, | |
3657 | "Wrong TX csum limit in DT, set to %dB\n", | |
3658 | MVNETA_TX_CSUM_DEF_SIZE); | |
3659 | } | |
3660 | } else if (of_device_is_compatible(dn, "marvell,armada-370-neta")) { | |
3661 | tx_csum_limit = MVNETA_TX_CSUM_DEF_SIZE; | |
3662 | } else { | |
3663 | tx_csum_limit = MVNETA_TX_CSUM_MAX_SIZE; | |
3664 | } | |
3665 | ||
3666 | pp->tx_csum_limit = tx_csum_limit; | |
b65657fc | 3667 | |
c5aff182 TP |
3668 | pp->tx_ring_size = MVNETA_MAX_TXD; |
3669 | pp->rx_ring_size = MVNETA_MAX_RXD; | |
3670 | ||
3671 | pp->dev = dev; | |
3672 | SET_NETDEV_DEV(dev, &pdev->dev); | |
3673 | ||
9672850b EG |
3674 | err = mvneta_init(&pdev->dev, pp); |
3675 | if (err < 0) | |
74c41b04 | 3676 | goto err_free_stats; |
3f1dd4bc TP |
3677 | |
3678 | err = mvneta_port_power_up(pp, phy_mode); | |
3679 | if (err < 0) { | |
3680 | dev_err(&pdev->dev, "can't power up port\n"); | |
9672850b | 3681 | goto err_free_stats; |
3f1dd4bc | 3682 | } |
c5aff182 TP |
3683 | |
3684 | dram_target_info = mv_mbus_dram_info(); | |
3685 | if (dram_target_info) | |
3686 | mvneta_conf_mbus_windows(pp, dram_target_info); | |
3687 | ||
12bb03b4 MR |
3688 | for_each_present_cpu(cpu) { |
3689 | struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu); | |
3690 | ||
3691 | netif_napi_add(dev, &port->napi, mvneta_poll, NAPI_POLL_WEIGHT); | |
3692 | port->pp = pp; | |
3693 | } | |
c5aff182 | 3694 | |
2adb719d | 3695 | dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO; |
01ef26ca EG |
3696 | dev->hw_features |= dev->features; |
3697 | dev->vlan_features |= dev->features; | |
b50b72de | 3698 | dev->priv_flags |= IFF_UNICAST_FLT; |
8eef5f97 | 3699 | dev->gso_max_segs = MVNETA_MAX_TSO_SEGS; |
b50b72de | 3700 | |
c5aff182 TP |
3701 | err = register_netdev(dev); |
3702 | if (err < 0) { | |
3703 | dev_err(&pdev->dev, "failed to register\n"); | |
9672850b | 3704 | goto err_free_stats; |
c5aff182 TP |
3705 | } |
3706 | ||
8cc3e439 TP |
3707 | netdev_info(dev, "Using %s mac address %pM\n", mac_from, |
3708 | dev->dev_addr); | |
c5aff182 TP |
3709 | |
3710 | platform_set_drvdata(pdev, pp->dev); | |
3711 | ||
898b2970 SS |
3712 | if (pp->use_inband_status) { |
3713 | struct phy_device *phy = of_phy_find_device(dn); | |
3714 | ||
3715 | mvneta_fixed_link_update(pp, phy); | |
04d53b20 RK |
3716 | |
3717 | put_device(&phy->dev); | |
898b2970 SS |
3718 | } |
3719 | ||
c5aff182 TP |
3720 | return 0; |
3721 | ||
74c41b04 | 3722 | err_free_stats: |
3723 | free_percpu(pp->stats); | |
12bb03b4 MR |
3724 | err_free_ports: |
3725 | free_percpu(pp->ports); | |
5445eaf3 APR |
3726 | err_clk: |
3727 | clk_disable_unprepare(pp->clk); | |
c891c24c UKK |
3728 | err_put_phy_node: |
3729 | of_node_put(phy_node); | |
c5aff182 TP |
3730 | err_free_irq: |
3731 | irq_dispose_mapping(dev->irq); | |
3732 | err_free_netdev: | |
3733 | free_netdev(dev); | |
3734 | return err; | |
3735 | } | |
3736 | ||
3737 | /* Device removal routine */ | |
03ce758e | 3738 | static int mvneta_remove(struct platform_device *pdev) |
c5aff182 TP |
3739 | { |
3740 | struct net_device *dev = platform_get_drvdata(pdev); | |
3741 | struct mvneta_port *pp = netdev_priv(dev); | |
3742 | ||
3743 | unregister_netdev(dev); | |
189dd626 | 3744 | clk_disable_unprepare(pp->clk); |
12bb03b4 | 3745 | free_percpu(pp->ports); |
74c41b04 | 3746 | free_percpu(pp->stats); |
c5aff182 | 3747 | irq_dispose_mapping(dev->irq); |
c891c24c | 3748 | of_node_put(pp->phy_node); |
c5aff182 TP |
3749 | free_netdev(dev); |
3750 | ||
c5aff182 TP |
3751 | return 0; |
3752 | } | |
3753 | ||
3754 | static const struct of_device_id mvneta_match[] = { | |
3755 | { .compatible = "marvell,armada-370-neta" }, | |
f522a975 | 3756 | { .compatible = "marvell,armada-xp-neta" }, |
c5aff182 TP |
3757 | { } |
3758 | }; | |
3759 | MODULE_DEVICE_TABLE(of, mvneta_match); | |
3760 | ||
3761 | static struct platform_driver mvneta_driver = { | |
3762 | .probe = mvneta_probe, | |
03ce758e | 3763 | .remove = mvneta_remove, |
c5aff182 TP |
3764 | .driver = { |
3765 | .name = MVNETA_DRIVER_NAME, | |
3766 | .of_match_table = mvneta_match, | |
3767 | }, | |
3768 | }; | |
3769 | ||
3770 | module_platform_driver(mvneta_driver); | |
3771 | ||
3772 | MODULE_DESCRIPTION("Marvell NETA Ethernet Driver - www.marvell.com"); | |
3773 | MODULE_AUTHOR("Rami Rosen <rosenr@marvell.com>, Thomas Petazzoni <thomas.petazzoni@free-electrons.com>"); | |
3774 | MODULE_LICENSE("GPL"); | |
3775 | ||
3776 | module_param(rxq_number, int, S_IRUGO); | |
3777 | module_param(txq_number, int, S_IRUGO); | |
3778 | ||
3779 | module_param(rxq_def, int, S_IRUGO); | |
f19fadfc | 3780 | module_param(rx_copybreak, int, S_IRUGO | S_IWUSR); |