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net: pxa168_eth: fix Ethernet flow control status
[deliverable/linux.git] / drivers / net / ethernet / marvell / pxa168_eth.c
CommitLineData
a49f37ee
SS		 1/*
2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
4 *
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
10206601 7 * Zhangfei Gao <zgao6@marvell.com>
a49f37ee
SS		 8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
0ab75ae8 22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
a49f37ee
SS		 23 */
24
a49f37ee 25#include <linux/bitops.h>
307f6565 26#include <linux/clk.h>
a49f37ee 27#include <linux/delay.h>
307f6565
AT		 28#include <linux/dma-mapping.h>
29#include <linux/etherdevice.h>
a49f37ee 30#include <linux/ethtool.h>
307f6565
AT		 31#include <linux/in.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/ip.h>
a49f37ee 35#include <linux/kernel.h>
307f6565
AT		 36#include <linux/module.h>
37#include <linux/of.h>
a49f37ee 38#include <linux/phy.h>
307f6565
AT		 39#include <linux/platform_device.h>
40#include <linux/pxa168_eth.h>
41#include <linux/tcp.h>
a49f37ee 42#include <linux/types.h>
307f6565
AT		 43#include <linux/udp.h>
44#include <linux/workqueue.h>
45
a49f37ee 46#include <asm/pgtable.h>
a49f37ee 47#include <asm/cacheflush.h>
a49f37ee
SS		 48
49#define DRIVER_NAME "pxa168-eth"
50#define DRIVER_VERSION "0.3"
51
52/*
53 * Registers
54 */
55
56#define PHY_ADDRESS 0x0000
57#define SMI 0x0010
58#define PORT_CONFIG 0x0400
59#define PORT_CONFIG_EXT 0x0408
60#define PORT_COMMAND 0x0410
61#define PORT_STATUS 0x0418
62#define HTPR 0x0428
63#define SDMA_CONFIG 0x0440
64#define SDMA_CMD 0x0448
65#define INT_CAUSE 0x0450
66#define INT_W_CLEAR 0x0454
67#define INT_MASK 0x0458
68#define ETH_F_RX_DESC_0 0x0480
69#define ETH_C_RX_DESC_0 0x04A0
70#define ETH_C_TX_DESC_1 0x04E4
71
72/* smi register */
73#define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
74#define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
75#define SMI_OP_W (0 << 26) /* Write operation */
76#define SMI_OP_R (1 << 26) /* Read operation */
77
78#define PHY_WAIT_ITERATIONS 10
79
80#define PXA168_ETH_PHY_ADDR_DEFAULT 0
81/* RX & TX descriptor command */
82#define BUF_OWNED_BY_DMA (1 << 31)
83
84/* RX descriptor status */
85#define RX_EN_INT (1 << 23)
86#define RX_FIRST_DESC (1 << 17)
87#define RX_LAST_DESC (1 << 16)
88#define RX_ERROR (1 << 15)
89
90/* TX descriptor command */
91#define TX_EN_INT (1 << 23)
92#define TX_GEN_CRC (1 << 22)
93#define TX_ZERO_PADDING (1 << 18)
94#define TX_FIRST_DESC (1 << 17)
95#define TX_LAST_DESC (1 << 16)
96#define TX_ERROR (1 << 15)
97
98/* SDMA_CMD */
99#define SDMA_CMD_AT (1 << 31)
100#define SDMA_CMD_TXDL (1 << 24)
101#define SDMA_CMD_TXDH (1 << 23)
102#define SDMA_CMD_AR (1 << 15)
103#define SDMA_CMD_ERD (1 << 7)
104
105/* Bit definitions of the Port Config Reg */
106#define PCR_HS (1 << 12)
107#define PCR_EN (1 << 7)
108#define PCR_PM (1 << 0)
109
110/* Bit definitions of the Port Config Extend Reg */
111#define PCXR_2BSM (1 << 28)
112#define PCXR_DSCP_EN (1 << 21)
113#define PCXR_MFL_1518 (0 << 14)
114#define PCXR_MFL_1536 (1 << 14)
115#define PCXR_MFL_2048 (2 << 14)
116#define PCXR_MFL_64K (3 << 14)
117#define PCXR_FLP (1 << 11)
118#define PCXR_PRIO_TX_OFF 3
119#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
120
121/* Bit definitions of the SDMA Config Reg */
122#define SDCR_BSZ_OFF 12
123#define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
124#define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
125#define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
126#define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
127#define SDCR_BLMR (1 << 6)
128#define SDCR_BLMT (1 << 7)
129#define SDCR_RIFB (1 << 9)
130#define SDCR_RC_OFF 2
131#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
132
133/*
134 * Bit definitions of the Interrupt Cause Reg
135 * and Interrupt MASK Reg is the same
136 */
137#define ICR_RXBUF (1 << 0)
138#define ICR_TXBUF_H (1 << 2)
139#define ICR_TXBUF_L (1 << 3)
140#define ICR_TXEND_H (1 << 6)
141#define ICR_TXEND_L (1 << 7)
142#define ICR_RXERR (1 << 8)
143#define ICR_TXERR_H (1 << 10)
144#define ICR_TXERR_L (1 << 11)
145#define ICR_TX_UDR (1 << 13)
146#define ICR_MII_CH (1 << 28)
147
148#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
149 ICR_TXERR_H | ICR_TXERR_L |\
150 ICR_TXEND_H | ICR_TXEND_L |\
151 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
152
153#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
154
155#define NUM_RX_DESCS 64
156#define NUM_TX_DESCS 64
157
158#define HASH_ADD 0
159#define HASH_DELETE 1
160#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
161#define HOP_NUMBER 12
162
163/* Bit definitions for Port status */
164#define PORT_SPEED_100 (1 << 0)
165#define FULL_DUPLEX (1 << 1)
09f5da1b 166#define FLOW_CONTROL_DISABLED (1 << 2)
a49f37ee
SS		 167#define LINK_UP (1 << 3)
168
169/* Bit definitions for work to be done */
170#define WORK_LINK (1 << 0)
171#define WORK_TX_DONE (1 << 1)
172
173/*
174 * Misc definitions.
175 */
176#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
177
178struct rx_desc {
179 u32 cmd_sts; /* Descriptor command status */
180 u16 byte_cnt; /* Descriptor buffer byte count */
181 u16 buf_size; /* Buffer size */
182 u32 buf_ptr; /* Descriptor buffer pointer */
183 u32 next_desc_ptr; /* Next descriptor pointer */
184};
185
186struct tx_desc {
187 u32 cmd_sts; /* Command/status field */
188 u16 reserved;
189 u16 byte_cnt; /* buffer byte count */
190 u32 buf_ptr; /* pointer to buffer for this descriptor */
191 u32 next_desc_ptr; /* Pointer to next descriptor */
192};
193
194struct pxa168_eth_private {
195 int port_num; /* User Ethernet port number */
43d3ddf8 196 int phy_addr;
a49f37ee
SS		 197
198 int rx_resource_err; /* Rx ring resource error flag */
199
200 /* Next available and first returning Rx resource */
201 int rx_curr_desc_q, rx_used_desc_q;
202
203 /* Next available and first returning Tx resource */
204 int tx_curr_desc_q, tx_used_desc_q;
205
206 struct rx_desc *p_rx_desc_area;
207 dma_addr_t rx_desc_dma;
208 int rx_desc_area_size;
209 struct sk_buff **rx_skb;
210
211 struct tx_desc *p_tx_desc_area;
212 dma_addr_t tx_desc_dma;
213 int tx_desc_area_size;
214 struct sk_buff **tx_skb;
215
216 struct work_struct tx_timeout_task;
217
218 struct net_device *dev;
219 struct napi_struct napi;
220 u8 work_todo;
221 int skb_size;
222
a49f37ee
SS		 223 /* Size of Tx Ring per queue */
224 int tx_ring_size;
225 /* Number of tx descriptors in use */
226 int tx_desc_count;
227 /* Size of Rx Ring per queue */
228 int rx_ring_size;
229 /* Number of rx descriptors in use */
230 int rx_desc_count;
231
232 /*
233 * Used in case RX Ring is empty, which can occur when
234 * system does not have resources (skb's)
235 */
236 struct timer_list timeout;
237 struct mii_bus *smi_bus;
238 struct phy_device *phy;
239
240 /* clock */
241 struct clk *clk;
242 struct pxa168_eth_platform_data *pd;
243 /*
244 * Ethernet controller base address.
245 */
246 void __iomem *base;
247
248 /* Pointer to the hardware address filter table */
249 void *htpr;
250 dma_addr_t htpr_dma;
251};
252
253struct addr_table_entry {
254 __le32 lo;
255 __le32 hi;
256};
257
258/* Bit fields of a Hash Table Entry */
259enum hash_table_entry {
260 HASH_ENTRY_VALID = 1,
261 SKIP = 2,
262 HASH_ENTRY_RECEIVE_DISCARD = 4,
263 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
264};
265
266static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
267static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
268static int pxa168_init_hw(struct pxa168_eth_private *pep);
269static void eth_port_reset(struct net_device *dev);
270static void eth_port_start(struct net_device *dev);
271static int pxa168_eth_open(struct net_device *dev);
272static int pxa168_eth_stop(struct net_device *dev);
273static int ethernet_phy_setup(struct net_device *dev);
274
275static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
276{
277 return readl(pep->base + offset);
278}
279
280static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
281{
282 writel(data, pep->base + offset);
283}
284
285static void abort_dma(struct pxa168_eth_private *pep)
286{
287 int delay;
288 int max_retries = 40;
289
290 do {
291 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
292 udelay(100);
293
294 delay = 10;
295 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
296 && delay-- > 0) {
297 udelay(10);
298 }
299 } while (max_retries-- > 0 && delay <= 0);
300
301 if (max_retries <= 0)
307f6565 302 netdev_err(pep->dev, "%s : DMA Stuck\n", __func__);
a49f37ee
SS		 303}
304
305static int ethernet_phy_get(struct pxa168_eth_private *pep)
306{
307 unsigned int reg_data;
308
309 reg_data = rdl(pep, PHY_ADDRESS);
310
311 return (reg_data >> (5 * pep->port_num)) & 0x1f;
312}
313
314static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
315{
316 u32 reg_data;
317 int addr_shift = 5 * pep->port_num;
318
319 reg_data = rdl(pep, PHY_ADDRESS);
320 reg_data &= ~(0x1f << addr_shift);
321 reg_data |= (phy_addr & 0x1f) << addr_shift;
322 wrl(pep, PHY_ADDRESS, reg_data);
323}
324
a49f37ee
SS		 325static void rxq_refill(struct net_device *dev)
326{
327 struct pxa168_eth_private *pep = netdev_priv(dev);
328 struct sk_buff *skb;
329 struct rx_desc *p_used_rx_desc;
330 int used_rx_desc;
331
332 while (pep->rx_desc_count < pep->rx_ring_size) {
333 int size;
334
c056b734 335 skb = netdev_alloc_skb(dev, pep->skb_size);
a49f37ee
SS		 336 if (!skb)
337 break;
338 if (SKB_DMA_REALIGN)
339 skb_reserve(skb, SKB_DMA_REALIGN);
340 pep->rx_desc_count++;
341 /* Get 'used' Rx descriptor */
342 used_rx_desc = pep->rx_used_desc_q;
343 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
511efbbb 344 size = skb_end_pointer(skb) - skb->data;
a49f37ee
SS		 345 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
346 skb->data,
347 size,
348 DMA_FROM_DEVICE);
349 p_used_rx_desc->buf_size = size;
350 pep->rx_skb[used_rx_desc] = skb;
351
352 /* Return the descriptor to DMA ownership */
353 wmb();
354 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
355 wmb();
356
357 /* Move the used descriptor pointer to the next descriptor */
358 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
359
360 /* Any Rx return cancels the Rx resource error status */
361 pep->rx_resource_err = 0;
362
363 skb_reserve(skb, ETH_HW_IP_ALIGN);
364 }
365
366 /*
367 * If RX ring is empty of SKB, set a timer to try allocating
368 * again at a later time.
369 */
370 if (pep->rx_desc_count == 0) {
371 pep->timeout.expires = jiffies + (HZ / 10);
372 add_timer(&pep->timeout);
373 }
374}
375
376static inline void rxq_refill_timer_wrapper(unsigned long data)
377{
378 struct pxa168_eth_private *pep = (void *)data;
379 napi_schedule(&pep->napi);
380}
381
382static inline u8 flip_8_bits(u8 x)
383{
384 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
385 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
386 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
387 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
388}
389
390static void nibble_swap_every_byte(unsigned char *mac_addr)
391{
392 int i;
393 for (i = 0; i < ETH_ALEN; i++) {
394 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
395 ((mac_addr[i] & 0xf0) >> 4);
396 }
397}
398
399static void inverse_every_nibble(unsigned char *mac_addr)
400{
401 int i;
402 for (i = 0; i < ETH_ALEN; i++)
403 mac_addr[i] = flip_8_bits(mac_addr[i]);
404}
405
406/*
407 * ----------------------------------------------------------------------------
408 * This function will calculate the hash function of the address.
409 * Inputs
410 * mac_addr_orig - MAC address.
411 * Outputs
412 * return the calculated entry.
413 */
414static u32 hash_function(unsigned char *mac_addr_orig)
415{
416 u32 hash_result;
417 u32 addr0;
418 u32 addr1;
419 u32 addr2;
420 u32 addr3;
421 unsigned char mac_addr[ETH_ALEN];
422
423 /* Make a copy of MAC address since we are going to performe bit
424 * operations on it
425 */
426 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
427
428 nibble_swap_every_byte(mac_addr);
429 inverse_every_nibble(mac_addr);
430
431 addr0 = (mac_addr[5] >> 2) & 0x3f;
432 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
433 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
434 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
435
436 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
437 hash_result = hash_result & 0x07ff;
438 return hash_result;
439}
440
441/*
442 * ----------------------------------------------------------------------------
443 * This function will add/del an entry to the address table.
444 * Inputs
445 * pep - ETHERNET .
446 * mac_addr - MAC address.
447 * skip - if 1, skip this address.Used in case of deleting an entry which is a
25985edc 448 * part of chain in the hash table.We can't just delete the entry since
a49f37ee
SS		 449 * that will break the chain.We need to defragment the tables time to
450 * time.
451 * rd - 0 Discard packet upon match.
452 * - 1 Receive packet upon match.
453 * Outputs
454 * address table entry is added/deleted.
455 * 0 if success.
456 * -ENOSPC if table full
457 */
458static int add_del_hash_entry(struct pxa168_eth_private *pep,
459 unsigned char *mac_addr,
460 u32 rd, u32 skip, int del)
461{
462 struct addr_table_entry *entry, *start;
463 u32 new_high;
464 u32 new_low;
465 u32 i;
466
467 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
468 | (((mac_addr[1] >> 0) & 0xf) << 11)
469 | (((mac_addr[0] >> 4) & 0xf) << 7)
470 | (((mac_addr[0] >> 0) & 0xf) << 3)
471 | (((mac_addr[3] >> 4) & 0x1) << 31)
472 | (((mac_addr[3] >> 0) & 0xf) << 27)
473 | (((mac_addr[2] >> 4) & 0xf) << 23)
474 | (((mac_addr[2] >> 0) & 0xf) << 19)
475 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
476 | HASH_ENTRY_VALID;
477
478 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
479 | (((mac_addr[5] >> 0) & 0xf) << 11)
480 | (((mac_addr[4] >> 4) & 0xf) << 7)
481 | (((mac_addr[4] >> 0) & 0xf) << 3)
482 | (((mac_addr[3] >> 5) & 0x7) << 0);
483
484 /*
485 * Pick the appropriate table, start scanning for free/reusable
486 * entries at the index obtained by hashing the specified MAC address
487 */
43d620c8 488 start = pep->htpr;
a49f37ee
SS		 489 entry = start + hash_function(mac_addr);
490 for (i = 0; i < HOP_NUMBER; i++) {
491 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
492 break;
493 } else {
494 /* if same address put in same position */
495 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
496 (new_low & 0xfffffff8)) &&
497 (le32_to_cpu(entry->hi) == new_high)) {
498 break;
499 }
500 }
501 if (entry == start + 0x7ff)
502 entry = start;
503 else
504 entry++;
505 }
506
507 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
508 (le32_to_cpu(entry->hi) != new_high) && del)
509 return 0;
510
511 if (i == HOP_NUMBER) {
512 if (!del) {
307f6565
AT		 513 netdev_info(pep->dev,
514 "%s: table section is full, need to "
515 "move to 16kB implementation?\n",
516 __FILE__);
a49f37ee
SS		 517 return -ENOSPC;
518 } else
519 return 0;
520 }
521
522 /*
523 * Update the selected entry
524 */
525 if (del) {
526 entry->hi = 0;
527 entry->lo = 0;
528 } else {
529 entry->hi = cpu_to_le32(new_high);
530 entry->lo = cpu_to_le32(new_low);
531 }
532
533 return 0;
534}
535
536/*
537 * ----------------------------------------------------------------------------
538 * Create an addressTable entry from MAC address info
539 * found in the specifed net_device struct
540 *
541 * Input : pointer to ethernet interface network device structure
542 * Output : N/A
543 */
544static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
545 unsigned char *oaddr,
546 unsigned char *addr)
547{
548 /* Delete old entry */
549 if (oaddr)
550 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
551 /* Add new entry */
552 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
553}
554
555static int init_hash_table(struct pxa168_eth_private *pep)
556{
557 /*
558 * Hardware expects CPU to build a hash table based on a predefined
559 * hash function and populate it based on hardware address. The
560 * location of the hash table is identified by 32-bit pointer stored
561 * in HTPR internal register. Two possible sizes exists for the hash
562 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
563 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
564 * 1/2kB.
565 */
566 /* TODO: Add support for 8kB hash table and alternative hash
567 * function.Driver can dynamically switch to them if the 1/2kB hash
568 * table is full.
569 */
570 if (pep->htpr == NULL) {
ede23fa8
JP		 571 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent,
572 HASH_ADDR_TABLE_SIZE,
573 &pep->htpr_dma, GFP_KERNEL);
a49f37ee
SS		 574 if (pep->htpr == NULL)
575 return -ENOMEM;
1f9061d2
JP		 576 } else {
577 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
a49f37ee 578 }
a49f37ee
SS		 579 wrl(pep, HTPR, pep->htpr_dma);
580 return 0;
581}
582
583static void pxa168_eth_set_rx_mode(struct net_device *dev)
584{
585 struct pxa168_eth_private *pep = netdev_priv(dev);
586 struct netdev_hw_addr *ha;
587 u32 val;
588
589 val = rdl(pep, PORT_CONFIG);
590 if (dev->flags & IFF_PROMISC)
591 val |= PCR_PM;
592 else
593 val &= ~PCR_PM;
594 wrl(pep, PORT_CONFIG, val);
595
596 /*
597 * Remove the old list of MAC address and add dev->addr
598 * and multicast address.
599 */
600 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
601 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
602
603 netdev_for_each_mc_addr(ha, dev)
604 update_hash_table_mac_address(pep, NULL, ha->addr);
605}
606
607static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
608{
609 struct sockaddr *sa = addr;
610 struct pxa168_eth_private *pep = netdev_priv(dev);
611 unsigned char oldMac[ETH_ALEN];
612
613 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 614 return -EADDRNOTAVAIL;
a49f37ee
SS		 615 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
616 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
617 netif_addr_lock_bh(dev);
618 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
619 netif_addr_unlock_bh(dev);
620 return 0;
621}
622
623static void eth_port_start(struct net_device *dev)
624{
625 unsigned int val = 0;
626 struct pxa168_eth_private *pep = netdev_priv(dev);
627 int tx_curr_desc, rx_curr_desc;
628
629 /* Perform PHY reset, if there is a PHY. */
630 if (pep->phy != NULL) {
631 struct ethtool_cmd cmd;
632
633 pxa168_get_settings(pep->dev, &cmd);
78de53f0 634 phy_init_hw(pep->phy);
a49f37ee
SS		 635 pxa168_set_settings(pep->dev, &cmd);
636 }
637
638 /* Assignment of Tx CTRP of given queue */
639 tx_curr_desc = pep->tx_curr_desc_q;
640 wrl(pep, ETH_C_TX_DESC_1,
b2bc8563 641 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
a49f37ee
SS		 642
643 /* Assignment of Rx CRDP of given queue */
644 rx_curr_desc = pep->rx_curr_desc_q;
645 wrl(pep, ETH_C_RX_DESC_0,
b2bc8563 646 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 647
648 wrl(pep, ETH_F_RX_DESC_0,
b2bc8563 649 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 650
651 /* Clear all interrupts */
652 wrl(pep, INT_CAUSE, 0);
653
654 /* Enable all interrupts for receive, transmit and error. */
655 wrl(pep, INT_MASK, ALL_INTS);
656
657 val = rdl(pep, PORT_CONFIG);
658 val |= PCR_EN;
659 wrl(pep, PORT_CONFIG, val);
660
661 /* Start RX DMA engine */
662 val = rdl(pep, SDMA_CMD);
663 val |= SDMA_CMD_ERD;
664 wrl(pep, SDMA_CMD, val);
665}
666
667static void eth_port_reset(struct net_device *dev)
668{
669 struct pxa168_eth_private *pep = netdev_priv(dev);
670 unsigned int val = 0;
671
672 /* Stop all interrupts for receive, transmit and error. */
673 wrl(pep, INT_MASK, 0);
674
675 /* Clear all interrupts */
676 wrl(pep, INT_CAUSE, 0);
677
678 /* Stop RX DMA */
679 val = rdl(pep, SDMA_CMD);
680 val &= ~SDMA_CMD_ERD; /* abort dma command */
681
682 /* Abort any transmit and receive operations and put DMA
683 * in idle state.
684 */
685 abort_dma(pep);
686
687 /* Disable port */
688 val = rdl(pep, PORT_CONFIG);
689 val &= ~PCR_EN;
690 wrl(pep, PORT_CONFIG, val);
691}
692
693/*
694 * txq_reclaim - Free the tx desc data for completed descriptors
695 * If force is non-zero, frees uncompleted descriptors as well
696 */
697static int txq_reclaim(struct net_device *dev, int force)
698{
699 struct pxa168_eth_private *pep = netdev_priv(dev);
700 struct tx_desc *desc;
701 u32 cmd_sts;
702 struct sk_buff *skb;
703 int tx_index;
704 dma_addr_t addr;
705 int count;
706 int released = 0;
707
708 netif_tx_lock(dev);
709
710 pep->work_todo &= ~WORK_TX_DONE;
711 while (pep->tx_desc_count > 0) {
712 tx_index = pep->tx_used_desc_q;
713 desc = &pep->p_tx_desc_area[tx_index];
714 cmd_sts = desc->cmd_sts;
715 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
716 if (released > 0) {
717 goto txq_reclaim_end;
718 } else {
719 released = -1;
720 goto txq_reclaim_end;
721 }
722 }
723 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
724 pep->tx_desc_count--;
725 addr = desc->buf_ptr;
726 count = desc->byte_cnt;
727 skb = pep->tx_skb[tx_index];
728 if (skb)
729 pep->tx_skb[tx_index] = NULL;
730
731 if (cmd_sts & TX_ERROR) {
732 if (net_ratelimit())
307f6565 733 netdev_err(dev, "Error in TX\n");
a49f37ee
SS		 734 dev->stats.tx_errors++;
735 }
736 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
737 if (skb)
738 dev_kfree_skb_irq(skb);
739 released++;
740 }
741txq_reclaim_end:
742 netif_tx_unlock(dev);
743 return released;
744}
745
746static void pxa168_eth_tx_timeout(struct net_device *dev)
747{
748 struct pxa168_eth_private *pep = netdev_priv(dev);
749
307f6565 750 netdev_info(dev, "TX timeout desc_count %d\n", pep->tx_desc_count);
a49f37ee
SS		 751
752 schedule_work(&pep->tx_timeout_task);
753}
754
755static void pxa168_eth_tx_timeout_task(struct work_struct *work)
756{
757 struct pxa168_eth_private *pep = container_of(work,
758 struct pxa168_eth_private,
759 tx_timeout_task);
760 struct net_device *dev = pep->dev;
761 pxa168_eth_stop(dev);
762 pxa168_eth_open(dev);
763}
764
765static int rxq_process(struct net_device *dev, int budget)
766{
767 struct pxa168_eth_private *pep = netdev_priv(dev);
768 struct net_device_stats *stats = &dev->stats;
769 unsigned int received_packets = 0;
770 struct sk_buff *skb;
771
772 while (budget-- > 0) {
773 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
774 struct rx_desc *rx_desc;
775 unsigned int cmd_sts;
776
777 /* Do not process Rx ring in case of Rx ring resource error */
778 if (pep->rx_resource_err)
779 break;
780 rx_curr_desc = pep->rx_curr_desc_q;
781 rx_used_desc = pep->rx_used_desc_q;
782 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
783 cmd_sts = rx_desc->cmd_sts;
784 rmb();
785 if (cmd_sts & (BUF_OWNED_BY_DMA))
786 break;
787 skb = pep->rx_skb[rx_curr_desc];
788 pep->rx_skb[rx_curr_desc] = NULL;
789
790 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
791 pep->rx_curr_desc_q = rx_next_curr_desc;
792
793 /* Rx descriptors exhausted. */
794 /* Set the Rx ring resource error flag */
795 if (rx_next_curr_desc == rx_used_desc)
796 pep->rx_resource_err = 1;
797 pep->rx_desc_count--;
798 dma_unmap_single(NULL, rx_desc->buf_ptr,
799 rx_desc->buf_size,
800 DMA_FROM_DEVICE);
801 received_packets++;
802 /*
803 * Update statistics.
804 * Note byte count includes 4 byte CRC count
805 */
806 stats->rx_packets++;
807 stats->rx_bytes += rx_desc->byte_cnt;
808 /*
809 * In case received a packet without first / last bits on OR
810 * the error summary bit is on, the packets needs to be droped.
811 */
812 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
813 (RX_FIRST_DESC | RX_LAST_DESC))
814 || (cmd_sts & RX_ERROR)) {
815
816 stats->rx_dropped++;
817 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
818 (RX_FIRST_DESC | RX_LAST_DESC)) {
819 if (net_ratelimit())
307f6565
AT		 820 netdev_err(dev,
821 "Rx pkt on multiple desc\n");
a49f37ee
SS		 822 }
823 if (cmd_sts & RX_ERROR)
824 stats->rx_errors++;
825 dev_kfree_skb_irq(skb);
826 } else {
827 /*
828 * The -4 is for the CRC in the trailer of the
829 * received packet
830 */
831 skb_put(skb, rx_desc->byte_cnt - 4);
832 skb->protocol = eth_type_trans(skb, dev);
833 netif_receive_skb(skb);
834 }
a49f37ee
SS		 835 }
836 /* Fill RX ring with skb's */
837 rxq_refill(dev);
838 return received_packets;
839}
840
841static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
842 struct net_device *dev)
843{
844 u32 icr;
845 int ret = 0;
846
847 icr = rdl(pep, INT_CAUSE);
848 if (icr == 0)
849 return IRQ_NONE;
850
851 wrl(pep, INT_CAUSE, ~icr);
852 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
853 pep->work_todo |= WORK_TX_DONE;
854 ret = 1;
855 }
856 if (icr & ICR_RXBUF)
857 ret = 1;
858 if (icr & ICR_MII_CH) {
859 pep->work_todo |= WORK_LINK;
860 ret = 1;
861 }
862 return ret;
863}
864
865static void handle_link_event(struct pxa168_eth_private *pep)
866{
867 struct net_device *dev = pep->dev;
868 u32 port_status;
869 int speed;
870 int duplex;
871 int fc;
872
873 port_status = rdl(pep, PORT_STATUS);
874 if (!(port_status & LINK_UP)) {
875 if (netif_carrier_ok(dev)) {
307f6565 876 netdev_info(dev, "link down\n");
a49f37ee
SS		 877 netif_carrier_off(dev);
878 txq_reclaim(dev, 1);
879 }
880 return;
881 }
882 if (port_status & PORT_SPEED_100)
883 speed = 100;
884 else
885 speed = 10;
886
887 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
09f5da1b 888 fc = (port_status & FLOW_CONTROL_DISABLED) ? 0 : 1;
307f6565
AT		 889 netdev_info(dev, "link up, %d Mb/s, %s duplex, flow control %sabled\n",
890 speed, duplex ? "full" : "half", fc ? "en" : "dis");
a49f37ee
SS		 891 if (!netif_carrier_ok(dev))
892 netif_carrier_on(dev);
893}
894
895static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
896{
897 struct net_device *dev = (struct net_device *)dev_id;
898 struct pxa168_eth_private *pep = netdev_priv(dev);
899
900 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
901 return IRQ_NONE;
902 /* Disable interrupts */
903 wrl(pep, INT_MASK, 0);
904 napi_schedule(&pep->napi);
905 return IRQ_HANDLED;
906}
907
908static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
909{
910 int skb_size;
911
912 /*
913 * Reserve 2+14 bytes for an ethernet header (the hardware
914 * automatically prepends 2 bytes of dummy data to each
915 * received packet), 16 bytes for up to four VLAN tags, and
916 * 4 bytes for the trailing FCS -- 36 bytes total.
917 */
918 skb_size = pep->dev->mtu + 36;
919
920 /*
921 * Make sure that the skb size is a multiple of 8 bytes, as
922 * the lower three bits of the receive descriptor's buffer
923 * size field are ignored by the hardware.
924 */
925 pep->skb_size = (skb_size + 7) & ~7;
926
927 /*
928 * If NET_SKB_PAD is smaller than a cache line,
929 * netdev_alloc_skb() will cause skb->data to be misaligned
930 * to a cache line boundary. If this is the case, include
931 * some extra space to allow re-aligning the data area.
932 */
933 pep->skb_size += SKB_DMA_REALIGN;
934
935}
936
937static int set_port_config_ext(struct pxa168_eth_private *pep)
938{
939 int skb_size;
940
941 pxa168_eth_recalc_skb_size(pep);
942 if (pep->skb_size <= 1518)
943 skb_size = PCXR_MFL_1518;
944 else if (pep->skb_size <= 1536)
945 skb_size = PCXR_MFL_1536;
946 else if (pep->skb_size <= 2048)
947 skb_size = PCXR_MFL_2048;
948 else
949 skb_size = PCXR_MFL_64K;
950
951 /* Extended Port Configuration */
952 wrl(pep,
953 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
954 PCXR_DSCP_EN | /* Enable DSCP in IP */
955 skb_size | PCXR_FLP | /* do not force link pass */
956 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
957
958 return 0;
959}
960
961static int pxa168_init_hw(struct pxa168_eth_private *pep)
962{
963 int err = 0;
964
965 /* Disable interrupts */
966 wrl(pep, INT_MASK, 0);
967 wrl(pep, INT_CAUSE, 0);
968 /* Write to ICR to clear interrupts. */
969 wrl(pep, INT_W_CLEAR, 0);
970 /* Abort any transmit and receive operations and put DMA
971 * in idle state.
972 */
973 abort_dma(pep);
974 /* Initialize address hash table */
975 err = init_hash_table(pep);
976 if (err)
977 return err;
978 /* SDMA configuration */
979 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
980 SDCR_RIFB | /* Rx interrupt on frame */
981 SDCR_BLMT | /* Little endian transmit */
982 SDCR_BLMR | /* Little endian receive */
983 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
984 /* Port Configuration */
985 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
986 set_port_config_ext(pep);
987
988 return err;
989}
990
991static int rxq_init(struct net_device *dev)
992{
993 struct pxa168_eth_private *pep = netdev_priv(dev);
994 struct rx_desc *p_rx_desc;
995 int size = 0, i = 0;
996 int rx_desc_num = pep->rx_ring_size;
997
998 /* Allocate RX skb rings */
451bff29 999 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
a49f37ee 1000 GFP_KERNEL);
e404decb 1001 if (!pep->rx_skb)
a49f37ee 1002 return -ENOMEM;
e404decb 1003
a49f37ee
SS		 1004 /* Allocate RX ring */
1005 pep->rx_desc_count = 0;
1006 size = pep->rx_ring_size * sizeof(struct rx_desc);
1007 pep->rx_desc_area_size = size;
ede23fa8
JP		 1008 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1009 &pep->rx_desc_dma,
1010 GFP_KERNEL);
d0320f75 1011 if (!pep->p_rx_desc_area)
a49f37ee 1012 goto out;
d0320f75 1013
a49f37ee 1014 /* initialize the next_desc_ptr links in the Rx descriptors ring */
64699336 1015 p_rx_desc = pep->p_rx_desc_area;
a49f37ee
SS		 1016 for (i = 0; i < rx_desc_num; i++) {
1017 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1018 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1019 }
1020 /* Save Rx desc pointer to driver struct. */
1021 pep->rx_curr_desc_q = 0;
1022 pep->rx_used_desc_q = 0;
1023 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1024 return 0;
1025out:
1026 kfree(pep->rx_skb);
1027 return -ENOMEM;
1028}
1029
1030static void rxq_deinit(struct net_device *dev)
1031{
1032 struct pxa168_eth_private *pep = netdev_priv(dev);
1033 int curr;
1034
1035 /* Free preallocated skb's on RX rings */
1036 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1037 if (pep->rx_skb[curr]) {
1038 dev_kfree_skb(pep->rx_skb[curr]);
1039 pep->rx_desc_count--;
1040 }
1041 }
1042 if (pep->rx_desc_count)
307f6565
AT		 1043 netdev_err(dev, "Error in freeing Rx Ring. %d skb's still\n",
1044 pep->rx_desc_count);
a49f37ee
SS		 1045 /* Free RX ring */
1046 if (pep->p_rx_desc_area)
1047 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1048 pep->p_rx_desc_area, pep->rx_desc_dma);
1049 kfree(pep->rx_skb);
1050}
1051
1052static int txq_init(struct net_device *dev)
1053{
1054 struct pxa168_eth_private *pep = netdev_priv(dev);
1055 struct tx_desc *p_tx_desc;
1056 int size = 0, i = 0;
1057 int tx_desc_num = pep->tx_ring_size;
1058
451bff29 1059 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
a49f37ee 1060 GFP_KERNEL);
e404decb 1061 if (!pep->tx_skb)
a49f37ee 1062 return -ENOMEM;
e404decb 1063
a49f37ee
SS		 1064 /* Allocate TX ring */
1065 pep->tx_desc_count = 0;
1066 size = pep->tx_ring_size * sizeof(struct tx_desc);
1067 pep->tx_desc_area_size = size;
ede23fa8
JP		 1068 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1069 &pep->tx_desc_dma,
1070 GFP_KERNEL);
d0320f75 1071 if (!pep->p_tx_desc_area)
a49f37ee 1072 goto out;
a49f37ee 1073 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
64699336 1074 p_tx_desc = pep->p_tx_desc_area;
a49f37ee
SS		 1075 for (i = 0; i < tx_desc_num; i++) {
1076 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1077 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1078 }
1079 pep->tx_curr_desc_q = 0;
1080 pep->tx_used_desc_q = 0;
1081 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1082 return 0;
1083out:
1084 kfree(pep->tx_skb);
1085 return -ENOMEM;
1086}
1087
1088static void txq_deinit(struct net_device *dev)
1089{
1090 struct pxa168_eth_private *pep = netdev_priv(dev);
1091
1092 /* Free outstanding skb's on TX ring */
1093 txq_reclaim(dev, 1);
1094 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1095 /* Free TX ring */
1096 if (pep->p_tx_desc_area)
1097 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1098 pep->p_tx_desc_area, pep->tx_desc_dma);
1099 kfree(pep->tx_skb);
1100}
1101
1102static int pxa168_eth_open(struct net_device *dev)
1103{
1104 struct pxa168_eth_private *pep = netdev_priv(dev);
1105 int err;
1106
599c2e1f 1107 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
a49f37ee 1108 if (err) {
f7b4fb22 1109 dev_err(&dev->dev, "can't assign irq\n");
a49f37ee
SS		 1110 return -EAGAIN;
1111 }
1112 pep->rx_resource_err = 0;
1113 err = rxq_init(dev);
1114 if (err != 0)
1115 goto out_free_irq;
1116 err = txq_init(dev);
1117 if (err != 0)
1118 goto out_free_rx_skb;
1119 pep->rx_used_desc_q = 0;
1120 pep->rx_curr_desc_q = 0;
1121
1122 /* Fill RX ring with skb's */
1123 rxq_refill(dev);
1124 pep->rx_used_desc_q = 0;
1125 pep->rx_curr_desc_q = 0;
1126 netif_carrier_off(dev);
1127 eth_port_start(dev);
1128 napi_enable(&pep->napi);
1129 return 0;
1130out_free_rx_skb:
1131 rxq_deinit(dev);
1132out_free_irq:
1133 free_irq(dev->irq, dev);
1134 return err;
1135}
1136
1137static int pxa168_eth_stop(struct net_device *dev)
1138{
1139 struct pxa168_eth_private *pep = netdev_priv(dev);
1140 eth_port_reset(dev);
1141
1142 /* Disable interrupts */
1143 wrl(pep, INT_MASK, 0);
1144 wrl(pep, INT_CAUSE, 0);
1145 /* Write to ICR to clear interrupts. */
1146 wrl(pep, INT_W_CLEAR, 0);
1147 napi_disable(&pep->napi);
1148 del_timer_sync(&pep->timeout);
1149 netif_carrier_off(dev);
1150 free_irq(dev->irq, dev);
1151 rxq_deinit(dev);
1152 txq_deinit(dev);
1153
1154 return 0;
1155}
1156
1157static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1158{
1159 int retval;
1160 struct pxa168_eth_private *pep = netdev_priv(dev);
1161
1162 if ((mtu > 9500) || (mtu < 68))
1163 return -EINVAL;
1164
1165 dev->mtu = mtu;
1166 retval = set_port_config_ext(pep);
1167
1168 if (!netif_running(dev))
1169 return 0;
1170
1171 /*
1172 * Stop and then re-open the interface. This will allocate RX
1173 * skbs of the new MTU.
1174 * There is a possible danger that the open will not succeed,
1175 * due to memory being full.
1176 */
1177 pxa168_eth_stop(dev);
1178 if (pxa168_eth_open(dev)) {
f7b4fb22
JP		 1179 dev_err(&dev->dev,
1180 "fatal error on re-opening device after MTU change\n");
a49f37ee
SS		 1181 }
1182
1183 return 0;
1184}
1185
1186static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1187{
1188 int tx_desc_curr;
1189
1190 tx_desc_curr = pep->tx_curr_desc_q;
1191 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1192 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1193 pep->tx_desc_count++;
1194
1195 return tx_desc_curr;
1196}
1197
1198static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1199{
1200 struct pxa168_eth_private *pep =
1201 container_of(napi, struct pxa168_eth_private, napi);
1202 struct net_device *dev = pep->dev;
1203 int work_done = 0;
1204
1205 if (unlikely(pep->work_todo & WORK_LINK)) {
1206 pep->work_todo &= ~(WORK_LINK);
1207 handle_link_event(pep);
1208 }
1209 /*
1210 * We call txq_reclaim every time since in NAPI interupts are disabled
1211 * and due to this we miss the TX_DONE interrupt,which is not updated in
1212 * interrupt status register.
1213 */
1214 txq_reclaim(dev, 0);
1215 if (netif_queue_stopped(dev)
1216 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1217 netif_wake_queue(dev);
1218 }
1219 work_done = rxq_process(dev, budget);
1220 if (work_done < budget) {
1221 napi_complete(napi);
1222 wrl(pep, INT_MASK, ALL_INTS);
1223 }
1224
1225 return work_done;
1226}
1227
1228static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1229{
1230 struct pxa168_eth_private *pep = netdev_priv(dev);
1231 struct net_device_stats *stats = &dev->stats;
1232 struct tx_desc *desc;
1233 int tx_index;
1234 int length;
1235
1236 tx_index = eth_alloc_tx_desc_index(pep);
1237 desc = &pep->p_tx_desc_area[tx_index];
1238 length = skb->len;
1239 pep->tx_skb[tx_index] = skb;
1240 desc->byte_cnt = length;
1241 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1f6e44a6
RC		 1242
1243 skb_tx_timestamp(skb);
1244
a49f37ee
SS		 1245 wmb();
1246 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1247 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1248 wmb();
1249 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1250
38442040 1251 stats->tx_bytes += length;
a49f37ee
SS		 1252 stats->tx_packets++;
1253 dev->trans_start = jiffies;
1254 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1255 /* We handled the current skb, but now we are out of space.*/
1256 netif_stop_queue(dev);
1257 }
1258
1259 return NETDEV_TX_OK;
1260}
1261
1262static int smi_wait_ready(struct pxa168_eth_private *pep)
1263{
1264 int i = 0;
1265
1266 /* wait for the SMI register to become available */
1267 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1268 if (i == PHY_WAIT_ITERATIONS)
1269 return -ETIMEDOUT;
1270 msleep(10);
1271 }
1272
1273 return 0;
1274}
1275
1276static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1277{
1278 struct pxa168_eth_private *pep = bus->priv;
1279 int i = 0;
1280 int val;
1281
1282 if (smi_wait_ready(pep)) {
307f6565 1283 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
a49f37ee
SS		 1284 return -ETIMEDOUT;
1285 }
1286 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1287 /* now wait for the data to be valid */
1288 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1289 if (i == PHY_WAIT_ITERATIONS) {
307f6565
AT		 1290 netdev_warn(pep->dev,
1291 "pxa168_eth: SMI bus read not valid\n");
a49f37ee
SS		 1292 return -ENODEV;
1293 }
1294 msleep(10);
1295 }
1296
1297 return val & 0xffff;
1298}
1299
1300static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1301 u16 value)
1302{
1303 struct pxa168_eth_private *pep = bus->priv;
1304
1305 if (smi_wait_ready(pep)) {
307f6565 1306 netdev_warn(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
a49f37ee
SS		 1307 return -ETIMEDOUT;
1308 }
1309
1310 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1311 SMI_OP_W | (value & 0xffff));
1312
1313 if (smi_wait_ready(pep)) {
307f6565 1314 netdev_err(pep->dev, "pxa168_eth: SMI bus busy timeout\n");
a49f37ee
SS		 1315 return -ETIMEDOUT;
1316 }
1317
1318 return 0;
1319}
1320
1321static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1322 int cmd)
1323{
1324 struct pxa168_eth_private *pep = netdev_priv(dev);
1325 if (pep->phy != NULL)
4f2c8510 1326 return phy_mii_ioctl(pep->phy, ifr, cmd);
a49f37ee
SS		 1327
1328 return -EOPNOTSUPP;
1329}
1330
1331static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1332{
1333 struct mii_bus *bus = pep->smi_bus;
1334 struct phy_device *phydev;
1335 int start;
1336 int num;
1337 int i;
1338
1339 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1340 /* Scan entire range */
1341 start = ethernet_phy_get(pep);
1342 num = 32;
1343 } else {
1344 /* Use phy addr specific to platform */
1345 start = phy_addr & 0x1f;
1346 num = 1;
1347 }
1348 phydev = NULL;
1349 for (i = 0; i < num; i++) {
1350 int addr = (start + i) & 0x1f;
1351 if (bus->phy_map[addr] == NULL)
1352 mdiobus_scan(bus, addr);
1353
1354 if (phydev == NULL) {
1355 phydev = bus->phy_map[addr];
1356 if (phydev != NULL)
1357 ethernet_phy_set_addr(pep, addr);
1358 }
1359 }
1360
1361 return phydev;
1362}
1363
43d3ddf8 1364static void phy_init(struct pxa168_eth_private *pep)
a49f37ee
SS		 1365{
1366 struct phy_device *phy = pep->phy;
a49f37ee 1367
f9a8f83b 1368 phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
a49f37ee 1369
43d3ddf8
AT		 1370 if (pep->pd && pep->pd->speed != 0) {
1371 phy->autoneg = AUTONEG_DISABLE;
1372 phy->advertising = 0;
1373 phy->speed = pep->pd->speed;
1374 phy->duplex = pep->pd->duplex;
1375 } else {
a49f37ee
SS		 1376 phy->autoneg = AUTONEG_ENABLE;
1377 phy->speed = 0;
1378 phy->duplex = 0;
1379 phy->supported &= PHY_BASIC_FEATURES;
1380 phy->advertising = phy->supported | ADVERTISED_Autoneg;
a49f37ee 1381 }
43d3ddf8 1382
a49f37ee
SS		 1383 phy_start_aneg(phy);
1384}
1385
1386static int ethernet_phy_setup(struct net_device *dev)
1387{
1388 struct pxa168_eth_private *pep = netdev_priv(dev);
1389
43d3ddf8 1390 if (pep->pd && pep->pd->init)
4169591f 1391 pep->pd->init();
43d3ddf8
AT		 1392
1393 pep->phy = phy_scan(pep, pep->phy_addr & 0x1f);
a49f37ee 1394 if (pep->phy != NULL)
43d3ddf8
AT		 1395 phy_init(pep);
1396
a49f37ee
SS		 1397 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1398
1399 return 0;
1400}
1401
1402static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1403{
1404 struct pxa168_eth_private *pep = netdev_priv(dev);
1405 int err;
1406
1407 err = phy_read_status(pep->phy);
1408 if (err == 0)
1409 err = phy_ethtool_gset(pep->phy, cmd);
1410
1411 return err;
1412}
1413
1414static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1415{
1416 struct pxa168_eth_private *pep = netdev_priv(dev);
1417
1418 return phy_ethtool_sset(pep->phy, cmd);
1419}
1420
1421static void pxa168_get_drvinfo(struct net_device *dev,
1422 struct ethtool_drvinfo *info)
1423{
7826d43f
JP		 1424 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1425 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
1426 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1427 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
a49f37ee
SS		 1428}
1429
a49f37ee 1430static const struct ethtool_ops pxa168_ethtool_ops = {
307f6565
AT		 1431 .get_settings = pxa168_get_settings,
1432 .set_settings = pxa168_set_settings,
1433 .get_drvinfo = pxa168_get_drvinfo,
1434 .get_link = ethtool_op_get_link,
1435 .get_ts_info = ethtool_op_get_ts_info,
a49f37ee
SS		 1436};
1437
1438static const struct net_device_ops pxa168_eth_netdev_ops = {
307f6565
AT		 1439 .ndo_open = pxa168_eth_open,
1440 .ndo_stop = pxa168_eth_stop,
1441 .ndo_start_xmit = pxa168_eth_start_xmit,
1442 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1443 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1444 .ndo_validate_addr = eth_validate_addr,
1445 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1446 .ndo_change_mtu = pxa168_eth_change_mtu,
1447 .ndo_tx_timeout = pxa168_eth_tx_timeout,
a49f37ee
SS		 1448};
1449
1450static int pxa168_eth_probe(struct platform_device *pdev)
1451{
1452 struct pxa168_eth_private *pep = NULL;
1453 struct net_device *dev = NULL;
1454 struct resource *res;
1455 struct clk *clk;
43d3ddf8 1456 struct device_node *np;
a49f37ee
SS		 1457 int err;
1458
1459 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1460
43d3ddf8 1461 clk = devm_clk_get(&pdev->dev, NULL);
a49f37ee 1462 if (IS_ERR(clk)) {
307f6565 1463 dev_err(&pdev->dev, "Fast Ethernet failed to get clock\n");
a49f37ee
SS		 1464 return -ENODEV;
1465 }
43d3ddf8 1466 clk_prepare_enable(clk);
a49f37ee
SS		 1467
1468 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1469 if (!dev) {
1470 err = -ENOMEM;
945c7c73 1471 goto err_clk;
a49f37ee
SS		 1472 }
1473
1474 platform_set_drvdata(pdev, dev);
1475 pep = netdev_priv(dev);
1476 pep->dev = dev;
1477 pep->clk = clk;
1478 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1479 if (res == NULL) {
1480 err = -ENODEV;
945c7c73 1481 goto err_netdev;
a49f37ee 1482 }
43d3ddf8
AT		 1483 pep->base = devm_ioremap_resource(&pdev->dev, res);
1484 if (IS_ERR(pep->base)) {
a49f37ee 1485 err = -ENOMEM;
945c7c73 1486 goto err_netdev;
a49f37ee
SS		 1487 }
1488 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1489 BUG_ON(!res);
1490 dev->irq = res->start;
1491 dev->netdev_ops = &pxa168_eth_netdev_ops;
1492 dev->watchdog_timeo = 2 * HZ;
1493 dev->base_addr = 0;
7ad24ea4 1494 dev->ethtool_ops = &pxa168_ethtool_ops;
a49f37ee
SS		 1495
1496 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1497
307f6565 1498 dev_info(&pdev->dev, "Using random mac address\n");
7ce5d222 1499 eth_hw_addr_random(dev);
a49f37ee 1500
a49f37ee 1501 pep->rx_ring_size = NUM_RX_DESCS;
a49f37ee 1502 pep->tx_ring_size = NUM_TX_DESCS;
a49f37ee 1503
43d3ddf8
AT		 1504 pep->pd = dev_get_platdata(&pdev->dev);
1505 if (pep->pd) {
1506 if (pep->pd->rx_queue_size)
1507 pep->rx_ring_size = pep->pd->rx_queue_size;
1508
1509 if (pep->pd->tx_queue_size)
1510 pep->tx_ring_size = pep->pd->tx_queue_size;
1511
1512 pep->port_num = pep->pd->port_number;
1513 pep->phy_addr = pep->pd->phy_addr;
1514 } else if (pdev->dev.of_node) {
1515 of_property_read_u32(pdev->dev.of_node, "port-id",
1516 &pep->port_num);
1517
1518 np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1519 if (np)
1520 of_property_read_u32(np, "reg", &pep->phy_addr);
1521 }
1522
a49f37ee
SS		 1523 /* Hardware supports only 3 ports */
1524 BUG_ON(pep->port_num > 2);
1525 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1526
1527 memset(&pep->timeout, 0, sizeof(struct timer_list));
1528 init_timer(&pep->timeout);
1529 pep->timeout.function = rxq_refill_timer_wrapper;
1530 pep->timeout.data = (unsigned long)pep;
1531
1532 pep->smi_bus = mdiobus_alloc();
1533 if (pep->smi_bus == NULL) {
1534 err = -ENOMEM;
945c7c73 1535 goto err_base;
a49f37ee
SS		 1536 }
1537 pep->smi_bus->priv = pep;
1538 pep->smi_bus->name = "pxa168_eth smi";
1539 pep->smi_bus->read = pxa168_smi_read;
1540 pep->smi_bus->write = pxa168_smi_write;
d073a102
FF		 1541 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1542 pdev->name, pdev->id);
a49f37ee
SS		 1543 pep->smi_bus->parent = &pdev->dev;
1544 pep->smi_bus->phy_mask = 0xffffffff;
945c7c73
DC		 1545 err = mdiobus_register(pep->smi_bus);
1546 if (err)
1547 goto err_free_mdio;
1548
a49f37ee
SS		 1549 pxa168_init_hw(pep);
1550 err = ethernet_phy_setup(dev);
1551 if (err)
945c7c73 1552 goto err_mdiobus;
a49f37ee
SS		 1553 SET_NETDEV_DEV(dev, &pdev->dev);
1554 err = register_netdev(dev);
1555 if (err)
945c7c73 1556 goto err_mdiobus;
a49f37ee 1557 return 0;
945c7c73
DC		 1558
1559err_mdiobus:
1560 mdiobus_unregister(pep->smi_bus);
1561err_free_mdio:
1562 mdiobus_free(pep->smi_bus);
1563err_base:
1564 iounmap(pep->base);
1565err_netdev:
1566 free_netdev(dev);
1567err_clk:
1568 clk_disable(clk);
1569 clk_put(clk);
a49f37ee
SS		 1570 return err;
1571}
1572
1573static int pxa168_eth_remove(struct platform_device *pdev)
1574{
1575 struct net_device *dev = platform_get_drvdata(pdev);
1576 struct pxa168_eth_private *pep = netdev_priv(dev);
1577
1578 if (pep->htpr) {
1579 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1580 pep->htpr, pep->htpr_dma);
1581 pep->htpr = NULL;
1582 }
1583 if (pep->clk) {
1584 clk_disable(pep->clk);
1585 clk_put(pep->clk);
1586 pep->clk = NULL;
1587 }
1588 if (pep->phy != NULL)
1589 phy_detach(pep->phy);
1590
1591 iounmap(pep->base);
1592 pep->base = NULL;
9c01ae58
DK		 1593 mdiobus_unregister(pep->smi_bus);
1594 mdiobus_free(pep->smi_bus);
a49f37ee 1595 unregister_netdev(dev);
23f333a2 1596 cancel_work_sync(&pep->tx_timeout_task);
a49f37ee 1597 free_netdev(dev);
a49f37ee
SS		 1598 return 0;
1599}
1600
1601static void pxa168_eth_shutdown(struct platform_device *pdev)
1602{
1603 struct net_device *dev = platform_get_drvdata(pdev);
1604 eth_port_reset(dev);
1605}
1606
1607#ifdef CONFIG_PM
1608static int pxa168_eth_resume(struct platform_device *pdev)
1609{
1610 return -ENOSYS;
1611}
1612
1613static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1614{
1615 return -ENOSYS;
1616}
1617
1618#else
1619#define pxa168_eth_resume NULL
1620#define pxa168_eth_suspend NULL
1621#endif
1622
43d3ddf8
AT		 1623static const struct of_device_id pxa168_eth_of_match[] = {
1624 { .compatible = "marvell,pxa168-eth" },
1625 { },
1626};
1627MODULE_DEVICE_TABLE(of, pxa168_eth_of_match);
1628
a49f37ee
SS		 1629static struct platform_driver pxa168_eth_driver = {
1630 .probe = pxa168_eth_probe,
1631 .remove = pxa168_eth_remove,
1632 .shutdown = pxa168_eth_shutdown,
1633 .resume = pxa168_eth_resume,
1634 .suspend = pxa168_eth_suspend,
1635 .driver = {
43d3ddf8
AT		 1636 .name = DRIVER_NAME,
1637 .of_match_table = of_match_ptr(pxa168_eth_of_match),
1638 },
a49f37ee
SS		 1639};
1640
db62f684 1641module_platform_driver(pxa168_eth_driver);
a49f37ee
SS		 1642
1643MODULE_LICENSE("GPL");
1644MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1645MODULE_ALIAS("platform:pxa168_eth");
Linux kernel - Deliverables
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