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net: pxa168_eth: remove deprecated IRQF_DISABLED
[deliverable/linux.git] / drivers / net / ethernet / marvell / pxa168_eth.c
CommitLineData
a49f37ee
SS		 1/*
2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
4 *
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
10206601 7 * Zhangfei Gao <zgao6@marvell.com>
a49f37ee
SS		 8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/in.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/udp.h>
32#include <linux/etherdevice.h>
33#include <linux/bitops.h>
34#include <linux/delay.h>
35#include <linux/ethtool.h>
36#include <linux/platform_device.h>
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/workqueue.h>
40#include <linux/clk.h>
41#include <linux/phy.h>
42#include <linux/io.h>
b7e43381 43#include <linux/interrupt.h>
a49f37ee
SS		 44#include <linux/types.h>
45#include <asm/pgtable.h>
a49f37ee
SS		 46#include <asm/cacheflush.h>
47#include <linux/pxa168_eth.h>
48
49#define DRIVER_NAME "pxa168-eth"
50#define DRIVER_VERSION "0.3"
51
52/*
53 * Registers
54 */
55
56#define PHY_ADDRESS 0x0000
57#define SMI 0x0010
58#define PORT_CONFIG 0x0400
59#define PORT_CONFIG_EXT 0x0408
60#define PORT_COMMAND 0x0410
61#define PORT_STATUS 0x0418
62#define HTPR 0x0428
63#define SDMA_CONFIG 0x0440
64#define SDMA_CMD 0x0448
65#define INT_CAUSE 0x0450
66#define INT_W_CLEAR 0x0454
67#define INT_MASK 0x0458
68#define ETH_F_RX_DESC_0 0x0480
69#define ETH_C_RX_DESC_0 0x04A0
70#define ETH_C_TX_DESC_1 0x04E4
71
72/* smi register */
73#define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
74#define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
75#define SMI_OP_W (0 << 26) /* Write operation */
76#define SMI_OP_R (1 << 26) /* Read operation */
77
78#define PHY_WAIT_ITERATIONS 10
79
80#define PXA168_ETH_PHY_ADDR_DEFAULT 0
81/* RX & TX descriptor command */
82#define BUF_OWNED_BY_DMA (1 << 31)
83
84/* RX descriptor status */
85#define RX_EN_INT (1 << 23)
86#define RX_FIRST_DESC (1 << 17)
87#define RX_LAST_DESC (1 << 16)
88#define RX_ERROR (1 << 15)
89
90/* TX descriptor command */
91#define TX_EN_INT (1 << 23)
92#define TX_GEN_CRC (1 << 22)
93#define TX_ZERO_PADDING (1 << 18)
94#define TX_FIRST_DESC (1 << 17)
95#define TX_LAST_DESC (1 << 16)
96#define TX_ERROR (1 << 15)
97
98/* SDMA_CMD */
99#define SDMA_CMD_AT (1 << 31)
100#define SDMA_CMD_TXDL (1 << 24)
101#define SDMA_CMD_TXDH (1 << 23)
102#define SDMA_CMD_AR (1 << 15)
103#define SDMA_CMD_ERD (1 << 7)
104
105/* Bit definitions of the Port Config Reg */
106#define PCR_HS (1 << 12)
107#define PCR_EN (1 << 7)
108#define PCR_PM (1 << 0)
109
110/* Bit definitions of the Port Config Extend Reg */
111#define PCXR_2BSM (1 << 28)
112#define PCXR_DSCP_EN (1 << 21)
113#define PCXR_MFL_1518 (0 << 14)
114#define PCXR_MFL_1536 (1 << 14)
115#define PCXR_MFL_2048 (2 << 14)
116#define PCXR_MFL_64K (3 << 14)
117#define PCXR_FLP (1 << 11)
118#define PCXR_PRIO_TX_OFF 3
119#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
120
121/* Bit definitions of the SDMA Config Reg */
122#define SDCR_BSZ_OFF 12
123#define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
124#define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
125#define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
126#define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
127#define SDCR_BLMR (1 << 6)
128#define SDCR_BLMT (1 << 7)
129#define SDCR_RIFB (1 << 9)
130#define SDCR_RC_OFF 2
131#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
132
133/*
134 * Bit definitions of the Interrupt Cause Reg
135 * and Interrupt MASK Reg is the same
136 */
137#define ICR_RXBUF (1 << 0)
138#define ICR_TXBUF_H (1 << 2)
139#define ICR_TXBUF_L (1 << 3)
140#define ICR_TXEND_H (1 << 6)
141#define ICR_TXEND_L (1 << 7)
142#define ICR_RXERR (1 << 8)
143#define ICR_TXERR_H (1 << 10)
144#define ICR_TXERR_L (1 << 11)
145#define ICR_TX_UDR (1 << 13)
146#define ICR_MII_CH (1 << 28)
147
148#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
149 ICR_TXERR_H | ICR_TXERR_L |\
150 ICR_TXEND_H | ICR_TXEND_L |\
151 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
152
153#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
154
155#define NUM_RX_DESCS 64
156#define NUM_TX_DESCS 64
157
158#define HASH_ADD 0
159#define HASH_DELETE 1
160#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
161#define HOP_NUMBER 12
162
163/* Bit definitions for Port status */
164#define PORT_SPEED_100 (1 << 0)
165#define FULL_DUPLEX (1 << 1)
166#define FLOW_CONTROL_ENABLED (1 << 2)
167#define LINK_UP (1 << 3)
168
169/* Bit definitions for work to be done */
170#define WORK_LINK (1 << 0)
171#define WORK_TX_DONE (1 << 1)
172
173/*
174 * Misc definitions.
175 */
176#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
177
178struct rx_desc {
179 u32 cmd_sts; /* Descriptor command status */
180 u16 byte_cnt; /* Descriptor buffer byte count */
181 u16 buf_size; /* Buffer size */
182 u32 buf_ptr; /* Descriptor buffer pointer */
183 u32 next_desc_ptr; /* Next descriptor pointer */
184};
185
186struct tx_desc {
187 u32 cmd_sts; /* Command/status field */
188 u16 reserved;
189 u16 byte_cnt; /* buffer byte count */
190 u32 buf_ptr; /* pointer to buffer for this descriptor */
191 u32 next_desc_ptr; /* Pointer to next descriptor */
192};
193
194struct pxa168_eth_private {
195 int port_num; /* User Ethernet port number */
196
197 int rx_resource_err; /* Rx ring resource error flag */
198
199 /* Next available and first returning Rx resource */
200 int rx_curr_desc_q, rx_used_desc_q;
201
202 /* Next available and first returning Tx resource */
203 int tx_curr_desc_q, tx_used_desc_q;
204
205 struct rx_desc *p_rx_desc_area;
206 dma_addr_t rx_desc_dma;
207 int rx_desc_area_size;
208 struct sk_buff **rx_skb;
209
210 struct tx_desc *p_tx_desc_area;
211 dma_addr_t tx_desc_dma;
212 int tx_desc_area_size;
213 struct sk_buff **tx_skb;
214
215 struct work_struct tx_timeout_task;
216
217 struct net_device *dev;
218 struct napi_struct napi;
219 u8 work_todo;
220 int skb_size;
221
a49f37ee
SS		 222 /* Size of Tx Ring per queue */
223 int tx_ring_size;
224 /* Number of tx descriptors in use */
225 int tx_desc_count;
226 /* Size of Rx Ring per queue */
227 int rx_ring_size;
228 /* Number of rx descriptors in use */
229 int rx_desc_count;
230
231 /*
232 * Used in case RX Ring is empty, which can occur when
233 * system does not have resources (skb's)
234 */
235 struct timer_list timeout;
236 struct mii_bus *smi_bus;
237 struct phy_device *phy;
238
239 /* clock */
240 struct clk *clk;
241 struct pxa168_eth_platform_data *pd;
242 /*
243 * Ethernet controller base address.
244 */
245 void __iomem *base;
246
247 /* Pointer to the hardware address filter table */
248 void *htpr;
249 dma_addr_t htpr_dma;
250};
251
252struct addr_table_entry {
253 __le32 lo;
254 __le32 hi;
255};
256
257/* Bit fields of a Hash Table Entry */
258enum hash_table_entry {
259 HASH_ENTRY_VALID = 1,
260 SKIP = 2,
261 HASH_ENTRY_RECEIVE_DISCARD = 4,
262 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
263};
264
265static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
266static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
267static int pxa168_init_hw(struct pxa168_eth_private *pep);
268static void eth_port_reset(struct net_device *dev);
269static void eth_port_start(struct net_device *dev);
270static int pxa168_eth_open(struct net_device *dev);
271static int pxa168_eth_stop(struct net_device *dev);
272static int ethernet_phy_setup(struct net_device *dev);
273
274static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
275{
276 return readl(pep->base + offset);
277}
278
279static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
280{
281 writel(data, pep->base + offset);
282}
283
284static void abort_dma(struct pxa168_eth_private *pep)
285{
286 int delay;
287 int max_retries = 40;
288
289 do {
290 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
291 udelay(100);
292
293 delay = 10;
294 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
295 && delay-- > 0) {
296 udelay(10);
297 }
298 } while (max_retries-- > 0 && delay <= 0);
299
300 if (max_retries <= 0)
301 printk(KERN_ERR "%s : DMA Stuck\n", __func__);
302}
303
304static int ethernet_phy_get(struct pxa168_eth_private *pep)
305{
306 unsigned int reg_data;
307
308 reg_data = rdl(pep, PHY_ADDRESS);
309
310 return (reg_data >> (5 * pep->port_num)) & 0x1f;
311}
312
313static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
314{
315 u32 reg_data;
316 int addr_shift = 5 * pep->port_num;
317
318 reg_data = rdl(pep, PHY_ADDRESS);
319 reg_data &= ~(0x1f << addr_shift);
320 reg_data |= (phy_addr & 0x1f) << addr_shift;
321 wrl(pep, PHY_ADDRESS, reg_data);
322}
323
324static void ethernet_phy_reset(struct pxa168_eth_private *pep)
325{
326 int data;
327
328 data = phy_read(pep->phy, MII_BMCR);
329 if (data < 0)
330 return;
331
332 data |= BMCR_RESET;
333 if (phy_write(pep->phy, MII_BMCR, data) < 0)
334 return;
335
336 do {
337 data = phy_read(pep->phy, MII_BMCR);
338 } while (data >= 0 && data & BMCR_RESET);
339}
340
341static void rxq_refill(struct net_device *dev)
342{
343 struct pxa168_eth_private *pep = netdev_priv(dev);
344 struct sk_buff *skb;
345 struct rx_desc *p_used_rx_desc;
346 int used_rx_desc;
347
348 while (pep->rx_desc_count < pep->rx_ring_size) {
349 int size;
350
c056b734 351 skb = netdev_alloc_skb(dev, pep->skb_size);
a49f37ee
SS		 352 if (!skb)
353 break;
354 if (SKB_DMA_REALIGN)
355 skb_reserve(skb, SKB_DMA_REALIGN);
356 pep->rx_desc_count++;
357 /* Get 'used' Rx descriptor */
358 used_rx_desc = pep->rx_used_desc_q;
359 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
511efbbb 360 size = skb_end_pointer(skb) - skb->data;
a49f37ee
SS		 361 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
362 skb->data,
363 size,
364 DMA_FROM_DEVICE);
365 p_used_rx_desc->buf_size = size;
366 pep->rx_skb[used_rx_desc] = skb;
367
368 /* Return the descriptor to DMA ownership */
369 wmb();
370 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
371 wmb();
372
373 /* Move the used descriptor pointer to the next descriptor */
374 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
375
376 /* Any Rx return cancels the Rx resource error status */
377 pep->rx_resource_err = 0;
378
379 skb_reserve(skb, ETH_HW_IP_ALIGN);
380 }
381
382 /*
383 * If RX ring is empty of SKB, set a timer to try allocating
384 * again at a later time.
385 */
386 if (pep->rx_desc_count == 0) {
387 pep->timeout.expires = jiffies + (HZ / 10);
388 add_timer(&pep->timeout);
389 }
390}
391
392static inline void rxq_refill_timer_wrapper(unsigned long data)
393{
394 struct pxa168_eth_private *pep = (void *)data;
395 napi_schedule(&pep->napi);
396}
397
398static inline u8 flip_8_bits(u8 x)
399{
400 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
401 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
402 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
403 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
404}
405
406static void nibble_swap_every_byte(unsigned char *mac_addr)
407{
408 int i;
409 for (i = 0; i < ETH_ALEN; i++) {
410 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
411 ((mac_addr[i] & 0xf0) >> 4);
412 }
413}
414
415static void inverse_every_nibble(unsigned char *mac_addr)
416{
417 int i;
418 for (i = 0; i < ETH_ALEN; i++)
419 mac_addr[i] = flip_8_bits(mac_addr[i]);
420}
421
422/*
423 * ----------------------------------------------------------------------------
424 * This function will calculate the hash function of the address.
425 * Inputs
426 * mac_addr_orig - MAC address.
427 * Outputs
428 * return the calculated entry.
429 */
430static u32 hash_function(unsigned char *mac_addr_orig)
431{
432 u32 hash_result;
433 u32 addr0;
434 u32 addr1;
435 u32 addr2;
436 u32 addr3;
437 unsigned char mac_addr[ETH_ALEN];
438
439 /* Make a copy of MAC address since we are going to performe bit
440 * operations on it
441 */
442 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
443
444 nibble_swap_every_byte(mac_addr);
445 inverse_every_nibble(mac_addr);
446
447 addr0 = (mac_addr[5] >> 2) & 0x3f;
448 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
449 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
450 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
451
452 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
453 hash_result = hash_result & 0x07ff;
454 return hash_result;
455}
456
457/*
458 * ----------------------------------------------------------------------------
459 * This function will add/del an entry to the address table.
460 * Inputs
461 * pep - ETHERNET .
462 * mac_addr - MAC address.
463 * skip - if 1, skip this address.Used in case of deleting an entry which is a
25985edc 464 * part of chain in the hash table.We can't just delete the entry since
a49f37ee
SS		 465 * that will break the chain.We need to defragment the tables time to
466 * time.
467 * rd - 0 Discard packet upon match.
468 * - 1 Receive packet upon match.
469 * Outputs
470 * address table entry is added/deleted.
471 * 0 if success.
472 * -ENOSPC if table full
473 */
474static int add_del_hash_entry(struct pxa168_eth_private *pep,
475 unsigned char *mac_addr,
476 u32 rd, u32 skip, int del)
477{
478 struct addr_table_entry *entry, *start;
479 u32 new_high;
480 u32 new_low;
481 u32 i;
482
483 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
484 | (((mac_addr[1] >> 0) & 0xf) << 11)
485 | (((mac_addr[0] >> 4) & 0xf) << 7)
486 | (((mac_addr[0] >> 0) & 0xf) << 3)
487 | (((mac_addr[3] >> 4) & 0x1) << 31)
488 | (((mac_addr[3] >> 0) & 0xf) << 27)
489 | (((mac_addr[2] >> 4) & 0xf) << 23)
490 | (((mac_addr[2] >> 0) & 0xf) << 19)
491 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
492 | HASH_ENTRY_VALID;
493
494 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
495 | (((mac_addr[5] >> 0) & 0xf) << 11)
496 | (((mac_addr[4] >> 4) & 0xf) << 7)
497 | (((mac_addr[4] >> 0) & 0xf) << 3)
498 | (((mac_addr[3] >> 5) & 0x7) << 0);
499
500 /*
501 * Pick the appropriate table, start scanning for free/reusable
502 * entries at the index obtained by hashing the specified MAC address
503 */
43d620c8 504 start = pep->htpr;
a49f37ee
SS		 505 entry = start + hash_function(mac_addr);
506 for (i = 0; i < HOP_NUMBER; i++) {
507 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
508 break;
509 } else {
510 /* if same address put in same position */
511 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
512 (new_low & 0xfffffff8)) &&
513 (le32_to_cpu(entry->hi) == new_high)) {
514 break;
515 }
516 }
517 if (entry == start + 0x7ff)
518 entry = start;
519 else
520 entry++;
521 }
522
523 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
524 (le32_to_cpu(entry->hi) != new_high) && del)
525 return 0;
526
527 if (i == HOP_NUMBER) {
528 if (!del) {
529 printk(KERN_INFO "%s: table section is full, need to "
530 "move to 16kB implementation?\n",
531 __FILE__);
532 return -ENOSPC;
533 } else
534 return 0;
535 }
536
537 /*
538 * Update the selected entry
539 */
540 if (del) {
541 entry->hi = 0;
542 entry->lo = 0;
543 } else {
544 entry->hi = cpu_to_le32(new_high);
545 entry->lo = cpu_to_le32(new_low);
546 }
547
548 return 0;
549}
550
551/*
552 * ----------------------------------------------------------------------------
553 * Create an addressTable entry from MAC address info
554 * found in the specifed net_device struct
555 *
556 * Input : pointer to ethernet interface network device structure
557 * Output : N/A
558 */
559static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
560 unsigned char *oaddr,
561 unsigned char *addr)
562{
563 /* Delete old entry */
564 if (oaddr)
565 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
566 /* Add new entry */
567 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
568}
569
570static int init_hash_table(struct pxa168_eth_private *pep)
571{
572 /*
573 * Hardware expects CPU to build a hash table based on a predefined
574 * hash function and populate it based on hardware address. The
575 * location of the hash table is identified by 32-bit pointer stored
576 * in HTPR internal register. Two possible sizes exists for the hash
577 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
578 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
579 * 1/2kB.
580 */
581 /* TODO: Add support for 8kB hash table and alternative hash
582 * function.Driver can dynamically switch to them if the 1/2kB hash
583 * table is full.
584 */
585 if (pep->htpr == NULL) {
ede23fa8
JP		 586 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent,
587 HASH_ADDR_TABLE_SIZE,
588 &pep->htpr_dma, GFP_KERNEL);
a49f37ee
SS		 589 if (pep->htpr == NULL)
590 return -ENOMEM;
1f9061d2
JP		 591 } else {
592 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
a49f37ee 593 }
a49f37ee
SS		 594 wrl(pep, HTPR, pep->htpr_dma);
595 return 0;
596}
597
598static void pxa168_eth_set_rx_mode(struct net_device *dev)
599{
600 struct pxa168_eth_private *pep = netdev_priv(dev);
601 struct netdev_hw_addr *ha;
602 u32 val;
603
604 val = rdl(pep, PORT_CONFIG);
605 if (dev->flags & IFF_PROMISC)
606 val |= PCR_PM;
607 else
608 val &= ~PCR_PM;
609 wrl(pep, PORT_CONFIG, val);
610
611 /*
612 * Remove the old list of MAC address and add dev->addr
613 * and multicast address.
614 */
615 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
616 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
617
618 netdev_for_each_mc_addr(ha, dev)
619 update_hash_table_mac_address(pep, NULL, ha->addr);
620}
621
622static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
623{
624 struct sockaddr *sa = addr;
625 struct pxa168_eth_private *pep = netdev_priv(dev);
626 unsigned char oldMac[ETH_ALEN];
627
628 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 629 return -EADDRNOTAVAIL;
a49f37ee
SS		 630 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
631 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
632 netif_addr_lock_bh(dev);
633 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
634 netif_addr_unlock_bh(dev);
635 return 0;
636}
637
638static void eth_port_start(struct net_device *dev)
639{
640 unsigned int val = 0;
641 struct pxa168_eth_private *pep = netdev_priv(dev);
642 int tx_curr_desc, rx_curr_desc;
643
644 /* Perform PHY reset, if there is a PHY. */
645 if (pep->phy != NULL) {
646 struct ethtool_cmd cmd;
647
648 pxa168_get_settings(pep->dev, &cmd);
649 ethernet_phy_reset(pep);
650 pxa168_set_settings(pep->dev, &cmd);
651 }
652
653 /* Assignment of Tx CTRP of given queue */
654 tx_curr_desc = pep->tx_curr_desc_q;
655 wrl(pep, ETH_C_TX_DESC_1,
b2bc8563 656 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
a49f37ee
SS		 657
658 /* Assignment of Rx CRDP of given queue */
659 rx_curr_desc = pep->rx_curr_desc_q;
660 wrl(pep, ETH_C_RX_DESC_0,
b2bc8563 661 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 662
663 wrl(pep, ETH_F_RX_DESC_0,
b2bc8563 664 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 665
666 /* Clear all interrupts */
667 wrl(pep, INT_CAUSE, 0);
668
669 /* Enable all interrupts for receive, transmit and error. */
670 wrl(pep, INT_MASK, ALL_INTS);
671
672 val = rdl(pep, PORT_CONFIG);
673 val |= PCR_EN;
674 wrl(pep, PORT_CONFIG, val);
675
676 /* Start RX DMA engine */
677 val = rdl(pep, SDMA_CMD);
678 val |= SDMA_CMD_ERD;
679 wrl(pep, SDMA_CMD, val);
680}
681
682static void eth_port_reset(struct net_device *dev)
683{
684 struct pxa168_eth_private *pep = netdev_priv(dev);
685 unsigned int val = 0;
686
687 /* Stop all interrupts for receive, transmit and error. */
688 wrl(pep, INT_MASK, 0);
689
690 /* Clear all interrupts */
691 wrl(pep, INT_CAUSE, 0);
692
693 /* Stop RX DMA */
694 val = rdl(pep, SDMA_CMD);
695 val &= ~SDMA_CMD_ERD; /* abort dma command */
696
697 /* Abort any transmit and receive operations and put DMA
698 * in idle state.
699 */
700 abort_dma(pep);
701
702 /* Disable port */
703 val = rdl(pep, PORT_CONFIG);
704 val &= ~PCR_EN;
705 wrl(pep, PORT_CONFIG, val);
706}
707
708/*
709 * txq_reclaim - Free the tx desc data for completed descriptors
710 * If force is non-zero, frees uncompleted descriptors as well
711 */
712static int txq_reclaim(struct net_device *dev, int force)
713{
714 struct pxa168_eth_private *pep = netdev_priv(dev);
715 struct tx_desc *desc;
716 u32 cmd_sts;
717 struct sk_buff *skb;
718 int tx_index;
719 dma_addr_t addr;
720 int count;
721 int released = 0;
722
723 netif_tx_lock(dev);
724
725 pep->work_todo &= ~WORK_TX_DONE;
726 while (pep->tx_desc_count > 0) {
727 tx_index = pep->tx_used_desc_q;
728 desc = &pep->p_tx_desc_area[tx_index];
729 cmd_sts = desc->cmd_sts;
730 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
731 if (released > 0) {
732 goto txq_reclaim_end;
733 } else {
734 released = -1;
735 goto txq_reclaim_end;
736 }
737 }
738 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
739 pep->tx_desc_count--;
740 addr = desc->buf_ptr;
741 count = desc->byte_cnt;
742 skb = pep->tx_skb[tx_index];
743 if (skb)
744 pep->tx_skb[tx_index] = NULL;
745
746 if (cmd_sts & TX_ERROR) {
747 if (net_ratelimit())
748 printk(KERN_ERR "%s: Error in TX\n", dev->name);
749 dev->stats.tx_errors++;
750 }
751 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
752 if (skb)
753 dev_kfree_skb_irq(skb);
754 released++;
755 }
756txq_reclaim_end:
757 netif_tx_unlock(dev);
758 return released;
759}
760
761static void pxa168_eth_tx_timeout(struct net_device *dev)
762{
763 struct pxa168_eth_private *pep = netdev_priv(dev);
764
765 printk(KERN_INFO "%s: TX timeout desc_count %d\n",
766 dev->name, pep->tx_desc_count);
767
768 schedule_work(&pep->tx_timeout_task);
769}
770
771static void pxa168_eth_tx_timeout_task(struct work_struct *work)
772{
773 struct pxa168_eth_private *pep = container_of(work,
774 struct pxa168_eth_private,
775 tx_timeout_task);
776 struct net_device *dev = pep->dev;
777 pxa168_eth_stop(dev);
778 pxa168_eth_open(dev);
779}
780
781static int rxq_process(struct net_device *dev, int budget)
782{
783 struct pxa168_eth_private *pep = netdev_priv(dev);
784 struct net_device_stats *stats = &dev->stats;
785 unsigned int received_packets = 0;
786 struct sk_buff *skb;
787
788 while (budget-- > 0) {
789 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
790 struct rx_desc *rx_desc;
791 unsigned int cmd_sts;
792
793 /* Do not process Rx ring in case of Rx ring resource error */
794 if (pep->rx_resource_err)
795 break;
796 rx_curr_desc = pep->rx_curr_desc_q;
797 rx_used_desc = pep->rx_used_desc_q;
798 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
799 cmd_sts = rx_desc->cmd_sts;
800 rmb();
801 if (cmd_sts & (BUF_OWNED_BY_DMA))
802 break;
803 skb = pep->rx_skb[rx_curr_desc];
804 pep->rx_skb[rx_curr_desc] = NULL;
805
806 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
807 pep->rx_curr_desc_q = rx_next_curr_desc;
808
809 /* Rx descriptors exhausted. */
810 /* Set the Rx ring resource error flag */
811 if (rx_next_curr_desc == rx_used_desc)
812 pep->rx_resource_err = 1;
813 pep->rx_desc_count--;
814 dma_unmap_single(NULL, rx_desc->buf_ptr,
815 rx_desc->buf_size,
816 DMA_FROM_DEVICE);
817 received_packets++;
818 /*
819 * Update statistics.
820 * Note byte count includes 4 byte CRC count
821 */
822 stats->rx_packets++;
823 stats->rx_bytes += rx_desc->byte_cnt;
824 /*
825 * In case received a packet without first / last bits on OR
826 * the error summary bit is on, the packets needs to be droped.
827 */
828 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
829 (RX_FIRST_DESC | RX_LAST_DESC))
830 || (cmd_sts & RX_ERROR)) {
831
832 stats->rx_dropped++;
833 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
834 (RX_FIRST_DESC | RX_LAST_DESC)) {
835 if (net_ratelimit())
836 printk(KERN_ERR
837 "%s: Rx pkt on multiple desc\n",
838 dev->name);
839 }
840 if (cmd_sts & RX_ERROR)
841 stats->rx_errors++;
842 dev_kfree_skb_irq(skb);
843 } else {
844 /*
845 * The -4 is for the CRC in the trailer of the
846 * received packet
847 */
848 skb_put(skb, rx_desc->byte_cnt - 4);
849 skb->protocol = eth_type_trans(skb, dev);
850 netif_receive_skb(skb);
851 }
a49f37ee
SS		 852 }
853 /* Fill RX ring with skb's */
854 rxq_refill(dev);
855 return received_packets;
856}
857
858static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
859 struct net_device *dev)
860{
861 u32 icr;
862 int ret = 0;
863
864 icr = rdl(pep, INT_CAUSE);
865 if (icr == 0)
866 return IRQ_NONE;
867
868 wrl(pep, INT_CAUSE, ~icr);
869 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
870 pep->work_todo |= WORK_TX_DONE;
871 ret = 1;
872 }
873 if (icr & ICR_RXBUF)
874 ret = 1;
875 if (icr & ICR_MII_CH) {
876 pep->work_todo |= WORK_LINK;
877 ret = 1;
878 }
879 return ret;
880}
881
882static void handle_link_event(struct pxa168_eth_private *pep)
883{
884 struct net_device *dev = pep->dev;
885 u32 port_status;
886 int speed;
887 int duplex;
888 int fc;
889
890 port_status = rdl(pep, PORT_STATUS);
891 if (!(port_status & LINK_UP)) {
892 if (netif_carrier_ok(dev)) {
893 printk(KERN_INFO "%s: link down\n", dev->name);
894 netif_carrier_off(dev);
895 txq_reclaim(dev, 1);
896 }
897 return;
898 }
899 if (port_status & PORT_SPEED_100)
900 speed = 100;
901 else
902 speed = 10;
903
904 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
905 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
906 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
907 "flow control %sabled\n", dev->name,
908 speed, duplex ? "full" : "half", fc ? "en" : "dis");
909 if (!netif_carrier_ok(dev))
910 netif_carrier_on(dev);
911}
912
913static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
914{
915 struct net_device *dev = (struct net_device *)dev_id;
916 struct pxa168_eth_private *pep = netdev_priv(dev);
917
918 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
919 return IRQ_NONE;
920 /* Disable interrupts */
921 wrl(pep, INT_MASK, 0);
922 napi_schedule(&pep->napi);
923 return IRQ_HANDLED;
924}
925
926static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
927{
928 int skb_size;
929
930 /*
931 * Reserve 2+14 bytes for an ethernet header (the hardware
932 * automatically prepends 2 bytes of dummy data to each
933 * received packet), 16 bytes for up to four VLAN tags, and
934 * 4 bytes for the trailing FCS -- 36 bytes total.
935 */
936 skb_size = pep->dev->mtu + 36;
937
938 /*
939 * Make sure that the skb size is a multiple of 8 bytes, as
940 * the lower three bits of the receive descriptor's buffer
941 * size field are ignored by the hardware.
942 */
943 pep->skb_size = (skb_size + 7) & ~7;
944
945 /*
946 * If NET_SKB_PAD is smaller than a cache line,
947 * netdev_alloc_skb() will cause skb->data to be misaligned
948 * to a cache line boundary. If this is the case, include
949 * some extra space to allow re-aligning the data area.
950 */
951 pep->skb_size += SKB_DMA_REALIGN;
952
953}
954
955static int set_port_config_ext(struct pxa168_eth_private *pep)
956{
957 int skb_size;
958
959 pxa168_eth_recalc_skb_size(pep);
960 if (pep->skb_size <= 1518)
961 skb_size = PCXR_MFL_1518;
962 else if (pep->skb_size <= 1536)
963 skb_size = PCXR_MFL_1536;
964 else if (pep->skb_size <= 2048)
965 skb_size = PCXR_MFL_2048;
966 else
967 skb_size = PCXR_MFL_64K;
968
969 /* Extended Port Configuration */
970 wrl(pep,
971 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
972 PCXR_DSCP_EN | /* Enable DSCP in IP */
973 skb_size | PCXR_FLP | /* do not force link pass */
974 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
975
976 return 0;
977}
978
979static int pxa168_init_hw(struct pxa168_eth_private *pep)
980{
981 int err = 0;
982
983 /* Disable interrupts */
984 wrl(pep, INT_MASK, 0);
985 wrl(pep, INT_CAUSE, 0);
986 /* Write to ICR to clear interrupts. */
987 wrl(pep, INT_W_CLEAR, 0);
988 /* Abort any transmit and receive operations and put DMA
989 * in idle state.
990 */
991 abort_dma(pep);
992 /* Initialize address hash table */
993 err = init_hash_table(pep);
994 if (err)
995 return err;
996 /* SDMA configuration */
997 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
998 SDCR_RIFB | /* Rx interrupt on frame */
999 SDCR_BLMT | /* Little endian transmit */
1000 SDCR_BLMR | /* Little endian receive */
1001 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
1002 /* Port Configuration */
1003 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
1004 set_port_config_ext(pep);
1005
1006 return err;
1007}
1008
1009static int rxq_init(struct net_device *dev)
1010{
1011 struct pxa168_eth_private *pep = netdev_priv(dev);
1012 struct rx_desc *p_rx_desc;
1013 int size = 0, i = 0;
1014 int rx_desc_num = pep->rx_ring_size;
1015
1016 /* Allocate RX skb rings */
451bff29 1017 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
a49f37ee 1018 GFP_KERNEL);
e404decb 1019 if (!pep->rx_skb)
a49f37ee 1020 return -ENOMEM;
e404decb 1021
a49f37ee
SS		 1022 /* Allocate RX ring */
1023 pep->rx_desc_count = 0;
1024 size = pep->rx_ring_size * sizeof(struct rx_desc);
1025 pep->rx_desc_area_size = size;
ede23fa8
JP		 1026 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1027 &pep->rx_desc_dma,
1028 GFP_KERNEL);
d0320f75 1029 if (!pep->p_rx_desc_area)
a49f37ee 1030 goto out;
d0320f75 1031
a49f37ee 1032 /* initialize the next_desc_ptr links in the Rx descriptors ring */
64699336 1033 p_rx_desc = pep->p_rx_desc_area;
a49f37ee
SS		 1034 for (i = 0; i < rx_desc_num; i++) {
1035 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1036 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1037 }
1038 /* Save Rx desc pointer to driver struct. */
1039 pep->rx_curr_desc_q = 0;
1040 pep->rx_used_desc_q = 0;
1041 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1042 return 0;
1043out:
1044 kfree(pep->rx_skb);
1045 return -ENOMEM;
1046}
1047
1048static void rxq_deinit(struct net_device *dev)
1049{
1050 struct pxa168_eth_private *pep = netdev_priv(dev);
1051 int curr;
1052
1053 /* Free preallocated skb's on RX rings */
1054 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1055 if (pep->rx_skb[curr]) {
1056 dev_kfree_skb(pep->rx_skb[curr]);
1057 pep->rx_desc_count--;
1058 }
1059 }
1060 if (pep->rx_desc_count)
1061 printk(KERN_ERR
1062 "Error in freeing Rx Ring. %d skb's still\n",
1063 pep->rx_desc_count);
1064 /* Free RX ring */
1065 if (pep->p_rx_desc_area)
1066 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1067 pep->p_rx_desc_area, pep->rx_desc_dma);
1068 kfree(pep->rx_skb);
1069}
1070
1071static int txq_init(struct net_device *dev)
1072{
1073 struct pxa168_eth_private *pep = netdev_priv(dev);
1074 struct tx_desc *p_tx_desc;
1075 int size = 0, i = 0;
1076 int tx_desc_num = pep->tx_ring_size;
1077
451bff29 1078 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
a49f37ee 1079 GFP_KERNEL);
e404decb 1080 if (!pep->tx_skb)
a49f37ee 1081 return -ENOMEM;
e404decb 1082
a49f37ee
SS		 1083 /* Allocate TX ring */
1084 pep->tx_desc_count = 0;
1085 size = pep->tx_ring_size * sizeof(struct tx_desc);
1086 pep->tx_desc_area_size = size;
ede23fa8
JP		 1087 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1088 &pep->tx_desc_dma,
1089 GFP_KERNEL);
d0320f75 1090 if (!pep->p_tx_desc_area)
a49f37ee 1091 goto out;
a49f37ee 1092 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
64699336 1093 p_tx_desc = pep->p_tx_desc_area;
a49f37ee
SS		 1094 for (i = 0; i < tx_desc_num; i++) {
1095 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1096 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1097 }
1098 pep->tx_curr_desc_q = 0;
1099 pep->tx_used_desc_q = 0;
1100 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1101 return 0;
1102out:
1103 kfree(pep->tx_skb);
1104 return -ENOMEM;
1105}
1106
1107static void txq_deinit(struct net_device *dev)
1108{
1109 struct pxa168_eth_private *pep = netdev_priv(dev);
1110
1111 /* Free outstanding skb's on TX ring */
1112 txq_reclaim(dev, 1);
1113 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1114 /* Free TX ring */
1115 if (pep->p_tx_desc_area)
1116 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1117 pep->p_tx_desc_area, pep->tx_desc_dma);
1118 kfree(pep->tx_skb);
1119}
1120
1121static int pxa168_eth_open(struct net_device *dev)
1122{
1123 struct pxa168_eth_private *pep = netdev_priv(dev);
1124 int err;
1125
599c2e1f 1126 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
a49f37ee 1127 if (err) {
f7b4fb22 1128 dev_err(&dev->dev, "can't assign irq\n");
a49f37ee
SS		 1129 return -EAGAIN;
1130 }
1131 pep->rx_resource_err = 0;
1132 err = rxq_init(dev);
1133 if (err != 0)
1134 goto out_free_irq;
1135 err = txq_init(dev);
1136 if (err != 0)
1137 goto out_free_rx_skb;
1138 pep->rx_used_desc_q = 0;
1139 pep->rx_curr_desc_q = 0;
1140
1141 /* Fill RX ring with skb's */
1142 rxq_refill(dev);
1143 pep->rx_used_desc_q = 0;
1144 pep->rx_curr_desc_q = 0;
1145 netif_carrier_off(dev);
1146 eth_port_start(dev);
1147 napi_enable(&pep->napi);
1148 return 0;
1149out_free_rx_skb:
1150 rxq_deinit(dev);
1151out_free_irq:
1152 free_irq(dev->irq, dev);
1153 return err;
1154}
1155
1156static int pxa168_eth_stop(struct net_device *dev)
1157{
1158 struct pxa168_eth_private *pep = netdev_priv(dev);
1159 eth_port_reset(dev);
1160
1161 /* Disable interrupts */
1162 wrl(pep, INT_MASK, 0);
1163 wrl(pep, INT_CAUSE, 0);
1164 /* Write to ICR to clear interrupts. */
1165 wrl(pep, INT_W_CLEAR, 0);
1166 napi_disable(&pep->napi);
1167 del_timer_sync(&pep->timeout);
1168 netif_carrier_off(dev);
1169 free_irq(dev->irq, dev);
1170 rxq_deinit(dev);
1171 txq_deinit(dev);
1172
1173 return 0;
1174}
1175
1176static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1177{
1178 int retval;
1179 struct pxa168_eth_private *pep = netdev_priv(dev);
1180
1181 if ((mtu > 9500) || (mtu < 68))
1182 return -EINVAL;
1183
1184 dev->mtu = mtu;
1185 retval = set_port_config_ext(pep);
1186
1187 if (!netif_running(dev))
1188 return 0;
1189
1190 /*
1191 * Stop and then re-open the interface. This will allocate RX
1192 * skbs of the new MTU.
1193 * There is a possible danger that the open will not succeed,
1194 * due to memory being full.
1195 */
1196 pxa168_eth_stop(dev);
1197 if (pxa168_eth_open(dev)) {
f7b4fb22
JP		 1198 dev_err(&dev->dev,
1199 "fatal error on re-opening device after MTU change\n");
a49f37ee
SS		 1200 }
1201
1202 return 0;
1203}
1204
1205static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1206{
1207 int tx_desc_curr;
1208
1209 tx_desc_curr = pep->tx_curr_desc_q;
1210 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1211 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1212 pep->tx_desc_count++;
1213
1214 return tx_desc_curr;
1215}
1216
1217static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1218{
1219 struct pxa168_eth_private *pep =
1220 container_of(napi, struct pxa168_eth_private, napi);
1221 struct net_device *dev = pep->dev;
1222 int work_done = 0;
1223
1224 if (unlikely(pep->work_todo & WORK_LINK)) {
1225 pep->work_todo &= ~(WORK_LINK);
1226 handle_link_event(pep);
1227 }
1228 /*
1229 * We call txq_reclaim every time since in NAPI interupts are disabled
1230 * and due to this we miss the TX_DONE interrupt,which is not updated in
1231 * interrupt status register.
1232 */
1233 txq_reclaim(dev, 0);
1234 if (netif_queue_stopped(dev)
1235 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1236 netif_wake_queue(dev);
1237 }
1238 work_done = rxq_process(dev, budget);
1239 if (work_done < budget) {
1240 napi_complete(napi);
1241 wrl(pep, INT_MASK, ALL_INTS);
1242 }
1243
1244 return work_done;
1245}
1246
1247static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1248{
1249 struct pxa168_eth_private *pep = netdev_priv(dev);
1250 struct net_device_stats *stats = &dev->stats;
1251 struct tx_desc *desc;
1252 int tx_index;
1253 int length;
1254
1255 tx_index = eth_alloc_tx_desc_index(pep);
1256 desc = &pep->p_tx_desc_area[tx_index];
1257 length = skb->len;
1258 pep->tx_skb[tx_index] = skb;
1259 desc->byte_cnt = length;
1260 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1f6e44a6
RC		 1261
1262 skb_tx_timestamp(skb);
1263
a49f37ee
SS		 1264 wmb();
1265 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1266 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1267 wmb();
1268 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1269
38442040 1270 stats->tx_bytes += length;
a49f37ee
SS		 1271 stats->tx_packets++;
1272 dev->trans_start = jiffies;
1273 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1274 /* We handled the current skb, but now we are out of space.*/
1275 netif_stop_queue(dev);
1276 }
1277
1278 return NETDEV_TX_OK;
1279}
1280
1281static int smi_wait_ready(struct pxa168_eth_private *pep)
1282{
1283 int i = 0;
1284
1285 /* wait for the SMI register to become available */
1286 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1287 if (i == PHY_WAIT_ITERATIONS)
1288 return -ETIMEDOUT;
1289 msleep(10);
1290 }
1291
1292 return 0;
1293}
1294
1295static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1296{
1297 struct pxa168_eth_private *pep = bus->priv;
1298 int i = 0;
1299 int val;
1300
1301 if (smi_wait_ready(pep)) {
1302 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1303 return -ETIMEDOUT;
1304 }
1305 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1306 /* now wait for the data to be valid */
1307 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1308 if (i == PHY_WAIT_ITERATIONS) {
1309 printk(KERN_WARNING
1310 "pxa168_eth: SMI bus read not valid\n");
1311 return -ENODEV;
1312 }
1313 msleep(10);
1314 }
1315
1316 return val & 0xffff;
1317}
1318
1319static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1320 u16 value)
1321{
1322 struct pxa168_eth_private *pep = bus->priv;
1323
1324 if (smi_wait_ready(pep)) {
1325 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1326 return -ETIMEDOUT;
1327 }
1328
1329 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1330 SMI_OP_W | (value & 0xffff));
1331
1332 if (smi_wait_ready(pep)) {
1333 printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n");
1334 return -ETIMEDOUT;
1335 }
1336
1337 return 0;
1338}
1339
1340static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1341 int cmd)
1342{
1343 struct pxa168_eth_private *pep = netdev_priv(dev);
1344 if (pep->phy != NULL)
4f2c8510 1345 return phy_mii_ioctl(pep->phy, ifr, cmd);
a49f37ee
SS		 1346
1347 return -EOPNOTSUPP;
1348}
1349
1350static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1351{
1352 struct mii_bus *bus = pep->smi_bus;
1353 struct phy_device *phydev;
1354 int start;
1355 int num;
1356 int i;
1357
1358 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1359 /* Scan entire range */
1360 start = ethernet_phy_get(pep);
1361 num = 32;
1362 } else {
1363 /* Use phy addr specific to platform */
1364 start = phy_addr & 0x1f;
1365 num = 1;
1366 }
1367 phydev = NULL;
1368 for (i = 0; i < num; i++) {
1369 int addr = (start + i) & 0x1f;
1370 if (bus->phy_map[addr] == NULL)
1371 mdiobus_scan(bus, addr);
1372
1373 if (phydev == NULL) {
1374 phydev = bus->phy_map[addr];
1375 if (phydev != NULL)
1376 ethernet_phy_set_addr(pep, addr);
1377 }
1378 }
1379
1380 return phydev;
1381}
1382
1383static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex)
1384{
1385 struct phy_device *phy = pep->phy;
1386 ethernet_phy_reset(pep);
1387
f9a8f83b 1388 phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
a49f37ee
SS		 1389
1390 if (speed == 0) {
1391 phy->autoneg = AUTONEG_ENABLE;
1392 phy->speed = 0;
1393 phy->duplex = 0;
1394 phy->supported &= PHY_BASIC_FEATURES;
1395 phy->advertising = phy->supported | ADVERTISED_Autoneg;
1396 } else {
1397 phy->autoneg = AUTONEG_DISABLE;
1398 phy->advertising = 0;
1399 phy->speed = speed;
1400 phy->duplex = duplex;
1401 }
1402 phy_start_aneg(phy);
1403}
1404
1405static int ethernet_phy_setup(struct net_device *dev)
1406{
1407 struct pxa168_eth_private *pep = netdev_priv(dev);
1408
4169591f
DC		 1409 if (pep->pd->init)
1410 pep->pd->init();
a49f37ee
SS		 1411 pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f);
1412 if (pep->phy != NULL)
1413 phy_init(pep, pep->pd->speed, pep->pd->duplex);
1414 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1415
1416 return 0;
1417}
1418
1419static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1420{
1421 struct pxa168_eth_private *pep = netdev_priv(dev);
1422 int err;
1423
1424 err = phy_read_status(pep->phy);
1425 if (err == 0)
1426 err = phy_ethtool_gset(pep->phy, cmd);
1427
1428 return err;
1429}
1430
1431static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1432{
1433 struct pxa168_eth_private *pep = netdev_priv(dev);
1434
1435 return phy_ethtool_sset(pep->phy, cmd);
1436}
1437
1438static void pxa168_get_drvinfo(struct net_device *dev,
1439 struct ethtool_drvinfo *info)
1440{
7826d43f
JP		 1441 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1442 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
1443 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1444 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
a49f37ee
SS		 1445}
1446
a49f37ee
SS		 1447static const struct ethtool_ops pxa168_ethtool_ops = {
1448 .get_settings = pxa168_get_settings,
1449 .set_settings = pxa168_set_settings,
1450 .get_drvinfo = pxa168_get_drvinfo,
ed4ba4b5 1451 .get_link = ethtool_op_get_link,
1975a54b 1452 .get_ts_info = ethtool_op_get_ts_info,
a49f37ee
SS		 1453};
1454
1455static const struct net_device_ops pxa168_eth_netdev_ops = {
1456 .ndo_open = pxa168_eth_open,
1457 .ndo_stop = pxa168_eth_stop,
1458 .ndo_start_xmit = pxa168_eth_start_xmit,
1459 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1460 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1461 .ndo_validate_addr = eth_validate_addr,
1462 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1463 .ndo_change_mtu = pxa168_eth_change_mtu,
1464 .ndo_tx_timeout = pxa168_eth_tx_timeout,
1465};
1466
1467static int pxa168_eth_probe(struct platform_device *pdev)
1468{
1469 struct pxa168_eth_private *pep = NULL;
1470 struct net_device *dev = NULL;
1471 struct resource *res;
1472 struct clk *clk;
1473 int err;
1474
1475 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1476
1477 clk = clk_get(&pdev->dev, "MFUCLK");
1478 if (IS_ERR(clk)) {
1479 printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n",
1480 DRIVER_NAME);
1481 return -ENODEV;
1482 }
1483 clk_enable(clk);
1484
1485 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1486 if (!dev) {
1487 err = -ENOMEM;
945c7c73 1488 goto err_clk;
a49f37ee
SS		 1489 }
1490
1491 platform_set_drvdata(pdev, dev);
1492 pep = netdev_priv(dev);
1493 pep->dev = dev;
1494 pep->clk = clk;
1495 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1496 if (res == NULL) {
1497 err = -ENODEV;
945c7c73 1498 goto err_netdev;
a49f37ee 1499 }
28f65c11 1500 pep->base = ioremap(res->start, resource_size(res));
a49f37ee
SS		 1501 if (pep->base == NULL) {
1502 err = -ENOMEM;
945c7c73 1503 goto err_netdev;
a49f37ee
SS		 1504 }
1505 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1506 BUG_ON(!res);
1507 dev->irq = res->start;
1508 dev->netdev_ops = &pxa168_eth_netdev_ops;
1509 dev->watchdog_timeo = 2 * HZ;
1510 dev->base_addr = 0;
1511 SET_ETHTOOL_OPS(dev, &pxa168_ethtool_ops);
1512
1513 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1514
1515 printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME);
7ce5d222 1516 eth_hw_addr_random(dev);
a49f37ee 1517
e19eac0e 1518 pep->pd = dev_get_platdata(&pdev->dev);
a49f37ee
SS		 1519 pep->rx_ring_size = NUM_RX_DESCS;
1520 if (pep->pd->rx_queue_size)
1521 pep->rx_ring_size = pep->pd->rx_queue_size;
1522
1523 pep->tx_ring_size = NUM_TX_DESCS;
1524 if (pep->pd->tx_queue_size)
1525 pep->tx_ring_size = pep->pd->tx_queue_size;
1526
1527 pep->port_num = pep->pd->port_number;
1528 /* Hardware supports only 3 ports */
1529 BUG_ON(pep->port_num > 2);
1530 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1531
1532 memset(&pep->timeout, 0, sizeof(struct timer_list));
1533 init_timer(&pep->timeout);
1534 pep->timeout.function = rxq_refill_timer_wrapper;
1535 pep->timeout.data = (unsigned long)pep;
1536
1537 pep->smi_bus = mdiobus_alloc();
1538 if (pep->smi_bus == NULL) {
1539 err = -ENOMEM;
945c7c73 1540 goto err_base;
a49f37ee
SS		 1541 }
1542 pep->smi_bus->priv = pep;
1543 pep->smi_bus->name = "pxa168_eth smi";
1544 pep->smi_bus->read = pxa168_smi_read;
1545 pep->smi_bus->write = pxa168_smi_write;
d073a102
FF		 1546 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1547 pdev->name, pdev->id);
a49f37ee
SS		 1548 pep->smi_bus->parent = &pdev->dev;
1549 pep->smi_bus->phy_mask = 0xffffffff;
945c7c73
DC		 1550 err = mdiobus_register(pep->smi_bus);
1551 if (err)
1552 goto err_free_mdio;
1553
a49f37ee
SS		 1554 pxa168_init_hw(pep);
1555 err = ethernet_phy_setup(dev);
1556 if (err)
945c7c73 1557 goto err_mdiobus;
a49f37ee
SS		 1558 SET_NETDEV_DEV(dev, &pdev->dev);
1559 err = register_netdev(dev);
1560 if (err)
945c7c73 1561 goto err_mdiobus;
a49f37ee 1562 return 0;
945c7c73
DC		 1563
1564err_mdiobus:
1565 mdiobus_unregister(pep->smi_bus);
1566err_free_mdio:
1567 mdiobus_free(pep->smi_bus);
1568err_base:
1569 iounmap(pep->base);
1570err_netdev:
1571 free_netdev(dev);
1572err_clk:
1573 clk_disable(clk);
1574 clk_put(clk);
a49f37ee
SS		 1575 return err;
1576}
1577
1578static int pxa168_eth_remove(struct platform_device *pdev)
1579{
1580 struct net_device *dev = platform_get_drvdata(pdev);
1581 struct pxa168_eth_private *pep = netdev_priv(dev);
1582
1583 if (pep->htpr) {
1584 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1585 pep->htpr, pep->htpr_dma);
1586 pep->htpr = NULL;
1587 }
1588 if (pep->clk) {
1589 clk_disable(pep->clk);
1590 clk_put(pep->clk);
1591 pep->clk = NULL;
1592 }
1593 if (pep->phy != NULL)
1594 phy_detach(pep->phy);
1595
1596 iounmap(pep->base);
1597 pep->base = NULL;
9c01ae58
DK		 1598 mdiobus_unregister(pep->smi_bus);
1599 mdiobus_free(pep->smi_bus);
a49f37ee 1600 unregister_netdev(dev);
23f333a2 1601 cancel_work_sync(&pep->tx_timeout_task);
a49f37ee 1602 free_netdev(dev);
a49f37ee
SS		 1603 return 0;
1604}
1605
1606static void pxa168_eth_shutdown(struct platform_device *pdev)
1607{
1608 struct net_device *dev = platform_get_drvdata(pdev);
1609 eth_port_reset(dev);
1610}
1611
1612#ifdef CONFIG_PM
1613static int pxa168_eth_resume(struct platform_device *pdev)
1614{
1615 return -ENOSYS;
1616}
1617
1618static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1619{
1620 return -ENOSYS;
1621}
1622
1623#else
1624#define pxa168_eth_resume NULL
1625#define pxa168_eth_suspend NULL
1626#endif
1627
1628static struct platform_driver pxa168_eth_driver = {
1629 .probe = pxa168_eth_probe,
1630 .remove = pxa168_eth_remove,
1631 .shutdown = pxa168_eth_shutdown,
1632 .resume = pxa168_eth_resume,
1633 .suspend = pxa168_eth_suspend,
1634 .driver = {
1635 .name = DRIVER_NAME,
1636 },
1637};
1638
db62f684 1639module_platform_driver(pxa168_eth_driver);
a49f37ee
SS		 1640
1641MODULE_LICENSE("GPL");
1642MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1643MODULE_ALIAS("platform:pxa168_eth");
Linux kernel - Deliverables
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