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net: mv643xx_eth: use phy_init_hw to reset PHY
[deliverable/linux.git] / drivers / net / ethernet / marvell / pxa168_eth.c
CommitLineData
a49f37ee
SS		 1/*
2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
4 *
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
10206601 7 * Zhangfei Gao <zgao6@marvell.com>
a49f37ee
SS		 8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
0ab75ae8 22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
a49f37ee
SS		 23 */
24
25#include <linux/init.h>
26#include <linux/dma-mapping.h>
27#include <linux/in.h>
28#include <linux/ip.h>
29#include <linux/tcp.h>
30#include <linux/udp.h>
31#include <linux/etherdevice.h>
32#include <linux/bitops.h>
33#include <linux/delay.h>
34#include <linux/ethtool.h>
35#include <linux/platform_device.h>
36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/workqueue.h>
39#include <linux/clk.h>
40#include <linux/phy.h>
41#include <linux/io.h>
b7e43381 42#include <linux/interrupt.h>
a49f37ee
SS		 43#include <linux/types.h>
44#include <asm/pgtable.h>
a49f37ee
SS		 45#include <asm/cacheflush.h>
46#include <linux/pxa168_eth.h>
47
48#define DRIVER_NAME "pxa168-eth"
49#define DRIVER_VERSION "0.3"
50
51/*
52 * Registers
53 */
54
55#define PHY_ADDRESS 0x0000
56#define SMI 0x0010
57#define PORT_CONFIG 0x0400
58#define PORT_CONFIG_EXT 0x0408
59#define PORT_COMMAND 0x0410
60#define PORT_STATUS 0x0418
61#define HTPR 0x0428
62#define SDMA_CONFIG 0x0440
63#define SDMA_CMD 0x0448
64#define INT_CAUSE 0x0450
65#define INT_W_CLEAR 0x0454
66#define INT_MASK 0x0458
67#define ETH_F_RX_DESC_0 0x0480
68#define ETH_C_RX_DESC_0 0x04A0
69#define ETH_C_TX_DESC_1 0x04E4
70
71/* smi register */
72#define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
73#define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
74#define SMI_OP_W (0 << 26) /* Write operation */
75#define SMI_OP_R (1 << 26) /* Read operation */
76
77#define PHY_WAIT_ITERATIONS 10
78
79#define PXA168_ETH_PHY_ADDR_DEFAULT 0
80/* RX & TX descriptor command */
81#define BUF_OWNED_BY_DMA (1 << 31)
82
83/* RX descriptor status */
84#define RX_EN_INT (1 << 23)
85#define RX_FIRST_DESC (1 << 17)
86#define RX_LAST_DESC (1 << 16)
87#define RX_ERROR (1 << 15)
88
89/* TX descriptor command */
90#define TX_EN_INT (1 << 23)
91#define TX_GEN_CRC (1 << 22)
92#define TX_ZERO_PADDING (1 << 18)
93#define TX_FIRST_DESC (1 << 17)
94#define TX_LAST_DESC (1 << 16)
95#define TX_ERROR (1 << 15)
96
97/* SDMA_CMD */
98#define SDMA_CMD_AT (1 << 31)
99#define SDMA_CMD_TXDL (1 << 24)
100#define SDMA_CMD_TXDH (1 << 23)
101#define SDMA_CMD_AR (1 << 15)
102#define SDMA_CMD_ERD (1 << 7)
103
104/* Bit definitions of the Port Config Reg */
105#define PCR_HS (1 << 12)
106#define PCR_EN (1 << 7)
107#define PCR_PM (1 << 0)
108
109/* Bit definitions of the Port Config Extend Reg */
110#define PCXR_2BSM (1 << 28)
111#define PCXR_DSCP_EN (1 << 21)
112#define PCXR_MFL_1518 (0 << 14)
113#define PCXR_MFL_1536 (1 << 14)
114#define PCXR_MFL_2048 (2 << 14)
115#define PCXR_MFL_64K (3 << 14)
116#define PCXR_FLP (1 << 11)
117#define PCXR_PRIO_TX_OFF 3
118#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
119
120/* Bit definitions of the SDMA Config Reg */
121#define SDCR_BSZ_OFF 12
122#define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
123#define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
124#define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
125#define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
126#define SDCR_BLMR (1 << 6)
127#define SDCR_BLMT (1 << 7)
128#define SDCR_RIFB (1 << 9)
129#define SDCR_RC_OFF 2
130#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
131
132/*
133 * Bit definitions of the Interrupt Cause Reg
134 * and Interrupt MASK Reg is the same
135 */
136#define ICR_RXBUF (1 << 0)
137#define ICR_TXBUF_H (1 << 2)
138#define ICR_TXBUF_L (1 << 3)
139#define ICR_TXEND_H (1 << 6)
140#define ICR_TXEND_L (1 << 7)
141#define ICR_RXERR (1 << 8)
142#define ICR_TXERR_H (1 << 10)
143#define ICR_TXERR_L (1 << 11)
144#define ICR_TX_UDR (1 << 13)
145#define ICR_MII_CH (1 << 28)
146
147#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
148 ICR_TXERR_H | ICR_TXERR_L |\
149 ICR_TXEND_H | ICR_TXEND_L |\
150 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
151
152#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
153
154#define NUM_RX_DESCS 64
155#define NUM_TX_DESCS 64
156
157#define HASH_ADD 0
158#define HASH_DELETE 1
159#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
160#define HOP_NUMBER 12
161
162/* Bit definitions for Port status */
163#define PORT_SPEED_100 (1 << 0)
164#define FULL_DUPLEX (1 << 1)
165#define FLOW_CONTROL_ENABLED (1 << 2)
166#define LINK_UP (1 << 3)
167
168/* Bit definitions for work to be done */
169#define WORK_LINK (1 << 0)
170#define WORK_TX_DONE (1 << 1)
171
172/*
173 * Misc definitions.
174 */
175#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
176
177struct rx_desc {
178 u32 cmd_sts; /* Descriptor command status */
179 u16 byte_cnt; /* Descriptor buffer byte count */
180 u16 buf_size; /* Buffer size */
181 u32 buf_ptr; /* Descriptor buffer pointer */
182 u32 next_desc_ptr; /* Next descriptor pointer */
183};
184
185struct tx_desc {
186 u32 cmd_sts; /* Command/status field */
187 u16 reserved;
188 u16 byte_cnt; /* buffer byte count */
189 u32 buf_ptr; /* pointer to buffer for this descriptor */
190 u32 next_desc_ptr; /* Pointer to next descriptor */
191};
192
193struct pxa168_eth_private {
194 int port_num; /* User Ethernet port number */
195
196 int rx_resource_err; /* Rx ring resource error flag */
197
198 /* Next available and first returning Rx resource */
199 int rx_curr_desc_q, rx_used_desc_q;
200
201 /* Next available and first returning Tx resource */
202 int tx_curr_desc_q, tx_used_desc_q;
203
204 struct rx_desc *p_rx_desc_area;
205 dma_addr_t rx_desc_dma;
206 int rx_desc_area_size;
207 struct sk_buff **rx_skb;
208
209 struct tx_desc *p_tx_desc_area;
210 dma_addr_t tx_desc_dma;
211 int tx_desc_area_size;
212 struct sk_buff **tx_skb;
213
214 struct work_struct tx_timeout_task;
215
216 struct net_device *dev;
217 struct napi_struct napi;
218 u8 work_todo;
219 int skb_size;
220
a49f37ee
SS		 221 /* Size of Tx Ring per queue */
222 int tx_ring_size;
223 /* Number of tx descriptors in use */
224 int tx_desc_count;
225 /* Size of Rx Ring per queue */
226 int rx_ring_size;
227 /* Number of rx descriptors in use */
228 int rx_desc_count;
229
230 /*
231 * Used in case RX Ring is empty, which can occur when
232 * system does not have resources (skb's)
233 */
234 struct timer_list timeout;
235 struct mii_bus *smi_bus;
236 struct phy_device *phy;
237
238 /* clock */
239 struct clk *clk;
240 struct pxa168_eth_platform_data *pd;
241 /*
242 * Ethernet controller base address.
243 */
244 void __iomem *base;
245
246 /* Pointer to the hardware address filter table */
247 void *htpr;
248 dma_addr_t htpr_dma;
249};
250
251struct addr_table_entry {
252 __le32 lo;
253 __le32 hi;
254};
255
256/* Bit fields of a Hash Table Entry */
257enum hash_table_entry {
258 HASH_ENTRY_VALID = 1,
259 SKIP = 2,
260 HASH_ENTRY_RECEIVE_DISCARD = 4,
261 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
262};
263
264static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
265static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
266static int pxa168_init_hw(struct pxa168_eth_private *pep);
267static void eth_port_reset(struct net_device *dev);
268static void eth_port_start(struct net_device *dev);
269static int pxa168_eth_open(struct net_device *dev);
270static int pxa168_eth_stop(struct net_device *dev);
271static int ethernet_phy_setup(struct net_device *dev);
272
273static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
274{
275 return readl(pep->base + offset);
276}
277
278static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
279{
280 writel(data, pep->base + offset);
281}
282
283static void abort_dma(struct pxa168_eth_private *pep)
284{
285 int delay;
286 int max_retries = 40;
287
288 do {
289 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
290 udelay(100);
291
292 delay = 10;
293 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
294 && delay-- > 0) {
295 udelay(10);
296 }
297 } while (max_retries-- > 0 && delay <= 0);
298
299 if (max_retries <= 0)
300 printk(KERN_ERR "%s : DMA Stuck\n", __func__);
301}
302
303static int ethernet_phy_get(struct pxa168_eth_private *pep)
304{
305 unsigned int reg_data;
306
307 reg_data = rdl(pep, PHY_ADDRESS);
308
309 return (reg_data >> (5 * pep->port_num)) & 0x1f;
310}
311
312static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
313{
314 u32 reg_data;
315 int addr_shift = 5 * pep->port_num;
316
317 reg_data = rdl(pep, PHY_ADDRESS);
318 reg_data &= ~(0x1f << addr_shift);
319 reg_data |= (phy_addr & 0x1f) << addr_shift;
320 wrl(pep, PHY_ADDRESS, reg_data);
321}
322
323static void ethernet_phy_reset(struct pxa168_eth_private *pep)
324{
325 int data;
326
327 data = phy_read(pep->phy, MII_BMCR);
328 if (data < 0)
329 return;
330
331 data |= BMCR_RESET;
332 if (phy_write(pep->phy, MII_BMCR, data) < 0)
333 return;
334
335 do {
336 data = phy_read(pep->phy, MII_BMCR);
337 } while (data >= 0 && data & BMCR_RESET);
338}
339
340static void rxq_refill(struct net_device *dev)
341{
342 struct pxa168_eth_private *pep = netdev_priv(dev);
343 struct sk_buff *skb;
344 struct rx_desc *p_used_rx_desc;
345 int used_rx_desc;
346
347 while (pep->rx_desc_count < pep->rx_ring_size) {
348 int size;
349
c056b734 350 skb = netdev_alloc_skb(dev, pep->skb_size);
a49f37ee
SS		 351 if (!skb)
352 break;
353 if (SKB_DMA_REALIGN)
354 skb_reserve(skb, SKB_DMA_REALIGN);
355 pep->rx_desc_count++;
356 /* Get 'used' Rx descriptor */
357 used_rx_desc = pep->rx_used_desc_q;
358 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
511efbbb 359 size = skb_end_pointer(skb) - skb->data;
a49f37ee
SS		 360 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
361 skb->data,
362 size,
363 DMA_FROM_DEVICE);
364 p_used_rx_desc->buf_size = size;
365 pep->rx_skb[used_rx_desc] = skb;
366
367 /* Return the descriptor to DMA ownership */
368 wmb();
369 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
370 wmb();
371
372 /* Move the used descriptor pointer to the next descriptor */
373 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
374
375 /* Any Rx return cancels the Rx resource error status */
376 pep->rx_resource_err = 0;
377
378 skb_reserve(skb, ETH_HW_IP_ALIGN);
379 }
380
381 /*
382 * If RX ring is empty of SKB, set a timer to try allocating
383 * again at a later time.
384 */
385 if (pep->rx_desc_count == 0) {
386 pep->timeout.expires = jiffies + (HZ / 10);
387 add_timer(&pep->timeout);
388 }
389}
390
391static inline void rxq_refill_timer_wrapper(unsigned long data)
392{
393 struct pxa168_eth_private *pep = (void *)data;
394 napi_schedule(&pep->napi);
395}
396
397static inline u8 flip_8_bits(u8 x)
398{
399 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
400 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
401 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
402 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
403}
404
405static void nibble_swap_every_byte(unsigned char *mac_addr)
406{
407 int i;
408 for (i = 0; i < ETH_ALEN; i++) {
409 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
410 ((mac_addr[i] & 0xf0) >> 4);
411 }
412}
413
414static void inverse_every_nibble(unsigned char *mac_addr)
415{
416 int i;
417 for (i = 0; i < ETH_ALEN; i++)
418 mac_addr[i] = flip_8_bits(mac_addr[i]);
419}
420
421/*
422 * ----------------------------------------------------------------------------
423 * This function will calculate the hash function of the address.
424 * Inputs
425 * mac_addr_orig - MAC address.
426 * Outputs
427 * return the calculated entry.
428 */
429static u32 hash_function(unsigned char *mac_addr_orig)
430{
431 u32 hash_result;
432 u32 addr0;
433 u32 addr1;
434 u32 addr2;
435 u32 addr3;
436 unsigned char mac_addr[ETH_ALEN];
437
438 /* Make a copy of MAC address since we are going to performe bit
439 * operations on it
440 */
441 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
442
443 nibble_swap_every_byte(mac_addr);
444 inverse_every_nibble(mac_addr);
445
446 addr0 = (mac_addr[5] >> 2) & 0x3f;
447 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
448 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
449 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
450
451 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
452 hash_result = hash_result & 0x07ff;
453 return hash_result;
454}
455
456/*
457 * ----------------------------------------------------------------------------
458 * This function will add/del an entry to the address table.
459 * Inputs
460 * pep - ETHERNET .
461 * mac_addr - MAC address.
462 * skip - if 1, skip this address.Used in case of deleting an entry which is a
25985edc 463 * part of chain in the hash table.We can't just delete the entry since
a49f37ee
SS		 464 * that will break the chain.We need to defragment the tables time to
465 * time.
466 * rd - 0 Discard packet upon match.
467 * - 1 Receive packet upon match.
468 * Outputs
469 * address table entry is added/deleted.
470 * 0 if success.
471 * -ENOSPC if table full
472 */
473static int add_del_hash_entry(struct pxa168_eth_private *pep,
474 unsigned char *mac_addr,
475 u32 rd, u32 skip, int del)
476{
477 struct addr_table_entry *entry, *start;
478 u32 new_high;
479 u32 new_low;
480 u32 i;
481
482 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
483 | (((mac_addr[1] >> 0) & 0xf) << 11)
484 | (((mac_addr[0] >> 4) & 0xf) << 7)
485 | (((mac_addr[0] >> 0) & 0xf) << 3)
486 | (((mac_addr[3] >> 4) & 0x1) << 31)
487 | (((mac_addr[3] >> 0) & 0xf) << 27)
488 | (((mac_addr[2] >> 4) & 0xf) << 23)
489 | (((mac_addr[2] >> 0) & 0xf) << 19)
490 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
491 | HASH_ENTRY_VALID;
492
493 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
494 | (((mac_addr[5] >> 0) & 0xf) << 11)
495 | (((mac_addr[4] >> 4) & 0xf) << 7)
496 | (((mac_addr[4] >> 0) & 0xf) << 3)
497 | (((mac_addr[3] >> 5) & 0x7) << 0);
498
499 /*
500 * Pick the appropriate table, start scanning for free/reusable
501 * entries at the index obtained by hashing the specified MAC address
502 */
43d620c8 503 start = pep->htpr;
a49f37ee
SS		 504 entry = start + hash_function(mac_addr);
505 for (i = 0; i < HOP_NUMBER; i++) {
506 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
507 break;
508 } else {
509 /* if same address put in same position */
510 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
511 (new_low & 0xfffffff8)) &&
512 (le32_to_cpu(entry->hi) == new_high)) {
513 break;
514 }
515 }
516 if (entry == start + 0x7ff)
517 entry = start;
518 else
519 entry++;
520 }
521
522 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
523 (le32_to_cpu(entry->hi) != new_high) && del)
524 return 0;
525
526 if (i == HOP_NUMBER) {
527 if (!del) {
528 printk(KERN_INFO "%s: table section is full, need to "
529 "move to 16kB implementation?\n",
530 __FILE__);
531 return -ENOSPC;
532 } else
533 return 0;
534 }
535
536 /*
537 * Update the selected entry
538 */
539 if (del) {
540 entry->hi = 0;
541 entry->lo = 0;
542 } else {
543 entry->hi = cpu_to_le32(new_high);
544 entry->lo = cpu_to_le32(new_low);
545 }
546
547 return 0;
548}
549
550/*
551 * ----------------------------------------------------------------------------
552 * Create an addressTable entry from MAC address info
553 * found in the specifed net_device struct
554 *
555 * Input : pointer to ethernet interface network device structure
556 * Output : N/A
557 */
558static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
559 unsigned char *oaddr,
560 unsigned char *addr)
561{
562 /* Delete old entry */
563 if (oaddr)
564 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
565 /* Add new entry */
566 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
567}
568
569static int init_hash_table(struct pxa168_eth_private *pep)
570{
571 /*
572 * Hardware expects CPU to build a hash table based on a predefined
573 * hash function and populate it based on hardware address. The
574 * location of the hash table is identified by 32-bit pointer stored
575 * in HTPR internal register. Two possible sizes exists for the hash
576 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
577 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
578 * 1/2kB.
579 */
580 /* TODO: Add support for 8kB hash table and alternative hash
581 * function.Driver can dynamically switch to them if the 1/2kB hash
582 * table is full.
583 */
584 if (pep->htpr == NULL) {
ede23fa8
JP		 585 pep->htpr = dma_zalloc_coherent(pep->dev->dev.parent,
586 HASH_ADDR_TABLE_SIZE,
587 &pep->htpr_dma, GFP_KERNEL);
a49f37ee
SS		 588 if (pep->htpr == NULL)
589 return -ENOMEM;
1f9061d2
JP		 590 } else {
591 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
a49f37ee 592 }
a49f37ee
SS		 593 wrl(pep, HTPR, pep->htpr_dma);
594 return 0;
595}
596
597static void pxa168_eth_set_rx_mode(struct net_device *dev)
598{
599 struct pxa168_eth_private *pep = netdev_priv(dev);
600 struct netdev_hw_addr *ha;
601 u32 val;
602
603 val = rdl(pep, PORT_CONFIG);
604 if (dev->flags & IFF_PROMISC)
605 val |= PCR_PM;
606 else
607 val &= ~PCR_PM;
608 wrl(pep, PORT_CONFIG, val);
609
610 /*
611 * Remove the old list of MAC address and add dev->addr
612 * and multicast address.
613 */
614 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
615 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
616
617 netdev_for_each_mc_addr(ha, dev)
618 update_hash_table_mac_address(pep, NULL, ha->addr);
619}
620
621static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
622{
623 struct sockaddr *sa = addr;
624 struct pxa168_eth_private *pep = netdev_priv(dev);
625 unsigned char oldMac[ETH_ALEN];
626
627 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 628 return -EADDRNOTAVAIL;
a49f37ee
SS		 629 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
630 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
631 netif_addr_lock_bh(dev);
632 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
633 netif_addr_unlock_bh(dev);
634 return 0;
635}
636
637static void eth_port_start(struct net_device *dev)
638{
639 unsigned int val = 0;
640 struct pxa168_eth_private *pep = netdev_priv(dev);
641 int tx_curr_desc, rx_curr_desc;
642
643 /* Perform PHY reset, if there is a PHY. */
644 if (pep->phy != NULL) {
645 struct ethtool_cmd cmd;
646
647 pxa168_get_settings(pep->dev, &cmd);
648 ethernet_phy_reset(pep);
649 pxa168_set_settings(pep->dev, &cmd);
650 }
651
652 /* Assignment of Tx CTRP of given queue */
653 tx_curr_desc = pep->tx_curr_desc_q;
654 wrl(pep, ETH_C_TX_DESC_1,
b2bc8563 655 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
a49f37ee
SS		 656
657 /* Assignment of Rx CRDP of given queue */
658 rx_curr_desc = pep->rx_curr_desc_q;
659 wrl(pep, ETH_C_RX_DESC_0,
b2bc8563 660 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 661
662 wrl(pep, ETH_F_RX_DESC_0,
b2bc8563 663 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 664
665 /* Clear all interrupts */
666 wrl(pep, INT_CAUSE, 0);
667
668 /* Enable all interrupts for receive, transmit and error. */
669 wrl(pep, INT_MASK, ALL_INTS);
670
671 val = rdl(pep, PORT_CONFIG);
672 val |= PCR_EN;
673 wrl(pep, PORT_CONFIG, val);
674
675 /* Start RX DMA engine */
676 val = rdl(pep, SDMA_CMD);
677 val |= SDMA_CMD_ERD;
678 wrl(pep, SDMA_CMD, val);
679}
680
681static void eth_port_reset(struct net_device *dev)
682{
683 struct pxa168_eth_private *pep = netdev_priv(dev);
684 unsigned int val = 0;
685
686 /* Stop all interrupts for receive, transmit and error. */
687 wrl(pep, INT_MASK, 0);
688
689 /* Clear all interrupts */
690 wrl(pep, INT_CAUSE, 0);
691
692 /* Stop RX DMA */
693 val = rdl(pep, SDMA_CMD);
694 val &= ~SDMA_CMD_ERD; /* abort dma command */
695
696 /* Abort any transmit and receive operations and put DMA
697 * in idle state.
698 */
699 abort_dma(pep);
700
701 /* Disable port */
702 val = rdl(pep, PORT_CONFIG);
703 val &= ~PCR_EN;
704 wrl(pep, PORT_CONFIG, val);
705}
706
707/*
708 * txq_reclaim - Free the tx desc data for completed descriptors
709 * If force is non-zero, frees uncompleted descriptors as well
710 */
711static int txq_reclaim(struct net_device *dev, int force)
712{
713 struct pxa168_eth_private *pep = netdev_priv(dev);
714 struct tx_desc *desc;
715 u32 cmd_sts;
716 struct sk_buff *skb;
717 int tx_index;
718 dma_addr_t addr;
719 int count;
720 int released = 0;
721
722 netif_tx_lock(dev);
723
724 pep->work_todo &= ~WORK_TX_DONE;
725 while (pep->tx_desc_count > 0) {
726 tx_index = pep->tx_used_desc_q;
727 desc = &pep->p_tx_desc_area[tx_index];
728 cmd_sts = desc->cmd_sts;
729 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
730 if (released > 0) {
731 goto txq_reclaim_end;
732 } else {
733 released = -1;
734 goto txq_reclaim_end;
735 }
736 }
737 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
738 pep->tx_desc_count--;
739 addr = desc->buf_ptr;
740 count = desc->byte_cnt;
741 skb = pep->tx_skb[tx_index];
742 if (skb)
743 pep->tx_skb[tx_index] = NULL;
744
745 if (cmd_sts & TX_ERROR) {
746 if (net_ratelimit())
747 printk(KERN_ERR "%s: Error in TX\n", dev->name);
748 dev->stats.tx_errors++;
749 }
750 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
751 if (skb)
752 dev_kfree_skb_irq(skb);
753 released++;
754 }
755txq_reclaim_end:
756 netif_tx_unlock(dev);
757 return released;
758}
759
760static void pxa168_eth_tx_timeout(struct net_device *dev)
761{
762 struct pxa168_eth_private *pep = netdev_priv(dev);
763
764 printk(KERN_INFO "%s: TX timeout desc_count %d\n",
765 dev->name, pep->tx_desc_count);
766
767 schedule_work(&pep->tx_timeout_task);
768}
769
770static void pxa168_eth_tx_timeout_task(struct work_struct *work)
771{
772 struct pxa168_eth_private *pep = container_of(work,
773 struct pxa168_eth_private,
774 tx_timeout_task);
775 struct net_device *dev = pep->dev;
776 pxa168_eth_stop(dev);
777 pxa168_eth_open(dev);
778}
779
780static int rxq_process(struct net_device *dev, int budget)
781{
782 struct pxa168_eth_private *pep = netdev_priv(dev);
783 struct net_device_stats *stats = &dev->stats;
784 unsigned int received_packets = 0;
785 struct sk_buff *skb;
786
787 while (budget-- > 0) {
788 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
789 struct rx_desc *rx_desc;
790 unsigned int cmd_sts;
791
792 /* Do not process Rx ring in case of Rx ring resource error */
793 if (pep->rx_resource_err)
794 break;
795 rx_curr_desc = pep->rx_curr_desc_q;
796 rx_used_desc = pep->rx_used_desc_q;
797 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
798 cmd_sts = rx_desc->cmd_sts;
799 rmb();
800 if (cmd_sts & (BUF_OWNED_BY_DMA))
801 break;
802 skb = pep->rx_skb[rx_curr_desc];
803 pep->rx_skb[rx_curr_desc] = NULL;
804
805 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
806 pep->rx_curr_desc_q = rx_next_curr_desc;
807
808 /* Rx descriptors exhausted. */
809 /* Set the Rx ring resource error flag */
810 if (rx_next_curr_desc == rx_used_desc)
811 pep->rx_resource_err = 1;
812 pep->rx_desc_count--;
813 dma_unmap_single(NULL, rx_desc->buf_ptr,
814 rx_desc->buf_size,
815 DMA_FROM_DEVICE);
816 received_packets++;
817 /*
818 * Update statistics.
819 * Note byte count includes 4 byte CRC count
820 */
821 stats->rx_packets++;
822 stats->rx_bytes += rx_desc->byte_cnt;
823 /*
824 * In case received a packet without first / last bits on OR
825 * the error summary bit is on, the packets needs to be droped.
826 */
827 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
828 (RX_FIRST_DESC | RX_LAST_DESC))
829 || (cmd_sts & RX_ERROR)) {
830
831 stats->rx_dropped++;
832 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
833 (RX_FIRST_DESC | RX_LAST_DESC)) {
834 if (net_ratelimit())
835 printk(KERN_ERR
836 "%s: Rx pkt on multiple desc\n",
837 dev->name);
838 }
839 if (cmd_sts & RX_ERROR)
840 stats->rx_errors++;
841 dev_kfree_skb_irq(skb);
842 } else {
843 /*
844 * The -4 is for the CRC in the trailer of the
845 * received packet
846 */
847 skb_put(skb, rx_desc->byte_cnt - 4);
848 skb->protocol = eth_type_trans(skb, dev);
849 netif_receive_skb(skb);
850 }
a49f37ee
SS		 851 }
852 /* Fill RX ring with skb's */
853 rxq_refill(dev);
854 return received_packets;
855}
856
857static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
858 struct net_device *dev)
859{
860 u32 icr;
861 int ret = 0;
862
863 icr = rdl(pep, INT_CAUSE);
864 if (icr == 0)
865 return IRQ_NONE;
866
867 wrl(pep, INT_CAUSE, ~icr);
868 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
869 pep->work_todo |= WORK_TX_DONE;
870 ret = 1;
871 }
872 if (icr & ICR_RXBUF)
873 ret = 1;
874 if (icr & ICR_MII_CH) {
875 pep->work_todo |= WORK_LINK;
876 ret = 1;
877 }
878 return ret;
879}
880
881static void handle_link_event(struct pxa168_eth_private *pep)
882{
883 struct net_device *dev = pep->dev;
884 u32 port_status;
885 int speed;
886 int duplex;
887 int fc;
888
889 port_status = rdl(pep, PORT_STATUS);
890 if (!(port_status & LINK_UP)) {
891 if (netif_carrier_ok(dev)) {
892 printk(KERN_INFO "%s: link down\n", dev->name);
893 netif_carrier_off(dev);
894 txq_reclaim(dev, 1);
895 }
896 return;
897 }
898 if (port_status & PORT_SPEED_100)
899 speed = 100;
900 else
901 speed = 10;
902
903 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
904 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
905 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
906 "flow control %sabled\n", dev->name,
907 speed, duplex ? "full" : "half", fc ? "en" : "dis");
908 if (!netif_carrier_ok(dev))
909 netif_carrier_on(dev);
910}
911
912static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
913{
914 struct net_device *dev = (struct net_device *)dev_id;
915 struct pxa168_eth_private *pep = netdev_priv(dev);
916
917 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
918 return IRQ_NONE;
919 /* Disable interrupts */
920 wrl(pep, INT_MASK, 0);
921 napi_schedule(&pep->napi);
922 return IRQ_HANDLED;
923}
924
925static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
926{
927 int skb_size;
928
929 /*
930 * Reserve 2+14 bytes for an ethernet header (the hardware
931 * automatically prepends 2 bytes of dummy data to each
932 * received packet), 16 bytes for up to four VLAN tags, and
933 * 4 bytes for the trailing FCS -- 36 bytes total.
934 */
935 skb_size = pep->dev->mtu + 36;
936
937 /*
938 * Make sure that the skb size is a multiple of 8 bytes, as
939 * the lower three bits of the receive descriptor's buffer
940 * size field are ignored by the hardware.
941 */
942 pep->skb_size = (skb_size + 7) & ~7;
943
944 /*
945 * If NET_SKB_PAD is smaller than a cache line,
946 * netdev_alloc_skb() will cause skb->data to be misaligned
947 * to a cache line boundary. If this is the case, include
948 * some extra space to allow re-aligning the data area.
949 */
950 pep->skb_size += SKB_DMA_REALIGN;
951
952}
953
954static int set_port_config_ext(struct pxa168_eth_private *pep)
955{
956 int skb_size;
957
958 pxa168_eth_recalc_skb_size(pep);
959 if (pep->skb_size <= 1518)
960 skb_size = PCXR_MFL_1518;
961 else if (pep->skb_size <= 1536)
962 skb_size = PCXR_MFL_1536;
963 else if (pep->skb_size <= 2048)
964 skb_size = PCXR_MFL_2048;
965 else
966 skb_size = PCXR_MFL_64K;
967
968 /* Extended Port Configuration */
969 wrl(pep,
970 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
971 PCXR_DSCP_EN | /* Enable DSCP in IP */
972 skb_size | PCXR_FLP | /* do not force link pass */
973 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
974
975 return 0;
976}
977
978static int pxa168_init_hw(struct pxa168_eth_private *pep)
979{
980 int err = 0;
981
982 /* Disable interrupts */
983 wrl(pep, INT_MASK, 0);
984 wrl(pep, INT_CAUSE, 0);
985 /* Write to ICR to clear interrupts. */
986 wrl(pep, INT_W_CLEAR, 0);
987 /* Abort any transmit and receive operations and put DMA
988 * in idle state.
989 */
990 abort_dma(pep);
991 /* Initialize address hash table */
992 err = init_hash_table(pep);
993 if (err)
994 return err;
995 /* SDMA configuration */
996 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
997 SDCR_RIFB | /* Rx interrupt on frame */
998 SDCR_BLMT | /* Little endian transmit */
999 SDCR_BLMR | /* Little endian receive */
1000 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
1001 /* Port Configuration */
1002 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
1003 set_port_config_ext(pep);
1004
1005 return err;
1006}
1007
1008static int rxq_init(struct net_device *dev)
1009{
1010 struct pxa168_eth_private *pep = netdev_priv(dev);
1011 struct rx_desc *p_rx_desc;
1012 int size = 0, i = 0;
1013 int rx_desc_num = pep->rx_ring_size;
1014
1015 /* Allocate RX skb rings */
451bff29 1016 pep->rx_skb = kzalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
a49f37ee 1017 GFP_KERNEL);
e404decb 1018 if (!pep->rx_skb)
a49f37ee 1019 return -ENOMEM;
e404decb 1020
a49f37ee
SS		 1021 /* Allocate RX ring */
1022 pep->rx_desc_count = 0;
1023 size = pep->rx_ring_size * sizeof(struct rx_desc);
1024 pep->rx_desc_area_size = size;
ede23fa8
JP		 1025 pep->p_rx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1026 &pep->rx_desc_dma,
1027 GFP_KERNEL);
d0320f75 1028 if (!pep->p_rx_desc_area)
a49f37ee 1029 goto out;
d0320f75 1030
a49f37ee 1031 /* initialize the next_desc_ptr links in the Rx descriptors ring */
64699336 1032 p_rx_desc = pep->p_rx_desc_area;
a49f37ee
SS		 1033 for (i = 0; i < rx_desc_num; i++) {
1034 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1035 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1036 }
1037 /* Save Rx desc pointer to driver struct. */
1038 pep->rx_curr_desc_q = 0;
1039 pep->rx_used_desc_q = 0;
1040 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1041 return 0;
1042out:
1043 kfree(pep->rx_skb);
1044 return -ENOMEM;
1045}
1046
1047static void rxq_deinit(struct net_device *dev)
1048{
1049 struct pxa168_eth_private *pep = netdev_priv(dev);
1050 int curr;
1051
1052 /* Free preallocated skb's on RX rings */
1053 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1054 if (pep->rx_skb[curr]) {
1055 dev_kfree_skb(pep->rx_skb[curr]);
1056 pep->rx_desc_count--;
1057 }
1058 }
1059 if (pep->rx_desc_count)
1060 printk(KERN_ERR
1061 "Error in freeing Rx Ring. %d skb's still\n",
1062 pep->rx_desc_count);
1063 /* Free RX ring */
1064 if (pep->p_rx_desc_area)
1065 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1066 pep->p_rx_desc_area, pep->rx_desc_dma);
1067 kfree(pep->rx_skb);
1068}
1069
1070static int txq_init(struct net_device *dev)
1071{
1072 struct pxa168_eth_private *pep = netdev_priv(dev);
1073 struct tx_desc *p_tx_desc;
1074 int size = 0, i = 0;
1075 int tx_desc_num = pep->tx_ring_size;
1076
451bff29 1077 pep->tx_skb = kzalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
a49f37ee 1078 GFP_KERNEL);
e404decb 1079 if (!pep->tx_skb)
a49f37ee 1080 return -ENOMEM;
e404decb 1081
a49f37ee
SS		 1082 /* Allocate TX ring */
1083 pep->tx_desc_count = 0;
1084 size = pep->tx_ring_size * sizeof(struct tx_desc);
1085 pep->tx_desc_area_size = size;
ede23fa8
JP		 1086 pep->p_tx_desc_area = dma_zalloc_coherent(pep->dev->dev.parent, size,
1087 &pep->tx_desc_dma,
1088 GFP_KERNEL);
d0320f75 1089 if (!pep->p_tx_desc_area)
a49f37ee 1090 goto out;
a49f37ee 1091 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
64699336 1092 p_tx_desc = pep->p_tx_desc_area;
a49f37ee
SS		 1093 for (i = 0; i < tx_desc_num; i++) {
1094 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1095 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1096 }
1097 pep->tx_curr_desc_q = 0;
1098 pep->tx_used_desc_q = 0;
1099 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1100 return 0;
1101out:
1102 kfree(pep->tx_skb);
1103 return -ENOMEM;
1104}
1105
1106static void txq_deinit(struct net_device *dev)
1107{
1108 struct pxa168_eth_private *pep = netdev_priv(dev);
1109
1110 /* Free outstanding skb's on TX ring */
1111 txq_reclaim(dev, 1);
1112 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1113 /* Free TX ring */
1114 if (pep->p_tx_desc_area)
1115 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1116 pep->p_tx_desc_area, pep->tx_desc_dma);
1117 kfree(pep->tx_skb);
1118}
1119
1120static int pxa168_eth_open(struct net_device *dev)
1121{
1122 struct pxa168_eth_private *pep = netdev_priv(dev);
1123 int err;
1124
599c2e1f 1125 err = request_irq(dev->irq, pxa168_eth_int_handler, 0, dev->name, dev);
a49f37ee 1126 if (err) {
f7b4fb22 1127 dev_err(&dev->dev, "can't assign irq\n");
a49f37ee
SS		 1128 return -EAGAIN;
1129 }
1130 pep->rx_resource_err = 0;
1131 err = rxq_init(dev);
1132 if (err != 0)
1133 goto out_free_irq;
1134 err = txq_init(dev);
1135 if (err != 0)
1136 goto out_free_rx_skb;
1137 pep->rx_used_desc_q = 0;
1138 pep->rx_curr_desc_q = 0;
1139
1140 /* Fill RX ring with skb's */
1141 rxq_refill(dev);
1142 pep->rx_used_desc_q = 0;
1143 pep->rx_curr_desc_q = 0;
1144 netif_carrier_off(dev);
1145 eth_port_start(dev);
1146 napi_enable(&pep->napi);
1147 return 0;
1148out_free_rx_skb:
1149 rxq_deinit(dev);
1150out_free_irq:
1151 free_irq(dev->irq, dev);
1152 return err;
1153}
1154
1155static int pxa168_eth_stop(struct net_device *dev)
1156{
1157 struct pxa168_eth_private *pep = netdev_priv(dev);
1158 eth_port_reset(dev);
1159
1160 /* Disable interrupts */
1161 wrl(pep, INT_MASK, 0);
1162 wrl(pep, INT_CAUSE, 0);
1163 /* Write to ICR to clear interrupts. */
1164 wrl(pep, INT_W_CLEAR, 0);
1165 napi_disable(&pep->napi);
1166 del_timer_sync(&pep->timeout);
1167 netif_carrier_off(dev);
1168 free_irq(dev->irq, dev);
1169 rxq_deinit(dev);
1170 txq_deinit(dev);
1171
1172 return 0;
1173}
1174
1175static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1176{
1177 int retval;
1178 struct pxa168_eth_private *pep = netdev_priv(dev);
1179
1180 if ((mtu > 9500) || (mtu < 68))
1181 return -EINVAL;
1182
1183 dev->mtu = mtu;
1184 retval = set_port_config_ext(pep);
1185
1186 if (!netif_running(dev))
1187 return 0;
1188
1189 /*
1190 * Stop and then re-open the interface. This will allocate RX
1191 * skbs of the new MTU.
1192 * There is a possible danger that the open will not succeed,
1193 * due to memory being full.
1194 */
1195 pxa168_eth_stop(dev);
1196 if (pxa168_eth_open(dev)) {
f7b4fb22
JP		 1197 dev_err(&dev->dev,
1198 "fatal error on re-opening device after MTU change\n");
a49f37ee
SS		 1199 }
1200
1201 return 0;
1202}
1203
1204static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1205{
1206 int tx_desc_curr;
1207
1208 tx_desc_curr = pep->tx_curr_desc_q;
1209 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1210 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1211 pep->tx_desc_count++;
1212
1213 return tx_desc_curr;
1214}
1215
1216static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1217{
1218 struct pxa168_eth_private *pep =
1219 container_of(napi, struct pxa168_eth_private, napi);
1220 struct net_device *dev = pep->dev;
1221 int work_done = 0;
1222
1223 if (unlikely(pep->work_todo & WORK_LINK)) {
1224 pep->work_todo &= ~(WORK_LINK);
1225 handle_link_event(pep);
1226 }
1227 /*
1228 * We call txq_reclaim every time since in NAPI interupts are disabled
1229 * and due to this we miss the TX_DONE interrupt,which is not updated in
1230 * interrupt status register.
1231 */
1232 txq_reclaim(dev, 0);
1233 if (netif_queue_stopped(dev)
1234 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1235 netif_wake_queue(dev);
1236 }
1237 work_done = rxq_process(dev, budget);
1238 if (work_done < budget) {
1239 napi_complete(napi);
1240 wrl(pep, INT_MASK, ALL_INTS);
1241 }
1242
1243 return work_done;
1244}
1245
1246static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1247{
1248 struct pxa168_eth_private *pep = netdev_priv(dev);
1249 struct net_device_stats *stats = &dev->stats;
1250 struct tx_desc *desc;
1251 int tx_index;
1252 int length;
1253
1254 tx_index = eth_alloc_tx_desc_index(pep);
1255 desc = &pep->p_tx_desc_area[tx_index];
1256 length = skb->len;
1257 pep->tx_skb[tx_index] = skb;
1258 desc->byte_cnt = length;
1259 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1f6e44a6
RC		 1260
1261 skb_tx_timestamp(skb);
1262
a49f37ee
SS		 1263 wmb();
1264 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1265 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1266 wmb();
1267 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1268
38442040 1269 stats->tx_bytes += length;
a49f37ee
SS		 1270 stats->tx_packets++;
1271 dev->trans_start = jiffies;
1272 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1273 /* We handled the current skb, but now we are out of space.*/
1274 netif_stop_queue(dev);
1275 }
1276
1277 return NETDEV_TX_OK;
1278}
1279
1280static int smi_wait_ready(struct pxa168_eth_private *pep)
1281{
1282 int i = 0;
1283
1284 /* wait for the SMI register to become available */
1285 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1286 if (i == PHY_WAIT_ITERATIONS)
1287 return -ETIMEDOUT;
1288 msleep(10);
1289 }
1290
1291 return 0;
1292}
1293
1294static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1295{
1296 struct pxa168_eth_private *pep = bus->priv;
1297 int i = 0;
1298 int val;
1299
1300 if (smi_wait_ready(pep)) {
1301 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1302 return -ETIMEDOUT;
1303 }
1304 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1305 /* now wait for the data to be valid */
1306 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1307 if (i == PHY_WAIT_ITERATIONS) {
1308 printk(KERN_WARNING
1309 "pxa168_eth: SMI bus read not valid\n");
1310 return -ENODEV;
1311 }
1312 msleep(10);
1313 }
1314
1315 return val & 0xffff;
1316}
1317
1318static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1319 u16 value)
1320{
1321 struct pxa168_eth_private *pep = bus->priv;
1322
1323 if (smi_wait_ready(pep)) {
1324 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1325 return -ETIMEDOUT;
1326 }
1327
1328 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1329 SMI_OP_W | (value & 0xffff));
1330
1331 if (smi_wait_ready(pep)) {
1332 printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n");
1333 return -ETIMEDOUT;
1334 }
1335
1336 return 0;
1337}
1338
1339static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1340 int cmd)
1341{
1342 struct pxa168_eth_private *pep = netdev_priv(dev);
1343 if (pep->phy != NULL)
4f2c8510 1344 return phy_mii_ioctl(pep->phy, ifr, cmd);
a49f37ee
SS		 1345
1346 return -EOPNOTSUPP;
1347}
1348
1349static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1350{
1351 struct mii_bus *bus = pep->smi_bus;
1352 struct phy_device *phydev;
1353 int start;
1354 int num;
1355 int i;
1356
1357 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1358 /* Scan entire range */
1359 start = ethernet_phy_get(pep);
1360 num = 32;
1361 } else {
1362 /* Use phy addr specific to platform */
1363 start = phy_addr & 0x1f;
1364 num = 1;
1365 }
1366 phydev = NULL;
1367 for (i = 0; i < num; i++) {
1368 int addr = (start + i) & 0x1f;
1369 if (bus->phy_map[addr] == NULL)
1370 mdiobus_scan(bus, addr);
1371
1372 if (phydev == NULL) {
1373 phydev = bus->phy_map[addr];
1374 if (phydev != NULL)
1375 ethernet_phy_set_addr(pep, addr);
1376 }
1377 }
1378
1379 return phydev;
1380}
1381
1382static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex)
1383{
1384 struct phy_device *phy = pep->phy;
1385 ethernet_phy_reset(pep);
1386
f9a8f83b 1387 phy_attach(pep->dev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
a49f37ee
SS		 1388
1389 if (speed == 0) {
1390 phy->autoneg = AUTONEG_ENABLE;
1391 phy->speed = 0;
1392 phy->duplex = 0;
1393 phy->supported &= PHY_BASIC_FEATURES;
1394 phy->advertising = phy->supported | ADVERTISED_Autoneg;
1395 } else {
1396 phy->autoneg = AUTONEG_DISABLE;
1397 phy->advertising = 0;
1398 phy->speed = speed;
1399 phy->duplex = duplex;
1400 }
1401 phy_start_aneg(phy);
1402}
1403
1404static int ethernet_phy_setup(struct net_device *dev)
1405{
1406 struct pxa168_eth_private *pep = netdev_priv(dev);
1407
4169591f
DC		 1408 if (pep->pd->init)
1409 pep->pd->init();
a49f37ee
SS		 1410 pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f);
1411 if (pep->phy != NULL)
1412 phy_init(pep, pep->pd->speed, pep->pd->duplex);
1413 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1414
1415 return 0;
1416}
1417
1418static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1419{
1420 struct pxa168_eth_private *pep = netdev_priv(dev);
1421 int err;
1422
1423 err = phy_read_status(pep->phy);
1424 if (err == 0)
1425 err = phy_ethtool_gset(pep->phy, cmd);
1426
1427 return err;
1428}
1429
1430static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1431{
1432 struct pxa168_eth_private *pep = netdev_priv(dev);
1433
1434 return phy_ethtool_sset(pep->phy, cmd);
1435}
1436
1437static void pxa168_get_drvinfo(struct net_device *dev,
1438 struct ethtool_drvinfo *info)
1439{
7826d43f
JP		 1440 strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1441 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
1442 strlcpy(info->fw_version, "N/A", sizeof(info->fw_version));
1443 strlcpy(info->bus_info, "N/A", sizeof(info->bus_info));
a49f37ee
SS		 1444}
1445
a49f37ee
SS		 1446static const struct ethtool_ops pxa168_ethtool_ops = {
1447 .get_settings = pxa168_get_settings,
1448 .set_settings = pxa168_set_settings,
1449 .get_drvinfo = pxa168_get_drvinfo,
ed4ba4b5 1450 .get_link = ethtool_op_get_link,
1975a54b 1451 .get_ts_info = ethtool_op_get_ts_info,
a49f37ee
SS		 1452};
1453
1454static const struct net_device_ops pxa168_eth_netdev_ops = {
1455 .ndo_open = pxa168_eth_open,
1456 .ndo_stop = pxa168_eth_stop,
1457 .ndo_start_xmit = pxa168_eth_start_xmit,
1458 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1459 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1460 .ndo_validate_addr = eth_validate_addr,
1461 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1462 .ndo_change_mtu = pxa168_eth_change_mtu,
1463 .ndo_tx_timeout = pxa168_eth_tx_timeout,
1464};
1465
1466static int pxa168_eth_probe(struct platform_device *pdev)
1467{
1468 struct pxa168_eth_private *pep = NULL;
1469 struct net_device *dev = NULL;
1470 struct resource *res;
1471 struct clk *clk;
1472 int err;
1473
1474 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1475
1476 clk = clk_get(&pdev->dev, "MFUCLK");
1477 if (IS_ERR(clk)) {
1478 printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n",
1479 DRIVER_NAME);
1480 return -ENODEV;
1481 }
1482 clk_enable(clk);
1483
1484 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1485 if (!dev) {
1486 err = -ENOMEM;
945c7c73 1487 goto err_clk;
a49f37ee
SS		 1488 }
1489
1490 platform_set_drvdata(pdev, dev);
1491 pep = netdev_priv(dev);
1492 pep->dev = dev;
1493 pep->clk = clk;
1494 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495 if (res == NULL) {
1496 err = -ENODEV;
945c7c73 1497 goto err_netdev;
a49f37ee 1498 }
28f65c11 1499 pep->base = ioremap(res->start, resource_size(res));
a49f37ee
SS		 1500 if (pep->base == NULL) {
1501 err = -ENOMEM;
945c7c73 1502 goto err_netdev;
a49f37ee
SS		 1503 }
1504 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1505 BUG_ON(!res);
1506 dev->irq = res->start;
1507 dev->netdev_ops = &pxa168_eth_netdev_ops;
1508 dev->watchdog_timeo = 2 * HZ;
1509 dev->base_addr = 0;
1510 SET_ETHTOOL_OPS(dev, &pxa168_ethtool_ops);
1511
1512 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1513
1514 printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME);
7ce5d222 1515 eth_hw_addr_random(dev);
a49f37ee 1516
e19eac0e 1517 pep->pd = dev_get_platdata(&pdev->dev);
a49f37ee
SS		 1518 pep->rx_ring_size = NUM_RX_DESCS;
1519 if (pep->pd->rx_queue_size)
1520 pep->rx_ring_size = pep->pd->rx_queue_size;
1521
1522 pep->tx_ring_size = NUM_TX_DESCS;
1523 if (pep->pd->tx_queue_size)
1524 pep->tx_ring_size = pep->pd->tx_queue_size;
1525
1526 pep->port_num = pep->pd->port_number;
1527 /* Hardware supports only 3 ports */
1528 BUG_ON(pep->port_num > 2);
1529 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1530
1531 memset(&pep->timeout, 0, sizeof(struct timer_list));
1532 init_timer(&pep->timeout);
1533 pep->timeout.function = rxq_refill_timer_wrapper;
1534 pep->timeout.data = (unsigned long)pep;
1535
1536 pep->smi_bus = mdiobus_alloc();
1537 if (pep->smi_bus == NULL) {
1538 err = -ENOMEM;
945c7c73 1539 goto err_base;
a49f37ee
SS		 1540 }
1541 pep->smi_bus->priv = pep;
1542 pep->smi_bus->name = "pxa168_eth smi";
1543 pep->smi_bus->read = pxa168_smi_read;
1544 pep->smi_bus->write = pxa168_smi_write;
d073a102
FF		 1545 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1546 pdev->name, pdev->id);
a49f37ee
SS		 1547 pep->smi_bus->parent = &pdev->dev;
1548 pep->smi_bus->phy_mask = 0xffffffff;
945c7c73
DC		 1549 err = mdiobus_register(pep->smi_bus);
1550 if (err)
1551 goto err_free_mdio;
1552
a49f37ee
SS		 1553 pxa168_init_hw(pep);
1554 err = ethernet_phy_setup(dev);
1555 if (err)
945c7c73 1556 goto err_mdiobus;
a49f37ee
SS		 1557 SET_NETDEV_DEV(dev, &pdev->dev);
1558 err = register_netdev(dev);
1559 if (err)
945c7c73 1560 goto err_mdiobus;
a49f37ee 1561 return 0;
945c7c73
DC		 1562
1563err_mdiobus:
1564 mdiobus_unregister(pep->smi_bus);
1565err_free_mdio:
1566 mdiobus_free(pep->smi_bus);
1567err_base:
1568 iounmap(pep->base);
1569err_netdev:
1570 free_netdev(dev);
1571err_clk:
1572 clk_disable(clk);
1573 clk_put(clk);
a49f37ee
SS		 1574 return err;
1575}
1576
1577static int pxa168_eth_remove(struct platform_device *pdev)
1578{
1579 struct net_device *dev = platform_get_drvdata(pdev);
1580 struct pxa168_eth_private *pep = netdev_priv(dev);
1581
1582 if (pep->htpr) {
1583 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1584 pep->htpr, pep->htpr_dma);
1585 pep->htpr = NULL;
1586 }
1587 if (pep->clk) {
1588 clk_disable(pep->clk);
1589 clk_put(pep->clk);
1590 pep->clk = NULL;
1591 }
1592 if (pep->phy != NULL)
1593 phy_detach(pep->phy);
1594
1595 iounmap(pep->base);
1596 pep->base = NULL;
9c01ae58
DK		 1597 mdiobus_unregister(pep->smi_bus);
1598 mdiobus_free(pep->smi_bus);
a49f37ee 1599 unregister_netdev(dev);
23f333a2 1600 cancel_work_sync(&pep->tx_timeout_task);
a49f37ee 1601 free_netdev(dev);
a49f37ee
SS		 1602 return 0;
1603}
1604
1605static void pxa168_eth_shutdown(struct platform_device *pdev)
1606{
1607 struct net_device *dev = platform_get_drvdata(pdev);
1608 eth_port_reset(dev);
1609}
1610
1611#ifdef CONFIG_PM
1612static int pxa168_eth_resume(struct platform_device *pdev)
1613{
1614 return -ENOSYS;
1615}
1616
1617static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1618{
1619 return -ENOSYS;
1620}
1621
1622#else
1623#define pxa168_eth_resume NULL
1624#define pxa168_eth_suspend NULL
1625#endif
1626
1627static struct platform_driver pxa168_eth_driver = {
1628 .probe = pxa168_eth_probe,
1629 .remove = pxa168_eth_remove,
1630 .shutdown = pxa168_eth_shutdown,
1631 .resume = pxa168_eth_resume,
1632 .suspend = pxa168_eth_suspend,
1633 .driver = {
1634 .name = DRIVER_NAME,
1635 },
1636};
1637
db62f684 1638module_platform_driver(pxa168_eth_driver);
a49f37ee
SS		 1639
1640MODULE_LICENSE("GPL");
1641MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1642MODULE_ALIAS("platform:pxa168_eth");
Linux kernel - Deliverables
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