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mv643xx_eth: Support the get_ts_info ethtool method.
[deliverable/linux.git] / drivers / net / ethernet / marvell / pxa168_eth.c
CommitLineData
a49f37ee
SS		 1/*
2 * PXA168 ethernet driver.
3 * Most of the code is derived from mv643xx ethernet driver.
4 *
5 * Copyright (C) 2010 Marvell International Ltd.
6 * Sachin Sanap <ssanap@marvell.com>
10206601 7 * Zhangfei Gao <zgao6@marvell.com>
a49f37ee
SS		 8 * Philip Rakity <prakity@marvell.com>
9 * Mark Brown <markb@marvell.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version 2
14 * of the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/dma-mapping.h>
28#include <linux/in.h>
29#include <linux/ip.h>
30#include <linux/tcp.h>
31#include <linux/udp.h>
32#include <linux/etherdevice.h>
33#include <linux/bitops.h>
34#include <linux/delay.h>
35#include <linux/ethtool.h>
36#include <linux/platform_device.h>
37#include <linux/module.h>
38#include <linux/kernel.h>
39#include <linux/workqueue.h>
40#include <linux/clk.h>
41#include <linux/phy.h>
42#include <linux/io.h>
b7e43381 43#include <linux/interrupt.h>
a49f37ee
SS		 44#include <linux/types.h>
45#include <asm/pgtable.h>
46#include <asm/system.h>
a49f37ee
SS		 47#include <asm/cacheflush.h>
48#include <linux/pxa168_eth.h>
49
50#define DRIVER_NAME "pxa168-eth"
51#define DRIVER_VERSION "0.3"
52
53/*
54 * Registers
55 */
56
57#define PHY_ADDRESS 0x0000
58#define SMI 0x0010
59#define PORT_CONFIG 0x0400
60#define PORT_CONFIG_EXT 0x0408
61#define PORT_COMMAND 0x0410
62#define PORT_STATUS 0x0418
63#define HTPR 0x0428
64#define SDMA_CONFIG 0x0440
65#define SDMA_CMD 0x0448
66#define INT_CAUSE 0x0450
67#define INT_W_CLEAR 0x0454
68#define INT_MASK 0x0458
69#define ETH_F_RX_DESC_0 0x0480
70#define ETH_C_RX_DESC_0 0x04A0
71#define ETH_C_TX_DESC_1 0x04E4
72
73/* smi register */
74#define SMI_BUSY (1 << 28) /* 0 - Write, 1 - Read */
75#define SMI_R_VALID (1 << 27) /* 0 - Write, 1 - Read */
76#define SMI_OP_W (0 << 26) /* Write operation */
77#define SMI_OP_R (1 << 26) /* Read operation */
78
79#define PHY_WAIT_ITERATIONS 10
80
81#define PXA168_ETH_PHY_ADDR_DEFAULT 0
82/* RX & TX descriptor command */
83#define BUF_OWNED_BY_DMA (1 << 31)
84
85/* RX descriptor status */
86#define RX_EN_INT (1 << 23)
87#define RX_FIRST_DESC (1 << 17)
88#define RX_LAST_DESC (1 << 16)
89#define RX_ERROR (1 << 15)
90
91/* TX descriptor command */
92#define TX_EN_INT (1 << 23)
93#define TX_GEN_CRC (1 << 22)
94#define TX_ZERO_PADDING (1 << 18)
95#define TX_FIRST_DESC (1 << 17)
96#define TX_LAST_DESC (1 << 16)
97#define TX_ERROR (1 << 15)
98
99/* SDMA_CMD */
100#define SDMA_CMD_AT (1 << 31)
101#define SDMA_CMD_TXDL (1 << 24)
102#define SDMA_CMD_TXDH (1 << 23)
103#define SDMA_CMD_AR (1 << 15)
104#define SDMA_CMD_ERD (1 << 7)
105
106/* Bit definitions of the Port Config Reg */
107#define PCR_HS (1 << 12)
108#define PCR_EN (1 << 7)
109#define PCR_PM (1 << 0)
110
111/* Bit definitions of the Port Config Extend Reg */
112#define PCXR_2BSM (1 << 28)
113#define PCXR_DSCP_EN (1 << 21)
114#define PCXR_MFL_1518 (0 << 14)
115#define PCXR_MFL_1536 (1 << 14)
116#define PCXR_MFL_2048 (2 << 14)
117#define PCXR_MFL_64K (3 << 14)
118#define PCXR_FLP (1 << 11)
119#define PCXR_PRIO_TX_OFF 3
120#define PCXR_TX_HIGH_PRI (7 << PCXR_PRIO_TX_OFF)
121
122/* Bit definitions of the SDMA Config Reg */
123#define SDCR_BSZ_OFF 12
124#define SDCR_BSZ8 (3 << SDCR_BSZ_OFF)
125#define SDCR_BSZ4 (2 << SDCR_BSZ_OFF)
126#define SDCR_BSZ2 (1 << SDCR_BSZ_OFF)
127#define SDCR_BSZ1 (0 << SDCR_BSZ_OFF)
128#define SDCR_BLMR (1 << 6)
129#define SDCR_BLMT (1 << 7)
130#define SDCR_RIFB (1 << 9)
131#define SDCR_RC_OFF 2
132#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
133
134/*
135 * Bit definitions of the Interrupt Cause Reg
136 * and Interrupt MASK Reg is the same
137 */
138#define ICR_RXBUF (1 << 0)
139#define ICR_TXBUF_H (1 << 2)
140#define ICR_TXBUF_L (1 << 3)
141#define ICR_TXEND_H (1 << 6)
142#define ICR_TXEND_L (1 << 7)
143#define ICR_RXERR (1 << 8)
144#define ICR_TXERR_H (1 << 10)
145#define ICR_TXERR_L (1 << 11)
146#define ICR_TX_UDR (1 << 13)
147#define ICR_MII_CH (1 << 28)
148
149#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
150 ICR_TXERR_H | ICR_TXERR_L |\
151 ICR_TXEND_H | ICR_TXEND_L |\
152 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
153
154#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
155
156#define NUM_RX_DESCS 64
157#define NUM_TX_DESCS 64
158
159#define HASH_ADD 0
160#define HASH_DELETE 1
161#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
162#define HOP_NUMBER 12
163
164/* Bit definitions for Port status */
165#define PORT_SPEED_100 (1 << 0)
166#define FULL_DUPLEX (1 << 1)
167#define FLOW_CONTROL_ENABLED (1 << 2)
168#define LINK_UP (1 << 3)
169
170/* Bit definitions for work to be done */
171#define WORK_LINK (1 << 0)
172#define WORK_TX_DONE (1 << 1)
173
174/*
175 * Misc definitions.
176 */
177#define SKB_DMA_REALIGN ((PAGE_SIZE - NET_SKB_PAD) % SMP_CACHE_BYTES)
178
179struct rx_desc {
180 u32 cmd_sts; /* Descriptor command status */
181 u16 byte_cnt; /* Descriptor buffer byte count */
182 u16 buf_size; /* Buffer size */
183 u32 buf_ptr; /* Descriptor buffer pointer */
184 u32 next_desc_ptr; /* Next descriptor pointer */
185};
186
187struct tx_desc {
188 u32 cmd_sts; /* Command/status field */
189 u16 reserved;
190 u16 byte_cnt; /* buffer byte count */
191 u32 buf_ptr; /* pointer to buffer for this descriptor */
192 u32 next_desc_ptr; /* Pointer to next descriptor */
193};
194
195struct pxa168_eth_private {
196 int port_num; /* User Ethernet port number */
197
198 int rx_resource_err; /* Rx ring resource error flag */
199
200 /* Next available and first returning Rx resource */
201 int rx_curr_desc_q, rx_used_desc_q;
202
203 /* Next available and first returning Tx resource */
204 int tx_curr_desc_q, tx_used_desc_q;
205
206 struct rx_desc *p_rx_desc_area;
207 dma_addr_t rx_desc_dma;
208 int rx_desc_area_size;
209 struct sk_buff **rx_skb;
210
211 struct tx_desc *p_tx_desc_area;
212 dma_addr_t tx_desc_dma;
213 int tx_desc_area_size;
214 struct sk_buff **tx_skb;
215
216 struct work_struct tx_timeout_task;
217
218 struct net_device *dev;
219 struct napi_struct napi;
220 u8 work_todo;
221 int skb_size;
222
a49f37ee
SS		 223 /* Size of Tx Ring per queue */
224 int tx_ring_size;
225 /* Number of tx descriptors in use */
226 int tx_desc_count;
227 /* Size of Rx Ring per queue */
228 int rx_ring_size;
229 /* Number of rx descriptors in use */
230 int rx_desc_count;
231
232 /*
233 * Used in case RX Ring is empty, which can occur when
234 * system does not have resources (skb's)
235 */
236 struct timer_list timeout;
237 struct mii_bus *smi_bus;
238 struct phy_device *phy;
239
240 /* clock */
241 struct clk *clk;
242 struct pxa168_eth_platform_data *pd;
243 /*
244 * Ethernet controller base address.
245 */
246 void __iomem *base;
247
248 /* Pointer to the hardware address filter table */
249 void *htpr;
250 dma_addr_t htpr_dma;
251};
252
253struct addr_table_entry {
254 __le32 lo;
255 __le32 hi;
256};
257
258/* Bit fields of a Hash Table Entry */
259enum hash_table_entry {
260 HASH_ENTRY_VALID = 1,
261 SKIP = 2,
262 HASH_ENTRY_RECEIVE_DISCARD = 4,
263 HASH_ENTRY_RECEIVE_DISCARD_BIT = 2
264};
265
266static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd);
267static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd);
268static int pxa168_init_hw(struct pxa168_eth_private *pep);
269static void eth_port_reset(struct net_device *dev);
270static void eth_port_start(struct net_device *dev);
271static int pxa168_eth_open(struct net_device *dev);
272static int pxa168_eth_stop(struct net_device *dev);
273static int ethernet_phy_setup(struct net_device *dev);
274
275static inline u32 rdl(struct pxa168_eth_private *pep, int offset)
276{
277 return readl(pep->base + offset);
278}
279
280static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data)
281{
282 writel(data, pep->base + offset);
283}
284
285static void abort_dma(struct pxa168_eth_private *pep)
286{
287 int delay;
288 int max_retries = 40;
289
290 do {
291 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT);
292 udelay(100);
293
294 delay = 10;
295 while ((rdl(pep, SDMA_CMD) & (SDMA_CMD_AR | SDMA_CMD_AT))
296 && delay-- > 0) {
297 udelay(10);
298 }
299 } while (max_retries-- > 0 && delay <= 0);
300
301 if (max_retries <= 0)
302 printk(KERN_ERR "%s : DMA Stuck\n", __func__);
303}
304
305static int ethernet_phy_get(struct pxa168_eth_private *pep)
306{
307 unsigned int reg_data;
308
309 reg_data = rdl(pep, PHY_ADDRESS);
310
311 return (reg_data >> (5 * pep->port_num)) & 0x1f;
312}
313
314static void ethernet_phy_set_addr(struct pxa168_eth_private *pep, int phy_addr)
315{
316 u32 reg_data;
317 int addr_shift = 5 * pep->port_num;
318
319 reg_data = rdl(pep, PHY_ADDRESS);
320 reg_data &= ~(0x1f << addr_shift);
321 reg_data |= (phy_addr & 0x1f) << addr_shift;
322 wrl(pep, PHY_ADDRESS, reg_data);
323}
324
325static void ethernet_phy_reset(struct pxa168_eth_private *pep)
326{
327 int data;
328
329 data = phy_read(pep->phy, MII_BMCR);
330 if (data < 0)
331 return;
332
333 data |= BMCR_RESET;
334 if (phy_write(pep->phy, MII_BMCR, data) < 0)
335 return;
336
337 do {
338 data = phy_read(pep->phy, MII_BMCR);
339 } while (data >= 0 && data & BMCR_RESET);
340}
341
342static void rxq_refill(struct net_device *dev)
343{
344 struct pxa168_eth_private *pep = netdev_priv(dev);
345 struct sk_buff *skb;
346 struct rx_desc *p_used_rx_desc;
347 int used_rx_desc;
348
349 while (pep->rx_desc_count < pep->rx_ring_size) {
350 int size;
351
c056b734 352 skb = netdev_alloc_skb(dev, pep->skb_size);
a49f37ee
SS		 353 if (!skb)
354 break;
355 if (SKB_DMA_REALIGN)
356 skb_reserve(skb, SKB_DMA_REALIGN);
357 pep->rx_desc_count++;
358 /* Get 'used' Rx descriptor */
359 used_rx_desc = pep->rx_used_desc_q;
360 p_used_rx_desc = &pep->p_rx_desc_area[used_rx_desc];
361 size = skb->end - skb->data;
362 p_used_rx_desc->buf_ptr = dma_map_single(NULL,
363 skb->data,
364 size,
365 DMA_FROM_DEVICE);
366 p_used_rx_desc->buf_size = size;
367 pep->rx_skb[used_rx_desc] = skb;
368
369 /* Return the descriptor to DMA ownership */
370 wmb();
371 p_used_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
372 wmb();
373
374 /* Move the used descriptor pointer to the next descriptor */
375 pep->rx_used_desc_q = (used_rx_desc + 1) % pep->rx_ring_size;
376
377 /* Any Rx return cancels the Rx resource error status */
378 pep->rx_resource_err = 0;
379
380 skb_reserve(skb, ETH_HW_IP_ALIGN);
381 }
382
383 /*
384 * If RX ring is empty of SKB, set a timer to try allocating
385 * again at a later time.
386 */
387 if (pep->rx_desc_count == 0) {
388 pep->timeout.expires = jiffies + (HZ / 10);
389 add_timer(&pep->timeout);
390 }
391}
392
393static inline void rxq_refill_timer_wrapper(unsigned long data)
394{
395 struct pxa168_eth_private *pep = (void *)data;
396 napi_schedule(&pep->napi);
397}
398
399static inline u8 flip_8_bits(u8 x)
400{
401 return (((x) & 0x01) << 3) | (((x) & 0x02) << 1)
402 | (((x) & 0x04) >> 1) | (((x) & 0x08) >> 3)
403 | (((x) & 0x10) << 3) | (((x) & 0x20) << 1)
404 | (((x) & 0x40) >> 1) | (((x) & 0x80) >> 3);
405}
406
407static void nibble_swap_every_byte(unsigned char *mac_addr)
408{
409 int i;
410 for (i = 0; i < ETH_ALEN; i++) {
411 mac_addr[i] = ((mac_addr[i] & 0x0f) << 4) |
412 ((mac_addr[i] & 0xf0) >> 4);
413 }
414}
415
416static void inverse_every_nibble(unsigned char *mac_addr)
417{
418 int i;
419 for (i = 0; i < ETH_ALEN; i++)
420 mac_addr[i] = flip_8_bits(mac_addr[i]);
421}
422
423/*
424 * ----------------------------------------------------------------------------
425 * This function will calculate the hash function of the address.
426 * Inputs
427 * mac_addr_orig - MAC address.
428 * Outputs
429 * return the calculated entry.
430 */
431static u32 hash_function(unsigned char *mac_addr_orig)
432{
433 u32 hash_result;
434 u32 addr0;
435 u32 addr1;
436 u32 addr2;
437 u32 addr3;
438 unsigned char mac_addr[ETH_ALEN];
439
440 /* Make a copy of MAC address since we are going to performe bit
441 * operations on it
442 */
443 memcpy(mac_addr, mac_addr_orig, ETH_ALEN);
444
445 nibble_swap_every_byte(mac_addr);
446 inverse_every_nibble(mac_addr);
447
448 addr0 = (mac_addr[5] >> 2) & 0x3f;
449 addr1 = (mac_addr[5] & 0x03) | (((mac_addr[4] & 0x7f)) << 2);
450 addr2 = ((mac_addr[4] & 0x80) >> 7) | mac_addr[3] << 1;
451 addr3 = (mac_addr[2] & 0xff) | ((mac_addr[1] & 1) << 8);
452
453 hash_result = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
454 hash_result = hash_result & 0x07ff;
455 return hash_result;
456}
457
458/*
459 * ----------------------------------------------------------------------------
460 * This function will add/del an entry to the address table.
461 * Inputs
462 * pep - ETHERNET .
463 * mac_addr - MAC address.
464 * skip - if 1, skip this address.Used in case of deleting an entry which is a
25985edc 465 * part of chain in the hash table.We can't just delete the entry since
a49f37ee
SS		 466 * that will break the chain.We need to defragment the tables time to
467 * time.
468 * rd - 0 Discard packet upon match.
469 * - 1 Receive packet upon match.
470 * Outputs
471 * address table entry is added/deleted.
472 * 0 if success.
473 * -ENOSPC if table full
474 */
475static int add_del_hash_entry(struct pxa168_eth_private *pep,
476 unsigned char *mac_addr,
477 u32 rd, u32 skip, int del)
478{
479 struct addr_table_entry *entry, *start;
480 u32 new_high;
481 u32 new_low;
482 u32 i;
483
484 new_low = (((mac_addr[1] >> 4) & 0xf) << 15)
485 | (((mac_addr[1] >> 0) & 0xf) << 11)
486 | (((mac_addr[0] >> 4) & 0xf) << 7)
487 | (((mac_addr[0] >> 0) & 0xf) << 3)
488 | (((mac_addr[3] >> 4) & 0x1) << 31)
489 | (((mac_addr[3] >> 0) & 0xf) << 27)
490 | (((mac_addr[2] >> 4) & 0xf) << 23)
491 | (((mac_addr[2] >> 0) & 0xf) << 19)
492 | (skip << SKIP) | (rd << HASH_ENTRY_RECEIVE_DISCARD_BIT)
493 | HASH_ENTRY_VALID;
494
495 new_high = (((mac_addr[5] >> 4) & 0xf) << 15)
496 | (((mac_addr[5] >> 0) & 0xf) << 11)
497 | (((mac_addr[4] >> 4) & 0xf) << 7)
498 | (((mac_addr[4] >> 0) & 0xf) << 3)
499 | (((mac_addr[3] >> 5) & 0x7) << 0);
500
501 /*
502 * Pick the appropriate table, start scanning for free/reusable
503 * entries at the index obtained by hashing the specified MAC address
504 */
43d620c8 505 start = pep->htpr;
a49f37ee
SS		 506 entry = start + hash_function(mac_addr);
507 for (i = 0; i < HOP_NUMBER; i++) {
508 if (!(le32_to_cpu(entry->lo) & HASH_ENTRY_VALID)) {
509 break;
510 } else {
511 /* if same address put in same position */
512 if (((le32_to_cpu(entry->lo) & 0xfffffff8) ==
513 (new_low & 0xfffffff8)) &&
514 (le32_to_cpu(entry->hi) == new_high)) {
515 break;
516 }
517 }
518 if (entry == start + 0x7ff)
519 entry = start;
520 else
521 entry++;
522 }
523
524 if (((le32_to_cpu(entry->lo) & 0xfffffff8) != (new_low & 0xfffffff8)) &&
525 (le32_to_cpu(entry->hi) != new_high) && del)
526 return 0;
527
528 if (i == HOP_NUMBER) {
529 if (!del) {
530 printk(KERN_INFO "%s: table section is full, need to "
531 "move to 16kB implementation?\n",
532 __FILE__);
533 return -ENOSPC;
534 } else
535 return 0;
536 }
537
538 /*
539 * Update the selected entry
540 */
541 if (del) {
542 entry->hi = 0;
543 entry->lo = 0;
544 } else {
545 entry->hi = cpu_to_le32(new_high);
546 entry->lo = cpu_to_le32(new_low);
547 }
548
549 return 0;
550}
551
552/*
553 * ----------------------------------------------------------------------------
554 * Create an addressTable entry from MAC address info
555 * found in the specifed net_device struct
556 *
557 * Input : pointer to ethernet interface network device structure
558 * Output : N/A
559 */
560static void update_hash_table_mac_address(struct pxa168_eth_private *pep,
561 unsigned char *oaddr,
562 unsigned char *addr)
563{
564 /* Delete old entry */
565 if (oaddr)
566 add_del_hash_entry(pep, oaddr, 1, 0, HASH_DELETE);
567 /* Add new entry */
568 add_del_hash_entry(pep, addr, 1, 0, HASH_ADD);
569}
570
571static int init_hash_table(struct pxa168_eth_private *pep)
572{
573 /*
574 * Hardware expects CPU to build a hash table based on a predefined
575 * hash function and populate it based on hardware address. The
576 * location of the hash table is identified by 32-bit pointer stored
577 * in HTPR internal register. Two possible sizes exists for the hash
578 * table 8kB (256kB of DRAM required (4 x 64 kB banks)) and 1/2kB
579 * (16kB of DRAM required (4 x 4 kB banks)).We currently only support
580 * 1/2kB.
581 */
582 /* TODO: Add support for 8kB hash table and alternative hash
583 * function.Driver can dynamically switch to them if the 1/2kB hash
584 * table is full.
585 */
586 if (pep->htpr == NULL) {
587 pep->htpr = dma_alloc_coherent(pep->dev->dev.parent,
588 HASH_ADDR_TABLE_SIZE,
589 &pep->htpr_dma, GFP_KERNEL);
590 if (pep->htpr == NULL)
591 return -ENOMEM;
592 }
593 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
594 wrl(pep, HTPR, pep->htpr_dma);
595 return 0;
596}
597
598static void pxa168_eth_set_rx_mode(struct net_device *dev)
599{
600 struct pxa168_eth_private *pep = netdev_priv(dev);
601 struct netdev_hw_addr *ha;
602 u32 val;
603
604 val = rdl(pep, PORT_CONFIG);
605 if (dev->flags & IFF_PROMISC)
606 val |= PCR_PM;
607 else
608 val &= ~PCR_PM;
609 wrl(pep, PORT_CONFIG, val);
610
611 /*
612 * Remove the old list of MAC address and add dev->addr
613 * and multicast address.
614 */
615 memset(pep->htpr, 0, HASH_ADDR_TABLE_SIZE);
616 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
617
618 netdev_for_each_mc_addr(ha, dev)
619 update_hash_table_mac_address(pep, NULL, ha->addr);
620}
621
622static int pxa168_eth_set_mac_address(struct net_device *dev, void *addr)
623{
624 struct sockaddr *sa = addr;
625 struct pxa168_eth_private *pep = netdev_priv(dev);
626 unsigned char oldMac[ETH_ALEN];
627
628 if (!is_valid_ether_addr(sa->sa_data))
504f9b5a 629 return -EADDRNOTAVAIL;
a49f37ee 630 memcpy(oldMac, dev->dev_addr, ETH_ALEN);
7ce5d222 631 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
a49f37ee
SS		 632 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
633 netif_addr_lock_bh(dev);
634 update_hash_table_mac_address(pep, oldMac, dev->dev_addr);
635 netif_addr_unlock_bh(dev);
636 return 0;
637}
638
639static void eth_port_start(struct net_device *dev)
640{
641 unsigned int val = 0;
642 struct pxa168_eth_private *pep = netdev_priv(dev);
643 int tx_curr_desc, rx_curr_desc;
644
645 /* Perform PHY reset, if there is a PHY. */
646 if (pep->phy != NULL) {
647 struct ethtool_cmd cmd;
648
649 pxa168_get_settings(pep->dev, &cmd);
650 ethernet_phy_reset(pep);
651 pxa168_set_settings(pep->dev, &cmd);
652 }
653
654 /* Assignment of Tx CTRP of given queue */
655 tx_curr_desc = pep->tx_curr_desc_q;
656 wrl(pep, ETH_C_TX_DESC_1,
b2bc8563 657 (u32) (pep->tx_desc_dma + tx_curr_desc * sizeof(struct tx_desc)));
a49f37ee
SS		 658
659 /* Assignment of Rx CRDP of given queue */
660 rx_curr_desc = pep->rx_curr_desc_q;
661 wrl(pep, ETH_C_RX_DESC_0,
b2bc8563 662 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 663
664 wrl(pep, ETH_F_RX_DESC_0,
b2bc8563 665 (u32) (pep->rx_desc_dma + rx_curr_desc * sizeof(struct rx_desc)));
a49f37ee
SS		 666
667 /* Clear all interrupts */
668 wrl(pep, INT_CAUSE, 0);
669
670 /* Enable all interrupts for receive, transmit and error. */
671 wrl(pep, INT_MASK, ALL_INTS);
672
673 val = rdl(pep, PORT_CONFIG);
674 val |= PCR_EN;
675 wrl(pep, PORT_CONFIG, val);
676
677 /* Start RX DMA engine */
678 val = rdl(pep, SDMA_CMD);
679 val |= SDMA_CMD_ERD;
680 wrl(pep, SDMA_CMD, val);
681}
682
683static void eth_port_reset(struct net_device *dev)
684{
685 struct pxa168_eth_private *pep = netdev_priv(dev);
686 unsigned int val = 0;
687
688 /* Stop all interrupts for receive, transmit and error. */
689 wrl(pep, INT_MASK, 0);
690
691 /* Clear all interrupts */
692 wrl(pep, INT_CAUSE, 0);
693
694 /* Stop RX DMA */
695 val = rdl(pep, SDMA_CMD);
696 val &= ~SDMA_CMD_ERD; /* abort dma command */
697
698 /* Abort any transmit and receive operations and put DMA
699 * in idle state.
700 */
701 abort_dma(pep);
702
703 /* Disable port */
704 val = rdl(pep, PORT_CONFIG);
705 val &= ~PCR_EN;
706 wrl(pep, PORT_CONFIG, val);
707}
708
709/*
710 * txq_reclaim - Free the tx desc data for completed descriptors
711 * If force is non-zero, frees uncompleted descriptors as well
712 */
713static int txq_reclaim(struct net_device *dev, int force)
714{
715 struct pxa168_eth_private *pep = netdev_priv(dev);
716 struct tx_desc *desc;
717 u32 cmd_sts;
718 struct sk_buff *skb;
719 int tx_index;
720 dma_addr_t addr;
721 int count;
722 int released = 0;
723
724 netif_tx_lock(dev);
725
726 pep->work_todo &= ~WORK_TX_DONE;
727 while (pep->tx_desc_count > 0) {
728 tx_index = pep->tx_used_desc_q;
729 desc = &pep->p_tx_desc_area[tx_index];
730 cmd_sts = desc->cmd_sts;
731 if (!force && (cmd_sts & BUF_OWNED_BY_DMA)) {
732 if (released > 0) {
733 goto txq_reclaim_end;
734 } else {
735 released = -1;
736 goto txq_reclaim_end;
737 }
738 }
739 pep->tx_used_desc_q = (tx_index + 1) % pep->tx_ring_size;
740 pep->tx_desc_count--;
741 addr = desc->buf_ptr;
742 count = desc->byte_cnt;
743 skb = pep->tx_skb[tx_index];
744 if (skb)
745 pep->tx_skb[tx_index] = NULL;
746
747 if (cmd_sts & TX_ERROR) {
748 if (net_ratelimit())
749 printk(KERN_ERR "%s: Error in TX\n", dev->name);
750 dev->stats.tx_errors++;
751 }
752 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
753 if (skb)
754 dev_kfree_skb_irq(skb);
755 released++;
756 }
757txq_reclaim_end:
758 netif_tx_unlock(dev);
759 return released;
760}
761
762static void pxa168_eth_tx_timeout(struct net_device *dev)
763{
764 struct pxa168_eth_private *pep = netdev_priv(dev);
765
766 printk(KERN_INFO "%s: TX timeout desc_count %d\n",
767 dev->name, pep->tx_desc_count);
768
769 schedule_work(&pep->tx_timeout_task);
770}
771
772static void pxa168_eth_tx_timeout_task(struct work_struct *work)
773{
774 struct pxa168_eth_private *pep = container_of(work,
775 struct pxa168_eth_private,
776 tx_timeout_task);
777 struct net_device *dev = pep->dev;
778 pxa168_eth_stop(dev);
779 pxa168_eth_open(dev);
780}
781
782static int rxq_process(struct net_device *dev, int budget)
783{
784 struct pxa168_eth_private *pep = netdev_priv(dev);
785 struct net_device_stats *stats = &dev->stats;
786 unsigned int received_packets = 0;
787 struct sk_buff *skb;
788
789 while (budget-- > 0) {
790 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
791 struct rx_desc *rx_desc;
792 unsigned int cmd_sts;
793
794 /* Do not process Rx ring in case of Rx ring resource error */
795 if (pep->rx_resource_err)
796 break;
797 rx_curr_desc = pep->rx_curr_desc_q;
798 rx_used_desc = pep->rx_used_desc_q;
799 rx_desc = &pep->p_rx_desc_area[rx_curr_desc];
800 cmd_sts = rx_desc->cmd_sts;
801 rmb();
802 if (cmd_sts & (BUF_OWNED_BY_DMA))
803 break;
804 skb = pep->rx_skb[rx_curr_desc];
805 pep->rx_skb[rx_curr_desc] = NULL;
806
807 rx_next_curr_desc = (rx_curr_desc + 1) % pep->rx_ring_size;
808 pep->rx_curr_desc_q = rx_next_curr_desc;
809
810 /* Rx descriptors exhausted. */
811 /* Set the Rx ring resource error flag */
812 if (rx_next_curr_desc == rx_used_desc)
813 pep->rx_resource_err = 1;
814 pep->rx_desc_count--;
815 dma_unmap_single(NULL, rx_desc->buf_ptr,
816 rx_desc->buf_size,
817 DMA_FROM_DEVICE);
818 received_packets++;
819 /*
820 * Update statistics.
821 * Note byte count includes 4 byte CRC count
822 */
823 stats->rx_packets++;
824 stats->rx_bytes += rx_desc->byte_cnt;
825 /*
826 * In case received a packet without first / last bits on OR
827 * the error summary bit is on, the packets needs to be droped.
828 */
829 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
830 (RX_FIRST_DESC | RX_LAST_DESC))
831 || (cmd_sts & RX_ERROR)) {
832
833 stats->rx_dropped++;
834 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
835 (RX_FIRST_DESC | RX_LAST_DESC)) {
836 if (net_ratelimit())
837 printk(KERN_ERR
838 "%s: Rx pkt on multiple desc\n",
839 dev->name);
840 }
841 if (cmd_sts & RX_ERROR)
842 stats->rx_errors++;
843 dev_kfree_skb_irq(skb);
844 } else {
845 /*
846 * The -4 is for the CRC in the trailer of the
847 * received packet
848 */
849 skb_put(skb, rx_desc->byte_cnt - 4);
850 skb->protocol = eth_type_trans(skb, dev);
851 netif_receive_skb(skb);
852 }
a49f37ee
SS		 853 }
854 /* Fill RX ring with skb's */
855 rxq_refill(dev);
856 return received_packets;
857}
858
859static int pxa168_eth_collect_events(struct pxa168_eth_private *pep,
860 struct net_device *dev)
861{
862 u32 icr;
863 int ret = 0;
864
865 icr = rdl(pep, INT_CAUSE);
866 if (icr == 0)
867 return IRQ_NONE;
868
869 wrl(pep, INT_CAUSE, ~icr);
870 if (icr & (ICR_TXBUF_H | ICR_TXBUF_L)) {
871 pep->work_todo |= WORK_TX_DONE;
872 ret = 1;
873 }
874 if (icr & ICR_RXBUF)
875 ret = 1;
876 if (icr & ICR_MII_CH) {
877 pep->work_todo |= WORK_LINK;
878 ret = 1;
879 }
880 return ret;
881}
882
883static void handle_link_event(struct pxa168_eth_private *pep)
884{
885 struct net_device *dev = pep->dev;
886 u32 port_status;
887 int speed;
888 int duplex;
889 int fc;
890
891 port_status = rdl(pep, PORT_STATUS);
892 if (!(port_status & LINK_UP)) {
893 if (netif_carrier_ok(dev)) {
894 printk(KERN_INFO "%s: link down\n", dev->name);
895 netif_carrier_off(dev);
896 txq_reclaim(dev, 1);
897 }
898 return;
899 }
900 if (port_status & PORT_SPEED_100)
901 speed = 100;
902 else
903 speed = 10;
904
905 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
906 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
907 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
908 "flow control %sabled\n", dev->name,
909 speed, duplex ? "full" : "half", fc ? "en" : "dis");
910 if (!netif_carrier_ok(dev))
911 netif_carrier_on(dev);
912}
913
914static irqreturn_t pxa168_eth_int_handler(int irq, void *dev_id)
915{
916 struct net_device *dev = (struct net_device *)dev_id;
917 struct pxa168_eth_private *pep = netdev_priv(dev);
918
919 if (unlikely(!pxa168_eth_collect_events(pep, dev)))
920 return IRQ_NONE;
921 /* Disable interrupts */
922 wrl(pep, INT_MASK, 0);
923 napi_schedule(&pep->napi);
924 return IRQ_HANDLED;
925}
926
927static void pxa168_eth_recalc_skb_size(struct pxa168_eth_private *pep)
928{
929 int skb_size;
930
931 /*
932 * Reserve 2+14 bytes for an ethernet header (the hardware
933 * automatically prepends 2 bytes of dummy data to each
934 * received packet), 16 bytes for up to four VLAN tags, and
935 * 4 bytes for the trailing FCS -- 36 bytes total.
936 */
937 skb_size = pep->dev->mtu + 36;
938
939 /*
940 * Make sure that the skb size is a multiple of 8 bytes, as
941 * the lower three bits of the receive descriptor's buffer
942 * size field are ignored by the hardware.
943 */
944 pep->skb_size = (skb_size + 7) & ~7;
945
946 /*
947 * If NET_SKB_PAD is smaller than a cache line,
948 * netdev_alloc_skb() will cause skb->data to be misaligned
949 * to a cache line boundary. If this is the case, include
950 * some extra space to allow re-aligning the data area.
951 */
952 pep->skb_size += SKB_DMA_REALIGN;
953
954}
955
956static int set_port_config_ext(struct pxa168_eth_private *pep)
957{
958 int skb_size;
959
960 pxa168_eth_recalc_skb_size(pep);
961 if (pep->skb_size <= 1518)
962 skb_size = PCXR_MFL_1518;
963 else if (pep->skb_size <= 1536)
964 skb_size = PCXR_MFL_1536;
965 else if (pep->skb_size <= 2048)
966 skb_size = PCXR_MFL_2048;
967 else
968 skb_size = PCXR_MFL_64K;
969
970 /* Extended Port Configuration */
971 wrl(pep,
972 PORT_CONFIG_EXT, PCXR_2BSM | /* Two byte prefix aligns IP hdr */
973 PCXR_DSCP_EN | /* Enable DSCP in IP */
974 skb_size | PCXR_FLP | /* do not force link pass */
975 PCXR_TX_HIGH_PRI); /* Transmit - high priority queue */
976
977 return 0;
978}
979
980static int pxa168_init_hw(struct pxa168_eth_private *pep)
981{
982 int err = 0;
983
984 /* Disable interrupts */
985 wrl(pep, INT_MASK, 0);
986 wrl(pep, INT_CAUSE, 0);
987 /* Write to ICR to clear interrupts. */
988 wrl(pep, INT_W_CLEAR, 0);
989 /* Abort any transmit and receive operations and put DMA
990 * in idle state.
991 */
992 abort_dma(pep);
993 /* Initialize address hash table */
994 err = init_hash_table(pep);
995 if (err)
996 return err;
997 /* SDMA configuration */
998 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */
999 SDCR_RIFB | /* Rx interrupt on frame */
1000 SDCR_BLMT | /* Little endian transmit */
1001 SDCR_BLMR | /* Little endian receive */
1002 SDCR_RC_MAX_RETRANS); /* Max retransmit count */
1003 /* Port Configuration */
1004 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */
1005 set_port_config_ext(pep);
1006
1007 return err;
1008}
1009
1010static int rxq_init(struct net_device *dev)
1011{
1012 struct pxa168_eth_private *pep = netdev_priv(dev);
1013 struct rx_desc *p_rx_desc;
1014 int size = 0, i = 0;
1015 int rx_desc_num = pep->rx_ring_size;
1016
1017 /* Allocate RX skb rings */
1018 pep->rx_skb = kmalloc(sizeof(*pep->rx_skb) * pep->rx_ring_size,
1019 GFP_KERNEL);
e404decb 1020 if (!pep->rx_skb)
a49f37ee 1021 return -ENOMEM;
e404decb 1022
a49f37ee
SS		 1023 /* Allocate RX ring */
1024 pep->rx_desc_count = 0;
1025 size = pep->rx_ring_size * sizeof(struct rx_desc);
1026 pep->rx_desc_area_size = size;
1027 pep->p_rx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size,
1028 &pep->rx_desc_dma, GFP_KERNEL);
1029 if (!pep->p_rx_desc_area) {
1030 printk(KERN_ERR "%s: Cannot alloc RX ring (size %d bytes)\n",
1031 dev->name, size);
1032 goto out;
1033 }
1034 memset((void *)pep->p_rx_desc_area, 0, size);
1035 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1036 p_rx_desc = (struct rx_desc *)pep->p_rx_desc_area;
1037 for (i = 0; i < rx_desc_num; i++) {
1038 p_rx_desc[i].next_desc_ptr = pep->rx_desc_dma +
1039 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1040 }
1041 /* Save Rx desc pointer to driver struct. */
1042 pep->rx_curr_desc_q = 0;
1043 pep->rx_used_desc_q = 0;
1044 pep->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1045 return 0;
1046out:
1047 kfree(pep->rx_skb);
1048 return -ENOMEM;
1049}
1050
1051static void rxq_deinit(struct net_device *dev)
1052{
1053 struct pxa168_eth_private *pep = netdev_priv(dev);
1054 int curr;
1055
1056 /* Free preallocated skb's on RX rings */
1057 for (curr = 0; pep->rx_desc_count && curr < pep->rx_ring_size; curr++) {
1058 if (pep->rx_skb[curr]) {
1059 dev_kfree_skb(pep->rx_skb[curr]);
1060 pep->rx_desc_count--;
1061 }
1062 }
1063 if (pep->rx_desc_count)
1064 printk(KERN_ERR
1065 "Error in freeing Rx Ring. %d skb's still\n",
1066 pep->rx_desc_count);
1067 /* Free RX ring */
1068 if (pep->p_rx_desc_area)
1069 dma_free_coherent(pep->dev->dev.parent, pep->rx_desc_area_size,
1070 pep->p_rx_desc_area, pep->rx_desc_dma);
1071 kfree(pep->rx_skb);
1072}
1073
1074static int txq_init(struct net_device *dev)
1075{
1076 struct pxa168_eth_private *pep = netdev_priv(dev);
1077 struct tx_desc *p_tx_desc;
1078 int size = 0, i = 0;
1079 int tx_desc_num = pep->tx_ring_size;
1080
1081 pep->tx_skb = kmalloc(sizeof(*pep->tx_skb) * pep->tx_ring_size,
1082 GFP_KERNEL);
e404decb 1083 if (!pep->tx_skb)
a49f37ee 1084 return -ENOMEM;
e404decb 1085
a49f37ee
SS		 1086 /* Allocate TX ring */
1087 pep->tx_desc_count = 0;
1088 size = pep->tx_ring_size * sizeof(struct tx_desc);
1089 pep->tx_desc_area_size = size;
1090 pep->p_tx_desc_area = dma_alloc_coherent(pep->dev->dev.parent, size,
1091 &pep->tx_desc_dma, GFP_KERNEL);
1092 if (!pep->p_tx_desc_area) {
1093 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1094 dev->name, size);
1095 goto out;
1096 }
1097 memset((void *)pep->p_tx_desc_area, 0, pep->tx_desc_area_size);
1098 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1099 p_tx_desc = (struct tx_desc *)pep->p_tx_desc_area;
1100 for (i = 0; i < tx_desc_num; i++) {
1101 p_tx_desc[i].next_desc_ptr = pep->tx_desc_dma +
1102 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1103 }
1104 pep->tx_curr_desc_q = 0;
1105 pep->tx_used_desc_q = 0;
1106 pep->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1107 return 0;
1108out:
1109 kfree(pep->tx_skb);
1110 return -ENOMEM;
1111}
1112
1113static void txq_deinit(struct net_device *dev)
1114{
1115 struct pxa168_eth_private *pep = netdev_priv(dev);
1116
1117 /* Free outstanding skb's on TX ring */
1118 txq_reclaim(dev, 1);
1119 BUG_ON(pep->tx_used_desc_q != pep->tx_curr_desc_q);
1120 /* Free TX ring */
1121 if (pep->p_tx_desc_area)
1122 dma_free_coherent(pep->dev->dev.parent, pep->tx_desc_area_size,
1123 pep->p_tx_desc_area, pep->tx_desc_dma);
1124 kfree(pep->tx_skb);
1125}
1126
1127static int pxa168_eth_open(struct net_device *dev)
1128{
1129 struct pxa168_eth_private *pep = netdev_priv(dev);
1130 int err;
1131
1132 err = request_irq(dev->irq, pxa168_eth_int_handler,
1133 IRQF_DISABLED, dev->name, dev);
1134 if (err) {
1135 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
1136 return -EAGAIN;
1137 }
1138 pep->rx_resource_err = 0;
1139 err = rxq_init(dev);
1140 if (err != 0)
1141 goto out_free_irq;
1142 err = txq_init(dev);
1143 if (err != 0)
1144 goto out_free_rx_skb;
1145 pep->rx_used_desc_q = 0;
1146 pep->rx_curr_desc_q = 0;
1147
1148 /* Fill RX ring with skb's */
1149 rxq_refill(dev);
1150 pep->rx_used_desc_q = 0;
1151 pep->rx_curr_desc_q = 0;
1152 netif_carrier_off(dev);
1153 eth_port_start(dev);
1154 napi_enable(&pep->napi);
1155 return 0;
1156out_free_rx_skb:
1157 rxq_deinit(dev);
1158out_free_irq:
1159 free_irq(dev->irq, dev);
1160 return err;
1161}
1162
1163static int pxa168_eth_stop(struct net_device *dev)
1164{
1165 struct pxa168_eth_private *pep = netdev_priv(dev);
1166 eth_port_reset(dev);
1167
1168 /* Disable interrupts */
1169 wrl(pep, INT_MASK, 0);
1170 wrl(pep, INT_CAUSE, 0);
1171 /* Write to ICR to clear interrupts. */
1172 wrl(pep, INT_W_CLEAR, 0);
1173 napi_disable(&pep->napi);
1174 del_timer_sync(&pep->timeout);
1175 netif_carrier_off(dev);
1176 free_irq(dev->irq, dev);
1177 rxq_deinit(dev);
1178 txq_deinit(dev);
1179
1180 return 0;
1181}
1182
1183static int pxa168_eth_change_mtu(struct net_device *dev, int mtu)
1184{
1185 int retval;
1186 struct pxa168_eth_private *pep = netdev_priv(dev);
1187
1188 if ((mtu > 9500) || (mtu < 68))
1189 return -EINVAL;
1190
1191 dev->mtu = mtu;
1192 retval = set_port_config_ext(pep);
1193
1194 if (!netif_running(dev))
1195 return 0;
1196
1197 /*
1198 * Stop and then re-open the interface. This will allocate RX
1199 * skbs of the new MTU.
1200 * There is a possible danger that the open will not succeed,
1201 * due to memory being full.
1202 */
1203 pxa168_eth_stop(dev);
1204 if (pxa168_eth_open(dev)) {
1205 dev_printk(KERN_ERR, &dev->dev,
1206 "fatal error on re-opening device after "
1207 "MTU change\n");
1208 }
1209
1210 return 0;
1211}
1212
1213static int eth_alloc_tx_desc_index(struct pxa168_eth_private *pep)
1214{
1215 int tx_desc_curr;
1216
1217 tx_desc_curr = pep->tx_curr_desc_q;
1218 pep->tx_curr_desc_q = (tx_desc_curr + 1) % pep->tx_ring_size;
1219 BUG_ON(pep->tx_curr_desc_q == pep->tx_used_desc_q);
1220 pep->tx_desc_count++;
1221
1222 return tx_desc_curr;
1223}
1224
1225static int pxa168_rx_poll(struct napi_struct *napi, int budget)
1226{
1227 struct pxa168_eth_private *pep =
1228 container_of(napi, struct pxa168_eth_private, napi);
1229 struct net_device *dev = pep->dev;
1230 int work_done = 0;
1231
1232 if (unlikely(pep->work_todo & WORK_LINK)) {
1233 pep->work_todo &= ~(WORK_LINK);
1234 handle_link_event(pep);
1235 }
1236 /*
1237 * We call txq_reclaim every time since in NAPI interupts are disabled
1238 * and due to this we miss the TX_DONE interrupt,which is not updated in
1239 * interrupt status register.
1240 */
1241 txq_reclaim(dev, 0);
1242 if (netif_queue_stopped(dev)
1243 && pep->tx_ring_size - pep->tx_desc_count > 1) {
1244 netif_wake_queue(dev);
1245 }
1246 work_done = rxq_process(dev, budget);
1247 if (work_done < budget) {
1248 napi_complete(napi);
1249 wrl(pep, INT_MASK, ALL_INTS);
1250 }
1251
1252 return work_done;
1253}
1254
1255static int pxa168_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1256{
1257 struct pxa168_eth_private *pep = netdev_priv(dev);
1258 struct net_device_stats *stats = &dev->stats;
1259 struct tx_desc *desc;
1260 int tx_index;
1261 int length;
1262
1263 tx_index = eth_alloc_tx_desc_index(pep);
1264 desc = &pep->p_tx_desc_area[tx_index];
1265 length = skb->len;
1266 pep->tx_skb[tx_index] = skb;
1267 desc->byte_cnt = length;
1268 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1f6e44a6
RC		 1269
1270 skb_tx_timestamp(skb);
1271
a49f37ee
SS		 1272 wmb();
1273 desc->cmd_sts = BUF_OWNED_BY_DMA | TX_GEN_CRC | TX_FIRST_DESC |
1274 TX_ZERO_PADDING | TX_LAST_DESC | TX_EN_INT;
1275 wmb();
1276 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD);
1277
38442040 1278 stats->tx_bytes += length;
a49f37ee
SS		 1279 stats->tx_packets++;
1280 dev->trans_start = jiffies;
1281 if (pep->tx_ring_size - pep->tx_desc_count <= 1) {
1282 /* We handled the current skb, but now we are out of space.*/
1283 netif_stop_queue(dev);
1284 }
1285
1286 return NETDEV_TX_OK;
1287}
1288
1289static int smi_wait_ready(struct pxa168_eth_private *pep)
1290{
1291 int i = 0;
1292
1293 /* wait for the SMI register to become available */
1294 for (i = 0; rdl(pep, SMI) & SMI_BUSY; i++) {
1295 if (i == PHY_WAIT_ITERATIONS)
1296 return -ETIMEDOUT;
1297 msleep(10);
1298 }
1299
1300 return 0;
1301}
1302
1303static int pxa168_smi_read(struct mii_bus *bus, int phy_addr, int regnum)
1304{
1305 struct pxa168_eth_private *pep = bus->priv;
1306 int i = 0;
1307 int val;
1308
1309 if (smi_wait_ready(pep)) {
1310 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1311 return -ETIMEDOUT;
1312 }
1313 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R);
1314 /* now wait for the data to be valid */
1315 for (i = 0; !((val = rdl(pep, SMI)) & SMI_R_VALID); i++) {
1316 if (i == PHY_WAIT_ITERATIONS) {
1317 printk(KERN_WARNING
1318 "pxa168_eth: SMI bus read not valid\n");
1319 return -ENODEV;
1320 }
1321 msleep(10);
1322 }
1323
1324 return val & 0xffff;
1325}
1326
1327static int pxa168_smi_write(struct mii_bus *bus, int phy_addr, int regnum,
1328 u16 value)
1329{
1330 struct pxa168_eth_private *pep = bus->priv;
1331
1332 if (smi_wait_ready(pep)) {
1333 printk(KERN_WARNING "pxa168_eth: SMI bus busy timeout\n");
1334 return -ETIMEDOUT;
1335 }
1336
1337 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) |
1338 SMI_OP_W | (value & 0xffff));
1339
1340 if (smi_wait_ready(pep)) {
1341 printk(KERN_ERR "pxa168_eth: SMI bus busy timeout\n");
1342 return -ETIMEDOUT;
1343 }
1344
1345 return 0;
1346}
1347
1348static int pxa168_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr,
1349 int cmd)
1350{
1351 struct pxa168_eth_private *pep = netdev_priv(dev);
1352 if (pep->phy != NULL)
4f2c8510 1353 return phy_mii_ioctl(pep->phy, ifr, cmd);
a49f37ee
SS		 1354
1355 return -EOPNOTSUPP;
1356}
1357
1358static struct phy_device *phy_scan(struct pxa168_eth_private *pep, int phy_addr)
1359{
1360 struct mii_bus *bus = pep->smi_bus;
1361 struct phy_device *phydev;
1362 int start;
1363 int num;
1364 int i;
1365
1366 if (phy_addr == PXA168_ETH_PHY_ADDR_DEFAULT) {
1367 /* Scan entire range */
1368 start = ethernet_phy_get(pep);
1369 num = 32;
1370 } else {
1371 /* Use phy addr specific to platform */
1372 start = phy_addr & 0x1f;
1373 num = 1;
1374 }
1375 phydev = NULL;
1376 for (i = 0; i < num; i++) {
1377 int addr = (start + i) & 0x1f;
1378 if (bus->phy_map[addr] == NULL)
1379 mdiobus_scan(bus, addr);
1380
1381 if (phydev == NULL) {
1382 phydev = bus->phy_map[addr];
1383 if (phydev != NULL)
1384 ethernet_phy_set_addr(pep, addr);
1385 }
1386 }
1387
1388 return phydev;
1389}
1390
1391static void phy_init(struct pxa168_eth_private *pep, int speed, int duplex)
1392{
1393 struct phy_device *phy = pep->phy;
1394 ethernet_phy_reset(pep);
1395
1396 phy_attach(pep->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_MII);
1397
1398 if (speed == 0) {
1399 phy->autoneg = AUTONEG_ENABLE;
1400 phy->speed = 0;
1401 phy->duplex = 0;
1402 phy->supported &= PHY_BASIC_FEATURES;
1403 phy->advertising = phy->supported | ADVERTISED_Autoneg;
1404 } else {
1405 phy->autoneg = AUTONEG_DISABLE;
1406 phy->advertising = 0;
1407 phy->speed = speed;
1408 phy->duplex = duplex;
1409 }
1410 phy_start_aneg(phy);
1411}
1412
1413static int ethernet_phy_setup(struct net_device *dev)
1414{
1415 struct pxa168_eth_private *pep = netdev_priv(dev);
1416
4169591f
DC		 1417 if (pep->pd->init)
1418 pep->pd->init();
a49f37ee
SS		 1419 pep->phy = phy_scan(pep, pep->pd->phy_addr & 0x1f);
1420 if (pep->phy != NULL)
1421 phy_init(pep, pep->pd->speed, pep->pd->duplex);
1422 update_hash_table_mac_address(pep, NULL, dev->dev_addr);
1423
1424 return 0;
1425}
1426
1427static int pxa168_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1428{
1429 struct pxa168_eth_private *pep = netdev_priv(dev);
1430 int err;
1431
1432 err = phy_read_status(pep->phy);
1433 if (err == 0)
1434 err = phy_ethtool_gset(pep->phy, cmd);
1435
1436 return err;
1437}
1438
1439static int pxa168_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1440{
1441 struct pxa168_eth_private *pep = netdev_priv(dev);
1442
1443 return phy_ethtool_sset(pep->phy, cmd);
1444}
1445
1446static void pxa168_get_drvinfo(struct net_device *dev,
1447 struct ethtool_drvinfo *info)
1448{
1449 strncpy(info->driver, DRIVER_NAME, 32);
1450 strncpy(info->version, DRIVER_VERSION, 32);
1451 strncpy(info->fw_version, "N/A", 32);
1452 strncpy(info->bus_info, "N/A", 32);
1453}
1454
a49f37ee
SS		 1455static const struct ethtool_ops pxa168_ethtool_ops = {
1456 .get_settings = pxa168_get_settings,
1457 .set_settings = pxa168_set_settings,
1458 .get_drvinfo = pxa168_get_drvinfo,
ed4ba4b5 1459 .get_link = ethtool_op_get_link,
a49f37ee
SS		 1460};
1461
1462static const struct net_device_ops pxa168_eth_netdev_ops = {
1463 .ndo_open = pxa168_eth_open,
1464 .ndo_stop = pxa168_eth_stop,
1465 .ndo_start_xmit = pxa168_eth_start_xmit,
1466 .ndo_set_rx_mode = pxa168_eth_set_rx_mode,
1467 .ndo_set_mac_address = pxa168_eth_set_mac_address,
1468 .ndo_validate_addr = eth_validate_addr,
1469 .ndo_do_ioctl = pxa168_eth_do_ioctl,
1470 .ndo_change_mtu = pxa168_eth_change_mtu,
1471 .ndo_tx_timeout = pxa168_eth_tx_timeout,
1472};
1473
1474static int pxa168_eth_probe(struct platform_device *pdev)
1475{
1476 struct pxa168_eth_private *pep = NULL;
1477 struct net_device *dev = NULL;
1478 struct resource *res;
1479 struct clk *clk;
1480 int err;
1481
1482 printk(KERN_NOTICE "PXA168 10/100 Ethernet Driver\n");
1483
1484 clk = clk_get(&pdev->dev, "MFUCLK");
1485 if (IS_ERR(clk)) {
1486 printk(KERN_ERR "%s: Fast Ethernet failed to get clock\n",
1487 DRIVER_NAME);
1488 return -ENODEV;
1489 }
1490 clk_enable(clk);
1491
1492 dev = alloc_etherdev(sizeof(struct pxa168_eth_private));
1493 if (!dev) {
1494 err = -ENOMEM;
945c7c73 1495 goto err_clk;
a49f37ee
SS		 1496 }
1497
1498 platform_set_drvdata(pdev, dev);
1499 pep = netdev_priv(dev);
1500 pep->dev = dev;
1501 pep->clk = clk;
1502 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1503 if (res == NULL) {
1504 err = -ENODEV;
945c7c73 1505 goto err_netdev;
a49f37ee 1506 }
28f65c11 1507 pep->base = ioremap(res->start, resource_size(res));
a49f37ee
SS		 1508 if (pep->base == NULL) {
1509 err = -ENOMEM;
945c7c73 1510 goto err_netdev;
a49f37ee
SS		 1511 }
1512 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1513 BUG_ON(!res);
1514 dev->irq = res->start;
1515 dev->netdev_ops = &pxa168_eth_netdev_ops;
1516 dev->watchdog_timeo = 2 * HZ;
1517 dev->base_addr = 0;
1518 SET_ETHTOOL_OPS(dev, &pxa168_ethtool_ops);
1519
1520 INIT_WORK(&pep->tx_timeout_task, pxa168_eth_tx_timeout_task);
1521
1522 printk(KERN_INFO "%s:Using random mac address\n", DRIVER_NAME);
7ce5d222 1523 eth_hw_addr_random(dev);
a49f37ee
SS		 1524
1525 pep->pd = pdev->dev.platform_data;
1526 pep->rx_ring_size = NUM_RX_DESCS;
1527 if (pep->pd->rx_queue_size)
1528 pep->rx_ring_size = pep->pd->rx_queue_size;
1529
1530 pep->tx_ring_size = NUM_TX_DESCS;
1531 if (pep->pd->tx_queue_size)
1532 pep->tx_ring_size = pep->pd->tx_queue_size;
1533
1534 pep->port_num = pep->pd->port_number;
1535 /* Hardware supports only 3 ports */
1536 BUG_ON(pep->port_num > 2);
1537 netif_napi_add(dev, &pep->napi, pxa168_rx_poll, pep->rx_ring_size);
1538
1539 memset(&pep->timeout, 0, sizeof(struct timer_list));
1540 init_timer(&pep->timeout);
1541 pep->timeout.function = rxq_refill_timer_wrapper;
1542 pep->timeout.data = (unsigned long)pep;
1543
1544 pep->smi_bus = mdiobus_alloc();
1545 if (pep->smi_bus == NULL) {
1546 err = -ENOMEM;
945c7c73 1547 goto err_base;
a49f37ee
SS		 1548 }
1549 pep->smi_bus->priv = pep;
1550 pep->smi_bus->name = "pxa168_eth smi";
1551 pep->smi_bus->read = pxa168_smi_read;
1552 pep->smi_bus->write = pxa168_smi_write;
d073a102
FF		 1553 snprintf(pep->smi_bus->id, MII_BUS_ID_SIZE, "%s-%d",
1554 pdev->name, pdev->id);
a49f37ee
SS		 1555 pep->smi_bus->parent = &pdev->dev;
1556 pep->smi_bus->phy_mask = 0xffffffff;
945c7c73
DC		 1557 err = mdiobus_register(pep->smi_bus);
1558 if (err)
1559 goto err_free_mdio;
1560
a49f37ee
SS		 1561 pxa168_init_hw(pep);
1562 err = ethernet_phy_setup(dev);
1563 if (err)
945c7c73 1564 goto err_mdiobus;
a49f37ee
SS		 1565 SET_NETDEV_DEV(dev, &pdev->dev);
1566 err = register_netdev(dev);
1567 if (err)
945c7c73 1568 goto err_mdiobus;
a49f37ee 1569 return 0;
945c7c73
DC		 1570
1571err_mdiobus:
1572 mdiobus_unregister(pep->smi_bus);
1573err_free_mdio:
1574 mdiobus_free(pep->smi_bus);
1575err_base:
1576 iounmap(pep->base);
1577err_netdev:
1578 free_netdev(dev);
1579err_clk:
1580 clk_disable(clk);
1581 clk_put(clk);
a49f37ee
SS		 1582 return err;
1583}
1584
1585static int pxa168_eth_remove(struct platform_device *pdev)
1586{
1587 struct net_device *dev = platform_get_drvdata(pdev);
1588 struct pxa168_eth_private *pep = netdev_priv(dev);
1589
1590 if (pep->htpr) {
1591 dma_free_coherent(pep->dev->dev.parent, HASH_ADDR_TABLE_SIZE,
1592 pep->htpr, pep->htpr_dma);
1593 pep->htpr = NULL;
1594 }
1595 if (pep->clk) {
1596 clk_disable(pep->clk);
1597 clk_put(pep->clk);
1598 pep->clk = NULL;
1599 }
1600 if (pep->phy != NULL)
1601 phy_detach(pep->phy);
1602
1603 iounmap(pep->base);
1604 pep->base = NULL;
9c01ae58
DK		 1605 mdiobus_unregister(pep->smi_bus);
1606 mdiobus_free(pep->smi_bus);
a49f37ee 1607 unregister_netdev(dev);
23f333a2 1608 cancel_work_sync(&pep->tx_timeout_task);
a49f37ee
SS		 1609 free_netdev(dev);
1610 platform_set_drvdata(pdev, NULL);
1611 return 0;
1612}
1613
1614static void pxa168_eth_shutdown(struct platform_device *pdev)
1615{
1616 struct net_device *dev = platform_get_drvdata(pdev);
1617 eth_port_reset(dev);
1618}
1619
1620#ifdef CONFIG_PM
1621static int pxa168_eth_resume(struct platform_device *pdev)
1622{
1623 return -ENOSYS;
1624}
1625
1626static int pxa168_eth_suspend(struct platform_device *pdev, pm_message_t state)
1627{
1628 return -ENOSYS;
1629}
1630
1631#else
1632#define pxa168_eth_resume NULL
1633#define pxa168_eth_suspend NULL
1634#endif
1635
1636static struct platform_driver pxa168_eth_driver = {
1637 .probe = pxa168_eth_probe,
1638 .remove = pxa168_eth_remove,
1639 .shutdown = pxa168_eth_shutdown,
1640 .resume = pxa168_eth_resume,
1641 .suspend = pxa168_eth_suspend,
1642 .driver = {
1643 .name = DRIVER_NAME,
1644 },
1645};
1646
db62f684 1647module_platform_driver(pxa168_eth_driver);
a49f37ee
SS		 1648
1649MODULE_LICENSE("GPL");
1650MODULE_DESCRIPTION("Ethernet driver for Marvell PXA168");
1651MODULE_ALIAS("platform:pxa168_eth");
Linux kernel - Deliverables
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