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Merge 3.4-rc6 into usb-next
[deliverable/linux.git] / drivers / net / ethernet / marvell / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
ada1db5c
JP		 25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
793b883e 27#include <linux/crc32.h>
cd28ab6a 28#include <linux/kernel.h>
cd28ab6a
SH		 29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
a6b7a407 35#include <linux/interrupt.h>
cd28ab6a 36#include <linux/ip.h>
5a0e3ad6 37#include <linux/slab.h>
c9bdd4b5 38#include <net/ip.h>
cd28ab6a
SH		 39#include <linux/tcp.h>
40#include <linux/in.h>
41#include <linux/delay.h>
91c86df5 42#include <linux/workqueue.h>
d1f13708 43#include <linux/if_vlan.h>
d70cd51a 44#include <linux/prefetch.h>
3cf26753 45#include <linux/debugfs.h>
ef743d33 46#include <linux/mii.h>
cd28ab6a
SH		 47
48#include <asm/irq.h>
49
50#include "sky2.h"
51
52#define DRV_NAME "sky2"
d9fa7c86 53#define DRV_VERSION "1.30"
cd28ab6a
SH		 54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
793b883e 65
ee5f68fe 66/* This is the worst case number of transmit list elements for a single skb:
07e31637
SH		 67 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
68#define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
e9c1be80 69#define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
efe91932 70#define TX_MAX_PENDING 1024
b1cb8256 71#define TX_DEF_PENDING 63
cd28ab6a 72
cd28ab6a
SH		 73#define TX_WATCHDOG (5 * HZ)
74#define NAPI_WEIGHT 64
75#define PHY_RETRIES 1000
76
f4331a6d
SH		 77#define SKY2_EEPROM_MAGIC 0x9955aabb
78
060b946c 79#define RING_NEXT(x, s) (((x)+1) & ((s)-1))
cb5d9547 80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
5676cc7b 98static int legacy_pme = 0;
99module_param(legacy_pme, int, 0);
100MODULE_PARM_DESC(legacy_pme, "Legacy power management");
101
e6cac9ba 102static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
e30a4ac2 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
05745c4a 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
a3b4fced 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
e5b74c7d 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
5a37a68d 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
05745c4a 126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
e5b74c7d
SH		 127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
05745c4a 132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
e5b74c7d
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
69161611 138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
5a37a68d 139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
ed4d4161
SH		 140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
0ce8b98d 142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
0f5aac70 143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
cd28ab6a
SH		 144 { 0 }
145};
793b883e 146
cd28ab6a
SH		 147MODULE_DEVICE_TABLE(pci, sky2_id_table);
148
149/* Avoid conditionals by using array */
150static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 152static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 153
d1b139c0 154static void sky2_set_multicast(struct net_device *dev);
0bdb0bd0 155static irqreturn_t sky2_intr(int irq, void *dev_id);
d1b139c0 156
af043aa5 157/* Access to PHY via serial interconnect */
ef743d33 158static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 159{
160 int i;
161
162 gma_write16(hw, port, GM_SMI_DATA, val);
163 gma_write16(hw, port, GM_SMI_CTRL,
164 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165
166 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 167 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
168 if (ctrl == 0xffff)
169 goto io_error;
170
171 if (!(ctrl & GM_SMI_CT_BUSY))
ef743d33 172 return 0;
af043aa5
SH		 173
174 udelay(10);
cd28ab6a 175 }
ef743d33 176
060b946c 177 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 178 return -ETIMEDOUT;
af043aa5
SH		 179
180io_error:
181 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
182 return -EIO;
cd28ab6a
SH		 183}
184
ef743d33 185static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 186{
187 int i;
188
793b883e 189 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 190 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191
192 for (i = 0; i < PHY_RETRIES; i++) {
af043aa5
SH		 193 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
194 if (ctrl == 0xffff)
195 goto io_error;
196
197 if (ctrl & GM_SMI_CT_RD_VAL) {
ef743d33 198 *val = gma_read16(hw, port, GM_SMI_DATA);
199 return 0;
200 }
201
af043aa5 202 udelay(10);
cd28ab6a
SH		 203 }
204
af043aa5 205 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
ef743d33 206 return -ETIMEDOUT;
af043aa5
SH		 207io_error:
208 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
209 return -EIO;
ef743d33 210}
211
af043aa5 212static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
ef743d33 213{
214 u16 v;
af043aa5 215 __gm_phy_read(hw, port, reg, &v);
ef743d33 216 return v;
cd28ab6a
SH		 217}
218
5afa0a9c 219
ae306cca
SH		 220static void sky2_power_on(struct sky2_hw *hw)
221{
222 /* switch power to VCC (WA for VAUX problem) */
223 sky2_write8(hw, B0_POWER_CTRL,
224 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 225
ae306cca
SH		 226 /* disable Core Clock Division, */
227 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 228
4b7c47aa 229 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 230 /* enable bits are inverted */
231 sky2_write8(hw, B2_Y2_CLK_GATE,
232 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
233 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
234 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 else
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 237
ea76e635 238 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
fc99fe06 239 u32 reg;
5afa0a9c 240
b32f40c4 241 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
b2345773 242
b32f40c4 243 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
fc99fe06
SH		 244 /* set all bits to 0 except bits 15..12 and 8 */
245 reg &= P_ASPM_CONTROL_MSK;
b32f40c4 246 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
fc99fe06 247
b32f40c4 248 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
fc99fe06
SH		 249 /* set all bits to 0 except bits 28 & 27 */
250 reg &= P_CTL_TIM_VMAIN_AV_MSK;
b32f40c4 251 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
fc99fe06 252
b32f40c4 253 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
8f70920f 254
5f8ae5c5 255 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
256
8f70920f
SH		 257 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
258 reg = sky2_read32(hw, B2_GP_IO);
259 reg |= GLB_GPIO_STAT_RACE_DIS;
260 sky2_write32(hw, B2_GP_IO, reg);
b2345773
SH		 261
262 sky2_read32(hw, B2_GP_IO);
5afa0a9c 263 }
10547ae2
SH		 264
265 /* Turn on "driver loaded" LED */
266 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
ae306cca 267}
5afa0a9c 268
ae306cca
SH		 269static void sky2_power_aux(struct sky2_hw *hw)
270{
4b7c47aa 271 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ae306cca
SH		 272 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
273 else
274 /* enable bits are inverted */
275 sky2_write8(hw, B2_Y2_CLK_GATE,
276 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
279
c23ddf8f
SH		 280 /* switch power to VAUX if supported and PME from D3cold */
281 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
282 pci_pme_capable(hw->pdev, PCI_D3cold))
ae306cca
SH		 283 sky2_write8(hw, B0_POWER_CTRL,
284 (PC_VAUX_ENA | PC_VCC_ENA |
285 PC_VAUX_ON | PC_VCC_OFF));
10547ae2
SH		 286
287 /* turn off "driver loaded LED" */
288 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
5afa0a9c 289}
290
d3bcfbeb 291static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 292{
293 u16 reg;
294
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
793b883e 297
cd28ab6a
SH		 298 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
299 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
300 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
301 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
302
303 reg = gma_read16(hw, port, GM_RX_CTRL);
304 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
305 gma_write16(hw, port, GM_RX_CTRL, reg);
306}
307
16ad91e1
SH		 308/* flow control to advertise bits */
309static const u16 copper_fc_adv[] = {
310 [FC_NONE] = 0,
311 [FC_TX] = PHY_M_AN_ASP,
312 [FC_RX] = PHY_M_AN_PC,
313 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
314};
315
316/* flow control to advertise bits when using 1000BaseX */
317static const u16 fiber_fc_adv[] = {
df3fe1f3 318 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
16ad91e1
SH		 319 [FC_TX] = PHY_M_P_ASYM_MD_X,
320 [FC_RX] = PHY_M_P_SYM_MD_X,
df3fe1f3 321 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
16ad91e1
SH		 322};
323
324/* flow control to GMA disable bits */
325static const u16 gm_fc_disable[] = {
326 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
327 [FC_TX] = GM_GPCR_FC_RX_DIS,
328 [FC_RX] = GM_GPCR_FC_TX_DIS,
329 [FC_BOTH] = 0,
330};
331
332
cd28ab6a
SH		 333static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
334{
335 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 336 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 337
0ea065e5 338 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
ea76e635 339 !(hw->flags & SKY2_HW_NEWER_PHY)) {
cd28ab6a
SH		 340 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
341
342 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 343 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 344 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
345
53419c68 346 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
cd28ab6a 347 if (hw->chip_id == CHIP_ID_YUKON_EC)
53419c68 348 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 349 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
350 else
53419c68
SH		 351 /* set master & slave downshift counter to 1x */
352 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
cd28ab6a
SH		 353
354 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
355 }
356
357 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 358 if (sky2_is_copper(hw)) {
05745c4a 359 if (!(hw->flags & SKY2_HW_GIGABIT)) {
cd28ab6a
SH		 360 /* enable automatic crossover */
361 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
6d3105d5
SH		 362
363 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
364 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
365 u16 spec;
366
367 /* Enable Class A driver for FE+ A0 */
368 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
369 spec |= PHY_M_FESC_SEL_CL_A;
370 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
371 }
cd28ab6a
SH		 372 } else {
373 /* disable energy detect */
374 ctrl &= ~PHY_M_PC_EN_DET_MSK;
375
376 /* enable automatic crossover */
377 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
378
53419c68 379 /* downshift on PHY 88E1112 and 88E1149 is changed */
8e95a202
JP		 380 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
381 (hw->flags & SKY2_HW_NEWER_PHY)) {
53419c68 382 /* set downshift counter to 3x and enable downshift */
cd28ab6a
SH		 383 ctrl &= ~PHY_M_PC_DSC_MSK;
384 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 }
386 }
cd28ab6a
SH		 387 } else {
388 /* workaround for deviation #4.88 (CRC errors) */
389 /* disable Automatic Crossover */
390
391 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 392 }
cd28ab6a 393
b89165f2
SH		 394 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
395
396 /* special setup for PHY 88E1112 Fiber */
ea76e635 397 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
b89165f2 398 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 399
b89165f2
SH		 400 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
401 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
402 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
403 ctrl &= ~PHY_M_MAC_MD_MSK;
404 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
405 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
406
407 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 408 /* select page 1 to access Fiber registers */
409 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 410
411 /* for SFP-module set SIGDET polarity to low */
412 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
413 ctrl |= PHY_M_FIB_SIGD_POL;
34dd962b 414 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
cd28ab6a 415 }
b89165f2
SH		 416
417 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 418 }
419
7800fddc 420 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 421 ct1000 = 0;
422 adv = PHY_AN_CSMA;
2eaba1a2 423 reg = 0;
cd28ab6a 424
0ea065e5 425 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
b89165f2 426 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 427 if (sky2->advertising & ADVERTISED_1000baseT_Full)
428 ct1000 |= PHY_M_1000C_AFD;
429 if (sky2->advertising & ADVERTISED_1000baseT_Half)
430 ct1000 |= PHY_M_1000C_AHD;
431 if (sky2->advertising & ADVERTISED_100baseT_Full)
432 adv |= PHY_M_AN_100_FD;
433 if (sky2->advertising & ADVERTISED_100baseT_Half)
434 adv |= PHY_M_AN_100_HD;
435 if (sky2->advertising & ADVERTISED_10baseT_Full)
436 adv |= PHY_M_AN_10_FD;
437 if (sky2->advertising & ADVERTISED_10baseT_Half)
438 adv |= PHY_M_AN_10_HD;
709c6e7b 439
b89165f2
SH		 440 } else { /* special defines for FIBER (88E1040S only) */
441 if (sky2->advertising & ADVERTISED_1000baseT_Full)
442 adv |= PHY_M_AN_1000X_AFD;
443 if (sky2->advertising & ADVERTISED_1000baseT_Half)
444 adv |= PHY_M_AN_1000X_AHD;
709c6e7b 445 }
cd28ab6a
SH		 446
447 /* Restart Auto-negotiation */
448 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
449 } else {
450 /* forced speed/duplex settings */
451 ct1000 = PHY_M_1000C_MSE;
452
0ea065e5
SH		 453 /* Disable auto update for duplex flow control and duplex */
454 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
cd28ab6a
SH		 455
456 switch (sky2->speed) {
457 case SPEED_1000:
458 ctrl |= PHY_CT_SP1000;
2eaba1a2 459 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 460 break;
461 case SPEED_100:
462 ctrl |= PHY_CT_SP100;
2eaba1a2 463 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 464 break;
465 }
466
2eaba1a2
SH		 467 if (sky2->duplex == DUPLEX_FULL) {
468 reg |= GM_GPCR_DUP_FULL;
469 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 470 } else if (sky2->speed < SPEED_1000)
471 sky2->flow_mode = FC_NONE;
0ea065e5 472 }
2eaba1a2 473
0ea065e5
SH		 474 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
475 if (sky2_is_copper(hw))
476 adv |= copper_fc_adv[sky2->flow_mode];
477 else
478 adv |= fiber_fc_adv[sky2->flow_mode];
479 } else {
480 reg |= GM_GPCR_AU_FCT_DIS;
16ad91e1 481 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 482
483 /* Forward pause packets to GMAC? */
16ad91e1 484 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
486 else
487 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 488 }
489
2eaba1a2
SH		 490 gma_write16(hw, port, GM_GP_CTRL, reg);
491
05745c4a 492 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a
SH		 493 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
494
495 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
496 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
497
498 /* Setup Phy LED's */
499 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
500 ledover = 0;
501
502 switch (hw->chip_id) {
503 case CHIP_ID_YUKON_FE:
504 /* on 88E3082 these bits are at 11..9 (shifted left) */
505 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
506
507 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
508
509 /* delete ACT LED control bits */
510 ctrl &= ~PHY_M_FELP_LED1_MSK;
511 /* change ACT LED control to blink mode */
512 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
513 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 break;
515
05745c4a
SH		 516 case CHIP_ID_YUKON_FE_P:
517 /* Enable Link Partner Next Page */
518 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
519 ctrl |= PHY_M_PC_ENA_LIP_NP;
520
521 /* disable Energy Detect and enable scrambler */
522 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
523 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
524
525 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
526 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
527 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
528 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
529
530 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
531 break;
532
cd28ab6a 533 case CHIP_ID_YUKON_XL:
793b883e 534 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 535
536 /* select page 3 to access LED control register */
537 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
538
539 /* set LED Function Control register */
ed6d32c7
SH		 540 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
541 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
542 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
543 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
544 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 545
546 /* set Polarity Control register */
547 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 548 (PHY_M_POLC_LS1_P_MIX(4) |
549 PHY_M_POLC_IS0_P_MIX(4) |
550 PHY_M_POLC_LOS_CTRL(2) |
551 PHY_M_POLC_INIT_CTRL(2) |
552 PHY_M_POLC_STA1_CTRL(2) |
553 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 554
555 /* restore page register */
793b883e 556 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 557 break;
93745494 558
ed6d32c7 559 case CHIP_ID_YUKON_EC_U:
93745494 560 case CHIP_ID_YUKON_EX:
ed4d4161 561 case CHIP_ID_YUKON_SUPR:
ed6d32c7
SH		 562 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
563
564 /* select page 3 to access LED control register */
565 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
566
567 /* set LED Function Control register */
568 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
569 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
570 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
571 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
572 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
573
574 /* set Blink Rate in LED Timer Control Register */
575 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
576 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
577 /* restore page register */
578 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 break;
cd28ab6a
SH		 580
581 default:
582 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
583 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
a84d0a3d 584
cd28ab6a 585 /* turn off the Rx LED (LED_RX) */
a84d0a3d 586 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
cd28ab6a
SH		 587 }
588
0ce8b98d 589 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
977bdf06 590 /* apply fixes in PHY AFE */
ed6d32c7
SH		 591 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
592
977bdf06 593 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 594 gm_phy_write(hw, port, 0x18, 0xaa99);
595 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 596
0ce8b98d
SH		 597 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
598 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
599 gm_phy_write(hw, port, 0x18, 0xa204);
600 gm_phy_write(hw, port, 0x17, 0x2002);
601 }
977bdf06
SH		 602
603 /* set page register to 0 */
9467a8fc 604 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
05745c4a
SH		 605 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
606 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
607 /* apply workaround for integrated resistors calibration */
608 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
609 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
0f5aac70
SH		 610 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
611 /* apply fixes in PHY AFE */
612 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
613
614 /* apply RDAC termination workaround */
615 gm_phy_write(hw, port, 24, 0x2800);
616 gm_phy_write(hw, port, 23, 0x2001);
617
618 /* set page register back to 0 */
619 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
e1a74b37
SH		 620 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
621 hw->chip_id < CHIP_ID_YUKON_SUPR) {
05745c4a 622 /* no effect on Yukon-XL */
977bdf06 623 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 624
8e95a202
JP		 625 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
626 sky2->speed == SPEED_100) {
977bdf06 627 /* turn on 100 Mbps LED (LED_LINK100) */
a84d0a3d 628 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
977bdf06 629 }
cd28ab6a 630
977bdf06
SH		 631 if (ledover)
632 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633
4fb99cd6 634 } else if (hw->chip_id == CHIP_ID_YUKON_PRM &&
635 (sky2_read8(hw, B2_MAC_CFG) & 0xf) == 0x7) {
636 int i;
637 /* This a phy register setup workaround copied from vendor driver. */
638 static const struct {
639 u16 reg, val;
640 } eee_afe[] = {
641 { 0x156, 0x58ce },
642 { 0x153, 0x99eb },
643 { 0x141, 0x8064 },
644 /* { 0x155, 0x130b },*/
645 { 0x000, 0x0000 },
646 { 0x151, 0x8433 },
647 { 0x14b, 0x8c44 },
648 { 0x14c, 0x0f90 },
649 { 0x14f, 0x39aa },
650 /* { 0x154, 0x2f39 },*/
651 { 0x14d, 0xba33 },
652 { 0x144, 0x0048 },
653 { 0x152, 0x2010 },
654 /* { 0x158, 0x1223 },*/
655 { 0x140, 0x4444 },
656 { 0x154, 0x2f3b },
657 { 0x158, 0xb203 },
658 { 0x157, 0x2029 },
659 };
660
661 /* Start Workaround for OptimaEEE Rev.Z0 */
662 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fb);
663
664 gm_phy_write(hw, port, 1, 0x4099);
665 gm_phy_write(hw, port, 3, 0x1120);
666 gm_phy_write(hw, port, 11, 0x113c);
667 gm_phy_write(hw, port, 14, 0x8100);
668 gm_phy_write(hw, port, 15, 0x112a);
669 gm_phy_write(hw, port, 17, 0x1008);
670
671 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00fc);
672 gm_phy_write(hw, port, 1, 0x20b0);
673
674 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
675
676 for (i = 0; i < ARRAY_SIZE(eee_afe); i++) {
677 /* apply AFE settings */
678 gm_phy_write(hw, port, 17, eee_afe[i].val);
679 gm_phy_write(hw, port, 16, eee_afe[i].reg | 1u<<13);
680 }
681
682 /* End Workaround for OptimaEEE */
683 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
684
685 /* Enable 10Base-Te (EEE) */
686 if (hw->chip_id >= CHIP_ID_YUKON_PRM) {
687 reg = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
688 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL,
689 reg | PHY_M_10B_TE_ENABLE);
690 }
977bdf06 691 }
2eaba1a2 692
d571b694 693 /* Enable phy interrupt on auto-negotiation complete (or link up) */
0ea065e5 694 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
cd28ab6a
SH		 695 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
696 else
697 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
698}
699
b96936da
SH		 700static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
701static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
702
703static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
d3bcfbeb 704{
705 u32 reg1;
d3bcfbeb 706
a40ccc68 707 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 708 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
b96936da 709 reg1 &= ~phy_power[port];
d3bcfbeb 710
4b7c47aa 711 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
ff35164e
SH		 712 reg1 |= coma_mode[port];
713
b32f40c4 714 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 715 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
82637e80 716 sky2_pci_read32(hw, PCI_DEV_REG1);
f71eb1a2
SH		 717
718 if (hw->chip_id == CHIP_ID_YUKON_FE)
719 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
720 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
721 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
b96936da 722}
167f53d0 723
b96936da
SH		 724static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
725{
726 u32 reg1;
db99b988
SH		 727 u16 ctrl;
728
729 /* release GPHY Control reset */
730 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
731
732 /* release GMAC reset */
733 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
734
735 if (hw->flags & SKY2_HW_NEWER_PHY) {
736 /* select page 2 to access MAC control register */
737 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
738
739 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
740 /* allow GMII Power Down */
741 ctrl &= ~PHY_M_MAC_GMIF_PUP;
742 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
743
744 /* set page register back to 0 */
745 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
746 }
747
748 /* setup General Purpose Control Register */
749 gma_write16(hw, port, GM_GP_CTRL,
0ea065e5
SH		 750 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
751 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
752 GM_GPCR_AU_SPD_DIS);
db99b988
SH		 753
754 if (hw->chip_id != CHIP_ID_YUKON_EC) {
755 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
e484d5f5
RW		 756 /* select page 2 to access MAC control register */
757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
db99b988 758
e484d5f5 759 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
db99b988
SH		 760 /* enable Power Down */
761 ctrl |= PHY_M_PC_POW_D_ENA;
762 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
e484d5f5
RW		 763
764 /* set page register back to 0 */
765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
db99b988
SH		 766 }
767
768 /* set IEEE compatible Power Down Mode (dev. #4.99) */
769 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
770 }
b96936da 771
a40ccc68 772 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b96936da 773 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
db99b988 774 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
b96936da 775 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
a40ccc68 776 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb 777}
778
8e11680f 779/* configure IPG according to used link speed */
780static void sky2_set_ipg(struct sky2_port *sky2)
781{
782 u16 reg;
783
784 reg = gma_read16(sky2->hw, sky2->port, GM_SERIAL_MODE);
785 reg &= ~GM_SMOD_IPG_MSK;
786 if (sky2->speed > SPEED_100)
787 reg |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
788 else
789 reg |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
790 gma_write16(sky2->hw, sky2->port, GM_SERIAL_MODE, reg);
791}
792
38000a94
BP		 793/* Enable Rx/Tx */
794static void sky2_enable_rx_tx(struct sky2_port *sky2)
795{
796 struct sky2_hw *hw = sky2->hw;
797 unsigned port = sky2->port;
798 u16 reg;
799
800 reg = gma_read16(hw, port, GM_GP_CTRL);
801 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
802 gma_write16(hw, port, GM_GP_CTRL, reg);
803}
804
1b537565
SH		 805/* Force a renegotiation */
806static void sky2_phy_reinit(struct sky2_port *sky2)
807{
e07b1aa8 808 spin_lock_bh(&sky2->phy_lock);
1b537565 809 sky2_phy_init(sky2->hw, sky2->port);
38000a94 810 sky2_enable_rx_tx(sky2);
e07b1aa8 811 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 812}
813
e3173832
SH		 814/* Put device in state to listen for Wake On Lan */
815static void sky2_wol_init(struct sky2_port *sky2)
816{
817 struct sky2_hw *hw = sky2->hw;
818 unsigned port = sky2->port;
819 enum flow_control save_mode;
820 u16 ctrl;
e3173832
SH		 821
822 /* Bring hardware out of reset */
823 sky2_write16(hw, B0_CTST, CS_RST_CLR);
824 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
825
826 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
827 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
828
829 /* Force to 10/100
830 * sky2_reset will re-enable on resume
831 */
832 save_mode = sky2->flow_mode;
833 ctrl = sky2->advertising;
834
835 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
836 sky2->flow_mode = FC_NONE;
b96936da
SH		 837
838 spin_lock_bh(&sky2->phy_lock);
839 sky2_phy_power_up(hw, port);
840 sky2_phy_init(hw, port);
841 spin_unlock_bh(&sky2->phy_lock);
e3173832
SH		 842
843 sky2->flow_mode = save_mode;
844 sky2->advertising = ctrl;
845
846 /* Set GMAC to no flow control and auto update for speed/duplex */
847 gma_write16(hw, port, GM_GP_CTRL,
848 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
849 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
850
851 /* Set WOL address */
852 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
853 sky2->netdev->dev_addr, ETH_ALEN);
854
855 /* Turn on appropriate WOL control bits */
856 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
857 ctrl = 0;
858 if (sky2->wol & WAKE_PHY)
859 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
860 else
861 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
862
863 if (sky2->wol & WAKE_MAGIC)
864 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
865 else
a419aef8 866 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
e3173832
SH		 867
868 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
869 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
870
5f8ae5c5 871 /* Disable PiG firmware */
872 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
873
5676cc7b 874 /* Needed by some broken BIOSes, use PCI rather than PCI-e for WOL */
875 if (legacy_pme) {
876 u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
877 reg1 |= PCI_Y2_PME_LEGACY;
878 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
879 }
880
e3173832
SH		 881 /* block receiver */
882 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
f9687c44 883 sky2_read32(hw, B0_CTST);
e3173832
SH		 884}
885
69161611
SH		 886static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
887{
05745c4a
SH		 888 struct net_device *dev = hw->dev[port];
889
ed4d4161
SH		 890 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
891 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
877c8570 892 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
ed4d4161 893 /* Yukon-Extreme B0 and further Extreme devices */
44dde56d 894 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
895 } else if (dev->mtu > ETH_DATA_LEN) {
896 /* set Tx GMAC FIFO Almost Empty Threshold */
897 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
898 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
05745c4a 899
44dde56d 900 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
901 } else
902 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
69161611
SH		 903}
904
cd28ab6a
SH		 905static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
906{
907 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
908 u16 reg;
25cccecc 909 u32 rx_reg;
cd28ab6a
SH		 910 int i;
911 const u8 *addr = hw->dev[port]->dev_addr;
912
f350339c
SH		 913 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
914 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
cd28ab6a
SH		 915
916 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
917
4b7c47aa 918 if (hw->chip_id == CHIP_ID_YUKON_XL &&
919 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
920 port == 1) {
cd28ab6a
SH		 921 /* WA DEV_472 -- looks like crossed wires on port 2 */
922 /* clear GMAC 1 Control reset */
923 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
924 do {
925 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
926 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
927 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
928 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
929 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
930 }
931
793b883e 932 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 933
2eaba1a2
SH		 934 /* Enable Transmit FIFO Underrun */
935 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
936
e07b1aa8 937 spin_lock_bh(&sky2->phy_lock);
b96936da 938 sky2_phy_power_up(hw, port);
cd28ab6a 939 sky2_phy_init(hw, port);
e07b1aa8 940 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 941
942 /* MIB clear */
943 reg = gma_read16(hw, port, GM_PHY_ADDR);
944 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
945
43f2f104
SH		 946 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
947 gma_read16(hw, port, i);
cd28ab6a
SH		 948 gma_write16(hw, port, GM_PHY_ADDR, reg);
949
950 /* transmit control */
951 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
952
953 /* receive control reg: unicast + multicast + no FCS */
954 gma_write16(hw, port, GM_RX_CTRL,
793b883e 955 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 956
957 /* transmit flow control */
958 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
959
960 /* transmit parameter */
961 gma_write16(hw, port, GM_TX_PARAM,
962 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
963 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
964 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
965 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
966
967 /* serial mode register */
968 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
8e11680f 969 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF_1000);
cd28ab6a 970
6b1a3aef 971 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 972 reg |= GM_SMOD_JUMBO_ENA;
973
c1cd0a85 974 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
975 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
976 reg |= GM_NEW_FLOW_CTRL;
977
cd28ab6a
SH		 978 gma_write16(hw, port, GM_SERIAL_MODE, reg);
979
cd28ab6a
SH		 980 /* virtual address for data */
981 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
982
793b883e
SH		 983 /* physical address: used for pause frames */
984 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
985
986 /* ignore counter overflows */
cd28ab6a
SH		 987 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
988 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
989 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
990
991 /* Configure Rx MAC FIFO */
992 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
25cccecc 993 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
05745c4a
SH		 994 if (hw->chip_id == CHIP_ID_YUKON_EX ||
995 hw->chip_id == CHIP_ID_YUKON_FE_P)
25cccecc 996 rx_reg |= GMF_RX_OVER_ON;
69161611 997
25cccecc 998 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
cd28ab6a 999
798fdd07
SH		 1000 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1001 /* Hardware errata - clear flush mask */
1002 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
1003 } else {
1004 /* Flush Rx MAC FIFO on any flow control or error */
1005 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
1006 }
cd28ab6a 1007
8df9a876 1008 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
05745c4a
SH		 1009 reg = RX_GMF_FL_THR_DEF + 1;
1010 /* Another magic mystery workaround from sk98lin */
1011 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1012 hw->chip_rev == CHIP_REV_YU_FE2_A0)
1013 reg = 0x178;
1014 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
cd28ab6a
SH		 1015
1016 /* Configure Tx MAC FIFO */
1017 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1018 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 1019
25985edc 1020 /* On chips without ram buffer, pause is controlled by MAC level */
39dbd958 1021 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
d6b54d24 1022 /* Pause threshold is scaled by 8 in bytes */
8e95a202
JP		 1023 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1024 hw->chip_rev == CHIP_REV_YU_FE2_A0)
d6b54d24
SH		 1025 reg = 1568 / 8;
1026 else
1027 reg = 1024 / 8;
1028 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
1029 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
b628ed98 1030
69161611 1031 sky2_set_tx_stfwd(hw, port);
5a5b1ea0 1032 }
1033
e970d1f8
SH		 1034 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
1035 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
1036 /* disable dynamic watermark */
1037 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
1038 reg &= ~TX_DYN_WM_ENA;
1039 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
1040 }
cd28ab6a
SH		 1041}
1042
67712901
SH		 1043/* Assign Ram Buffer allocation to queue */
1044static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 1045{
67712901
SH		 1046 u32 end;
1047
1048 /* convert from K bytes to qwords used for hw register */
1049 start *= 1024/8;
1050 space *= 1024/8;
1051 end = start + space - 1;
793b883e 1052
cd28ab6a
SH		 1053 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
1054 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1055 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1056 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1057 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1058
1059 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 1060 u32 tp = space - space/4;
793b883e 1061
1c28f6ba
SH		 1062 /* On receive queue's set the thresholds
1063 * give receiver priority when > 3/4 full
1064 * send pause when down to 2K
1065 */
1066 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1067 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 1068
1c28f6ba
SH		 1069 tp = space - 2048/8;
1070 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1071 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 1072 } else {
1073 /* Enable store & forward on Tx queue's because
1074 * Tx FIFO is only 1K on Yukon
1075 */
1076 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
1077 }
1078
1079 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 1080 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 1081}
1082
cd28ab6a 1083/* Setup Bus Memory Interface */
af4ed7e6 1084static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 1085{
1086 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1087 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1088 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 1089 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 1090}
1091
cd28ab6a
SH		 1092/* Setup prefetch unit registers. This is the interface between
1093 * hardware and driver list elements
1094 */
8cc048e3 1095static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
d6e74b6b 1096 dma_addr_t addr, u32 last)
cd28ab6a 1097{
cd28ab6a
SH		 1098 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1099 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
d6e74b6b
SH		 1100 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1101 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
cd28ab6a
SH		 1102 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1103 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 1104
1105 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 1106}
1107
9b289c33 1108static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
793b883e 1109{
9b289c33 1110 struct sky2_tx_le *le = sky2->tx_le + *slot;
793b883e 1111
ee5f68fe 1112 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
291ea614 1113 le->ctrl = 0;
793b883e
SH		 1114 return le;
1115}
cd28ab6a 1116
88f5f0ca
SH		 1117static void tx_init(struct sky2_port *sky2)
1118{
1119 struct sky2_tx_le *le;
1120
1121 sky2->tx_prod = sky2->tx_cons = 0;
1122 sky2->tx_tcpsum = 0;
1123 sky2->tx_last_mss = 0;
ec2a5466 1124 netdev_reset_queue(sky2->netdev);
88f5f0ca 1125
9b289c33 1126 le = get_tx_le(sky2, &sky2->tx_prod);
88f5f0ca
SH		 1127 le->addr = 0;
1128 le->opcode = OP_ADDR64 | HW_OWNER;
5dce95e5 1129 sky2->tx_last_upper = 0;
88f5f0ca
SH		 1130}
1131
290d4de5
SH		 1132/* Update chip's next pointer */
1133static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 1134{
50432cb5 1135 /* Make sure write' to descriptors are complete before we tell hardware */
762c2de2 1136 wmb();
50432cb5
SH		 1137 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1138
1139 /* Synchronize I/O on since next processor may write to tail */
1140 mmiowb();
cd28ab6a
SH		 1141}
1142
793b883e 1143
cd28ab6a
SH		 1144static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1145{
1146 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 1147 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 1148 le->ctrl = 0;
cd28ab6a
SH		 1149 return le;
1150}
1151
060b946c 1152static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
39ef110b
MM		 1153{
1154 unsigned size;
1155
1156 /* Space needed for frame data + headers rounded up */
1157 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1158
1159 /* Stopping point for hardware truncation */
1160 return (size - 8) / sizeof(u32);
1161}
1162
060b946c 1163static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
39ef110b
MM		 1164{
1165 struct rx_ring_info *re;
1166 unsigned size;
1167
1168 /* Space needed for frame data + headers rounded up */
1169 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1170
1171 sky2->rx_nfrags = size >> PAGE_SHIFT;
1172 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1173
1174 /* Compute residue after pages */
1175 size -= sky2->rx_nfrags << PAGE_SHIFT;
1176
1177 /* Optimize to handle small packets and headers */
1178 if (size < copybreak)
1179 size = copybreak;
1180 if (size < ETH_HLEN)
1181 size = ETH_HLEN;
1182
1183 return size;
1184}
1185
14d0263f 1186/* Build description to hardware for one receive segment */
060b946c 1187static void sky2_rx_add(struct sky2_port *sky2, u8 op,
14d0263f 1188 dma_addr_t map, unsigned len)
cd28ab6a
SH		 1189{
1190 struct sky2_rx_le *le;
1191
86c6887e 1192 if (sizeof(dma_addr_t) > sizeof(u32)) {
cd28ab6a 1193 le = sky2_next_rx(sky2);
86c6887e 1194 le->addr = cpu_to_le32(upper_32_bits(map));
cd28ab6a
SH		 1195 le->opcode = OP_ADDR64 | HW_OWNER;
1196 }
793b883e 1197
cd28ab6a 1198 le = sky2_next_rx(sky2);
d6e74b6b 1199 le->addr = cpu_to_le32(lower_32_bits(map));
734d1868 1200 le->length = cpu_to_le16(len);
14d0263f 1201 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 1202}
1203
14d0263f
SH		 1204/* Build description to hardware for one possibly fragmented skb */
1205static void sky2_rx_submit(struct sky2_port *sky2,
1206 const struct rx_ring_info *re)
1207{
1208 int i;
1209
1210 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1211
1212 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1213 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1214}
1215
1216
454e6cb6 1217static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
14d0263f
SH		 1218 unsigned size)
1219{
1220 struct sk_buff *skb = re->skb;
1221 int i;
1222
1223 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
3fbd9187 1224 if (pci_dma_mapping_error(pdev, re->data_addr))
1225 goto mapping_error;
454e6cb6 1226
7cd26ce5 1227 dma_unmap_len_set(re, data_size, size);
14d0263f 1228
3fbd9187 1229 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 1230 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3fbd9187 1231
950a5a4f 1232 re->frag_addr[i] = skb_frag_dma_map(&pdev->dev, frag, 0,
9e903e08 1233 skb_frag_size(frag),
5d6bcdfe 1234 DMA_FROM_DEVICE);
3fbd9187 1235
5d6bcdfe 1236 if (dma_mapping_error(&pdev->dev, re->frag_addr[i]))
3fbd9187 1237 goto map_page_error;
1238 }
454e6cb6 1239 return 0;
3fbd9187 1240
1241map_page_error:
1242 while (--i >= 0) {
1243 pci_unmap_page(pdev, re->frag_addr[i],
9e903e08 1244 skb_frag_size(&skb_shinfo(skb)->frags[i]),
3fbd9187 1245 PCI_DMA_FROMDEVICE);
1246 }
1247
7cd26ce5 1248 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
3fbd9187 1249 PCI_DMA_FROMDEVICE);
1250
1251mapping_error:
1252 if (net_ratelimit())
1253 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1254 skb->dev->name);
1255 return -EIO;
14d0263f
SH		 1256}
1257
1258static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1259{
1260 struct sk_buff *skb = re->skb;
1261 int i;
1262
7cd26ce5 1263 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
14d0263f
SH		 1264 PCI_DMA_FROMDEVICE);
1265
1266 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1267 pci_unmap_page(pdev, re->frag_addr[i],
9e903e08 1268 skb_frag_size(&skb_shinfo(skb)->frags[i]),
14d0263f
SH		 1269 PCI_DMA_FROMDEVICE);
1270}
793b883e 1271
cd28ab6a
SH		 1272/* Tell chip where to start receive checksum.
1273 * Actually has two checksums, but set both same to avoid possible byte
1274 * order problems.
1275 */
793b883e 1276static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a 1277{
ea76e635 1278 struct sky2_rx_le *le = sky2_next_rx(sky2);
793b883e 1279
ea76e635
SH		 1280 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1281 le->ctrl = 0;
1282 le->opcode = OP_TCPSTART | HW_OWNER;
cd28ab6a 1283
ea76e635
SH		 1284 sky2_write32(sky2->hw,
1285 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
f5d64037 1286 (sky2->netdev->features & NETIF_F_RXCSUM)
0ea065e5 1287 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 1288}
1289
00427a73 1290/*
1291 * Fixed initial key as seed to RSS.
1292 */
1293static const uint32_t rss_init_key[10] = {
1294 0x7c3351da, 0x51c5cf4e, 0x44adbdd1, 0xe8d38d18, 0x48897c43,
1295 0xb1d60e7e, 0x6a3dd760, 0x01a2e453, 0x16f46f13, 0x1a0e7b30
1296};
1297
bf73130d 1298/* Enable/disable receive hash calculation (RSS) */
c8f44aff 1299static void rx_set_rss(struct net_device *dev, netdev_features_t features)
bf73130d
SH		 1300{
1301 struct sky2_port *sky2 = netdev_priv(dev);
1302 struct sky2_hw *hw = sky2->hw;
1303 int i, nkeys = 4;
1304
1305 /* Supports IPv6 and other modes */
1306 if (hw->flags & SKY2_HW_NEW_LE) {
1307 nkeys = 10;
1308 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1309 }
1310
1311 /* Program RSS initial values */
f5d64037 1312 if (features & NETIF_F_RXHASH) {
bf73130d
SH		 1313 for (i = 0; i < nkeys; i++)
1314 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
00427a73 1315 rss_init_key[i]);
bf73130d
SH		 1316
1317 /* Need to turn on (undocumented) flag to make hashing work */
1318 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1319 RX_STFW_ENA);
1320
1321 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1322 BMU_ENA_RX_RSS_HASH);
1323 } else
1324 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1325 BMU_DIS_RX_RSS_HASH);
1326}
1327
6b1a3aef 1328/*
1329 * The RX Stop command will not work for Yukon-2 if the BMU does not
1330 * reach the end of packet and since we can't make sure that we have
1331 * incoming data, we must reset the BMU while it is not doing a DMA
1332 * transfer. Since it is possible that the RX path is still active,
1333 * the RX RAM buffer will be stopped first, so any possible incoming
1334 * data will not trigger a DMA. After the RAM buffer is stopped, the
1335 * BMU is polled until any DMA in progress is ended and only then it
1336 * will be reset.
1337 */
1338static void sky2_rx_stop(struct sky2_port *sky2)
1339{
1340 struct sky2_hw *hw = sky2->hw;
1341 unsigned rxq = rxqaddr[sky2->port];
1342 int i;
1343
1344 /* disable the RAM Buffer receive queue */
1345 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1346
1347 for (i = 0; i < 0xffff; i++)
1348 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1349 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1350 goto stopped;
1351
ada1db5c 1352 netdev_warn(sky2->netdev, "receiver stop failed\n");
6b1a3aef 1353stopped:
1354 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1355
1356 /* reset the Rx prefetch unit */
1357 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
3d1454dd 1358 mmiowb();
6b1a3aef 1359}
793b883e 1360
d571b694 1361/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 1362static void sky2_rx_clean(struct sky2_port *sky2)
1363{
1364 unsigned i;
1365
1366 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 1367 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 1368 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 1369
1370 if (re->skb) {
14d0263f 1371 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 1372 kfree_skb(re->skb);
1373 re->skb = NULL;
1374 }
1375 }
1376}
1377
ef743d33 1378/* Basic MII support */
1379static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1380{
1381 struct mii_ioctl_data *data = if_mii(ifr);
1382 struct sky2_port *sky2 = netdev_priv(dev);
1383 struct sky2_hw *hw = sky2->hw;
1384 int err = -EOPNOTSUPP;
1385
1386 if (!netif_running(dev))
1387 return -ENODEV; /* Phy still in reset */
1388
d89e1343 1389 switch (cmd) {
ef743d33 1390 case SIOCGMIIPHY:
1391 data->phy_id = PHY_ADDR_MARV;
1392
1393 /* fallthru */
1394 case SIOCGMIIREG: {
1395 u16 val = 0;
91c86df5 1396
e07b1aa8 1397 spin_lock_bh(&sky2->phy_lock);
ef743d33 1398 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1399 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1400
ef743d33 1401 data->val_out = val;
1402 break;
1403 }
1404
1405 case SIOCSMIIREG:
e07b1aa8 1406 spin_lock_bh(&sky2->phy_lock);
ef743d33 1407 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1408 data->val_in);
e07b1aa8 1409 spin_unlock_bh(&sky2->phy_lock);
ef743d33 1410 break;
1411 }
1412 return err;
1413}
1414
f5d64037 1415#define SKY2_VLAN_OFFLOADS (NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO)
d494eacd 1416
c8f44aff 1417static void sky2_vlan_mode(struct net_device *dev, netdev_features_t features)
d494eacd
SH		 1418{
1419 struct sky2_port *sky2 = netdev_priv(dev);
1420 struct sky2_hw *hw = sky2->hw;
1421 u16 port = sky2->port;
1422
f5d64037 1423 if (features & NETIF_F_HW_VLAN_RX)
86aa7785
SH		 1424 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1425 RX_VLAN_STRIP_ON);
1426 else
1427 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1428 RX_VLAN_STRIP_OFF);
d494eacd 1429
f5d64037 1430 if (features & NETIF_F_HW_VLAN_TX) {
86aa7785
SH		 1431 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1432 TX_VLAN_TAG_ON);
f5d64037
MM		 1433
1434 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
1435 } else {
86aa7785
SH		 1436 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1437 TX_VLAN_TAG_OFF);
d1f13708 1438
86aa7785 1439 /* Can't do transmit offload of vlan without hw vlan */
f5d64037 1440 dev->vlan_features &= ~SKY2_VLAN_OFFLOADS;
86aa7785 1441 }
d1f13708 1442}
d1f13708 1443
bd1c6869
SH		 1444/* Amount of required worst case padding in rx buffer */
1445static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1446{
1447 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1448}
1449
82788c7a 1450/*
14d0263f
SH		 1451 * Allocate an skb for receiving. If the MTU is large enough
1452 * make the skb non-linear with a fragment list of pages.
82788c7a 1453 */
68ac3191 1454static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2, gfp_t gfp)
82788c7a
SH		 1455{
1456 struct sk_buff *skb;
14d0263f 1457 int i;
82788c7a 1458
68ac3191
ED		 1459 skb = __netdev_alloc_skb(sky2->netdev,
1460 sky2->rx_data_size + sky2_rx_pad(sky2->hw),
1461 gfp);
bd1c6869
SH		 1462 if (!skb)
1463 goto nomem;
1464
39dbd958 1465 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
f03b8654
SH		 1466 unsigned char *start;
1467 /*
1468 * Workaround for a bug in FIFO that cause hang
1469 * if the FIFO if the receive buffer is not 64 byte aligned.
1470 * The buffer returned from netdev_alloc_skb is
1471 * aligned except if slab debugging is enabled.
1472 */
f03b8654
SH		 1473 start = PTR_ALIGN(skb->data, 8);
1474 skb_reserve(skb, start - skb->data);
bd1c6869 1475 } else
f03b8654 1476 skb_reserve(skb, NET_IP_ALIGN);
14d0263f
SH		 1477
1478 for (i = 0; i < sky2->rx_nfrags; i++) {
68ac3191 1479 struct page *page = alloc_page(gfp);
14d0263f
SH		 1480
1481 if (!page)
1482 goto free_partial;
1483 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1484 }
1485
1486 return skb;
14d0263f
SH		 1487free_partial:
1488 kfree_skb(skb);
1489nomem:
1490 return NULL;
82788c7a
SH		 1491}
1492
55c9dd35
SH		 1493static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1494{
1495 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1496}
1497
200ac492
MM		 1498static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1499{
1500 struct sky2_hw *hw = sky2->hw;
1501 unsigned i;
1502
1503 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1504
1505 /* Fill Rx ring */
1506 for (i = 0; i < sky2->rx_pending; i++) {
1507 struct rx_ring_info *re = sky2->rx_ring + i;
1508
68ac3191 1509 re->skb = sky2_rx_alloc(sky2, GFP_KERNEL);
200ac492
MM		 1510 if (!re->skb)
1511 return -ENOMEM;
1512
1513 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1514 dev_kfree_skb(re->skb);
1515 re->skb = NULL;
1516 return -ENOMEM;
1517 }
1518 }
1519 return 0;
1520}
1521
cd28ab6a 1522/*
200ac492 1523 * Setup receiver buffer pool.
14d0263f
SH		 1524 * Normal case this ends up creating one list element for skb
1525 * in the receive ring. Worst case if using large MTU and each
1526 * allocation falls on a different 64 bit region, that results
1527 * in 6 list elements per ring entry.
1528 * One element is used for checksum enable/disable, and one
1529 * extra to avoid wrap.
cd28ab6a 1530 */
200ac492 1531static void sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1532{
6b1a3aef 1533 struct sky2_hw *hw = sky2->hw;
14d0263f 1534 struct rx_ring_info *re;
6b1a3aef 1535 unsigned rxq = rxqaddr[sky2->port];
39ef110b 1536 unsigned i, thresh;
cd28ab6a 1537
6b1a3aef 1538 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1539 sky2_qset(hw, rxq);
977bdf06 1540
c3905bc4 1541 /* On PCI express lowering the watermark gives better performance */
1a10ccae 1542 if (pci_is_pcie(hw->pdev))
c3905bc4
SH		 1543 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1544
1545 /* These chips have no ram buffer?
1546 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1547 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c1cd0a85 1548 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
f449c7c1 1549 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
977bdf06 1550
6b1a3aef 1551 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1552
ea76e635
SH		 1553 if (!(hw->flags & SKY2_HW_NEW_LE))
1554 rx_set_checksum(sky2);
14d0263f 1555
bf73130d 1556 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037 1557 rx_set_rss(sky2->netdev, sky2->netdev->features);
bf73130d 1558
200ac492 1559 /* submit Rx ring */
793b883e 1560 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1561 re = sky2->rx_ring + i;
14d0263f 1562 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1563 }
1564
a1433ac4
SH		 1565 /*
1566 * The receiver hangs if it receives frames larger than the
1567 * packet buffer. As a workaround, truncate oversize frames, but
1568 * the register is limited to 9 bits, so if you do frames > 2052
1569 * you better get the MTU right!
1570 */
39ef110b 1571 thresh = sky2_get_rx_threshold(sky2);
a1433ac4
SH		 1572 if (thresh > 0x1ff)
1573 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1574 else {
1575 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1576 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1577 }
1578
6b1a3aef 1579 /* Tell chip about available buffers */
55c9dd35 1580 sky2_rx_update(sky2, rxq);
877c8570
SH		 1581
1582 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1583 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1584 /*
1585 * Disable flushing of non ASF packets;
1586 * must be done after initializing the BMUs;
1587 * drivers without ASF support should do this too, otherwise
1588 * it may happen that they cannot run on ASF devices;
1589 * remember that the MAC FIFO isn't reset during initialization.
1590 */
1591 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1592 }
1593
1594 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1595 /* Enable RX Home Address & Routing Header checksum fix */
1596 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1597 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1598
1599 /* Enable TX Home Address & Routing Header checksum fix */
1600 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1601 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1602 }
cd28ab6a
SH		 1603}
1604
90bbebb4
MM		 1605static int sky2_alloc_buffers(struct sky2_port *sky2)
1606{
1607 struct sky2_hw *hw = sky2->hw;
1608
1609 /* must be power of 2 */
1610 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1611 sky2->tx_ring_size *
1612 sizeof(struct sky2_tx_le),
1613 &sky2->tx_le_map);
1614 if (!sky2->tx_le)
1615 goto nomem;
1616
1617 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1618 GFP_KERNEL);
1619 if (!sky2->tx_ring)
1620 goto nomem;
1621
1622 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1623 &sky2->rx_le_map);
1624 if (!sky2->rx_le)
1625 goto nomem;
1626 memset(sky2->rx_le, 0, RX_LE_BYTES);
1627
1628 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1629 GFP_KERNEL);
1630 if (!sky2->rx_ring)
1631 goto nomem;
1632
200ac492 1633 return sky2_alloc_rx_skbs(sky2);
90bbebb4
MM		 1634nomem:
1635 return -ENOMEM;
1636}
1637
1638static void sky2_free_buffers(struct sky2_port *sky2)
1639{
1640 struct sky2_hw *hw = sky2->hw;
1641
200ac492
MM		 1642 sky2_rx_clean(sky2);
1643
90bbebb4
MM		 1644 if (sky2->rx_le) {
1645 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1646 sky2->rx_le, sky2->rx_le_map);
1647 sky2->rx_le = NULL;
1648 }
1649 if (sky2->tx_le) {
1650 pci_free_consistent(hw->pdev,
1651 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1652 sky2->tx_le, sky2->tx_le_map);
1653 sky2->tx_le = NULL;
1654 }
1655 kfree(sky2->tx_ring);
1656 kfree(sky2->rx_ring);
1657
1658 sky2->tx_ring = NULL;
1659 sky2->rx_ring = NULL;
1660}
1661
ea0f71e5 1662static void sky2_hw_up(struct sky2_port *sky2)
cd28ab6a 1663{
cd28ab6a
SH		 1664 struct sky2_hw *hw = sky2->hw;
1665 unsigned port = sky2->port;
ea0f71e5
MM		 1666 u32 ramsize;
1667 int cap;
843a46f4 1668 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1669
ea0f71e5
MM		 1670 tx_init(sky2);
1671
ee7abb04
SH		 1672 /*
1673 * On dual port PCI-X card, there is an problem where status
1674 * can be received out of order due to split transactions
843a46f4 1675 */
ee7abb04
SH		 1676 if (otherdev && netif_running(otherdev) &&
1677 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
ee7abb04
SH		 1678 u16 cmd;
1679
b32f40c4 1680 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
ee7abb04 1681 cmd &= ~PCI_X_CMD_MAX_SPLIT;
b32f40c4 1682 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
ea0f71e5 1683 }
cd28ab6a 1684
cd28ab6a
SH		 1685 sky2_mac_init(hw, port);
1686
e0c28116
SH		 1687 /* Register is number of 4K blocks on internal RAM buffer. */
1688 ramsize = sky2_read8(hw, B2_E_0) * 4;
1689 if (ramsize > 0) {
67712901 1690 u32 rxspace;
cd28ab6a 1691
ada1db5c 1692 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
67712901
SH		 1693 if (ramsize < 16)
1694 rxspace = ramsize / 2;
1695 else
1696 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1697
67712901
SH		 1698 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1699 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1700
1701 /* Make sure SyncQ is disabled */
1702 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1703 RB_RST_SET);
1704 }
793b883e 1705
af4ed7e6 1706 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1707
69161611
SH		 1708 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1709 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1710 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1711
977bdf06 1712 /* Set almost empty threshold */
8e95a202
JP		 1713 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1714 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
b628ed98 1715 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
5a5b1ea0 1716
6b1a3aef 1717 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
ee5f68fe 1718 sky2->tx_ring_size - 1);
cd28ab6a 1719
f5d64037
MM		 1720 sky2_vlan_mode(sky2->netdev, sky2->netdev->features);
1721 netdev_update_features(sky2->netdev);
d494eacd 1722
200ac492 1723 sky2_rx_start(sky2);
ea0f71e5
MM		 1724}
1725
0bdb0bd0 1726/* Setup device IRQ and enable napi to process */
1727static int sky2_setup_irq(struct sky2_hw *hw, const char *name)
1728{
1729 struct pci_dev *pdev = hw->pdev;
1730 int err;
1731
1732 err = request_irq(pdev->irq, sky2_intr,
1733 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
1734 name, hw);
1735 if (err)
1736 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
1737 else {
282edcec 1738 hw->flags |= SKY2_HW_IRQ_SETUP;
1739
0bdb0bd0 1740 napi_enable(&hw->napi);
1741 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1742 sky2_read32(hw, B0_IMSK);
1743 }
1744
1745 return err;
1746}
1747
1748
ea0f71e5 1749/* Bring up network interface. */
926d0977 1750static int sky2_open(struct net_device *dev)
ea0f71e5
MM		 1751{
1752 struct sky2_port *sky2 = netdev_priv(dev);
1753 struct sky2_hw *hw = sky2->hw;
1754 unsigned port = sky2->port;
1755 u32 imask;
1756 int err;
1757
1758 netif_carrier_off(dev);
1759
1760 err = sky2_alloc_buffers(sky2);
1761 if (err)
1762 goto err_out;
1763
0bdb0bd0 1764 /* With single port, IRQ is setup when device is brought up */
1765 if (hw->ports == 1 && (err = sky2_setup_irq(hw, dev->name)))
1766 goto err_out;
1767
ea0f71e5 1768 sky2_hw_up(sky2);
cd28ab6a 1769
2240eb4a
LS		 1770 /* Enable interrupts from phy/mac for port */
1771 imask = sky2_read32(hw, B0_IMSK);
1772
1401a800 1773 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
1774 hw->chip_id == CHIP_ID_YUKON_PRM ||
1775 hw->chip_id == CHIP_ID_YUKON_OP_2)
1776 imask |= Y2_IS_PHY_QLNK; /* enable PHY Quick Link */
1777
f4ea431b 1778 imask |= portirq_msk[port];
e07b1aa8 1779 sky2_write32(hw, B0_IMSK, imask);
1fd82f3c 1780 sky2_read32(hw, B0_IMSK);
e07b1aa8 1781
6c35abae 1782 netif_info(sky2, ifup, dev, "enabling interface\n");
af18d8b8 1783
cd28ab6a
SH		 1784 return 0;
1785
1786err_out:
90bbebb4 1787 sky2_free_buffers(sky2);
cd28ab6a
SH		 1788 return err;
1789}
1790
793b883e 1791/* Modular subtraction in ring */
ee5f68fe 1792static inline int tx_inuse(const struct sky2_port *sky2)
793b883e 1793{
ee5f68fe 1794 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
793b883e 1795}
cd28ab6a 1796
793b883e
SH		 1797/* Number of list elements available for next tx */
1798static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1799{
ee5f68fe 1800 return sky2->tx_pending - tx_inuse(sky2);
cd28ab6a
SH		 1801}
1802
793b883e 1803/* Estimate of number of transmit list elements required */
28bd181a 1804static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1805{
793b883e
SH		 1806 unsigned count;
1807
07e31637
SH		 1808 count = (skb_shinfo(skb)->nr_frags + 1)
1809 * (sizeof(dma_addr_t) / sizeof(u32));
793b883e 1810
89114afd 1811 if (skb_is_gso(skb))
793b883e 1812 ++count;
07e31637
SH		 1813 else if (sizeof(dma_addr_t) == sizeof(u32))
1814 ++count; /* possible vlan */
793b883e 1815
84fa7933 1816 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1817 ++count;
1818
1819 return count;
cd28ab6a
SH		 1820}
1821
f6815077 1822static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
6b84daca
SH		 1823{
1824 if (re->flags & TX_MAP_SINGLE)
7cd26ce5
FT		 1825 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1826 dma_unmap_len(re, maplen),
6b84daca
SH		 1827 PCI_DMA_TODEVICE);
1828 else if (re->flags & TX_MAP_PAGE)
7cd26ce5
FT		 1829 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1830 dma_unmap_len(re, maplen),
6b84daca 1831 PCI_DMA_TODEVICE);
f6815077 1832 re->flags = 0;
6b84daca
SH		 1833}
1834
793b883e
SH		 1835/*
1836 * Put one packet in ring for transmit.
1837 * A single packet can generate multiple list elements, and
1838 * the number of ring elements will probably be less than the number
1839 * of list elements used.
1840 */
61357325
SH		 1841static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1842 struct net_device *dev)
cd28ab6a
SH		 1843{
1844 struct sky2_port *sky2 = netdev_priv(dev);
1845 struct sky2_hw *hw = sky2->hw;
d1f13708 1846 struct sky2_tx_le *le = NULL;
6cdbbdf3 1847 struct tx_ring_info *re;
9b289c33 1848 unsigned i, len;
cd28ab6a 1849 dma_addr_t mapping;
5dce95e5
SH		 1850 u32 upper;
1851 u16 slot;
cd28ab6a
SH		 1852 u16 mss;
1853 u8 ctrl;
1854
2bb8c262
SH		 1855 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1856 return NETDEV_TX_BUSY;
cd28ab6a 1857
cd28ab6a
SH		 1858 len = skb_headlen(skb);
1859 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
793b883e 1860
454e6cb6
SH		 1861 if (pci_dma_mapping_error(hw->pdev, mapping))
1862 goto mapping_error;
1863
9b289c33 1864 slot = sky2->tx_prod;
6c35abae
JP		 1865 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1866 "tx queued, slot %u, len %d\n", slot, skb->len);
454e6cb6 1867
86c6887e 1868 /* Send high bits if needed */
5dce95e5
SH		 1869 upper = upper_32_bits(mapping);
1870 if (upper != sky2->tx_last_upper) {
9b289c33 1871 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1872 le->addr = cpu_to_le32(upper);
1873 sky2->tx_last_upper = upper;
793b883e 1874 le->opcode = OP_ADDR64 | HW_OWNER;
793b883e 1875 }
cd28ab6a
SH		 1876
1877 /* Check for TCP Segmentation Offload */
7967168c 1878 mss = skb_shinfo(skb)->gso_size;
793b883e 1879 if (mss != 0) {
ea76e635
SH		 1880
1881 if (!(hw->flags & SKY2_HW_NEW_LE))
69161611
SH		 1882 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1883
1884 if (mss != sky2->tx_last_mss) {
9b289c33 1885 le = get_tx_le(sky2, &slot);
69161611 1886 le->addr = cpu_to_le32(mss);
ea76e635
SH		 1887
1888 if (hw->flags & SKY2_HW_NEW_LE)
69161611
SH		 1889 le->opcode = OP_MSS | HW_OWNER;
1890 else
1891 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd 1892 sky2->tx_last_mss = mss;
1893 }
cd28ab6a
SH		 1894 }
1895
cd28ab6a 1896 ctrl = 0;
86aa7785 1897
d1f13708 1898 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
eab6d18d 1899 if (vlan_tx_tag_present(skb)) {
d1f13708 1900 if (!le) {
9b289c33 1901 le = get_tx_le(sky2, &slot);
f65b138c 1902 le->addr = 0;
d1f13708 1903 le->opcode = OP_VLAN|HW_OWNER;
d1f13708 1904 } else
1905 le->opcode |= OP_VLAN;
1906 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1907 ctrl |= INS_VLAN;
1908 }
d1f13708 1909
1910 /* Handle TCP checksum offload */
84fa7933 1911 if (skb->ip_summed == CHECKSUM_PARTIAL) {
69161611 1912 /* On Yukon EX (some versions) encoding change. */
ea76e635 1913 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
69161611
SH		 1914 ctrl |= CALSUM; /* auto checksum */
1915 else {
1916 const unsigned offset = skb_transport_offset(skb);
1917 u32 tcpsum;
1918
1919 tcpsum = offset << 16; /* sum start */
1920 tcpsum |= offset + skb->csum_offset; /* sum write */
1921
1922 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1923 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1924 ctrl |= UDPTCP;
1925
1926 if (tcpsum != sky2->tx_tcpsum) {
1927 sky2->tx_tcpsum = tcpsum;
1928
9b289c33 1929 le = get_tx_le(sky2, &slot);
69161611
SH		 1930 le->addr = cpu_to_le32(tcpsum);
1931 le->length = 0; /* initial checksum value */
1932 le->ctrl = 1; /* one packet */
1933 le->opcode = OP_TCPLISW | HW_OWNER;
1934 }
1d179332 1935 }
cd28ab6a
SH		 1936 }
1937
6b84daca
SH		 1938 re = sky2->tx_ring + slot;
1939 re->flags = TX_MAP_SINGLE;
7cd26ce5
FT		 1940 dma_unmap_addr_set(re, mapaddr, mapping);
1941 dma_unmap_len_set(re, maplen, len);
6b84daca 1942
9b289c33 1943 le = get_tx_le(sky2, &slot);
d6e74b6b 1944 le->addr = cpu_to_le32(lower_32_bits(mapping));
cd28ab6a
SH		 1945 le->length = cpu_to_le16(len);
1946 le->ctrl = ctrl;
793b883e 1947 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1948
cd28ab6a
SH		 1949
1950 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1951 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a 1952
950a5a4f 1953 mapping = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
9e903e08 1954 skb_frag_size(frag), DMA_TO_DEVICE);
86c6887e 1955
5d6bcdfe 1956 if (dma_mapping_error(&hw->pdev->dev, mapping))
454e6cb6
SH		 1957 goto mapping_unwind;
1958
5dce95e5
SH		 1959 upper = upper_32_bits(mapping);
1960 if (upper != sky2->tx_last_upper) {
9b289c33 1961 le = get_tx_le(sky2, &slot);
5dce95e5
SH		 1962 le->addr = cpu_to_le32(upper);
1963 sky2->tx_last_upper = upper;
793b883e 1964 le->opcode = OP_ADDR64 | HW_OWNER;
cd28ab6a
SH		 1965 }
1966
6b84daca
SH		 1967 re = sky2->tx_ring + slot;
1968 re->flags = TX_MAP_PAGE;
7cd26ce5 1969 dma_unmap_addr_set(re, mapaddr, mapping);
9e903e08 1970 dma_unmap_len_set(re, maplen, skb_frag_size(frag));
6b84daca 1971
9b289c33 1972 le = get_tx_le(sky2, &slot);
d6e74b6b 1973 le->addr = cpu_to_le32(lower_32_bits(mapping));
9e903e08 1974 le->length = cpu_to_le16(skb_frag_size(frag));
cd28ab6a 1975 le->ctrl = ctrl;
793b883e 1976 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1977 }
6cdbbdf3 1978
6b84daca 1979 re->skb = skb;
cd28ab6a
SH		 1980 le->ctrl |= EOP;
1981
9b289c33
MM		 1982 sky2->tx_prod = slot;
1983
97bda706 1984 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1985 netif_stop_queue(dev);
b19666d9 1986
ec2a5466 1987 netdev_sent_queue(dev, skb->len);
290d4de5 1988 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1989
cd28ab6a 1990 return NETDEV_TX_OK;
454e6cb6
SH		 1991
1992mapping_unwind:
ee5f68fe 1993 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
454e6cb6
SH		 1994 re = sky2->tx_ring + i;
1995
6b84daca 1996 sky2_tx_unmap(hw->pdev, re);
454e6cb6
SH		 1997 }
1998
454e6cb6
SH		 1999mapping_error:
2000 if (net_ratelimit())
2001 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2002 dev_kfree_skb(skb);
2003 return NETDEV_TX_OK;
cd28ab6a
SH		 2004}
2005
cd28ab6a 2006/*
793b883e
SH		 2007 * Free ring elements from starting at tx_cons until "done"
2008 *
481cea4a
SH		 2009 * NB:
2010 * 1. The hardware will tell us about partial completion of multi-part
291ea614 2011 * buffers so make sure not to free skb to early.
481cea4a
SH		 2012 * 2. This may run in parallel start_xmit because the it only
2013 * looks at the tail of the queue of FIFO (tx_cons), not
2014 * the head (tx_prod)
cd28ab6a 2015 */
d11c13e7 2016static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 2017{
d11c13e7 2018 struct net_device *dev = sky2->netdev;
ec2a5466 2019 u16 idx;
2020 unsigned int bytes_compl = 0, pkts_compl = 0;
cd28ab6a 2021
ee5f68fe 2022 BUG_ON(done >= sky2->tx_ring_size);
2224795d 2023
291ea614 2024 for (idx = sky2->tx_cons; idx != done;
ee5f68fe 2025 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
291ea614 2026 struct tx_ring_info *re = sky2->tx_ring + idx;
6b84daca 2027 struct sk_buff *skb = re->skb;
291ea614 2028
6b84daca 2029 sky2_tx_unmap(sky2->hw->pdev, re);
bd1c6869 2030
6b84daca 2031 if (skb) {
6c35abae
JP		 2032 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
2033 "tx done %u\n", idx);
3cf26753 2034
ec2a5466 2035 pkts_compl++;
2036 bytes_compl += skb->len;
bd1c6869 2037
f6815077 2038 re->skb = NULL;
724b6942 2039 dev_kfree_skb_any(skb);
2bf56fe2 2040
ee5f68fe 2041 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
cd28ab6a 2042 }
793b883e 2043 }
793b883e 2044
291ea614 2045 sky2->tx_cons = idx;
50432cb5 2046 smp_mb();
ec2a5466 2047
2048 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2049
2050 u64_stats_update_begin(&sky2->tx_stats.syncp);
2051 sky2->tx_stats.packets += pkts_compl;
2052 sky2->tx_stats.bytes += bytes_compl;
2053 u64_stats_update_end(&sky2->tx_stats.syncp);
cd28ab6a
SH		 2054}
2055
264bb4fa 2056static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
a510996b 2057{
a510996b
MM		 2058 /* Disable Force Sync bit and Enable Alloc bit */
2059 sky2_write8(hw, SK_REG(port, TXA_CTRL),
2060 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2061
2062 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2063 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2064 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2065
2066 /* Reset the PCI FIFO of the async Tx queue */
2067 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2068 BMU_RST_SET | BMU_FIFO_RST);
2069
2070 /* Reset the Tx prefetch units */
2071 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2072 PREF_UNIT_RST_SET);
2073
2074 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2075 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
f9687c44 2076
2077 sky2_read32(hw, B0_CTST);
a510996b
MM		 2078}
2079
f2b31cb3 2080static void sky2_hw_down(struct sky2_port *sky2)
cd28ab6a 2081{
cd28ab6a
SH		 2082 struct sky2_hw *hw = sky2->hw;
2083 unsigned port = sky2->port;
f2b31cb3 2084 u16 ctrl;
cd28ab6a 2085
d104acaf
SH		 2086 /* Force flow control off */
2087 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e 2088
cd28ab6a
SH		 2089 /* Stop transmitter */
2090 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2091 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
2092
2093 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 2094 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 2095
2096 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 2097 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 2098 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2099
2100 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2101
2102 /* Workaround shared GMAC reset */
8e95a202
JP		 2103 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
2104 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 2105 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2106
cd28ab6a 2107 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
cd28ab6a 2108
fb914ebf 2109 /* Force any delayed status interrupt and NAPI */
6c83504f
SH		 2110 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2111 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2112 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2113 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
2114
a947a39d
MM		 2115 sky2_rx_stop(sky2);
2116
0da6d7b3 2117 spin_lock_bh(&sky2->phy_lock);
b96936da 2118 sky2_phy_power_down(hw, port);
0da6d7b3 2119 spin_unlock_bh(&sky2->phy_lock);
d3bcfbeb 2120
264bb4fa
MM		 2121 sky2_tx_reset(hw, port);
2122
481cea4a
SH		 2123 /* Free any pending frames stuck in HW queue */
2124 sky2_tx_complete(sky2, sky2->tx_prod);
f2b31cb3
MM		 2125}
2126
2127/* Network shutdown */
926d0977 2128static int sky2_close(struct net_device *dev)
f2b31cb3
MM		 2129{
2130 struct sky2_port *sky2 = netdev_priv(dev);
8a0c9228 2131 struct sky2_hw *hw = sky2->hw;
f2b31cb3
MM		 2132
2133 /* Never really got started! */
2134 if (!sky2->tx_le)
2135 return 0;
2136
6c35abae 2137 netif_info(sky2, ifdown, dev, "disabling interface\n");
f2b31cb3 2138
0bdb0bd0 2139 if (hw->ports == 1) {
1401a800 2140 sky2_write32(hw, B0_IMSK, 0);
2141 sky2_read32(hw, B0_IMSK);
2142
0bdb0bd0 2143 napi_disable(&hw->napi);
2144 free_irq(hw->pdev->irq, hw);
282edcec 2145 hw->flags &= ~SKY2_HW_IRQ_SETUP;
0bdb0bd0 2146 } else {
1401a800 2147 u32 imask;
2148
2149 /* Disable port IRQ */
2150 imask = sky2_read32(hw, B0_IMSK);
2151 imask &= ~portirq_msk[sky2->port];
2152 sky2_write32(hw, B0_IMSK, imask);
2153 sky2_read32(hw, B0_IMSK);
2154
0bdb0bd0 2155 synchronize_irq(hw->pdev->irq);
2156 napi_synchronize(&hw->napi);
2157 }
8a0c9228 2158
f2b31cb3 2159 sky2_hw_down(sky2);
481cea4a 2160
90bbebb4 2161 sky2_free_buffers(sky2);
1b537565 2162
cd28ab6a
SH		 2163 return 0;
2164}
2165
2166static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2167{
ea76e635 2168 if (hw->flags & SKY2_HW_FIBRE_PHY)
793b883e
SH		 2169 return SPEED_1000;
2170
05745c4a
SH		 2171 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2172 if (aux & PHY_M_PS_SPEED_100)
2173 return SPEED_100;
2174 else
2175 return SPEED_10;
2176 }
cd28ab6a
SH		 2177
2178 switch (aux & PHY_M_PS_SPEED_MSK) {
2179 case PHY_M_PS_SPEED_1000:
2180 return SPEED_1000;
2181 case PHY_M_PS_SPEED_100:
2182 return SPEED_100;
2183 default:
2184 return SPEED_10;
2185 }
2186}
2187
2188static void sky2_link_up(struct sky2_port *sky2)
2189{
2190 struct sky2_hw *hw = sky2->hw;
2191 unsigned port = sky2->port;
16ad91e1
SH		 2192 static const char *fc_name[] = {
2193 [FC_NONE] = "none",
2194 [FC_TX] = "tx",
2195 [FC_RX] = "rx",
2196 [FC_BOTH] = "both",
2197 };
cd28ab6a 2198
8e11680f 2199 sky2_set_ipg(sky2);
2200
38000a94 2201 sky2_enable_rx_tx(sky2);
cd28ab6a
SH		 2202
2203 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2204
2205 netif_carrier_on(sky2->netdev);
cd28ab6a 2206
75e80683 2207 mod_timer(&hw->watchdog_timer, jiffies + 1);
32c2c300 2208
cd28ab6a 2209 /* Turn on link LED */
793b883e 2210 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 2211 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2212
6c35abae
JP		 2213 netif_info(sky2, link, sky2->netdev,
2214 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2215 sky2->speed,
2216 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2217 fc_name[sky2->flow_status]);
cd28ab6a
SH		 2218}
2219
2220static void sky2_link_down(struct sky2_port *sky2)
2221{
2222 struct sky2_hw *hw = sky2->hw;
2223 unsigned port = sky2->port;
2224 u16 reg;
2225
2226 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2227
2228 reg = gma_read16(hw, port, GM_GP_CTRL);
2229 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2230 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 2231
cd28ab6a 2232 netif_carrier_off(sky2->netdev);
cd28ab6a 2233
809aaaae 2234 /* Turn off link LED */
cd28ab6a
SH		 2235 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2236
6c35abae 2237 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2eaba1a2 2238
cd28ab6a
SH		 2239 sky2_phy_init(hw, port);
2240}
2241
16ad91e1
SH		 2242static enum flow_control sky2_flow(int rx, int tx)
2243{
2244 if (rx)
2245 return tx ? FC_BOTH : FC_RX;
2246 else
2247 return tx ? FC_TX : FC_NONE;
2248}
2249
793b883e
SH		 2250static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2251{
2252 struct sky2_hw *hw = sky2->hw;
2253 unsigned port = sky2->port;
da4c1ff4 2254 u16 advert, lpa;
793b883e 2255
da4c1ff4 2256 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 2257 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e 2258 if (lpa & PHY_M_AN_RF) {
ada1db5c 2259 netdev_err(sky2->netdev, "remote fault\n");
793b883e
SH		 2260 return -1;
2261 }
2262
793b883e 2263 if (!(aux & PHY_M_PS_SPDUP_RES)) {
ada1db5c 2264 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
793b883e
SH		 2265 return -1;
2266 }
2267
793b883e 2268 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 2269 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 2270
da4c1ff4
SH		 2271 /* Since the pause result bits seem to in different positions on
2272 * different chips. look at registers.
2273 */
ea76e635 2274 if (hw->flags & SKY2_HW_FIBRE_PHY) {
da4c1ff4
SH		 2275 /* Shift for bits in fiber PHY */
2276 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2277 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2278
2279 if (advert & ADVERTISE_1000XPAUSE)
2280 advert |= ADVERTISE_PAUSE_CAP;
2281 if (advert & ADVERTISE_1000XPSE_ASYM)
2282 advert |= ADVERTISE_PAUSE_ASYM;
2283 if (lpa & LPA_1000XPAUSE)
2284 lpa |= LPA_PAUSE_CAP;
2285 if (lpa & LPA_1000XPAUSE_ASYM)
2286 lpa |= LPA_PAUSE_ASYM;
2287 }
793b883e 2288
da4c1ff4
SH		 2289 sky2->flow_status = FC_NONE;
2290 if (advert & ADVERTISE_PAUSE_CAP) {
2291 if (lpa & LPA_PAUSE_CAP)
2292 sky2->flow_status = FC_BOTH;
2293 else if (advert & ADVERTISE_PAUSE_ASYM)
2294 sky2->flow_status = FC_RX;
2295 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2296 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2297 sky2->flow_status = FC_TX;
2298 }
793b883e 2299
8e95a202
JP		 2300 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2301 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 2302 sky2->flow_status = FC_NONE;
2eaba1a2 2303
da4c1ff4 2304 if (sky2->flow_status & FC_TX)
793b883e
SH		 2305 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2306 else
2307 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2308
2309 return 0;
2310}
cd28ab6a 2311
e07b1aa8
SH		 2312/* Interrupt from PHY */
2313static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 2314{
e07b1aa8
SH		 2315 struct net_device *dev = hw->dev[port];
2316 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2317 u16 istatus, phystat;
2318
ebc646f6
SH		 2319 if (!netif_running(dev))
2320 return;
2321
e07b1aa8
SH		 2322 spin_lock(&sky2->phy_lock);
2323 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2324 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2325
6c35abae
JP		 2326 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2327 istatus, phystat);
cd28ab6a 2328
0ea065e5 2329 if (istatus & PHY_M_IS_AN_COMPL) {
9badba25 2330 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2331 !netif_carrier_ok(dev))
793b883e
SH		 2332 sky2_link_up(sky2);
2333 goto out;
2334 }
cd28ab6a 2335
793b883e
SH		 2336 if (istatus & PHY_M_IS_LSP_CHANGE)
2337 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 2338
793b883e
SH		 2339 if (istatus & PHY_M_IS_DUP_CHANGE)
2340 sky2->duplex =
2341 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 2342
793b883e
SH		 2343 if (istatus & PHY_M_IS_LST_CHANGE) {
2344 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 2345 sky2_link_up(sky2);
793b883e
SH		 2346 else
2347 sky2_link_down(sky2);
cd28ab6a 2348 }
793b883e 2349out:
e07b1aa8 2350 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 2351}
2352
0f5aac70
SH		 2353/* Special quick link interrupt (Yukon-2 Optima only) */
2354static void sky2_qlink_intr(struct sky2_hw *hw)
2355{
2356 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2357 u32 imask;
2358 u16 phy;
2359
2360 /* disable irq */
2361 imask = sky2_read32(hw, B0_IMSK);
2362 imask &= ~Y2_IS_PHY_QLNK;
2363 sky2_write32(hw, B0_IMSK, imask);
2364
2365 /* reset PHY Link Detect */
2366 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
a40ccc68 2367 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70 2368 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
a40ccc68 2369 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 2370
2371 sky2_link_up(sky2);
2372}
2373
62335ab0 2374/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 2375 * and tx queue is full (stopped).
2376 */
cd28ab6a
SH		 2377static void sky2_tx_timeout(struct net_device *dev)
2378{
2379 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 2380 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2381
6c35abae 2382 netif_err(sky2, timer, dev, "tx timeout\n");
cd28ab6a 2383
ada1db5c
JP		 2384 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2385 sky2->tx_cons, sky2->tx_prod,
2386 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2387 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 2388
81906791
SH		 2389 /* can't restart safely under softirq */
2390 schedule_work(&hw->restart_work);
cd28ab6a
SH		 2391}
2392
2393static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2394{
6b1a3aef 2395 struct sky2_port *sky2 = netdev_priv(dev);
2396 struct sky2_hw *hw = sky2->hw;
b628ed98 2397 unsigned port = sky2->port;
6b1a3aef 2398 int err;
2399 u16 ctl, mode;
e07b1aa8 2400 u32 imask;
cd28ab6a 2401
44dde56d 2402 /* MTU size outside the spec */
cd28ab6a
SH		 2403 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2404 return -EINVAL;
2405
44dde56d 2406 /* MTU > 1500 on yukon FE and FE+ not allowed */
05745c4a
SH		 2407 if (new_mtu > ETH_DATA_LEN &&
2408 (hw->chip_id == CHIP_ID_YUKON_FE ||
2409 hw->chip_id == CHIP_ID_YUKON_FE_P))
d2adf4f6
SH		 2410 return -EINVAL;
2411
6b1a3aef 2412 if (!netif_running(dev)) {
2413 dev->mtu = new_mtu;
f5d64037 2414 netdev_update_features(dev);
6b1a3aef 2415 return 0;
2416 }
2417
e07b1aa8 2418 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef 2419 sky2_write32(hw, B0_IMSK, 0);
2420
018d1c66 2421 dev->trans_start = jiffies; /* prevent tx timeout */
bea3348e 2422 napi_disable(&hw->napi);
df01093b 2423 netif_tx_disable(dev);
018d1c66 2424
e07b1aa8
SH		 2425 synchronize_irq(hw->pdev->irq);
2426
39dbd958 2427 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
69161611 2428 sky2_set_tx_stfwd(hw, port);
b628ed98
SH		 2429
2430 ctl = gma_read16(hw, port, GM_GP_CTRL);
2431 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
6b1a3aef 2432 sky2_rx_stop(sky2);
2433 sky2_rx_clean(sky2);
cd28ab6a
SH		 2434
2435 dev->mtu = new_mtu;
f5d64037 2436 netdev_update_features(dev);
14d0263f 2437
8e11680f 2438 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | GM_SMOD_VLAN_ENA;
2439 if (sky2->speed > SPEED_100)
2440 mode |= IPG_DATA_VAL(IPG_DATA_DEF_1000);
2441 else
2442 mode |= IPG_DATA_VAL(IPG_DATA_DEF_10_100);
6b1a3aef 2443
2444 if (dev->mtu > ETH_DATA_LEN)
2445 mode |= GM_SMOD_JUMBO_ENA;
2446
b628ed98 2447 gma_write16(hw, port, GM_SERIAL_MODE, mode);
cd28ab6a 2448
b628ed98 2449 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 2450
200ac492
MM		 2451 err = sky2_alloc_rx_skbs(sky2);
2452 if (!err)
2453 sky2_rx_start(sky2);
2454 else
2455 sky2_rx_clean(sky2);
e07b1aa8 2456 sky2_write32(hw, B0_IMSK, imask);
018d1c66 2457
d1d08d12 2458 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e
SH		 2459 napi_enable(&hw->napi);
2460
1b537565
SH		 2461 if (err)
2462 dev_close(dev);
2463 else {
b628ed98 2464 gma_write16(hw, port, GM_GP_CTRL, ctl);
1b537565 2465
1b537565
SH		 2466 netif_wake_queue(dev);
2467 }
2468
cd28ab6a
SH		 2469 return err;
2470}
2471
857504d0 2472static inline bool needs_copy(const struct rx_ring_info *re,
2473 unsigned length)
2474{
2475#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2476 /* Some architectures need the IP header to be aligned */
2477 if (!IS_ALIGNED(re->data_addr + ETH_HLEN, sizeof(u32)))
2478 return true;
2479#endif
2480 return length < copybreak;
2481}
2482
14d0263f
SH		 2483/* For small just reuse existing skb for next receive */
2484static struct sk_buff *receive_copy(struct sky2_port *sky2,
2485 const struct rx_ring_info *re,
2486 unsigned length)
2487{
2488 struct sk_buff *skb;
2489
89d71a66 2490 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
14d0263f 2491 if (likely(skb)) {
14d0263f
SH		 2492 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2493 length, PCI_DMA_FROMDEVICE);
d626f62b 2494 skb_copy_from_linear_data(re->skb, skb->data, length);
14d0263f
SH		 2495 skb->ip_summed = re->skb->ip_summed;
2496 skb->csum = re->skb->csum;
3f42941b 2497 skb->rxhash = re->skb->rxhash;
e072b3fa 2498 skb->vlan_tci = re->skb->vlan_tci;
3f42941b 2499
14d0263f
SH		 2500 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2501 length, PCI_DMA_FROMDEVICE);
e072b3fa 2502 re->skb->vlan_tci = 0;
3f42941b 2503 re->skb->rxhash = 0;
14d0263f 2504 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 2505 skb_put(skb, length);
14d0263f
SH		 2506 }
2507 return skb;
2508}
2509
2510/* Adjust length of skb with fragments to match received data */
2511static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2512 unsigned int length)
2513{
2514 int i, num_frags;
2515 unsigned int size;
2516
2517 /* put header into skb */
2518 size = min(length, hdr_space);
2519 skb->tail += size;
2520 skb->len += size;
2521 length -= size;
2522
2523 num_frags = skb_shinfo(skb)->nr_frags;
2524 for (i = 0; i < num_frags; i++) {
2525 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2526
2527 if (length == 0) {
2528 /* don't need this page */
950a5a4f 2529 __skb_frag_unref(frag);
14d0263f
SH		 2530 --skb_shinfo(skb)->nr_frags;
2531 } else {
2532 size = min(length, (unsigned) PAGE_SIZE);
2533
9e903e08 2534 skb_frag_size_set(frag, size);
14d0263f 2535 skb->data_len += size;
7ae60b3f 2536 skb->truesize += PAGE_SIZE;
14d0263f
SH		 2537 skb->len += size;
2538 length -= size;
2539 }
2540 }
2541}
2542
2543/* Normal packet - take skb from ring element and put in a new one */
2544static struct sk_buff *receive_new(struct sky2_port *sky2,
2545 struct rx_ring_info *re,
2546 unsigned int length)
2547{
3fbd9187 2548 struct sk_buff *skb;
2549 struct rx_ring_info nre;
14d0263f
SH		 2550 unsigned hdr_space = sky2->rx_data_size;
2551
68ac3191 2552 nre.skb = sky2_rx_alloc(sky2, GFP_ATOMIC);
3fbd9187 2553 if (unlikely(!nre.skb))
2554 goto nobuf;
2555
2556 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2557 goto nomap;
14d0263f
SH		 2558
2559 skb = re->skb;
2560 sky2_rx_unmap_skb(sky2->hw->pdev, re);
14d0263f 2561 prefetch(skb->data);
3fbd9187 2562 *re = nre;
14d0263f
SH		 2563
2564 if (skb_shinfo(skb)->nr_frags)
2565 skb_put_frags(skb, hdr_space, length);
2566 else
489b10c1 2567 skb_put(skb, length);
14d0263f 2568 return skb;
3fbd9187 2569
2570nomap:
2571 dev_kfree_skb(nre.skb);
2572nobuf:
2573 return NULL;
14d0263f
SH		 2574}
2575
cd28ab6a
SH		 2576/*
2577 * Receive one packet.
d571b694 2578 * For larger packets, get new buffer.
cd28ab6a 2579 */
497d7c86 2580static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2581 u16 length, u32 status)
2582{
497d7c86 2583 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2584 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2585 struct sk_buff *skb = NULL;
d6532232
SH		 2586 u16 count = (status & GMR_FS_LEN) >> 16;
2587
6c35abae
JP		 2588 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2589 "rx slot %u status 0x%x len %d\n",
2590 sky2->rx_next, status, length);
cd28ab6a 2591
793b883e 2592 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2593 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2594
e072b3fa 2595 if (vlan_tx_tag_present(re->skb))
2596 count -= VLAN_HLEN; /* Account for vlan tag */
2597
3b12e014
SH		 2598 /* This chip has hardware problems that generates bogus status.
2599 * So do only marginal checking and expect higher level protocols
2600 * to handle crap frames.
2601 */
2602 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2603 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2604 length != count)
2605 goto okay;
2606
42eeea01 2607 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2608 goto error;
2609
42eeea01 2610 if (!(status & GMR_FS_RX_OK))
2611 goto resubmit;
2612
d6532232
SH		 2613 /* if length reported by DMA does not match PHY, packet was truncated */
2614 if (length != count)
0885a30b 2615 goto error;
71749531 2616
3b12e014 2617okay:
857504d0 2618 if (needs_copy(re, length))
14d0263f
SH		 2619 skb = receive_copy(sky2, re, length);
2620 else
2621 skb = receive_new(sky2, re, length);
90c30335
SH		 2622
2623 dev->stats.rx_dropped += (skb == NULL);
2624
793b883e 2625resubmit:
14d0263f 2626 sky2_rx_submit(sky2, re);
79e57d32 2627
cd28ab6a
SH		 2628 return skb;
2629
2630error:
7138a0f5 2631 ++dev->stats.rx_errors;
6e15b712 2632
6c35abae
JP		 2633 if (net_ratelimit())
2634 netif_info(sky2, rx_err, dev,
2635 "rx error, status 0x%x length %d\n", status, length);
793b883e 2636
793b883e 2637 goto resubmit;
cd28ab6a
SH		 2638}
2639
e07b1aa8
SH		 2640/* Transmit complete */
2641static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2642{
e07b1aa8 2643 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2644
8a0c9228 2645 if (netif_running(dev)) {
e07b1aa8 2646 sky2_tx_complete(sky2, last);
8a0c9228 2647
926d0977 2648 /* Wake unless it's detached, and called e.g. from sky2_close() */
8a0c9228
MM		 2649 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2650 netif_wake_queue(dev);
2651 }
cd28ab6a
SH		 2652}
2653
37e5a243 2654static inline void sky2_skb_rx(const struct sky2_port *sky2,
e072b3fa 2655 struct sk_buff *skb)
37e5a243 2656{
37e5a243
SH		 2657 if (skb->ip_summed == CHECKSUM_NONE)
2658 netif_receive_skb(skb);
2659 else
2660 napi_gro_receive(&sky2->hw->napi, skb);
2661}
2662
bf15fe99
SH		 2663static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2664 unsigned packets, unsigned bytes)
2665{
0885a30b 2666 struct net_device *dev = hw->dev[port];
2667 struct sky2_port *sky2 = netdev_priv(dev);
bf15fe99 2668
0885a30b 2669 if (packets == 0)
2670 return;
2671
2672 u64_stats_update_begin(&sky2->rx_stats.syncp);
2673 sky2->rx_stats.packets += packets;
2674 sky2->rx_stats.bytes += bytes;
2675 u64_stats_update_end(&sky2->rx_stats.syncp);
2676
2677 dev->last_rx = jiffies;
2678 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
bf15fe99
SH		 2679}
2680
375c5688 2681static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2682{
2683 /* If this happens then driver assuming wrong format for chip type */
2684 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2685
2686 /* Both checksum counters are programmed to start at
2687 * the same offset, so unless there is a problem they
2688 * should match. This failure is an early indication that
2689 * hardware receive checksumming won't work.
2690 */
2691 if (likely((u16)(status >> 16) == (u16)status)) {
2692 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2693 skb->ip_summed = CHECKSUM_COMPLETE;
2694 skb->csum = le16_to_cpu(status);
2695 } else {
2696 dev_notice(&sky2->hw->pdev->dev,
2697 "%s: receive checksum problem (status = %#x)\n",
2698 sky2->netdev->name, status);
2699
f5d64037
MM		 2700 /* Disable checksum offload
2701 * It will be reenabled on next ndo_set_features, but if it's
2702 * really broken, will get disabled again
2703 */
2704 sky2->netdev->features &= ~NETIF_F_RXCSUM;
375c5688 2705 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2706 BMU_DIS_RX_CHKSUM);
2707 }
2708}
2709
e072b3fa 2710static void sky2_rx_tag(struct sky2_port *sky2, u16 length)
2711{
2712 struct sk_buff *skb;
2713
2714 skb = sky2->rx_ring[sky2->rx_next].skb;
2715 __vlan_hwaccel_put_tag(skb, be16_to_cpu(length));
2716}
2717
bf73130d
SH		 2718static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2719{
2720 struct sk_buff *skb;
2721
2722 skb = sky2->rx_ring[sky2->rx_next].skb;
2723 skb->rxhash = le32_to_cpu(status);
2724}
2725
e07b1aa8 2726/* Process status response ring */
26691830 2727static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
cd28ab6a 2728{
e07b1aa8 2729 int work_done = 0;
bf15fe99
SH		 2730 unsigned int total_bytes[2] = { 0 };
2731 unsigned int total_packets[2] = { 0 };
a8fd6266 2732
af2a58ac 2733 rmb();
26691830 2734 do {
55c9dd35 2735 struct sky2_port *sky2;
13210ce5 2736 struct sky2_status_le *le = hw->st_le + hw->st_idx;
ab5adecb 2737 unsigned port;
13210ce5 2738 struct net_device *dev;
cd28ab6a 2739 struct sk_buff *skb;
cd28ab6a
SH		 2740 u32 status;
2741 u16 length;
ab5adecb
SH		 2742 u8 opcode = le->opcode;
2743
2744 if (!(opcode & HW_OWNER))
2745 break;
cd28ab6a 2746
efe91932 2747 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
bea86103 2748
ab5adecb 2749 port = le->css & CSS_LINK_BIT;
69161611 2750 dev = hw->dev[port];
13210ce5 2751 sky2 = netdev_priv(dev);
f65b138c
SH		 2752 length = le16_to_cpu(le->length);
2753 status = le32_to_cpu(le->status);
cd28ab6a 2754
ab5adecb
SH		 2755 le->opcode = 0;
2756 switch (opcode & ~HW_OWNER) {
cd28ab6a 2757 case OP_RXSTAT:
bf15fe99
SH		 2758 total_packets[port]++;
2759 total_bytes[port] += length;
90c30335 2760
497d7c86 2761 skb = sky2_receive(dev, length, status);
90c30335 2762 if (!skb)
55c9dd35 2763 break;
13210ce5 2764
69161611 2765 /* This chip reports checksum status differently */
05745c4a 2766 if (hw->flags & SKY2_HW_NEW_LE) {
f5d64037 2767 if ((dev->features & NETIF_F_RXCSUM) &&
69161611
SH		 2768 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2769 (le->css & CSS_TCPUDPCSOK))
2770 skb->ip_summed = CHECKSUM_UNNECESSARY;
2771 else
2772 skb->ip_summed = CHECKSUM_NONE;
2773 }
2774
13210ce5 2775 skb->protocol = eth_type_trans(skb, dev);
e072b3fa 2776 sky2_skb_rx(sky2, skb);
13210ce5 2777
22e11703 2778 /* Stop after net poll weight */
13210ce5 2779 if (++work_done >= to_do)
2780 goto exit_loop;
cd28ab6a
SH		 2781 break;
2782
d1f13708 2783 case OP_RXVLAN:
e072b3fa 2784 sky2_rx_tag(sky2, length);
d1f13708 2785 break;
2786
2787 case OP_RXCHKSVLAN:
e072b3fa 2788 sky2_rx_tag(sky2, length);
d1f13708 2789 /* fall through */
cd28ab6a 2790 case OP_RXCHKS:
f5d64037 2791 if (likely(dev->features & NETIF_F_RXCSUM))
375c5688 2792 sky2_rx_checksum(sky2, status);
cd28ab6a
SH		 2793 break;
2794
bf73130d
SH		 2795 case OP_RSS_HASH:
2796 sky2_rx_hash(sky2, status);
2797 break;
2798
cd28ab6a 2799 case OP_TXINDEXLE:
13b97b74 2800 /* TX index reports status for both ports */
f55925d7 2801 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2802 if (hw->dev[1])
2803 sky2_tx_done(hw->dev[1],
2804 ((status >> 24) & 0xff)
2805 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2806 break;
2807
cd28ab6a
SH		 2808 default:
2809 if (net_ratelimit())
ada1db5c 2810 pr_warning("unknown status opcode 0x%x\n", opcode);
cd28ab6a 2811 }
26691830 2812 } while (hw->st_idx != idx);
cd28ab6a 2813
fe2a24df
SH		 2814 /* Fully processed status ring so clear irq */
2815 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2816
13210ce5 2817exit_loop:
bf15fe99
SH		 2818 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2819 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
22e11703 2820
e07b1aa8 2821 return work_done;
cd28ab6a
SH		 2822}
2823
2824static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2825{
2826 struct net_device *dev = hw->dev[port];
2827
3be92a70 2828 if (net_ratelimit())
ada1db5c 2829 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
cd28ab6a
SH		 2830
2831 if (status & Y2_IS_PAR_RD1) {
3be92a70 2832 if (net_ratelimit())
ada1db5c 2833 netdev_err(dev, "ram data read parity error\n");
cd28ab6a
SH		 2834 /* Clear IRQ */
2835 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2836 }
2837
2838 if (status & Y2_IS_PAR_WR1) {
3be92a70 2839 if (net_ratelimit())
ada1db5c 2840 netdev_err(dev, "ram data write parity error\n");
cd28ab6a
SH		 2841
2842 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2843 }
2844
2845 if (status & Y2_IS_PAR_MAC1) {
3be92a70 2846 if (net_ratelimit())
ada1db5c 2847 netdev_err(dev, "MAC parity error\n");
cd28ab6a
SH		 2848 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2849 }
2850
2851 if (status & Y2_IS_PAR_RX1) {
3be92a70 2852 if (net_ratelimit())
ada1db5c 2853 netdev_err(dev, "RX parity error\n");
cd28ab6a
SH		 2854 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2855 }
2856
2857 if (status & Y2_IS_TCP_TXA1) {
3be92a70 2858 if (net_ratelimit())
ada1db5c 2859 netdev_err(dev, "TCP segmentation error\n");
cd28ab6a
SH		 2860 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2861 }
2862}
2863
2864static void sky2_hw_intr(struct sky2_hw *hw)
2865{
555382cb 2866 struct pci_dev *pdev = hw->pdev;
cd28ab6a 2867 u32 status = sky2_read32(hw, B0_HWE_ISRC);
555382cb
SH		 2868 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2869
2870 status &= hwmsk;
cd28ab6a 2871
793b883e 2872 if (status & Y2_IS_TIST_OV)
cd28ab6a 2873 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2874
2875 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2876 u16 pci_err;
2877
a40ccc68 2878 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
b32f40c4 2879 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2880 if (net_ratelimit())
555382cb 2881 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
b02a9258 2882 pci_err);
cd28ab6a 2883
b32f40c4 2884 sky2_pci_write16(hw, PCI_STATUS,
167f53d0 2885 pci_err | PCI_STATUS_ERROR_BITS);
a40ccc68 2886 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2887 }
2888
2889 if (status & Y2_IS_PCI_EXP) {
d571b694 2890 /* PCI-Express uncorrectable Error occurred */
555382cb 2891 u32 err;
cd28ab6a 2892
a40ccc68 2893 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7782c8c4
SH		 2894 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2895 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2896 0xfffffffful);
3be92a70 2897 if (net_ratelimit())
555382cb 2898 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
cf06ffb4 2899
7782c8c4 2900 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
a40ccc68 2901 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 2902 }
2903
2904 if (status & Y2_HWE_L1_MASK)
2905 sky2_hw_error(hw, 0, status);
2906 status >>= 8;
2907 if (status & Y2_HWE_L1_MASK)
2908 sky2_hw_error(hw, 1, status);
2909}
2910
2911static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2912{
2913 struct net_device *dev = hw->dev[port];
2914 struct sky2_port *sky2 = netdev_priv(dev);
2915 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2916
6c35abae 2917 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
cd28ab6a 2918
a3caeada
SH		 2919 if (status & GM_IS_RX_CO_OV)
2920 gma_read16(hw, port, GM_RX_IRQ_SRC);
2921
2922 if (status & GM_IS_TX_CO_OV)
2923 gma_read16(hw, port, GM_TX_IRQ_SRC);
2924
cd28ab6a 2925 if (status & GM_IS_RX_FF_OR) {
7138a0f5 2926 ++dev->stats.rx_fifo_errors;
cd28ab6a
SH		 2927 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2928 }
2929
2930 if (status & GM_IS_TX_FF_UR) {
7138a0f5 2931 ++dev->stats.tx_fifo_errors;
cd28ab6a
SH		 2932 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2933 }
cd28ab6a
SH		 2934}
2935
40b01727 2936/* This should never happen it is a bug. */
c119731d 2937static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
d257924e
SH		 2938{
2939 struct net_device *dev = hw->dev[port];
c119731d 2940 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
d257924e 2941
ada1db5c 2942 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
c119731d
SH		 2943 dev->name, (unsigned) q, (unsigned) idx,
2944 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
d257924e 2945
40b01727 2946 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
d257924e 2947}
cd28ab6a 2948
75e80683
SH		 2949static int sky2_rx_hung(struct net_device *dev)
2950{
2951 struct sky2_port *sky2 = netdev_priv(dev);
2952 struct sky2_hw *hw = sky2->hw;
2953 unsigned port = sky2->port;
2954 unsigned rxq = rxqaddr[port];
2955 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2956 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2957 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2958 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2959
2960 /* If idle and MAC or PCI is stuck */
2961 if (sky2->check.last == dev->last_rx &&
2962 ((mac_rp == sky2->check.mac_rp &&
2963 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2964 /* Check if the PCI RX hang */
2965 (fifo_rp == sky2->check.fifo_rp &&
2966 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
ada1db5c
JP		 2967 netdev_printk(KERN_DEBUG, dev,
2968 "hung mac %d:%d fifo %d (%d:%d)\n",
2969 mac_lev, mac_rp, fifo_lev,
2970 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
75e80683
SH		 2971 return 1;
2972 } else {
2973 sky2->check.last = dev->last_rx;
2974 sky2->check.mac_rp = mac_rp;
2975 sky2->check.mac_lev = mac_lev;
2976 sky2->check.fifo_rp = fifo_rp;
2977 sky2->check.fifo_lev = fifo_lev;
2978 return 0;
2979 }
2980}
2981
32c2c300 2982static void sky2_watchdog(unsigned long arg)
d27ed387 2983{
01bd7564 2984 struct sky2_hw *hw = (struct sky2_hw *) arg;
d27ed387 2985
75e80683 2986 /* Check for lost IRQ once a second */
32c2c300 2987 if (sky2_read32(hw, B0_ISRC)) {
bea3348e 2988 napi_schedule(&hw->napi);
75e80683
SH		 2989 } else {
2990 int i, active = 0;
2991
2992 for (i = 0; i < hw->ports; i++) {
bea3348e 2993 struct net_device *dev = hw->dev[i];
75e80683
SH		 2994 if (!netif_running(dev))
2995 continue;
2996 ++active;
2997
2998 /* For chips with Rx FIFO, check if stuck */
39dbd958 2999 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
75e80683 3000 sky2_rx_hung(dev)) {
ada1db5c 3001 netdev_info(dev, "receiver hang detected\n");
75e80683
SH		 3002 schedule_work(&hw->restart_work);
3003 return;
3004 }
3005 }
3006
3007 if (active == 0)
3008 return;
32c2c300 3009 }
01bd7564 3010
75e80683 3011 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
d27ed387
SH		 3012}
3013
40b01727
SH		 3014/* Hardware/software error handling */
3015static void sky2_err_intr(struct sky2_hw *hw, u32 status)
cd28ab6a 3016{
40b01727
SH		 3017 if (net_ratelimit())
3018 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
cd28ab6a 3019
1e5f1283
SH		 3020 if (status & Y2_IS_HW_ERR)
3021 sky2_hw_intr(hw);
d257924e 3022
1e5f1283
SH		 3023 if (status & Y2_IS_IRQ_MAC1)
3024 sky2_mac_intr(hw, 0);
cd28ab6a 3025
1e5f1283
SH		 3026 if (status & Y2_IS_IRQ_MAC2)
3027 sky2_mac_intr(hw, 1);
cd28ab6a 3028
1e5f1283 3029 if (status & Y2_IS_CHK_RX1)
c119731d 3030 sky2_le_error(hw, 0, Q_R1);
d257924e 3031
1e5f1283 3032 if (status & Y2_IS_CHK_RX2)
c119731d 3033 sky2_le_error(hw, 1, Q_R2);
d257924e 3034
1e5f1283 3035 if (status & Y2_IS_CHK_TXA1)
c119731d 3036 sky2_le_error(hw, 0, Q_XA1);
d257924e 3037
1e5f1283 3038 if (status & Y2_IS_CHK_TXA2)
c119731d 3039 sky2_le_error(hw, 1, Q_XA2);
40b01727
SH		 3040}
3041
bea3348e 3042static int sky2_poll(struct napi_struct *napi, int work_limit)
40b01727 3043{
bea3348e 3044 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
40b01727 3045 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
6f535763 3046 int work_done = 0;
26691830 3047 u16 idx;
40b01727
SH		 3048
3049 if (unlikely(status & Y2_IS_ERROR))
3050 sky2_err_intr(hw, status);
3051
3052 if (status & Y2_IS_IRQ_PHY1)
3053 sky2_phy_intr(hw, 0);
3054
3055 if (status & Y2_IS_IRQ_PHY2)
3056 sky2_phy_intr(hw, 1);
cd28ab6a 3057
0f5aac70
SH		 3058 if (status & Y2_IS_PHY_QLNK)
3059 sky2_qlink_intr(hw);
3060
26691830
SH		 3061 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
3062 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
6f535763
DM		 3063
3064 if (work_done >= work_limit)
26691830
SH		 3065 goto done;
3066 }
6f535763 3067
26691830
SH		 3068 napi_complete(napi);
3069 sky2_read32(hw, B0_Y2_SP_LISR);
3070done:
6f535763 3071
bea3348e 3072 return work_done;
e07b1aa8
SH		 3073}
3074
7d12e780 3075static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 3076{
3077 struct sky2_hw *hw = dev_id;
e07b1aa8
SH		 3078 u32 status;
3079
3080 /* Reading this mask interrupts as side effect */
3081 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3082 if (status == 0 || status == ~0)
3083 return IRQ_NONE;
793b883e 3084
e07b1aa8 3085 prefetch(&hw->st_le[hw->st_idx]);
bea3348e
SH		 3086
3087 napi_schedule(&hw->napi);
793b883e 3088
cd28ab6a
SH		 3089 return IRQ_HANDLED;
3090}
3091
3092#ifdef CONFIG_NET_POLL_CONTROLLER
3093static void sky2_netpoll(struct net_device *dev)
3094{
3095 struct sky2_port *sky2 = netdev_priv(dev);
3096
bea3348e 3097 napi_schedule(&sky2->hw->napi);
cd28ab6a
SH		 3098}
3099#endif
3100
3101/* Chip internal frequency for clock calculations */
05745c4a 3102static u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 3103{
793b883e 3104 switch (hw->chip_id) {
cd28ab6a 3105 case CHIP_ID_YUKON_EC:
5a5b1ea0 3106 case CHIP_ID_YUKON_EC_U:
93745494 3107 case CHIP_ID_YUKON_EX:
ed4d4161 3108 case CHIP_ID_YUKON_SUPR:
0ce8b98d 3109 case CHIP_ID_YUKON_UL_2:
0f5aac70 3110 case CHIP_ID_YUKON_OPT:
4fb99cd6 3111 case CHIP_ID_YUKON_PRM:
3112 case CHIP_ID_YUKON_OP_2:
05745c4a
SH		 3113 return 125;
3114
cd28ab6a 3115 case CHIP_ID_YUKON_FE:
05745c4a
SH		 3116 return 100;
3117
3118 case CHIP_ID_YUKON_FE_P:
3119 return 50;
3120
3121 case CHIP_ID_YUKON_XL:
3122 return 156;
3123
3124 default:
3125 BUG();
cd28ab6a
SH		 3126 }
3127}
3128
fb17358f 3129static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 3130{
fb17358f 3131 return sky2_mhz(hw) * us;
cd28ab6a
SH		 3132}
3133
fb17358f 3134static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 3135{
fb17358f 3136 return clk / sky2_mhz(hw);
cd28ab6a
SH		 3137}
3138
fb17358f 3139
e3173832 3140static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 3141{
b89165f2 3142 u8 t8;
cd28ab6a 3143
167f53d0 3144 /* Enable all clocks and check for bad PCI access */
b32f40c4 3145 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
451af335 3146
cd28ab6a 3147 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 3148
cd28ab6a 3149 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
ea76e635
SH		 3150 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3151
060b946c 3152 switch (hw->chip_id) {
ea76e635 3153 case CHIP_ID_YUKON_XL:
39dbd958 3154 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
bf73130d
SH		 3155 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3156 hw->flags |= SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3157 break;
3158
3159 case CHIP_ID_YUKON_EC_U:
3160 hw->flags = SKY2_HW_GIGABIT
3161 | SKY2_HW_NEWER_PHY
3162 | SKY2_HW_ADV_POWER_CTL;
3163 break;
3164
3165 case CHIP_ID_YUKON_EX:
3166 hw->flags = SKY2_HW_GIGABIT
3167 | SKY2_HW_NEWER_PHY
3168 | SKY2_HW_NEW_LE
aa5ca96c 3169 | SKY2_HW_ADV_POWER_CTL
3170 | SKY2_HW_RSS_CHKSUM;
ea76e635
SH		 3171
3172 /* New transmit checksum */
3173 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3174 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3175 break;
3176
3177 case CHIP_ID_YUKON_EC:
3178 /* This rev is really old, and requires untested workarounds */
3179 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3180 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3181 return -EOPNOTSUPP;
3182 }
bf73130d 3183 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3184 break;
3185
3186 case CHIP_ID_YUKON_FE:
bf73130d 3187 hw->flags = SKY2_HW_RSS_BROKEN;
ea76e635
SH		 3188 break;
3189
05745c4a
SH		 3190 case CHIP_ID_YUKON_FE_P:
3191 hw->flags = SKY2_HW_NEWER_PHY
3192 | SKY2_HW_NEW_LE
3193 | SKY2_HW_AUTO_TX_SUM
3194 | SKY2_HW_ADV_POWER_CTL;
86aa7785
SH		 3195
3196 /* The workaround for status conflicts VLAN tag detection. */
3197 if (hw->chip_rev == CHIP_REV_YU_FE2_A0)
aa5ca96c 3198 hw->flags |= SKY2_HW_VLAN_BROKEN | SKY2_HW_RSS_CHKSUM;
05745c4a 3199 break;
ed4d4161
SH		 3200
3201 case CHIP_ID_YUKON_SUPR:
3202 hw->flags = SKY2_HW_GIGABIT
3203 | SKY2_HW_NEWER_PHY
3204 | SKY2_HW_NEW_LE
3205 | SKY2_HW_AUTO_TX_SUM
3206 | SKY2_HW_ADV_POWER_CTL;
aa5ca96c 3207
3208 if (hw->chip_rev == CHIP_REV_YU_SU_A0)
3209 hw->flags |= SKY2_HW_RSS_CHKSUM;
ed4d4161
SH		 3210 break;
3211
0ce8b98d 3212 case CHIP_ID_YUKON_UL_2:
b338682d
TI		 3213 hw->flags = SKY2_HW_GIGABIT
3214 | SKY2_HW_ADV_POWER_CTL;
3215 break;
3216
0f5aac70 3217 case CHIP_ID_YUKON_OPT:
4fb99cd6 3218 case CHIP_ID_YUKON_PRM:
3219 case CHIP_ID_YUKON_OP_2:
0ce8b98d 3220 hw->flags = SKY2_HW_GIGABIT
b338682d 3221 | SKY2_HW_NEW_LE
0ce8b98d
SH		 3222 | SKY2_HW_ADV_POWER_CTL;
3223 break;
3224
ea76e635 3225 default:
b02a9258
SH		 3226 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3227 hw->chip_id);
cd28ab6a
SH		 3228 return -EOPNOTSUPP;
3229 }
3230
ea76e635
SH		 3231 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3232 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3233 hw->flags |= SKY2_HW_FIBRE_PHY;
290d4de5 3234
e3173832
SH		 3235 hw->ports = 1;
3236 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3237 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3238 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3239 ++hw->ports;
3240 }
3241
74a61ebf
MM		 3242 if (sky2_read8(hw, B2_E_0))
3243 hw->flags |= SKY2_HW_RAM_BUFFER;
3244
e3173832
SH		 3245 return 0;
3246}
3247
3248static void sky2_reset(struct sky2_hw *hw)
3249{
555382cb 3250 struct pci_dev *pdev = hw->pdev;
e3173832 3251 u16 status;
1a10ccae 3252 int i;
555382cb 3253 u32 hwe_mask = Y2_HWE_ALL_MASK;
e3173832 3254
cd28ab6a 3255 /* disable ASF */
acd12dde 3256 if (hw->chip_id == CHIP_ID_YUKON_EX
3257 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3258 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3259 status = sky2_read16(hw, HCU_CCSR);
3260 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3261 HCU_CCSR_UC_STATE_MSK);
acd12dde 3262 /*
3263 * CPU clock divider shouldn't be used because
3264 * - ASF firmware may malfunction
3265 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3266 */
3267 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
4f44d8ba 3268 sky2_write16(hw, HCU_CCSR, status);
acd12dde 3269 sky2_write32(hw, CPU_WDOG, 0);
4f44d8ba
SH		 3270 } else
3271 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3272 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
cd28ab6a
SH		 3273
3274 /* do a SW reset */
3275 sky2_write8(hw, B0_CTST, CS_RST_SET);
3276 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3277
ac93a394
SH		 3278 /* allow writes to PCI config */
3279 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3280
cd28ab6a 3281 /* clear PCI errors, if any */
b32f40c4 3282 status = sky2_pci_read16(hw, PCI_STATUS);
167f53d0 3283 status |= PCI_STATUS_ERROR_BITS;
b32f40c4 3284 sky2_pci_write16(hw, PCI_STATUS, status);
cd28ab6a
SH		 3285
3286 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3287
1a10ccae 3288 if (pci_is_pcie(pdev)) {
7782c8c4
SH		 3289 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3290 0xfffffffful);
555382cb
SH		 3291
3292 /* If error bit is stuck on ignore it */
3293 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3294 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
7782c8c4 3295 else
555382cb
SH		 3296 hwe_mask |= Y2_IS_PCI_EXP;
3297 }
cd28ab6a 3298
ae306cca 3299 sky2_power_on(hw);
a40ccc68 3300 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
cd28ab6a
SH		 3301
3302 for (i = 0; i < hw->ports; i++) {
3303 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3304 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
69161611 3305
ed4d4161
SH		 3306 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3307 hw->chip_id == CHIP_ID_YUKON_SUPR)
69161611
SH		 3308 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3309 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3310 | GMC_BYP_RETR_ON);
877c8570
SH		 3311
3312 }
3313
3314 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3315 /* enable MACSec clock gating */
3316 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
cd28ab6a
SH		 3317 }
3318
4fb99cd6 3319 if (hw->chip_id == CHIP_ID_YUKON_OPT ||
3320 hw->chip_id == CHIP_ID_YUKON_PRM ||
3321 hw->chip_id == CHIP_ID_YUKON_OP_2) {
0f5aac70 3322 u16 reg;
0f5aac70 3323
4fb99cd6 3324 if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
0f5aac70
SH		 3325 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3326 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3327
3328 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3329 reg = 10;
4fb99cd6 3330
3331 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3332 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
0f5aac70
SH		 3333 } else {
3334 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3335 reg = 3;
3336 }
3337
3338 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
4fb99cd6 3339 reg |= PSM_CONFIG_REG4_RST_PHY_LINK_DETECT;
0f5aac70
SH		 3340
3341 /* reset PHY Link Detect */
a40ccc68 3342 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
0f5aac70
SH		 3343 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3344
0f5aac70
SH		 3345 /* check if PSMv2 was running before */
3346 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
1a10ccae 3347 if (reg & PCI_EXP_LNKCTL_ASPMC)
0f5aac70 3348 /* restore the PCIe Link Control register */
1a10ccae
JM		 3349 sky2_pci_write16(hw, pdev->pcie_cap + PCI_EXP_LNKCTL,
3350 reg);
3351
a40ccc68 3352 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
0f5aac70
SH		 3353
3354 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3355 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3356 }
3357
793b883e
SH		 3358 /* Clear I2C IRQ noise */
3359 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 3360
3361 /* turn off hardware timer (unused) */
3362 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3363 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 3364
69634ee7
SH		 3365 /* Turn off descriptor polling */
3366 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 3367
3368 /* Turn off receive timestamp */
3369 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 3370 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 3371
3372 /* enable the Tx Arbiters */
3373 for (i = 0; i < hw->ports; i++)
3374 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3375
3376 /* Initialize ram interface */
3377 for (i = 0; i < hw->ports; i++) {
793b883e 3378 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 3379
3380 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3381 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3382 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3383 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3384 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3385 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3386 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3387 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3388 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3389 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3390 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3391 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3392 }
3393
555382cb 3394 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
cd28ab6a 3395
cd28ab6a 3396 for (i = 0; i < hw->ports; i++)
d3bcfbeb 3397 sky2_gmac_reset(hw, i);
cd28ab6a 3398
efe91932 3399 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
cd28ab6a
SH		 3400 hw->st_idx = 0;
3401
3402 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3403 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3404
3405 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 3406 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 3407
3408 /* Set the list last index */
efe91932 3409 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
cd28ab6a 3410
290d4de5
SH		 3411 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3412 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 3413
290d4de5
SH		 3414 /* set Status-FIFO ISR watermark */
3415 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3416 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3417 else
3418 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 3419
290d4de5 3420 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 3421 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3422 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 3423
793b883e 3424 /* enable status unit */
cd28ab6a
SH		 3425 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3426
3427 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3428 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3429 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 3430}
3431
af18d8b8
SH		 3432/* Take device down (offline).
3433 * Equivalent to doing dev_stop() but this does not
25985edc 3434 * inform upper layers of the transition.
af18d8b8
SH		 3435 */
3436static void sky2_detach(struct net_device *dev)
3437{
3438 if (netif_running(dev)) {
c36531b9 3439 netif_tx_lock(dev);
af18d8b8 3440 netif_device_detach(dev); /* stop txq */
c36531b9 3441 netif_tx_unlock(dev);
926d0977 3442 sky2_close(dev);
af18d8b8
SH		 3443 }
3444}
3445
3446/* Bring device back after doing sky2_detach */
3447static int sky2_reattach(struct net_device *dev)
3448{
3449 int err = 0;
3450
3451 if (netif_running(dev)) {
926d0977 3452 err = sky2_open(dev);
af18d8b8 3453 if (err) {
ada1db5c 3454 netdev_info(dev, "could not restart %d\n", err);
af18d8b8
SH		 3455 dev_close(dev);
3456 } else {
3457 netif_device_attach(dev);
3458 sky2_set_multicast(dev);
3459 }
3460 }
3461
3462 return err;
3463}
3464
d72ff8fa 3465static void sky2_all_down(struct sky2_hw *hw)
81906791 3466{
af18d8b8 3467 int i;
81906791 3468
282edcec 3469 if (hw->flags & SKY2_HW_IRQ_SETUP) {
3470 sky2_read32(hw, B0_IMSK);
3471 sky2_write32(hw, B0_IMSK, 0);
1401a800 3472
1401a800 3473 synchronize_irq(hw->pdev->irq);
282edcec 3474 napi_disable(&hw->napi);
3475 }
8a0c9228
MM		 3476
3477 for (i = 0; i < hw->ports; i++) {
3478 struct net_device *dev = hw->dev[i];
3479 struct sky2_port *sky2 = netdev_priv(dev);
3480
3481 if (!netif_running(dev))
3482 continue;
3483
3484 netif_carrier_off(dev);
3485 netif_tx_disable(dev);
3486 sky2_hw_down(sky2);
3487 }
d72ff8fa 3488}
8a0c9228 3489
d72ff8fa
MM		 3490static void sky2_all_up(struct sky2_hw *hw)
3491{
3492 u32 imask = Y2_IS_BASE;
3493 int i;
81906791 3494
8a0c9228
MM		 3495 for (i = 0; i < hw->ports; i++) {
3496 struct net_device *dev = hw->dev[i];
3497 struct sky2_port *sky2 = netdev_priv(dev);
3498
3499 if (!netif_running(dev))
3500 continue;
3501
3502 sky2_hw_up(sky2);
37652522 3503 sky2_set_multicast(dev);
d72ff8fa 3504 imask |= portirq_msk[i];
8a0c9228
MM		 3505 netif_wake_queue(dev);
3506 }
3507
282edcec 3508 if (hw->flags & SKY2_HW_IRQ_SETUP) {
1401a800 3509 sky2_write32(hw, B0_IMSK, imask);
3510 sky2_read32(hw, B0_IMSK);
3511 sky2_read32(hw, B0_Y2_SP_LISR);
3512 napi_enable(&hw->napi);
3513 }
d72ff8fa
MM		 3514}
3515
3516static void sky2_restart(struct work_struct *work)
3517{
3518 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3519
3520 rtnl_lock();
3521
3522 sky2_all_down(hw);
3523 sky2_reset(hw);
3524 sky2_all_up(hw);
81906791 3525
81906791
SH		 3526 rtnl_unlock();
3527}
3528
e3173832
SH		 3529static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3530{
3531 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3532}
3533
3534static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3535{
3536 const struct sky2_port *sky2 = netdev_priv(dev);
3537
3538 wol->supported = sky2_wol_supported(sky2->hw);
3539 wol->wolopts = sky2->wol;
3540}
3541
3542static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3543{
3544 struct sky2_port *sky2 = netdev_priv(dev);
3545 struct sky2_hw *hw = sky2->hw;
0f333d10
RW		 3546 bool enable_wakeup = false;
3547 int i;
cd28ab6a 3548
8e95a202
JP		 3549 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3550 !device_can_wakeup(&hw->pdev->dev))
e3173832
SH		 3551 return -EOPNOTSUPP;
3552
3553 sky2->wol = wol->wolopts;
0f333d10
RW		 3554
3555 for (i = 0; i < hw->ports; i++) {
3556 struct net_device *dev = hw->dev[i];
3557 struct sky2_port *sky2 = netdev_priv(dev);
3558
3559 if (sky2->wol)
3560 enable_wakeup = true;
3561 }
3562 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3563
cd28ab6a
SH		 3564 return 0;
3565}
3566
28bd181a 3567static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 3568{
b89165f2
SH		 3569 if (sky2_is_copper(hw)) {
3570 u32 modes = SUPPORTED_10baseT_Half
3571 | SUPPORTED_10baseT_Full
3572 | SUPPORTED_100baseT_Half
2aca31e7 3573 | SUPPORTED_100baseT_Full;
cd28ab6a 3574
ea76e635 3575 if (hw->flags & SKY2_HW_GIGABIT)
cd28ab6a 3576 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 3577 | SUPPORTED_1000baseT_Full;
3578 return modes;
cd28ab6a 3579 } else
2aca31e7
SH		 3580 return SUPPORTED_1000baseT_Half
3581 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 3582}
3583
793b883e 3584static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 3585{
3586 struct sky2_port *sky2 = netdev_priv(dev);
3587 struct sky2_hw *hw = sky2->hw;
3588
3589 ecmd->transceiver = XCVR_INTERNAL;
3590 ecmd->supported = sky2_supported_modes(hw);
3591 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 3592 if (sky2_is_copper(hw)) {
cd28ab6a 3593 ecmd->port = PORT_TP;
70739497 3594 ethtool_cmd_speed_set(ecmd, sky2->speed);
2aca31e7 3595 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_TP;
b89165f2 3596 } else {
70739497 3597 ethtool_cmd_speed_set(ecmd, SPEED_1000);
cd28ab6a 3598 ecmd->port = PORT_FIBRE;
2aca31e7 3599 ecmd->supported |= SUPPORTED_Autoneg | SUPPORTED_FIBRE;
b89165f2 3600 }
cd28ab6a
SH		 3601
3602 ecmd->advertising = sky2->advertising;
0ea065e5
SH		 3603 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3604 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 3605 ecmd->duplex = sky2->duplex;
3606 return 0;
3607}
3608
3609static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3610{
3611 struct sky2_port *sky2 = netdev_priv(dev);
3612 const struct sky2_hw *hw = sky2->hw;
3613 u32 supported = sky2_supported_modes(hw);
3614
3615 if (ecmd->autoneg == AUTONEG_ENABLE) {
2aca31e7
SH		 3616 if (ecmd->advertising & ~supported)
3617 return -EINVAL;
3618
3619 if (sky2_is_copper(hw))
3620 sky2->advertising = ecmd->advertising |
3621 ADVERTISED_TP |
3622 ADVERTISED_Autoneg;
3623 else
3624 sky2->advertising = ecmd->advertising |
3625 ADVERTISED_FIBRE |
3626 ADVERTISED_Autoneg;
3627
0ea065e5 3628 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3629 sky2->duplex = -1;
3630 sky2->speed = -1;
3631 } else {
3632 u32 setting;
25db0338 3633 u32 speed = ethtool_cmd_speed(ecmd);
cd28ab6a 3634
25db0338 3635 switch (speed) {
cd28ab6a
SH		 3636 case SPEED_1000:
3637 if (ecmd->duplex == DUPLEX_FULL)
3638 setting = SUPPORTED_1000baseT_Full;
3639 else if (ecmd->duplex == DUPLEX_HALF)
3640 setting = SUPPORTED_1000baseT_Half;
3641 else
3642 return -EINVAL;
3643 break;
3644 case SPEED_100:
3645 if (ecmd->duplex == DUPLEX_FULL)
3646 setting = SUPPORTED_100baseT_Full;
3647 else if (ecmd->duplex == DUPLEX_HALF)
3648 setting = SUPPORTED_100baseT_Half;
3649 else
3650 return -EINVAL;
3651 break;
3652
3653 case SPEED_10:
3654 if (ecmd->duplex == DUPLEX_FULL)
3655 setting = SUPPORTED_10baseT_Full;
3656 else if (ecmd->duplex == DUPLEX_HALF)
3657 setting = SUPPORTED_10baseT_Half;
3658 else
3659 return -EINVAL;
3660 break;
3661 default:
3662 return -EINVAL;
3663 }
3664
3665 if ((setting & supported) == 0)
3666 return -EINVAL;
3667
25db0338 3668 sky2->speed = speed;
cd28ab6a 3669 sky2->duplex = ecmd->duplex;
0ea065e5 3670 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
cd28ab6a
SH		 3671 }
3672
d1b139c0 3673 if (netif_running(dev)) {
1b537565 3674 sky2_phy_reinit(sky2);
d1b139c0
SH		 3675 sky2_set_multicast(dev);
3676 }
cd28ab6a
SH		 3677
3678 return 0;
3679}
3680
3681static void sky2_get_drvinfo(struct net_device *dev,
3682 struct ethtool_drvinfo *info)
3683{
3684 struct sky2_port *sky2 = netdev_priv(dev);
3685
68aad78c
RJ		 3686 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
3687 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
68aad78c
RJ		 3688 strlcpy(info->bus_info, pci_name(sky2->hw->pdev),
3689 sizeof(info->bus_info));
cd28ab6a
SH		 3690}
3691
3692static const struct sky2_stat {
793b883e
SH		 3693 char name[ETH_GSTRING_LEN];
3694 u16 offset;
cd28ab6a
SH		 3695} sky2_stats[] = {
3696 { "tx_bytes", GM_TXO_OK_HI },
3697 { "rx_bytes", GM_RXO_OK_HI },
3698 { "tx_broadcast", GM_TXF_BC_OK },
3699 { "rx_broadcast", GM_RXF_BC_OK },
3700 { "tx_multicast", GM_TXF_MC_OK },
3701 { "rx_multicast", GM_RXF_MC_OK },
3702 { "tx_unicast", GM_TXF_UC_OK },
3703 { "rx_unicast", GM_RXF_UC_OK },
3704 { "tx_mac_pause", GM_TXF_MPAUSE },
3705 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 3706 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 3707 { "late_collision",GM_TXF_LAT_COL },
3708 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 3709 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 3710 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 3711
d2604540 3712 { "rx_short", GM_RXF_SHT },
cd28ab6a 3713 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 3714 { "rx_64_byte_packets", GM_RXF_64B },
3715 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3716 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3717 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3718 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3719 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3720 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 3721 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 3722 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3723 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 3724 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 3725
3726 { "tx_64_byte_packets", GM_TXF_64B },
3727 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3728 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3729 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3730 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3731 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3732 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3733 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 3734};
3735
cd28ab6a
SH		 3736static u32 sky2_get_msglevel(struct net_device *netdev)
3737{
3738 struct sky2_port *sky2 = netdev_priv(netdev);
3739 return sky2->msg_enable;
3740}
3741
9a7ae0a9
SH		 3742static int sky2_nway_reset(struct net_device *dev)
3743{
3744 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 3745
0ea065e5 3746 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
9a7ae0a9
SH		 3747 return -EINVAL;
3748
1b537565 3749 sky2_phy_reinit(sky2);
d1b139c0 3750 sky2_set_multicast(dev);
9a7ae0a9
SH		 3751
3752 return 0;
3753}
3754
793b883e 3755static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 3756{
3757 struct sky2_hw *hw = sky2->hw;
3758 unsigned port = sky2->port;
3759 int i;
3760
0885a30b 3761 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3762 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
cd28ab6a 3763
793b883e 3764 for (i = 2; i < count; i++)
0885a30b 3765 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
cd28ab6a
SH		 3766}
3767
cd28ab6a
SH		 3768static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3769{
3770 struct sky2_port *sky2 = netdev_priv(netdev);
3771 sky2->msg_enable = value;
3772}
3773
b9f2c044 3774static int sky2_get_sset_count(struct net_device *dev, int sset)
cd28ab6a 3775{
b9f2c044
JG		 3776 switch (sset) {
3777 case ETH_SS_STATS:
3778 return ARRAY_SIZE(sky2_stats);
3779 default:
3780 return -EOPNOTSUPP;
3781 }
cd28ab6a
SH		 3782}
3783
3784static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 3785 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 3786{
3787 struct sky2_port *sky2 = netdev_priv(dev);
3788
793b883e 3789 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 3790}
3791
793b883e 3792static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 3793{
3794 int i;
3795
3796 switch (stringset) {
3797 case ETH_SS_STATS:
3798 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3799 memcpy(data + i * ETH_GSTRING_LEN,
3800 sky2_stats[i].name, ETH_GSTRING_LEN);
3801 break;
3802 }
3803}
3804
cd28ab6a
SH		 3805static int sky2_set_mac_address(struct net_device *dev, void *p)
3806{
3807 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 3808 struct sky2_hw *hw = sky2->hw;
3809 unsigned port = sky2->port;
3810 const struct sockaddr *addr = p;
cd28ab6a
SH		 3811
3812 if (!is_valid_ether_addr(addr->sa_data))
3813 return -EADDRNOTAVAIL;
3814
cd28ab6a 3815 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 3816 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 3817 dev->dev_addr, ETH_ALEN);
a8ab1ec0 3818 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 3819 dev->dev_addr, ETH_ALEN);
1b537565 3820
a8ab1ec0
SH		 3821 /* virtual address for data */
3822 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3823
3824 /* physical address: used for pause frames */
3825 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3826
3827 return 0;
cd28ab6a
SH		 3828}
3829
060b946c 3830static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
a052b52f
SH		 3831{
3832 u32 bit;
3833
3834 bit = ether_crc(ETH_ALEN, addr) & 63;
3835 filter[bit >> 3] |= 1 << (bit & 7);
3836}
3837
cd28ab6a
SH		 3838static void sky2_set_multicast(struct net_device *dev)
3839{
3840 struct sky2_port *sky2 = netdev_priv(dev);
3841 struct sky2_hw *hw = sky2->hw;
3842 unsigned port = sky2->port;
22bedad3 3843 struct netdev_hw_addr *ha;
cd28ab6a
SH		 3844 u16 reg;
3845 u8 filter[8];
a052b52f
SH		 3846 int rx_pause;
3847 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3848
a052b52f 3849 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3850 memset(filter, 0, sizeof(filter));
3851
3852 reg = gma_read16(hw, port, GM_RX_CTRL);
3853 reg |= GM_RXCR_UCF_ENA;
3854
d571b694 3855 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3856 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3857 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3858 memset(filter, 0xff, sizeof(filter));
4cd24eaf 3859 else if (netdev_mc_empty(dev) && !rx_pause)
cd28ab6a
SH		 3860 reg &= ~GM_RXCR_MCF_ENA;
3861 else {
cd28ab6a
SH		 3862 reg |= GM_RXCR_MCF_ENA;
3863
a052b52f
SH		 3864 if (rx_pause)
3865 sky2_add_filter(filter, pause_mc_addr);
3866
22bedad3
JP		 3867 netdev_for_each_mc_addr(ha, dev)
3868 sky2_add_filter(filter, ha->addr);
cd28ab6a
SH		 3869 }
3870
cd28ab6a 3871 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3872 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3873 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3874 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3875 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3876 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3877 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3878 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3879
3880 gma_write16(hw, port, GM_RX_CTRL, reg);
3881}
3882
0885a30b 3883static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3884 struct rtnl_link_stats64 *stats)
3885{
3886 struct sky2_port *sky2 = netdev_priv(dev);
3887 struct sky2_hw *hw = sky2->hw;
3888 unsigned port = sky2->port;
3889 unsigned int start;
3890 u64 _bytes, _packets;
3891
3892 do {
3893 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3894 _bytes = sky2->rx_stats.bytes;
3895 _packets = sky2->rx_stats.packets;
3896 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3897
3898 stats->rx_packets = _packets;
3899 stats->rx_bytes = _bytes;
3900
3901 do {
3902 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3903 _bytes = sky2->tx_stats.bytes;
3904 _packets = sky2->tx_stats.packets;
3905 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3906
3907 stats->tx_packets = _packets;
3908 stats->tx_bytes = _bytes;
3909
3910 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3911 + get_stats32(hw, port, GM_RXF_BC_OK);
3912
3913 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3914
3915 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3916 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3917 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3918 + get_stats32(hw, port, GM_RXE_FRAG);
3919 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3920
3921 stats->rx_dropped = dev->stats.rx_dropped;
3922 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3923 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3924
3925 return stats;
3926}
3927
cd28ab6a
SH		 3928/* Can have one global because blinking is controlled by
3929 * ethtool and that is always under RTNL mutex
3930 */
a84d0a3d 3931static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
cd28ab6a 3932{
a84d0a3d
SH		 3933 struct sky2_hw *hw = sky2->hw;
3934 unsigned port = sky2->port;
793b883e 3935
a84d0a3d
SH		 3936 spin_lock_bh(&sky2->phy_lock);
3937 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3938 hw->chip_id == CHIP_ID_YUKON_EX ||
3939 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3940 u16 pg;
793b883e
SH		 3941 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3942 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
793b883e 3943
a84d0a3d
SH		 3944 switch (mode) {
3945 case MO_LED_OFF:
3946 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3947 PHY_M_LEDC_LOS_CTRL(8) |
3948 PHY_M_LEDC_INIT_CTRL(8) |
3949 PHY_M_LEDC_STA1_CTRL(8) |
3950 PHY_M_LEDC_STA0_CTRL(8));
3951 break;
3952 case MO_LED_ON:
3953 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3954 PHY_M_LEDC_LOS_CTRL(9) |
3955 PHY_M_LEDC_INIT_CTRL(9) |
3956 PHY_M_LEDC_STA1_CTRL(9) |
3957 PHY_M_LEDC_STA0_CTRL(9));
3958 break;
3959 case MO_LED_BLINK:
3960 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3961 PHY_M_LEDC_LOS_CTRL(0xa) |
3962 PHY_M_LEDC_INIT_CTRL(0xa) |
3963 PHY_M_LEDC_STA1_CTRL(0xa) |
3964 PHY_M_LEDC_STA0_CTRL(0xa));
3965 break;
3966 case MO_LED_NORM:
3967 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3968 PHY_M_LEDC_LOS_CTRL(1) |
3969 PHY_M_LEDC_INIT_CTRL(8) |
3970 PHY_M_LEDC_STA1_CTRL(7) |
3971 PHY_M_LEDC_STA0_CTRL(7));
3972 }
793b883e 3973
a84d0a3d
SH		 3974 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3975 } else
7d2e3cb7 3976 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
a84d0a3d
SH		 3977 PHY_M_LED_MO_DUP(mode) |
3978 PHY_M_LED_MO_10(mode) |
3979 PHY_M_LED_MO_100(mode) |
3980 PHY_M_LED_MO_1000(mode) |
3981 PHY_M_LED_MO_RX(mode) |
3982 PHY_M_LED_MO_TX(mode));
3983
3984 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3985}
3986
3987/* blink LED's for finding board */
74e532ff 3988static int sky2_set_phys_id(struct net_device *dev,
3989 enum ethtool_phys_id_state state)
cd28ab6a
SH		 3990{
3991 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3992
74e532ff 3993 switch (state) {
3994 case ETHTOOL_ID_ACTIVE:
fce55922 3995 return 1; /* cycle on/off once per second */
74e532ff 3996 case ETHTOOL_ID_INACTIVE:
3997 sky2_led(sky2, MO_LED_NORM);
3998 break;
3999 case ETHTOOL_ID_ON:
a84d0a3d 4000 sky2_led(sky2, MO_LED_ON);
74e532ff 4001 break;
4002 case ETHTOOL_ID_OFF:
a84d0a3d 4003 sky2_led(sky2, MO_LED_OFF);
74e532ff 4004 break;
793b883e 4005 }
cd28ab6a
SH		 4006
4007 return 0;
4008}
4009
4010static void sky2_get_pauseparam(struct net_device *dev,
4011 struct ethtool_pauseparam *ecmd)
4012{
4013 struct sky2_port *sky2 = netdev_priv(dev);
4014
16ad91e1
SH		 4015 switch (sky2->flow_mode) {
4016 case FC_NONE:
4017 ecmd->tx_pause = ecmd->rx_pause = 0;
4018 break;
4019 case FC_TX:
4020 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
4021 break;
4022 case FC_RX:
4023 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
4024 break;
4025 case FC_BOTH:
4026 ecmd->tx_pause = ecmd->rx_pause = 1;
4027 }
4028
0ea065e5
SH		 4029 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
4030 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
cd28ab6a
SH		 4031}
4032
4033static int sky2_set_pauseparam(struct net_device *dev,
4034 struct ethtool_pauseparam *ecmd)
4035{
4036 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 4037
0ea065e5
SH		 4038 if (ecmd->autoneg == AUTONEG_ENABLE)
4039 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
4040 else
4041 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
4042
16ad91e1 4043 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 4044
16ad91e1
SH		 4045 if (netif_running(dev))
4046 sky2_phy_reinit(sky2);
cd28ab6a 4047
2eaba1a2 4048 return 0;
cd28ab6a
SH		 4049}
4050
fb17358f
SH		 4051static int sky2_get_coalesce(struct net_device *dev,
4052 struct ethtool_coalesce *ecmd)
4053{
4054 struct sky2_port *sky2 = netdev_priv(dev);
4055 struct sky2_hw *hw = sky2->hw;
4056
4057 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
4058 ecmd->tx_coalesce_usecs = 0;
4059 else {
4060 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
4061 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
4062 }
4063 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
4064
4065 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
4066 ecmd->rx_coalesce_usecs = 0;
4067 else {
4068 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
4069 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
4070 }
4071 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
4072
4073 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
4074 ecmd->rx_coalesce_usecs_irq = 0;
4075 else {
4076 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
4077 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
4078 }
4079
4080 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
4081
4082 return 0;
4083}
4084
4085/* Note: this affect both ports */
4086static int sky2_set_coalesce(struct net_device *dev,
4087 struct ethtool_coalesce *ecmd)
4088{
4089 struct sky2_port *sky2 = netdev_priv(dev);
4090 struct sky2_hw *hw = sky2->hw;
77b3d6a2 4091 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 4092
77b3d6a2
SH		 4093 if (ecmd->tx_coalesce_usecs > tmax ||
4094 ecmd->rx_coalesce_usecs > tmax ||
4095 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 4096 return -EINVAL;
4097
ee5f68fe 4098 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
fb17358f 4099 return -EINVAL;
ff81fbbe 4100 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 4101 return -EINVAL;
060b946c 4102 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
fb17358f
SH		 4103 return -EINVAL;
4104
4105 if (ecmd->tx_coalesce_usecs == 0)
4106 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
4107 else {
4108 sky2_write32(hw, STAT_TX_TIMER_INI,
4109 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
4110 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
4111 }
4112 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
4113
4114 if (ecmd->rx_coalesce_usecs == 0)
4115 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
4116 else {
4117 sky2_write32(hw, STAT_LEV_TIMER_INI,
4118 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
4119 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
4120 }
4121 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
4122
4123 if (ecmd->rx_coalesce_usecs_irq == 0)
4124 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
4125 else {
d28d4870 4126 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 4127 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
4128 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
4129 }
4130 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
4131 return 0;
4132}
4133
738a849c 4134/*
4135 * Hardware is limited to min of 128 and max of 2048 for ring size
4136 * and rounded up to next power of two
4137 * to avoid division in modulus calclation
4138 */
4139static unsigned long roundup_ring_size(unsigned long pending)
4140{
4141 return max(128ul, roundup_pow_of_two(pending+1));
4142}
4143
793b883e
SH		 4144static void sky2_get_ringparam(struct net_device *dev,
4145 struct ethtool_ringparam *ering)
4146{
4147 struct sky2_port *sky2 = netdev_priv(dev);
4148
4149 ering->rx_max_pending = RX_MAX_PENDING;
ee5f68fe 4150 ering->tx_max_pending = TX_MAX_PENDING;
793b883e
SH		 4151
4152 ering->rx_pending = sky2->rx_pending;
793b883e
SH		 4153 ering->tx_pending = sky2->tx_pending;
4154}
4155
4156static int sky2_set_ringparam(struct net_device *dev,
4157 struct ethtool_ringparam *ering)
4158{
4159 struct sky2_port *sky2 = netdev_priv(dev);
793b883e
SH		 4160
4161 if (ering->rx_pending > RX_MAX_PENDING ||
4162 ering->rx_pending < 8 ||
ee5f68fe
SH		 4163 ering->tx_pending < TX_MIN_PENDING ||
4164 ering->tx_pending > TX_MAX_PENDING)
793b883e
SH		 4165 return -EINVAL;
4166
af18d8b8 4167 sky2_detach(dev);
793b883e
SH		 4168
4169 sky2->rx_pending = ering->rx_pending;
4170 sky2->tx_pending = ering->tx_pending;
738a849c 4171 sky2->tx_ring_size = roundup_ring_size(sky2->tx_pending);
793b883e 4172
af18d8b8 4173 return sky2_reattach(dev);
793b883e
SH		 4174}
4175
793b883e
SH		 4176static int sky2_get_regs_len(struct net_device *dev)
4177{
6e4cbb34 4178 return 0x4000;
793b883e
SH		 4179}
4180
c32bbff8
MM		 4181static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4182{
4183 /* This complicated switch statement is to make sure and
4184 * only access regions that are unreserved.
4185 * Some blocks are only valid on dual port cards.
4186 */
4187 switch (b) {
4188 /* second port */
4189 case 5: /* Tx Arbiter 2 */
4190 case 9: /* RX2 */
4191 case 14 ... 15: /* TX2 */
4192 case 17: case 19: /* Ram Buffer 2 */
4193 case 22 ... 23: /* Tx Ram Buffer 2 */
4194 case 25: /* Rx MAC Fifo 1 */
4195 case 27: /* Tx MAC Fifo 2 */
4196 case 31: /* GPHY 2 */
4197 case 40 ... 47: /* Pattern Ram 2 */
4198 case 52: case 54: /* TCP Segmentation 2 */
4199 case 112 ... 116: /* GMAC 2 */
4200 return hw->ports > 1;
4201
4202 case 0: /* Control */
4203 case 2: /* Mac address */
4204 case 4: /* Tx Arbiter 1 */
4205 case 7: /* PCI express reg */
4206 case 8: /* RX1 */
4207 case 12 ... 13: /* TX1 */
4208 case 16: case 18:/* Rx Ram Buffer 1 */
4209 case 20 ... 21: /* Tx Ram Buffer 1 */
4210 case 24: /* Rx MAC Fifo 1 */
4211 case 26: /* Tx MAC Fifo 1 */
4212 case 28 ... 29: /* Descriptor and status unit */
4213 case 30: /* GPHY 1*/
4214 case 32 ... 39: /* Pattern Ram 1 */
4215 case 48: case 50: /* TCP Segmentation 1 */
4216 case 56 ... 60: /* PCI space */
4217 case 80 ... 84: /* GMAC 1 */
4218 return 1;
4219
4220 default:
4221 return 0;
4222 }
4223}
4224
793b883e
SH		 4225/*
4226 * Returns copy of control register region
3ead5db7 4227 * Note: ethtool_get_regs always provides full size (16k) buffer
793b883e
SH		 4228 */
4229static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4230 void *p)
4231{
4232 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 4233 const void __iomem *io = sky2->hw->regs;
295b54c4 4234 unsigned int b;
793b883e
SH		 4235
4236 regs->version = 1;
793b883e 4237
295b54c4 4238 for (b = 0; b < 128; b++) {
c32bbff8
MM		 4239 /* skip poisonous diagnostic ram region in block 3 */
4240 if (b == 3)
295b54c4 4241 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
c32bbff8 4242 else if (sky2_reg_access_ok(sky2->hw, b))
295b54c4 4243 memcpy_fromio(p, io, 128);
c32bbff8 4244 else
295b54c4 4245 memset(p, 0, 128);
3ead5db7 4246
295b54c4
SH		 4247 p += 128;
4248 io += 128;
4249 }
793b883e 4250}
cd28ab6a 4251
f4331a6d
SH		 4252static int sky2_get_eeprom_len(struct net_device *dev)
4253{
4254 struct sky2_port *sky2 = netdev_priv(dev);
b32f40c4 4255 struct sky2_hw *hw = sky2->hw;
f4331a6d
SH		 4256 u16 reg2;
4257
b32f40c4 4258 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
f4331a6d
SH		 4259 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4260}
4261
1413235c 4262static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
f4331a6d 4263{
1413235c 4264 unsigned long start = jiffies;
f4331a6d 4265
1413235c
SH		 4266 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4267 /* Can take up to 10.6 ms for write */
4268 if (time_after(jiffies, start + HZ/4)) {
ada1db5c 4269 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
1413235c
SH		 4270 return -ETIMEDOUT;
4271 }
4272 mdelay(1);
4273 }
167f53d0 4274
1413235c
SH		 4275 return 0;
4276}
167f53d0 4277
1413235c
SH		 4278static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4279 u16 offset, size_t length)
4280{
4281 int rc = 0;
4282
4283 while (length > 0) {
4284 u32 val;
4285
4286 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4287 rc = sky2_vpd_wait(hw, cap, 0);
4288 if (rc)
4289 break;
4290
4291 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4292
4293 memcpy(data, &val, min(sizeof(val), length));
4294 offset += sizeof(u32);
4295 data += sizeof(u32);
4296 length -= sizeof(u32);
4297 }
4298
4299 return rc;
f4331a6d
SH		 4300}
4301
1413235c
SH		 4302static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4303 u16 offset, unsigned int length)
f4331a6d 4304{
1413235c
SH		 4305 unsigned int i;
4306 int rc = 0;
4307
4308 for (i = 0; i < length; i += sizeof(u32)) {
4309 u32 val = *(u32 *)(data + i);
4310
4311 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4312 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4313
4314 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4315 if (rc)
4316 break;
4317 }
4318 return rc;
f4331a6d
SH		 4319}
4320
4321static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4322 u8 *data)
4323{
4324 struct sky2_port *sky2 = netdev_priv(dev);
4325 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4326
4327 if (!cap)
4328 return -EINVAL;
4329
4330 eeprom->magic = SKY2_EEPROM_MAGIC;
4331
1413235c 4332 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4333}
4334
4335static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4336 u8 *data)
4337{
4338 struct sky2_port *sky2 = netdev_priv(dev);
4339 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
f4331a6d
SH		 4340
4341 if (!cap)
4342 return -EINVAL;
4343
4344 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4345 return -EINVAL;
4346
1413235c
SH		 4347 /* Partial writes not supported */
4348 if ((eeprom->offset & 3) || (eeprom->len & 3))
4349 return -EINVAL;
f4331a6d 4350
1413235c 4351 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
f4331a6d
SH		 4352}
4353
c8f44aff
MM		 4354static netdev_features_t sky2_fix_features(struct net_device *dev,
4355 netdev_features_t features)
bf73130d 4356{
f5d64037
MM		 4357 const struct sky2_port *sky2 = netdev_priv(dev);
4358 const struct sky2_hw *hw = sky2->hw;
bf73130d 4359
f5d64037
MM		 4360 /* In order to do Jumbo packets on these chips, need to turn off the
4361 * transmit store/forward. Therefore checksum offload won't work.
4362 */
aa5ca96c 4363 if (dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U) {
4364 netdev_info(dev, "checksum offload not possible with jumbo frames\n");
f5d64037 4365 features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
aa5ca96c 4366 }
4367
4368 /* Some hardware requires receive checksum for RSS to work. */
4369 if ( (features & NETIF_F_RXHASH) &&
4370 !(features & NETIF_F_RXCSUM) &&
4371 (sky2->hw->flags & SKY2_HW_RSS_CHKSUM)) {
4372 netdev_info(dev, "receive hashing forces receive checksum\n");
4373 features |= NETIF_F_RXCSUM;
4374 }
86aa7785 4375
f5d64037
MM		 4376 return features;
4377}
86aa7785 4378
c8f44aff 4379static int sky2_set_features(struct net_device *dev, netdev_features_t features)
f5d64037
MM		 4380{
4381 struct sky2_port *sky2 = netdev_priv(dev);
c8f44aff 4382 netdev_features_t changed = dev->features ^ features;
86aa7785 4383
f5d64037 4384 if (changed & NETIF_F_RXCSUM) {
3ad9b358 4385 bool on = features & NETIF_F_RXCSUM;
f5d64037
MM		 4386 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
4387 on ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
4388 }
bf73130d 4389
f5d64037
MM		 4390 if (changed & NETIF_F_RXHASH)
4391 rx_set_rss(dev, features);
86aa7785 4392
f5d64037
MM		 4393 if (changed & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4394 sky2_vlan_mode(dev, features);
bf73130d
SH		 4395
4396 return 0;
4397}
f4331a6d 4398
7282d491 4399static const struct ethtool_ops sky2_ethtool_ops = {
f4331a6d
SH		 4400 .get_settings = sky2_get_settings,
4401 .set_settings = sky2_set_settings,
4402 .get_drvinfo = sky2_get_drvinfo,
4403 .get_wol = sky2_get_wol,
4404 .set_wol = sky2_set_wol,
4405 .get_msglevel = sky2_get_msglevel,
4406 .set_msglevel = sky2_set_msglevel,
4407 .nway_reset = sky2_nway_reset,
4408 .get_regs_len = sky2_get_regs_len,
4409 .get_regs = sky2_get_regs,
4410 .get_link = ethtool_op_get_link,
4411 .get_eeprom_len = sky2_get_eeprom_len,
4412 .get_eeprom = sky2_get_eeprom,
4413 .set_eeprom = sky2_set_eeprom,
f4331a6d
SH		 4414 .get_strings = sky2_get_strings,
4415 .get_coalesce = sky2_get_coalesce,
4416 .set_coalesce = sky2_set_coalesce,
4417 .get_ringparam = sky2_get_ringparam,
4418 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 4419 .get_pauseparam = sky2_get_pauseparam,
4420 .set_pauseparam = sky2_set_pauseparam,
74e532ff 4421 .set_phys_id = sky2_set_phys_id,
b9f2c044 4422 .get_sset_count = sky2_get_sset_count,
cd28ab6a
SH		 4423 .get_ethtool_stats = sky2_get_ethtool_stats,
4424};
4425
3cf26753
SH		 4426#ifdef CONFIG_SKY2_DEBUG
4427
4428static struct dentry *sky2_debug;
4429
e4c2abe2
SH		 4430
4431/*
4432 * Read and parse the first part of Vital Product Data
4433 */
4434#define VPD_SIZE 128
4435#define VPD_MAGIC 0x82
4436
4437static const struct vpd_tag {
4438 char tag[2];
4439 char *label;
4440} vpd_tags[] = {
4441 { "PN", "Part Number" },
4442 { "EC", "Engineering Level" },
4443 { "MN", "Manufacturer" },
4444 { "SN", "Serial Number" },
4445 { "YA", "Asset Tag" },
4446 { "VL", "First Error Log Message" },
4447 { "VF", "Second Error Log Message" },
4448 { "VB", "Boot Agent ROM Configuration" },
4449 { "VE", "EFI UNDI Configuration" },
4450};
4451
4452static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4453{
4454 size_t vpd_size;
4455 loff_t offs;
4456 u8 len;
4457 unsigned char *buf;
4458 u16 reg2;
4459
4460 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4461 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4462
4463 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4464 buf = kmalloc(vpd_size, GFP_KERNEL);
4465 if (!buf) {
4466 seq_puts(seq, "no memory!\n");
4467 return;
4468 }
4469
4470 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4471 seq_puts(seq, "VPD read failed\n");
4472 goto out;
4473 }
4474
4475 if (buf[0] != VPD_MAGIC) {
4476 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4477 goto out;
4478 }
4479 len = buf[1];
4480 if (len == 0 || len > vpd_size - 4) {
4481 seq_printf(seq, "Invalid id length: %d\n", len);
4482 goto out;
4483 }
4484
4485 seq_printf(seq, "%.*s\n", len, buf + 3);
4486 offs = len + 3;
4487
4488 while (offs < vpd_size - 4) {
4489 int i;
4490
4491 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4492 break;
4493 len = buf[offs + 2];
4494 if (offs + len + 3 >= vpd_size)
4495 break;
4496
4497 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4498 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4499 seq_printf(seq, " %s: %.*s\n",
4500 vpd_tags[i].label, len, buf + offs + 3);
4501 break;
4502 }
4503 }
4504 offs += len + 3;
4505 }
4506out:
4507 kfree(buf);
4508}
4509
3cf26753
SH		 4510static int sky2_debug_show(struct seq_file *seq, void *v)
4511{
4512 struct net_device *dev = seq->private;
4513 const struct sky2_port *sky2 = netdev_priv(dev);
bea3348e 4514 struct sky2_hw *hw = sky2->hw;
3cf26753
SH		 4515 unsigned port = sky2->port;
4516 unsigned idx, last;
4517 int sop;
4518
e4c2abe2 4519 sky2_show_vpd(seq, hw);
3cf26753 4520
e4c2abe2 4521 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
3cf26753
SH		 4522 sky2_read32(hw, B0_ISRC),
4523 sky2_read32(hw, B0_IMSK),
4524 sky2_read32(hw, B0_Y2_SP_ICR));
4525
e4c2abe2
SH		 4526 if (!netif_running(dev)) {
4527 seq_printf(seq, "network not running\n");
4528 return 0;
4529 }
4530
bea3348e 4531 napi_disable(&hw->napi);
3cf26753
SH		 4532 last = sky2_read16(hw, STAT_PUT_IDX);
4533
efe91932 4534 seq_printf(seq, "Status ring %u\n", hw->st_size);
3cf26753
SH		 4535 if (hw->st_idx == last)
4536 seq_puts(seq, "Status ring (empty)\n");
4537 else {
4538 seq_puts(seq, "Status ring\n");
efe91932 4539 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4540 idx = RING_NEXT(idx, hw->st_size)) {
3cf26753
SH		 4541 const struct sky2_status_le *le = hw->st_le + idx;
4542 seq_printf(seq, "[%d] %#x %d %#x\n",
4543 idx, le->opcode, le->length, le->status);
4544 }
4545 seq_puts(seq, "\n");
4546 }
4547
4548 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4549 sky2->tx_cons, sky2->tx_prod,
4550 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4551 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4552
4553 /* Dump contents of tx ring */
4554 sop = 1;
ee5f68fe
SH		 4555 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4556 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
3cf26753
SH		 4557 const struct sky2_tx_le *le = sky2->tx_le + idx;
4558 u32 a = le32_to_cpu(le->addr);
4559
4560 if (sop)
4561 seq_printf(seq, "%u:", idx);
4562 sop = 0;
4563
060b946c 4564 switch (le->opcode & ~HW_OWNER) {
3cf26753
SH		 4565 case OP_ADDR64:
4566 seq_printf(seq, " %#x:", a);
4567 break;
4568 case OP_LRGLEN:
4569 seq_printf(seq, " mtu=%d", a);
4570 break;
4571 case OP_VLAN:
4572 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4573 break;
4574 case OP_TCPLISW:
4575 seq_printf(seq, " csum=%#x", a);
4576 break;
4577 case OP_LARGESEND:
4578 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4579 break;
4580 case OP_PACKET:
4581 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4582 break;
4583 case OP_BUFFER:
4584 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4585 break;
4586 default:
4587 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4588 a, le16_to_cpu(le->length));
4589 }
4590
4591 if (le->ctrl & EOP) {
4592 seq_putc(seq, '\n');
4593 sop = 1;
4594 }
4595 }
4596
4597 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4598 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
c409c34b 4599 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
3cf26753
SH		 4600 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4601
d1d08d12 4602 sky2_read32(hw, B0_Y2_SP_LISR);
bea3348e 4603 napi_enable(&hw->napi);
3cf26753
SH		 4604 return 0;
4605}
4606
4607static int sky2_debug_open(struct inode *inode, struct file *file)
4608{
4609 return single_open(file, sky2_debug_show, inode->i_private);
4610}
4611
4612static const struct file_operations sky2_debug_fops = {
4613 .owner = THIS_MODULE,
4614 .open = sky2_debug_open,
4615 .read = seq_read,
4616 .llseek = seq_lseek,
4617 .release = single_release,
4618};
4619
4620/*
4621 * Use network device events to create/remove/rename
4622 * debugfs file entries
4623 */
4624static int sky2_device_event(struct notifier_block *unused,
4625 unsigned long event, void *ptr)
4626{
4627 struct net_device *dev = ptr;
5b296bc9 4628 struct sky2_port *sky2 = netdev_priv(dev);
3cf26753 4629
926d0977 4630 if (dev->netdev_ops->ndo_open != sky2_open || !sky2_debug)
5b296bc9 4631 return NOTIFY_DONE;
3cf26753 4632
060b946c 4633 switch (event) {
5b296bc9
SH		 4634 case NETDEV_CHANGENAME:
4635 if (sky2->debugfs) {
4636 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4637 sky2_debug, dev->name);
4638 }
4639 break;
3cf26753 4640
5b296bc9
SH		 4641 case NETDEV_GOING_DOWN:
4642 if (sky2->debugfs) {
ada1db5c 4643 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
5b296bc9
SH		 4644 debugfs_remove(sky2->debugfs);
4645 sky2->debugfs = NULL;
3cf26753 4646 }
5b296bc9
SH		 4647 break;
4648
4649 case NETDEV_UP:
4650 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4651 sky2_debug, dev,
4652 &sky2_debug_fops);
4653 if (IS_ERR(sky2->debugfs))
4654 sky2->debugfs = NULL;
3cf26753
SH		 4655 }
4656
4657 return NOTIFY_DONE;
4658}
4659
4660static struct notifier_block sky2_notifier = {
4661 .notifier_call = sky2_device_event,
4662};
4663
4664
4665static __init void sky2_debug_init(void)
4666{
4667 struct dentry *ent;
4668
4669 ent = debugfs_create_dir("sky2", NULL);
4670 if (!ent || IS_ERR(ent))
4671 return;
4672
4673 sky2_debug = ent;
4674 register_netdevice_notifier(&sky2_notifier);
4675}
4676
4677static __exit void sky2_debug_cleanup(void)
4678{
4679 if (sky2_debug) {
4680 unregister_netdevice_notifier(&sky2_notifier);
4681 debugfs_remove(sky2_debug);
4682 sky2_debug = NULL;
4683 }
4684}
4685
4686#else
4687#define sky2_debug_init()
4688#define sky2_debug_cleanup()
4689#endif
4690
1436b301
SH		 4691/* Two copies of network device operations to handle special case of
4692 not allowing netpoll on second port */
4693static const struct net_device_ops sky2_netdev_ops[2] = {
4694 {
926d0977 4695 .ndo_open = sky2_open,
4696 .ndo_stop = sky2_close,
00829823 4697 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4698 .ndo_do_ioctl = sky2_ioctl,
4699 .ndo_validate_addr = eth_validate_addr,
4700 .ndo_set_mac_address = sky2_set_mac_address,
afc4b13d 4701 .ndo_set_rx_mode = sky2_set_multicast,
1436b301 4702 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4703 .ndo_fix_features = sky2_fix_features,
4704 .ndo_set_features = sky2_set_features,
1436b301 4705 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4706 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4707#ifdef CONFIG_NET_POLL_CONTROLLER
4708 .ndo_poll_controller = sky2_netpoll,
4709#endif
4710 },
4711 {
926d0977 4712 .ndo_open = sky2_open,
4713 .ndo_stop = sky2_close,
00829823 4714 .ndo_start_xmit = sky2_xmit_frame,
1436b301
SH		 4715 .ndo_do_ioctl = sky2_ioctl,
4716 .ndo_validate_addr = eth_validate_addr,
4717 .ndo_set_mac_address = sky2_set_mac_address,
afc4b13d 4718 .ndo_set_rx_mode = sky2_set_multicast,
1436b301 4719 .ndo_change_mtu = sky2_change_mtu,
f5d64037
MM		 4720 .ndo_fix_features = sky2_fix_features,
4721 .ndo_set_features = sky2_set_features,
1436b301 4722 .ndo_tx_timeout = sky2_tx_timeout,
0885a30b 4723 .ndo_get_stats64 = sky2_get_stats,
1436b301
SH		 4724 },
4725};
3cf26753 4726
cd28ab6a
SH		 4727/* Initialize network device */
4728static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832 4729 unsigned port,
be63a21c 4730 int highmem, int wol)
cd28ab6a
SH		 4731{
4732 struct sky2_port *sky2;
4733 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4734
41de8d4c 4735 if (!dev)
cd28ab6a 4736 return NULL;
cd28ab6a 4737
cd28ab6a 4738 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 4739 dev->irq = hw->pdev->irq;
cd28ab6a 4740 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
cd28ab6a 4741 dev->watchdog_timeo = TX_WATCHDOG;
1436b301 4742 dev->netdev_ops = &sky2_netdev_ops[port];
cd28ab6a
SH		 4743
4744 sky2 = netdev_priv(dev);
4745 sky2->netdev = dev;
4746 sky2->hw = hw;
4747 sky2->msg_enable = netif_msg_init(debug, default_msg);
4748
cd28ab6a 4749 /* Auto speed and flow control */
0ea065e5
SH		 4750 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4751 if (hw->chip_id != CHIP_ID_YUKON_XL)
f5d64037 4752 dev->hw_features |= NETIF_F_RXCSUM;
0ea065e5 4753
16ad91e1
SH		 4754 sky2->flow_mode = FC_BOTH;
4755
cd28ab6a
SH		 4756 sky2->duplex = -1;
4757 sky2->speed = -1;
4758 sky2->advertising = sky2_supported_modes(hw);
be63a21c 4759 sky2->wol = wol;
75d070c5 4760
e07b1aa8 4761 spin_lock_init(&sky2->phy_lock);
ee5f68fe 4762
793b883e 4763 sky2->tx_pending = TX_DEF_PENDING;
738a849c 4764 sky2->tx_ring_size = roundup_ring_size(TX_DEF_PENDING);
290d4de5 4765 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 4766
4767 hw->dev[port] = dev;
4768
4769 sky2->port = port;
4770
f5d64037 4771 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG | NETIF_F_TSO;
86aa7785 4772
cd28ab6a
SH		 4773 if (highmem)
4774 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 4775
bf73130d
SH		 4776 /* Enable receive hashing unless hardware is known broken */
4777 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
f5d64037
MM		 4778 dev->hw_features |= NETIF_F_RXHASH;
4779
4780 if (!(hw->flags & SKY2_HW_VLAN_BROKEN)) {
4781 dev->hw_features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4782 dev->vlan_features |= SKY2_VLAN_OFFLOADS;
4783 }
bf73130d 4784
f5d64037 4785 dev->features |= dev->hw_features;
d1f13708 4786
cd28ab6a 4787 /* read the mac address */
793b883e 4788 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 4789 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a 4790
cd28ab6a
SH		 4791 return dev;
4792}
4793
28bd181a 4794static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 4795{
4796 const struct sky2_port *sky2 = netdev_priv(dev);
4797
6c35abae 4798 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
cd28ab6a
SH		 4799}
4800
fb2690a9 4801/* Handle software interrupt used during MSI test */
7d12e780 4802static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 4803{
4804 struct sky2_hw *hw = dev_id;
4805 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4806
4807 if (status == 0)
4808 return IRQ_NONE;
4809
4810 if (status & Y2_IS_IRQ_SW) {
ea76e635 4811 hw->flags |= SKY2_HW_USE_MSI;
fb2690a9
SH		 4812 wake_up(&hw->msi_wait);
4813 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4814 }
4815 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4816
4817 return IRQ_HANDLED;
4818}
4819
4820/* Test interrupt path by forcing a a software IRQ */
4821static int __devinit sky2_test_msi(struct sky2_hw *hw)
4822{
4823 struct pci_dev *pdev = hw->pdev;
4824 int err;
4825
060b946c 4826 init_waitqueue_head(&hw->msi_wait);
bb507fe1 4827
fb2690a9
SH		 4828 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4829
b0a20ded 4830 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 4831 if (err) {
b02a9258 4832 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 4833 return err;
4834 }
4835
fb2690a9 4836 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 4837 sky2_read8(hw, B0_CTST);
fb2690a9 4838
ea76e635 4839 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
fb2690a9 4840
ea76e635 4841 if (!(hw->flags & SKY2_HW_USE_MSI)) {
fb2690a9 4842 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 4843 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4844 "switching to INTx mode.\n");
fb2690a9
SH		 4845
4846 err = -EOPNOTSUPP;
4847 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4848 }
4849
4850 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 4851 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 4852
4853 free_irq(pdev->irq, hw);
4854
4855 return err;
4856}
4857
c7127a34
SH		 4858/* This driver supports yukon2 chipset only */
4859static const char *sky2_name(u8 chipid, char *buf, int sz)
4860{
4861 const char *name[] = {
4862 "XL", /* 0xb3 */
4863 "EC Ultra", /* 0xb4 */
4864 "Extreme", /* 0xb5 */
4865 "EC", /* 0xb6 */
4866 "FE", /* 0xb7 */
4867 "FE+", /* 0xb8 */
4868 "Supreme", /* 0xb9 */
0ce8b98d 4869 "UL 2", /* 0xba */
0f5aac70
SH		 4870 "Unknown", /* 0xbb */
4871 "Optima", /* 0xbc */
4fb99cd6 4872 "Optima Prime", /* 0xbd */
4873 "Optima 2", /* 0xbe */
c7127a34
SH		 4874 };
4875
4fb99cd6 4876 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OP_2)
c7127a34
SH		 4877 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4878 else
4879 snprintf(buf, sz, "(chip %#x)", chipid);
4880 return buf;
4881}
4882
cd28ab6a
SH		 4883static int __devinit sky2_probe(struct pci_dev *pdev,
4884 const struct pci_device_id *ent)
4885{
0bdb0bd0 4886 struct net_device *dev, *dev1;
cd28ab6a 4887 struct sky2_hw *hw;
be63a21c 4888 int err, using_dac = 0, wol_default;
3834507d 4889 u32 reg;
c7127a34 4890 char buf1[16];
cd28ab6a 4891
793b883e
SH		 4892 err = pci_enable_device(pdev);
4893 if (err) {
b02a9258 4894 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 4895 goto err_out;
4896 }
4897
6cc90a5a
SH		 4898 /* Get configuration information
4899 * Note: only regular PCI config access once to test for HW issues
4900 * other PCI access through shared memory for speed and to
4901 * avoid MMCONFIG problems.
4902 */
4903 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4904 if (err) {
4905 dev_err(&pdev->dev, "PCI read config failed\n");
4906 goto err_out;
4907 }
4908
4909 if (~reg == 0) {
4910 dev_err(&pdev->dev, "PCI configuration read error\n");
4911 goto err_out;
4912 }
4913
793b883e
SH		 4914 err = pci_request_regions(pdev, DRV_NAME);
4915 if (err) {
b02a9258 4916 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
44a1d2e5 4917 goto err_out_disable;
cd28ab6a
SH		 4918 }
4919
4920 pci_set_master(pdev);
4921
d1f3d4dd 4922 if (sizeof(dma_addr_t) > sizeof(u32) &&
6a35528a 4923 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
d1f3d4dd 4924 using_dac = 1;
6a35528a 4925 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
d1f3d4dd 4926 if (err < 0) {
b02a9258
SH		 4927 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4928 "for consistent allocations\n");
d1f3d4dd
SH		 4929 goto err_out_free_regions;
4930 }
d1f3d4dd 4931 } else {
284901a9 4932 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cd28ab6a 4933 if (err) {
b02a9258 4934 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 4935 goto err_out_free_regions;
4936 }
4937 }
d1f3d4dd 4938
3834507d
SH		 4939
4940#ifdef __BIG_ENDIAN
4941 /* The sk98lin vendor driver uses hardware byte swapping but
4942 * this driver uses software swapping.
4943 */
4944 reg &= ~PCI_REV_DESC;
060b946c 4945 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3834507d
SH		 4946 if (err) {
4947 dev_err(&pdev->dev, "PCI write config failed\n");
4948 goto err_out_free_regions;
4949 }
4950#endif
4951
9d731d77 4952 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
be63a21c 4953
cd28ab6a 4954 err = -ENOMEM;
66466797
SH		 4955
4956 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4957 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
cd28ab6a 4958 if (!hw) {
b02a9258 4959 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 4960 goto err_out_free_regions;
4961 }
4962
cd28ab6a 4963 hw->pdev = pdev;
66466797 4964 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
cd28ab6a
SH		 4965
4966 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4967 if (!hw->regs) {
b02a9258 4968 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 4969 goto err_out_free_hw;
4970 }
4971
e3173832 4972 err = sky2_init(hw);
cd28ab6a 4973 if (err)
793b883e 4974 goto err_out_iounmap;
cd28ab6a 4975
efe91932 4976 /* ring for status responses */
bf73130d 4977 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
efe91932 4978 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4979 &hw->st_dma);
4980 if (!hw->st_le)
4981 goto err_out_reset;
4982
c844d483
SH		 4983 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4984 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
cd28ab6a 4985
e3173832
SH		 4986 sky2_reset(hw);
4987
be63a21c 4988 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 4989 if (!dev) {
4990 err = -ENOMEM;
cd28ab6a 4991 goto err_out_free_pci;
7f60c64b 4992 }
cd28ab6a 4993
9fa1b1f3
SH		 4994 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4995 err = sky2_test_msi(hw);
4996 if (err == -EOPNOTSUPP)
4997 pci_disable_msi(pdev);
4998 else if (err)
4999 goto err_out_free_netdev;
5000 }
5001
793b883e
SH		 5002 err = register_netdev(dev);
5003 if (err) {
b02a9258 5004 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 5005 goto err_out_free_netdev;
5006 }
5007
33cb7d33
BP		 5008 netif_carrier_off(dev);
5009
6de16237
SH		 5010 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
5011
cd28ab6a
SH		 5012 sky2_show_addr(dev);
5013
7f60c64b 5014 if (hw->ports > 1) {
be63a21c 5015 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
0bdb0bd0 5016 if (!dev1) {
5017 err = -ENOMEM;
5018 goto err_out_unregister;
ca519274 5019 }
0bdb0bd0 5020
5021 err = register_netdev(dev1);
5022 if (err) {
5023 dev_err(&pdev->dev, "cannot register second net device\n");
5024 goto err_out_free_dev1;
5025 }
5026
5027 err = sky2_setup_irq(hw, hw->irq_name);
5028 if (err)
5029 goto err_out_unregister_dev1;
5030
5031 sky2_show_addr(dev1);
cd28ab6a
SH		 5032 }
5033
32c2c300 5034 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
81906791
SH		 5035 INIT_WORK(&hw->restart_work, sky2_restart);
5036
793b883e 5037 pci_set_drvdata(pdev, hw);
1ae861e6 5038 pdev->d3_delay = 150;
793b883e 5039
cd28ab6a
SH		 5040 return 0;
5041
0bdb0bd0 5042err_out_unregister_dev1:
5043 unregister_netdev(dev1);
5044err_out_free_dev1:
5045 free_netdev(dev1);
793b883e 5046err_out_unregister:
ea76e635 5047 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 5048 pci_disable_msi(pdev);
793b883e 5049 unregister_netdev(dev);
cd28ab6a
SH		 5050err_out_free_netdev:
5051 free_netdev(dev);
cd28ab6a 5052err_out_free_pci:
efe91932 5053 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5054 hw->st_le, hw->st_dma);
5055err_out_reset:
793b883e 5056 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 5057err_out_iounmap:
5058 iounmap(hw->regs);
5059err_out_free_hw:
5060 kfree(hw);
5061err_out_free_regions:
5062 pci_release_regions(pdev);
44a1d2e5 5063err_out_disable:
cd28ab6a 5064 pci_disable_device(pdev);
cd28ab6a 5065err_out:
549a68c3 5066 pci_set_drvdata(pdev, NULL);
cd28ab6a
SH		 5067 return err;
5068}
5069
5070static void __devexit sky2_remove(struct pci_dev *pdev)
5071{
793b883e 5072 struct sky2_hw *hw = pci_get_drvdata(pdev);
6de16237 5073 int i;
cd28ab6a 5074
793b883e 5075 if (!hw)
cd28ab6a
SH		 5076 return;
5077
32c2c300 5078 del_timer_sync(&hw->watchdog_timer);
6de16237 5079 cancel_work_sync(&hw->restart_work);
d27ed387 5080
b877fe28 5081 for (i = hw->ports-1; i >= 0; --i)
6de16237 5082 unregister_netdev(hw->dev[i]);
81906791 5083
d27ed387 5084 sky2_write32(hw, B0_IMSK, 0);
0bdb0bd0 5085 sky2_read32(hw, B0_IMSK);
cd28ab6a 5086
ae306cca
SH		 5087 sky2_power_aux(hw);
5088
793b883e 5089 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 5090 sky2_read8(hw, B0_CTST);
cd28ab6a 5091
0bdb0bd0 5092 if (hw->ports > 1) {
5093 napi_disable(&hw->napi);
5094 free_irq(pdev->irq, hw);
5095 }
5096
ea76e635 5097 if (hw->flags & SKY2_HW_USE_MSI)
b0a20ded 5098 pci_disable_msi(pdev);
efe91932 5099 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
5100 hw->st_le, hw->st_dma);
cd28ab6a
SH		 5101 pci_release_regions(pdev);
5102 pci_disable_device(pdev);
793b883e 5103
b877fe28 5104 for (i = hw->ports-1; i >= 0; --i)
6de16237
SH		 5105 free_netdev(hw->dev[i]);
5106
cd28ab6a
SH		 5107 iounmap(hw->regs);
5108 kfree(hw);
5afa0a9c 5109
cd28ab6a
SH		 5110 pci_set_drvdata(pdev, NULL);
5111}
5112
0f333d10 5113static int sky2_suspend(struct device *dev)
cd28ab6a 5114{
0f333d10 5115 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5116 struct sky2_hw *hw = pci_get_drvdata(pdev);
0f333d10 5117 int i;
cd28ab6a 5118
549a68c3
SH		 5119 if (!hw)
5120 return 0;
5121
063a0b38
SH		 5122 del_timer_sync(&hw->watchdog_timer);
5123 cancel_work_sync(&hw->restart_work);
5124
19720737 5125 rtnl_lock();
3403aca2
MM		 5126
5127 sky2_all_down(hw);
f05267e7 5128 for (i = 0; i < hw->ports; i++) {
cd28ab6a 5129 struct net_device *dev = hw->dev[i];
e3173832 5130 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 5131
e3173832
SH		 5132 if (sky2->wol)
5133 sky2_wol_init(sky2);
cd28ab6a
SH		 5134 }
5135
ae306cca 5136 sky2_power_aux(hw);
19720737 5137 rtnl_unlock();
e3173832 5138
2ccc99b7 5139 return 0;
cd28ab6a
SH		 5140}
5141
94252763 5142#ifdef CONFIG_PM_SLEEP
0f333d10 5143static int sky2_resume(struct device *dev)
cd28ab6a 5144{
0f333d10 5145 struct pci_dev *pdev = to_pci_dev(dev);
793b883e 5146 struct sky2_hw *hw = pci_get_drvdata(pdev);
3403aca2 5147 int err;
cd28ab6a 5148
549a68c3
SH		 5149 if (!hw)
5150 return 0;
5151
1ad5b4a5 5152 /* Re-enable all clocks */
a0db28b8 5153 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5154 if (err) {
5155 dev_err(&pdev->dev, "PCI write config failed\n");
5156 goto out;
5157 }
1ad5b4a5 5158
3403aca2 5159 rtnl_lock();
e3173832 5160 sky2_reset(hw);
3403aca2 5161 sky2_all_up(hw);
af18d8b8 5162 rtnl_unlock();
eb35cf60 5163
ae306cca 5164 return 0;
08c06d8a 5165out:
af18d8b8 5166
b02a9258 5167 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 5168 pci_disable_device(pdev);
08c06d8a 5169 return err;
cd28ab6a 5170}
0f333d10
RW		 5171
5172static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5173#define SKY2_PM_OPS (&sky2_pm_ops)
5174
5175#else
5176
5177#define SKY2_PM_OPS NULL
cd28ab6a
SH		 5178#endif
5179
e3173832
SH		 5180static void sky2_shutdown(struct pci_dev *pdev)
5181{
0f333d10
RW		 5182 sky2_suspend(&pdev->dev);
5183 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5184 pci_set_power_state(pdev, PCI_D3hot);
e3173832
SH		 5185}
5186
cd28ab6a 5187static struct pci_driver sky2_driver = {
793b883e
SH		 5188 .name = DRV_NAME,
5189 .id_table = sky2_id_table,
5190 .probe = sky2_probe,
5191 .remove = __devexit_p(sky2_remove),
e3173832 5192 .shutdown = sky2_shutdown,
0f333d10 5193 .driver.pm = SKY2_PM_OPS,
cd28ab6a
SH		 5194};
5195
5196static int __init sky2_init_module(void)
5197{
ada1db5c 5198 pr_info("driver version " DRV_VERSION "\n");
c844d483 5199
3cf26753 5200 sky2_debug_init();
50241c4c 5201 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 5202}
5203
5204static void __exit sky2_cleanup_module(void)
5205{
5206 pci_unregister_driver(&sky2_driver);
3cf26753 5207 sky2_debug_cleanup();
cd28ab6a
SH		 5208}
5209
5210module_init(sky2_init_module);
5211module_exit(sky2_cleanup_module);
5212
5213MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 5214MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 5215MODULE_LICENSE("GPL");
5f4f9dc1 5216MODULE_VERSION(DRV_VERSION);
Linux kernel - Deliverables
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