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net/bonding: Notify state change on slaves
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/sched.h>
5a0e3ad6 36#include <linux/slab.h>
ee40fa06 37#include <linux/export.h>
225c7b1f
RD		 38#include <linux/pci.h>
39#include <linux/errno.h>
40
41#include <linux/mlx4/cmd.h>
948e306d 42#include <linux/mlx4/device.h>
e8f081aa 43#include <linux/semaphore.h>
0a9a0188 44#include <rdma/ib_smi.h>
55ad3592 45#include <linux/delay.h>
225c7b1f
RD		 46
47#include <asm/io.h>
48
49#include "mlx4.h"
e8f081aa 50#include "fw.h"
225c7b1f
RD		 51
52#define CMD_POLL_TOKEN 0xffff
e8f081aa
YP		 53#define INBOX_MASK 0xffffffffffffff00ULL
54
55#define CMD_CHAN_VER 1
56#define CMD_CHAN_IF_REV 1
225c7b1f
RD		 57
58enum {
59 /* command completed successfully: */
60 CMD_STAT_OK = 0x00,
61 /* Internal error (such as a bus error) occurred while processing command: */
62 CMD_STAT_INTERNAL_ERR = 0x01,
63 /* Operation/command not supported or opcode modifier not supported: */
64 CMD_STAT_BAD_OP = 0x02,
65 /* Parameter not supported or parameter out of range: */
66 CMD_STAT_BAD_PARAM = 0x03,
67 /* System not enabled or bad system state: */
68 CMD_STAT_BAD_SYS_STATE = 0x04,
69 /* Attempt to access reserved or unallocaterd resource: */
70 CMD_STAT_BAD_RESOURCE = 0x05,
71 /* Requested resource is currently executing a command, or is otherwise busy: */
72 CMD_STAT_RESOURCE_BUSY = 0x06,
73 /* Required capability exceeds device limits: */
74 CMD_STAT_EXCEED_LIM = 0x08,
75 /* Resource is not in the appropriate state or ownership: */
76 CMD_STAT_BAD_RES_STATE = 0x09,
77 /* Index out of range: */
78 CMD_STAT_BAD_INDEX = 0x0a,
79 /* FW image corrupted: */
80 CMD_STAT_BAD_NVMEM = 0x0b,
899698da
JM		 81 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
82 CMD_STAT_ICM_ERROR = 0x0c,
225c7b1f
RD		 83 /* Attempt to modify a QP/EE which is not in the presumed state: */
84 CMD_STAT_BAD_QP_STATE = 0x10,
85 /* Bad segment parameters (Address/Size): */
86 CMD_STAT_BAD_SEG_PARAM = 0x20,
87 /* Memory Region has Memory Windows bound to: */
88 CMD_STAT_REG_BOUND = 0x21,
89 /* HCA local attached memory not present: */
90 CMD_STAT_LAM_NOT_PRE = 0x22,
91 /* Bad management packet (silently discarded): */
92 CMD_STAT_BAD_PKT = 0x30,
93 /* More outstanding CQEs in CQ than new CQ size: */
cc4ac2e7
YP		 94 CMD_STAT_BAD_SIZE = 0x40,
95 /* Multi Function device support required: */
96 CMD_STAT_MULTI_FUNC_REQ = 0x50,
225c7b1f
RD		 97};
98
99enum {
100 HCR_IN_PARAM_OFFSET = 0x00,
101 HCR_IN_MODIFIER_OFFSET = 0x08,
102 HCR_OUT_PARAM_OFFSET = 0x0c,
103 HCR_TOKEN_OFFSET = 0x14,
104 HCR_STATUS_OFFSET = 0x18,
105
106 HCR_OPMOD_SHIFT = 12,
107 HCR_T_BIT = 21,
108 HCR_E_BIT = 22,
109 HCR_GO_BIT = 23
110};
111
112enum {
36ce10d3 113 GO_BIT_TIMEOUT_MSECS = 10000
225c7b1f
RD		 114};
115
b01978ca
JM		 116enum mlx4_vlan_transition {
117 MLX4_VLAN_TRANSITION_VST_VST = 0,
118 MLX4_VLAN_TRANSITION_VST_VGT = 1,
119 MLX4_VLAN_TRANSITION_VGT_VST = 2,
120 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
121};
122
123
225c7b1f
RD		 124struct mlx4_cmd_context {
125 struct completion done;
126 int result;
127 int next;
128 u64 out_param;
129 u16 token;
e8f081aa 130 u8 fw_status;
225c7b1f
RD		 131};
132
e8f081aa
YP		 133static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
134 struct mlx4_vhcr_cmd *in_vhcr);
135
ca281211
RD		 136static int mlx4_status_to_errno(u8 status)
137{
225c7b1f
RD		 138 static const int trans_table[] = {
139 [CMD_STAT_INTERNAL_ERR] = -EIO,
140 [CMD_STAT_BAD_OP] = -EPERM,
141 [CMD_STAT_BAD_PARAM] = -EINVAL,
142 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
143 [CMD_STAT_BAD_RESOURCE] = -EBADF,
144 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
145 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
146 [CMD_STAT_BAD_RES_STATE] = -EBADF,
147 [CMD_STAT_BAD_INDEX] = -EBADF,
148 [CMD_STAT_BAD_NVMEM] = -EFAULT,
899698da 149 [CMD_STAT_ICM_ERROR] = -ENFILE,
225c7b1f
RD		 150 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
151 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
152 [CMD_STAT_REG_BOUND] = -EBUSY,
153 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
154 [CMD_STAT_BAD_PKT] = -EINVAL,
155 [CMD_STAT_BAD_SIZE] = -ENOMEM,
cc4ac2e7 156 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
225c7b1f
RD		 157 };
158
159 if (status >= ARRAY_SIZE(trans_table) ||
160 (status != CMD_STAT_OK && trans_table[status] == 0))
161 return -EIO;
162
163 return trans_table[status];
164}
165
72be84f1
YP		 166static u8 mlx4_errno_to_status(int errno)
167{
168 switch (errno) {
169 case -EPERM:
170 return CMD_STAT_BAD_OP;
171 case -EINVAL:
172 return CMD_STAT_BAD_PARAM;
173 case -ENXIO:
174 return CMD_STAT_BAD_SYS_STATE;
175 case -EBUSY:
176 return CMD_STAT_RESOURCE_BUSY;
177 case -ENOMEM:
178 return CMD_STAT_EXCEED_LIM;
179 case -ENFILE:
180 return CMD_STAT_ICM_ERROR;
181 default:
182 return CMD_STAT_INTERNAL_ERR;
183 }
184}
185
f5aef5aa
YH		 186static int mlx4_internal_err_ret_value(struct mlx4_dev *dev, u16 op,
187 u8 op_modifier)
188{
189 switch (op) {
190 case MLX4_CMD_UNMAP_ICM:
191 case MLX4_CMD_UNMAP_ICM_AUX:
192 case MLX4_CMD_UNMAP_FA:
193 case MLX4_CMD_2RST_QP:
194 case MLX4_CMD_HW2SW_EQ:
195 case MLX4_CMD_HW2SW_CQ:
196 case MLX4_CMD_HW2SW_SRQ:
197 case MLX4_CMD_HW2SW_MPT:
198 case MLX4_CMD_CLOSE_HCA:
199 case MLX4_QP_FLOW_STEERING_DETACH:
200 case MLX4_CMD_FREE_RES:
201 case MLX4_CMD_CLOSE_PORT:
202 return CMD_STAT_OK;
203
204 case MLX4_CMD_QP_ATTACH:
205 /* On Detach case return success */
206 if (op_modifier == 0)
207 return CMD_STAT_OK;
208 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
209
210 default:
211 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
212 }
213}
214
215static int mlx4_closing_cmd_fatal_error(u16 op, u8 fw_status)
216{
217 /* Any error during the closing commands below is considered fatal */
218 if (op == MLX4_CMD_CLOSE_HCA ||
219 op == MLX4_CMD_HW2SW_EQ ||
220 op == MLX4_CMD_HW2SW_CQ ||
221 op == MLX4_CMD_2RST_QP ||
222 op == MLX4_CMD_HW2SW_SRQ ||
223 op == MLX4_CMD_SYNC_TPT ||
224 op == MLX4_CMD_UNMAP_ICM ||
225 op == MLX4_CMD_UNMAP_ICM_AUX ||
226 op == MLX4_CMD_UNMAP_FA)
227 return 1;
228 /* Error on MLX4_CMD_HW2SW_MPT is fatal except when fw status equals
229 * CMD_STAT_REG_BOUND.
230 * This status indicates that memory region has memory windows bound to it
231 * which may result from invalid user space usage and is not fatal.
232 */
233 if (op == MLX4_CMD_HW2SW_MPT && fw_status != CMD_STAT_REG_BOUND)
234 return 1;
235 return 0;
236}
237
238static int mlx4_cmd_reset_flow(struct mlx4_dev *dev, u16 op, u8 op_modifier,
239 int err)
240{
241 /* Only if reset flow is really active return code is based on
242 * command, otherwise current error code is returned.
243 */
244 if (mlx4_internal_err_reset) {
245 mlx4_enter_error_state(dev->persist);
246 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
247 }
248
249 return err;
250}
251
e8f081aa
YP		 252static int comm_pending(struct mlx4_dev *dev)
253{
254 struct mlx4_priv *priv = mlx4_priv(dev);
255 u32 status = readl(&priv->mfunc.comm->slave_read);
256
257 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
258}
259
0cd93027 260static int mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
e8f081aa
YP		 261{
262 struct mlx4_priv *priv = mlx4_priv(dev);
263 u32 val;
264
0cd93027
YH		 265 /* To avoid writing to unknown addresses after the device state was
266 * changed to internal error and the function was rest,
267 * check the INTERNAL_ERROR flag which is updated under
268 * device_state_mutex lock.
269 */
270 mutex_lock(&dev->persist->device_state_mutex);
271
272 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
273 mutex_unlock(&dev->persist->device_state_mutex);
274 return -EIO;
275 }
276
e8f081aa
YP		 277 priv->cmd.comm_toggle ^= 1;
278 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
279 __raw_writel((__force u32) cpu_to_be32(val),
280 &priv->mfunc.comm->slave_write);
281 mmiowb();
0cd93027
YH		 282 mutex_unlock(&dev->persist->device_state_mutex);
283 return 0;
e8f081aa
YP		 284}
285
e8f081aa
YP		 286static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
287 unsigned long timeout)
288{
289 struct mlx4_priv *priv = mlx4_priv(dev);
290 unsigned long end;
291 int err = 0;
292 int ret_from_pending = 0;
293
294 /* First, verify that the master reports correct status */
295 if (comm_pending(dev)) {
1a91de28 296 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
e8f081aa
YP		 297 priv->cmd.comm_toggle, cmd);
298 return -EAGAIN;
299 }
300
301 /* Write command */
302 down(&priv->cmd.poll_sem);
0cd93027
YH		 303 if (mlx4_comm_cmd_post(dev, cmd, param)) {
304 /* Only in case the device state is INTERNAL_ERROR,
305 * mlx4_comm_cmd_post returns with an error
306 */
307 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
308 goto out;
309 }
e8f081aa
YP		 310
311 end = msecs_to_jiffies(timeout) + jiffies;
312 while (comm_pending(dev) && time_before(jiffies, end))
313 cond_resched();
314 ret_from_pending = comm_pending(dev);
315 if (ret_from_pending) {
316 /* check if the slave is trying to boot in the middle of
317 * FLR process. The only non-zero result in the RESET command
318 * is MLX4_DELAY_RESET_SLAVE*/
319 if ((MLX4_COMM_CMD_RESET == cmd)) {
e8f081aa 320 err = MLX4_DELAY_RESET_SLAVE;
0cd93027 321 goto out;
e8f081aa 322 } else {
0cd93027
YH		 323 mlx4_warn(dev, "Communication channel command 0x%x timed out\n",
324 cmd);
325 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
e8f081aa
YP		 326 }
327 }
328
0cd93027
YH		 329 if (err)
330 mlx4_enter_error_state(dev->persist);
331out:
e8f081aa
YP		 332 up(&priv->cmd.poll_sem);
333 return err;
334}
335
0cd93027
YH		 336static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 vhcr_cmd,
337 u16 param, u16 op, unsigned long timeout)
e8f081aa
YP		 338{
339 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
340 struct mlx4_cmd_context *context;
58a3de05 341 unsigned long end;
e8f081aa
YP		 342 int err = 0;
343
344 down(&cmd->event_sem);
345
346 spin_lock(&cmd->context_lock);
347 BUG_ON(cmd->free_head < 0);
348 context = &cmd->context[cmd->free_head];
349 context->token += cmd->token_mask + 1;
350 cmd->free_head = context->next;
351 spin_unlock(&cmd->context_lock);
352
f5aef5aa 353 reinit_completion(&context->done);
e8f081aa 354
0cd93027
YH		 355 if (mlx4_comm_cmd_post(dev, vhcr_cmd, param)) {
356 /* Only in case the device state is INTERNAL_ERROR,
357 * mlx4_comm_cmd_post returns with an error
358 */
359 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
360 goto out;
361 }
e8f081aa
YP		 362
363 if (!wait_for_completion_timeout(&context->done,
364 msecs_to_jiffies(timeout))) {
0cd93027
YH		 365 mlx4_warn(dev, "communication channel command 0x%x (op=0x%x) timed out\n",
366 vhcr_cmd, op);
367 goto out_reset;
e8f081aa
YP		 368 }
369
370 err = context->result;
371 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
372 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
0cd93027
YH		 373 vhcr_cmd, context->fw_status);
374 if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
375 goto out_reset;
e8f081aa
YP		 376 }
377
58a3de05
EE		 378 /* wait for comm channel ready
379 * this is necessary for prevention the race
380 * when switching between event to polling mode
0cd93027
YH		 381 * Skipping this section in case the device is in FATAL_ERROR state,
382 * In this state, no commands are sent via the comm channel until
383 * the device has returned from reset.
58a3de05 384 */
0cd93027
YH		 385 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
386 end = msecs_to_jiffies(timeout) + jiffies;
387 while (comm_pending(dev) && time_before(jiffies, end))
388 cond_resched();
389 }
390 goto out;
58a3de05 391
0cd93027
YH		 392out_reset:
393 err = mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
394 mlx4_enter_error_state(dev->persist);
395out:
e8f081aa
YP		 396 spin_lock(&cmd->context_lock);
397 context->next = cmd->free_head;
398 cmd->free_head = context - cmd->context;
399 spin_unlock(&cmd->context_lock);
400
401 up(&cmd->event_sem);
402 return err;
403}
404
ab9c17a0 405int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
0cd93027 406 u16 op, unsigned long timeout)
e8f081aa 407{
0cd93027
YH		 408 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
409 return mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
410
e8f081aa 411 if (mlx4_priv(dev)->cmd.use_events)
0cd93027 412 return mlx4_comm_cmd_wait(dev, cmd, param, op, timeout);
e8f081aa
YP		 413 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
414}
415
225c7b1f
RD		 416static int cmd_pending(struct mlx4_dev *dev)
417{
57dbf29a
KSS		 418 u32 status;
419
872bf2fb 420 if (pci_channel_offline(dev->persist->pdev))
57dbf29a
KSS		 421 return -EIO;
422
423 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
225c7b1f
RD		 424
425 return (status & swab32(1 << HCR_GO_BIT)) ||
426 (mlx4_priv(dev)->cmd.toggle ==
427 !!(status & swab32(1 << HCR_T_BIT)));
428}
429
430static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
431 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
432 int event)
433{
434 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
435 u32 __iomem *hcr = cmd->hcr;
f5aef5aa 436 int ret = -EIO;
225c7b1f
RD		 437 unsigned long end;
438
f5aef5aa
YH		 439 mutex_lock(&dev->persist->device_state_mutex);
440 /* To avoid writing to unknown addresses after the device state was
441 * changed to internal error and the chip was reset,
442 * check the INTERNAL_ERROR flag which is updated under
443 * device_state_mutex lock.
444 */
445 if (pci_channel_offline(dev->persist->pdev) ||
446 (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)) {
57dbf29a
KSS		 447 /*
448 * Device is going through error recovery
449 * and cannot accept commands.
450 */
57dbf29a
KSS		 451 goto out;
452 }
453
225c7b1f
RD		 454 end = jiffies;
455 if (event)
36ce10d3 456 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
225c7b1f
RD		 457
458 while (cmd_pending(dev)) {
872bf2fb 459 if (pci_channel_offline(dev->persist->pdev)) {
57dbf29a
KSS		 460 /*
461 * Device is going through error recovery
462 * and cannot accept commands.
463 */
57dbf29a
KSS		 464 goto out;
465 }
466
e8f081aa
YP		 467 if (time_after_eq(jiffies, end)) {
468 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
225c7b1f 469 goto out;
e8f081aa 470 }
225c7b1f
RD		 471 cond_resched();
472 }
473
474 /*
475 * We use writel (instead of something like memcpy_toio)
476 * because writes of less than 32 bits to the HCR don't work
477 * (and some architectures such as ia64 implement memcpy_toio
478 * in terms of writeb).
479 */
480 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
481 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
482 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
483 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
484 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
485 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
486
487 /* __raw_writel may not order writes. */
488 wmb();
489
490 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
491 (cmd->toggle << HCR_T_BIT) |
492 (event ? (1 << HCR_E_BIT) : 0) |
493 (op_modifier << HCR_OPMOD_SHIFT) |
e8f081aa 494 op), hcr + 6);
2e61c646
RD		 495
496 /*
497 * Make sure that our HCR writes don't get mixed in with
498 * writes from another CPU starting a FW command.
499 */
500 mmiowb();
501
225c7b1f
RD		 502 cmd->toggle = cmd->toggle ^ 1;
503
504 ret = 0;
505
506out:
f5aef5aa
YH		 507 if (ret)
508 mlx4_warn(dev, "Could not post command 0x%x: ret=%d, in_param=0x%llx, in_mod=0x%x, op_mod=0x%x\n",
509 op, ret, in_param, in_modifier, op_modifier);
510 mutex_unlock(&dev->persist->device_state_mutex);
511
225c7b1f
RD		 512 return ret;
513}
514
e8f081aa
YP		 515static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
516 int out_is_imm, u32 in_modifier, u8 op_modifier,
517 u16 op, unsigned long timeout)
518{
519 struct mlx4_priv *priv = mlx4_priv(dev);
520 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
521 int ret;
522
f3d4c89e
RD		 523 mutex_lock(&priv->cmd.slave_cmd_mutex);
524
e8f081aa
YP		 525 vhcr->in_param = cpu_to_be64(in_param);
526 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
527 vhcr->in_modifier = cpu_to_be32(in_modifier);
528 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
529 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
530 vhcr->status = 0;
531 vhcr->flags = !!(priv->cmd.use_events) << 6;
f3d4c89e 532
e8f081aa
YP		 533 if (mlx4_is_master(dev)) {
534 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
535 if (!ret) {
536 if (out_is_imm) {
537 if (out_param)
538 *out_param =
539 be64_to_cpu(vhcr->out_param);
540 else {
1a91de28
JP		 541 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
542 op);
72be84f1 543 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 544 }
545 }
72be84f1 546 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa 547 }
0cd93027
YH		 548 if (ret &&
549 dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
550 ret = mlx4_internal_err_ret_value(dev, op, op_modifier);
e8f081aa 551 } else {
0cd93027 552 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0, op,
e8f081aa
YP		 553 MLX4_COMM_TIME + timeout);
554 if (!ret) {
555 if (out_is_imm) {
556 if (out_param)
557 *out_param =
558 be64_to_cpu(vhcr->out_param);
559 else {
1a91de28
JP		 560 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
561 op);
72be84f1 562 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 563 }
564 }
72be84f1 565 ret = mlx4_status_to_errno(vhcr->status);
0cd93027
YH		 566 } else {
567 if (dev->persist->state &
568 MLX4_DEVICE_STATE_INTERNAL_ERROR)
569 ret = mlx4_internal_err_ret_value(dev, op,
570 op_modifier);
571 else
572 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n", op);
573 }
e8f081aa 574 }
f3d4c89e
RD		 575
576 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 577 return ret;
578}
579
225c7b1f
RD		 580static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
581 int out_is_imm, u32 in_modifier, u8 op_modifier,
582 u16 op, unsigned long timeout)
583{
584 struct mlx4_priv *priv = mlx4_priv(dev);
585 void __iomem *hcr = priv->cmd.hcr;
586 int err = 0;
587 unsigned long end;
e8f081aa 588 u32 stat;
225c7b1f
RD		 589
590 down(&priv->cmd.poll_sem);
591
f5aef5aa 592 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
57dbf29a
KSS		 593 /*
594 * Device is going through error recovery
595 * and cannot accept commands.
596 */
f5aef5aa 597 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
57dbf29a
KSS		 598 goto out;
599 }
600
c05a116f
EP		 601 if (out_is_imm && !out_param) {
602 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
603 op);
604 err = -EINVAL;
605 goto out;
606 }
607
225c7b1f
RD		 608 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
609 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
610 if (err)
f5aef5aa 611 goto out_reset;
225c7b1f
RD		 612
613 end = msecs_to_jiffies(timeout) + jiffies;
57dbf29a 614 while (cmd_pending(dev) && time_before(jiffies, end)) {
872bf2fb 615 if (pci_channel_offline(dev->persist->pdev)) {
57dbf29a
KSS		 616 /*
617 * Device is going through error recovery
618 * and cannot accept commands.
619 */
620 err = -EIO;
f5aef5aa
YH		 621 goto out_reset;
622 }
623
624 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
625 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
57dbf29a
KSS		 626 goto out;
627 }
628
225c7b1f 629 cond_resched();
57dbf29a 630 }
225c7b1f
RD		 631
632 if (cmd_pending(dev)) {
674925ed
DB		 633 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
634 op);
f5aef5aa
YH		 635 err = -EIO;
636 goto out_reset;
225c7b1f
RD		 637 }
638
639 if (out_is_imm)
640 *out_param =
641 (u64) be32_to_cpu((__force __be32)
642 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
643 (u64) be32_to_cpu((__force __be32)
644 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
e8f081aa
YP		 645 stat = be32_to_cpu((__force __be32)
646 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
647 err = mlx4_status_to_errno(stat);
f5aef5aa 648 if (err) {
e8f081aa
YP		 649 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
650 op, stat);
f5aef5aa
YH		 651 if (mlx4_closing_cmd_fatal_error(op, stat))
652 goto out_reset;
653 goto out;
654 }
225c7b1f 655
f5aef5aa
YH		 656out_reset:
657 if (err)
658 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
225c7b1f
RD		 659out:
660 up(&priv->cmd.poll_sem);
661 return err;
662}
663
664void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
665{
666 struct mlx4_priv *priv = mlx4_priv(dev);
667 struct mlx4_cmd_context *context =
668 &priv->cmd.context[token & priv->cmd.token_mask];
669
670 /* previously timed out command completing at long last */
671 if (token != context->token)
672 return;
673
e8f081aa 674 context->fw_status = status;
225c7b1f
RD		 675 context->result = mlx4_status_to_errno(status);
676 context->out_param = out_param;
677
225c7b1f
RD		 678 complete(&context->done);
679}
680
681static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
682 int out_is_imm, u32 in_modifier, u8 op_modifier,
683 u16 op, unsigned long timeout)
684{
685 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
686 struct mlx4_cmd_context *context;
687 int err = 0;
688
689 down(&cmd->event_sem);
690
691 spin_lock(&cmd->context_lock);
692 BUG_ON(cmd->free_head < 0);
693 context = &cmd->context[cmd->free_head];
0981582d 694 context->token += cmd->token_mask + 1;
225c7b1f
RD		 695 cmd->free_head = context->next;
696 spin_unlock(&cmd->context_lock);
697
c05a116f
EP		 698 if (out_is_imm && !out_param) {
699 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
700 op);
701 err = -EINVAL;
702 goto out;
703 }
704
f5aef5aa 705 reinit_completion(&context->done);
225c7b1f 706
f5aef5aa
YH		 707 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
708 in_modifier, op_modifier, op, context->token, 1);
709 if (err)
710 goto out_reset;
225c7b1f 711
e8f081aa
YP		 712 if (!wait_for_completion_timeout(&context->done,
713 msecs_to_jiffies(timeout))) {
674925ed
DB		 714 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
715 op);
f5aef5aa
YH		 716 err = -EIO;
717 goto out_reset;
225c7b1f
RD		 718 }
719
720 err = context->result;
e8f081aa 721 if (err) {
1daa4303
JM		 722 /* Since we do not want to have this error message always
723 * displayed at driver start when there are ConnectX2 HCAs
724 * on the host, we deprecate the error message for this
725 * specific command/input_mod/opcode_mod/fw-status to be debug.
726 */
727 if (op == MLX4_CMD_SET_PORT && in_modifier == 1 &&
728 op_modifier == 0 && context->fw_status == CMD_STAT_BAD_SIZE)
729 mlx4_dbg(dev, "command 0x%x failed: fw status = 0x%x\n",
730 op, context->fw_status);
731 else
732 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
733 op, context->fw_status);
f5aef5aa
YH		 734 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
735 err = mlx4_internal_err_ret_value(dev, op, op_modifier);
736 else if (mlx4_closing_cmd_fatal_error(op, context->fw_status))
737 goto out_reset;
738
225c7b1f 739 goto out;
e8f081aa 740 }
225c7b1f
RD		 741
742 if (out_is_imm)
743 *out_param = context->out_param;
744
f5aef5aa
YH		 745out_reset:
746 if (err)
747 err = mlx4_cmd_reset_flow(dev, op, op_modifier, err);
225c7b1f
RD		 748out:
749 spin_lock(&cmd->context_lock);
750 context->next = cmd->free_head;
751 cmd->free_head = context - cmd->context;
752 spin_unlock(&cmd->context_lock);
753
754 up(&cmd->event_sem);
755 return err;
756}
757
758int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
759 int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50 760 u16 op, unsigned long timeout, int native)
225c7b1f 761{
872bf2fb 762 if (pci_channel_offline(dev->persist->pdev))
f5aef5aa 763 return mlx4_cmd_reset_flow(dev, op, op_modifier, -EIO);
57dbf29a 764
e8f081aa 765 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
f5aef5aa
YH		 766 if (dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR)
767 return mlx4_internal_err_ret_value(dev, op,
768 op_modifier);
e8f081aa
YP		 769 if (mlx4_priv(dev)->cmd.use_events)
770 return mlx4_cmd_wait(dev, in_param, out_param,
771 out_is_imm, in_modifier,
772 op_modifier, op, timeout);
773 else
774 return mlx4_cmd_poll(dev, in_param, out_param,
775 out_is_imm, in_modifier,
776 op_modifier, op, timeout);
777 }
778 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
779 in_modifier, op_modifier, op, timeout);
225c7b1f
RD		 780}
781EXPORT_SYMBOL_GPL(__mlx4_cmd);
782
e8f081aa 783
55ad3592 784int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
e8f081aa
YP		 785{
786 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
787 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
788}
789
790static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
791 int slave, u64 slave_addr,
792 int size, int is_read)
793{
794 u64 in_param;
795 u64 out_param;
796
797 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
798 (slave & ~0x7f) | (size & 0xff)) {
1a91de28
JP		 799 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
800 slave_addr, master_addr, slave, size);
e8f081aa
YP		 801 return -EINVAL;
802 }
803
804 if (is_read) {
805 in_param = (u64) slave | slave_addr;
806 out_param = (u64) dev->caps.function | master_addr;
807 } else {
808 in_param = (u64) dev->caps.function | master_addr;
809 out_param = (u64) slave | slave_addr;
810 }
811
812 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
813 MLX4_CMD_ACCESS_MEM,
814 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
815}
816
0a9a0188
JM		 817static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
818 struct mlx4_cmd_mailbox *inbox,
819 struct mlx4_cmd_mailbox *outbox)
820{
821 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
822 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
823 int err;
824 int i;
825
826 if (index & 0x1f)
827 return -EINVAL;
828
829 in_mad->attr_mod = cpu_to_be32(index / 32);
830
831 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
832 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
833 MLX4_CMD_NATIVE);
834 if (err)
835 return err;
836
837 for (i = 0; i < 32; ++i)
838 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
839
840 return err;
841}
842
843static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
844 struct mlx4_cmd_mailbox *inbox,
845 struct mlx4_cmd_mailbox *outbox)
846{
847 int i;
848 int err;
849
850 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
851 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
852 if (err)
853 return err;
854 }
855
856 return 0;
857}
858#define PORT_CAPABILITY_LOCATION_IN_SMP 20
859#define PORT_STATE_OFFSET 32
860
861static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
862{
a0c64a17
JM		 863 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
864 return IB_PORT_ACTIVE;
865 else
866 return IB_PORT_DOWN;
0a9a0188
JM		 867}
868
869static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
870 struct mlx4_vhcr *vhcr,
871 struct mlx4_cmd_mailbox *inbox,
872 struct mlx4_cmd_mailbox *outbox,
873 struct mlx4_cmd_info *cmd)
874{
875 struct ib_smp *smp = inbox->buf;
876 u32 index;
877 u8 port;
97982f5a 878 u8 opcode_modifier;
0a9a0188
JM		 879 u16 *table;
880 int err;
881 int vidx, pidx;
97982f5a 882 int network_view;
0a9a0188
JM		 883 struct mlx4_priv *priv = mlx4_priv(dev);
884 struct ib_smp *outsmp = outbox->buf;
885 __be16 *outtab = (__be16 *)(outsmp->data);
886 __be32 slave_cap_mask;
afa8fd1d 887 __be64 slave_node_guid;
97982f5a 888
0a9a0188
JM		 889 port = vhcr->in_modifier;
890
97982f5a
JM		 891 /* network-view bit is for driver use only, and should not be passed to FW */
892 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
893 network_view = !!(vhcr->op_modifier & 0x8);
894
0a9a0188
JM		 895 if (smp->base_version == 1 &&
896 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
897 smp->class_version == 1) {
97982f5a
JM		 898 /* host view is paravirtualized */
899 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
0a9a0188
JM		 900 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
901 index = be32_to_cpu(smp->attr_mod);
902 if (port < 1 || port > dev->caps.num_ports)
903 return -EINVAL;
19ab574f
MB		 904 table = kcalloc((dev->caps.pkey_table_len[port] / 32) + 1,
905 sizeof(*table) * 32, GFP_KERNEL);
906
0a9a0188
JM		 907 if (!table)
908 return -ENOMEM;
909 /* need to get the full pkey table because the paravirtualized
910 * pkeys may be scattered among several pkey blocks.
911 */
912 err = get_full_pkey_table(dev, port, table, inbox, outbox);
913 if (!err) {
914 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
915 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
916 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
917 }
918 }
919 kfree(table);
920 return err;
921 }
922 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
923 /*get the slave specific caps:*/
924 /*do the command */
925 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 926 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 927 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
928 /* modify the response for slaves */
929 if (!err && slave != mlx4_master_func_num(dev)) {
930 u8 *state = outsmp->data + PORT_STATE_OFFSET;
931
932 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
933 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
934 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
935 }
936 return err;
937 }
938 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
939 /* compute slave's gid block */
940 smp->attr_mod = cpu_to_be32(slave / 8);
941 /* execute cmd */
942 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 943 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 944 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
945 if (!err) {
946 /* if needed, move slave gid to index 0 */
947 if (slave % 8)
948 memcpy(outsmp->data,
949 outsmp->data + (slave % 8) * 8, 8);
950 /* delete all other gids */
951 memset(outsmp->data + 8, 0, 56);
952 }
953 return err;
954 }
afa8fd1d
JM		 955 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
956 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 957 vhcr->in_modifier, opcode_modifier,
afa8fd1d
JM		 958 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
959 if (!err) {
960 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
961 memcpy(outsmp->data + 12, &slave_node_guid, 8);
962 }
963 return err;
964 }
0a9a0188
JM		 965 }
966 }
97982f5a
JM		 967
968 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
969 * These are the MADs used by ib verbs (such as ib_query_gids).
970 */
0a9a0188 971 if (slave != mlx4_master_func_num(dev) &&
97982f5a
JM		 972 !mlx4_vf_smi_enabled(dev, slave, port)) {
973 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
974 smp->method == IB_MGMT_METHOD_GET) || network_view) {
975 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
976 slave, smp->method, smp->mgmt_class,
977 network_view ? "Network" : "Host",
978 be16_to_cpu(smp->attr_id));
979 return -EPERM;
980 }
0a9a0188 981 }
97982f5a 982
0a9a0188 983 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 984 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 985 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
986}
987
b7475794 988static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
fe6f700d
YP		 989 struct mlx4_vhcr *vhcr,
990 struct mlx4_cmd_mailbox *inbox,
991 struct mlx4_cmd_mailbox *outbox,
992 struct mlx4_cmd_info *cmd)
993{
994 return -EPERM;
995}
996
e8f081aa
YP		 997int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
998 struct mlx4_vhcr *vhcr,
999 struct mlx4_cmd_mailbox *inbox,
1000 struct mlx4_cmd_mailbox *outbox,
1001 struct mlx4_cmd_info *cmd)
1002{
1003 u64 in_param;
1004 u64 out_param;
1005 int err;
1006
1007 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
1008 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
1009 if (cmd->encode_slave_id) {
1010 in_param &= 0xffffffffffffff00ll;
1011 in_param |= slave;
1012 }
1013
1014 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
1015 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
1016 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1017
1018 if (cmd->out_is_imm)
1019 vhcr->out_param = out_param;
1020
1021 return err;
1022}
1023
1024static struct mlx4_cmd_info cmd_info[] = {
1025 {
1026 .opcode = MLX4_CMD_QUERY_FW,
1027 .has_inbox = false,
1028 .has_outbox = true,
1029 .out_is_imm = false,
1030 .encode_slave_id = false,
1031 .verify = NULL,
b91cb3eb 1032 .wrapper = mlx4_QUERY_FW_wrapper
e8f081aa
YP		 1033 },
1034 {
1035 .opcode = MLX4_CMD_QUERY_HCA,
1036 .has_inbox = false,
1037 .has_outbox = true,
1038 .out_is_imm = false,
1039 .encode_slave_id = false,
1040 .verify = NULL,
1041 .wrapper = NULL
1042 },
1043 {
1044 .opcode = MLX4_CMD_QUERY_DEV_CAP,
1045 .has_inbox = false,
1046 .has_outbox = true,
1047 .out_is_imm = false,
1048 .encode_slave_id = false,
1049 .verify = NULL,
b91cb3eb 1050 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
e8f081aa 1051 },
c82e9aa0
EC		 1052 {
1053 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
1054 .has_inbox = false,
1055 .has_outbox = true,
1056 .out_is_imm = false,
1057 .encode_slave_id = false,
1058 .verify = NULL,
1059 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
1060 },
1061 {
1062 .opcode = MLX4_CMD_QUERY_ADAPTER,
1063 .has_inbox = false,
1064 .has_outbox = true,
1065 .out_is_imm = false,
1066 .encode_slave_id = false,
1067 .verify = NULL,
1068 .wrapper = NULL
1069 },
1070 {
1071 .opcode = MLX4_CMD_INIT_PORT,
1072 .has_inbox = false,
1073 .has_outbox = false,
1074 .out_is_imm = false,
1075 .encode_slave_id = false,
1076 .verify = NULL,
1077 .wrapper = mlx4_INIT_PORT_wrapper
1078 },
1079 {
1080 .opcode = MLX4_CMD_CLOSE_PORT,
1081 .has_inbox = false,
1082 .has_outbox = false,
1083 .out_is_imm = false,
1084 .encode_slave_id = false,
1085 .verify = NULL,
1086 .wrapper = mlx4_CLOSE_PORT_wrapper
1087 },
1088 {
1089 .opcode = MLX4_CMD_QUERY_PORT,
1090 .has_inbox = false,
1091 .has_outbox = true,
1092 .out_is_imm = false,
1093 .encode_slave_id = false,
1094 .verify = NULL,
1095 .wrapper = mlx4_QUERY_PORT_wrapper
1096 },
ffe455ad
EE		 1097 {
1098 .opcode = MLX4_CMD_SET_PORT,
1099 .has_inbox = true,
1100 .has_outbox = false,
1101 .out_is_imm = false,
1102 .encode_slave_id = false,
1103 .verify = NULL,
1104 .wrapper = mlx4_SET_PORT_wrapper
1105 },
c82e9aa0
EC		 1106 {
1107 .opcode = MLX4_CMD_MAP_EQ,
1108 .has_inbox = false,
1109 .has_outbox = false,
1110 .out_is_imm = false,
1111 .encode_slave_id = false,
1112 .verify = NULL,
1113 .wrapper = mlx4_MAP_EQ_wrapper
1114 },
1115 {
1116 .opcode = MLX4_CMD_SW2HW_EQ,
1117 .has_inbox = true,
1118 .has_outbox = false,
1119 .out_is_imm = false,
1120 .encode_slave_id = true,
1121 .verify = NULL,
1122 .wrapper = mlx4_SW2HW_EQ_wrapper
1123 },
1124 {
1125 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
1126 .has_inbox = false,
1127 .has_outbox = false,
1128 .out_is_imm = false,
1129 .encode_slave_id = false,
1130 .verify = NULL,
1131 .wrapper = NULL
1132 },
1133 {
1134 .opcode = MLX4_CMD_NOP,
1135 .has_inbox = false,
1136 .has_outbox = false,
1137 .out_is_imm = false,
1138 .encode_slave_id = false,
1139 .verify = NULL,
1140 .wrapper = NULL
1141 },
d18f141a
OG		 1142 {
1143 .opcode = MLX4_CMD_CONFIG_DEV,
1144 .has_inbox = false,
d475c95b 1145 .has_outbox = true,
d18f141a
OG		 1146 .out_is_imm = false,
1147 .encode_slave_id = false,
1148 .verify = NULL,
d475c95b 1149 .wrapper = mlx4_CONFIG_DEV_wrapper
d18f141a 1150 },
c82e9aa0
EC		 1151 {
1152 .opcode = MLX4_CMD_ALLOC_RES,
1153 .has_inbox = false,
1154 .has_outbox = false,
1155 .out_is_imm = true,
1156 .encode_slave_id = false,
1157 .verify = NULL,
1158 .wrapper = mlx4_ALLOC_RES_wrapper
1159 },
1160 {
1161 .opcode = MLX4_CMD_FREE_RES,
1162 .has_inbox = false,
1163 .has_outbox = false,
1164 .out_is_imm = false,
1165 .encode_slave_id = false,
1166 .verify = NULL,
1167 .wrapper = mlx4_FREE_RES_wrapper
1168 },
1169 {
1170 .opcode = MLX4_CMD_SW2HW_MPT,
1171 .has_inbox = true,
1172 .has_outbox = false,
1173 .out_is_imm = false,
1174 .encode_slave_id = true,
1175 .verify = NULL,
1176 .wrapper = mlx4_SW2HW_MPT_wrapper
1177 },
1178 {
1179 .opcode = MLX4_CMD_QUERY_MPT,
1180 .has_inbox = false,
1181 .has_outbox = true,
1182 .out_is_imm = false,
1183 .encode_slave_id = false,
1184 .verify = NULL,
1185 .wrapper = mlx4_QUERY_MPT_wrapper
1186 },
1187 {
1188 .opcode = MLX4_CMD_HW2SW_MPT,
1189 .has_inbox = false,
1190 .has_outbox = false,
1191 .out_is_imm = false,
1192 .encode_slave_id = false,
1193 .verify = NULL,
1194 .wrapper = mlx4_HW2SW_MPT_wrapper
1195 },
1196 {
1197 .opcode = MLX4_CMD_READ_MTT,
1198 .has_inbox = false,
1199 .has_outbox = true,
1200 .out_is_imm = false,
1201 .encode_slave_id = false,
1202 .verify = NULL,
1203 .wrapper = NULL
1204 },
1205 {
1206 .opcode = MLX4_CMD_WRITE_MTT,
1207 .has_inbox = true,
1208 .has_outbox = false,
1209 .out_is_imm = false,
1210 .encode_slave_id = false,
1211 .verify = NULL,
1212 .wrapper = mlx4_WRITE_MTT_wrapper
1213 },
1214 {
1215 .opcode = MLX4_CMD_SYNC_TPT,
1216 .has_inbox = true,
1217 .has_outbox = false,
1218 .out_is_imm = false,
1219 .encode_slave_id = false,
1220 .verify = NULL,
1221 .wrapper = NULL
1222 },
1223 {
1224 .opcode = MLX4_CMD_HW2SW_EQ,
1225 .has_inbox = false,
30a5da5b 1226 .has_outbox = false,
c82e9aa0
EC		 1227 .out_is_imm = false,
1228 .encode_slave_id = true,
1229 .verify = NULL,
1230 .wrapper = mlx4_HW2SW_EQ_wrapper
1231 },
1232 {
1233 .opcode = MLX4_CMD_QUERY_EQ,
1234 .has_inbox = false,
1235 .has_outbox = true,
1236 .out_is_imm = false,
1237 .encode_slave_id = true,
1238 .verify = NULL,
1239 .wrapper = mlx4_QUERY_EQ_wrapper
1240 },
1241 {
1242 .opcode = MLX4_CMD_SW2HW_CQ,
1243 .has_inbox = true,
1244 .has_outbox = false,
1245 .out_is_imm = false,
1246 .encode_slave_id = true,
1247 .verify = NULL,
1248 .wrapper = mlx4_SW2HW_CQ_wrapper
1249 },
1250 {
1251 .opcode = MLX4_CMD_HW2SW_CQ,
1252 .has_inbox = false,
1253 .has_outbox = false,
1254 .out_is_imm = false,
1255 .encode_slave_id = false,
1256 .verify = NULL,
1257 .wrapper = mlx4_HW2SW_CQ_wrapper
1258 },
1259 {
1260 .opcode = MLX4_CMD_QUERY_CQ,
1261 .has_inbox = false,
1262 .has_outbox = true,
1263 .out_is_imm = false,
1264 .encode_slave_id = false,
1265 .verify = NULL,
1266 .wrapper = mlx4_QUERY_CQ_wrapper
1267 },
1268 {
1269 .opcode = MLX4_CMD_MODIFY_CQ,
1270 .has_inbox = true,
1271 .has_outbox = false,
1272 .out_is_imm = true,
1273 .encode_slave_id = false,
1274 .verify = NULL,
1275 .wrapper = mlx4_MODIFY_CQ_wrapper
1276 },
1277 {
1278 .opcode = MLX4_CMD_SW2HW_SRQ,
1279 .has_inbox = true,
1280 .has_outbox = false,
1281 .out_is_imm = false,
1282 .encode_slave_id = true,
1283 .verify = NULL,
1284 .wrapper = mlx4_SW2HW_SRQ_wrapper
1285 },
1286 {
1287 .opcode = MLX4_CMD_HW2SW_SRQ,
1288 .has_inbox = false,
1289 .has_outbox = false,
1290 .out_is_imm = false,
1291 .encode_slave_id = false,
1292 .verify = NULL,
1293 .wrapper = mlx4_HW2SW_SRQ_wrapper
1294 },
1295 {
1296 .opcode = MLX4_CMD_QUERY_SRQ,
1297 .has_inbox = false,
1298 .has_outbox = true,
1299 .out_is_imm = false,
1300 .encode_slave_id = false,
1301 .verify = NULL,
1302 .wrapper = mlx4_QUERY_SRQ_wrapper
1303 },
1304 {
1305 .opcode = MLX4_CMD_ARM_SRQ,
1306 .has_inbox = false,
1307 .has_outbox = false,
1308 .out_is_imm = false,
1309 .encode_slave_id = false,
1310 .verify = NULL,
1311 .wrapper = mlx4_ARM_SRQ_wrapper
1312 },
1313 {
1314 .opcode = MLX4_CMD_RST2INIT_QP,
1315 .has_inbox = true,
1316 .has_outbox = false,
1317 .out_is_imm = false,
1318 .encode_slave_id = true,
1319 .verify = NULL,
1320 .wrapper = mlx4_RST2INIT_QP_wrapper
1321 },
1322 {
1323 .opcode = MLX4_CMD_INIT2INIT_QP,
1324 .has_inbox = true,
1325 .has_outbox = false,
1326 .out_is_imm = false,
1327 .encode_slave_id = false,
1328 .verify = NULL,
54679e14 1329 .wrapper = mlx4_INIT2INIT_QP_wrapper
c82e9aa0
EC		 1330 },
1331 {
1332 .opcode = MLX4_CMD_INIT2RTR_QP,
1333 .has_inbox = true,
1334 .has_outbox = false,
1335 .out_is_imm = false,
1336 .encode_slave_id = false,
1337 .verify = NULL,
1338 .wrapper = mlx4_INIT2RTR_QP_wrapper
1339 },
1340 {
1341 .opcode = MLX4_CMD_RTR2RTS_QP,
1342 .has_inbox = true,
1343 .has_outbox = false,
1344 .out_is_imm = false,
1345 .encode_slave_id = false,
1346 .verify = NULL,
54679e14 1347 .wrapper = mlx4_RTR2RTS_QP_wrapper
c82e9aa0
EC		 1348 },
1349 {
1350 .opcode = MLX4_CMD_RTS2RTS_QP,
1351 .has_inbox = true,
1352 .has_outbox = false,
1353 .out_is_imm = false,
1354 .encode_slave_id = false,
1355 .verify = NULL,
54679e14 1356 .wrapper = mlx4_RTS2RTS_QP_wrapper
c82e9aa0
EC		 1357 },
1358 {
1359 .opcode = MLX4_CMD_SQERR2RTS_QP,
1360 .has_inbox = true,
1361 .has_outbox = false,
1362 .out_is_imm = false,
1363 .encode_slave_id = false,
1364 .verify = NULL,
54679e14 1365 .wrapper = mlx4_SQERR2RTS_QP_wrapper
c82e9aa0
EC		 1366 },
1367 {
1368 .opcode = MLX4_CMD_2ERR_QP,
1369 .has_inbox = false,
1370 .has_outbox = false,
1371 .out_is_imm = false,
1372 .encode_slave_id = false,
1373 .verify = NULL,
1374 .wrapper = mlx4_GEN_QP_wrapper
1375 },
1376 {
1377 .opcode = MLX4_CMD_RTS2SQD_QP,
1378 .has_inbox = false,
1379 .has_outbox = false,
1380 .out_is_imm = false,
1381 .encode_slave_id = false,
1382 .verify = NULL,
1383 .wrapper = mlx4_GEN_QP_wrapper
1384 },
1385 {
1386 .opcode = MLX4_CMD_SQD2SQD_QP,
1387 .has_inbox = true,
1388 .has_outbox = false,
1389 .out_is_imm = false,
1390 .encode_slave_id = false,
1391 .verify = NULL,
54679e14 1392 .wrapper = mlx4_SQD2SQD_QP_wrapper
c82e9aa0
EC		 1393 },
1394 {
1395 .opcode = MLX4_CMD_SQD2RTS_QP,
1396 .has_inbox = true,
1397 .has_outbox = false,
1398 .out_is_imm = false,
1399 .encode_slave_id = false,
1400 .verify = NULL,
54679e14 1401 .wrapper = mlx4_SQD2RTS_QP_wrapper
c82e9aa0
EC		 1402 },
1403 {
1404 .opcode = MLX4_CMD_2RST_QP,
1405 .has_inbox = false,
1406 .has_outbox = false,
1407 .out_is_imm = false,
1408 .encode_slave_id = false,
1409 .verify = NULL,
1410 .wrapper = mlx4_2RST_QP_wrapper
1411 },
1412 {
1413 .opcode = MLX4_CMD_QUERY_QP,
1414 .has_inbox = false,
1415 .has_outbox = true,
1416 .out_is_imm = false,
1417 .encode_slave_id = false,
1418 .verify = NULL,
1419 .wrapper = mlx4_GEN_QP_wrapper
1420 },
1421 {
1422 .opcode = MLX4_CMD_SUSPEND_QP,
1423 .has_inbox = false,
1424 .has_outbox = false,
1425 .out_is_imm = false,
1426 .encode_slave_id = false,
1427 .verify = NULL,
1428 .wrapper = mlx4_GEN_QP_wrapper
1429 },
1430 {
1431 .opcode = MLX4_CMD_UNSUSPEND_QP,
1432 .has_inbox = false,
1433 .has_outbox = false,
1434 .out_is_imm = false,
1435 .encode_slave_id = false,
1436 .verify = NULL,
1437 .wrapper = mlx4_GEN_QP_wrapper
1438 },
b01978ca
JM		 1439 {
1440 .opcode = MLX4_CMD_UPDATE_QP,
ce8d9e0d 1441 .has_inbox = true,
b01978ca
JM		 1442 .has_outbox = false,
1443 .out_is_imm = false,
1444 .encode_slave_id = false,
1445 .verify = NULL,
ce8d9e0d 1446 .wrapper = mlx4_UPDATE_QP_wrapper
b01978ca 1447 },
fe6f700d
YP		 1448 {
1449 .opcode = MLX4_CMD_GET_OP_REQ,
1450 .has_inbox = false,
1451 .has_outbox = false,
1452 .out_is_imm = false,
1453 .encode_slave_id = false,
1454 .verify = NULL,
b7475794 1455 .wrapper = mlx4_CMD_EPERM_wrapper,
fe6f700d 1456 },
0a9a0188
JM		 1457 {
1458 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1459 .has_inbox = false,
1460 .has_outbox = false,
1461 .out_is_imm = false,
1462 .encode_slave_id = false,
1463 .verify = NULL, /* XXX verify: only demux can do this */
1464 .wrapper = NULL
1465 },
1466 {
1467 .opcode = MLX4_CMD_MAD_IFC,
1468 .has_inbox = true,
1469 .has_outbox = true,
1470 .out_is_imm = false,
1471 .encode_slave_id = false,
1472 .verify = NULL,
1473 .wrapper = mlx4_MAD_IFC_wrapper
1474 },
114840c3
JM		 1475 {
1476 .opcode = MLX4_CMD_MAD_DEMUX,
1477 .has_inbox = false,
1478 .has_outbox = false,
1479 .out_is_imm = false,
1480 .encode_slave_id = false,
1481 .verify = NULL,
1482 .wrapper = mlx4_CMD_EPERM_wrapper
1483 },
c82e9aa0
EC		 1484 {
1485 .opcode = MLX4_CMD_QUERY_IF_STAT,
1486 .has_inbox = false,
1487 .has_outbox = true,
1488 .out_is_imm = false,
1489 .encode_slave_id = false,
1490 .verify = NULL,
1491 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1492 },
adbc7ac5
SM		 1493 {
1494 .opcode = MLX4_CMD_ACCESS_REG,
1495 .has_inbox = true,
1496 .has_outbox = true,
1497 .out_is_imm = false,
1498 .encode_slave_id = false,
1499 .verify = NULL,
6e806699 1500 .wrapper = mlx4_ACCESS_REG_wrapper,
adbc7ac5 1501 },
c82e9aa0
EC		 1502 /* Native multicast commands are not available for guests */
1503 {
1504 .opcode = MLX4_CMD_QP_ATTACH,
1505 .has_inbox = true,
1506 .has_outbox = false,
1507 .out_is_imm = false,
1508 .encode_slave_id = false,
1509 .verify = NULL,
1510 .wrapper = mlx4_QP_ATTACH_wrapper
1511 },
0ec2c0f8
EE		 1512 {
1513 .opcode = MLX4_CMD_PROMISC,
1514 .has_inbox = false,
1515 .has_outbox = false,
1516 .out_is_imm = false,
1517 .encode_slave_id = false,
1518 .verify = NULL,
1519 .wrapper = mlx4_PROMISC_wrapper
1520 },
ffe455ad
EE		 1521 /* Ethernet specific commands */
1522 {
1523 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1524 .has_inbox = true,
1525 .has_outbox = false,
1526 .out_is_imm = false,
1527 .encode_slave_id = false,
1528 .verify = NULL,
1529 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1530 },
1531 {
1532 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1533 .has_inbox = false,
1534 .has_outbox = false,
1535 .out_is_imm = false,
1536 .encode_slave_id = false,
1537 .verify = NULL,
1538 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1539 },
1540 {
1541 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1542 .has_inbox = false,
1543 .has_outbox = true,
1544 .out_is_imm = false,
1545 .encode_slave_id = false,
1546 .verify = NULL,
1547 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1548 },
c82e9aa0
EC		 1549 {
1550 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1551 .has_inbox = false,
1552 .has_outbox = false,
1553 .out_is_imm = false,
1554 .encode_slave_id = false,
1555 .verify = NULL,
1556 .wrapper = NULL
1557 },
8fcfb4db
HHZ		 1558 /* flow steering commands */
1559 {
1560 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1561 .has_inbox = true,
1562 .has_outbox = false,
1563 .out_is_imm = true,
1564 .encode_slave_id = false,
1565 .verify = NULL,
1566 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1567 },
1568 {
1569 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1570 .has_inbox = false,
1571 .has_outbox = false,
1572 .out_is_imm = false,
1573 .encode_slave_id = false,
1574 .verify = NULL,
1575 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1576 },
4de65803
MB		 1577 {
1578 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1579 .has_inbox = false,
1580 .has_outbox = false,
1581 .out_is_imm = false,
1582 .encode_slave_id = false,
1583 .verify = NULL,
b7475794 1584 .wrapper = mlx4_CMD_EPERM_wrapper
4de65803 1585 },
e8f081aa
YP		 1586};
1587
1588static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1589 struct mlx4_vhcr_cmd *in_vhcr)
1590{
1591 struct mlx4_priv *priv = mlx4_priv(dev);
1592 struct mlx4_cmd_info *cmd = NULL;
1593 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1594 struct mlx4_vhcr *vhcr;
1595 struct mlx4_cmd_mailbox *inbox = NULL;
1596 struct mlx4_cmd_mailbox *outbox = NULL;
1597 u64 in_param;
1598 u64 out_param;
1599 int ret = 0;
1600 int i;
72be84f1 1601 int err = 0;
e8f081aa
YP		 1602
1603 /* Create sw representation of Virtual HCR */
1604 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1605 if (!vhcr)
1606 return -ENOMEM;
1607
1608 /* DMA in the vHCR */
1609 if (!in_vhcr) {
1610 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1611 priv->mfunc.master.slave_state[slave].vhcr_dma,
1612 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1613 MLX4_ACCESS_MEM_ALIGN), 1);
1614 if (ret) {
0cd93027
YH		 1615 if (!(dev->persist->state &
1616 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1617 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1618 __func__, ret);
e8f081aa
YP		 1619 kfree(vhcr);
1620 return ret;
1621 }
1622 }
1623
1624 /* Fill SW VHCR fields */
1625 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1626 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1627 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1628 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1629 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1630 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1631 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1632
1633 /* Lookup command */
1634 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1635 if (vhcr->op == cmd_info[i].opcode) {
1636 cmd = &cmd_info[i];
1637 break;
1638 }
1639 }
1640 if (!cmd) {
1641 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1642 vhcr->op, slave);
72be84f1 1643 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 1644 goto out_status;
1645 }
1646
1647 /* Read inbox */
1648 if (cmd->has_inbox) {
1649 vhcr->in_param &= INBOX_MASK;
1650 inbox = mlx4_alloc_cmd_mailbox(dev);
1651 if (IS_ERR(inbox)) {
72be84f1 1652 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1653 inbox = NULL;
72be84f1 1654 goto out_status;
e8f081aa
YP		 1655 }
1656
0cd93027
YH		 1657 ret = mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1658 vhcr->in_param,
1659 MLX4_MAILBOX_SIZE, 1);
1660 if (ret) {
1661 if (!(dev->persist->state &
1662 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1663 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1664 __func__, cmd->opcode);
72be84f1
YP		 1665 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1666 goto out_status;
e8f081aa
YP		 1667 }
1668 }
1669
1670 /* Apply permission and bound checks if applicable */
1671 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1a91de28
JP		 1672 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1673 vhcr->op, slave, vhcr->in_modifier);
72be84f1 1674 vhcr_cmd->status = CMD_STAT_BAD_OP;
e8f081aa
YP		 1675 goto out_status;
1676 }
1677
1678 /* Allocate outbox */
1679 if (cmd->has_outbox) {
1680 outbox = mlx4_alloc_cmd_mailbox(dev);
1681 if (IS_ERR(outbox)) {
72be84f1 1682 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1683 outbox = NULL;
72be84f1 1684 goto out_status;
e8f081aa
YP		 1685 }
1686 }
1687
1688 /* Execute the command! */
1689 if (cmd->wrapper) {
72be84f1
YP		 1690 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1691 cmd);
e8f081aa
YP		 1692 if (cmd->out_is_imm)
1693 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1694 } else {
1695 in_param = cmd->has_inbox ? (u64) inbox->dma :
1696 vhcr->in_param;
1697 out_param = cmd->has_outbox ? (u64) outbox->dma :
1698 vhcr->out_param;
72be84f1
YP		 1699 err = __mlx4_cmd(dev, in_param, &out_param,
1700 cmd->out_is_imm, vhcr->in_modifier,
1701 vhcr->op_modifier, vhcr->op,
1702 MLX4_CMD_TIME_CLASS_A,
1703 MLX4_CMD_NATIVE);
e8f081aa
YP		 1704
1705 if (cmd->out_is_imm) {
1706 vhcr->out_param = out_param;
1707 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1708 }
1709 }
1710
72be84f1 1711 if (err) {
0cd93027
YH		 1712 if (!(dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR))
1713 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
1714 vhcr->op, slave, vhcr->errno, err);
72be84f1
YP		 1715 vhcr_cmd->status = mlx4_errno_to_status(err);
1716 goto out_status;
1717 }
1718
1719
e8f081aa 1720 /* Write outbox if command completed successfully */
72be84f1 1721 if (cmd->has_outbox && !vhcr_cmd->status) {
e8f081aa
YP		 1722 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1723 vhcr->out_param,
1724 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1725 if (ret) {
72be84f1
YP		 1726 /* If we failed to write back the outbox after the
1727 *command was successfully executed, we must fail this
1728 * slave, as it is now in undefined state */
0cd93027
YH		 1729 if (!(dev->persist->state &
1730 MLX4_DEVICE_STATE_INTERNAL_ERROR))
1731 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
e8f081aa
YP		 1732 goto out;
1733 }
1734 }
1735
1736out_status:
1737 /* DMA back vhcr result */
1738 if (!in_vhcr) {
1739 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1740 priv->mfunc.master.slave_state[slave].vhcr_dma,
1741 ALIGN(sizeof(struct mlx4_vhcr),
1742 MLX4_ACCESS_MEM_ALIGN),
1743 MLX4_CMD_WRAPPED);
1744 if (ret)
1745 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1746 __func__);
1747 else if (vhcr->e_bit &&
1748 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1a91de28
JP		 1749 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1750 slave);
e8f081aa
YP		 1751 }
1752
1753out:
1754 kfree(vhcr);
1755 mlx4_free_cmd_mailbox(dev, inbox);
1756 mlx4_free_cmd_mailbox(dev, outbox);
1757 return ret;
1758}
1759
f094668c 1760static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
b01978ca
JM		 1761 int slave, int port)
1762{
1763 struct mlx4_vport_oper_state *vp_oper;
1764 struct mlx4_vport_state *vp_admin;
1765 struct mlx4_vf_immed_vlan_work *work;
0a6eac24 1766 struct mlx4_dev *dev = &(priv->dev);
b01978ca
JM		 1767 int err;
1768 int admin_vlan_ix = NO_INDX;
1769
1770 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1771 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1772
1773 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
0a6eac24
RE		 1774 vp_oper->state.default_qos == vp_admin->default_qos &&
1775 vp_oper->state.link_state == vp_admin->link_state)
b01978ca
JM		 1776 return 0;
1777
0a6eac24 1778 if (!(priv->mfunc.master.slave_state[slave].active &&
f0f829bf 1779 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
0a6eac24
RE		 1780 /* even if the UPDATE_QP command isn't supported, we still want
1781 * to set this VF link according to the admin directive
1782 */
1783 vp_oper->state.link_state = vp_admin->link_state;
1784 return -1;
1785 }
1786
1787 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1788 slave, port);
1a91de28
JP		 1789 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1790 vp_admin->default_vlan, vp_admin->default_qos,
1791 vp_admin->link_state);
0a6eac24 1792
b01978ca
JM		 1793 work = kzalloc(sizeof(*work), GFP_KERNEL);
1794 if (!work)
1795 return -ENOMEM;
1796
1797 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
f0f829bf
RE		 1798 if (MLX4_VGT != vp_admin->default_vlan) {
1799 err = __mlx4_register_vlan(&priv->dev, port,
1800 vp_admin->default_vlan,
1801 &admin_vlan_ix);
1802 if (err) {
1803 kfree(work);
1a91de28 1804 mlx4_warn(&priv->dev,
f0f829bf
RE		 1805 "No vlan resources slave %d, port %d\n",
1806 slave, port);
1807 return err;
1808 }
1809 } else {
1810 admin_vlan_ix = NO_INDX;
b01978ca
JM		 1811 }
1812 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1a91de28 1813 mlx4_dbg(&priv->dev,
b01978ca
JM		 1814 "alloc vlan %d idx %d slave %d port %d\n",
1815 (int)(vp_admin->default_vlan),
1816 admin_vlan_ix, slave, port);
1817 }
1818
1819 /* save original vlan ix and vlan id */
1820 work->orig_vlan_id = vp_oper->state.default_vlan;
1821 work->orig_vlan_ix = vp_oper->vlan_idx;
1822
1823 /* handle new qos */
1824 if (vp_oper->state.default_qos != vp_admin->default_qos)
1825 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1826
1827 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1828 vp_oper->vlan_idx = admin_vlan_ix;
1829
1830 vp_oper->state.default_vlan = vp_admin->default_vlan;
1831 vp_oper->state.default_qos = vp_admin->default_qos;
0a6eac24
RE		 1832 vp_oper->state.link_state = vp_admin->link_state;
1833
1834 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1835 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
b01978ca
JM		 1836
1837 /* iterate over QPs owned by this slave, using UPDATE_QP */
1838 work->port = port;
1839 work->slave = slave;
1840 work->qos = vp_oper->state.default_qos;
1841 work->vlan_id = vp_oper->state.default_vlan;
1842 work->vlan_ix = vp_oper->vlan_idx;
1843 work->priv = priv;
1844 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1845 queue_work(priv->mfunc.master.comm_wq, &work->work);
1846
1847 return 0;
1848}
1849
1850
0eb62b93
RE		 1851static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1852{
3f7fb021
RE		 1853 int port, err;
1854 struct mlx4_vport_state *vp_admin;
1855 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1856 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1857 &priv->dev, slave);
1858 int min_port = find_first_bit(actv_ports.ports,
1859 priv->dev.caps.num_ports) + 1;
1860 int max_port = min_port - 1 +
1861 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1862
1863 for (port = min_port; port <= max_port; port++) {
1864 if (!test_bit(port - 1, actv_ports.ports))
1865 continue;
99ec41d0
JM		 1866 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1867 priv->mfunc.master.vf_admin[slave].enable_smi[port];
3f7fb021
RE		 1868 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1869 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1870 vp_oper->state = *vp_admin;
1871 if (MLX4_VGT != vp_admin->default_vlan) {
1872 err = __mlx4_register_vlan(&priv->dev, port,
1873 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1874 if (err) {
1875 vp_oper->vlan_idx = NO_INDX;
1a91de28 1876 mlx4_warn(&priv->dev,
1a84db56 1877 "No vlan resources slave %d, port %d\n",
3f7fb021
RE		 1878 slave, port);
1879 return err;
1880 }
1a91de28 1881 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
3f7fb021
RE		 1882 (int)(vp_oper->state.default_vlan),
1883 vp_oper->vlan_idx, slave, port);
1884 }
e6b6a231
RE		 1885 if (vp_admin->spoofchk) {
1886 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1887 port,
1888 vp_admin->mac);
1889 if (0 > vp_oper->mac_idx) {
1890 err = vp_oper->mac_idx;
1891 vp_oper->mac_idx = NO_INDX;
1a91de28 1892 mlx4_warn(&priv->dev,
1a84db56 1893 "No mac resources slave %d, port %d\n",
e6b6a231
RE		 1894 slave, port);
1895 return err;
1896 }
1a91de28 1897 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
e6b6a231
RE		 1898 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1899 }
0eb62b93
RE		 1900 }
1901 return 0;
1902}
1903
3f7fb021
RE		 1904static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1905{
1906 int port;
1907 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1908 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1909 &priv->dev, slave);
1910 int min_port = find_first_bit(actv_ports.ports,
1911 priv->dev.caps.num_ports) + 1;
1912 int max_port = min_port - 1 +
1913 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1914
3f7fb021 1915
449fc488
MB		 1916 for (port = min_port; port <= max_port; port++) {
1917 if (!test_bit(port - 1, actv_ports.ports))
1918 continue;
99ec41d0
JM		 1919 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1920 MLX4_VF_SMI_DISABLED;
3f7fb021
RE		 1921 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1922 if (NO_INDX != vp_oper->vlan_idx) {
1923 __mlx4_unregister_vlan(&priv->dev,
2009d005 1924 port, vp_oper->state.default_vlan);
3f7fb021
RE		 1925 vp_oper->vlan_idx = NO_INDX;
1926 }
e6b6a231 1927 if (NO_INDX != vp_oper->mac_idx) {
c32b7dfb 1928 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
e6b6a231
RE		 1929 vp_oper->mac_idx = NO_INDX;
1930 }
3f7fb021
RE		 1931 }
1932 return;
1933}
1934
e8f081aa
YP		 1935static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1936 u16 param, u8 toggle)
1937{
1938 struct mlx4_priv *priv = mlx4_priv(dev);
1939 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1940 u32 reply;
e8f081aa 1941 u8 is_going_down = 0;
803143fb 1942 int i;
311f813a 1943 unsigned long flags;
e8f081aa
YP		 1944
1945 slave_state[slave].comm_toggle ^= 1;
1946 reply = (u32) slave_state[slave].comm_toggle << 31;
1947 if (toggle != slave_state[slave].comm_toggle) {
1a91de28
JP		 1948 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1949 toggle, slave);
e8f081aa
YP		 1950 goto reset_slave;
1951 }
1952 if (cmd == MLX4_COMM_CMD_RESET) {
1953 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1954 slave_state[slave].active = false;
2c957ff2 1955 slave_state[slave].old_vlan_api = false;
3f7fb021 1956 mlx4_master_deactivate_admin_state(priv, slave);
803143fb
MA		 1957 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1958 slave_state[slave].event_eq[i].eqn = -1;
1959 slave_state[slave].event_eq[i].token = 0;
1960 }
e8f081aa
YP		 1961 /*check if we are in the middle of FLR process,
1962 if so return "retry" status to the slave*/
162344ed 1963 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
e8f081aa 1964 goto inform_slave_state;
e8f081aa 1965
fc06573d
JM		 1966 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1967
e8f081aa
YP		 1968 /* write the version in the event field */
1969 reply |= mlx4_comm_get_version();
1970
1971 goto reset_slave;
1972 }
1973 /*command from slave in the middle of FLR*/
1974 if (cmd != MLX4_COMM_CMD_RESET &&
1975 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1a91de28
JP		 1976 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1977 slave, cmd);
e8f081aa
YP		 1978 return;
1979 }
1980
1981 switch (cmd) {
1982 case MLX4_COMM_CMD_VHCR0:
1983 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1984 goto reset_slave;
1985 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1986 priv->mfunc.master.slave_state[slave].cookie = 0;
1987 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1988 break;
1989 case MLX4_COMM_CMD_VHCR1:
1990 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1991 goto reset_slave;
1992 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1993 break;
1994 case MLX4_COMM_CMD_VHCR2:
1995 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1996 goto reset_slave;
1997 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1998 break;
1999 case MLX4_COMM_CMD_VHCR_EN:
2000 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
2001 goto reset_slave;
2002 slave_state[slave].vhcr_dma |= param;
3f7fb021
RE		 2003 if (mlx4_master_activate_admin_state(priv, slave))
2004 goto reset_slave;
e8f081aa 2005 slave_state[slave].active = true;
fc06573d 2006 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
e8f081aa
YP		 2007 break;
2008 case MLX4_COMM_CMD_VHCR_POST:
2009 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
55ad3592
YH		 2010 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST)) {
2011 mlx4_warn(dev, "slave:%d is out of sync, cmd=0x%x, last command=0x%x, reset is needed\n",
2012 slave, cmd, slave_state[slave].last_cmd);
e8f081aa 2013 goto reset_slave;
55ad3592 2014 }
f3d4c89e
RD		 2015
2016 mutex_lock(&priv->cmd.slave_cmd_mutex);
e8f081aa 2017 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1a91de28
JP		 2018 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
2019 slave);
f3d4c89e 2020 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 2021 goto reset_slave;
2022 }
f3d4c89e 2023 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 2024 break;
2025 default:
2026 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
2027 goto reset_slave;
2028 }
311f813a 2029 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 2030 if (!slave_state[slave].is_slave_going_down)
2031 slave_state[slave].last_cmd = cmd;
2032 else
2033 is_going_down = 1;
311f813a 2034 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa 2035 if (is_going_down) {
1a91de28 2036 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
e8f081aa
YP		 2037 cmd, slave);
2038 return;
2039 }
2040 __raw_writel((__force u32) cpu_to_be32(reply),
2041 &priv->mfunc.comm[slave].slave_read);
2042 mmiowb();
2043
2044 return;
2045
2046reset_slave:
c82e9aa0 2047 /* cleanup any slave resources */
55ad3592
YH		 2048 if (dev->persist->interface_state & MLX4_INTERFACE_STATE_UP)
2049 mlx4_delete_all_resources_for_slave(dev, slave);
2050
2051 if (cmd != MLX4_COMM_CMD_RESET) {
2052 mlx4_warn(dev, "Turn on internal error to force reset, slave=%d, cmd=0x%x\n",
2053 slave, cmd);
2054 /* Turn on internal error letting slave reset itself immeditaly,
2055 * otherwise it might take till timeout on command is passed
2056 */
2057 reply |= ((u32)COMM_CHAN_EVENT_INTERNAL_ERR);
2058 }
2059
311f813a 2060 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 2061 if (!slave_state[slave].is_slave_going_down)
2062 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
311f813a 2063 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 2064 /*with slave in the middle of flr, no need to clean resources again.*/
2065inform_slave_state:
2066 memset(&slave_state[slave].event_eq, 0,
2067 sizeof(struct mlx4_slave_event_eq_info));
2068 __raw_writel((__force u32) cpu_to_be32(reply),
2069 &priv->mfunc.comm[slave].slave_read);
2070 wmb();
2071}
2072
2073/* master command processing */
2074void mlx4_master_comm_channel(struct work_struct *work)
2075{
2076 struct mlx4_mfunc_master_ctx *master =
2077 container_of(work,
2078 struct mlx4_mfunc_master_ctx,
2079 comm_work);
2080 struct mlx4_mfunc *mfunc =
2081 container_of(master, struct mlx4_mfunc, master);
2082 struct mlx4_priv *priv =
2083 container_of(mfunc, struct mlx4_priv, mfunc);
2084 struct mlx4_dev *dev = &priv->dev;
2085 __be32 *bit_vec;
2086 u32 comm_cmd;
2087 u32 vec;
2088 int i, j, slave;
2089 int toggle;
2090 int served = 0;
2091 int reported = 0;
2092 u32 slt;
2093
2094 bit_vec = master->comm_arm_bit_vector;
2095 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
2096 vec = be32_to_cpu(bit_vec[i]);
2097 for (j = 0; j < 32; j++) {
2098 if (!(vec & (1 << j)))
2099 continue;
2100 ++reported;
2101 slave = (i * 32) + j;
2102 comm_cmd = swab32(readl(
2103 &mfunc->comm[slave].slave_write));
2104 slt = swab32(readl(&mfunc->comm[slave].slave_read))
2105 >> 31;
2106 toggle = comm_cmd >> 31;
2107 if (toggle != slt) {
2108 if (master->slave_state[slave].comm_toggle
2109 != slt) {
c20862c8
AV		 2110 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
2111 slave, slt,
2112 master->slave_state[slave].comm_toggle);
e8f081aa
YP		 2113 master->slave_state[slave].comm_toggle =
2114 slt;
2115 }
2116 mlx4_master_do_cmd(dev, slave,
2117 comm_cmd >> 16 & 0xff,
2118 comm_cmd & 0xffff, toggle);
2119 ++served;
2120 }
2121 }
2122 }
2123
2124 if (reported && reported != served)
1a91de28 2125 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
e8f081aa
YP		 2126 reported, served);
2127
2128 if (mlx4_ARM_COMM_CHANNEL(dev))
2129 mlx4_warn(dev, "Failed to arm comm channel events\n");
2130}
2131
ab9c17a0
JM		 2132static int sync_toggles(struct mlx4_dev *dev)
2133{
2134 struct mlx4_priv *priv = mlx4_priv(dev);
55ad3592
YH		 2135 u32 wr_toggle;
2136 u32 rd_toggle;
ab9c17a0
JM		 2137 unsigned long end;
2138
55ad3592
YH		 2139 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write));
2140 if (wr_toggle == 0xffffffff)
2141 end = jiffies + msecs_to_jiffies(30000);
2142 else
2143 end = jiffies + msecs_to_jiffies(5000);
ab9c17a0
JM		 2144
2145 while (time_before(jiffies, end)) {
55ad3592
YH		 2146 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read));
2147 if (wr_toggle == 0xffffffff || rd_toggle == 0xffffffff) {
2148 /* PCI might be offline */
2149 msleep(100);
2150 wr_toggle = swab32(readl(&priv->mfunc.comm->
2151 slave_write));
2152 continue;
2153 }
2154
2155 if (rd_toggle >> 31 == wr_toggle >> 31) {
2156 priv->cmd.comm_toggle = rd_toggle >> 31;
ab9c17a0
JM		 2157 return 0;
2158 }
2159
2160 cond_resched();
2161 }
2162
2163 /*
2164 * we could reach here if for example the previous VM using this
2165 * function misbehaved and left the channel with unsynced state. We
2166 * should fix this here and give this VM a chance to use a properly
2167 * synced channel
2168 */
2169 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
2170 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
2171 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
2172 priv->cmd.comm_toggle = 0;
2173
2174 return 0;
2175}
2176
2177int mlx4_multi_func_init(struct mlx4_dev *dev)
2178{
2179 struct mlx4_priv *priv = mlx4_priv(dev);
2180 struct mlx4_slave_state *s_state;
803143fb 2181 int i, j, err, port;
ab9c17a0 2182
ab9c17a0
JM		 2183 if (mlx4_is_master(dev))
2184 priv->mfunc.comm =
872bf2fb
YH		 2185 ioremap(pci_resource_start(dev->persist->pdev,
2186 priv->fw.comm_bar) +
ab9c17a0
JM		 2187 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
2188 else
2189 priv->mfunc.comm =
872bf2fb 2190 ioremap(pci_resource_start(dev->persist->pdev, 2) +
ab9c17a0
JM		 2191 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
2192 if (!priv->mfunc.comm) {
1a91de28 2193 mlx4_err(dev, "Couldn't map communication vector\n");
ab9c17a0
JM		 2194 goto err_vhcr;
2195 }
2196
2197 if (mlx4_is_master(dev)) {
2198 priv->mfunc.master.slave_state =
2199 kzalloc(dev->num_slaves *
2200 sizeof(struct mlx4_slave_state), GFP_KERNEL);
2201 if (!priv->mfunc.master.slave_state)
2202 goto err_comm;
2203
0eb62b93
RE		 2204 priv->mfunc.master.vf_admin =
2205 kzalloc(dev->num_slaves *
2206 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2207 if (!priv->mfunc.master.vf_admin)
2208 goto err_comm_admin;
2209
2210 priv->mfunc.master.vf_oper =
2211 kzalloc(dev->num_slaves *
2212 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2213 if (!priv->mfunc.master.vf_oper)
2214 goto err_comm_oper;
2215
ab9c17a0
JM		 2216 for (i = 0; i < dev->num_slaves; ++i) {
2217 s_state = &priv->mfunc.master.slave_state[i];
2218 s_state->last_cmd = MLX4_COMM_CMD_RESET;
803143fb
MA		 2219 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2220 s_state->event_eq[j].eqn = -1;
ab9c17a0
JM		 2221 __raw_writel((__force u32) 0,
2222 &priv->mfunc.comm[i].slave_write);
2223 __raw_writel((__force u32) 0,
2224 &priv->mfunc.comm[i].slave_read);
2225 mmiowb();
2226 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2227 s_state->vlan_filter[port] =
2228 kzalloc(sizeof(struct mlx4_vlan_fltr),
2229 GFP_KERNEL);
2230 if (!s_state->vlan_filter[port]) {
2231 if (--port)
2232 kfree(s_state->vlan_filter[port]);
2233 goto err_slaves;
2234 }
2235 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
0eb62b93 2236 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
3f7fb021 2237 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
0eb62b93
RE		 2238 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2239 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
ab9c17a0
JM		 2240 }
2241 spin_lock_init(&s_state->lock);
2242 }
2243
08ff3235 2244 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
ab9c17a0
JM		 2245 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2246 INIT_WORK(&priv->mfunc.master.comm_work,
2247 mlx4_master_comm_channel);
2248 INIT_WORK(&priv->mfunc.master.slave_event_work,
2249 mlx4_gen_slave_eqe);
2250 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2251 mlx4_master_handle_slave_flr);
2252 spin_lock_init(&priv->mfunc.master.slave_state_lock);
992e8e6e 2253 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
ab9c17a0
JM		 2254 priv->mfunc.master.comm_wq =
2255 create_singlethread_workqueue("mlx4_comm");
2256 if (!priv->mfunc.master.comm_wq)
2257 goto err_slaves;
2258
2259 if (mlx4_init_resource_tracker(dev))
2260 goto err_thread;
2261
ab9c17a0
JM		 2262 } else {
2263 err = sync_toggles(dev);
2264 if (err) {
2265 mlx4_err(dev, "Couldn't sync toggles\n");
2266 goto err_comm;
2267 }
ab9c17a0
JM		 2268 }
2269 return 0;
2270
ab9c17a0
JM		 2271err_thread:
2272 flush_workqueue(priv->mfunc.master.comm_wq);
2273 destroy_workqueue(priv->mfunc.master.comm_wq);
2274err_slaves:
2275 while (--i) {
2276 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2277 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2278 }
0eb62b93
RE		 2279 kfree(priv->mfunc.master.vf_oper);
2280err_comm_oper:
2281 kfree(priv->mfunc.master.vf_admin);
2282err_comm_admin:
ab9c17a0
JM		 2283 kfree(priv->mfunc.master.slave_state);
2284err_comm:
2285 iounmap(priv->mfunc.comm);
2286err_vhcr:
872bf2fb
YH		 2287 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
2288 priv->mfunc.vhcr,
2289 priv->mfunc.vhcr_dma);
ab9c17a0
JM		 2290 priv->mfunc.vhcr = NULL;
2291 return -ENOMEM;
2292}
2293
225c7b1f
RD		 2294int mlx4_cmd_init(struct mlx4_dev *dev)
2295{
2296 struct mlx4_priv *priv = mlx4_priv(dev);
ffc39f6d
MB		 2297 int flags = 0;
2298
2299 if (!priv->cmd.initialized) {
ffc39f6d
MB		 2300 mutex_init(&priv->cmd.slave_cmd_mutex);
2301 sema_init(&priv->cmd.poll_sem, 1);
2302 priv->cmd.use_events = 0;
2303 priv->cmd.toggle = 1;
2304 priv->cmd.initialized = 1;
2305 flags |= MLX4_CMD_CLEANUP_STRUCT;
2306 }
225c7b1f 2307
ffc39f6d 2308 if (!mlx4_is_slave(dev) && !priv->cmd.hcr) {
872bf2fb
YH		 2309 priv->cmd.hcr = ioremap(pci_resource_start(dev->persist->pdev,
2310 0) + MLX4_HCR_BASE, MLX4_HCR_SIZE);
e8f081aa 2311 if (!priv->cmd.hcr) {
1a91de28 2312 mlx4_err(dev, "Couldn't map command register\n");
ffc39f6d 2313 goto err;
e8f081aa 2314 }
ffc39f6d 2315 flags |= MLX4_CMD_CLEANUP_HCR;
225c7b1f
RD		 2316 }
2317
ffc39f6d 2318 if (mlx4_is_mfunc(dev) && !priv->mfunc.vhcr) {
872bf2fb
YH		 2319 priv->mfunc.vhcr = dma_alloc_coherent(&dev->persist->pdev->dev,
2320 PAGE_SIZE,
f3d4c89e
RD		 2321 &priv->mfunc.vhcr_dma,
2322 GFP_KERNEL);
d0320f75 2323 if (!priv->mfunc.vhcr)
ffc39f6d
MB		 2324 goto err;
2325
2326 flags |= MLX4_CMD_CLEANUP_VHCR;
f3d4c89e
RD		 2327 }
2328
ffc39f6d 2329 if (!priv->cmd.pool) {
872bf2fb
YH		 2330 priv->cmd.pool = pci_pool_create("mlx4_cmd",
2331 dev->persist->pdev,
ffc39f6d
MB		 2332 MLX4_MAILBOX_SIZE,
2333 MLX4_MAILBOX_SIZE, 0);
2334 if (!priv->cmd.pool)
2335 goto err;
225c7b1f 2336
ffc39f6d
MB		 2337 flags |= MLX4_CMD_CLEANUP_POOL;
2338 }
e8f081aa 2339
ffc39f6d 2340 return 0;
f3d4c89e 2341
ffc39f6d
MB		 2342err:
2343 mlx4_cmd_cleanup(dev, flags);
e8f081aa 2344 return -ENOMEM;
225c7b1f
RD		 2345}
2346
55ad3592
YH		 2347void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev)
2348{
2349 struct mlx4_priv *priv = mlx4_priv(dev);
2350 int slave;
2351 u32 slave_read;
2352
2353 /* Report an internal error event to all
2354 * communication channels.
2355 */
2356 for (slave = 0; slave < dev->num_slaves; slave++) {
2357 slave_read = swab32(readl(&priv->mfunc.comm[slave].slave_read));
2358 slave_read |= (u32)COMM_CHAN_EVENT_INTERNAL_ERR;
2359 __raw_writel((__force u32)cpu_to_be32(slave_read),
2360 &priv->mfunc.comm[slave].slave_read);
2361 /* Make sure that our comm channel write doesn't
2362 * get mixed in with writes from another CPU.
2363 */
2364 mmiowb();
2365 }
2366}
2367
ab9c17a0
JM		 2368void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2369{
2370 struct mlx4_priv *priv = mlx4_priv(dev);
2371 int i, port;
2372
2373 if (mlx4_is_master(dev)) {
2374 flush_workqueue(priv->mfunc.master.comm_wq);
2375 destroy_workqueue(priv->mfunc.master.comm_wq);
2376 for (i = 0; i < dev->num_slaves; i++) {
2377 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2378 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2379 }
2380 kfree(priv->mfunc.master.slave_state);
0eb62b93
RE		 2381 kfree(priv->mfunc.master.vf_admin);
2382 kfree(priv->mfunc.master.vf_oper);
55ad3592 2383 dev->num_slaves = 0;
ab9c17a0 2384 }
f08ad06c
EE		 2385
2386 iounmap(priv->mfunc.comm);
ab9c17a0
JM		 2387}
2388
ffc39f6d 2389void mlx4_cmd_cleanup(struct mlx4_dev *dev, int cleanup_mask)
225c7b1f
RD		 2390{
2391 struct mlx4_priv *priv = mlx4_priv(dev);
2392
ffc39f6d
MB		 2393 if (priv->cmd.pool && (cleanup_mask & MLX4_CMD_CLEANUP_POOL)) {
2394 pci_pool_destroy(priv->cmd.pool);
2395 priv->cmd.pool = NULL;
2396 }
e8f081aa 2397
ffc39f6d
MB		 2398 if (!mlx4_is_slave(dev) && priv->cmd.hcr &&
2399 (cleanup_mask & MLX4_CMD_CLEANUP_HCR)) {
e8f081aa 2400 iounmap(priv->cmd.hcr);
ffc39f6d
MB		 2401 priv->cmd.hcr = NULL;
2402 }
2403 if (mlx4_is_mfunc(dev) && priv->mfunc.vhcr &&
2404 (cleanup_mask & MLX4_CMD_CLEANUP_VHCR)) {
872bf2fb 2405 dma_free_coherent(&dev->persist->pdev->dev, PAGE_SIZE,
f3d4c89e 2406 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
ffc39f6d
MB		 2407 priv->mfunc.vhcr = NULL;
2408 }
2409 if (priv->cmd.initialized && (cleanup_mask & MLX4_CMD_CLEANUP_STRUCT))
2410 priv->cmd.initialized = 0;
225c7b1f
RD		 2411}
2412
2413/*
2414 * Switch to using events to issue FW commands (can only be called
2415 * after event queue for command events has been initialized).
2416 */
2417int mlx4_cmd_use_events(struct mlx4_dev *dev)
2418{
2419 struct mlx4_priv *priv = mlx4_priv(dev);
2420 int i;
e8f081aa 2421 int err = 0;
225c7b1f
RD		 2422
2423 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2424 sizeof (struct mlx4_cmd_context),
2425 GFP_KERNEL);
2426 if (!priv->cmd.context)
2427 return -ENOMEM;
2428
2429 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2430 priv->cmd.context[i].token = i;
2431 priv->cmd.context[i].next = i + 1;
f5aef5aa
YH		 2432 /* To support fatal error flow, initialize all
2433 * cmd contexts to allow simulating completions
2434 * with complete() at any time.
2435 */
2436 init_completion(&priv->cmd.context[i].done);
225c7b1f
RD		 2437 }
2438
2439 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2440 priv->cmd.free_head = 0;
2441
2442 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2443 spin_lock_init(&priv->cmd.context_lock);
2444
2445 for (priv->cmd.token_mask = 1;
2446 priv->cmd.token_mask < priv->cmd.max_cmds;
2447 priv->cmd.token_mask <<= 1)
2448 ; /* nothing */
2449 --priv->cmd.token_mask;
2450
225c7b1f 2451 down(&priv->cmd.poll_sem);
e8f081aa 2452 priv->cmd.use_events = 1;
225c7b1f 2453
e8f081aa 2454 return err;
225c7b1f
RD		 2455}
2456
2457/*
2458 * Switch back to polling (used when shutting down the device)
2459 */
2460void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2461{
2462 struct mlx4_priv *priv = mlx4_priv(dev);
2463 int i;
2464
2465 priv->cmd.use_events = 0;
2466
2467 for (i = 0; i < priv->cmd.max_cmds; ++i)
2468 down(&priv->cmd.event_sem);
2469
2470 kfree(priv->cmd.context);
2471
2472 up(&priv->cmd.poll_sem);
2473}
2474
2475struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2476{
2477 struct mlx4_cmd_mailbox *mailbox;
2478
2479 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2480 if (!mailbox)
2481 return ERR_PTR(-ENOMEM);
2482
2483 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2484 &mailbox->dma);
2485 if (!mailbox->buf) {
2486 kfree(mailbox);
2487 return ERR_PTR(-ENOMEM);
2488 }
2489
571b8b92
JM		 2490 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2491
225c7b1f
RD		 2492 return mailbox;
2493}
2494EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2495
e8f081aa
YP		 2496void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2497 struct mlx4_cmd_mailbox *mailbox)
225c7b1f
RD		 2498{
2499 if (!mailbox)
2500 return;
2501
2502 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2503 kfree(mailbox);
2504}
2505EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
e8f081aa
YP		 2506
2507u32 mlx4_comm_get_version(void)
2508{
2509 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2510}
8f7ba3ca
RE		 2511
2512static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2513{
872bf2fb
YH		 2514 if ((vf < 0) || (vf >= dev->persist->num_vfs)) {
2515 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n",
2516 vf, dev->persist->num_vfs);
8f7ba3ca
RE		 2517 return -EINVAL;
2518 }
2519
2520 return vf+1;
2521}
2522
f74462ac
MB		 2523int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2524{
872bf2fb 2525 if (slave < 1 || slave > dev->persist->num_vfs) {
f74462ac
MB		 2526 mlx4_err(dev,
2527 "Bad slave number:%d (number of activated slaves: %lu)\n",
2528 slave, dev->num_slaves);
2529 return -EINVAL;
2530 }
2531 return slave - 1;
2532}
2533
f5aef5aa
YH		 2534void mlx4_cmd_wake_completions(struct mlx4_dev *dev)
2535{
2536 struct mlx4_priv *priv = mlx4_priv(dev);
2537 struct mlx4_cmd_context *context;
2538 int i;
2539
2540 spin_lock(&priv->cmd.context_lock);
2541 if (priv->cmd.context) {
2542 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2543 context = &priv->cmd.context[i];
2544 context->fw_status = CMD_STAT_INTERNAL_ERR;
2545 context->result =
2546 mlx4_status_to_errno(CMD_STAT_INTERNAL_ERR);
2547 complete(&context->done);
2548 }
2549 }
2550 spin_unlock(&priv->cmd.context_lock);
2551}
2552
f74462ac
MB		 2553struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2554{
2555 struct mlx4_active_ports actv_ports;
2556 int vf;
2557
2558 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2559
2560 if (slave == 0) {
2561 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2562 return actv_ports;
2563 }
2564
2565 vf = mlx4_get_vf_indx(dev, slave);
2566 if (vf < 0)
2567 return actv_ports;
2568
2569 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2570 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2571 dev->caps.num_ports));
2572
2573 return actv_ports;
2574}
2575EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2576
2577int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2578{
2579 unsigned n;
2580 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2581 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2582
2583 if (port <= 0 || port > m)
2584 return -EINVAL;
2585
2586 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2587 if (port <= n)
2588 port = n + 1;
2589
2590 return port;
2591}
2592EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2593
2594int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2595{
2596 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2597 if (test_bit(port - 1, actv_ports.ports))
2598 return port -
2599 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2600
2601 return -1;
2602}
2603EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2604
2605struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2606 int port)
2607{
2608 unsigned i;
2609 struct mlx4_slaves_pport slaves_pport;
2610
2611 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2612
2613 if (port <= 0 || port > dev->caps.num_ports)
2614 return slaves_pport;
2615
872bf2fb 2616 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
f74462ac
MB		 2617 struct mlx4_active_ports actv_ports =
2618 mlx4_get_active_ports(dev, i);
2619 if (test_bit(port - 1, actv_ports.ports))
2620 set_bit(i, slaves_pport.slaves);
2621 }
2622
2623 return slaves_pport;
2624}
2625EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2626
2627struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2628 struct mlx4_dev *dev,
2629 const struct mlx4_active_ports *crit_ports)
2630{
2631 unsigned i;
2632 struct mlx4_slaves_pport slaves_pport;
2633
2634 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2635
872bf2fb 2636 for (i = 0; i < dev->persist->num_vfs + 1; i++) {
f74462ac
MB		 2637 struct mlx4_active_ports actv_ports =
2638 mlx4_get_active_ports(dev, i);
2639 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2640 dev->caps.num_ports))
2641 set_bit(i, slaves_pport.slaves);
2642 }
2643
2644 return slaves_pport;
2645}
2646EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2647
a91c772f
MB		 2648static int mlx4_slaves_closest_port(struct mlx4_dev *dev, int slave, int port)
2649{
2650 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2651 int min_port = find_first_bit(actv_ports.ports, dev->caps.num_ports)
2652 + 1;
2653 int max_port = min_port +
2654 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2655
2656 if (port < min_port)
2657 port = min_port;
2658 else if (port >= max_port)
2659 port = max_port - 1;
2660
2661 return port;
2662}
2663
8f7ba3ca
RE		 2664int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2665{
2666 struct mlx4_priv *priv = mlx4_priv(dev);
2667 struct mlx4_vport_state *s_info;
2668 int slave;
2669
2670 if (!mlx4_is_master(dev))
2671 return -EPROTONOSUPPORT;
2672
2673 slave = mlx4_get_slave_indx(dev, vf);
2674 if (slave < 0)
2675 return -EINVAL;
2676
a91c772f 2677 port = mlx4_slaves_closest_port(dev, slave, port);
8f7ba3ca
RE		 2678 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2679 s_info->mac = mac;
2680 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2681 vf, port, s_info->mac);
2682 return 0;
2683}
2684EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3f7fb021 2685
b01978ca 2686
3f7fb021
RE		 2687int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2688{
2689 struct mlx4_priv *priv = mlx4_priv(dev);
b01978ca 2690 struct mlx4_vport_state *vf_admin;
3f7fb021
RE		 2691 int slave;
2692
2693 if ((!mlx4_is_master(dev)) ||
2694 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2695 return -EPROTONOSUPPORT;
2696
2697 if ((vlan > 4095) || (qos > 7))
2698 return -EINVAL;
2699
2700 slave = mlx4_get_slave_indx(dev, vf);
2701 if (slave < 0)
2702 return -EINVAL;
2703
a91c772f 2704 port = mlx4_slaves_closest_port(dev, slave, port);
b01978ca 2705 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
b01978ca 2706
3f7fb021 2707 if ((0 == vlan) && (0 == qos))
b01978ca 2708 vf_admin->default_vlan = MLX4_VGT;
3f7fb021 2709 else
b01978ca
JM		 2710 vf_admin->default_vlan = vlan;
2711 vf_admin->default_qos = qos;
2712
0a6eac24
RE		 2713 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2714 mlx4_info(dev,
2715 "updating vf %d port %d config will take effect on next VF restart\n",
b01978ca 2716 vf, port);
3f7fb021
RE		 2717 return 0;
2718}
2719EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
e6b6a231 2720
5ea8bbfc
JM		 2721 /* mlx4_get_slave_default_vlan -
2722 * return true if VST ( default vlan)
2723 * if VST, will return vlan & qos (if not NULL)
2724 */
2725bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2726 u16 *vlan, u8 *qos)
2727{
2728 struct mlx4_vport_oper_state *vp_oper;
2729 struct mlx4_priv *priv;
2730
2731 priv = mlx4_priv(dev);
a91c772f 2732 port = mlx4_slaves_closest_port(dev, slave, port);
5ea8bbfc
JM		 2733 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2734
2735 if (MLX4_VGT != vp_oper->state.default_vlan) {
2736 if (vlan)
2737 *vlan = vp_oper->state.default_vlan;
2738 if (qos)
2739 *qos = vp_oper->state.default_qos;
2740 return true;
2741 }
2742 return false;
2743}
2744EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2745
e6b6a231
RE		 2746int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2747{
2748 struct mlx4_priv *priv = mlx4_priv(dev);
2749 struct mlx4_vport_state *s_info;
2750 int slave;
2751
2752 if ((!mlx4_is_master(dev)) ||
2753 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2754 return -EPROTONOSUPPORT;
2755
2756 slave = mlx4_get_slave_indx(dev, vf);
2757 if (slave < 0)
2758 return -EINVAL;
2759
a91c772f 2760 port = mlx4_slaves_closest_port(dev, slave, port);
e6b6a231
RE		 2761 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2762 s_info->spoofchk = setting;
2763
2764 return 0;
2765}
2766EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2cccb9e4
RE		 2767
2768int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2769{
2770 struct mlx4_priv *priv = mlx4_priv(dev);
2771 struct mlx4_vport_state *s_info;
2772 int slave;
2773
2774 if (!mlx4_is_master(dev))
2775 return -EPROTONOSUPPORT;
2776
2777 slave = mlx4_get_slave_indx(dev, vf);
2778 if (slave < 0)
2779 return -EINVAL;
2780
2781 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2782 ivf->vf = vf;
2783
2784 /* need to convert it to a func */
2785 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2786 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2787 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2788 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2789 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2790 ivf->mac[5] = ((s_info->mac) & 0xff);
2791
ed616689
SC		 2792 ivf->vlan = s_info->default_vlan;
2793 ivf->qos = s_info->default_qos;
2794 ivf->max_tx_rate = s_info->tx_rate;
2795 ivf->min_tx_rate = 0;
2796 ivf->spoofchk = s_info->spoofchk;
2797 ivf->linkstate = s_info->link_state;
2cccb9e4
RE		 2798
2799 return 0;
2800}
2801EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
948e306d
RE		 2802
2803int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2804{
2805 struct mlx4_priv *priv = mlx4_priv(dev);
2806 struct mlx4_vport_state *s_info;
948e306d
RE		 2807 int slave;
2808 u8 link_stat_event;
2809
2810 slave = mlx4_get_slave_indx(dev, vf);
2811 if (slave < 0)
2812 return -EINVAL;
2813
a91c772f 2814 port = mlx4_slaves_closest_port(dev, slave, port);
948e306d
RE		 2815 switch (link_state) {
2816 case IFLA_VF_LINK_STATE_AUTO:
2817 /* get current link state */
2818 if (!priv->sense.do_sense_port[port])
2819 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2820 else
2821 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2822 break;
2823
2824 case IFLA_VF_LINK_STATE_ENABLE:
2825 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2826 break;
2827
2828 case IFLA_VF_LINK_STATE_DISABLE:
2829 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2830 break;
2831
2832 default:
2833 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2834 link_state, slave, port);
2835 return -EINVAL;
2836 };
948e306d 2837 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
948e306d 2838 s_info->link_state = link_state;
948e306d
RE		 2839
2840 /* send event */
2841 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
0a6eac24
RE		 2842
2843 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2844 mlx4_dbg(dev,
2845 "updating vf %d port %d no link state HW enforcment\n",
2846 vf, port);
948e306d
RE		 2847 return 0;
2848}
2849EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
97982f5a
JM		 2850
2851int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2852{
99ec41d0
JM		 2853 struct mlx4_priv *priv = mlx4_priv(dev);
2854
2855 if (slave < 1 || slave >= dev->num_slaves ||
2856 port < 1 || port > MLX4_MAX_PORTS)
2857 return 0;
2858
2859 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2860 MLX4_VF_SMI_ENABLED;
97982f5a
JM		 2861}
2862EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
65fed8a8
JM		 2863
2864int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
2865{
2866 struct mlx4_priv *priv = mlx4_priv(dev);
2867
2868 if (slave == mlx4_master_func_num(dev))
2869 return 1;
2870
2871 if (slave < 1 || slave >= dev->num_slaves ||
2872 port < 1 || port > MLX4_MAX_PORTS)
2873 return 0;
2874
2875 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
2876 MLX4_VF_SMI_ENABLED;
2877}
2878EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
2879
2880int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
2881 int enabled)
2882{
2883 struct mlx4_priv *priv = mlx4_priv(dev);
2884
2885 if (slave == mlx4_master_func_num(dev))
2886 return 0;
2887
2888 if (slave < 1 || slave >= dev->num_slaves ||
2889 port < 1 || port > MLX4_MAX_PORTS ||
2890 enabled < 0 || enabled > 1)
2891 return -EINVAL;
2892
2893 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
2894 return 0;
2895}
2896EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);
Linux kernel - Deliverables
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