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drivers: net: cpsw: dual_emac: fix reducing of rx descriptor during ifdown
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / cmd.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35#include <linux/sched.h>
5a0e3ad6 36#include <linux/slab.h>
ee40fa06 37#include <linux/export.h>
225c7b1f
RD		 38#include <linux/pci.h>
39#include <linux/errno.h>
40
41#include <linux/mlx4/cmd.h>
948e306d 42#include <linux/mlx4/device.h>
e8f081aa 43#include <linux/semaphore.h>
0a9a0188 44#include <rdma/ib_smi.h>
225c7b1f
RD		 45
46#include <asm/io.h>
47
48#include "mlx4.h"
e8f081aa 49#include "fw.h"
225c7b1f
RD		 50
51#define CMD_POLL_TOKEN 0xffff
e8f081aa
YP		 52#define INBOX_MASK 0xffffffffffffff00ULL
53
54#define CMD_CHAN_VER 1
55#define CMD_CHAN_IF_REV 1
225c7b1f
RD		 56
57enum {
58 /* command completed successfully: */
59 CMD_STAT_OK = 0x00,
60 /* Internal error (such as a bus error) occurred while processing command: */
61 CMD_STAT_INTERNAL_ERR = 0x01,
62 /* Operation/command not supported or opcode modifier not supported: */
63 CMD_STAT_BAD_OP = 0x02,
64 /* Parameter not supported or parameter out of range: */
65 CMD_STAT_BAD_PARAM = 0x03,
66 /* System not enabled or bad system state: */
67 CMD_STAT_BAD_SYS_STATE = 0x04,
68 /* Attempt to access reserved or unallocaterd resource: */
69 CMD_STAT_BAD_RESOURCE = 0x05,
70 /* Requested resource is currently executing a command, or is otherwise busy: */
71 CMD_STAT_RESOURCE_BUSY = 0x06,
72 /* Required capability exceeds device limits: */
73 CMD_STAT_EXCEED_LIM = 0x08,
74 /* Resource is not in the appropriate state or ownership: */
75 CMD_STAT_BAD_RES_STATE = 0x09,
76 /* Index out of range: */
77 CMD_STAT_BAD_INDEX = 0x0a,
78 /* FW image corrupted: */
79 CMD_STAT_BAD_NVMEM = 0x0b,
899698da
JM		 80 /* Error in ICM mapping (e.g. not enough auxiliary ICM pages to execute command): */
81 CMD_STAT_ICM_ERROR = 0x0c,
225c7b1f
RD		 82 /* Attempt to modify a QP/EE which is not in the presumed state: */
83 CMD_STAT_BAD_QP_STATE = 0x10,
84 /* Bad segment parameters (Address/Size): */
85 CMD_STAT_BAD_SEG_PARAM = 0x20,
86 /* Memory Region has Memory Windows bound to: */
87 CMD_STAT_REG_BOUND = 0x21,
88 /* HCA local attached memory not present: */
89 CMD_STAT_LAM_NOT_PRE = 0x22,
90 /* Bad management packet (silently discarded): */
91 CMD_STAT_BAD_PKT = 0x30,
92 /* More outstanding CQEs in CQ than new CQ size: */
cc4ac2e7
YP		 93 CMD_STAT_BAD_SIZE = 0x40,
94 /* Multi Function device support required: */
95 CMD_STAT_MULTI_FUNC_REQ = 0x50,
225c7b1f
RD		 96};
97
98enum {
99 HCR_IN_PARAM_OFFSET = 0x00,
100 HCR_IN_MODIFIER_OFFSET = 0x08,
101 HCR_OUT_PARAM_OFFSET = 0x0c,
102 HCR_TOKEN_OFFSET = 0x14,
103 HCR_STATUS_OFFSET = 0x18,
104
105 HCR_OPMOD_SHIFT = 12,
106 HCR_T_BIT = 21,
107 HCR_E_BIT = 22,
108 HCR_GO_BIT = 23
109};
110
111enum {
36ce10d3 112 GO_BIT_TIMEOUT_MSECS = 10000
225c7b1f
RD		 113};
114
b01978ca
JM		 115enum mlx4_vlan_transition {
116 MLX4_VLAN_TRANSITION_VST_VST = 0,
117 MLX4_VLAN_TRANSITION_VST_VGT = 1,
118 MLX4_VLAN_TRANSITION_VGT_VST = 2,
119 MLX4_VLAN_TRANSITION_VGT_VGT = 3,
120};
121
122
225c7b1f
RD		 123struct mlx4_cmd_context {
124 struct completion done;
125 int result;
126 int next;
127 u64 out_param;
128 u16 token;
e8f081aa 129 u8 fw_status;
225c7b1f
RD		 130};
131
e8f081aa
YP		 132static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
133 struct mlx4_vhcr_cmd *in_vhcr);
134
ca281211
RD		 135static int mlx4_status_to_errno(u8 status)
136{
225c7b1f
RD		 137 static const int trans_table[] = {
138 [CMD_STAT_INTERNAL_ERR] = -EIO,
139 [CMD_STAT_BAD_OP] = -EPERM,
140 [CMD_STAT_BAD_PARAM] = -EINVAL,
141 [CMD_STAT_BAD_SYS_STATE] = -ENXIO,
142 [CMD_STAT_BAD_RESOURCE] = -EBADF,
143 [CMD_STAT_RESOURCE_BUSY] = -EBUSY,
144 [CMD_STAT_EXCEED_LIM] = -ENOMEM,
145 [CMD_STAT_BAD_RES_STATE] = -EBADF,
146 [CMD_STAT_BAD_INDEX] = -EBADF,
147 [CMD_STAT_BAD_NVMEM] = -EFAULT,
899698da 148 [CMD_STAT_ICM_ERROR] = -ENFILE,
225c7b1f
RD		 149 [CMD_STAT_BAD_QP_STATE] = -EINVAL,
150 [CMD_STAT_BAD_SEG_PARAM] = -EFAULT,
151 [CMD_STAT_REG_BOUND] = -EBUSY,
152 [CMD_STAT_LAM_NOT_PRE] = -EAGAIN,
153 [CMD_STAT_BAD_PKT] = -EINVAL,
154 [CMD_STAT_BAD_SIZE] = -ENOMEM,
cc4ac2e7 155 [CMD_STAT_MULTI_FUNC_REQ] = -EACCES,
225c7b1f
RD		 156 };
157
158 if (status >= ARRAY_SIZE(trans_table) ||
159 (status != CMD_STAT_OK && trans_table[status] == 0))
160 return -EIO;
161
162 return trans_table[status];
163}
164
72be84f1
YP		 165static u8 mlx4_errno_to_status(int errno)
166{
167 switch (errno) {
168 case -EPERM:
169 return CMD_STAT_BAD_OP;
170 case -EINVAL:
171 return CMD_STAT_BAD_PARAM;
172 case -ENXIO:
173 return CMD_STAT_BAD_SYS_STATE;
174 case -EBUSY:
175 return CMD_STAT_RESOURCE_BUSY;
176 case -ENOMEM:
177 return CMD_STAT_EXCEED_LIM;
178 case -ENFILE:
179 return CMD_STAT_ICM_ERROR;
180 default:
181 return CMD_STAT_INTERNAL_ERR;
182 }
183}
184
e8f081aa
YP		 185static int comm_pending(struct mlx4_dev *dev)
186{
187 struct mlx4_priv *priv = mlx4_priv(dev);
188 u32 status = readl(&priv->mfunc.comm->slave_read);
189
190 return (swab32(status) >> 31) != priv->cmd.comm_toggle;
191}
192
193static void mlx4_comm_cmd_post(struct mlx4_dev *dev, u8 cmd, u16 param)
194{
195 struct mlx4_priv *priv = mlx4_priv(dev);
196 u32 val;
197
198 priv->cmd.comm_toggle ^= 1;
199 val = param | (cmd << 16) | (priv->cmd.comm_toggle << 31);
200 __raw_writel((__force u32) cpu_to_be32(val),
201 &priv->mfunc.comm->slave_write);
202 mmiowb();
203}
204
e8f081aa
YP		 205static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
206 unsigned long timeout)
207{
208 struct mlx4_priv *priv = mlx4_priv(dev);
209 unsigned long end;
210 int err = 0;
211 int ret_from_pending = 0;
212
213 /* First, verify that the master reports correct status */
214 if (comm_pending(dev)) {
1a91de28 215 mlx4_warn(dev, "Communication channel is not idle - my toggle is %d (cmd:0x%x)\n",
e8f081aa
YP		 216 priv->cmd.comm_toggle, cmd);
217 return -EAGAIN;
218 }
219
220 /* Write command */
221 down(&priv->cmd.poll_sem);
222 mlx4_comm_cmd_post(dev, cmd, param);
223
224 end = msecs_to_jiffies(timeout) + jiffies;
225 while (comm_pending(dev) && time_before(jiffies, end))
226 cond_resched();
227 ret_from_pending = comm_pending(dev);
228 if (ret_from_pending) {
229 /* check if the slave is trying to boot in the middle of
230 * FLR process. The only non-zero result in the RESET command
231 * is MLX4_DELAY_RESET_SLAVE*/
232 if ((MLX4_COMM_CMD_RESET == cmd)) {
e8f081aa
YP		 233 err = MLX4_DELAY_RESET_SLAVE;
234 } else {
235 mlx4_warn(dev, "Communication channel timed out\n");
236 err = -ETIMEDOUT;
237 }
238 }
239
240 up(&priv->cmd.poll_sem);
241 return err;
242}
243
244static int mlx4_comm_cmd_wait(struct mlx4_dev *dev, u8 op,
245 u16 param, unsigned long timeout)
246{
247 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
248 struct mlx4_cmd_context *context;
58a3de05 249 unsigned long end;
e8f081aa
YP		 250 int err = 0;
251
252 down(&cmd->event_sem);
253
254 spin_lock(&cmd->context_lock);
255 BUG_ON(cmd->free_head < 0);
256 context = &cmd->context[cmd->free_head];
257 context->token += cmd->token_mask + 1;
258 cmd->free_head = context->next;
259 spin_unlock(&cmd->context_lock);
260
261 init_completion(&context->done);
262
263 mlx4_comm_cmd_post(dev, op, param);
264
265 if (!wait_for_completion_timeout(&context->done,
266 msecs_to_jiffies(timeout))) {
674925ed
DB		 267 mlx4_warn(dev, "communication channel command 0x%x timed out\n",
268 op);
e8f081aa
YP		 269 err = -EBUSY;
270 goto out;
271 }
272
273 err = context->result;
274 if (err && context->fw_status != CMD_STAT_MULTI_FUNC_REQ) {
275 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
276 op, context->fw_status);
277 goto out;
278 }
279
280out:
58a3de05
EE		 281 /* wait for comm channel ready
282 * this is necessary for prevention the race
283 * when switching between event to polling mode
284 */
285 end = msecs_to_jiffies(timeout) + jiffies;
286 while (comm_pending(dev) && time_before(jiffies, end))
287 cond_resched();
288
e8f081aa
YP		 289 spin_lock(&cmd->context_lock);
290 context->next = cmd->free_head;
291 cmd->free_head = context - cmd->context;
292 spin_unlock(&cmd->context_lock);
293
294 up(&cmd->event_sem);
295 return err;
296}
297
ab9c17a0 298int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
e8f081aa
YP		 299 unsigned long timeout)
300{
301 if (mlx4_priv(dev)->cmd.use_events)
302 return mlx4_comm_cmd_wait(dev, cmd, param, timeout);
303 return mlx4_comm_cmd_poll(dev, cmd, param, timeout);
304}
305
225c7b1f
RD		 306static int cmd_pending(struct mlx4_dev *dev)
307{
57dbf29a
KSS		 308 u32 status;
309
310 if (pci_channel_offline(dev->pdev))
311 return -EIO;
312
313 status = readl(mlx4_priv(dev)->cmd.hcr + HCR_STATUS_OFFSET);
225c7b1f
RD		 314
315 return (status & swab32(1 << HCR_GO_BIT)) ||
316 (mlx4_priv(dev)->cmd.toggle ==
317 !!(status & swab32(1 << HCR_T_BIT)));
318}
319
320static int mlx4_cmd_post(struct mlx4_dev *dev, u64 in_param, u64 out_param,
321 u32 in_modifier, u8 op_modifier, u16 op, u16 token,
322 int event)
323{
324 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
325 u32 __iomem *hcr = cmd->hcr;
326 int ret = -EAGAIN;
327 unsigned long end;
328
329 mutex_lock(&cmd->hcr_mutex);
330
57dbf29a
KSS		 331 if (pci_channel_offline(dev->pdev)) {
332 /*
333 * Device is going through error recovery
334 * and cannot accept commands.
335 */
336 ret = -EIO;
337 goto out;
338 }
339
225c7b1f
RD		 340 end = jiffies;
341 if (event)
36ce10d3 342 end += msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS);
225c7b1f
RD		 343
344 while (cmd_pending(dev)) {
57dbf29a
KSS		 345 if (pci_channel_offline(dev->pdev)) {
346 /*
347 * Device is going through error recovery
348 * and cannot accept commands.
349 */
350 ret = -EIO;
351 goto out;
352 }
353
e8f081aa
YP		 354 if (time_after_eq(jiffies, end)) {
355 mlx4_err(dev, "%s:cmd_pending failed\n", __func__);
225c7b1f 356 goto out;
e8f081aa 357 }
225c7b1f
RD		 358 cond_resched();
359 }
360
361 /*
362 * We use writel (instead of something like memcpy_toio)
363 * because writes of less than 32 bits to the HCR don't work
364 * (and some architectures such as ia64 implement memcpy_toio
365 * in terms of writeb).
366 */
367 __raw_writel((__force u32) cpu_to_be32(in_param >> 32), hcr + 0);
368 __raw_writel((__force u32) cpu_to_be32(in_param & 0xfffffffful), hcr + 1);
369 __raw_writel((__force u32) cpu_to_be32(in_modifier), hcr + 2);
370 __raw_writel((__force u32) cpu_to_be32(out_param >> 32), hcr + 3);
371 __raw_writel((__force u32) cpu_to_be32(out_param & 0xfffffffful), hcr + 4);
372 __raw_writel((__force u32) cpu_to_be32(token << 16), hcr + 5);
373
374 /* __raw_writel may not order writes. */
375 wmb();
376
377 __raw_writel((__force u32) cpu_to_be32((1 << HCR_GO_BIT) |
378 (cmd->toggle << HCR_T_BIT) |
379 (event ? (1 << HCR_E_BIT) : 0) |
380 (op_modifier << HCR_OPMOD_SHIFT) |
e8f081aa 381 op), hcr + 6);
2e61c646
RD		 382
383 /*
384 * Make sure that our HCR writes don't get mixed in with
385 * writes from another CPU starting a FW command.
386 */
387 mmiowb();
388
225c7b1f
RD		 389 cmd->toggle = cmd->toggle ^ 1;
390
391 ret = 0;
392
393out:
394 mutex_unlock(&cmd->hcr_mutex);
395 return ret;
396}
397
e8f081aa
YP		 398static int mlx4_slave_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
399 int out_is_imm, u32 in_modifier, u8 op_modifier,
400 u16 op, unsigned long timeout)
401{
402 struct mlx4_priv *priv = mlx4_priv(dev);
403 struct mlx4_vhcr_cmd *vhcr = priv->mfunc.vhcr;
404 int ret;
405
f3d4c89e
RD		 406 mutex_lock(&priv->cmd.slave_cmd_mutex);
407
e8f081aa
YP		 408 vhcr->in_param = cpu_to_be64(in_param);
409 vhcr->out_param = out_param ? cpu_to_be64(*out_param) : 0;
410 vhcr->in_modifier = cpu_to_be32(in_modifier);
411 vhcr->opcode = cpu_to_be16((((u16) op_modifier) << 12) | (op & 0xfff));
412 vhcr->token = cpu_to_be16(CMD_POLL_TOKEN);
413 vhcr->status = 0;
414 vhcr->flags = !!(priv->cmd.use_events) << 6;
f3d4c89e 415
e8f081aa
YP		 416 if (mlx4_is_master(dev)) {
417 ret = mlx4_master_process_vhcr(dev, dev->caps.function, vhcr);
418 if (!ret) {
419 if (out_is_imm) {
420 if (out_param)
421 *out_param =
422 be64_to_cpu(vhcr->out_param);
423 else {
1a91de28
JP		 424 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
425 op);
72be84f1 426 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 427 }
428 }
72be84f1 429 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa
YP		 430 }
431 } else {
432 ret = mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_POST, 0,
433 MLX4_COMM_TIME + timeout);
434 if (!ret) {
435 if (out_is_imm) {
436 if (out_param)
437 *out_param =
438 be64_to_cpu(vhcr->out_param);
439 else {
1a91de28
JP		 440 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
441 op);
72be84f1 442 vhcr->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 443 }
444 }
72be84f1 445 ret = mlx4_status_to_errno(vhcr->status);
e8f081aa 446 } else
1a91de28
JP		 447 mlx4_err(dev, "failed execution of VHCR_POST command opcode 0x%x\n",
448 op);
e8f081aa 449 }
f3d4c89e
RD		 450
451 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 452 return ret;
453}
454
225c7b1f
RD		 455static int mlx4_cmd_poll(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
456 int out_is_imm, u32 in_modifier, u8 op_modifier,
457 u16 op, unsigned long timeout)
458{
459 struct mlx4_priv *priv = mlx4_priv(dev);
460 void __iomem *hcr = priv->cmd.hcr;
461 int err = 0;
462 unsigned long end;
e8f081aa 463 u32 stat;
225c7b1f
RD		 464
465 down(&priv->cmd.poll_sem);
466
57dbf29a
KSS		 467 if (pci_channel_offline(dev->pdev)) {
468 /*
469 * Device is going through error recovery
470 * and cannot accept commands.
471 */
472 err = -EIO;
473 goto out;
474 }
475
c05a116f
EP		 476 if (out_is_imm && !out_param) {
477 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
478 op);
479 err = -EINVAL;
480 goto out;
481 }
482
225c7b1f
RD		 483 err = mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
484 in_modifier, op_modifier, op, CMD_POLL_TOKEN, 0);
485 if (err)
486 goto out;
487
488 end = msecs_to_jiffies(timeout) + jiffies;
57dbf29a
KSS		 489 while (cmd_pending(dev) && time_before(jiffies, end)) {
490 if (pci_channel_offline(dev->pdev)) {
491 /*
492 * Device is going through error recovery
493 * and cannot accept commands.
494 */
495 err = -EIO;
496 goto out;
497 }
498
225c7b1f 499 cond_resched();
57dbf29a 500 }
225c7b1f
RD		 501
502 if (cmd_pending(dev)) {
674925ed
DB		 503 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
504 op);
225c7b1f
RD		 505 err = -ETIMEDOUT;
506 goto out;
507 }
508
509 if (out_is_imm)
510 *out_param =
511 (u64) be32_to_cpu((__force __be32)
512 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET)) << 32 |
513 (u64) be32_to_cpu((__force __be32)
514 __raw_readl(hcr + HCR_OUT_PARAM_OFFSET + 4));
e8f081aa
YP		 515 stat = be32_to_cpu((__force __be32)
516 __raw_readl(hcr + HCR_STATUS_OFFSET)) >> 24;
517 err = mlx4_status_to_errno(stat);
518 if (err)
519 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
520 op, stat);
225c7b1f
RD		 521
522out:
523 up(&priv->cmd.poll_sem);
524 return err;
525}
526
527void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param)
528{
529 struct mlx4_priv *priv = mlx4_priv(dev);
530 struct mlx4_cmd_context *context =
531 &priv->cmd.context[token & priv->cmd.token_mask];
532
533 /* previously timed out command completing at long last */
534 if (token != context->token)
535 return;
536
e8f081aa 537 context->fw_status = status;
225c7b1f
RD		 538 context->result = mlx4_status_to_errno(status);
539 context->out_param = out_param;
540
225c7b1f
RD		 541 complete(&context->done);
542}
543
544static int mlx4_cmd_wait(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
545 int out_is_imm, u32 in_modifier, u8 op_modifier,
546 u16 op, unsigned long timeout)
547{
548 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
549 struct mlx4_cmd_context *context;
550 int err = 0;
551
552 down(&cmd->event_sem);
553
554 spin_lock(&cmd->context_lock);
555 BUG_ON(cmd->free_head < 0);
556 context = &cmd->context[cmd->free_head];
0981582d 557 context->token += cmd->token_mask + 1;
225c7b1f
RD		 558 cmd->free_head = context->next;
559 spin_unlock(&cmd->context_lock);
560
c05a116f
EP		 561 if (out_is_imm && !out_param) {
562 mlx4_err(dev, "response expected while output mailbox is NULL for command 0x%x\n",
563 op);
564 err = -EINVAL;
565 goto out;
566 }
567
225c7b1f
RD		 568 init_completion(&context->done);
569
570 mlx4_cmd_post(dev, in_param, out_param ? *out_param : 0,
571 in_modifier, op_modifier, op, context->token, 1);
572
e8f081aa
YP		 573 if (!wait_for_completion_timeout(&context->done,
574 msecs_to_jiffies(timeout))) {
674925ed
DB		 575 mlx4_warn(dev, "command 0x%x timed out (go bit not cleared)\n",
576 op);
225c7b1f
RD		 577 err = -EBUSY;
578 goto out;
579 }
580
581 err = context->result;
e8f081aa
YP		 582 if (err) {
583 mlx4_err(dev, "command 0x%x failed: fw status = 0x%x\n",
584 op, context->fw_status);
225c7b1f 585 goto out;
e8f081aa 586 }
225c7b1f
RD		 587
588 if (out_is_imm)
589 *out_param = context->out_param;
590
591out:
592 spin_lock(&cmd->context_lock);
593 context->next = cmd->free_head;
594 cmd->free_head = context - cmd->context;
595 spin_unlock(&cmd->context_lock);
596
597 up(&cmd->event_sem);
598 return err;
599}
600
601int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param,
602 int out_is_imm, u32 in_modifier, u8 op_modifier,
f9baff50 603 u16 op, unsigned long timeout, int native)
225c7b1f 604{
57dbf29a
KSS		 605 if (pci_channel_offline(dev->pdev))
606 return -EIO;
607
e8f081aa
YP		 608 if (!mlx4_is_mfunc(dev) || (native && mlx4_is_master(dev))) {
609 if (mlx4_priv(dev)->cmd.use_events)
610 return mlx4_cmd_wait(dev, in_param, out_param,
611 out_is_imm, in_modifier,
612 op_modifier, op, timeout);
613 else
614 return mlx4_cmd_poll(dev, in_param, out_param,
615 out_is_imm, in_modifier,
616 op_modifier, op, timeout);
617 }
618 return mlx4_slave_cmd(dev, in_param, out_param, out_is_imm,
619 in_modifier, op_modifier, op, timeout);
225c7b1f
RD		 620}
621EXPORT_SYMBOL_GPL(__mlx4_cmd);
622
e8f081aa
YP		 623
624static int mlx4_ARM_COMM_CHANNEL(struct mlx4_dev *dev)
625{
626 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_ARM_COMM_CHANNEL,
627 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
628}
629
630static int mlx4_ACCESS_MEM(struct mlx4_dev *dev, u64 master_addr,
631 int slave, u64 slave_addr,
632 int size, int is_read)
633{
634 u64 in_param;
635 u64 out_param;
636
637 if ((slave_addr & 0xfff) | (master_addr & 0xfff) |
638 (slave & ~0x7f) | (size & 0xff)) {
1a91de28
JP		 639 mlx4_err(dev, "Bad access mem params - slave_addr:0x%llx master_addr:0x%llx slave_id:%d size:%d\n",
640 slave_addr, master_addr, slave, size);
e8f081aa
YP		 641 return -EINVAL;
642 }
643
644 if (is_read) {
645 in_param = (u64) slave | slave_addr;
646 out_param = (u64) dev->caps.function | master_addr;
647 } else {
648 in_param = (u64) dev->caps.function | master_addr;
649 out_param = (u64) slave | slave_addr;
650 }
651
652 return mlx4_cmd_imm(dev, in_param, &out_param, size, 0,
653 MLX4_CMD_ACCESS_MEM,
654 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
655}
656
0a9a0188
JM		 657static int query_pkey_block(struct mlx4_dev *dev, u8 port, u16 index, u16 *pkey,
658 struct mlx4_cmd_mailbox *inbox,
659 struct mlx4_cmd_mailbox *outbox)
660{
661 struct ib_smp *in_mad = (struct ib_smp *)(inbox->buf);
662 struct ib_smp *out_mad = (struct ib_smp *)(outbox->buf);
663 int err;
664 int i;
665
666 if (index & 0x1f)
667 return -EINVAL;
668
669 in_mad->attr_mod = cpu_to_be32(index / 32);
670
671 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, port, 3,
672 MLX4_CMD_MAD_IFC, MLX4_CMD_TIME_CLASS_C,
673 MLX4_CMD_NATIVE);
674 if (err)
675 return err;
676
677 for (i = 0; i < 32; ++i)
678 pkey[i] = be16_to_cpu(((__be16 *) out_mad->data)[i]);
679
680 return err;
681}
682
683static int get_full_pkey_table(struct mlx4_dev *dev, u8 port, u16 *table,
684 struct mlx4_cmd_mailbox *inbox,
685 struct mlx4_cmd_mailbox *outbox)
686{
687 int i;
688 int err;
689
690 for (i = 0; i < dev->caps.pkey_table_len[port]; i += 32) {
691 err = query_pkey_block(dev, port, i, table + i, inbox, outbox);
692 if (err)
693 return err;
694 }
695
696 return 0;
697}
698#define PORT_CAPABILITY_LOCATION_IN_SMP 20
699#define PORT_STATE_OFFSET 32
700
701static enum ib_port_state vf_port_state(struct mlx4_dev *dev, int port, int vf)
702{
a0c64a17
JM		 703 if (mlx4_get_slave_port_state(dev, vf, port) == SLAVE_PORT_UP)
704 return IB_PORT_ACTIVE;
705 else
706 return IB_PORT_DOWN;
0a9a0188
JM		 707}
708
709static int mlx4_MAD_IFC_wrapper(struct mlx4_dev *dev, int slave,
710 struct mlx4_vhcr *vhcr,
711 struct mlx4_cmd_mailbox *inbox,
712 struct mlx4_cmd_mailbox *outbox,
713 struct mlx4_cmd_info *cmd)
714{
715 struct ib_smp *smp = inbox->buf;
716 u32 index;
717 u8 port;
97982f5a 718 u8 opcode_modifier;
0a9a0188
JM		 719 u16 *table;
720 int err;
721 int vidx, pidx;
97982f5a 722 int network_view;
0a9a0188
JM		 723 struct mlx4_priv *priv = mlx4_priv(dev);
724 struct ib_smp *outsmp = outbox->buf;
725 __be16 *outtab = (__be16 *)(outsmp->data);
726 __be32 slave_cap_mask;
afa8fd1d 727 __be64 slave_node_guid;
97982f5a 728
0a9a0188
JM		 729 port = vhcr->in_modifier;
730
97982f5a
JM		 731 /* network-view bit is for driver use only, and should not be passed to FW */
732 opcode_modifier = vhcr->op_modifier & ~0x8; /* clear netw view bit */
733 network_view = !!(vhcr->op_modifier & 0x8);
734
0a9a0188
JM		 735 if (smp->base_version == 1 &&
736 smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
737 smp->class_version == 1) {
97982f5a
JM		 738 /* host view is paravirtualized */
739 if (!network_view && smp->method == IB_MGMT_METHOD_GET) {
0a9a0188
JM		 740 if (smp->attr_id == IB_SMP_ATTR_PKEY_TABLE) {
741 index = be32_to_cpu(smp->attr_mod);
742 if (port < 1 || port > dev->caps.num_ports)
743 return -EINVAL;
744 table = kcalloc(dev->caps.pkey_table_len[port], sizeof *table, GFP_KERNEL);
745 if (!table)
746 return -ENOMEM;
747 /* need to get the full pkey table because the paravirtualized
748 * pkeys may be scattered among several pkey blocks.
749 */
750 err = get_full_pkey_table(dev, port, table, inbox, outbox);
751 if (!err) {
752 for (vidx = index * 32; vidx < (index + 1) * 32; ++vidx) {
753 pidx = priv->virt2phys_pkey[slave][port - 1][vidx];
754 outtab[vidx % 32] = cpu_to_be16(table[pidx]);
755 }
756 }
757 kfree(table);
758 return err;
759 }
760 if (smp->attr_id == IB_SMP_ATTR_PORT_INFO) {
761 /*get the slave specific caps:*/
762 /*do the command */
763 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 764 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 765 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
766 /* modify the response for slaves */
767 if (!err && slave != mlx4_master_func_num(dev)) {
768 u8 *state = outsmp->data + PORT_STATE_OFFSET;
769
770 *state = (*state & 0xf0) | vf_port_state(dev, port, slave);
771 slave_cap_mask = priv->mfunc.master.slave_state[slave].ib_cap_mask[port];
772 memcpy(outsmp->data + PORT_CAPABILITY_LOCATION_IN_SMP, &slave_cap_mask, 4);
773 }
774 return err;
775 }
776 if (smp->attr_id == IB_SMP_ATTR_GUID_INFO) {
777 /* compute slave's gid block */
778 smp->attr_mod = cpu_to_be32(slave / 8);
779 /* execute cmd */
780 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 781 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 782 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
783 if (!err) {
784 /* if needed, move slave gid to index 0 */
785 if (slave % 8)
786 memcpy(outsmp->data,
787 outsmp->data + (slave % 8) * 8, 8);
788 /* delete all other gids */
789 memset(outsmp->data + 8, 0, 56);
790 }
791 return err;
792 }
afa8fd1d
JM		 793 if (smp->attr_id == IB_SMP_ATTR_NODE_INFO) {
794 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 795 vhcr->in_modifier, opcode_modifier,
afa8fd1d
JM		 796 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
797 if (!err) {
798 slave_node_guid = mlx4_get_slave_node_guid(dev, slave);
799 memcpy(outsmp->data + 12, &slave_node_guid, 8);
800 }
801 return err;
802 }
0a9a0188
JM		 803 }
804 }
97982f5a
JM		 805
806 /* Non-privileged VFs are only allowed "host" view LID-routed 'Get' MADs.
807 * These are the MADs used by ib verbs (such as ib_query_gids).
808 */
0a9a0188 809 if (slave != mlx4_master_func_num(dev) &&
97982f5a
JM		 810 !mlx4_vf_smi_enabled(dev, slave, port)) {
811 if (!(smp->mgmt_class == IB_MGMT_CLASS_SUBN_LID_ROUTED &&
812 smp->method == IB_MGMT_METHOD_GET) || network_view) {
813 mlx4_err(dev, "Unprivileged slave %d is trying to execute a Subnet MGMT MAD, class 0x%x, method 0x%x, view=%s for attr 0x%x. Rejecting\n",
814 slave, smp->method, smp->mgmt_class,
815 network_view ? "Network" : "Host",
816 be16_to_cpu(smp->attr_id));
817 return -EPERM;
818 }
0a9a0188 819 }
97982f5a 820
0a9a0188 821 return mlx4_cmd_box(dev, inbox->dma, outbox->dma,
97982f5a 822 vhcr->in_modifier, opcode_modifier,
0a9a0188
JM		 823 vhcr->op, MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE);
824}
825
b7475794 826static int mlx4_CMD_EPERM_wrapper(struct mlx4_dev *dev, int slave,
fe6f700d
YP		 827 struct mlx4_vhcr *vhcr,
828 struct mlx4_cmd_mailbox *inbox,
829 struct mlx4_cmd_mailbox *outbox,
830 struct mlx4_cmd_info *cmd)
831{
832 return -EPERM;
833}
834
e8f081aa
YP		 835int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
836 struct mlx4_vhcr *vhcr,
837 struct mlx4_cmd_mailbox *inbox,
838 struct mlx4_cmd_mailbox *outbox,
839 struct mlx4_cmd_info *cmd)
840{
841 u64 in_param;
842 u64 out_param;
843 int err;
844
845 in_param = cmd->has_inbox ? (u64) inbox->dma : vhcr->in_param;
846 out_param = cmd->has_outbox ? (u64) outbox->dma : vhcr->out_param;
847 if (cmd->encode_slave_id) {
848 in_param &= 0xffffffffffffff00ll;
849 in_param |= slave;
850 }
851
852 err = __mlx4_cmd(dev, in_param, &out_param, cmd->out_is_imm,
853 vhcr->in_modifier, vhcr->op_modifier, vhcr->op,
854 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
855
856 if (cmd->out_is_imm)
857 vhcr->out_param = out_param;
858
859 return err;
860}
861
862static struct mlx4_cmd_info cmd_info[] = {
863 {
864 .opcode = MLX4_CMD_QUERY_FW,
865 .has_inbox = false,
866 .has_outbox = true,
867 .out_is_imm = false,
868 .encode_slave_id = false,
869 .verify = NULL,
b91cb3eb 870 .wrapper = mlx4_QUERY_FW_wrapper
e8f081aa
YP		 871 },
872 {
873 .opcode = MLX4_CMD_QUERY_HCA,
874 .has_inbox = false,
875 .has_outbox = true,
876 .out_is_imm = false,
877 .encode_slave_id = false,
878 .verify = NULL,
879 .wrapper = NULL
880 },
881 {
882 .opcode = MLX4_CMD_QUERY_DEV_CAP,
883 .has_inbox = false,
884 .has_outbox = true,
885 .out_is_imm = false,
886 .encode_slave_id = false,
887 .verify = NULL,
b91cb3eb 888 .wrapper = mlx4_QUERY_DEV_CAP_wrapper
e8f081aa 889 },
c82e9aa0
EC		 890 {
891 .opcode = MLX4_CMD_QUERY_FUNC_CAP,
892 .has_inbox = false,
893 .has_outbox = true,
894 .out_is_imm = false,
895 .encode_slave_id = false,
896 .verify = NULL,
897 .wrapper = mlx4_QUERY_FUNC_CAP_wrapper
898 },
899 {
900 .opcode = MLX4_CMD_QUERY_ADAPTER,
901 .has_inbox = false,
902 .has_outbox = true,
903 .out_is_imm = false,
904 .encode_slave_id = false,
905 .verify = NULL,
906 .wrapper = NULL
907 },
908 {
909 .opcode = MLX4_CMD_INIT_PORT,
910 .has_inbox = false,
911 .has_outbox = false,
912 .out_is_imm = false,
913 .encode_slave_id = false,
914 .verify = NULL,
915 .wrapper = mlx4_INIT_PORT_wrapper
916 },
917 {
918 .opcode = MLX4_CMD_CLOSE_PORT,
919 .has_inbox = false,
920 .has_outbox = false,
921 .out_is_imm = false,
922 .encode_slave_id = false,
923 .verify = NULL,
924 .wrapper = mlx4_CLOSE_PORT_wrapper
925 },
926 {
927 .opcode = MLX4_CMD_QUERY_PORT,
928 .has_inbox = false,
929 .has_outbox = true,
930 .out_is_imm = false,
931 .encode_slave_id = false,
932 .verify = NULL,
933 .wrapper = mlx4_QUERY_PORT_wrapper
934 },
ffe455ad
EE		 935 {
936 .opcode = MLX4_CMD_SET_PORT,
937 .has_inbox = true,
938 .has_outbox = false,
939 .out_is_imm = false,
940 .encode_slave_id = false,
941 .verify = NULL,
942 .wrapper = mlx4_SET_PORT_wrapper
943 },
c82e9aa0
EC		 944 {
945 .opcode = MLX4_CMD_MAP_EQ,
946 .has_inbox = false,
947 .has_outbox = false,
948 .out_is_imm = false,
949 .encode_slave_id = false,
950 .verify = NULL,
951 .wrapper = mlx4_MAP_EQ_wrapper
952 },
953 {
954 .opcode = MLX4_CMD_SW2HW_EQ,
955 .has_inbox = true,
956 .has_outbox = false,
957 .out_is_imm = false,
958 .encode_slave_id = true,
959 .verify = NULL,
960 .wrapper = mlx4_SW2HW_EQ_wrapper
961 },
962 {
963 .opcode = MLX4_CMD_HW_HEALTH_CHECK,
964 .has_inbox = false,
965 .has_outbox = false,
966 .out_is_imm = false,
967 .encode_slave_id = false,
968 .verify = NULL,
969 .wrapper = NULL
970 },
971 {
972 .opcode = MLX4_CMD_NOP,
973 .has_inbox = false,
974 .has_outbox = false,
975 .out_is_imm = false,
976 .encode_slave_id = false,
977 .verify = NULL,
978 .wrapper = NULL
979 },
d18f141a
OG		 980 {
981 .opcode = MLX4_CMD_CONFIG_DEV,
982 .has_inbox = false,
983 .has_outbox = false,
984 .out_is_imm = false,
985 .encode_slave_id = false,
986 .verify = NULL,
987 .wrapper = mlx4_CMD_EPERM_wrapper
988 },
c82e9aa0
EC		 989 {
990 .opcode = MLX4_CMD_ALLOC_RES,
991 .has_inbox = false,
992 .has_outbox = false,
993 .out_is_imm = true,
994 .encode_slave_id = false,
995 .verify = NULL,
996 .wrapper = mlx4_ALLOC_RES_wrapper
997 },
998 {
999 .opcode = MLX4_CMD_FREE_RES,
1000 .has_inbox = false,
1001 .has_outbox = false,
1002 .out_is_imm = false,
1003 .encode_slave_id = false,
1004 .verify = NULL,
1005 .wrapper = mlx4_FREE_RES_wrapper
1006 },
1007 {
1008 .opcode = MLX4_CMD_SW2HW_MPT,
1009 .has_inbox = true,
1010 .has_outbox = false,
1011 .out_is_imm = false,
1012 .encode_slave_id = true,
1013 .verify = NULL,
1014 .wrapper = mlx4_SW2HW_MPT_wrapper
1015 },
1016 {
1017 .opcode = MLX4_CMD_QUERY_MPT,
1018 .has_inbox = false,
1019 .has_outbox = true,
1020 .out_is_imm = false,
1021 .encode_slave_id = false,
1022 .verify = NULL,
1023 .wrapper = mlx4_QUERY_MPT_wrapper
1024 },
1025 {
1026 .opcode = MLX4_CMD_HW2SW_MPT,
1027 .has_inbox = false,
1028 .has_outbox = false,
1029 .out_is_imm = false,
1030 .encode_slave_id = false,
1031 .verify = NULL,
1032 .wrapper = mlx4_HW2SW_MPT_wrapper
1033 },
1034 {
1035 .opcode = MLX4_CMD_READ_MTT,
1036 .has_inbox = false,
1037 .has_outbox = true,
1038 .out_is_imm = false,
1039 .encode_slave_id = false,
1040 .verify = NULL,
1041 .wrapper = NULL
1042 },
1043 {
1044 .opcode = MLX4_CMD_WRITE_MTT,
1045 .has_inbox = true,
1046 .has_outbox = false,
1047 .out_is_imm = false,
1048 .encode_slave_id = false,
1049 .verify = NULL,
1050 .wrapper = mlx4_WRITE_MTT_wrapper
1051 },
1052 {
1053 .opcode = MLX4_CMD_SYNC_TPT,
1054 .has_inbox = true,
1055 .has_outbox = false,
1056 .out_is_imm = false,
1057 .encode_slave_id = false,
1058 .verify = NULL,
1059 .wrapper = NULL
1060 },
1061 {
1062 .opcode = MLX4_CMD_HW2SW_EQ,
1063 .has_inbox = false,
1064 .has_outbox = true,
1065 .out_is_imm = false,
1066 .encode_slave_id = true,
1067 .verify = NULL,
1068 .wrapper = mlx4_HW2SW_EQ_wrapper
1069 },
1070 {
1071 .opcode = MLX4_CMD_QUERY_EQ,
1072 .has_inbox = false,
1073 .has_outbox = true,
1074 .out_is_imm = false,
1075 .encode_slave_id = true,
1076 .verify = NULL,
1077 .wrapper = mlx4_QUERY_EQ_wrapper
1078 },
1079 {
1080 .opcode = MLX4_CMD_SW2HW_CQ,
1081 .has_inbox = true,
1082 .has_outbox = false,
1083 .out_is_imm = false,
1084 .encode_slave_id = true,
1085 .verify = NULL,
1086 .wrapper = mlx4_SW2HW_CQ_wrapper
1087 },
1088 {
1089 .opcode = MLX4_CMD_HW2SW_CQ,
1090 .has_inbox = false,
1091 .has_outbox = false,
1092 .out_is_imm = false,
1093 .encode_slave_id = false,
1094 .verify = NULL,
1095 .wrapper = mlx4_HW2SW_CQ_wrapper
1096 },
1097 {
1098 .opcode = MLX4_CMD_QUERY_CQ,
1099 .has_inbox = false,
1100 .has_outbox = true,
1101 .out_is_imm = false,
1102 .encode_slave_id = false,
1103 .verify = NULL,
1104 .wrapper = mlx4_QUERY_CQ_wrapper
1105 },
1106 {
1107 .opcode = MLX4_CMD_MODIFY_CQ,
1108 .has_inbox = true,
1109 .has_outbox = false,
1110 .out_is_imm = true,
1111 .encode_slave_id = false,
1112 .verify = NULL,
1113 .wrapper = mlx4_MODIFY_CQ_wrapper
1114 },
1115 {
1116 .opcode = MLX4_CMD_SW2HW_SRQ,
1117 .has_inbox = true,
1118 .has_outbox = false,
1119 .out_is_imm = false,
1120 .encode_slave_id = true,
1121 .verify = NULL,
1122 .wrapper = mlx4_SW2HW_SRQ_wrapper
1123 },
1124 {
1125 .opcode = MLX4_CMD_HW2SW_SRQ,
1126 .has_inbox = false,
1127 .has_outbox = false,
1128 .out_is_imm = false,
1129 .encode_slave_id = false,
1130 .verify = NULL,
1131 .wrapper = mlx4_HW2SW_SRQ_wrapper
1132 },
1133 {
1134 .opcode = MLX4_CMD_QUERY_SRQ,
1135 .has_inbox = false,
1136 .has_outbox = true,
1137 .out_is_imm = false,
1138 .encode_slave_id = false,
1139 .verify = NULL,
1140 .wrapper = mlx4_QUERY_SRQ_wrapper
1141 },
1142 {
1143 .opcode = MLX4_CMD_ARM_SRQ,
1144 .has_inbox = false,
1145 .has_outbox = false,
1146 .out_is_imm = false,
1147 .encode_slave_id = false,
1148 .verify = NULL,
1149 .wrapper = mlx4_ARM_SRQ_wrapper
1150 },
1151 {
1152 .opcode = MLX4_CMD_RST2INIT_QP,
1153 .has_inbox = true,
1154 .has_outbox = false,
1155 .out_is_imm = false,
1156 .encode_slave_id = true,
1157 .verify = NULL,
1158 .wrapper = mlx4_RST2INIT_QP_wrapper
1159 },
1160 {
1161 .opcode = MLX4_CMD_INIT2INIT_QP,
1162 .has_inbox = true,
1163 .has_outbox = false,
1164 .out_is_imm = false,
1165 .encode_slave_id = false,
1166 .verify = NULL,
54679e14 1167 .wrapper = mlx4_INIT2INIT_QP_wrapper
c82e9aa0
EC		 1168 },
1169 {
1170 .opcode = MLX4_CMD_INIT2RTR_QP,
1171 .has_inbox = true,
1172 .has_outbox = false,
1173 .out_is_imm = false,
1174 .encode_slave_id = false,
1175 .verify = NULL,
1176 .wrapper = mlx4_INIT2RTR_QP_wrapper
1177 },
1178 {
1179 .opcode = MLX4_CMD_RTR2RTS_QP,
1180 .has_inbox = true,
1181 .has_outbox = false,
1182 .out_is_imm = false,
1183 .encode_slave_id = false,
1184 .verify = NULL,
54679e14 1185 .wrapper = mlx4_RTR2RTS_QP_wrapper
c82e9aa0
EC		 1186 },
1187 {
1188 .opcode = MLX4_CMD_RTS2RTS_QP,
1189 .has_inbox = true,
1190 .has_outbox = false,
1191 .out_is_imm = false,
1192 .encode_slave_id = false,
1193 .verify = NULL,
54679e14 1194 .wrapper = mlx4_RTS2RTS_QP_wrapper
c82e9aa0
EC		 1195 },
1196 {
1197 .opcode = MLX4_CMD_SQERR2RTS_QP,
1198 .has_inbox = true,
1199 .has_outbox = false,
1200 .out_is_imm = false,
1201 .encode_slave_id = false,
1202 .verify = NULL,
54679e14 1203 .wrapper = mlx4_SQERR2RTS_QP_wrapper
c82e9aa0
EC		 1204 },
1205 {
1206 .opcode = MLX4_CMD_2ERR_QP,
1207 .has_inbox = false,
1208 .has_outbox = false,
1209 .out_is_imm = false,
1210 .encode_slave_id = false,
1211 .verify = NULL,
1212 .wrapper = mlx4_GEN_QP_wrapper
1213 },
1214 {
1215 .opcode = MLX4_CMD_RTS2SQD_QP,
1216 .has_inbox = false,
1217 .has_outbox = false,
1218 .out_is_imm = false,
1219 .encode_slave_id = false,
1220 .verify = NULL,
1221 .wrapper = mlx4_GEN_QP_wrapper
1222 },
1223 {
1224 .opcode = MLX4_CMD_SQD2SQD_QP,
1225 .has_inbox = true,
1226 .has_outbox = false,
1227 .out_is_imm = false,
1228 .encode_slave_id = false,
1229 .verify = NULL,
54679e14 1230 .wrapper = mlx4_SQD2SQD_QP_wrapper
c82e9aa0
EC		 1231 },
1232 {
1233 .opcode = MLX4_CMD_SQD2RTS_QP,
1234 .has_inbox = true,
1235 .has_outbox = false,
1236 .out_is_imm = false,
1237 .encode_slave_id = false,
1238 .verify = NULL,
54679e14 1239 .wrapper = mlx4_SQD2RTS_QP_wrapper
c82e9aa0
EC		 1240 },
1241 {
1242 .opcode = MLX4_CMD_2RST_QP,
1243 .has_inbox = false,
1244 .has_outbox = false,
1245 .out_is_imm = false,
1246 .encode_slave_id = false,
1247 .verify = NULL,
1248 .wrapper = mlx4_2RST_QP_wrapper
1249 },
1250 {
1251 .opcode = MLX4_CMD_QUERY_QP,
1252 .has_inbox = false,
1253 .has_outbox = true,
1254 .out_is_imm = false,
1255 .encode_slave_id = false,
1256 .verify = NULL,
1257 .wrapper = mlx4_GEN_QP_wrapper
1258 },
1259 {
1260 .opcode = MLX4_CMD_SUSPEND_QP,
1261 .has_inbox = false,
1262 .has_outbox = false,
1263 .out_is_imm = false,
1264 .encode_slave_id = false,
1265 .verify = NULL,
1266 .wrapper = mlx4_GEN_QP_wrapper
1267 },
1268 {
1269 .opcode = MLX4_CMD_UNSUSPEND_QP,
1270 .has_inbox = false,
1271 .has_outbox = false,
1272 .out_is_imm = false,
1273 .encode_slave_id = false,
1274 .verify = NULL,
1275 .wrapper = mlx4_GEN_QP_wrapper
1276 },
b01978ca
JM		 1277 {
1278 .opcode = MLX4_CMD_UPDATE_QP,
ce8d9e0d 1279 .has_inbox = true,
b01978ca
JM		 1280 .has_outbox = false,
1281 .out_is_imm = false,
1282 .encode_slave_id = false,
1283 .verify = NULL,
ce8d9e0d 1284 .wrapper = mlx4_UPDATE_QP_wrapper
b01978ca 1285 },
fe6f700d
YP		 1286 {
1287 .opcode = MLX4_CMD_GET_OP_REQ,
1288 .has_inbox = false,
1289 .has_outbox = false,
1290 .out_is_imm = false,
1291 .encode_slave_id = false,
1292 .verify = NULL,
b7475794 1293 .wrapper = mlx4_CMD_EPERM_wrapper,
fe6f700d 1294 },
0a9a0188
JM		 1295 {
1296 .opcode = MLX4_CMD_CONF_SPECIAL_QP,
1297 .has_inbox = false,
1298 .has_outbox = false,
1299 .out_is_imm = false,
1300 .encode_slave_id = false,
1301 .verify = NULL, /* XXX verify: only demux can do this */
1302 .wrapper = NULL
1303 },
1304 {
1305 .opcode = MLX4_CMD_MAD_IFC,
1306 .has_inbox = true,
1307 .has_outbox = true,
1308 .out_is_imm = false,
1309 .encode_slave_id = false,
1310 .verify = NULL,
1311 .wrapper = mlx4_MAD_IFC_wrapper
1312 },
114840c3
JM		 1313 {
1314 .opcode = MLX4_CMD_MAD_DEMUX,
1315 .has_inbox = false,
1316 .has_outbox = false,
1317 .out_is_imm = false,
1318 .encode_slave_id = false,
1319 .verify = NULL,
1320 .wrapper = mlx4_CMD_EPERM_wrapper
1321 },
c82e9aa0
EC		 1322 {
1323 .opcode = MLX4_CMD_QUERY_IF_STAT,
1324 .has_inbox = false,
1325 .has_outbox = true,
1326 .out_is_imm = false,
1327 .encode_slave_id = false,
1328 .verify = NULL,
1329 .wrapper = mlx4_QUERY_IF_STAT_wrapper
1330 },
1331 /* Native multicast commands are not available for guests */
1332 {
1333 .opcode = MLX4_CMD_QP_ATTACH,
1334 .has_inbox = true,
1335 .has_outbox = false,
1336 .out_is_imm = false,
1337 .encode_slave_id = false,
1338 .verify = NULL,
1339 .wrapper = mlx4_QP_ATTACH_wrapper
1340 },
0ec2c0f8
EE		 1341 {
1342 .opcode = MLX4_CMD_PROMISC,
1343 .has_inbox = false,
1344 .has_outbox = false,
1345 .out_is_imm = false,
1346 .encode_slave_id = false,
1347 .verify = NULL,
1348 .wrapper = mlx4_PROMISC_wrapper
1349 },
ffe455ad
EE		 1350 /* Ethernet specific commands */
1351 {
1352 .opcode = MLX4_CMD_SET_VLAN_FLTR,
1353 .has_inbox = true,
1354 .has_outbox = false,
1355 .out_is_imm = false,
1356 .encode_slave_id = false,
1357 .verify = NULL,
1358 .wrapper = mlx4_SET_VLAN_FLTR_wrapper
1359 },
1360 {
1361 .opcode = MLX4_CMD_SET_MCAST_FLTR,
1362 .has_inbox = false,
1363 .has_outbox = false,
1364 .out_is_imm = false,
1365 .encode_slave_id = false,
1366 .verify = NULL,
1367 .wrapper = mlx4_SET_MCAST_FLTR_wrapper
1368 },
1369 {
1370 .opcode = MLX4_CMD_DUMP_ETH_STATS,
1371 .has_inbox = false,
1372 .has_outbox = true,
1373 .out_is_imm = false,
1374 .encode_slave_id = false,
1375 .verify = NULL,
1376 .wrapper = mlx4_DUMP_ETH_STATS_wrapper
1377 },
c82e9aa0
EC		 1378 {
1379 .opcode = MLX4_CMD_INFORM_FLR_DONE,
1380 .has_inbox = false,
1381 .has_outbox = false,
1382 .out_is_imm = false,
1383 .encode_slave_id = false,
1384 .verify = NULL,
1385 .wrapper = NULL
1386 },
8fcfb4db
HHZ		 1387 /* flow steering commands */
1388 {
1389 .opcode = MLX4_QP_FLOW_STEERING_ATTACH,
1390 .has_inbox = true,
1391 .has_outbox = false,
1392 .out_is_imm = true,
1393 .encode_slave_id = false,
1394 .verify = NULL,
1395 .wrapper = mlx4_QP_FLOW_STEERING_ATTACH_wrapper
1396 },
1397 {
1398 .opcode = MLX4_QP_FLOW_STEERING_DETACH,
1399 .has_inbox = false,
1400 .has_outbox = false,
1401 .out_is_imm = false,
1402 .encode_slave_id = false,
1403 .verify = NULL,
1404 .wrapper = mlx4_QP_FLOW_STEERING_DETACH_wrapper
1405 },
4de65803
MB		 1406 {
1407 .opcode = MLX4_FLOW_STEERING_IB_UC_QP_RANGE,
1408 .has_inbox = false,
1409 .has_outbox = false,
1410 .out_is_imm = false,
1411 .encode_slave_id = false,
1412 .verify = NULL,
b7475794 1413 .wrapper = mlx4_CMD_EPERM_wrapper
4de65803 1414 },
e8f081aa
YP		 1415};
1416
1417static int mlx4_master_process_vhcr(struct mlx4_dev *dev, int slave,
1418 struct mlx4_vhcr_cmd *in_vhcr)
1419{
1420 struct mlx4_priv *priv = mlx4_priv(dev);
1421 struct mlx4_cmd_info *cmd = NULL;
1422 struct mlx4_vhcr_cmd *vhcr_cmd = in_vhcr ? in_vhcr : priv->mfunc.vhcr;
1423 struct mlx4_vhcr *vhcr;
1424 struct mlx4_cmd_mailbox *inbox = NULL;
1425 struct mlx4_cmd_mailbox *outbox = NULL;
1426 u64 in_param;
1427 u64 out_param;
1428 int ret = 0;
1429 int i;
72be84f1 1430 int err = 0;
e8f081aa
YP		 1431
1432 /* Create sw representation of Virtual HCR */
1433 vhcr = kzalloc(sizeof(struct mlx4_vhcr), GFP_KERNEL);
1434 if (!vhcr)
1435 return -ENOMEM;
1436
1437 /* DMA in the vHCR */
1438 if (!in_vhcr) {
1439 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1440 priv->mfunc.master.slave_state[slave].vhcr_dma,
1441 ALIGN(sizeof(struct mlx4_vhcr_cmd),
1442 MLX4_ACCESS_MEM_ALIGN), 1);
1443 if (ret) {
1a91de28
JP		 1444 mlx4_err(dev, "%s: Failed reading vhcr ret: 0x%x\n",
1445 __func__, ret);
e8f081aa
YP		 1446 kfree(vhcr);
1447 return ret;
1448 }
1449 }
1450
1451 /* Fill SW VHCR fields */
1452 vhcr->in_param = be64_to_cpu(vhcr_cmd->in_param);
1453 vhcr->out_param = be64_to_cpu(vhcr_cmd->out_param);
1454 vhcr->in_modifier = be32_to_cpu(vhcr_cmd->in_modifier);
1455 vhcr->token = be16_to_cpu(vhcr_cmd->token);
1456 vhcr->op = be16_to_cpu(vhcr_cmd->opcode) & 0xfff;
1457 vhcr->op_modifier = (u8) (be16_to_cpu(vhcr_cmd->opcode) >> 12);
1458 vhcr->e_bit = vhcr_cmd->flags & (1 << 6);
1459
1460 /* Lookup command */
1461 for (i = 0; i < ARRAY_SIZE(cmd_info); ++i) {
1462 if (vhcr->op == cmd_info[i].opcode) {
1463 cmd = &cmd_info[i];
1464 break;
1465 }
1466 }
1467 if (!cmd) {
1468 mlx4_err(dev, "Unknown command:0x%x accepted from slave:%d\n",
1469 vhcr->op, slave);
72be84f1 1470 vhcr_cmd->status = CMD_STAT_BAD_PARAM;
e8f081aa
YP		 1471 goto out_status;
1472 }
1473
1474 /* Read inbox */
1475 if (cmd->has_inbox) {
1476 vhcr->in_param &= INBOX_MASK;
1477 inbox = mlx4_alloc_cmd_mailbox(dev);
1478 if (IS_ERR(inbox)) {
72be84f1 1479 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1480 inbox = NULL;
72be84f1 1481 goto out_status;
e8f081aa
YP		 1482 }
1483
72be84f1
YP		 1484 if (mlx4_ACCESS_MEM(dev, inbox->dma, slave,
1485 vhcr->in_param,
1486 MLX4_MAILBOX_SIZE, 1)) {
e8f081aa
YP		 1487 mlx4_err(dev, "%s: Failed reading inbox (cmd:0x%x)\n",
1488 __func__, cmd->opcode);
72be84f1
YP		 1489 vhcr_cmd->status = CMD_STAT_INTERNAL_ERR;
1490 goto out_status;
e8f081aa
YP		 1491 }
1492 }
1493
1494 /* Apply permission and bound checks if applicable */
1495 if (cmd->verify && cmd->verify(dev, slave, vhcr, inbox)) {
1a91de28
JP		 1496 mlx4_warn(dev, "Command:0x%x from slave: %d failed protection checks for resource_id:%d\n",
1497 vhcr->op, slave, vhcr->in_modifier);
72be84f1 1498 vhcr_cmd->status = CMD_STAT_BAD_OP;
e8f081aa
YP		 1499 goto out_status;
1500 }
1501
1502 /* Allocate outbox */
1503 if (cmd->has_outbox) {
1504 outbox = mlx4_alloc_cmd_mailbox(dev);
1505 if (IS_ERR(outbox)) {
72be84f1 1506 vhcr_cmd->status = CMD_STAT_BAD_SIZE;
e8f081aa 1507 outbox = NULL;
72be84f1 1508 goto out_status;
e8f081aa
YP		 1509 }
1510 }
1511
1512 /* Execute the command! */
1513 if (cmd->wrapper) {
72be84f1
YP		 1514 err = cmd->wrapper(dev, slave, vhcr, inbox, outbox,
1515 cmd);
e8f081aa
YP		 1516 if (cmd->out_is_imm)
1517 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1518 } else {
1519 in_param = cmd->has_inbox ? (u64) inbox->dma :
1520 vhcr->in_param;
1521 out_param = cmd->has_outbox ? (u64) outbox->dma :
1522 vhcr->out_param;
72be84f1
YP		 1523 err = __mlx4_cmd(dev, in_param, &out_param,
1524 cmd->out_is_imm, vhcr->in_modifier,
1525 vhcr->op_modifier, vhcr->op,
1526 MLX4_CMD_TIME_CLASS_A,
1527 MLX4_CMD_NATIVE);
e8f081aa
YP		 1528
1529 if (cmd->out_is_imm) {
1530 vhcr->out_param = out_param;
1531 vhcr_cmd->out_param = cpu_to_be64(vhcr->out_param);
1532 }
1533 }
1534
72be84f1 1535 if (err) {
1a91de28 1536 mlx4_warn(dev, "vhcr command:0x%x slave:%d failed with error:%d, status %d\n",
72be84f1
YP		 1537 vhcr->op, slave, vhcr->errno, err);
1538 vhcr_cmd->status = mlx4_errno_to_status(err);
1539 goto out_status;
1540 }
1541
1542
e8f081aa 1543 /* Write outbox if command completed successfully */
72be84f1 1544 if (cmd->has_outbox && !vhcr_cmd->status) {
e8f081aa
YP		 1545 ret = mlx4_ACCESS_MEM(dev, outbox->dma, slave,
1546 vhcr->out_param,
1547 MLX4_MAILBOX_SIZE, MLX4_CMD_WRAPPED);
1548 if (ret) {
72be84f1
YP		 1549 /* If we failed to write back the outbox after the
1550 *command was successfully executed, we must fail this
1551 * slave, as it is now in undefined state */
e8f081aa
YP		 1552 mlx4_err(dev, "%s:Failed writing outbox\n", __func__);
1553 goto out;
1554 }
1555 }
1556
1557out_status:
1558 /* DMA back vhcr result */
1559 if (!in_vhcr) {
1560 ret = mlx4_ACCESS_MEM(dev, priv->mfunc.vhcr_dma, slave,
1561 priv->mfunc.master.slave_state[slave].vhcr_dma,
1562 ALIGN(sizeof(struct mlx4_vhcr),
1563 MLX4_ACCESS_MEM_ALIGN),
1564 MLX4_CMD_WRAPPED);
1565 if (ret)
1566 mlx4_err(dev, "%s:Failed writing vhcr result\n",
1567 __func__);
1568 else if (vhcr->e_bit &&
1569 mlx4_GEN_EQE(dev, slave, &priv->mfunc.master.cmd_eqe))
1a91de28
JP		 1570 mlx4_warn(dev, "Failed to generate command completion eqe for slave %d\n",
1571 slave);
e8f081aa
YP		 1572 }
1573
1574out:
1575 kfree(vhcr);
1576 mlx4_free_cmd_mailbox(dev, inbox);
1577 mlx4_free_cmd_mailbox(dev, outbox);
1578 return ret;
1579}
1580
f094668c 1581static int mlx4_master_immediate_activate_vlan_qos(struct mlx4_priv *priv,
b01978ca
JM		 1582 int slave, int port)
1583{
1584 struct mlx4_vport_oper_state *vp_oper;
1585 struct mlx4_vport_state *vp_admin;
1586 struct mlx4_vf_immed_vlan_work *work;
0a6eac24 1587 struct mlx4_dev *dev = &(priv->dev);
b01978ca
JM		 1588 int err;
1589 int admin_vlan_ix = NO_INDX;
1590
1591 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1592 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1593
1594 if (vp_oper->state.default_vlan == vp_admin->default_vlan &&
0a6eac24
RE		 1595 vp_oper->state.default_qos == vp_admin->default_qos &&
1596 vp_oper->state.link_state == vp_admin->link_state)
b01978ca
JM		 1597 return 0;
1598
0a6eac24 1599 if (!(priv->mfunc.master.slave_state[slave].active &&
f0f829bf 1600 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_UPDATE_QP)) {
0a6eac24
RE		 1601 /* even if the UPDATE_QP command isn't supported, we still want
1602 * to set this VF link according to the admin directive
1603 */
1604 vp_oper->state.link_state = vp_admin->link_state;
1605 return -1;
1606 }
1607
1608 mlx4_dbg(dev, "updating immediately admin params slave %d port %d\n",
1609 slave, port);
1a91de28
JP		 1610 mlx4_dbg(dev, "vlan %d QoS %d link down %d\n",
1611 vp_admin->default_vlan, vp_admin->default_qos,
1612 vp_admin->link_state);
0a6eac24 1613
b01978ca
JM		 1614 work = kzalloc(sizeof(*work), GFP_KERNEL);
1615 if (!work)
1616 return -ENOMEM;
1617
1618 if (vp_oper->state.default_vlan != vp_admin->default_vlan) {
f0f829bf
RE		 1619 if (MLX4_VGT != vp_admin->default_vlan) {
1620 err = __mlx4_register_vlan(&priv->dev, port,
1621 vp_admin->default_vlan,
1622 &admin_vlan_ix);
1623 if (err) {
1624 kfree(work);
1a91de28 1625 mlx4_warn(&priv->dev,
f0f829bf
RE		 1626 "No vlan resources slave %d, port %d\n",
1627 slave, port);
1628 return err;
1629 }
1630 } else {
1631 admin_vlan_ix = NO_INDX;
b01978ca
JM		 1632 }
1633 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_VLAN;
1a91de28 1634 mlx4_dbg(&priv->dev,
b01978ca
JM		 1635 "alloc vlan %d idx %d slave %d port %d\n",
1636 (int)(vp_admin->default_vlan),
1637 admin_vlan_ix, slave, port);
1638 }
1639
1640 /* save original vlan ix and vlan id */
1641 work->orig_vlan_id = vp_oper->state.default_vlan;
1642 work->orig_vlan_ix = vp_oper->vlan_idx;
1643
1644 /* handle new qos */
1645 if (vp_oper->state.default_qos != vp_admin->default_qos)
1646 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_QOS;
1647
1648 if (work->flags & MLX4_VF_IMMED_VLAN_FLAG_VLAN)
1649 vp_oper->vlan_idx = admin_vlan_ix;
1650
1651 vp_oper->state.default_vlan = vp_admin->default_vlan;
1652 vp_oper->state.default_qos = vp_admin->default_qos;
0a6eac24
RE		 1653 vp_oper->state.link_state = vp_admin->link_state;
1654
1655 if (vp_admin->link_state == IFLA_VF_LINK_STATE_DISABLE)
1656 work->flags |= MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE;
b01978ca
JM		 1657
1658 /* iterate over QPs owned by this slave, using UPDATE_QP */
1659 work->port = port;
1660 work->slave = slave;
1661 work->qos = vp_oper->state.default_qos;
1662 work->vlan_id = vp_oper->state.default_vlan;
1663 work->vlan_ix = vp_oper->vlan_idx;
1664 work->priv = priv;
1665 INIT_WORK(&work->work, mlx4_vf_immed_vlan_work_handler);
1666 queue_work(priv->mfunc.master.comm_wq, &work->work);
1667
1668 return 0;
1669}
1670
1671
0eb62b93
RE		 1672static int mlx4_master_activate_admin_state(struct mlx4_priv *priv, int slave)
1673{
3f7fb021
RE		 1674 int port, err;
1675 struct mlx4_vport_state *vp_admin;
1676 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1677 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1678 &priv->dev, slave);
1679 int min_port = find_first_bit(actv_ports.ports,
1680 priv->dev.caps.num_ports) + 1;
1681 int max_port = min_port - 1 +
1682 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1683
1684 for (port = min_port; port <= max_port; port++) {
1685 if (!test_bit(port - 1, actv_ports.ports))
1686 continue;
99ec41d0
JM		 1687 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1688 priv->mfunc.master.vf_admin[slave].enable_smi[port];
3f7fb021
RE		 1689 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1690 vp_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
1691 vp_oper->state = *vp_admin;
1692 if (MLX4_VGT != vp_admin->default_vlan) {
1693 err = __mlx4_register_vlan(&priv->dev, port,
1694 vp_admin->default_vlan, &(vp_oper->vlan_idx));
1695 if (err) {
1696 vp_oper->vlan_idx = NO_INDX;
1a91de28 1697 mlx4_warn(&priv->dev,
3f7fb021
RE		 1698 "No vlan resorces slave %d, port %d\n",
1699 slave, port);
1700 return err;
1701 }
1a91de28 1702 mlx4_dbg(&priv->dev, "alloc vlan %d idx %d slave %d port %d\n",
3f7fb021
RE		 1703 (int)(vp_oper->state.default_vlan),
1704 vp_oper->vlan_idx, slave, port);
1705 }
e6b6a231
RE		 1706 if (vp_admin->spoofchk) {
1707 vp_oper->mac_idx = __mlx4_register_mac(&priv->dev,
1708 port,
1709 vp_admin->mac);
1710 if (0 > vp_oper->mac_idx) {
1711 err = vp_oper->mac_idx;
1712 vp_oper->mac_idx = NO_INDX;
1a91de28 1713 mlx4_warn(&priv->dev,
e6b6a231
RE		 1714 "No mac resorces slave %d, port %d\n",
1715 slave, port);
1716 return err;
1717 }
1a91de28 1718 mlx4_dbg(&priv->dev, "alloc mac %llx idx %d slave %d port %d\n",
e6b6a231
RE		 1719 vp_oper->state.mac, vp_oper->mac_idx, slave, port);
1720 }
0eb62b93
RE		 1721 }
1722 return 0;
1723}
1724
3f7fb021
RE		 1725static void mlx4_master_deactivate_admin_state(struct mlx4_priv *priv, int slave)
1726{
1727 int port;
1728 struct mlx4_vport_oper_state *vp_oper;
449fc488
MB		 1729 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(
1730 &priv->dev, slave);
1731 int min_port = find_first_bit(actv_ports.ports,
1732 priv->dev.caps.num_ports) + 1;
1733 int max_port = min_port - 1 +
1734 bitmap_weight(actv_ports.ports, priv->dev.caps.num_ports);
1735
3f7fb021 1736
449fc488
MB		 1737 for (port = min_port; port <= max_port; port++) {
1738 if (!test_bit(port - 1, actv_ports.ports))
1739 continue;
99ec41d0
JM		 1740 priv->mfunc.master.vf_oper[slave].smi_enabled[port] =
1741 MLX4_VF_SMI_DISABLED;
3f7fb021
RE		 1742 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
1743 if (NO_INDX != vp_oper->vlan_idx) {
1744 __mlx4_unregister_vlan(&priv->dev,
2009d005 1745 port, vp_oper->state.default_vlan);
3f7fb021
RE		 1746 vp_oper->vlan_idx = NO_INDX;
1747 }
e6b6a231 1748 if (NO_INDX != vp_oper->mac_idx) {
c32b7dfb 1749 __mlx4_unregister_mac(&priv->dev, port, vp_oper->state.mac);
e6b6a231
RE		 1750 vp_oper->mac_idx = NO_INDX;
1751 }
3f7fb021
RE		 1752 }
1753 return;
1754}
1755
e8f081aa
YP		 1756static void mlx4_master_do_cmd(struct mlx4_dev *dev, int slave, u8 cmd,
1757 u16 param, u8 toggle)
1758{
1759 struct mlx4_priv *priv = mlx4_priv(dev);
1760 struct mlx4_slave_state *slave_state = priv->mfunc.master.slave_state;
1761 u32 reply;
e8f081aa 1762 u8 is_going_down = 0;
803143fb 1763 int i;
311f813a 1764 unsigned long flags;
e8f081aa
YP		 1765
1766 slave_state[slave].comm_toggle ^= 1;
1767 reply = (u32) slave_state[slave].comm_toggle << 31;
1768 if (toggle != slave_state[slave].comm_toggle) {
1a91de28
JP		 1769 mlx4_warn(dev, "Incorrect toggle %d from slave %d. *** MASTER STATE COMPROMISED ***\n",
1770 toggle, slave);
e8f081aa
YP		 1771 goto reset_slave;
1772 }
1773 if (cmd == MLX4_COMM_CMD_RESET) {
1774 mlx4_warn(dev, "Received reset from slave:%d\n", slave);
1775 slave_state[slave].active = false;
2c957ff2 1776 slave_state[slave].old_vlan_api = false;
3f7fb021 1777 mlx4_master_deactivate_admin_state(priv, slave);
803143fb
MA		 1778 for (i = 0; i < MLX4_EVENT_TYPES_NUM; ++i) {
1779 slave_state[slave].event_eq[i].eqn = -1;
1780 slave_state[slave].event_eq[i].token = 0;
1781 }
e8f081aa
YP		 1782 /*check if we are in the middle of FLR process,
1783 if so return "retry" status to the slave*/
162344ed 1784 if (MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd)
e8f081aa 1785 goto inform_slave_state;
e8f081aa 1786
fc06573d
JM		 1787 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_SHUTDOWN, slave);
1788
e8f081aa
YP		 1789 /* write the version in the event field */
1790 reply |= mlx4_comm_get_version();
1791
1792 goto reset_slave;
1793 }
1794 /*command from slave in the middle of FLR*/
1795 if (cmd != MLX4_COMM_CMD_RESET &&
1796 MLX4_COMM_CMD_FLR == slave_state[slave].last_cmd) {
1a91de28
JP		 1797 mlx4_warn(dev, "slave:%d is Trying to run cmd(0x%x) in the middle of FLR\n",
1798 slave, cmd);
e8f081aa
YP		 1799 return;
1800 }
1801
1802 switch (cmd) {
1803 case MLX4_COMM_CMD_VHCR0:
1804 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_RESET)
1805 goto reset_slave;
1806 slave_state[slave].vhcr_dma = ((u64) param) << 48;
1807 priv->mfunc.master.slave_state[slave].cookie = 0;
1808 mutex_init(&priv->mfunc.master.gen_eqe_mutex[slave]);
1809 break;
1810 case MLX4_COMM_CMD_VHCR1:
1811 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR0)
1812 goto reset_slave;
1813 slave_state[slave].vhcr_dma |= ((u64) param) << 32;
1814 break;
1815 case MLX4_COMM_CMD_VHCR2:
1816 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR1)
1817 goto reset_slave;
1818 slave_state[slave].vhcr_dma |= ((u64) param) << 16;
1819 break;
1820 case MLX4_COMM_CMD_VHCR_EN:
1821 if (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR2)
1822 goto reset_slave;
1823 slave_state[slave].vhcr_dma |= param;
3f7fb021
RE		 1824 if (mlx4_master_activate_admin_state(priv, slave))
1825 goto reset_slave;
e8f081aa 1826 slave_state[slave].active = true;
fc06573d 1827 mlx4_dispatch_event(dev, MLX4_DEV_EVENT_SLAVE_INIT, slave);
e8f081aa
YP		 1828 break;
1829 case MLX4_COMM_CMD_VHCR_POST:
1830 if ((slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_EN) &&
1831 (slave_state[slave].last_cmd != MLX4_COMM_CMD_VHCR_POST))
1832 goto reset_slave;
f3d4c89e
RD		 1833
1834 mutex_lock(&priv->cmd.slave_cmd_mutex);
e8f081aa 1835 if (mlx4_master_process_vhcr(dev, slave, NULL)) {
1a91de28
JP		 1836 mlx4_err(dev, "Failed processing vhcr for slave:%d, resetting slave\n",
1837 slave);
f3d4c89e 1838 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1839 goto reset_slave;
1840 }
f3d4c89e 1841 mutex_unlock(&priv->cmd.slave_cmd_mutex);
e8f081aa
YP		 1842 break;
1843 default:
1844 mlx4_warn(dev, "Bad comm cmd:%d from slave:%d\n", cmd, slave);
1845 goto reset_slave;
1846 }
311f813a 1847 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1848 if (!slave_state[slave].is_slave_going_down)
1849 slave_state[slave].last_cmd = cmd;
1850 else
1851 is_going_down = 1;
311f813a 1852 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa 1853 if (is_going_down) {
1a91de28 1854 mlx4_warn(dev, "Slave is going down aborting command(%d) executing from slave:%d\n",
e8f081aa
YP		 1855 cmd, slave);
1856 return;
1857 }
1858 __raw_writel((__force u32) cpu_to_be32(reply),
1859 &priv->mfunc.comm[slave].slave_read);
1860 mmiowb();
1861
1862 return;
1863
1864reset_slave:
c82e9aa0
EC		 1865 /* cleanup any slave resources */
1866 mlx4_delete_all_resources_for_slave(dev, slave);
311f813a 1867 spin_lock_irqsave(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1868 if (!slave_state[slave].is_slave_going_down)
1869 slave_state[slave].last_cmd = MLX4_COMM_CMD_RESET;
311f813a 1870 spin_unlock_irqrestore(&priv->mfunc.master.slave_state_lock, flags);
e8f081aa
YP		 1871 /*with slave in the middle of flr, no need to clean resources again.*/
1872inform_slave_state:
1873 memset(&slave_state[slave].event_eq, 0,
1874 sizeof(struct mlx4_slave_event_eq_info));
1875 __raw_writel((__force u32) cpu_to_be32(reply),
1876 &priv->mfunc.comm[slave].slave_read);
1877 wmb();
1878}
1879
1880/* master command processing */
1881void mlx4_master_comm_channel(struct work_struct *work)
1882{
1883 struct mlx4_mfunc_master_ctx *master =
1884 container_of(work,
1885 struct mlx4_mfunc_master_ctx,
1886 comm_work);
1887 struct mlx4_mfunc *mfunc =
1888 container_of(master, struct mlx4_mfunc, master);
1889 struct mlx4_priv *priv =
1890 container_of(mfunc, struct mlx4_priv, mfunc);
1891 struct mlx4_dev *dev = &priv->dev;
1892 __be32 *bit_vec;
1893 u32 comm_cmd;
1894 u32 vec;
1895 int i, j, slave;
1896 int toggle;
1897 int served = 0;
1898 int reported = 0;
1899 u32 slt;
1900
1901 bit_vec = master->comm_arm_bit_vector;
1902 for (i = 0; i < COMM_CHANNEL_BIT_ARRAY_SIZE; i++) {
1903 vec = be32_to_cpu(bit_vec[i]);
1904 for (j = 0; j < 32; j++) {
1905 if (!(vec & (1 << j)))
1906 continue;
1907 ++reported;
1908 slave = (i * 32) + j;
1909 comm_cmd = swab32(readl(
1910 &mfunc->comm[slave].slave_write));
1911 slt = swab32(readl(&mfunc->comm[slave].slave_read))
1912 >> 31;
1913 toggle = comm_cmd >> 31;
1914 if (toggle != slt) {
1915 if (master->slave_state[slave].comm_toggle
1916 != slt) {
c20862c8
AV		 1917 pr_info("slave %d out of sync. read toggle %d, state toggle %d. Resynching.\n",
1918 slave, slt,
1919 master->slave_state[slave].comm_toggle);
e8f081aa
YP		 1920 master->slave_state[slave].comm_toggle =
1921 slt;
1922 }
1923 mlx4_master_do_cmd(dev, slave,
1924 comm_cmd >> 16 & 0xff,
1925 comm_cmd & 0xffff, toggle);
1926 ++served;
1927 }
1928 }
1929 }
1930
1931 if (reported && reported != served)
1a91de28 1932 mlx4_warn(dev, "Got command event with bitmask from %d slaves but %d were served\n",
e8f081aa
YP		 1933 reported, served);
1934
1935 if (mlx4_ARM_COMM_CHANNEL(dev))
1936 mlx4_warn(dev, "Failed to arm comm channel events\n");
1937}
1938
ab9c17a0
JM		 1939static int sync_toggles(struct mlx4_dev *dev)
1940{
1941 struct mlx4_priv *priv = mlx4_priv(dev);
1942 int wr_toggle;
1943 int rd_toggle;
1944 unsigned long end;
1945
1946 wr_toggle = swab32(readl(&priv->mfunc.comm->slave_write)) >> 31;
1947 end = jiffies + msecs_to_jiffies(5000);
1948
1949 while (time_before(jiffies, end)) {
1950 rd_toggle = swab32(readl(&priv->mfunc.comm->slave_read)) >> 31;
1951 if (rd_toggle == wr_toggle) {
1952 priv->cmd.comm_toggle = rd_toggle;
1953 return 0;
1954 }
1955
1956 cond_resched();
1957 }
1958
1959 /*
1960 * we could reach here if for example the previous VM using this
1961 * function misbehaved and left the channel with unsynced state. We
1962 * should fix this here and give this VM a chance to use a properly
1963 * synced channel
1964 */
1965 mlx4_warn(dev, "recovering from previously mis-behaved VM\n");
1966 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_read);
1967 __raw_writel((__force u32) 0, &priv->mfunc.comm->slave_write);
1968 priv->cmd.comm_toggle = 0;
1969
1970 return 0;
1971}
1972
1973int mlx4_multi_func_init(struct mlx4_dev *dev)
1974{
1975 struct mlx4_priv *priv = mlx4_priv(dev);
1976 struct mlx4_slave_state *s_state;
803143fb 1977 int i, j, err, port;
ab9c17a0 1978
ab9c17a0
JM		 1979 if (mlx4_is_master(dev))
1980 priv->mfunc.comm =
1981 ioremap(pci_resource_start(dev->pdev, priv->fw.comm_bar) +
1982 priv->fw.comm_base, MLX4_COMM_PAGESIZE);
1983 else
1984 priv->mfunc.comm =
1985 ioremap(pci_resource_start(dev->pdev, 2) +
1986 MLX4_SLAVE_COMM_BASE, MLX4_COMM_PAGESIZE);
1987 if (!priv->mfunc.comm) {
1a91de28 1988 mlx4_err(dev, "Couldn't map communication vector\n");
ab9c17a0
JM		 1989 goto err_vhcr;
1990 }
1991
1992 if (mlx4_is_master(dev)) {
1993 priv->mfunc.master.slave_state =
1994 kzalloc(dev->num_slaves *
1995 sizeof(struct mlx4_slave_state), GFP_KERNEL);
1996 if (!priv->mfunc.master.slave_state)
1997 goto err_comm;
1998
0eb62b93
RE		 1999 priv->mfunc.master.vf_admin =
2000 kzalloc(dev->num_slaves *
2001 sizeof(struct mlx4_vf_admin_state), GFP_KERNEL);
2002 if (!priv->mfunc.master.vf_admin)
2003 goto err_comm_admin;
2004
2005 priv->mfunc.master.vf_oper =
2006 kzalloc(dev->num_slaves *
2007 sizeof(struct mlx4_vf_oper_state), GFP_KERNEL);
2008 if (!priv->mfunc.master.vf_oper)
2009 goto err_comm_oper;
2010
ab9c17a0
JM		 2011 for (i = 0; i < dev->num_slaves; ++i) {
2012 s_state = &priv->mfunc.master.slave_state[i];
2013 s_state->last_cmd = MLX4_COMM_CMD_RESET;
803143fb
MA		 2014 for (j = 0; j < MLX4_EVENT_TYPES_NUM; ++j)
2015 s_state->event_eq[j].eqn = -1;
ab9c17a0
JM		 2016 __raw_writel((__force u32) 0,
2017 &priv->mfunc.comm[i].slave_write);
2018 __raw_writel((__force u32) 0,
2019 &priv->mfunc.comm[i].slave_read);
2020 mmiowb();
2021 for (port = 1; port <= MLX4_MAX_PORTS; port++) {
2022 s_state->vlan_filter[port] =
2023 kzalloc(sizeof(struct mlx4_vlan_fltr),
2024 GFP_KERNEL);
2025 if (!s_state->vlan_filter[port]) {
2026 if (--port)
2027 kfree(s_state->vlan_filter[port]);
2028 goto err_slaves;
2029 }
2030 INIT_LIST_HEAD(&s_state->mcast_filters[port]);
0eb62b93 2031 priv->mfunc.master.vf_admin[i].vport[port].default_vlan = MLX4_VGT;
3f7fb021 2032 priv->mfunc.master.vf_oper[i].vport[port].state.default_vlan = MLX4_VGT;
0eb62b93
RE		 2033 priv->mfunc.master.vf_oper[i].vport[port].vlan_idx = NO_INDX;
2034 priv->mfunc.master.vf_oper[i].vport[port].mac_idx = NO_INDX;
ab9c17a0
JM		 2035 }
2036 spin_lock_init(&s_state->lock);
2037 }
2038
08ff3235 2039 memset(&priv->mfunc.master.cmd_eqe, 0, dev->caps.eqe_size);
ab9c17a0
JM		 2040 priv->mfunc.master.cmd_eqe.type = MLX4_EVENT_TYPE_CMD;
2041 INIT_WORK(&priv->mfunc.master.comm_work,
2042 mlx4_master_comm_channel);
2043 INIT_WORK(&priv->mfunc.master.slave_event_work,
2044 mlx4_gen_slave_eqe);
2045 INIT_WORK(&priv->mfunc.master.slave_flr_event_work,
2046 mlx4_master_handle_slave_flr);
2047 spin_lock_init(&priv->mfunc.master.slave_state_lock);
992e8e6e 2048 spin_lock_init(&priv->mfunc.master.slave_eq.event_lock);
ab9c17a0
JM		 2049 priv->mfunc.master.comm_wq =
2050 create_singlethread_workqueue("mlx4_comm");
2051 if (!priv->mfunc.master.comm_wq)
2052 goto err_slaves;
2053
2054 if (mlx4_init_resource_tracker(dev))
2055 goto err_thread;
2056
ab9c17a0
JM		 2057 err = mlx4_ARM_COMM_CHANNEL(dev);
2058 if (err) {
2059 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
2060 err);
2061 goto err_resource;
2062 }
2063
2064 } else {
2065 err = sync_toggles(dev);
2066 if (err) {
2067 mlx4_err(dev, "Couldn't sync toggles\n");
2068 goto err_comm;
2069 }
ab9c17a0
JM		 2070 }
2071 return 0;
2072
2073err_resource:
b8924951 2074 mlx4_free_resource_tracker(dev, RES_TR_FREE_ALL);
ab9c17a0
JM		 2075err_thread:
2076 flush_workqueue(priv->mfunc.master.comm_wq);
2077 destroy_workqueue(priv->mfunc.master.comm_wq);
2078err_slaves:
2079 while (--i) {
2080 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2081 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2082 }
0eb62b93
RE		 2083 kfree(priv->mfunc.master.vf_oper);
2084err_comm_oper:
2085 kfree(priv->mfunc.master.vf_admin);
2086err_comm_admin:
ab9c17a0
JM		 2087 kfree(priv->mfunc.master.slave_state);
2088err_comm:
2089 iounmap(priv->mfunc.comm);
2090err_vhcr:
2091 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2092 priv->mfunc.vhcr,
2093 priv->mfunc.vhcr_dma);
2094 priv->mfunc.vhcr = NULL;
2095 return -ENOMEM;
2096}
2097
225c7b1f
RD		 2098int mlx4_cmd_init(struct mlx4_dev *dev)
2099{
2100 struct mlx4_priv *priv = mlx4_priv(dev);
2101
2102 mutex_init(&priv->cmd.hcr_mutex);
f3d4c89e 2103 mutex_init(&priv->cmd.slave_cmd_mutex);
225c7b1f
RD		 2104 sema_init(&priv->cmd.poll_sem, 1);
2105 priv->cmd.use_events = 0;
2106 priv->cmd.toggle = 1;
2107
e8f081aa
YP		 2108 priv->cmd.hcr = NULL;
2109 priv->mfunc.vhcr = NULL;
2110
2111 if (!mlx4_is_slave(dev)) {
2112 priv->cmd.hcr = ioremap(pci_resource_start(dev->pdev, 0) +
2113 MLX4_HCR_BASE, MLX4_HCR_SIZE);
2114 if (!priv->cmd.hcr) {
1a91de28 2115 mlx4_err(dev, "Couldn't map command register\n");
e8f081aa
YP		 2116 return -ENOMEM;
2117 }
225c7b1f
RD		 2118 }
2119
f3d4c89e
RD		 2120 if (mlx4_is_mfunc(dev)) {
2121 priv->mfunc.vhcr = dma_alloc_coherent(&(dev->pdev->dev), PAGE_SIZE,
2122 &priv->mfunc.vhcr_dma,
2123 GFP_KERNEL);
d0320f75 2124 if (!priv->mfunc.vhcr)
f3d4c89e 2125 goto err_hcr;
f3d4c89e
RD		 2126 }
2127
225c7b1f
RD		 2128 priv->cmd.pool = pci_pool_create("mlx4_cmd", dev->pdev,
2129 MLX4_MAILBOX_SIZE,
2130 MLX4_MAILBOX_SIZE, 0);
e8f081aa 2131 if (!priv->cmd.pool)
f3d4c89e 2132 goto err_vhcr;
225c7b1f
RD		 2133
2134 return 0;
e8f081aa 2135
f3d4c89e
RD		 2136err_vhcr:
2137 if (mlx4_is_mfunc(dev))
2138 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2139 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2140 priv->mfunc.vhcr = NULL;
2141
e8f081aa
YP		 2142err_hcr:
2143 if (!mlx4_is_slave(dev))
2144 iounmap(priv->cmd.hcr);
2145 return -ENOMEM;
225c7b1f
RD		 2146}
2147
ab9c17a0
JM		 2148void mlx4_multi_func_cleanup(struct mlx4_dev *dev)
2149{
2150 struct mlx4_priv *priv = mlx4_priv(dev);
2151 int i, port;
2152
2153 if (mlx4_is_master(dev)) {
2154 flush_workqueue(priv->mfunc.master.comm_wq);
2155 destroy_workqueue(priv->mfunc.master.comm_wq);
2156 for (i = 0; i < dev->num_slaves; i++) {
2157 for (port = 1; port <= MLX4_MAX_PORTS; port++)
2158 kfree(priv->mfunc.master.slave_state[i].vlan_filter[port]);
2159 }
2160 kfree(priv->mfunc.master.slave_state);
0eb62b93
RE		 2161 kfree(priv->mfunc.master.vf_admin);
2162 kfree(priv->mfunc.master.vf_oper);
ab9c17a0 2163 }
f08ad06c
EE		 2164
2165 iounmap(priv->mfunc.comm);
ab9c17a0
JM		 2166}
2167
225c7b1f
RD		 2168void mlx4_cmd_cleanup(struct mlx4_dev *dev)
2169{
2170 struct mlx4_priv *priv = mlx4_priv(dev);
2171
2172 pci_pool_destroy(priv->cmd.pool);
e8f081aa
YP		 2173
2174 if (!mlx4_is_slave(dev))
2175 iounmap(priv->cmd.hcr);
f3d4c89e
RD		 2176 if (mlx4_is_mfunc(dev))
2177 dma_free_coherent(&(dev->pdev->dev), PAGE_SIZE,
2178 priv->mfunc.vhcr, priv->mfunc.vhcr_dma);
2179 priv->mfunc.vhcr = NULL;
225c7b1f
RD		 2180}
2181
2182/*
2183 * Switch to using events to issue FW commands (can only be called
2184 * after event queue for command events has been initialized).
2185 */
2186int mlx4_cmd_use_events(struct mlx4_dev *dev)
2187{
2188 struct mlx4_priv *priv = mlx4_priv(dev);
2189 int i;
e8f081aa 2190 int err = 0;
225c7b1f
RD		 2191
2192 priv->cmd.context = kmalloc(priv->cmd.max_cmds *
2193 sizeof (struct mlx4_cmd_context),
2194 GFP_KERNEL);
2195 if (!priv->cmd.context)
2196 return -ENOMEM;
2197
2198 for (i = 0; i < priv->cmd.max_cmds; ++i) {
2199 priv->cmd.context[i].token = i;
2200 priv->cmd.context[i].next = i + 1;
2201 }
2202
2203 priv->cmd.context[priv->cmd.max_cmds - 1].next = -1;
2204 priv->cmd.free_head = 0;
2205
2206 sema_init(&priv->cmd.event_sem, priv->cmd.max_cmds);
2207 spin_lock_init(&priv->cmd.context_lock);
2208
2209 for (priv->cmd.token_mask = 1;
2210 priv->cmd.token_mask < priv->cmd.max_cmds;
2211 priv->cmd.token_mask <<= 1)
2212 ; /* nothing */
2213 --priv->cmd.token_mask;
2214
225c7b1f 2215 down(&priv->cmd.poll_sem);
e8f081aa 2216 priv->cmd.use_events = 1;
225c7b1f 2217
e8f081aa 2218 return err;
225c7b1f
RD		 2219}
2220
2221/*
2222 * Switch back to polling (used when shutting down the device)
2223 */
2224void mlx4_cmd_use_polling(struct mlx4_dev *dev)
2225{
2226 struct mlx4_priv *priv = mlx4_priv(dev);
2227 int i;
2228
2229 priv->cmd.use_events = 0;
2230
2231 for (i = 0; i < priv->cmd.max_cmds; ++i)
2232 down(&priv->cmd.event_sem);
2233
2234 kfree(priv->cmd.context);
2235
2236 up(&priv->cmd.poll_sem);
2237}
2238
2239struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev)
2240{
2241 struct mlx4_cmd_mailbox *mailbox;
2242
2243 mailbox = kmalloc(sizeof *mailbox, GFP_KERNEL);
2244 if (!mailbox)
2245 return ERR_PTR(-ENOMEM);
2246
2247 mailbox->buf = pci_pool_alloc(mlx4_priv(dev)->cmd.pool, GFP_KERNEL,
2248 &mailbox->dma);
2249 if (!mailbox->buf) {
2250 kfree(mailbox);
2251 return ERR_PTR(-ENOMEM);
2252 }
2253
571b8b92
JM		 2254 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
2255
225c7b1f
RD		 2256 return mailbox;
2257}
2258EXPORT_SYMBOL_GPL(mlx4_alloc_cmd_mailbox);
2259
e8f081aa
YP		 2260void mlx4_free_cmd_mailbox(struct mlx4_dev *dev,
2261 struct mlx4_cmd_mailbox *mailbox)
225c7b1f
RD		 2262{
2263 if (!mailbox)
2264 return;
2265
2266 pci_pool_free(mlx4_priv(dev)->cmd.pool, mailbox->buf, mailbox->dma);
2267 kfree(mailbox);
2268}
2269EXPORT_SYMBOL_GPL(mlx4_free_cmd_mailbox);
e8f081aa
YP		 2270
2271u32 mlx4_comm_get_version(void)
2272{
2273 return ((u32) CMD_CHAN_IF_REV << 8) | (u32) CMD_CHAN_VER;
2274}
8f7ba3ca
RE		 2275
2276static int mlx4_get_slave_indx(struct mlx4_dev *dev, int vf)
2277{
2278 if ((vf < 0) || (vf >= dev->num_vfs)) {
2279 mlx4_err(dev, "Bad vf number:%d (number of activated vf: %d)\n", vf, dev->num_vfs);
2280 return -EINVAL;
2281 }
2282
2283 return vf+1;
2284}
2285
f74462ac
MB		 2286int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave)
2287{
2288 if (slave < 1 || slave > dev->num_vfs) {
2289 mlx4_err(dev,
2290 "Bad slave number:%d (number of activated slaves: %lu)\n",
2291 slave, dev->num_slaves);
2292 return -EINVAL;
2293 }
2294 return slave - 1;
2295}
2296
2297struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave)
2298{
2299 struct mlx4_active_ports actv_ports;
2300 int vf;
2301
2302 bitmap_zero(actv_ports.ports, MLX4_MAX_PORTS);
2303
2304 if (slave == 0) {
2305 bitmap_fill(actv_ports.ports, dev->caps.num_ports);
2306 return actv_ports;
2307 }
2308
2309 vf = mlx4_get_vf_indx(dev, slave);
2310 if (vf < 0)
2311 return actv_ports;
2312
2313 bitmap_set(actv_ports.ports, dev->dev_vfs[vf].min_port - 1,
2314 min((int)dev->dev_vfs[mlx4_get_vf_indx(dev, slave)].n_ports,
2315 dev->caps.num_ports));
2316
2317 return actv_ports;
2318}
2319EXPORT_SYMBOL_GPL(mlx4_get_active_ports);
2320
2321int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port)
2322{
2323 unsigned n;
2324 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2325 unsigned m = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
2326
2327 if (port <= 0 || port > m)
2328 return -EINVAL;
2329
2330 n = find_first_bit(actv_ports.ports, dev->caps.num_ports);
2331 if (port <= n)
2332 port = n + 1;
2333
2334 return port;
2335}
2336EXPORT_SYMBOL_GPL(mlx4_slave_convert_port);
2337
2338int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port)
2339{
2340 struct mlx4_active_ports actv_ports = mlx4_get_active_ports(dev, slave);
2341 if (test_bit(port - 1, actv_ports.ports))
2342 return port -
2343 find_first_bit(actv_ports.ports, dev->caps.num_ports);
2344
2345 return -1;
2346}
2347EXPORT_SYMBOL_GPL(mlx4_phys_to_slave_port);
2348
2349struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev,
2350 int port)
2351{
2352 unsigned i;
2353 struct mlx4_slaves_pport slaves_pport;
2354
2355 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2356
2357 if (port <= 0 || port > dev->caps.num_ports)
2358 return slaves_pport;
2359
2360 for (i = 0; i < dev->num_vfs + 1; i++) {
2361 struct mlx4_active_ports actv_ports =
2362 mlx4_get_active_ports(dev, i);
2363 if (test_bit(port - 1, actv_ports.ports))
2364 set_bit(i, slaves_pport.slaves);
2365 }
2366
2367 return slaves_pport;
2368}
2369EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport);
2370
2371struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv(
2372 struct mlx4_dev *dev,
2373 const struct mlx4_active_ports *crit_ports)
2374{
2375 unsigned i;
2376 struct mlx4_slaves_pport slaves_pport;
2377
2378 bitmap_zero(slaves_pport.slaves, MLX4_MFUNC_MAX);
2379
2380 for (i = 0; i < dev->num_vfs + 1; i++) {
2381 struct mlx4_active_ports actv_ports =
2382 mlx4_get_active_ports(dev, i);
2383 if (bitmap_equal(crit_ports->ports, actv_ports.ports,
2384 dev->caps.num_ports))
2385 set_bit(i, slaves_pport.slaves);
2386 }
2387
2388 return slaves_pport;
2389}
2390EXPORT_SYMBOL_GPL(mlx4_phys_to_slaves_pport_actv);
2391
8f7ba3ca
RE		 2392int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac)
2393{
2394 struct mlx4_priv *priv = mlx4_priv(dev);
2395 struct mlx4_vport_state *s_info;
2396 int slave;
2397
2398 if (!mlx4_is_master(dev))
2399 return -EPROTONOSUPPORT;
2400
2401 slave = mlx4_get_slave_indx(dev, vf);
2402 if (slave < 0)
2403 return -EINVAL;
2404
2405 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2406 s_info->mac = mac;
2407 mlx4_info(dev, "default mac on vf %d port %d to %llX will take afect only after vf restart\n",
2408 vf, port, s_info->mac);
2409 return 0;
2410}
2411EXPORT_SYMBOL_GPL(mlx4_set_vf_mac);
3f7fb021 2412
b01978ca 2413
3f7fb021
RE		 2414int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos)
2415{
2416 struct mlx4_priv *priv = mlx4_priv(dev);
b01978ca 2417 struct mlx4_vport_state *vf_admin;
3f7fb021
RE		 2418 int slave;
2419
2420 if ((!mlx4_is_master(dev)) ||
2421 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VLAN_CONTROL))
2422 return -EPROTONOSUPPORT;
2423
2424 if ((vlan > 4095) || (qos > 7))
2425 return -EINVAL;
2426
2427 slave = mlx4_get_slave_indx(dev, vf);
2428 if (slave < 0)
2429 return -EINVAL;
2430
b01978ca 2431 vf_admin = &priv->mfunc.master.vf_admin[slave].vport[port];
b01978ca 2432
3f7fb021 2433 if ((0 == vlan) && (0 == qos))
b01978ca 2434 vf_admin->default_vlan = MLX4_VGT;
3f7fb021 2435 else
b01978ca
JM		 2436 vf_admin->default_vlan = vlan;
2437 vf_admin->default_qos = qos;
2438
0a6eac24
RE		 2439 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2440 mlx4_info(dev,
2441 "updating vf %d port %d config will take effect on next VF restart\n",
b01978ca 2442 vf, port);
3f7fb021
RE		 2443 return 0;
2444}
2445EXPORT_SYMBOL_GPL(mlx4_set_vf_vlan);
e6b6a231 2446
5ea8bbfc
JM		 2447 /* mlx4_get_slave_default_vlan -
2448 * return true if VST ( default vlan)
2449 * if VST, will return vlan & qos (if not NULL)
2450 */
2451bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave,
2452 u16 *vlan, u8 *qos)
2453{
2454 struct mlx4_vport_oper_state *vp_oper;
2455 struct mlx4_priv *priv;
2456
2457 priv = mlx4_priv(dev);
2458 vp_oper = &priv->mfunc.master.vf_oper[slave].vport[port];
2459
2460 if (MLX4_VGT != vp_oper->state.default_vlan) {
2461 if (vlan)
2462 *vlan = vp_oper->state.default_vlan;
2463 if (qos)
2464 *qos = vp_oper->state.default_qos;
2465 return true;
2466 }
2467 return false;
2468}
2469EXPORT_SYMBOL_GPL(mlx4_get_slave_default_vlan);
2470
e6b6a231
RE		 2471int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting)
2472{
2473 struct mlx4_priv *priv = mlx4_priv(dev);
2474 struct mlx4_vport_state *s_info;
2475 int slave;
2476
2477 if ((!mlx4_is_master(dev)) ||
2478 !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FSM))
2479 return -EPROTONOSUPPORT;
2480
2481 slave = mlx4_get_slave_indx(dev, vf);
2482 if (slave < 0)
2483 return -EINVAL;
2484
2485 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2486 s_info->spoofchk = setting;
2487
2488 return 0;
2489}
2490EXPORT_SYMBOL_GPL(mlx4_set_vf_spoofchk);
2cccb9e4
RE		 2491
2492int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf)
2493{
2494 struct mlx4_priv *priv = mlx4_priv(dev);
2495 struct mlx4_vport_state *s_info;
2496 int slave;
2497
2498 if (!mlx4_is_master(dev))
2499 return -EPROTONOSUPPORT;
2500
2501 slave = mlx4_get_slave_indx(dev, vf);
2502 if (slave < 0)
2503 return -EINVAL;
2504
2505 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
2506 ivf->vf = vf;
2507
2508 /* need to convert it to a func */
2509 ivf->mac[0] = ((s_info->mac >> (5*8)) & 0xff);
2510 ivf->mac[1] = ((s_info->mac >> (4*8)) & 0xff);
2511 ivf->mac[2] = ((s_info->mac >> (3*8)) & 0xff);
2512 ivf->mac[3] = ((s_info->mac >> (2*8)) & 0xff);
2513 ivf->mac[4] = ((s_info->mac >> (1*8)) & 0xff);
2514 ivf->mac[5] = ((s_info->mac) & 0xff);
2515
ed616689
SC		 2516 ivf->vlan = s_info->default_vlan;
2517 ivf->qos = s_info->default_qos;
2518 ivf->max_tx_rate = s_info->tx_rate;
2519 ivf->min_tx_rate = 0;
2520 ivf->spoofchk = s_info->spoofchk;
2521 ivf->linkstate = s_info->link_state;
2cccb9e4
RE		 2522
2523 return 0;
2524}
2525EXPORT_SYMBOL_GPL(mlx4_get_vf_config);
948e306d
RE		 2526
2527int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state)
2528{
2529 struct mlx4_priv *priv = mlx4_priv(dev);
2530 struct mlx4_vport_state *s_info;
948e306d
RE		 2531 int slave;
2532 u8 link_stat_event;
2533
2534 slave = mlx4_get_slave_indx(dev, vf);
2535 if (slave < 0)
2536 return -EINVAL;
2537
2538 switch (link_state) {
2539 case IFLA_VF_LINK_STATE_AUTO:
2540 /* get current link state */
2541 if (!priv->sense.do_sense_port[port])
2542 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2543 else
2544 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2545 break;
2546
2547 case IFLA_VF_LINK_STATE_ENABLE:
2548 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_ACTIVE;
2549 break;
2550
2551 case IFLA_VF_LINK_STATE_DISABLE:
2552 link_stat_event = MLX4_PORT_CHANGE_SUBTYPE_DOWN;
2553 break;
2554
2555 default:
2556 mlx4_warn(dev, "unknown value for link_state %02x on slave %d port %d\n",
2557 link_state, slave, port);
2558 return -EINVAL;
2559 };
948e306d 2560 s_info = &priv->mfunc.master.vf_admin[slave].vport[port];
948e306d 2561 s_info->link_state = link_state;
948e306d
RE		 2562
2563 /* send event */
2564 mlx4_gen_port_state_change_eqe(dev, slave, port, link_stat_event);
0a6eac24
RE		 2565
2566 if (mlx4_master_immediate_activate_vlan_qos(priv, slave, port))
2567 mlx4_dbg(dev,
2568 "updating vf %d port %d no link state HW enforcment\n",
2569 vf, port);
948e306d
RE		 2570 return 0;
2571}
2572EXPORT_SYMBOL_GPL(mlx4_set_vf_link_state);
97982f5a
JM		 2573
2574int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port)
2575{
99ec41d0
JM		 2576 struct mlx4_priv *priv = mlx4_priv(dev);
2577
2578 if (slave < 1 || slave >= dev->num_slaves ||
2579 port < 1 || port > MLX4_MAX_PORTS)
2580 return 0;
2581
2582 return priv->mfunc.master.vf_oper[slave].smi_enabled[port] ==
2583 MLX4_VF_SMI_ENABLED;
97982f5a
JM		 2584}
2585EXPORT_SYMBOL_GPL(mlx4_vf_smi_enabled);
65fed8a8
JM		 2586
2587int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port)
2588{
2589 struct mlx4_priv *priv = mlx4_priv(dev);
2590
2591 if (slave == mlx4_master_func_num(dev))
2592 return 1;
2593
2594 if (slave < 1 || slave >= dev->num_slaves ||
2595 port < 1 || port > MLX4_MAX_PORTS)
2596 return 0;
2597
2598 return priv->mfunc.master.vf_admin[slave].enable_smi[port] ==
2599 MLX4_VF_SMI_ENABLED;
2600}
2601EXPORT_SYMBOL_GPL(mlx4_vf_get_enable_smi_admin);
2602
2603int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port,
2604 int enabled)
2605{
2606 struct mlx4_priv *priv = mlx4_priv(dev);
2607
2608 if (slave == mlx4_master_func_num(dev))
2609 return 0;
2610
2611 if (slave < 1 || slave >= dev->num_slaves ||
2612 port < 1 || port > MLX4_MAX_PORTS ||
2613 enabled < 0 || enabled > 1)
2614 return -EINVAL;
2615
2616 priv->mfunc.master.vf_admin[slave].enable_smi[port] = enabled;
2617 return 0;
2618}
2619EXPORT_SYMBOL_GPL(mlx4_vf_set_enable_smi_admin);
Linux kernel - Deliverables
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