Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/tcp.h> | |
36 | #include <linux/if_vlan.h> | |
37 | #include <linux/delay.h> | |
5a0e3ad6 | 38 | #include <linux/slab.h> |
1eb8c695 AV |
39 | #include <linux/hash.h> |
40 | #include <net/ip.h> | |
c27a02cd YP |
41 | |
42 | #include <linux/mlx4/driver.h> | |
43 | #include <linux/mlx4/device.h> | |
44 | #include <linux/mlx4/cmd.h> | |
45 | #include <linux/mlx4/cq.h> | |
46 | ||
47 | #include "mlx4_en.h" | |
48 | #include "en_port.h" | |
49 | ||
d317966b | 50 | int mlx4_en_setup_tc(struct net_device *dev, u8 up) |
897d7846 | 51 | { |
bc6a4744 AV |
52 | struct mlx4_en_priv *priv = netdev_priv(dev); |
53 | int i; | |
d317966b | 54 | unsigned int offset = 0; |
bc6a4744 AV |
55 | |
56 | if (up && up != MLX4_EN_NUM_UP) | |
897d7846 AV |
57 | return -EINVAL; |
58 | ||
bc6a4744 AV |
59 | netdev_set_num_tc(dev, up); |
60 | ||
61 | /* Partition Tx queues evenly amongst UP's */ | |
bc6a4744 | 62 | for (i = 0; i < up; i++) { |
d317966b AV |
63 | netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset); |
64 | offset += priv->num_tx_rings_p_up; | |
bc6a4744 AV |
65 | } |
66 | ||
897d7846 AV |
67 | return 0; |
68 | } | |
69 | ||
1eb8c695 AV |
70 | #ifdef CONFIG_RFS_ACCEL |
71 | ||
72 | struct mlx4_en_filter { | |
73 | struct list_head next; | |
74 | struct work_struct work; | |
75 | ||
76 | __be32 src_ip; | |
77 | __be32 dst_ip; | |
78 | __be16 src_port; | |
79 | __be16 dst_port; | |
80 | ||
81 | int rxq_index; | |
82 | struct mlx4_en_priv *priv; | |
83 | u32 flow_id; /* RFS infrastructure id */ | |
84 | int id; /* mlx4_en driver id */ | |
85 | u64 reg_id; /* Flow steering API id */ | |
86 | u8 activated; /* Used to prevent expiry before filter | |
87 | * is attached | |
88 | */ | |
89 | struct hlist_node filter_chain; | |
90 | }; | |
91 | ||
92 | static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv); | |
93 | ||
94 | static void mlx4_en_filter_work(struct work_struct *work) | |
95 | { | |
96 | struct mlx4_en_filter *filter = container_of(work, | |
97 | struct mlx4_en_filter, | |
98 | work); | |
99 | struct mlx4_en_priv *priv = filter->priv; | |
100 | struct mlx4_spec_list spec_tcp = { | |
101 | .id = MLX4_NET_TRANS_RULE_ID_TCP, | |
102 | { | |
103 | .tcp_udp = { | |
104 | .dst_port = filter->dst_port, | |
105 | .dst_port_msk = (__force __be16)-1, | |
106 | .src_port = filter->src_port, | |
107 | .src_port_msk = (__force __be16)-1, | |
108 | }, | |
109 | }, | |
110 | }; | |
111 | struct mlx4_spec_list spec_ip = { | |
112 | .id = MLX4_NET_TRANS_RULE_ID_IPV4, | |
113 | { | |
114 | .ipv4 = { | |
115 | .dst_ip = filter->dst_ip, | |
116 | .dst_ip_msk = (__force __be32)-1, | |
117 | .src_ip = filter->src_ip, | |
118 | .src_ip_msk = (__force __be32)-1, | |
119 | }, | |
120 | }, | |
121 | }; | |
122 | struct mlx4_spec_list spec_eth = { | |
123 | .id = MLX4_NET_TRANS_RULE_ID_ETH, | |
124 | }; | |
125 | struct mlx4_net_trans_rule rule = { | |
126 | .list = LIST_HEAD_INIT(rule.list), | |
127 | .queue_mode = MLX4_NET_TRANS_Q_LIFO, | |
128 | .exclusive = 1, | |
129 | .allow_loopback = 1, | |
130 | .promisc_mode = MLX4_FS_PROMISC_NONE, | |
131 | .port = priv->port, | |
132 | .priority = MLX4_DOMAIN_RFS, | |
133 | }; | |
134 | int rc; | |
1eb8c695 AV |
135 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); |
136 | ||
137 | list_add_tail(&spec_eth.list, &rule.list); | |
138 | list_add_tail(&spec_ip.list, &rule.list); | |
139 | list_add_tail(&spec_tcp.list, &rule.list); | |
140 | ||
1eb8c695 | 141 | rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn; |
6bbb6d99 | 142 | memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN); |
1eb8c695 AV |
143 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); |
144 | ||
145 | filter->activated = 0; | |
146 | ||
147 | if (filter->reg_id) { | |
148 | rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id); | |
149 | if (rc && rc != -ENOENT) | |
150 | en_err(priv, "Error detaching flow. rc = %d\n", rc); | |
151 | } | |
152 | ||
153 | rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id); | |
154 | if (rc) | |
155 | en_err(priv, "Error attaching flow. err = %d\n", rc); | |
156 | ||
157 | mlx4_en_filter_rfs_expire(priv); | |
158 | ||
159 | filter->activated = 1; | |
160 | } | |
161 | ||
162 | static inline struct hlist_head * | |
163 | filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, | |
164 | __be16 src_port, __be16 dst_port) | |
165 | { | |
166 | unsigned long l; | |
167 | int bucket_idx; | |
168 | ||
169 | l = (__force unsigned long)src_port | | |
170 | ((__force unsigned long)dst_port << 2); | |
171 | l ^= (__force unsigned long)(src_ip ^ dst_ip); | |
172 | ||
173 | bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT); | |
174 | ||
175 | return &priv->filter_hash[bucket_idx]; | |
176 | } | |
177 | ||
178 | static struct mlx4_en_filter * | |
179 | mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip, | |
180 | __be32 dst_ip, __be16 src_port, __be16 dst_port, | |
181 | u32 flow_id) | |
182 | { | |
183 | struct mlx4_en_filter *filter = NULL; | |
184 | ||
185 | filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC); | |
186 | if (!filter) | |
187 | return NULL; | |
188 | ||
189 | filter->priv = priv; | |
190 | filter->rxq_index = rxq_index; | |
191 | INIT_WORK(&filter->work, mlx4_en_filter_work); | |
192 | ||
193 | filter->src_ip = src_ip; | |
194 | filter->dst_ip = dst_ip; | |
195 | filter->src_port = src_port; | |
196 | filter->dst_port = dst_port; | |
197 | ||
198 | filter->flow_id = flow_id; | |
199 | ||
ee64c0ee | 200 | filter->id = priv->last_filter_id++ % RPS_NO_FILTER; |
1eb8c695 AV |
201 | |
202 | list_add_tail(&filter->next, &priv->filters); | |
203 | hlist_add_head(&filter->filter_chain, | |
204 | filter_hash_bucket(priv, src_ip, dst_ip, src_port, | |
205 | dst_port)); | |
206 | ||
207 | return filter; | |
208 | } | |
209 | ||
210 | static void mlx4_en_filter_free(struct mlx4_en_filter *filter) | |
211 | { | |
212 | struct mlx4_en_priv *priv = filter->priv; | |
213 | int rc; | |
214 | ||
215 | list_del(&filter->next); | |
216 | ||
217 | rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id); | |
218 | if (rc && rc != -ENOENT) | |
219 | en_err(priv, "Error detaching flow. rc = %d\n", rc); | |
220 | ||
221 | kfree(filter); | |
222 | } | |
223 | ||
224 | static inline struct mlx4_en_filter * | |
225 | mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip, | |
226 | __be16 src_port, __be16 dst_port) | |
227 | { | |
1eb8c695 AV |
228 | struct mlx4_en_filter *filter; |
229 | struct mlx4_en_filter *ret = NULL; | |
230 | ||
b67bfe0d | 231 | hlist_for_each_entry(filter, |
1eb8c695 AV |
232 | filter_hash_bucket(priv, src_ip, dst_ip, |
233 | src_port, dst_port), | |
234 | filter_chain) { | |
235 | if (filter->src_ip == src_ip && | |
236 | filter->dst_ip == dst_ip && | |
237 | filter->src_port == src_port && | |
238 | filter->dst_port == dst_port) { | |
239 | ret = filter; | |
240 | break; | |
241 | } | |
242 | } | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int | |
248 | mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb, | |
249 | u16 rxq_index, u32 flow_id) | |
250 | { | |
251 | struct mlx4_en_priv *priv = netdev_priv(net_dev); | |
252 | struct mlx4_en_filter *filter; | |
253 | const struct iphdr *ip; | |
254 | const __be16 *ports; | |
255 | __be32 src_ip; | |
256 | __be32 dst_ip; | |
257 | __be16 src_port; | |
258 | __be16 dst_port; | |
259 | int nhoff = skb_network_offset(skb); | |
260 | int ret = 0; | |
261 | ||
262 | if (skb->protocol != htons(ETH_P_IP)) | |
263 | return -EPROTONOSUPPORT; | |
264 | ||
265 | ip = (const struct iphdr *)(skb->data + nhoff); | |
266 | if (ip_is_fragment(ip)) | |
267 | return -EPROTONOSUPPORT; | |
268 | ||
269 | ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl); | |
270 | ||
271 | src_ip = ip->saddr; | |
272 | dst_ip = ip->daddr; | |
273 | src_port = ports[0]; | |
274 | dst_port = ports[1]; | |
275 | ||
276 | if (ip->protocol != IPPROTO_TCP) | |
277 | return -EPROTONOSUPPORT; | |
278 | ||
279 | spin_lock_bh(&priv->filters_lock); | |
280 | filter = mlx4_en_filter_find(priv, src_ip, dst_ip, src_port, dst_port); | |
281 | if (filter) { | |
282 | if (filter->rxq_index == rxq_index) | |
283 | goto out; | |
284 | ||
285 | filter->rxq_index = rxq_index; | |
286 | } else { | |
287 | filter = mlx4_en_filter_alloc(priv, rxq_index, | |
288 | src_ip, dst_ip, | |
289 | src_port, dst_port, flow_id); | |
290 | if (!filter) { | |
291 | ret = -ENOMEM; | |
292 | goto err; | |
293 | } | |
294 | } | |
295 | ||
296 | queue_work(priv->mdev->workqueue, &filter->work); | |
297 | ||
298 | out: | |
299 | ret = filter->id; | |
300 | err: | |
301 | spin_unlock_bh(&priv->filters_lock); | |
302 | ||
303 | return ret; | |
304 | } | |
305 | ||
306 | void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv, | |
307 | struct mlx4_en_rx_ring *rx_ring) | |
308 | { | |
309 | struct mlx4_en_filter *filter, *tmp; | |
310 | LIST_HEAD(del_list); | |
311 | ||
312 | spin_lock_bh(&priv->filters_lock); | |
313 | list_for_each_entry_safe(filter, tmp, &priv->filters, next) { | |
314 | list_move(&filter->next, &del_list); | |
315 | hlist_del(&filter->filter_chain); | |
316 | } | |
317 | spin_unlock_bh(&priv->filters_lock); | |
318 | ||
319 | list_for_each_entry_safe(filter, tmp, &del_list, next) { | |
320 | cancel_work_sync(&filter->work); | |
321 | mlx4_en_filter_free(filter); | |
322 | } | |
323 | } | |
324 | ||
325 | static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv) | |
326 | { | |
327 | struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL; | |
328 | LIST_HEAD(del_list); | |
329 | int i = 0; | |
330 | ||
331 | spin_lock_bh(&priv->filters_lock); | |
332 | list_for_each_entry_safe(filter, tmp, &priv->filters, next) { | |
333 | if (i > MLX4_EN_FILTER_EXPIRY_QUOTA) | |
334 | break; | |
335 | ||
336 | if (filter->activated && | |
337 | !work_pending(&filter->work) && | |
338 | rps_may_expire_flow(priv->dev, | |
339 | filter->rxq_index, filter->flow_id, | |
340 | filter->id)) { | |
341 | list_move(&filter->next, &del_list); | |
342 | hlist_del(&filter->filter_chain); | |
343 | } else | |
344 | last_filter = filter; | |
345 | ||
346 | i++; | |
347 | } | |
348 | ||
349 | if (last_filter && (&last_filter->next != priv->filters.next)) | |
350 | list_move(&priv->filters, &last_filter->next); | |
351 | ||
352 | spin_unlock_bh(&priv->filters_lock); | |
353 | ||
354 | list_for_each_entry_safe(filter, tmp, &del_list, next) | |
355 | mlx4_en_filter_free(filter); | |
356 | } | |
357 | #endif | |
358 | ||
80d5c368 PM |
359 | static int mlx4_en_vlan_rx_add_vid(struct net_device *dev, |
360 | __be16 proto, u16 vid) | |
c27a02cd YP |
361 | { |
362 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
363 | struct mlx4_en_dev *mdev = priv->mdev; | |
364 | int err; | |
4c3eb3ca | 365 | int idx; |
c27a02cd | 366 | |
f1b553fb | 367 | en_dbg(HW, priv, "adding VLAN:%d\n", vid); |
c27a02cd | 368 | |
f1b553fb | 369 | set_bit(vid, priv->active_vlans); |
c27a02cd YP |
370 | |
371 | /* Add VID to port VLAN filter */ | |
372 | mutex_lock(&mdev->state_lock); | |
373 | if (mdev->device_up && priv->port_up) { | |
f1b553fb | 374 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
c27a02cd | 375 | if (err) |
453a6082 | 376 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd | 377 | } |
4c3eb3ca EC |
378 | if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx)) |
379 | en_err(priv, "failed adding vlan %d\n", vid); | |
c27a02cd | 380 | mutex_unlock(&mdev->state_lock); |
4c3eb3ca | 381 | |
8e586137 | 382 | return 0; |
c27a02cd YP |
383 | } |
384 | ||
80d5c368 PM |
385 | static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev, |
386 | __be16 proto, u16 vid) | |
c27a02cd YP |
387 | { |
388 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
389 | struct mlx4_en_dev *mdev = priv->mdev; | |
390 | int err; | |
4c3eb3ca | 391 | int idx; |
c27a02cd | 392 | |
f1b553fb | 393 | en_dbg(HW, priv, "Killing VID:%d\n", vid); |
c27a02cd | 394 | |
f1b553fb | 395 | clear_bit(vid, priv->active_vlans); |
c27a02cd YP |
396 | |
397 | /* Remove VID from port VLAN filter */ | |
398 | mutex_lock(&mdev->state_lock); | |
4c3eb3ca EC |
399 | if (!mlx4_find_cached_vlan(mdev->dev, priv->port, vid, &idx)) |
400 | mlx4_unregister_vlan(mdev->dev, priv->port, idx); | |
401 | else | |
402 | en_err(priv, "could not find vid %d in cache\n", vid); | |
403 | ||
c27a02cd | 404 | if (mdev->device_up && priv->port_up) { |
f1b553fb | 405 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
c27a02cd | 406 | if (err) |
453a6082 | 407 | en_err(priv, "Failed configuring VLAN filter\n"); |
c27a02cd YP |
408 | } |
409 | mutex_unlock(&mdev->state_lock); | |
8e586137 JP |
410 | |
411 | return 0; | |
c27a02cd YP |
412 | } |
413 | ||
6bbb6d99 YB |
414 | static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac) |
415 | { | |
bab6a9ea YB |
416 | int i; |
417 | for (i = ETH_ALEN - 1; i >= 0; --i) { | |
6bbb6d99 YB |
418 | dst_mac[i] = src_mac & 0xff; |
419 | src_mac >>= 8; | |
420 | } | |
421 | memset(&dst_mac[ETH_ALEN], 0, 2); | |
422 | } | |
423 | ||
16a10ffd YB |
424 | static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv, |
425 | unsigned char *mac, int *qpn, u64 *reg_id) | |
426 | { | |
427 | struct mlx4_en_dev *mdev = priv->mdev; | |
428 | struct mlx4_dev *dev = mdev->dev; | |
429 | int err; | |
430 | ||
431 | switch (dev->caps.steering_mode) { | |
432 | case MLX4_STEERING_MODE_B0: { | |
433 | struct mlx4_qp qp; | |
434 | u8 gid[16] = {0}; | |
435 | ||
436 | qp.qpn = *qpn; | |
437 | memcpy(&gid[10], mac, ETH_ALEN); | |
438 | gid[5] = priv->port; | |
439 | ||
440 | err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH); | |
441 | break; | |
442 | } | |
443 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
444 | struct mlx4_spec_list spec_eth = { {NULL} }; | |
445 | __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16); | |
446 | ||
447 | struct mlx4_net_trans_rule rule = { | |
448 | .queue_mode = MLX4_NET_TRANS_Q_FIFO, | |
449 | .exclusive = 0, | |
450 | .allow_loopback = 1, | |
451 | .promisc_mode = MLX4_FS_PROMISC_NONE, | |
452 | .priority = MLX4_DOMAIN_NIC, | |
453 | }; | |
454 | ||
455 | rule.port = priv->port; | |
456 | rule.qpn = *qpn; | |
457 | INIT_LIST_HEAD(&rule.list); | |
458 | ||
459 | spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH; | |
460 | memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN); | |
461 | memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN); | |
462 | list_add_tail(&spec_eth.list, &rule.list); | |
463 | ||
464 | err = mlx4_flow_attach(dev, &rule, reg_id); | |
465 | break; | |
466 | } | |
467 | default: | |
468 | return -EINVAL; | |
469 | } | |
470 | if (err) | |
471 | en_warn(priv, "Failed Attaching Unicast\n"); | |
472 | ||
473 | return err; | |
474 | } | |
475 | ||
476 | static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv, | |
477 | unsigned char *mac, int qpn, u64 reg_id) | |
478 | { | |
479 | struct mlx4_en_dev *mdev = priv->mdev; | |
480 | struct mlx4_dev *dev = mdev->dev; | |
481 | ||
482 | switch (dev->caps.steering_mode) { | |
483 | case MLX4_STEERING_MODE_B0: { | |
484 | struct mlx4_qp qp; | |
485 | u8 gid[16] = {0}; | |
486 | ||
487 | qp.qpn = qpn; | |
488 | memcpy(&gid[10], mac, ETH_ALEN); | |
489 | gid[5] = priv->port; | |
490 | ||
491 | mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH); | |
492 | break; | |
493 | } | |
494 | case MLX4_STEERING_MODE_DEVICE_MANAGED: { | |
495 | mlx4_flow_detach(dev, reg_id); | |
496 | break; | |
497 | } | |
498 | default: | |
499 | en_err(priv, "Invalid steering mode.\n"); | |
500 | } | |
501 | } | |
502 | ||
503 | static int mlx4_en_get_qp(struct mlx4_en_priv *priv) | |
504 | { | |
505 | struct mlx4_en_dev *mdev = priv->mdev; | |
506 | struct mlx4_dev *dev = mdev->dev; | |
507 | struct mlx4_mac_entry *entry; | |
508 | int index = 0; | |
509 | int err = 0; | |
510 | u64 reg_id; | |
511 | int *qpn = &priv->base_qpn; | |
512 | u64 mac = mlx4_en_mac_to_u64(priv->dev->dev_addr); | |
513 | ||
514 | en_dbg(DRV, priv, "Registering MAC: %pM for adding\n", | |
515 | priv->dev->dev_addr); | |
516 | index = mlx4_register_mac(dev, priv->port, mac); | |
517 | if (index < 0) { | |
518 | err = index; | |
519 | en_err(priv, "Failed adding MAC: %pM\n", | |
520 | priv->dev->dev_addr); | |
521 | return err; | |
522 | } | |
523 | ||
524 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { | |
525 | int base_qpn = mlx4_get_base_qpn(dev, priv->port); | |
526 | *qpn = base_qpn + index; | |
527 | return 0; | |
528 | } | |
529 | ||
530 | err = mlx4_qp_reserve_range(dev, 1, 1, qpn); | |
531 | en_dbg(DRV, priv, "Reserved qp %d\n", *qpn); | |
532 | if (err) { | |
533 | en_err(priv, "Failed to reserve qp for mac registration\n"); | |
534 | goto qp_err; | |
535 | } | |
536 | ||
537 | err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, ®_id); | |
538 | if (err) | |
539 | goto steer_err; | |
540 | ||
541 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
542 | if (!entry) { | |
543 | err = -ENOMEM; | |
544 | goto alloc_err; | |
545 | } | |
546 | memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac)); | |
547 | entry->reg_id = reg_id; | |
548 | ||
c07cb4b0 YB |
549 | hlist_add_head_rcu(&entry->hlist, |
550 | &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]); | |
16a10ffd | 551 | |
c07cb4b0 | 552 | return 0; |
16a10ffd YB |
553 | |
554 | alloc_err: | |
555 | mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id); | |
556 | ||
557 | steer_err: | |
558 | mlx4_qp_release_range(dev, *qpn, 1); | |
559 | ||
560 | qp_err: | |
561 | mlx4_unregister_mac(dev, priv->port, mac); | |
562 | return err; | |
563 | } | |
564 | ||
565 | static void mlx4_en_put_qp(struct mlx4_en_priv *priv) | |
566 | { | |
567 | struct mlx4_en_dev *mdev = priv->mdev; | |
568 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd | 569 | int qpn = priv->base_qpn; |
83a5a6ce | 570 | u64 mac; |
16a10ffd | 571 | |
83a5a6ce YB |
572 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) { |
573 | mac = mlx4_en_mac_to_u64(priv->dev->dev_addr); | |
574 | en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n", | |
575 | priv->dev->dev_addr); | |
576 | mlx4_unregister_mac(dev, priv->port, mac); | |
577 | } else { | |
c07cb4b0 | 578 | struct mlx4_mac_entry *entry; |
b67bfe0d | 579 | struct hlist_node *tmp; |
c07cb4b0 | 580 | struct hlist_head *bucket; |
83a5a6ce | 581 | unsigned int i; |
c07cb4b0 | 582 | |
83a5a6ce YB |
583 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) { |
584 | bucket = &priv->mac_hash[i]; | |
585 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { | |
586 | mac = mlx4_en_mac_to_u64(entry->mac); | |
587 | en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n", | |
588 | entry->mac); | |
c07cb4b0 YB |
589 | mlx4_en_uc_steer_release(priv, entry->mac, |
590 | qpn, entry->reg_id); | |
c07cb4b0 | 591 | |
83a5a6ce | 592 | mlx4_unregister_mac(dev, priv->port, mac); |
c07cb4b0 YB |
593 | hlist_del_rcu(&entry->hlist); |
594 | kfree_rcu(entry, rcu); | |
c07cb4b0 | 595 | } |
16a10ffd | 596 | } |
83a5a6ce YB |
597 | |
598 | en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n", | |
599 | priv->port, qpn); | |
600 | mlx4_qp_release_range(dev, qpn, 1); | |
601 | priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC; | |
16a10ffd YB |
602 | } |
603 | } | |
604 | ||
605 | static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn, | |
90bbb74a | 606 | unsigned char *new_mac, unsigned char *prev_mac) |
16a10ffd YB |
607 | { |
608 | struct mlx4_en_dev *mdev = priv->mdev; | |
609 | struct mlx4_dev *dev = mdev->dev; | |
16a10ffd YB |
610 | int err = 0; |
611 | u64 new_mac_u64 = mlx4_en_mac_to_u64(new_mac); | |
612 | ||
613 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) { | |
c07cb4b0 YB |
614 | struct hlist_head *bucket; |
615 | unsigned int mac_hash; | |
616 | struct mlx4_mac_entry *entry; | |
b67bfe0d | 617 | struct hlist_node *tmp; |
c07cb4b0 YB |
618 | u64 prev_mac_u64 = mlx4_en_mac_to_u64(prev_mac); |
619 | ||
620 | bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]]; | |
b67bfe0d | 621 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { |
c07cb4b0 YB |
622 | if (ether_addr_equal_64bits(entry->mac, prev_mac)) { |
623 | mlx4_en_uc_steer_release(priv, entry->mac, | |
624 | qpn, entry->reg_id); | |
625 | mlx4_unregister_mac(dev, priv->port, | |
626 | prev_mac_u64); | |
627 | hlist_del_rcu(&entry->hlist); | |
628 | synchronize_rcu(); | |
629 | memcpy(entry->mac, new_mac, ETH_ALEN); | |
630 | entry->reg_id = 0; | |
631 | mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX]; | |
632 | hlist_add_head_rcu(&entry->hlist, | |
633 | &priv->mac_hash[mac_hash]); | |
634 | mlx4_register_mac(dev, priv->port, new_mac_u64); | |
635 | err = mlx4_en_uc_steer_add(priv, new_mac, | |
636 | &qpn, | |
637 | &entry->reg_id); | |
638 | return err; | |
639 | } | |
640 | } | |
641 | return -EINVAL; | |
16a10ffd YB |
642 | } |
643 | ||
644 | return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64); | |
645 | } | |
646 | ||
e7c1c2c4 | 647 | u64 mlx4_en_mac_to_u64(u8 *addr) |
c27a02cd YP |
648 | { |
649 | u64 mac = 0; | |
650 | int i; | |
651 | ||
652 | for (i = 0; i < ETH_ALEN; i++) { | |
653 | mac <<= 8; | |
654 | mac |= addr[i]; | |
655 | } | |
656 | return mac; | |
657 | } | |
658 | ||
bfa8ab47 | 659 | static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv) |
c27a02cd | 660 | { |
c27a02cd YP |
661 | int err = 0; |
662 | ||
c27a02cd YP |
663 | if (priv->port_up) { |
664 | /* Remove old MAC and insert the new one */ | |
16a10ffd | 665 | err = mlx4_en_replace_mac(priv, priv->base_qpn, |
90bbb74a | 666 | priv->dev->dev_addr, priv->prev_mac); |
c27a02cd | 667 | if (err) |
453a6082 | 668 | en_err(priv, "Failed changing HW MAC address\n"); |
6bbb6d99 YB |
669 | memcpy(priv->prev_mac, priv->dev->dev_addr, |
670 | sizeof(priv->prev_mac)); | |
c27a02cd | 671 | } else |
48e551ff | 672 | en_dbg(HW, priv, "Port is down while registering mac, exiting...\n"); |
c27a02cd | 673 | |
bfa8ab47 YB |
674 | return err; |
675 | } | |
676 | ||
677 | static int mlx4_en_set_mac(struct net_device *dev, void *addr) | |
678 | { | |
679 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
680 | struct mlx4_en_dev *mdev = priv->mdev; | |
681 | struct sockaddr *saddr = addr; | |
682 | int err; | |
683 | ||
684 | if (!is_valid_ether_addr(saddr->sa_data)) | |
685 | return -EADDRNOTAVAIL; | |
686 | ||
687 | memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN); | |
688 | ||
689 | mutex_lock(&mdev->state_lock); | |
690 | err = mlx4_en_do_set_mac(priv); | |
c27a02cd | 691 | mutex_unlock(&mdev->state_lock); |
bfa8ab47 YB |
692 | |
693 | return err; | |
c27a02cd YP |
694 | } |
695 | ||
696 | static void mlx4_en_clear_list(struct net_device *dev) | |
697 | { | |
698 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
6d199937 | 699 | struct mlx4_en_mc_list *tmp, *mc_to_del; |
c27a02cd | 700 | |
6d199937 YP |
701 | list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) { |
702 | list_del(&mc_to_del->list); | |
703 | kfree(mc_to_del); | |
704 | } | |
c27a02cd YP |
705 | } |
706 | ||
707 | static void mlx4_en_cache_mclist(struct net_device *dev) | |
708 | { | |
709 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
22bedad3 | 710 | struct netdev_hw_addr *ha; |
6d199937 | 711 | struct mlx4_en_mc_list *tmp; |
ff6e2163 | 712 | |
0e03567a | 713 | mlx4_en_clear_list(dev); |
6d199937 YP |
714 | netdev_for_each_mc_addr(ha, dev) { |
715 | tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC); | |
716 | if (!tmp) { | |
6d199937 YP |
717 | mlx4_en_clear_list(dev); |
718 | return; | |
719 | } | |
720 | memcpy(tmp->addr, ha->addr, ETH_ALEN); | |
721 | list_add_tail(&tmp->list, &priv->mc_list); | |
722 | } | |
c27a02cd YP |
723 | } |
724 | ||
6d199937 YP |
725 | static void update_mclist_flags(struct mlx4_en_priv *priv, |
726 | struct list_head *dst, | |
727 | struct list_head *src) | |
728 | { | |
729 | struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc; | |
730 | bool found; | |
731 | ||
732 | /* Find all the entries that should be removed from dst, | |
733 | * These are the entries that are not found in src | |
734 | */ | |
735 | list_for_each_entry(dst_tmp, dst, list) { | |
736 | found = false; | |
737 | list_for_each_entry(src_tmp, src, list) { | |
738 | if (!memcmp(dst_tmp->addr, src_tmp->addr, ETH_ALEN)) { | |
739 | found = true; | |
740 | break; | |
741 | } | |
742 | } | |
743 | if (!found) | |
744 | dst_tmp->action = MCLIST_REM; | |
745 | } | |
746 | ||
747 | /* Add entries that exist in src but not in dst | |
748 | * mark them as need to add | |
749 | */ | |
750 | list_for_each_entry(src_tmp, src, list) { | |
751 | found = false; | |
752 | list_for_each_entry(dst_tmp, dst, list) { | |
753 | if (!memcmp(dst_tmp->addr, src_tmp->addr, ETH_ALEN)) { | |
754 | dst_tmp->action = MCLIST_NONE; | |
755 | found = true; | |
756 | break; | |
757 | } | |
758 | } | |
759 | if (!found) { | |
14f8dc49 JP |
760 | new_mc = kmemdup(src_tmp, |
761 | sizeof(struct mlx4_en_mc_list), | |
6d199937 | 762 | GFP_KERNEL); |
14f8dc49 | 763 | if (!new_mc) |
6d199937 | 764 | return; |
14f8dc49 | 765 | |
6d199937 YP |
766 | new_mc->action = MCLIST_ADD; |
767 | list_add_tail(&new_mc->list, dst); | |
768 | } | |
769 | } | |
770 | } | |
c27a02cd | 771 | |
0eb74fdd | 772 | static void mlx4_en_set_rx_mode(struct net_device *dev) |
c27a02cd YP |
773 | { |
774 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
775 | ||
776 | if (!priv->port_up) | |
777 | return; | |
778 | ||
0eb74fdd | 779 | queue_work(priv->mdev->workqueue, &priv->rx_mode_task); |
c27a02cd YP |
780 | } |
781 | ||
0eb74fdd YB |
782 | static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv, |
783 | struct mlx4_en_dev *mdev) | |
c27a02cd | 784 | { |
c96d97f4 | 785 | int err = 0; |
c27a02cd | 786 | |
0eb74fdd | 787 | if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) { |
c27a02cd | 788 | if (netif_msg_rx_status(priv)) |
0eb74fdd YB |
789 | en_warn(priv, "Entering promiscuous mode\n"); |
790 | priv->flags |= MLX4_EN_FLAG_PROMISC; | |
c27a02cd | 791 | |
0eb74fdd | 792 | /* Enable promiscouos mode */ |
c96d97f4 | 793 | switch (mdev->dev->caps.steering_mode) { |
592e49dd | 794 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
0eb74fdd YB |
795 | err = mlx4_flow_steer_promisc_add(mdev->dev, |
796 | priv->port, | |
797 | priv->base_qpn, | |
798 | MLX4_FS_PROMISC_UPLINK); | |
592e49dd | 799 | if (err) |
0eb74fdd YB |
800 | en_err(priv, "Failed enabling promiscuous mode\n"); |
801 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
592e49dd HHZ |
802 | break; |
803 | ||
c96d97f4 | 804 | case MLX4_STEERING_MODE_B0: |
0eb74fdd YB |
805 | err = mlx4_unicast_promisc_add(mdev->dev, |
806 | priv->base_qpn, | |
807 | priv->port); | |
c96d97f4 | 808 | if (err) |
0eb74fdd YB |
809 | en_err(priv, "Failed enabling unicast promiscuous mode\n"); |
810 | ||
811 | /* Add the default qp number as multicast | |
812 | * promisc | |
813 | */ | |
814 | if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) { | |
815 | err = mlx4_multicast_promisc_add(mdev->dev, | |
816 | priv->base_qpn, | |
817 | priv->port); | |
c96d97f4 | 818 | if (err) |
0eb74fdd YB |
819 | en_err(priv, "Failed enabling multicast promiscuous mode\n"); |
820 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
c96d97f4 HHZ |
821 | } |
822 | break; | |
c27a02cd | 823 | |
c96d97f4 HHZ |
824 | case MLX4_STEERING_MODE_A0: |
825 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, | |
826 | priv->port, | |
0eb74fdd YB |
827 | priv->base_qpn, |
828 | 1); | |
1679200f | 829 | if (err) |
0eb74fdd | 830 | en_err(priv, "Failed enabling promiscuous mode\n"); |
c96d97f4 | 831 | break; |
1679200f YP |
832 | } |
833 | ||
0eb74fdd YB |
834 | /* Disable port multicast filter (unconditionally) */ |
835 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
836 | 0, MLX4_MCAST_DISABLE); | |
837 | if (err) | |
838 | en_err(priv, "Failed disabling multicast filter\n"); | |
839 | ||
840 | /* Disable port VLAN filter */ | |
f1b553fb | 841 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); |
c27a02cd | 842 | if (err) |
0eb74fdd YB |
843 | en_err(priv, "Failed disabling VLAN filter\n"); |
844 | } | |
845 | } | |
846 | ||
847 | static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv, | |
848 | struct mlx4_en_dev *mdev) | |
849 | { | |
850 | int err = 0; | |
851 | ||
852 | if (netif_msg_rx_status(priv)) | |
853 | en_warn(priv, "Leaving promiscuous mode\n"); | |
854 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; | |
855 | ||
856 | /* Disable promiscouos mode */ | |
857 | switch (mdev->dev->caps.steering_mode) { | |
858 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
859 | err = mlx4_flow_steer_promisc_remove(mdev->dev, | |
860 | priv->port, | |
861 | MLX4_FS_PROMISC_UPLINK); | |
862 | if (err) | |
863 | en_err(priv, "Failed disabling promiscuous mode\n"); | |
864 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
865 | break; | |
866 | ||
867 | case MLX4_STEERING_MODE_B0: | |
868 | err = mlx4_unicast_promisc_remove(mdev->dev, | |
869 | priv->base_qpn, | |
870 | priv->port); | |
871 | if (err) | |
872 | en_err(priv, "Failed disabling unicast promiscuous mode\n"); | |
873 | /* Disable Multicast promisc */ | |
874 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
875 | err = mlx4_multicast_promisc_remove(mdev->dev, | |
876 | priv->base_qpn, | |
877 | priv->port); | |
878 | if (err) | |
879 | en_err(priv, "Failed disabling multicast promiscuous mode\n"); | |
880 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
881 | } | |
882 | break; | |
883 | ||
884 | case MLX4_STEERING_MODE_A0: | |
885 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, | |
886 | priv->port, | |
887 | priv->base_qpn, 0); | |
888 | if (err) | |
889 | en_err(priv, "Failed disabling promiscuous mode\n"); | |
890 | break; | |
c27a02cd YP |
891 | } |
892 | ||
0eb74fdd YB |
893 | /* Enable port VLAN filter */ |
894 | err = mlx4_SET_VLAN_FLTR(mdev->dev, priv); | |
895 | if (err) | |
896 | en_err(priv, "Failed enabling VLAN filter\n"); | |
897 | } | |
898 | ||
899 | static void mlx4_en_do_multicast(struct mlx4_en_priv *priv, | |
900 | struct net_device *dev, | |
901 | struct mlx4_en_dev *mdev) | |
902 | { | |
903 | struct mlx4_en_mc_list *mclist, *tmp; | |
904 | u64 mcast_addr = 0; | |
905 | u8 mc_list[16] = {0}; | |
906 | int err = 0; | |
907 | ||
c27a02cd YP |
908 | /* Enable/disable the multicast filter according to IFF_ALLMULTI */ |
909 | if (dev->flags & IFF_ALLMULTI) { | |
910 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
911 | 0, MLX4_MCAST_DISABLE); | |
912 | if (err) | |
453a6082 | 913 | en_err(priv, "Failed disabling multicast filter\n"); |
1679200f YP |
914 | |
915 | /* Add the default qp number as multicast promisc */ | |
916 | if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) { | |
c96d97f4 | 917 | switch (mdev->dev->caps.steering_mode) { |
592e49dd HHZ |
918 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
919 | err = mlx4_flow_steer_promisc_add(mdev->dev, | |
920 | priv->port, | |
921 | priv->base_qpn, | |
922 | MLX4_FS_PROMISC_ALL_MULTI); | |
923 | break; | |
924 | ||
c96d97f4 HHZ |
925 | case MLX4_STEERING_MODE_B0: |
926 | err = mlx4_multicast_promisc_add(mdev->dev, | |
927 | priv->base_qpn, | |
928 | priv->port); | |
929 | break; | |
930 | ||
931 | case MLX4_STEERING_MODE_A0: | |
932 | break; | |
933 | } | |
1679200f YP |
934 | if (err) |
935 | en_err(priv, "Failed entering multicast promisc mode\n"); | |
936 | priv->flags |= MLX4_EN_FLAG_MC_PROMISC; | |
937 | } | |
c27a02cd | 938 | } else { |
1679200f YP |
939 | /* Disable Multicast promisc */ |
940 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
c96d97f4 | 941 | switch (mdev->dev->caps.steering_mode) { |
592e49dd HHZ |
942 | case MLX4_STEERING_MODE_DEVICE_MANAGED: |
943 | err = mlx4_flow_steer_promisc_remove(mdev->dev, | |
944 | priv->port, | |
945 | MLX4_FS_PROMISC_ALL_MULTI); | |
946 | break; | |
947 | ||
c96d97f4 HHZ |
948 | case MLX4_STEERING_MODE_B0: |
949 | err = mlx4_multicast_promisc_remove(mdev->dev, | |
950 | priv->base_qpn, | |
951 | priv->port); | |
952 | break; | |
953 | ||
954 | case MLX4_STEERING_MODE_A0: | |
955 | break; | |
956 | } | |
1679200f | 957 | if (err) |
25985edc | 958 | en_err(priv, "Failed disabling multicast promiscuous mode\n"); |
1679200f YP |
959 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; |
960 | } | |
ff6e2163 | 961 | |
c27a02cd YP |
962 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, |
963 | 0, MLX4_MCAST_DISABLE); | |
964 | if (err) | |
453a6082 | 965 | en_err(priv, "Failed disabling multicast filter\n"); |
c27a02cd YP |
966 | |
967 | /* Flush mcast filter and init it with broadcast address */ | |
968 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST, | |
969 | 1, MLX4_MCAST_CONFIG); | |
970 | ||
971 | /* Update multicast list - we cache all addresses so they won't | |
972 | * change while HW is updated holding the command semaphor */ | |
dbd501a8 | 973 | netif_addr_lock_bh(dev); |
c27a02cd | 974 | mlx4_en_cache_mclist(dev); |
dbd501a8 | 975 | netif_addr_unlock_bh(dev); |
6d199937 YP |
976 | list_for_each_entry(mclist, &priv->mc_list, list) { |
977 | mcast_addr = mlx4_en_mac_to_u64(mclist->addr); | |
c27a02cd YP |
978 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, |
979 | mcast_addr, 0, MLX4_MCAST_CONFIG); | |
980 | } | |
981 | err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, | |
982 | 0, MLX4_MCAST_ENABLE); | |
983 | if (err) | |
453a6082 | 984 | en_err(priv, "Failed enabling multicast filter\n"); |
6d199937 YP |
985 | |
986 | update_mclist_flags(priv, &priv->curr_list, &priv->mc_list); | |
987 | list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) { | |
988 | if (mclist->action == MCLIST_REM) { | |
989 | /* detach this address and delete from list */ | |
990 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
991 | mc_list[5] = priv->port; | |
992 | err = mlx4_multicast_detach(mdev->dev, | |
993 | &priv->rss_map.indir_qp, | |
994 | mc_list, | |
0ff1fb65 HHZ |
995 | MLX4_PROT_ETH, |
996 | mclist->reg_id); | |
6d199937 YP |
997 | if (err) |
998 | en_err(priv, "Fail to detach multicast address\n"); | |
999 | ||
1000 | /* remove from list */ | |
1001 | list_del(&mclist->list); | |
1002 | kfree(mclist); | |
9c64508a | 1003 | } else if (mclist->action == MCLIST_ADD) { |
6d199937 YP |
1004 | /* attach the address */ |
1005 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
0ff1fb65 | 1006 | /* needed for B0 steering support */ |
6d199937 YP |
1007 | mc_list[5] = priv->port; |
1008 | err = mlx4_multicast_attach(mdev->dev, | |
1009 | &priv->rss_map.indir_qp, | |
0ff1fb65 HHZ |
1010 | mc_list, |
1011 | priv->port, 0, | |
1012 | MLX4_PROT_ETH, | |
1013 | &mclist->reg_id); | |
6d199937 YP |
1014 | if (err) |
1015 | en_err(priv, "Fail to attach multicast address\n"); | |
1016 | ||
1017 | } | |
1018 | } | |
c27a02cd | 1019 | } |
0eb74fdd YB |
1020 | } |
1021 | ||
cc5387f7 YB |
1022 | static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv, |
1023 | struct net_device *dev, | |
1024 | struct mlx4_en_dev *mdev) | |
1025 | { | |
1026 | struct netdev_hw_addr *ha; | |
1027 | struct mlx4_mac_entry *entry; | |
b67bfe0d | 1028 | struct hlist_node *tmp; |
cc5387f7 YB |
1029 | bool found; |
1030 | u64 mac; | |
1031 | int err = 0; | |
1032 | struct hlist_head *bucket; | |
1033 | unsigned int i; | |
1034 | int removed = 0; | |
1035 | u32 prev_flags; | |
1036 | ||
1037 | /* Note that we do not need to protect our mac_hash traversal with rcu, | |
1038 | * since all modification code is protected by mdev->state_lock | |
1039 | */ | |
1040 | ||
1041 | /* find what to remove */ | |
1042 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) { | |
1043 | bucket = &priv->mac_hash[i]; | |
b67bfe0d | 1044 | hlist_for_each_entry_safe(entry, tmp, bucket, hlist) { |
cc5387f7 YB |
1045 | found = false; |
1046 | netdev_for_each_uc_addr(ha, dev) { | |
1047 | if (ether_addr_equal_64bits(entry->mac, | |
1048 | ha->addr)) { | |
1049 | found = true; | |
1050 | break; | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | /* MAC address of the port is not in uc list */ | |
1055 | if (ether_addr_equal_64bits(entry->mac, dev->dev_addr)) | |
1056 | found = true; | |
1057 | ||
1058 | if (!found) { | |
1059 | mac = mlx4_en_mac_to_u64(entry->mac); | |
1060 | mlx4_en_uc_steer_release(priv, entry->mac, | |
1061 | priv->base_qpn, | |
1062 | entry->reg_id); | |
1063 | mlx4_unregister_mac(mdev->dev, priv->port, mac); | |
1064 | ||
1065 | hlist_del_rcu(&entry->hlist); | |
1066 | kfree_rcu(entry, rcu); | |
1067 | en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n", | |
1068 | entry->mac, priv->port); | |
1069 | ++removed; | |
1070 | } | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | /* if we didn't remove anything, there is no use in trying to add | |
1075 | * again once we are in a forced promisc mode state | |
1076 | */ | |
1077 | if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed) | |
1078 | return; | |
1079 | ||
1080 | prev_flags = priv->flags; | |
1081 | priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC; | |
1082 | ||
1083 | /* find what to add */ | |
1084 | netdev_for_each_uc_addr(ha, dev) { | |
1085 | found = false; | |
1086 | bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]]; | |
b67bfe0d | 1087 | hlist_for_each_entry(entry, bucket, hlist) { |
cc5387f7 YB |
1088 | if (ether_addr_equal_64bits(entry->mac, ha->addr)) { |
1089 | found = true; | |
1090 | break; | |
1091 | } | |
1092 | } | |
1093 | ||
1094 | if (!found) { | |
1095 | entry = kmalloc(sizeof(*entry), GFP_KERNEL); | |
1096 | if (!entry) { | |
1097 | en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n", | |
1098 | ha->addr, priv->port); | |
1099 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1100 | break; | |
1101 | } | |
1102 | mac = mlx4_en_mac_to_u64(ha->addr); | |
1103 | memcpy(entry->mac, ha->addr, ETH_ALEN); | |
1104 | err = mlx4_register_mac(mdev->dev, priv->port, mac); | |
1105 | if (err < 0) { | |
1106 | en_err(priv, "Failed registering MAC %pM on port %d: %d\n", | |
1107 | ha->addr, priv->port, err); | |
1108 | kfree(entry); | |
1109 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1110 | break; | |
1111 | } | |
1112 | err = mlx4_en_uc_steer_add(priv, ha->addr, | |
1113 | &priv->base_qpn, | |
1114 | &entry->reg_id); | |
1115 | if (err) { | |
1116 | en_err(priv, "Failed adding MAC %pM on port %d: %d\n", | |
1117 | ha->addr, priv->port, err); | |
1118 | mlx4_unregister_mac(mdev->dev, priv->port, mac); | |
1119 | kfree(entry); | |
1120 | priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC; | |
1121 | break; | |
1122 | } else { | |
1123 | unsigned int mac_hash; | |
1124 | en_dbg(DRV, priv, "Added MAC %pM on port:%d\n", | |
1125 | ha->addr, priv->port); | |
1126 | mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX]; | |
1127 | bucket = &priv->mac_hash[mac_hash]; | |
1128 | hlist_add_head_rcu(&entry->hlist, bucket); | |
1129 | } | |
1130 | } | |
1131 | } | |
1132 | ||
1133 | if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) { | |
1134 | en_warn(priv, "Forcing promiscuous mode on port:%d\n", | |
1135 | priv->port); | |
1136 | } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) { | |
1137 | en_warn(priv, "Stop forcing promiscuous mode on port:%d\n", | |
1138 | priv->port); | |
1139 | } | |
1140 | } | |
1141 | ||
0eb74fdd YB |
1142 | static void mlx4_en_do_set_rx_mode(struct work_struct *work) |
1143 | { | |
1144 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1145 | rx_mode_task); | |
1146 | struct mlx4_en_dev *mdev = priv->mdev; | |
1147 | struct net_device *dev = priv->dev; | |
1148 | ||
1149 | mutex_lock(&mdev->state_lock); | |
1150 | if (!mdev->device_up) { | |
1151 | en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n"); | |
1152 | goto out; | |
1153 | } | |
1154 | if (!priv->port_up) { | |
1155 | en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n"); | |
1156 | goto out; | |
1157 | } | |
1158 | ||
1159 | if (!netif_carrier_ok(dev)) { | |
1160 | if (!mlx4_en_QUERY_PORT(mdev, priv->port)) { | |
1161 | if (priv->port_state.link_state) { | |
1162 | priv->last_link_state = MLX4_DEV_EVENT_PORT_UP; | |
1163 | netif_carrier_on(dev); | |
1164 | en_dbg(LINK, priv, "Link Up\n"); | |
1165 | } | |
1166 | } | |
1167 | } | |
1168 | ||
cc5387f7 YB |
1169 | if (dev->priv_flags & IFF_UNICAST_FLT) |
1170 | mlx4_en_do_uc_filter(priv, dev, mdev); | |
1171 | ||
0eb74fdd | 1172 | /* Promsicuous mode: disable all filters */ |
cc5387f7 YB |
1173 | if ((dev->flags & IFF_PROMISC) || |
1174 | (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) { | |
0eb74fdd YB |
1175 | mlx4_en_set_promisc_mode(priv, mdev); |
1176 | goto out; | |
1177 | } | |
1178 | ||
1179 | /* Not in promiscuous mode */ | |
1180 | if (priv->flags & MLX4_EN_FLAG_PROMISC) | |
1181 | mlx4_en_clear_promisc_mode(priv, mdev); | |
1182 | ||
1183 | mlx4_en_do_multicast(priv, dev, mdev); | |
c27a02cd YP |
1184 | out: |
1185 | mutex_unlock(&mdev->state_lock); | |
1186 | } | |
1187 | ||
1188 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1189 | static void mlx4_en_netpoll(struct net_device *dev) | |
1190 | { | |
1191 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1192 | struct mlx4_en_cq *cq; | |
1193 | unsigned long flags; | |
1194 | int i; | |
1195 | ||
1196 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1197 | cq = &priv->rx_cq[i]; | |
1198 | spin_lock_irqsave(&cq->lock, flags); | |
1199 | napi_synchronize(&cq->napi); | |
1200 | mlx4_en_process_rx_cq(dev, cq, 0); | |
1201 | spin_unlock_irqrestore(&cq->lock, flags); | |
1202 | } | |
1203 | } | |
1204 | #endif | |
1205 | ||
1206 | static void mlx4_en_tx_timeout(struct net_device *dev) | |
1207 | { | |
1208 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1209 | struct mlx4_en_dev *mdev = priv->mdev; | |
1210 | ||
1211 | if (netif_msg_timer(priv)) | |
453a6082 | 1212 | en_warn(priv, "Tx timeout called on port:%d\n", priv->port); |
c27a02cd | 1213 | |
1e338db5 | 1214 | priv->port_stats.tx_timeout++; |
453a6082 | 1215 | en_dbg(DRV, priv, "Scheduling watchdog\n"); |
1e338db5 | 1216 | queue_work(mdev->workqueue, &priv->watchdog_task); |
c27a02cd YP |
1217 | } |
1218 | ||
1219 | ||
1220 | static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev) | |
1221 | { | |
1222 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1223 | ||
1224 | spin_lock_bh(&priv->stats_lock); | |
1225 | memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats)); | |
1226 | spin_unlock_bh(&priv->stats_lock); | |
1227 | ||
1228 | return &priv->ret_stats; | |
1229 | } | |
1230 | ||
1231 | static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv) | |
1232 | { | |
c27a02cd YP |
1233 | struct mlx4_en_cq *cq; |
1234 | int i; | |
1235 | ||
1236 | /* If we haven't received a specific coalescing setting | |
98a1708d | 1237 | * (module param), we set the moderation parameters as follows: |
c27a02cd | 1238 | * - moder_cnt is set to the number of mtu sized packets to |
ecfd2ce1 | 1239 | * satisfy our coalescing target. |
c27a02cd YP |
1240 | * - moder_time is set to a fixed value. |
1241 | */ | |
3db36fb2 | 1242 | priv->rx_frames = MLX4_EN_RX_COAL_TARGET; |
60b9f9e5 | 1243 | priv->rx_usecs = MLX4_EN_RX_COAL_TIME; |
a19a848a YP |
1244 | priv->tx_frames = MLX4_EN_TX_COAL_PKTS; |
1245 | priv->tx_usecs = MLX4_EN_TX_COAL_TIME; | |
48e551ff YB |
1246 | en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n", |
1247 | priv->dev->mtu, priv->rx_frames, priv->rx_usecs); | |
c27a02cd YP |
1248 | |
1249 | /* Setup cq moderation params */ | |
1250 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1251 | cq = &priv->rx_cq[i]; | |
1252 | cq->moder_cnt = priv->rx_frames; | |
1253 | cq->moder_time = priv->rx_usecs; | |
6b4d8d9f AG |
1254 | priv->last_moder_time[i] = MLX4_EN_AUTO_CONF; |
1255 | priv->last_moder_packets[i] = 0; | |
1256 | priv->last_moder_bytes[i] = 0; | |
c27a02cd YP |
1257 | } |
1258 | ||
1259 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1260 | cq = &priv->tx_cq[i]; | |
a19a848a YP |
1261 | cq->moder_cnt = priv->tx_frames; |
1262 | cq->moder_time = priv->tx_usecs; | |
c27a02cd YP |
1263 | } |
1264 | ||
1265 | /* Reset auto-moderation params */ | |
1266 | priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW; | |
1267 | priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW; | |
1268 | priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH; | |
1269 | priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH; | |
1270 | priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL; | |
60b9f9e5 | 1271 | priv->adaptive_rx_coal = 1; |
c27a02cd | 1272 | priv->last_moder_jiffies = 0; |
c27a02cd | 1273 | priv->last_moder_tx_packets = 0; |
c27a02cd YP |
1274 | } |
1275 | ||
1276 | static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv) | |
1277 | { | |
1278 | unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies); | |
c27a02cd YP |
1279 | struct mlx4_en_cq *cq; |
1280 | unsigned long packets; | |
1281 | unsigned long rate; | |
1282 | unsigned long avg_pkt_size; | |
1283 | unsigned long rx_packets; | |
1284 | unsigned long rx_bytes; | |
c27a02cd YP |
1285 | unsigned long rx_pkt_diff; |
1286 | int moder_time; | |
6b4d8d9f | 1287 | int ring, err; |
c27a02cd YP |
1288 | |
1289 | if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ) | |
1290 | return; | |
1291 | ||
6b4d8d9f AG |
1292 | for (ring = 0; ring < priv->rx_ring_num; ring++) { |
1293 | spin_lock_bh(&priv->stats_lock); | |
1294 | rx_packets = priv->rx_ring[ring].packets; | |
1295 | rx_bytes = priv->rx_ring[ring].bytes; | |
1296 | spin_unlock_bh(&priv->stats_lock); | |
1297 | ||
1298 | rx_pkt_diff = ((unsigned long) (rx_packets - | |
1299 | priv->last_moder_packets[ring])); | |
1300 | packets = rx_pkt_diff; | |
1301 | rate = packets * HZ / period; | |
1302 | avg_pkt_size = packets ? ((unsigned long) (rx_bytes - | |
1303 | priv->last_moder_bytes[ring])) / packets : 0; | |
1304 | ||
1305 | /* Apply auto-moderation only when packet rate | |
1306 | * exceeds a rate that it matters */ | |
1307 | if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) && | |
1308 | avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) { | |
c27a02cd YP |
1309 | if (rate < priv->pkt_rate_low) |
1310 | moder_time = priv->rx_usecs_low; | |
1311 | else if (rate > priv->pkt_rate_high) | |
1312 | moder_time = priv->rx_usecs_high; | |
1313 | else | |
1314 | moder_time = (rate - priv->pkt_rate_low) * | |
1315 | (priv->rx_usecs_high - priv->rx_usecs_low) / | |
1316 | (priv->pkt_rate_high - priv->pkt_rate_low) + | |
1317 | priv->rx_usecs_low; | |
6b4d8d9f AG |
1318 | } else { |
1319 | moder_time = priv->rx_usecs_low; | |
c27a02cd | 1320 | } |
c27a02cd | 1321 | |
6b4d8d9f AG |
1322 | if (moder_time != priv->last_moder_time[ring]) { |
1323 | priv->last_moder_time[ring] = moder_time; | |
1324 | cq = &priv->rx_cq[ring]; | |
c27a02cd YP |
1325 | cq->moder_time = moder_time; |
1326 | err = mlx4_en_set_cq_moder(priv, cq); | |
6b4d8d9f | 1327 | if (err) |
48e551ff YB |
1328 | en_err(priv, "Failed modifying moderation for cq:%d\n", |
1329 | ring); | |
c27a02cd | 1330 | } |
6b4d8d9f AG |
1331 | priv->last_moder_packets[ring] = rx_packets; |
1332 | priv->last_moder_bytes[ring] = rx_bytes; | |
c27a02cd YP |
1333 | } |
1334 | ||
c27a02cd YP |
1335 | priv->last_moder_jiffies = jiffies; |
1336 | } | |
1337 | ||
1338 | static void mlx4_en_do_get_stats(struct work_struct *work) | |
1339 | { | |
bf6aede7 | 1340 | struct delayed_work *delay = to_delayed_work(work); |
c27a02cd YP |
1341 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, |
1342 | stats_task); | |
1343 | struct mlx4_en_dev *mdev = priv->mdev; | |
1344 | int err; | |
1345 | ||
c27a02cd YP |
1346 | mutex_lock(&mdev->state_lock); |
1347 | if (mdev->device_up) { | |
2d51837f EE |
1348 | err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0); |
1349 | if (err) | |
1350 | en_dbg(HW, priv, "Could not update stats\n"); | |
1351 | ||
c27a02cd YP |
1352 | if (priv->port_up) |
1353 | mlx4_en_auto_moderation(priv); | |
1354 | ||
1355 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); | |
1356 | } | |
d7e1a487 | 1357 | if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) { |
bfa8ab47 | 1358 | mlx4_en_do_set_mac(priv); |
d7e1a487 YP |
1359 | mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0; |
1360 | } | |
c27a02cd YP |
1361 | mutex_unlock(&mdev->state_lock); |
1362 | } | |
1363 | ||
b6c39bfc AV |
1364 | /* mlx4_en_service_task - Run service task for tasks that needed to be done |
1365 | * periodically | |
1366 | */ | |
1367 | static void mlx4_en_service_task(struct work_struct *work) | |
1368 | { | |
1369 | struct delayed_work *delay = to_delayed_work(work); | |
1370 | struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv, | |
1371 | service_task); | |
1372 | struct mlx4_en_dev *mdev = priv->mdev; | |
1373 | ||
1374 | mutex_lock(&mdev->state_lock); | |
1375 | if (mdev->device_up) { | |
1376 | mlx4_en_ptp_overflow_check(mdev); | |
1377 | ||
1378 | queue_delayed_work(mdev->workqueue, &priv->service_task, | |
1379 | SERVICE_TASK_DELAY); | |
1380 | } | |
1381 | mutex_unlock(&mdev->state_lock); | |
1382 | } | |
1383 | ||
c27a02cd YP |
1384 | static void mlx4_en_linkstate(struct work_struct *work) |
1385 | { | |
1386 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1387 | linkstate_task); | |
1388 | struct mlx4_en_dev *mdev = priv->mdev; | |
1389 | int linkstate = priv->link_state; | |
1390 | ||
1391 | mutex_lock(&mdev->state_lock); | |
1392 | /* If observable port state changed set carrier state and | |
1393 | * report to system log */ | |
1394 | if (priv->last_link_state != linkstate) { | |
1395 | if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) { | |
e5cc44b2 | 1396 | en_info(priv, "Link Down\n"); |
c27a02cd YP |
1397 | netif_carrier_off(priv->dev); |
1398 | } else { | |
e5cc44b2 | 1399 | en_info(priv, "Link Up\n"); |
c27a02cd YP |
1400 | netif_carrier_on(priv->dev); |
1401 | } | |
1402 | } | |
1403 | priv->last_link_state = linkstate; | |
1404 | mutex_unlock(&mdev->state_lock); | |
1405 | } | |
1406 | ||
1407 | ||
18cc42a3 | 1408 | int mlx4_en_start_port(struct net_device *dev) |
c27a02cd YP |
1409 | { |
1410 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1411 | struct mlx4_en_dev *mdev = priv->mdev; | |
1412 | struct mlx4_en_cq *cq; | |
1413 | struct mlx4_en_tx_ring *tx_ring; | |
c27a02cd YP |
1414 | int rx_index = 0; |
1415 | int tx_index = 0; | |
c27a02cd YP |
1416 | int err = 0; |
1417 | int i; | |
1418 | int j; | |
1679200f | 1419 | u8 mc_list[16] = {0}; |
c27a02cd YP |
1420 | |
1421 | if (priv->port_up) { | |
453a6082 | 1422 | en_dbg(DRV, priv, "start port called while port already up\n"); |
c27a02cd YP |
1423 | return 0; |
1424 | } | |
1425 | ||
6d199937 YP |
1426 | INIT_LIST_HEAD(&priv->mc_list); |
1427 | INIT_LIST_HEAD(&priv->curr_list); | |
0d256c0e HHZ |
1428 | INIT_LIST_HEAD(&priv->ethtool_list); |
1429 | memset(&priv->ethtool_rules[0], 0, | |
1430 | sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES); | |
6d199937 | 1431 | |
c27a02cd YP |
1432 | /* Calculate Rx buf size */ |
1433 | dev->mtu = min(dev->mtu, priv->max_mtu); | |
1434 | mlx4_en_calc_rx_buf(dev); | |
453a6082 | 1435 | en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size); |
38aab07c | 1436 | |
c27a02cd | 1437 | /* Configure rx cq's and rings */ |
38aab07c YP |
1438 | err = mlx4_en_activate_rx_rings(priv); |
1439 | if (err) { | |
453a6082 | 1440 | en_err(priv, "Failed to activate RX rings\n"); |
38aab07c YP |
1441 | return err; |
1442 | } | |
c27a02cd YP |
1443 | for (i = 0; i < priv->rx_ring_num; i++) { |
1444 | cq = &priv->rx_cq[i]; | |
c27a02cd | 1445 | |
76532d0c | 1446 | err = mlx4_en_activate_cq(priv, cq, i); |
c27a02cd | 1447 | if (err) { |
453a6082 | 1448 | en_err(priv, "Failed activating Rx CQ\n"); |
a4233304 | 1449 | goto cq_err; |
c27a02cd YP |
1450 | } |
1451 | for (j = 0; j < cq->size; j++) | |
1452 | cq->buf[j].owner_sr_opcode = MLX4_CQE_OWNER_MASK; | |
1453 | err = mlx4_en_set_cq_moder(priv, cq); | |
1454 | if (err) { | |
453a6082 | 1455 | en_err(priv, "Failed setting cq moderation parameters"); |
c27a02cd YP |
1456 | mlx4_en_deactivate_cq(priv, cq); |
1457 | goto cq_err; | |
1458 | } | |
1459 | mlx4_en_arm_cq(priv, cq); | |
38aab07c | 1460 | priv->rx_ring[i].cqn = cq->mcq.cqn; |
c27a02cd YP |
1461 | ++rx_index; |
1462 | } | |
1463 | ||
ffe455ad EE |
1464 | /* Set qp number */ |
1465 | en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port); | |
16a10ffd | 1466 | err = mlx4_en_get_qp(priv); |
1679200f | 1467 | if (err) { |
ffe455ad | 1468 | en_err(priv, "Failed getting eth qp\n"); |
1679200f YP |
1469 | goto cq_err; |
1470 | } | |
1471 | mdev->mac_removed[priv->port] = 0; | |
1472 | ||
c27a02cd YP |
1473 | err = mlx4_en_config_rss_steer(priv); |
1474 | if (err) { | |
453a6082 | 1475 | en_err(priv, "Failed configuring rss steering\n"); |
1679200f | 1476 | goto mac_err; |
c27a02cd YP |
1477 | } |
1478 | ||
cabdc8ee HHZ |
1479 | err = mlx4_en_create_drop_qp(priv); |
1480 | if (err) | |
1481 | goto rss_err; | |
1482 | ||
c27a02cd YP |
1483 | /* Configure tx cq's and rings */ |
1484 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1485 | /* Configure cq */ | |
1486 | cq = &priv->tx_cq[i]; | |
76532d0c | 1487 | err = mlx4_en_activate_cq(priv, cq, i); |
c27a02cd | 1488 | if (err) { |
453a6082 | 1489 | en_err(priv, "Failed allocating Tx CQ\n"); |
c27a02cd YP |
1490 | goto tx_err; |
1491 | } | |
1492 | err = mlx4_en_set_cq_moder(priv, cq); | |
1493 | if (err) { | |
453a6082 | 1494 | en_err(priv, "Failed setting cq moderation parameters"); |
c27a02cd YP |
1495 | mlx4_en_deactivate_cq(priv, cq); |
1496 | goto tx_err; | |
1497 | } | |
453a6082 | 1498 | en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i); |
c27a02cd YP |
1499 | cq->buf->wqe_index = cpu_to_be16(0xffff); |
1500 | ||
1501 | /* Configure ring */ | |
1502 | tx_ring = &priv->tx_ring[i]; | |
0e98b523 | 1503 | err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn, |
d317966b | 1504 | i / priv->num_tx_rings_p_up); |
c27a02cd | 1505 | if (err) { |
453a6082 | 1506 | en_err(priv, "Failed allocating Tx ring\n"); |
c27a02cd YP |
1507 | mlx4_en_deactivate_cq(priv, cq); |
1508 | goto tx_err; | |
1509 | } | |
5b263f53 | 1510 | tx_ring->tx_queue = netdev_get_tx_queue(dev, i); |
e22979d9 YP |
1511 | |
1512 | /* Arm CQ for TX completions */ | |
1513 | mlx4_en_arm_cq(priv, cq); | |
1514 | ||
c27a02cd YP |
1515 | /* Set initial ownership of all Tx TXBBs to SW (1) */ |
1516 | for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE) | |
1517 | *((u32 *) (tx_ring->buf + j)) = 0xffffffff; | |
1518 | ++tx_index; | |
1519 | } | |
1520 | ||
1521 | /* Configure port */ | |
1522 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, | |
1523 | priv->rx_skb_size + ETH_FCS_LEN, | |
d53b93f2 YP |
1524 | priv->prof->tx_pause, |
1525 | priv->prof->tx_ppp, | |
1526 | priv->prof->rx_pause, | |
1527 | priv->prof->rx_ppp); | |
c27a02cd | 1528 | if (err) { |
48e551ff YB |
1529 | en_err(priv, "Failed setting port general configurations for port %d, with error %d\n", |
1530 | priv->port, err); | |
c27a02cd YP |
1531 | goto tx_err; |
1532 | } | |
1533 | /* Set default qp number */ | |
1534 | err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0); | |
1535 | if (err) { | |
453a6082 | 1536 | en_err(priv, "Failed setting default qp numbers\n"); |
c27a02cd YP |
1537 | goto tx_err; |
1538 | } | |
c27a02cd YP |
1539 | |
1540 | /* Init port */ | |
453a6082 | 1541 | en_dbg(HW, priv, "Initializing port\n"); |
c27a02cd YP |
1542 | err = mlx4_INIT_PORT(mdev->dev, priv->port); |
1543 | if (err) { | |
453a6082 | 1544 | en_err(priv, "Failed Initializing port\n"); |
1679200f | 1545 | goto tx_err; |
c27a02cd YP |
1546 | } |
1547 | ||
1679200f YP |
1548 | /* Attach rx QP to bradcast address */ |
1549 | memset(&mc_list[10], 0xff, ETH_ALEN); | |
0ff1fb65 | 1550 | mc_list[5] = priv->port; /* needed for B0 steering support */ |
1679200f | 1551 | if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list, |
0ff1fb65 HHZ |
1552 | priv->port, 0, MLX4_PROT_ETH, |
1553 | &priv->broadcast_id)) | |
1679200f YP |
1554 | mlx4_warn(mdev, "Failed Attaching Broadcast\n"); |
1555 | ||
b5845f98 HX |
1556 | /* Must redo promiscuous mode setup. */ |
1557 | priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC); | |
1558 | ||
c27a02cd | 1559 | /* Schedule multicast task to populate multicast list */ |
0eb74fdd | 1560 | queue_work(mdev->workqueue, &priv->rx_mode_task); |
c27a02cd | 1561 | |
93ece0c1 EE |
1562 | mlx4_set_stats_bitmap(mdev->dev, &priv->stats_bitmap); |
1563 | ||
c27a02cd | 1564 | priv->port_up = true; |
a11faac7 | 1565 | netif_tx_start_all_queues(dev); |
3484aac1 AV |
1566 | netif_device_attach(dev); |
1567 | ||
c27a02cd YP |
1568 | return 0; |
1569 | ||
c27a02cd YP |
1570 | tx_err: |
1571 | while (tx_index--) { | |
1572 | mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[tx_index]); | |
1573 | mlx4_en_deactivate_cq(priv, &priv->tx_cq[tx_index]); | |
1574 | } | |
cabdc8ee HHZ |
1575 | mlx4_en_destroy_drop_qp(priv); |
1576 | rss_err: | |
c27a02cd | 1577 | mlx4_en_release_rss_steer(priv); |
1679200f | 1578 | mac_err: |
16a10ffd | 1579 | mlx4_en_put_qp(priv); |
c27a02cd YP |
1580 | cq_err: |
1581 | while (rx_index--) | |
1582 | mlx4_en_deactivate_cq(priv, &priv->rx_cq[rx_index]); | |
38aab07c YP |
1583 | for (i = 0; i < priv->rx_ring_num; i++) |
1584 | mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); | |
c27a02cd YP |
1585 | |
1586 | return err; /* need to close devices */ | |
1587 | } | |
1588 | ||
1589 | ||
3484aac1 | 1590 | void mlx4_en_stop_port(struct net_device *dev, int detach) |
c27a02cd YP |
1591 | { |
1592 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1593 | struct mlx4_en_dev *mdev = priv->mdev; | |
6d199937 | 1594 | struct mlx4_en_mc_list *mclist, *tmp; |
0d256c0e | 1595 | struct ethtool_flow_id *flow, *tmp_flow; |
c27a02cd | 1596 | int i; |
1679200f | 1597 | u8 mc_list[16] = {0}; |
c27a02cd YP |
1598 | |
1599 | if (!priv->port_up) { | |
453a6082 | 1600 | en_dbg(DRV, priv, "stop port called while port already down\n"); |
c27a02cd YP |
1601 | return; |
1602 | } | |
c27a02cd YP |
1603 | |
1604 | /* Synchronize with tx routine */ | |
1605 | netif_tx_lock_bh(dev); | |
3484aac1 AV |
1606 | if (detach) |
1607 | netif_device_detach(dev); | |
3c05f5ef | 1608 | netif_tx_stop_all_queues(dev); |
c27a02cd YP |
1609 | netif_tx_unlock_bh(dev); |
1610 | ||
3484aac1 AV |
1611 | netif_tx_disable(dev); |
1612 | ||
7c287380 | 1613 | /* Set port as not active */ |
3c05f5ef | 1614 | priv->port_up = false; |
c27a02cd | 1615 | |
db0e7cba AY |
1616 | /* Promsicuous mode */ |
1617 | if (mdev->dev->caps.steering_mode == | |
1618 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1619 | priv->flags &= ~(MLX4_EN_FLAG_PROMISC | | |
1620 | MLX4_EN_FLAG_MC_PROMISC); | |
1621 | mlx4_flow_steer_promisc_remove(mdev->dev, | |
1622 | priv->port, | |
1623 | MLX4_FS_PROMISC_UPLINK); | |
1624 | mlx4_flow_steer_promisc_remove(mdev->dev, | |
1625 | priv->port, | |
1626 | MLX4_FS_PROMISC_ALL_MULTI); | |
1627 | } else if (priv->flags & MLX4_EN_FLAG_PROMISC) { | |
1628 | priv->flags &= ~MLX4_EN_FLAG_PROMISC; | |
1629 | ||
1630 | /* Disable promiscouos mode */ | |
1631 | mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn, | |
1632 | priv->port); | |
1633 | ||
1634 | /* Disable Multicast promisc */ | |
1635 | if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) { | |
1636 | mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn, | |
1637 | priv->port); | |
1638 | priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC; | |
1639 | } | |
1640 | } | |
1641 | ||
1679200f YP |
1642 | /* Detach All multicasts */ |
1643 | memset(&mc_list[10], 0xff, ETH_ALEN); | |
0ff1fb65 | 1644 | mc_list[5] = priv->port; /* needed for B0 steering support */ |
1679200f | 1645 | mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list, |
0ff1fb65 | 1646 | MLX4_PROT_ETH, priv->broadcast_id); |
6d199937 YP |
1647 | list_for_each_entry(mclist, &priv->curr_list, list) { |
1648 | memcpy(&mc_list[10], mclist->addr, ETH_ALEN); | |
1679200f YP |
1649 | mc_list[5] = priv->port; |
1650 | mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, | |
0ff1fb65 | 1651 | mc_list, MLX4_PROT_ETH, mclist->reg_id); |
1679200f YP |
1652 | } |
1653 | mlx4_en_clear_list(dev); | |
6d199937 YP |
1654 | list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) { |
1655 | list_del(&mclist->list); | |
1656 | kfree(mclist); | |
1657 | } | |
1658 | ||
1679200f YP |
1659 | /* Flush multicast filter */ |
1660 | mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG); | |
1661 | ||
6efb5fac HHZ |
1662 | /* Remove flow steering rules for the port*/ |
1663 | if (mdev->dev->caps.steering_mode == | |
1664 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1665 | ASSERT_RTNL(); | |
1666 | list_for_each_entry_safe(flow, tmp_flow, | |
1667 | &priv->ethtool_list, list) { | |
1668 | mlx4_flow_detach(mdev->dev, flow->id); | |
1669 | list_del(&flow->list); | |
1670 | } | |
1671 | } | |
1672 | ||
cabdc8ee HHZ |
1673 | mlx4_en_destroy_drop_qp(priv); |
1674 | ||
c27a02cd YP |
1675 | /* Free TX Rings */ |
1676 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1677 | mlx4_en_deactivate_tx_ring(priv, &priv->tx_ring[i]); | |
1678 | mlx4_en_deactivate_cq(priv, &priv->tx_cq[i]); | |
1679 | } | |
1680 | msleep(10); | |
1681 | ||
1682 | for (i = 0; i < priv->tx_ring_num; i++) | |
1683 | mlx4_en_free_tx_buf(dev, &priv->tx_ring[i]); | |
1684 | ||
1685 | /* Free RSS qps */ | |
1686 | mlx4_en_release_rss_steer(priv); | |
1687 | ||
ffe455ad | 1688 | /* Unregister Mac address for the port */ |
16a10ffd | 1689 | mlx4_en_put_qp(priv); |
955154fa MB |
1690 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN)) |
1691 | mdev->mac_removed[priv->port] = 1; | |
ffe455ad | 1692 | |
c27a02cd YP |
1693 | /* Free RX Rings */ |
1694 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1695 | mlx4_en_deactivate_rx_ring(priv, &priv->rx_ring[i]); | |
1696 | while (test_bit(NAPI_STATE_SCHED, &priv->rx_cq[i].napi.state)) | |
1697 | msleep(1); | |
1698 | mlx4_en_deactivate_cq(priv, &priv->rx_cq[i]); | |
1699 | } | |
7c287380 YP |
1700 | |
1701 | /* close port*/ | |
1702 | mlx4_CLOSE_PORT(mdev->dev, priv->port); | |
c27a02cd YP |
1703 | } |
1704 | ||
1705 | static void mlx4_en_restart(struct work_struct *work) | |
1706 | { | |
1707 | struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv, | |
1708 | watchdog_task); | |
1709 | struct mlx4_en_dev *mdev = priv->mdev; | |
1710 | struct net_device *dev = priv->dev; | |
1711 | ||
453a6082 | 1712 | en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port); |
1e338db5 YP |
1713 | |
1714 | mutex_lock(&mdev->state_lock); | |
1715 | if (priv->port_up) { | |
3484aac1 | 1716 | mlx4_en_stop_port(dev, 1); |
1e338db5 | 1717 | if (mlx4_en_start_port(dev)) |
453a6082 | 1718 | en_err(priv, "Failed restarting port %d\n", priv->port); |
1e338db5 YP |
1719 | } |
1720 | mutex_unlock(&mdev->state_lock); | |
c27a02cd YP |
1721 | } |
1722 | ||
b477ba62 | 1723 | static void mlx4_en_clear_stats(struct net_device *dev) |
c27a02cd YP |
1724 | { |
1725 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1726 | struct mlx4_en_dev *mdev = priv->mdev; | |
1727 | int i; | |
c27a02cd | 1728 | |
c27a02cd | 1729 | if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1)) |
453a6082 | 1730 | en_dbg(HW, priv, "Failed dumping statistics\n"); |
c27a02cd YP |
1731 | |
1732 | memset(&priv->stats, 0, sizeof(priv->stats)); | |
1733 | memset(&priv->pstats, 0, sizeof(priv->pstats)); | |
b477ba62 EE |
1734 | memset(&priv->pkstats, 0, sizeof(priv->pkstats)); |
1735 | memset(&priv->port_stats, 0, sizeof(priv->port_stats)); | |
c27a02cd YP |
1736 | |
1737 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1738 | priv->tx_ring[i].bytes = 0; | |
1739 | priv->tx_ring[i].packets = 0; | |
b477ba62 | 1740 | priv->tx_ring[i].tx_csum = 0; |
c27a02cd YP |
1741 | } |
1742 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1743 | priv->rx_ring[i].bytes = 0; | |
1744 | priv->rx_ring[i].packets = 0; | |
b477ba62 EE |
1745 | priv->rx_ring[i].csum_ok = 0; |
1746 | priv->rx_ring[i].csum_none = 0; | |
c27a02cd | 1747 | } |
b477ba62 EE |
1748 | } |
1749 | ||
1750 | static int mlx4_en_open(struct net_device *dev) | |
1751 | { | |
1752 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1753 | struct mlx4_en_dev *mdev = priv->mdev; | |
1754 | int err = 0; | |
1755 | ||
1756 | mutex_lock(&mdev->state_lock); | |
1757 | ||
1758 | if (!mdev->device_up) { | |
1759 | en_err(priv, "Cannot open - device down/disabled\n"); | |
1760 | err = -EBUSY; | |
1761 | goto out; | |
1762 | } | |
1763 | ||
1764 | /* Reset HW statistics and SW counters */ | |
1765 | mlx4_en_clear_stats(dev); | |
c27a02cd | 1766 | |
c27a02cd YP |
1767 | err = mlx4_en_start_port(dev); |
1768 | if (err) | |
453a6082 | 1769 | en_err(priv, "Failed starting port:%d\n", priv->port); |
c27a02cd YP |
1770 | |
1771 | out: | |
1772 | mutex_unlock(&mdev->state_lock); | |
1773 | return err; | |
1774 | } | |
1775 | ||
1776 | ||
1777 | static int mlx4_en_close(struct net_device *dev) | |
1778 | { | |
1779 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1780 | struct mlx4_en_dev *mdev = priv->mdev; | |
1781 | ||
453a6082 | 1782 | en_dbg(IFDOWN, priv, "Close port called\n"); |
c27a02cd YP |
1783 | |
1784 | mutex_lock(&mdev->state_lock); | |
1785 | ||
3484aac1 | 1786 | mlx4_en_stop_port(dev, 0); |
c27a02cd YP |
1787 | netif_carrier_off(dev); |
1788 | ||
1789 | mutex_unlock(&mdev->state_lock); | |
1790 | return 0; | |
1791 | } | |
1792 | ||
fe0af03c | 1793 | void mlx4_en_free_resources(struct mlx4_en_priv *priv) |
c27a02cd YP |
1794 | { |
1795 | int i; | |
1796 | ||
1eb8c695 AV |
1797 | #ifdef CONFIG_RFS_ACCEL |
1798 | free_irq_cpu_rmap(priv->dev->rx_cpu_rmap); | |
1799 | priv->dev->rx_cpu_rmap = NULL; | |
1800 | #endif | |
1801 | ||
c27a02cd YP |
1802 | for (i = 0; i < priv->tx_ring_num; i++) { |
1803 | if (priv->tx_ring[i].tx_info) | |
1804 | mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]); | |
1805 | if (priv->tx_cq[i].buf) | |
fe0af03c | 1806 | mlx4_en_destroy_cq(priv, &priv->tx_cq[i]); |
c27a02cd YP |
1807 | } |
1808 | ||
1809 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1810 | if (priv->rx_ring[i].rx_info) | |
68355f71 TLSC |
1811 | mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i], |
1812 | priv->prof->rx_ring_size, priv->stride); | |
c27a02cd | 1813 | if (priv->rx_cq[i].buf) |
fe0af03c | 1814 | mlx4_en_destroy_cq(priv, &priv->rx_cq[i]); |
c27a02cd | 1815 | } |
044ca2a5 YP |
1816 | |
1817 | if (priv->base_tx_qpn) { | |
1818 | mlx4_qp_release_range(priv->mdev->dev, priv->base_tx_qpn, priv->tx_ring_num); | |
1819 | priv->base_tx_qpn = 0; | |
1820 | } | |
c27a02cd YP |
1821 | } |
1822 | ||
18cc42a3 | 1823 | int mlx4_en_alloc_resources(struct mlx4_en_priv *priv) |
c27a02cd | 1824 | { |
c27a02cd YP |
1825 | struct mlx4_en_port_profile *prof = priv->prof; |
1826 | int i; | |
044ca2a5 | 1827 | int err; |
87a5c389 | 1828 | |
044ca2a5 | 1829 | err = mlx4_qp_reserve_range(priv->mdev->dev, priv->tx_ring_num, 256, &priv->base_tx_qpn); |
87a5c389 YP |
1830 | if (err) { |
1831 | en_err(priv, "failed reserving range for TX rings\n"); | |
1832 | return err; | |
1833 | } | |
c27a02cd YP |
1834 | |
1835 | /* Create tx Rings */ | |
1836 | for (i = 0; i < priv->tx_ring_num; i++) { | |
1837 | if (mlx4_en_create_cq(priv, &priv->tx_cq[i], | |
1838 | prof->tx_ring_size, i, TX)) | |
1839 | goto err; | |
1840 | ||
044ca2a5 | 1841 | if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i], priv->base_tx_qpn + i, |
c27a02cd YP |
1842 | prof->tx_ring_size, TXBB_SIZE)) |
1843 | goto err; | |
1844 | } | |
1845 | ||
1846 | /* Create rx Rings */ | |
1847 | for (i = 0; i < priv->rx_ring_num; i++) { | |
1848 | if (mlx4_en_create_cq(priv, &priv->rx_cq[i], | |
1849 | prof->rx_ring_size, i, RX)) | |
1850 | goto err; | |
1851 | ||
1852 | if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i], | |
1853 | prof->rx_ring_size, priv->stride)) | |
1854 | goto err; | |
1855 | } | |
1856 | ||
1eb8c695 | 1857 | #ifdef CONFIG_RFS_ACCEL |
a229e488 AV |
1858 | if (priv->mdev->dev->caps.comp_pool) { |
1859 | priv->dev->rx_cpu_rmap = alloc_irq_cpu_rmap(priv->mdev->dev->caps.comp_pool); | |
1860 | if (!priv->dev->rx_cpu_rmap) | |
1861 | goto err; | |
1862 | } | |
1eb8c695 AV |
1863 | #endif |
1864 | ||
c27a02cd YP |
1865 | return 0; |
1866 | ||
1867 | err: | |
453a6082 | 1868 | en_err(priv, "Failed to allocate NIC resources\n"); |
c27a02cd YP |
1869 | return -ENOMEM; |
1870 | } | |
1871 | ||
1872 | ||
1873 | void mlx4_en_destroy_netdev(struct net_device *dev) | |
1874 | { | |
1875 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1876 | struct mlx4_en_dev *mdev = priv->mdev; | |
1877 | ||
453a6082 | 1878 | en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port); |
c27a02cd YP |
1879 | |
1880 | /* Unregister device - this will close the port if it was up */ | |
1881 | if (priv->registered) | |
1882 | unregister_netdev(dev); | |
1883 | ||
1884 | if (priv->allocated) | |
1885 | mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE); | |
1886 | ||
1887 | cancel_delayed_work(&priv->stats_task); | |
b6c39bfc | 1888 | cancel_delayed_work(&priv->service_task); |
c27a02cd YP |
1889 | /* flush any pending task for this netdev */ |
1890 | flush_workqueue(mdev->workqueue); | |
1891 | ||
1892 | /* Detach the netdev so tasks would not attempt to access it */ | |
1893 | mutex_lock(&mdev->state_lock); | |
1894 | mdev->pndev[priv->port] = NULL; | |
1895 | mutex_unlock(&mdev->state_lock); | |
1896 | ||
fe0af03c | 1897 | mlx4_en_free_resources(priv); |
564c274c | 1898 | |
bc6a4744 AV |
1899 | kfree(priv->tx_ring); |
1900 | kfree(priv->tx_cq); | |
1901 | ||
c27a02cd YP |
1902 | free_netdev(dev); |
1903 | } | |
1904 | ||
1905 | static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu) | |
1906 | { | |
1907 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1908 | struct mlx4_en_dev *mdev = priv->mdev; | |
1909 | int err = 0; | |
1910 | ||
453a6082 | 1911 | en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n", |
c27a02cd YP |
1912 | dev->mtu, new_mtu); |
1913 | ||
1914 | if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) { | |
453a6082 | 1915 | en_err(priv, "Bad MTU size:%d.\n", new_mtu); |
c27a02cd YP |
1916 | return -EPERM; |
1917 | } | |
1918 | dev->mtu = new_mtu; | |
1919 | ||
1920 | if (netif_running(dev)) { | |
1921 | mutex_lock(&mdev->state_lock); | |
1922 | if (!mdev->device_up) { | |
1923 | /* NIC is probably restarting - let watchdog task reset | |
1924 | * the port */ | |
453a6082 | 1925 | en_dbg(DRV, priv, "Change MTU called with card down!?\n"); |
c27a02cd | 1926 | } else { |
3484aac1 | 1927 | mlx4_en_stop_port(dev, 1); |
c27a02cd YP |
1928 | err = mlx4_en_start_port(dev); |
1929 | if (err) { | |
453a6082 | 1930 | en_err(priv, "Failed restarting port:%d\n", |
c27a02cd YP |
1931 | priv->port); |
1932 | queue_work(mdev->workqueue, &priv->watchdog_task); | |
1933 | } | |
1934 | } | |
1935 | mutex_unlock(&mdev->state_lock); | |
1936 | } | |
1937 | return 0; | |
1938 | } | |
1939 | ||
ec693d47 AV |
1940 | static int mlx4_en_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) |
1941 | { | |
1942 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
1943 | struct mlx4_en_dev *mdev = priv->mdev; | |
1944 | struct hwtstamp_config config; | |
1945 | ||
1946 | if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) | |
1947 | return -EFAULT; | |
1948 | ||
1949 | /* reserved for future extensions */ | |
1950 | if (config.flags) | |
1951 | return -EINVAL; | |
1952 | ||
1953 | /* device doesn't support time stamping */ | |
1954 | if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)) | |
1955 | return -EINVAL; | |
1956 | ||
1957 | /* TX HW timestamp */ | |
1958 | switch (config.tx_type) { | |
1959 | case HWTSTAMP_TX_OFF: | |
1960 | case HWTSTAMP_TX_ON: | |
1961 | break; | |
1962 | default: | |
1963 | return -ERANGE; | |
1964 | } | |
1965 | ||
1966 | /* RX HW timestamp */ | |
1967 | switch (config.rx_filter) { | |
1968 | case HWTSTAMP_FILTER_NONE: | |
1969 | break; | |
1970 | case HWTSTAMP_FILTER_ALL: | |
1971 | case HWTSTAMP_FILTER_SOME: | |
1972 | case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: | |
1973 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | |
1974 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | |
1975 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | |
1976 | case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: | |
1977 | case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: | |
1978 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: | |
1979 | case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: | |
1980 | case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: | |
1981 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | |
1982 | case HWTSTAMP_FILTER_PTP_V2_SYNC: | |
1983 | case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: | |
1984 | config.rx_filter = HWTSTAMP_FILTER_ALL; | |
1985 | break; | |
1986 | default: | |
1987 | return -ERANGE; | |
1988 | } | |
1989 | ||
1990 | if (mlx4_en_timestamp_config(dev, config.tx_type, config.rx_filter)) { | |
1991 | config.tx_type = HWTSTAMP_TX_OFF; | |
1992 | config.rx_filter = HWTSTAMP_FILTER_NONE; | |
1993 | } | |
1994 | ||
1995 | return copy_to_user(ifr->ifr_data, &config, | |
1996 | sizeof(config)) ? -EFAULT : 0; | |
1997 | } | |
1998 | ||
1999 | static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2000 | { | |
2001 | switch (cmd) { | |
2002 | case SIOCSHWTSTAMP: | |
2003 | return mlx4_en_hwtstamp_ioctl(dev, ifr); | |
2004 | default: | |
2005 | return -EOPNOTSUPP; | |
2006 | } | |
2007 | } | |
2008 | ||
60d6fe99 AV |
2009 | static int mlx4_en_set_features(struct net_device *netdev, |
2010 | netdev_features_t features) | |
2011 | { | |
2012 | struct mlx4_en_priv *priv = netdev_priv(netdev); | |
2013 | ||
2014 | if (features & NETIF_F_LOOPBACK) | |
2015 | priv->ctrl_flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK); | |
2016 | else | |
2017 | priv->ctrl_flags &= | |
2018 | cpu_to_be32(~MLX4_WQE_CTRL_FORCE_LOOPBACK); | |
2019 | ||
79aeaccd YB |
2020 | mlx4_en_update_loopback_state(netdev, features); |
2021 | ||
60d6fe99 AV |
2022 | return 0; |
2023 | ||
2024 | } | |
2025 | ||
3addc568 SH |
2026 | static const struct net_device_ops mlx4_netdev_ops = { |
2027 | .ndo_open = mlx4_en_open, | |
2028 | .ndo_stop = mlx4_en_close, | |
2029 | .ndo_start_xmit = mlx4_en_xmit, | |
f813cad8 | 2030 | .ndo_select_queue = mlx4_en_select_queue, |
3addc568 | 2031 | .ndo_get_stats = mlx4_en_get_stats, |
0eb74fdd | 2032 | .ndo_set_rx_mode = mlx4_en_set_rx_mode, |
3addc568 | 2033 | .ndo_set_mac_address = mlx4_en_set_mac, |
52255bbe | 2034 | .ndo_validate_addr = eth_validate_addr, |
3addc568 | 2035 | .ndo_change_mtu = mlx4_en_change_mtu, |
ec693d47 | 2036 | .ndo_do_ioctl = mlx4_en_ioctl, |
3addc568 | 2037 | .ndo_tx_timeout = mlx4_en_tx_timeout, |
3addc568 SH |
2038 | .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid, |
2039 | .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid, | |
2040 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2041 | .ndo_poll_controller = mlx4_en_netpoll, | |
2042 | #endif | |
60d6fe99 | 2043 | .ndo_set_features = mlx4_en_set_features, |
897d7846 | 2044 | .ndo_setup_tc = mlx4_en_setup_tc, |
1eb8c695 AV |
2045 | #ifdef CONFIG_RFS_ACCEL |
2046 | .ndo_rx_flow_steer = mlx4_en_filter_rfs, | |
2047 | #endif | |
3addc568 SH |
2048 | }; |
2049 | ||
c27a02cd YP |
2050 | int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port, |
2051 | struct mlx4_en_port_profile *prof) | |
2052 | { | |
2053 | struct net_device *dev; | |
2054 | struct mlx4_en_priv *priv; | |
c07cb4b0 | 2055 | int i; |
c27a02cd YP |
2056 | int err; |
2057 | ||
f1593d22 | 2058 | dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv), |
d317966b | 2059 | MAX_TX_RINGS, MAX_RX_RINGS); |
41de8d4c | 2060 | if (dev == NULL) |
c27a02cd | 2061 | return -ENOMEM; |
c27a02cd | 2062 | |
d317966b AV |
2063 | netif_set_real_num_tx_queues(dev, prof->tx_ring_num); |
2064 | netif_set_real_num_rx_queues(dev, prof->rx_ring_num); | |
2065 | ||
c27a02cd | 2066 | SET_NETDEV_DEV(dev, &mdev->dev->pdev->dev); |
741a00be | 2067 | dev->dev_id = port - 1; |
c27a02cd YP |
2068 | |
2069 | /* | |
2070 | * Initialize driver private data | |
2071 | */ | |
2072 | ||
2073 | priv = netdev_priv(dev); | |
2074 | memset(priv, 0, sizeof(struct mlx4_en_priv)); | |
2075 | priv->dev = dev; | |
2076 | priv->mdev = mdev; | |
ebf8c9aa | 2077 | priv->ddev = &mdev->pdev->dev; |
c27a02cd YP |
2078 | priv->prof = prof; |
2079 | priv->port = port; | |
2080 | priv->port_up = false; | |
c27a02cd | 2081 | priv->flags = prof->flags; |
60d6fe99 AV |
2082 | priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE | |
2083 | MLX4_WQE_CTRL_SOLICITED); | |
d317966b | 2084 | priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up; |
c27a02cd | 2085 | priv->tx_ring_num = prof->tx_ring_num; |
d317966b AV |
2086 | |
2087 | priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring) * MAX_TX_RINGS, | |
2088 | GFP_KERNEL); | |
bc6a4744 AV |
2089 | if (!priv->tx_ring) { |
2090 | err = -ENOMEM; | |
2091 | goto out; | |
2092 | } | |
427a9625 | 2093 | priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq) * MAX_TX_RINGS, |
d317966b | 2094 | GFP_KERNEL); |
bc6a4744 AV |
2095 | if (!priv->tx_cq) { |
2096 | err = -ENOMEM; | |
2097 | goto out; | |
2098 | } | |
c27a02cd | 2099 | priv->rx_ring_num = prof->rx_ring_num; |
08ff3235 | 2100 | priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0; |
c27a02cd YP |
2101 | priv->mac_index = -1; |
2102 | priv->msg_enable = MLX4_EN_MSG_LEVEL; | |
2103 | spin_lock_init(&priv->stats_lock); | |
0eb74fdd | 2104 | INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode); |
c27a02cd YP |
2105 | INIT_WORK(&priv->watchdog_task, mlx4_en_restart); |
2106 | INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate); | |
2107 | INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats); | |
b6c39bfc | 2108 | INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task); |
564c274c | 2109 | #ifdef CONFIG_MLX4_EN_DCB |
540b3a39 OG |
2110 | if (!mlx4_is_slave(priv->mdev->dev)) { |
2111 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) { | |
2112 | dev->dcbnl_ops = &mlx4_en_dcbnl_ops; | |
2113 | } else { | |
2114 | en_info(priv, "enabling only PFC DCB ops\n"); | |
2115 | dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops; | |
2116 | } | |
2117 | } | |
564c274c | 2118 | #endif |
c27a02cd | 2119 | |
c07cb4b0 YB |
2120 | for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) |
2121 | INIT_HLIST_HEAD(&priv->mac_hash[i]); | |
16a10ffd | 2122 | |
c27a02cd YP |
2123 | /* Query for default mac and max mtu */ |
2124 | priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port]; | |
6bbb6d99 YB |
2125 | |
2126 | /* Set default MAC */ | |
2127 | dev->addr_len = ETH_ALEN; | |
2128 | mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]); | |
2129 | if (!is_valid_ether_addr(dev->dev_addr)) { | |
2130 | en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n", | |
2131 | priv->port, dev->dev_addr); | |
c27a02cd YP |
2132 | err = -EINVAL; |
2133 | goto out; | |
2134 | } | |
2135 | ||
6bbb6d99 YB |
2136 | memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac)); |
2137 | ||
c27a02cd YP |
2138 | priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + |
2139 | DS_SIZE * MLX4_EN_MAX_RX_FRAGS); | |
2140 | err = mlx4_en_alloc_resources(priv); | |
2141 | if (err) | |
2142 | goto out; | |
2143 | ||
78fb2de7 AV |
2144 | #ifdef CONFIG_RFS_ACCEL |
2145 | INIT_LIST_HEAD(&priv->filters); | |
2146 | spin_lock_init(&priv->filters_lock); | |
2147 | #endif | |
2148 | ||
ec693d47 AV |
2149 | /* Initialize time stamping config */ |
2150 | priv->hwtstamp_config.flags = 0; | |
2151 | priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF; | |
2152 | priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE; | |
2153 | ||
c27a02cd YP |
2154 | /* Allocate page for receive rings */ |
2155 | err = mlx4_alloc_hwq_res(mdev->dev, &priv->res, | |
2156 | MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE); | |
2157 | if (err) { | |
453a6082 | 2158 | en_err(priv, "Failed to allocate page for rx qps\n"); |
c27a02cd YP |
2159 | goto out; |
2160 | } | |
2161 | priv->allocated = 1; | |
2162 | ||
c27a02cd YP |
2163 | /* |
2164 | * Initialize netdev entry points | |
2165 | */ | |
3addc568 | 2166 | dev->netdev_ops = &mlx4_netdev_ops; |
c27a02cd | 2167 | dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT; |
1eb63a28 BH |
2168 | netif_set_real_num_tx_queues(dev, priv->tx_ring_num); |
2169 | netif_set_real_num_rx_queues(dev, priv->rx_ring_num); | |
3addc568 | 2170 | |
c27a02cd YP |
2171 | SET_ETHTOOL_OPS(dev, &mlx4_en_ethtool_ops); |
2172 | ||
c27a02cd YP |
2173 | /* |
2174 | * Set driver features | |
2175 | */ | |
c8c64cff MM |
2176 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; |
2177 | if (mdev->LSO_support) | |
2178 | dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; | |
2179 | ||
2180 | dev->vlan_features = dev->hw_features; | |
2181 | ||
ad86107f | 2182 | dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH; |
c8c64cff | 2183 | dev->features = dev->hw_features | NETIF_F_HIGHDMA | |
f646968f PM |
2184 | NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX | |
2185 | NETIF_F_HW_VLAN_CTAG_FILTER; | |
60d6fe99 | 2186 | dev->hw_features |= NETIF_F_LOOPBACK; |
c27a02cd | 2187 | |
1eb8c695 AV |
2188 | if (mdev->dev->caps.steering_mode == |
2189 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
2190 | dev->hw_features |= NETIF_F_NTUPLE; | |
2191 | ||
cc5387f7 YB |
2192 | if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0) |
2193 | dev->priv_flags |= IFF_UNICAST_FLT; | |
2194 | ||
c27a02cd YP |
2195 | mdev->pndev[port] = dev; |
2196 | ||
2197 | netif_carrier_off(dev); | |
2198 | err = register_netdev(dev); | |
2199 | if (err) { | |
453a6082 | 2200 | en_err(priv, "Netdev registration failed for port %d\n", port); |
c27a02cd YP |
2201 | goto out; |
2202 | } | |
4234144f | 2203 | priv->registered = 1; |
453a6082 YP |
2204 | |
2205 | en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num); | |
2206 | en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num); | |
2207 | ||
79aeaccd YB |
2208 | mlx4_en_update_loopback_state(priv->dev, priv->dev->features); |
2209 | ||
90822265 | 2210 | /* Configure port */ |
5c8e9046 | 2211 | mlx4_en_calc_rx_buf(dev); |
90822265 | 2212 | err = mlx4_SET_PORT_general(mdev->dev, priv->port, |
5c8e9046 YP |
2213 | priv->rx_skb_size + ETH_FCS_LEN, |
2214 | prof->tx_pause, prof->tx_ppp, | |
2215 | prof->rx_pause, prof->rx_ppp); | |
90822265 YP |
2216 | if (err) { |
2217 | en_err(priv, "Failed setting port general configurations " | |
2218 | "for port %d, with error %d\n", priv->port, err); | |
2219 | goto out; | |
2220 | } | |
2221 | ||
2222 | /* Init port */ | |
2223 | en_warn(priv, "Initializing port\n"); | |
2224 | err = mlx4_INIT_PORT(mdev->dev, priv->port); | |
2225 | if (err) { | |
2226 | en_err(priv, "Failed Initializing port\n"); | |
2227 | goto out; | |
2228 | } | |
39f17b44 | 2229 | mlx4_en_set_default_moderation(priv); |
c27a02cd | 2230 | queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY); |
b6c39bfc AV |
2231 | queue_delayed_work(mdev->workqueue, &priv->service_task, |
2232 | SERVICE_TASK_DELAY); | |
c27a02cd YP |
2233 | return 0; |
2234 | ||
2235 | out: | |
2236 | mlx4_en_destroy_netdev(dev); | |
2237 | return err; | |
2238 | } | |
2239 |