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Merge branch 'ip-sysctl-namespaceify'
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_netdev.c
CommitLineData
c27a02cd
YP		 1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/etherdevice.h>
35#include <linux/tcp.h>
36#include <linux/if_vlan.h>
37#include <linux/delay.h>
5a0e3ad6 38#include <linux/slab.h>
1eb8c695
AV		 39#include <linux/hash.h>
40#include <net/ip.h>
076bb0c8 41#include <net/busy_poll.h>
1b136de1 42#include <net/vxlan.h>
c27a02cd
YP		 43
44#include <linux/mlx4/driver.h>
45#include <linux/mlx4/device.h>
46#include <linux/mlx4/cmd.h>
47#include <linux/mlx4/cq.h>
48
49#include "mlx4_en.h"
50#include "en_port.h"
51
d317966b 52int mlx4_en_setup_tc(struct net_device *dev, u8 up)
897d7846 53{
bc6a4744
AV		 54 struct mlx4_en_priv *priv = netdev_priv(dev);
55 int i;
d317966b 56 unsigned int offset = 0;
bc6a4744
AV		 57
58 if (up && up != MLX4_EN_NUM_UP)
897d7846
AV		 59 return -EINVAL;
60
bc6a4744
AV		 61 netdev_set_num_tc(dev, up);
62
63 /* Partition Tx queues evenly amongst UP's */
bc6a4744 64 for (i = 0; i < up; i++) {
d317966b
AV		 65 netdev_set_tc_queue(dev, i, priv->num_tx_rings_p_up, offset);
66 offset += priv->num_tx_rings_p_up;
bc6a4744
AV		 67 }
68
897d7846
AV		 69 return 0;
70}
71
1eb8c695
AV		 72#ifdef CONFIG_RFS_ACCEL
73
74struct mlx4_en_filter {
75 struct list_head next;
76 struct work_struct work;
77
75a353d4 78 u8 ip_proto;
1eb8c695
AV		 79 __be32 src_ip;
80 __be32 dst_ip;
81 __be16 src_port;
82 __be16 dst_port;
83
84 int rxq_index;
85 struct mlx4_en_priv *priv;
86 u32 flow_id; /* RFS infrastructure id */
87 int id; /* mlx4_en driver id */
88 u64 reg_id; /* Flow steering API id */
89 u8 activated; /* Used to prevent expiry before filter
90 * is attached
91 */
92 struct hlist_node filter_chain;
93};
94
95static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv);
96
75a353d4
EP		 97static enum mlx4_net_trans_rule_id mlx4_ip_proto_to_trans_rule_id(u8 ip_proto)
98{
99 switch (ip_proto) {
100 case IPPROTO_UDP:
101 return MLX4_NET_TRANS_RULE_ID_UDP;
102 case IPPROTO_TCP:
103 return MLX4_NET_TRANS_RULE_ID_TCP;
104 default:
c3ca5205 105 return MLX4_NET_TRANS_RULE_NUM;
75a353d4
EP		 106 }
107};
108
1eb8c695
AV		 109static void mlx4_en_filter_work(struct work_struct *work)
110{
111 struct mlx4_en_filter *filter = container_of(work,
112 struct mlx4_en_filter,
113 work);
114 struct mlx4_en_priv *priv = filter->priv;
75a353d4
EP		 115 struct mlx4_spec_list spec_tcp_udp = {
116 .id = mlx4_ip_proto_to_trans_rule_id(filter->ip_proto),
1eb8c695
AV		 117 {
118 .tcp_udp = {
119 .dst_port = filter->dst_port,
120 .dst_port_msk = (__force __be16)-1,
121 .src_port = filter->src_port,
122 .src_port_msk = (__force __be16)-1,
123 },
124 },
125 };
126 struct mlx4_spec_list spec_ip = {
127 .id = MLX4_NET_TRANS_RULE_ID_IPV4,
128 {
129 .ipv4 = {
130 .dst_ip = filter->dst_ip,
131 .dst_ip_msk = (__force __be32)-1,
132 .src_ip = filter->src_ip,
133 .src_ip_msk = (__force __be32)-1,
134 },
135 },
136 };
137 struct mlx4_spec_list spec_eth = {
138 .id = MLX4_NET_TRANS_RULE_ID_ETH,
139 };
140 struct mlx4_net_trans_rule rule = {
141 .list = LIST_HEAD_INIT(rule.list),
142 .queue_mode = MLX4_NET_TRANS_Q_LIFO,
143 .exclusive = 1,
144 .allow_loopback = 1,
f9162539 145 .promisc_mode = MLX4_FS_REGULAR,
1eb8c695
AV		 146 .port = priv->port,
147 .priority = MLX4_DOMAIN_RFS,
148 };
149 int rc;
1eb8c695
AV		 150 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
151
c3ca5205 152 if (spec_tcp_udp.id >= MLX4_NET_TRANS_RULE_NUM) {
75a353d4
EP		 153 en_warn(priv, "RFS: ignoring unsupported ip protocol (%d)\n",
154 filter->ip_proto);
155 goto ignore;
156 }
1eb8c695
AV		 157 list_add_tail(&spec_eth.list, &rule.list);
158 list_add_tail(&spec_ip.list, &rule.list);
75a353d4 159 list_add_tail(&spec_tcp_udp.list, &rule.list);
1eb8c695 160
1eb8c695 161 rule.qpn = priv->rss_map.qps[filter->rxq_index].qpn;
6bbb6d99 162 memcpy(spec_eth.eth.dst_mac, priv->dev->dev_addr, ETH_ALEN);
1eb8c695
AV		 163 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
164
165 filter->activated = 0;
166
167 if (filter->reg_id) {
168 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
169 if (rc && rc != -ENOENT)
170 en_err(priv, "Error detaching flow. rc = %d\n", rc);
171 }
172
173 rc = mlx4_flow_attach(priv->mdev->dev, &rule, &filter->reg_id);
174 if (rc)
175 en_err(priv, "Error attaching flow. err = %d\n", rc);
176
75a353d4 177ignore:
1eb8c695
AV		 178 mlx4_en_filter_rfs_expire(priv);
179
180 filter->activated = 1;
181}
182
183static inline struct hlist_head *
184filter_hash_bucket(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
185 __be16 src_port, __be16 dst_port)
186{
187 unsigned long l;
188 int bucket_idx;
189
190 l = (__force unsigned long)src_port |
191 ((__force unsigned long)dst_port << 2);
192 l ^= (__force unsigned long)(src_ip ^ dst_ip);
193
194 bucket_idx = hash_long(l, MLX4_EN_FILTER_HASH_SHIFT);
195
196 return &priv->filter_hash[bucket_idx];
197}
198
199static struct mlx4_en_filter *
200mlx4_en_filter_alloc(struct mlx4_en_priv *priv, int rxq_index, __be32 src_ip,
75a353d4
EP		 201 __be32 dst_ip, u8 ip_proto, __be16 src_port,
202 __be16 dst_port, u32 flow_id)
1eb8c695
AV		 203{
204 struct mlx4_en_filter *filter = NULL;
205
206 filter = kzalloc(sizeof(struct mlx4_en_filter), GFP_ATOMIC);
207 if (!filter)
208 return NULL;
209
210 filter->priv = priv;
211 filter->rxq_index = rxq_index;
212 INIT_WORK(&filter->work, mlx4_en_filter_work);
213
214 filter->src_ip = src_ip;
215 filter->dst_ip = dst_ip;
75a353d4 216 filter->ip_proto = ip_proto;
1eb8c695
AV		 217 filter->src_port = src_port;
218 filter->dst_port = dst_port;
219
220 filter->flow_id = flow_id;
221
ee64c0ee 222 filter->id = priv->last_filter_id++ % RPS_NO_FILTER;
1eb8c695
AV		 223
224 list_add_tail(&filter->next, &priv->filters);
225 hlist_add_head(&filter->filter_chain,
226 filter_hash_bucket(priv, src_ip, dst_ip, src_port,
227 dst_port));
228
229 return filter;
230}
231
232static void mlx4_en_filter_free(struct mlx4_en_filter *filter)
233{
234 struct mlx4_en_priv *priv = filter->priv;
235 int rc;
236
237 list_del(&filter->next);
238
239 rc = mlx4_flow_detach(priv->mdev->dev, filter->reg_id);
240 if (rc && rc != -ENOENT)
241 en_err(priv, "Error detaching flow. rc = %d\n", rc);
242
243 kfree(filter);
244}
245
246static inline struct mlx4_en_filter *
247mlx4_en_filter_find(struct mlx4_en_priv *priv, __be32 src_ip, __be32 dst_ip,
75a353d4 248 u8 ip_proto, __be16 src_port, __be16 dst_port)
1eb8c695 249{
1eb8c695
AV		 250 struct mlx4_en_filter *filter;
251 struct mlx4_en_filter *ret = NULL;
252
b67bfe0d 253 hlist_for_each_entry(filter,
1eb8c695
AV		 254 filter_hash_bucket(priv, src_ip, dst_ip,
255 src_port, dst_port),
256 filter_chain) {
257 if (filter->src_ip == src_ip &&
258 filter->dst_ip == dst_ip &&
75a353d4 259 filter->ip_proto == ip_proto &&
1eb8c695
AV		 260 filter->src_port == src_port &&
261 filter->dst_port == dst_port) {
262 ret = filter;
263 break;
264 }
265 }
266
267 return ret;
268}
269
270static int
271mlx4_en_filter_rfs(struct net_device *net_dev, const struct sk_buff *skb,
272 u16 rxq_index, u32 flow_id)
273{
274 struct mlx4_en_priv *priv = netdev_priv(net_dev);
275 struct mlx4_en_filter *filter;
276 const struct iphdr *ip;
277 const __be16 *ports;
75a353d4 278 u8 ip_proto;
1eb8c695
AV		 279 __be32 src_ip;
280 __be32 dst_ip;
281 __be16 src_port;
282 __be16 dst_port;
283 int nhoff = skb_network_offset(skb);
284 int ret = 0;
285
286 if (skb->protocol != htons(ETH_P_IP))
287 return -EPROTONOSUPPORT;
288
289 ip = (const struct iphdr *)(skb->data + nhoff);
290 if (ip_is_fragment(ip))
291 return -EPROTONOSUPPORT;
292
75a353d4
EP		 293 if ((ip->protocol != IPPROTO_TCP) && (ip->protocol != IPPROTO_UDP))
294 return -EPROTONOSUPPORT;
1eb8c695
AV		 295 ports = (const __be16 *)(skb->data + nhoff + 4 * ip->ihl);
296
75a353d4 297 ip_proto = ip->protocol;
1eb8c695
AV		 298 src_ip = ip->saddr;
299 dst_ip = ip->daddr;
300 src_port = ports[0];
301 dst_port = ports[1];
302
1eb8c695 303 spin_lock_bh(&priv->filters_lock);
75a353d4
EP		 304 filter = mlx4_en_filter_find(priv, src_ip, dst_ip, ip_proto,
305 src_port, dst_port);
1eb8c695
AV		 306 if (filter) {
307 if (filter->rxq_index == rxq_index)
308 goto out;
309
310 filter->rxq_index = rxq_index;
311 } else {
312 filter = mlx4_en_filter_alloc(priv, rxq_index,
75a353d4 313 src_ip, dst_ip, ip_proto,
1eb8c695
AV		 314 src_port, dst_port, flow_id);
315 if (!filter) {
316 ret = -ENOMEM;
317 goto err;
318 }
319 }
320
321 queue_work(priv->mdev->workqueue, &filter->work);
322
323out:
324 ret = filter->id;
325err:
326 spin_unlock_bh(&priv->filters_lock);
327
328 return ret;
329}
330
41d942d5 331void mlx4_en_cleanup_filters(struct mlx4_en_priv *priv)
1eb8c695
AV		 332{
333 struct mlx4_en_filter *filter, *tmp;
334 LIST_HEAD(del_list);
335
336 spin_lock_bh(&priv->filters_lock);
337 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
338 list_move(&filter->next, &del_list);
339 hlist_del(&filter->filter_chain);
340 }
341 spin_unlock_bh(&priv->filters_lock);
342
343 list_for_each_entry_safe(filter, tmp, &del_list, next) {
344 cancel_work_sync(&filter->work);
345 mlx4_en_filter_free(filter);
346 }
347}
348
349static void mlx4_en_filter_rfs_expire(struct mlx4_en_priv *priv)
350{
351 struct mlx4_en_filter *filter = NULL, *tmp, *last_filter = NULL;
352 LIST_HEAD(del_list);
353 int i = 0;
354
355 spin_lock_bh(&priv->filters_lock);
356 list_for_each_entry_safe(filter, tmp, &priv->filters, next) {
357 if (i > MLX4_EN_FILTER_EXPIRY_QUOTA)
358 break;
359
360 if (filter->activated &&
361 !work_pending(&filter->work) &&
362 rps_may_expire_flow(priv->dev,
363 filter->rxq_index, filter->flow_id,
364 filter->id)) {
365 list_move(&filter->next, &del_list);
366 hlist_del(&filter->filter_chain);
367 } else
368 last_filter = filter;
369
370 i++;
371 }
372
373 if (last_filter && (&last_filter->next != priv->filters.next))
374 list_move(&priv->filters, &last_filter->next);
375
376 spin_unlock_bh(&priv->filters_lock);
377
378 list_for_each_entry_safe(filter, tmp, &del_list, next)
379 mlx4_en_filter_free(filter);
380}
381#endif
382
80d5c368
PM		 383static int mlx4_en_vlan_rx_add_vid(struct net_device *dev,
384 __be16 proto, u16 vid)
c27a02cd
YP		 385{
386 struct mlx4_en_priv *priv = netdev_priv(dev);
387 struct mlx4_en_dev *mdev = priv->mdev;
388 int err;
4c3eb3ca 389 int idx;
c27a02cd 390
f1b553fb 391 en_dbg(HW, priv, "adding VLAN:%d\n", vid);
c27a02cd 392
f1b553fb 393 set_bit(vid, priv->active_vlans);
c27a02cd
YP		 394
395 /* Add VID to port VLAN filter */
396 mutex_lock(&mdev->state_lock);
397 if (mdev->device_up && priv->port_up) {
f1b553fb 398 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 399 if (err)
453a6082 400 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd 401 }
4c3eb3ca 402 if (mlx4_register_vlan(mdev->dev, priv->port, vid, &idx))
9e19b545 403 en_dbg(HW, priv, "failed adding vlan %d\n", vid);
c27a02cd 404 mutex_unlock(&mdev->state_lock);
4c3eb3ca 405
8e586137 406 return 0;
c27a02cd
YP		 407}
408
80d5c368
PM		 409static int mlx4_en_vlan_rx_kill_vid(struct net_device *dev,
410 __be16 proto, u16 vid)
c27a02cd
YP		 411{
412 struct mlx4_en_priv *priv = netdev_priv(dev);
413 struct mlx4_en_dev *mdev = priv->mdev;
414 int err;
415
f1b553fb 416 en_dbg(HW, priv, "Killing VID:%d\n", vid);
c27a02cd 417
f1b553fb 418 clear_bit(vid, priv->active_vlans);
c27a02cd
YP		 419
420 /* Remove VID from port VLAN filter */
421 mutex_lock(&mdev->state_lock);
2009d005 422 mlx4_unregister_vlan(mdev->dev, priv->port, vid);
4c3eb3ca 423
c27a02cd 424 if (mdev->device_up && priv->port_up) {
f1b553fb 425 err = mlx4_SET_VLAN_FLTR(mdev->dev, priv);
c27a02cd 426 if (err)
453a6082 427 en_err(priv, "Failed configuring VLAN filter\n");
c27a02cd
YP		 428 }
429 mutex_unlock(&mdev->state_lock);
8e586137
JP		 430
431 return 0;
c27a02cd
YP		 432}
433
6bbb6d99
YB		 434static void mlx4_en_u64_to_mac(unsigned char dst_mac[ETH_ALEN + 2], u64 src_mac)
435{
bab6a9ea
YB		 436 int i;
437 for (i = ETH_ALEN - 1; i >= 0; --i) {
6bbb6d99
YB		 438 dst_mac[i] = src_mac & 0xff;
439 src_mac >>= 8;
440 }
441 memset(&dst_mac[ETH_ALEN], 0, 2);
442}
443
837052d0
OG		 444
445static int mlx4_en_tunnel_steer_add(struct mlx4_en_priv *priv, unsigned char *addr,
446 int qpn, u64 *reg_id)
447{
448 int err;
837052d0 449
5eff6dad
OG		 450 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
451 priv->mdev->dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
837052d0
OG		 452 return 0; /* do nothing */
453
b95089d0
OG		 454 err = mlx4_tunnel_steer_add(priv->mdev->dev, addr, priv->port, qpn,
455 MLX4_DOMAIN_NIC, reg_id);
837052d0
OG		 456 if (err) {
457 en_err(priv, "failed to add vxlan steering rule, err %d\n", err);
458 return err;
459 }
460 en_dbg(DRV, priv, "added vxlan steering rule, mac %pM reg_id %llx\n", addr, *reg_id);
461 return 0;
462}
463
464
16a10ffd
YB		 465static int mlx4_en_uc_steer_add(struct mlx4_en_priv *priv,
466 unsigned char *mac, int *qpn, u64 *reg_id)
467{
468 struct mlx4_en_dev *mdev = priv->mdev;
469 struct mlx4_dev *dev = mdev->dev;
470 int err;
471
472 switch (dev->caps.steering_mode) {
473 case MLX4_STEERING_MODE_B0: {
474 struct mlx4_qp qp;
475 u8 gid[16] = {0};
476
477 qp.qpn = *qpn;
478 memcpy(&gid[10], mac, ETH_ALEN);
479 gid[5] = priv->port;
480
481 err = mlx4_unicast_attach(dev, &qp, gid, 0, MLX4_PROT_ETH);
482 break;
483 }
484 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
485 struct mlx4_spec_list spec_eth = { {NULL} };
486 __be64 mac_mask = cpu_to_be64(MLX4_MAC_MASK << 16);
487
488 struct mlx4_net_trans_rule rule = {
489 .queue_mode = MLX4_NET_TRANS_Q_FIFO,
490 .exclusive = 0,
491 .allow_loopback = 1,
f9162539 492 .promisc_mode = MLX4_FS_REGULAR,
16a10ffd
YB		 493 .priority = MLX4_DOMAIN_NIC,
494 };
495
496 rule.port = priv->port;
497 rule.qpn = *qpn;
498 INIT_LIST_HEAD(&rule.list);
499
500 spec_eth.id = MLX4_NET_TRANS_RULE_ID_ETH;
501 memcpy(spec_eth.eth.dst_mac, mac, ETH_ALEN);
502 memcpy(spec_eth.eth.dst_mac_msk, &mac_mask, ETH_ALEN);
503 list_add_tail(&spec_eth.list, &rule.list);
504
505 err = mlx4_flow_attach(dev, &rule, reg_id);
506 break;
507 }
508 default:
509 return -EINVAL;
510 }
511 if (err)
512 en_warn(priv, "Failed Attaching Unicast\n");
513
514 return err;
515}
516
517static void mlx4_en_uc_steer_release(struct mlx4_en_priv *priv,
518 unsigned char *mac, int qpn, u64 reg_id)
519{
520 struct mlx4_en_dev *mdev = priv->mdev;
521 struct mlx4_dev *dev = mdev->dev;
522
523 switch (dev->caps.steering_mode) {
524 case MLX4_STEERING_MODE_B0: {
525 struct mlx4_qp qp;
526 u8 gid[16] = {0};
527
528 qp.qpn = qpn;
529 memcpy(&gid[10], mac, ETH_ALEN);
530 gid[5] = priv->port;
531
532 mlx4_unicast_detach(dev, &qp, gid, MLX4_PROT_ETH);
533 break;
534 }
535 case MLX4_STEERING_MODE_DEVICE_MANAGED: {
536 mlx4_flow_detach(dev, reg_id);
537 break;
538 }
539 default:
540 en_err(priv, "Invalid steering mode.\n");
541 }
542}
543
544static int mlx4_en_get_qp(struct mlx4_en_priv *priv)
545{
546 struct mlx4_en_dev *mdev = priv->mdev;
547 struct mlx4_dev *dev = mdev->dev;
16a10ffd
YB		 548 int index = 0;
549 int err = 0;
16a10ffd 550 int *qpn = &priv->base_qpn;
9813337a 551 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
16a10ffd
YB		 552
553 en_dbg(DRV, priv, "Registering MAC: %pM for adding\n",
554 priv->dev->dev_addr);
555 index = mlx4_register_mac(dev, priv->port, mac);
556 if (index < 0) {
557 err = index;
558 en_err(priv, "Failed adding MAC: %pM\n",
559 priv->dev->dev_addr);
560 return err;
561 }
562
563 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
564 int base_qpn = mlx4_get_base_qpn(dev, priv->port);
565 *qpn = base_qpn + index;
566 return 0;
567 }
568
d57febe1 569 err = mlx4_qp_reserve_range(dev, 1, 1, qpn, MLX4_RESERVE_A0_QP);
16a10ffd
YB		 570 en_dbg(DRV, priv, "Reserved qp %d\n", *qpn);
571 if (err) {
572 en_err(priv, "Failed to reserve qp for mac registration\n");
ba4b87ae
IS		 573 mlx4_unregister_mac(dev, priv->port, mac);
574 return err;
16a10ffd 575 }
16a10ffd 576
c07cb4b0 577 return 0;
16a10ffd
YB		 578}
579
580static void mlx4_en_put_qp(struct mlx4_en_priv *priv)
581{
582 struct mlx4_en_dev *mdev = priv->mdev;
583 struct mlx4_dev *dev = mdev->dev;
16a10ffd 584 int qpn = priv->base_qpn;
16a10ffd 585
83a5a6ce 586 if (dev->caps.steering_mode == MLX4_STEERING_MODE_A0) {
ba4b87ae 587 u64 mac = mlx4_mac_to_u64(priv->dev->dev_addr);
83a5a6ce
YB		 588 en_dbg(DRV, priv, "Registering MAC: %pM for deleting\n",
589 priv->dev->dev_addr);
590 mlx4_unregister_mac(dev, priv->port, mac);
591 } else {
83a5a6ce
YB		 592 en_dbg(DRV, priv, "Releasing qp: port %d, qpn %d\n",
593 priv->port, qpn);
594 mlx4_qp_release_range(dev, qpn, 1);
595 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
16a10ffd
YB		 596 }
597}
598
599static int mlx4_en_replace_mac(struct mlx4_en_priv *priv, int qpn,
90bbb74a 600 unsigned char *new_mac, unsigned char *prev_mac)
16a10ffd
YB		 601{
602 struct mlx4_en_dev *mdev = priv->mdev;
603 struct mlx4_dev *dev = mdev->dev;
16a10ffd 604 int err = 0;
9813337a 605 u64 new_mac_u64 = mlx4_mac_to_u64(new_mac);
16a10ffd
YB		 606
607 if (dev->caps.steering_mode != MLX4_STEERING_MODE_A0) {
c07cb4b0
YB		 608 struct hlist_head *bucket;
609 unsigned int mac_hash;
610 struct mlx4_mac_entry *entry;
b67bfe0d 611 struct hlist_node *tmp;
9813337a 612 u64 prev_mac_u64 = mlx4_mac_to_u64(prev_mac);
c07cb4b0
YB		 613
614 bucket = &priv->mac_hash[prev_mac[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 615 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
c07cb4b0
YB		 616 if (ether_addr_equal_64bits(entry->mac, prev_mac)) {
617 mlx4_en_uc_steer_release(priv, entry->mac,
618 qpn, entry->reg_id);
619 mlx4_unregister_mac(dev, priv->port,
620 prev_mac_u64);
621 hlist_del_rcu(&entry->hlist);
622 synchronize_rcu();
623 memcpy(entry->mac, new_mac, ETH_ALEN);
624 entry->reg_id = 0;
625 mac_hash = new_mac[MLX4_EN_MAC_HASH_IDX];
626 hlist_add_head_rcu(&entry->hlist,
627 &priv->mac_hash[mac_hash]);
628 mlx4_register_mac(dev, priv->port, new_mac_u64);
629 err = mlx4_en_uc_steer_add(priv, new_mac,
630 &qpn,
631 &entry->reg_id);
2a2083f7
OG		 632 if (err)
633 return err;
634 if (priv->tunnel_reg_id) {
635 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
636 priv->tunnel_reg_id = 0;
637 }
638 err = mlx4_en_tunnel_steer_add(priv, new_mac, qpn,
639 &priv->tunnel_reg_id);
c07cb4b0
YB		 640 return err;
641 }
642 }
643 return -EINVAL;
16a10ffd
YB		 644 }
645
646 return __mlx4_replace_mac(dev, priv->port, qpn, new_mac_u64);
647}
648
2695bab2
NO		 649static int mlx4_en_do_set_mac(struct mlx4_en_priv *priv,
650 unsigned char new_mac[ETH_ALEN + 2])
c27a02cd 651{
c27a02cd
YP		 652 int err = 0;
653
c27a02cd
YP		 654 if (priv->port_up) {
655 /* Remove old MAC and insert the new one */
16a10ffd 656 err = mlx4_en_replace_mac(priv, priv->base_qpn,
2695bab2 657 new_mac, priv->current_mac);
c27a02cd 658 if (err)
453a6082 659 en_err(priv, "Failed changing HW MAC address\n");
c27a02cd 660 } else
48e551ff 661 en_dbg(HW, priv, "Port is down while registering mac, exiting...\n");
c27a02cd 662
2695bab2
NO		 663 if (!err)
664 memcpy(priv->current_mac, new_mac, sizeof(priv->current_mac));
ee755324 665
bfa8ab47
YB		 666 return err;
667}
668
669static int mlx4_en_set_mac(struct net_device *dev, void *addr)
670{
671 struct mlx4_en_priv *priv = netdev_priv(dev);
672 struct mlx4_en_dev *mdev = priv->mdev;
673 struct sockaddr *saddr = addr;
2695bab2 674 unsigned char new_mac[ETH_ALEN + 2];
bfa8ab47
YB		 675 int err;
676
677 if (!is_valid_ether_addr(saddr->sa_data))
678 return -EADDRNOTAVAIL;
679
bfa8ab47 680 mutex_lock(&mdev->state_lock);
2695bab2
NO		 681 memcpy(new_mac, saddr->sa_data, ETH_ALEN);
682 err = mlx4_en_do_set_mac(priv, new_mac);
683 if (!err)
684 memcpy(dev->dev_addr, saddr->sa_data, ETH_ALEN);
c27a02cd 685 mutex_unlock(&mdev->state_lock);
bfa8ab47
YB		 686
687 return err;
c27a02cd
YP		 688}
689
690static void mlx4_en_clear_list(struct net_device *dev)
691{
692 struct mlx4_en_priv *priv = netdev_priv(dev);
6d199937 693 struct mlx4_en_mc_list *tmp, *mc_to_del;
c27a02cd 694
6d199937
YP		 695 list_for_each_entry_safe(mc_to_del, tmp, &priv->mc_list, list) {
696 list_del(&mc_to_del->list);
697 kfree(mc_to_del);
698 }
c27a02cd
YP		 699}
700
701static void mlx4_en_cache_mclist(struct net_device *dev)
702{
703 struct mlx4_en_priv *priv = netdev_priv(dev);
22bedad3 704 struct netdev_hw_addr *ha;
6d199937 705 struct mlx4_en_mc_list *tmp;
ff6e2163 706
0e03567a 707 mlx4_en_clear_list(dev);
6d199937
YP		 708 netdev_for_each_mc_addr(ha, dev) {
709 tmp = kzalloc(sizeof(struct mlx4_en_mc_list), GFP_ATOMIC);
710 if (!tmp) {
6d199937
YP		 711 mlx4_en_clear_list(dev);
712 return;
713 }
714 memcpy(tmp->addr, ha->addr, ETH_ALEN);
715 list_add_tail(&tmp->list, &priv->mc_list);
716 }
c27a02cd
YP		 717}
718
6d199937
YP		 719static void update_mclist_flags(struct mlx4_en_priv *priv,
720 struct list_head *dst,
721 struct list_head *src)
722{
723 struct mlx4_en_mc_list *dst_tmp, *src_tmp, *new_mc;
724 bool found;
725
726 /* Find all the entries that should be removed from dst,
727 * These are the entries that are not found in src
728 */
729 list_for_each_entry(dst_tmp, dst, list) {
730 found = false;
731 list_for_each_entry(src_tmp, src, list) {
c0623e58 732 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 733 found = true;
734 break;
735 }
736 }
737 if (!found)
738 dst_tmp->action = MCLIST_REM;
739 }
740
741 /* Add entries that exist in src but not in dst
742 * mark them as need to add
743 */
744 list_for_each_entry(src_tmp, src, list) {
745 found = false;
746 list_for_each_entry(dst_tmp, dst, list) {
c0623e58 747 if (ether_addr_equal(dst_tmp->addr, src_tmp->addr)) {
6d199937
YP		 748 dst_tmp->action = MCLIST_NONE;
749 found = true;
750 break;
751 }
752 }
753 if (!found) {
14f8dc49
JP		 754 new_mc = kmemdup(src_tmp,
755 sizeof(struct mlx4_en_mc_list),
6d199937 756 GFP_KERNEL);
14f8dc49 757 if (!new_mc)
6d199937 758 return;
14f8dc49 759
6d199937
YP		 760 new_mc->action = MCLIST_ADD;
761 list_add_tail(&new_mc->list, dst);
762 }
763 }
764}
c27a02cd 765
0eb74fdd 766static void mlx4_en_set_rx_mode(struct net_device *dev)
c27a02cd
YP		 767{
768 struct mlx4_en_priv *priv = netdev_priv(dev);
769
770 if (!priv->port_up)
771 return;
772
0eb74fdd 773 queue_work(priv->mdev->workqueue, &priv->rx_mode_task);
c27a02cd
YP		 774}
775
0eb74fdd
YB		 776static void mlx4_en_set_promisc_mode(struct mlx4_en_priv *priv,
777 struct mlx4_en_dev *mdev)
c27a02cd 778{
c96d97f4 779 int err = 0;
c27a02cd 780
0eb74fdd 781 if (!(priv->flags & MLX4_EN_FLAG_PROMISC)) {
c27a02cd 782 if (netif_msg_rx_status(priv))
0eb74fdd
YB		 783 en_warn(priv, "Entering promiscuous mode\n");
784 priv->flags |= MLX4_EN_FLAG_PROMISC;
c27a02cd 785
0eb74fdd 786 /* Enable promiscouos mode */
c96d97f4 787 switch (mdev->dev->caps.steering_mode) {
592e49dd 788 case MLX4_STEERING_MODE_DEVICE_MANAGED:
0eb74fdd
YB		 789 err = mlx4_flow_steer_promisc_add(mdev->dev,
790 priv->port,
791 priv->base_qpn,
f9162539 792 MLX4_FS_ALL_DEFAULT);
592e49dd 793 if (err)
0eb74fdd
YB		 794 en_err(priv, "Failed enabling promiscuous mode\n");
795 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
592e49dd
HHZ		 796 break;
797
c96d97f4 798 case MLX4_STEERING_MODE_B0:
0eb74fdd
YB		 799 err = mlx4_unicast_promisc_add(mdev->dev,
800 priv->base_qpn,
801 priv->port);
c96d97f4 802 if (err)
0eb74fdd
YB		 803 en_err(priv, "Failed enabling unicast promiscuous mode\n");
804
805 /* Add the default qp number as multicast
806 * promisc
807 */
808 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
809 err = mlx4_multicast_promisc_add(mdev->dev,
810 priv->base_qpn,
811 priv->port);
c96d97f4 812 if (err)
0eb74fdd
YB		 813 en_err(priv, "Failed enabling multicast promiscuous mode\n");
814 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
c96d97f4
HHZ		 815 }
816 break;
c27a02cd 817
c96d97f4
HHZ		 818 case MLX4_STEERING_MODE_A0:
819 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
820 priv->port,
0eb74fdd
YB		 821 priv->base_qpn,
822 1);
1679200f 823 if (err)
0eb74fdd 824 en_err(priv, "Failed enabling promiscuous mode\n");
c96d97f4 825 break;
1679200f
YP		 826 }
827
0eb74fdd
YB		 828 /* Disable port multicast filter (unconditionally) */
829 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
830 0, MLX4_MCAST_DISABLE);
831 if (err)
832 en_err(priv, "Failed disabling multicast filter\n");
0eb74fdd
YB		 833 }
834}
835
836static void mlx4_en_clear_promisc_mode(struct mlx4_en_priv *priv,
837 struct mlx4_en_dev *mdev)
838{
839 int err = 0;
840
841 if (netif_msg_rx_status(priv))
842 en_warn(priv, "Leaving promiscuous mode\n");
843 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
844
845 /* Disable promiscouos mode */
846 switch (mdev->dev->caps.steering_mode) {
847 case MLX4_STEERING_MODE_DEVICE_MANAGED:
848 err = mlx4_flow_steer_promisc_remove(mdev->dev,
849 priv->port,
f9162539 850 MLX4_FS_ALL_DEFAULT);
0eb74fdd
YB		 851 if (err)
852 en_err(priv, "Failed disabling promiscuous mode\n");
853 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
854 break;
855
856 case MLX4_STEERING_MODE_B0:
857 err = mlx4_unicast_promisc_remove(mdev->dev,
858 priv->base_qpn,
859 priv->port);
860 if (err)
861 en_err(priv, "Failed disabling unicast promiscuous mode\n");
862 /* Disable Multicast promisc */
863 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
864 err = mlx4_multicast_promisc_remove(mdev->dev,
865 priv->base_qpn,
866 priv->port);
867 if (err)
868 en_err(priv, "Failed disabling multicast promiscuous mode\n");
869 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
870 }
871 break;
872
873 case MLX4_STEERING_MODE_A0:
874 err = mlx4_SET_PORT_qpn_calc(mdev->dev,
875 priv->port,
876 priv->base_qpn, 0);
877 if (err)
878 en_err(priv, "Failed disabling promiscuous mode\n");
879 break;
c27a02cd 880 }
0eb74fdd
YB		 881}
882
883static void mlx4_en_do_multicast(struct mlx4_en_priv *priv,
884 struct net_device *dev,
885 struct mlx4_en_dev *mdev)
886{
887 struct mlx4_en_mc_list *mclist, *tmp;
888 u64 mcast_addr = 0;
889 u8 mc_list[16] = {0};
890 int err = 0;
891
c27a02cd
YP		 892 /* Enable/disable the multicast filter according to IFF_ALLMULTI */
893 if (dev->flags & IFF_ALLMULTI) {
894 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
895 0, MLX4_MCAST_DISABLE);
896 if (err)
453a6082 897 en_err(priv, "Failed disabling multicast filter\n");
1679200f
YP		 898
899 /* Add the default qp number as multicast promisc */
900 if (!(priv->flags & MLX4_EN_FLAG_MC_PROMISC)) {
c96d97f4 901 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 902 case MLX4_STEERING_MODE_DEVICE_MANAGED:
903 err = mlx4_flow_steer_promisc_add(mdev->dev,
904 priv->port,
905 priv->base_qpn,
f9162539 906 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 907 break;
908
c96d97f4
HHZ		 909 case MLX4_STEERING_MODE_B0:
910 err = mlx4_multicast_promisc_add(mdev->dev,
911 priv->base_qpn,
912 priv->port);
913 break;
914
915 case MLX4_STEERING_MODE_A0:
916 break;
917 }
1679200f
YP		 918 if (err)
919 en_err(priv, "Failed entering multicast promisc mode\n");
920 priv->flags |= MLX4_EN_FLAG_MC_PROMISC;
921 }
c27a02cd 922 } else {
1679200f
YP		 923 /* Disable Multicast promisc */
924 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
c96d97f4 925 switch (mdev->dev->caps.steering_mode) {
592e49dd
HHZ		 926 case MLX4_STEERING_MODE_DEVICE_MANAGED:
927 err = mlx4_flow_steer_promisc_remove(mdev->dev,
928 priv->port,
f9162539 929 MLX4_FS_MC_DEFAULT);
592e49dd
HHZ		 930 break;
931
c96d97f4
HHZ		 932 case MLX4_STEERING_MODE_B0:
933 err = mlx4_multicast_promisc_remove(mdev->dev,
934 priv->base_qpn,
935 priv->port);
936 break;
937
938 case MLX4_STEERING_MODE_A0:
939 break;
940 }
1679200f 941 if (err)
25985edc 942 en_err(priv, "Failed disabling multicast promiscuous mode\n");
1679200f
YP		 943 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
944 }
ff6e2163 945
c27a02cd
YP		 946 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
947 0, MLX4_MCAST_DISABLE);
948 if (err)
453a6082 949 en_err(priv, "Failed disabling multicast filter\n");
c27a02cd
YP		 950
951 /* Flush mcast filter and init it with broadcast address */
952 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, ETH_BCAST,
953 1, MLX4_MCAST_CONFIG);
954
955 /* Update multicast list - we cache all addresses so they won't
956 * change while HW is updated holding the command semaphor */
dbd501a8 957 netif_addr_lock_bh(dev);
c27a02cd 958 mlx4_en_cache_mclist(dev);
dbd501a8 959 netif_addr_unlock_bh(dev);
6d199937 960 list_for_each_entry(mclist, &priv->mc_list, list) {
9813337a 961 mcast_addr = mlx4_mac_to_u64(mclist->addr);
c27a02cd
YP		 962 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port,
963 mcast_addr, 0, MLX4_MCAST_CONFIG);
964 }
965 err = mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0,
966 0, MLX4_MCAST_ENABLE);
967 if (err)
453a6082 968 en_err(priv, "Failed enabling multicast filter\n");
6d199937
YP		 969
970 update_mclist_flags(priv, &priv->curr_list, &priv->mc_list);
971 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
972 if (mclist->action == MCLIST_REM) {
973 /* detach this address and delete from list */
974 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
975 mc_list[5] = priv->port;
976 err = mlx4_multicast_detach(mdev->dev,
977 &priv->rss_map.indir_qp,
978 mc_list,
0ff1fb65
HHZ		 979 MLX4_PROT_ETH,
980 mclist->reg_id);
6d199937
YP		 981 if (err)
982 en_err(priv, "Fail to detach multicast address\n");
983
837052d0
OG		 984 if (mclist->tunnel_reg_id) {
985 err = mlx4_flow_detach(priv->mdev->dev, mclist->tunnel_reg_id);
986 if (err)
987 en_err(priv, "Failed to detach multicast address\n");
988 }
989
6d199937
YP		 990 /* remove from list */
991 list_del(&mclist->list);
992 kfree(mclist);
9c64508a 993 } else if (mclist->action == MCLIST_ADD) {
6d199937
YP		 994 /* attach the address */
995 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
0ff1fb65 996 /* needed for B0 steering support */
6d199937
YP		 997 mc_list[5] = priv->port;
998 err = mlx4_multicast_attach(mdev->dev,
999 &priv->rss_map.indir_qp,
0ff1fb65
HHZ		 1000 mc_list,
1001 priv->port, 0,
1002 MLX4_PROT_ETH,
1003 &mclist->reg_id);
6d199937
YP		 1004 if (err)
1005 en_err(priv, "Fail to attach multicast address\n");
1006
837052d0
OG		 1007 err = mlx4_en_tunnel_steer_add(priv, &mc_list[10], priv->base_qpn,
1008 &mclist->tunnel_reg_id);
1009 if (err)
1010 en_err(priv, "Failed to attach multicast address\n");
6d199937
YP		 1011 }
1012 }
c27a02cd 1013 }
0eb74fdd
YB		 1014}
1015
cc5387f7
YB		 1016static void mlx4_en_do_uc_filter(struct mlx4_en_priv *priv,
1017 struct net_device *dev,
1018 struct mlx4_en_dev *mdev)
1019{
1020 struct netdev_hw_addr *ha;
1021 struct mlx4_mac_entry *entry;
b67bfe0d 1022 struct hlist_node *tmp;
cc5387f7
YB		 1023 bool found;
1024 u64 mac;
1025 int err = 0;
1026 struct hlist_head *bucket;
1027 unsigned int i;
1028 int removed = 0;
1029 u32 prev_flags;
1030
1031 /* Note that we do not need to protect our mac_hash traversal with rcu,
1032 * since all modification code is protected by mdev->state_lock
1033 */
1034
1035 /* find what to remove */
1036 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1037 bucket = &priv->mac_hash[i];
b67bfe0d 1038 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
cc5387f7
YB		 1039 found = false;
1040 netdev_for_each_uc_addr(ha, dev) {
1041 if (ether_addr_equal_64bits(entry->mac,
1042 ha->addr)) {
1043 found = true;
1044 break;
1045 }
1046 }
1047
1048 /* MAC address of the port is not in uc list */
2695bab2
NO		 1049 if (ether_addr_equal_64bits(entry->mac,
1050 priv->current_mac))
cc5387f7
YB		 1051 found = true;
1052
1053 if (!found) {
9813337a 1054 mac = mlx4_mac_to_u64(entry->mac);
cc5387f7
YB		 1055 mlx4_en_uc_steer_release(priv, entry->mac,
1056 priv->base_qpn,
1057 entry->reg_id);
1058 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1059
1060 hlist_del_rcu(&entry->hlist);
1061 kfree_rcu(entry, rcu);
1062 en_dbg(DRV, priv, "Removed MAC %pM on port:%d\n",
1063 entry->mac, priv->port);
1064 ++removed;
1065 }
1066 }
1067 }
1068
1069 /* if we didn't remove anything, there is no use in trying to add
1070 * again once we are in a forced promisc mode state
1071 */
1072 if ((priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) && 0 == removed)
1073 return;
1074
1075 prev_flags = priv->flags;
1076 priv->flags &= ~MLX4_EN_FLAG_FORCE_PROMISC;
1077
1078 /* find what to add */
1079 netdev_for_each_uc_addr(ha, dev) {
1080 found = false;
1081 bucket = &priv->mac_hash[ha->addr[MLX4_EN_MAC_HASH_IDX]];
b67bfe0d 1082 hlist_for_each_entry(entry, bucket, hlist) {
cc5387f7
YB		 1083 if (ether_addr_equal_64bits(entry->mac, ha->addr)) {
1084 found = true;
1085 break;
1086 }
1087 }
1088
1089 if (!found) {
1090 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1091 if (!entry) {
1092 en_err(priv, "Failed adding MAC %pM on port:%d (out of memory)\n",
1093 ha->addr, priv->port);
1094 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1095 break;
1096 }
9813337a 1097 mac = mlx4_mac_to_u64(ha->addr);
cc5387f7
YB		 1098 memcpy(entry->mac, ha->addr, ETH_ALEN);
1099 err = mlx4_register_mac(mdev->dev, priv->port, mac);
1100 if (err < 0) {
1101 en_err(priv, "Failed registering MAC %pM on port %d: %d\n",
1102 ha->addr, priv->port, err);
1103 kfree(entry);
1104 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1105 break;
1106 }
1107 err = mlx4_en_uc_steer_add(priv, ha->addr,
1108 &priv->base_qpn,
1109 &entry->reg_id);
1110 if (err) {
1111 en_err(priv, "Failed adding MAC %pM on port %d: %d\n",
1112 ha->addr, priv->port, err);
1113 mlx4_unregister_mac(mdev->dev, priv->port, mac);
1114 kfree(entry);
1115 priv->flags |= MLX4_EN_FLAG_FORCE_PROMISC;
1116 break;
1117 } else {
1118 unsigned int mac_hash;
1119 en_dbg(DRV, priv, "Added MAC %pM on port:%d\n",
1120 ha->addr, priv->port);
1121 mac_hash = ha->addr[MLX4_EN_MAC_HASH_IDX];
1122 bucket = &priv->mac_hash[mac_hash];
1123 hlist_add_head_rcu(&entry->hlist, bucket);
1124 }
1125 }
1126 }
1127
1128 if (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1129 en_warn(priv, "Forcing promiscuous mode on port:%d\n",
1130 priv->port);
1131 } else if (prev_flags & MLX4_EN_FLAG_FORCE_PROMISC) {
1132 en_warn(priv, "Stop forcing promiscuous mode on port:%d\n",
1133 priv->port);
1134 }
1135}
1136
0eb74fdd
YB		 1137static void mlx4_en_do_set_rx_mode(struct work_struct *work)
1138{
1139 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1140 rx_mode_task);
1141 struct mlx4_en_dev *mdev = priv->mdev;
1142 struct net_device *dev = priv->dev;
1143
1144 mutex_lock(&mdev->state_lock);
1145 if (!mdev->device_up) {
1146 en_dbg(HW, priv, "Card is not up, ignoring rx mode change.\n");
1147 goto out;
1148 }
1149 if (!priv->port_up) {
1150 en_dbg(HW, priv, "Port is down, ignoring rx mode change.\n");
1151 goto out;
1152 }
1153
1154 if (!netif_carrier_ok(dev)) {
1155 if (!mlx4_en_QUERY_PORT(mdev, priv->port)) {
1156 if (priv->port_state.link_state) {
1157 priv->last_link_state = MLX4_DEV_EVENT_PORT_UP;
1158 netif_carrier_on(dev);
1159 en_dbg(LINK, priv, "Link Up\n");
1160 }
1161 }
1162 }
1163
cc5387f7
YB		 1164 if (dev->priv_flags & IFF_UNICAST_FLT)
1165 mlx4_en_do_uc_filter(priv, dev, mdev);
1166
0eb74fdd 1167 /* Promsicuous mode: disable all filters */
cc5387f7
YB		 1168 if ((dev->flags & IFF_PROMISC) ||
1169 (priv->flags & MLX4_EN_FLAG_FORCE_PROMISC)) {
0eb74fdd
YB		 1170 mlx4_en_set_promisc_mode(priv, mdev);
1171 goto out;
1172 }
1173
1174 /* Not in promiscuous mode */
1175 if (priv->flags & MLX4_EN_FLAG_PROMISC)
1176 mlx4_en_clear_promisc_mode(priv, mdev);
1177
1178 mlx4_en_do_multicast(priv, dev, mdev);
c27a02cd
YP		 1179out:
1180 mutex_unlock(&mdev->state_lock);
1181}
1182
1183#ifdef CONFIG_NET_POLL_CONTROLLER
1184static void mlx4_en_netpoll(struct net_device *dev)
1185{
1186 struct mlx4_en_priv *priv = netdev_priv(dev);
1187 struct mlx4_en_cq *cq;
c27a02cd
YP		 1188 int i;
1189
1190 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1191 cq = priv->rx_cq[i];
c98235cb 1192 napi_schedule(&cq->napi);
c27a02cd
YP		 1193 }
1194}
1195#endif
1196
ba4b87ae
IS		 1197static int mlx4_en_set_rss_steer_rules(struct mlx4_en_priv *priv)
1198{
1199 u64 reg_id;
1200 int err = 0;
1201 int *qpn = &priv->base_qpn;
1202 struct mlx4_mac_entry *entry;
1203
1204 err = mlx4_en_uc_steer_add(priv, priv->dev->dev_addr, qpn, &reg_id);
1205 if (err)
1206 return err;
1207
1208 err = mlx4_en_tunnel_steer_add(priv, priv->dev->dev_addr, *qpn,
1209 &priv->tunnel_reg_id);
1210 if (err)
1211 goto tunnel_err;
1212
1213 entry = kmalloc(sizeof(*entry), GFP_KERNEL);
1214 if (!entry) {
1215 err = -ENOMEM;
1216 goto alloc_err;
1217 }
1218
1219 memcpy(entry->mac, priv->dev->dev_addr, sizeof(entry->mac));
1220 memcpy(priv->current_mac, entry->mac, sizeof(priv->current_mac));
1221 entry->reg_id = reg_id;
1222 hlist_add_head_rcu(&entry->hlist,
1223 &priv->mac_hash[entry->mac[MLX4_EN_MAC_HASH_IDX]]);
1224
1225 return 0;
1226
1227alloc_err:
1228 if (priv->tunnel_reg_id)
1229 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1230
1231tunnel_err:
1232 mlx4_en_uc_steer_release(priv, priv->dev->dev_addr, *qpn, reg_id);
1233 return err;
1234}
1235
1236static void mlx4_en_delete_rss_steer_rules(struct mlx4_en_priv *priv)
1237{
1238 u64 mac;
1239 unsigned int i;
1240 int qpn = priv->base_qpn;
1241 struct hlist_head *bucket;
1242 struct hlist_node *tmp;
1243 struct mlx4_mac_entry *entry;
1244
1245 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i) {
1246 bucket = &priv->mac_hash[i];
1247 hlist_for_each_entry_safe(entry, tmp, bucket, hlist) {
1248 mac = mlx4_mac_to_u64(entry->mac);
1249 en_dbg(DRV, priv, "Registering MAC:%pM for deleting\n",
1250 entry->mac);
1251 mlx4_en_uc_steer_release(priv, entry->mac,
1252 qpn, entry->reg_id);
1253
1254 mlx4_unregister_mac(priv->mdev->dev, priv->port, mac);
1255 hlist_del_rcu(&entry->hlist);
1256 kfree_rcu(entry, rcu);
1257 }
1258 }
1259
1260 if (priv->tunnel_reg_id) {
1261 mlx4_flow_detach(priv->mdev->dev, priv->tunnel_reg_id);
1262 priv->tunnel_reg_id = 0;
1263 }
1264}
1265
c27a02cd
YP		 1266static void mlx4_en_tx_timeout(struct net_device *dev)
1267{
1268 struct mlx4_en_priv *priv = netdev_priv(dev);
1269 struct mlx4_en_dev *mdev = priv->mdev;
b944ebec 1270 int i;
c27a02cd
YP		 1271
1272 if (netif_msg_timer(priv))
453a6082 1273 en_warn(priv, "Tx timeout called on port:%d\n", priv->port);
c27a02cd 1274
b944ebec
YP		 1275 for (i = 0; i < priv->tx_ring_num; i++) {
1276 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, i)))
1277 continue;
1278 en_warn(priv, "TX timeout on queue: %d, QP: 0x%x, CQ: 0x%x, Cons: 0x%x, Prod: 0x%x\n",
41d942d5
EE		 1279 i, priv->tx_ring[i]->qpn, priv->tx_ring[i]->cqn,
1280 priv->tx_ring[i]->cons, priv->tx_ring[i]->prod);
b944ebec
YP		 1281 }
1282
1e338db5 1283 priv->port_stats.tx_timeout++;
453a6082 1284 en_dbg(DRV, priv, "Scheduling watchdog\n");
1e338db5 1285 queue_work(mdev->workqueue, &priv->watchdog_task);
c27a02cd
YP		 1286}
1287
1288
1289static struct net_device_stats *mlx4_en_get_stats(struct net_device *dev)
1290{
1291 struct mlx4_en_priv *priv = netdev_priv(dev);
1292
1293 spin_lock_bh(&priv->stats_lock);
1294 memcpy(&priv->ret_stats, &priv->stats, sizeof(priv->stats));
1295 spin_unlock_bh(&priv->stats_lock);
1296
1297 return &priv->ret_stats;
1298}
1299
1300static void mlx4_en_set_default_moderation(struct mlx4_en_priv *priv)
1301{
c27a02cd
YP		 1302 struct mlx4_en_cq *cq;
1303 int i;
1304
1305 /* If we haven't received a specific coalescing setting
98a1708d 1306 * (module param), we set the moderation parameters as follows:
c27a02cd 1307 * - moder_cnt is set to the number of mtu sized packets to
ecfd2ce1 1308 * satisfy our coalescing target.
c27a02cd
YP		 1309 * - moder_time is set to a fixed value.
1310 */
3db36fb2 1311 priv->rx_frames = MLX4_EN_RX_COAL_TARGET;
60b9f9e5 1312 priv->rx_usecs = MLX4_EN_RX_COAL_TIME;
a19a848a
YP		 1313 priv->tx_frames = MLX4_EN_TX_COAL_PKTS;
1314 priv->tx_usecs = MLX4_EN_TX_COAL_TIME;
48e551ff
YB		 1315 en_dbg(INTR, priv, "Default coalesing params for mtu:%d - rx_frames:%d rx_usecs:%d\n",
1316 priv->dev->mtu, priv->rx_frames, priv->rx_usecs);
c27a02cd
YP		 1317
1318 /* Setup cq moderation params */
1319 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1320 cq = priv->rx_cq[i];
c27a02cd
YP		 1321 cq->moder_cnt = priv->rx_frames;
1322 cq->moder_time = priv->rx_usecs;
6b4d8d9f
AG		 1323 priv->last_moder_time[i] = MLX4_EN_AUTO_CONF;
1324 priv->last_moder_packets[i] = 0;
1325 priv->last_moder_bytes[i] = 0;
c27a02cd
YP		 1326 }
1327
1328 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1329 cq = priv->tx_cq[i];
a19a848a
YP		 1330 cq->moder_cnt = priv->tx_frames;
1331 cq->moder_time = priv->tx_usecs;
c27a02cd
YP		 1332 }
1333
1334 /* Reset auto-moderation params */
1335 priv->pkt_rate_low = MLX4_EN_RX_RATE_LOW;
1336 priv->rx_usecs_low = MLX4_EN_RX_COAL_TIME_LOW;
1337 priv->pkt_rate_high = MLX4_EN_RX_RATE_HIGH;
1338 priv->rx_usecs_high = MLX4_EN_RX_COAL_TIME_HIGH;
1339 priv->sample_interval = MLX4_EN_SAMPLE_INTERVAL;
60b9f9e5 1340 priv->adaptive_rx_coal = 1;
c27a02cd 1341 priv->last_moder_jiffies = 0;
c27a02cd 1342 priv->last_moder_tx_packets = 0;
c27a02cd
YP		 1343}
1344
1345static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
1346{
1347 unsigned long period = (unsigned long) (jiffies - priv->last_moder_jiffies);
c27a02cd
YP		 1348 struct mlx4_en_cq *cq;
1349 unsigned long packets;
1350 unsigned long rate;
1351 unsigned long avg_pkt_size;
1352 unsigned long rx_packets;
1353 unsigned long rx_bytes;
c27a02cd
YP		 1354 unsigned long rx_pkt_diff;
1355 int moder_time;
6b4d8d9f 1356 int ring, err;
c27a02cd
YP		 1357
1358 if (!priv->adaptive_rx_coal || period < priv->sample_interval * HZ)
1359 return;
1360
6b4d8d9f
AG		 1361 for (ring = 0; ring < priv->rx_ring_num; ring++) {
1362 spin_lock_bh(&priv->stats_lock);
41d942d5
EE		 1363 rx_packets = priv->rx_ring[ring]->packets;
1364 rx_bytes = priv->rx_ring[ring]->bytes;
6b4d8d9f
AG		 1365 spin_unlock_bh(&priv->stats_lock);
1366
1367 rx_pkt_diff = ((unsigned long) (rx_packets -
1368 priv->last_moder_packets[ring]));
1369 packets = rx_pkt_diff;
1370 rate = packets * HZ / period;
1371 avg_pkt_size = packets ? ((unsigned long) (rx_bytes -
1372 priv->last_moder_bytes[ring])) / packets : 0;
1373
1374 /* Apply auto-moderation only when packet rate
1375 * exceeds a rate that it matters */
1376 if (rate > (MLX4_EN_RX_RATE_THRESH / priv->rx_ring_num) &&
1377 avg_pkt_size > MLX4_EN_AVG_PKT_SMALL) {
c27a02cd
YP		 1378 if (rate < priv->pkt_rate_low)
1379 moder_time = priv->rx_usecs_low;
1380 else if (rate > priv->pkt_rate_high)
1381 moder_time = priv->rx_usecs_high;
1382 else
1383 moder_time = (rate - priv->pkt_rate_low) *
1384 (priv->rx_usecs_high - priv->rx_usecs_low) /
1385 (priv->pkt_rate_high - priv->pkt_rate_low) +
1386 priv->rx_usecs_low;
6b4d8d9f
AG		 1387 } else {
1388 moder_time = priv->rx_usecs_low;
c27a02cd 1389 }
c27a02cd 1390
6b4d8d9f
AG		 1391 if (moder_time != priv->last_moder_time[ring]) {
1392 priv->last_moder_time[ring] = moder_time;
41d942d5 1393 cq = priv->rx_cq[ring];
c27a02cd 1394 cq->moder_time = moder_time;
a1c6693a 1395 cq->moder_cnt = priv->rx_frames;
c27a02cd 1396 err = mlx4_en_set_cq_moder(priv, cq);
6b4d8d9f 1397 if (err)
48e551ff
YB		 1398 en_err(priv, "Failed modifying moderation for cq:%d\n",
1399 ring);
c27a02cd 1400 }
6b4d8d9f
AG		 1401 priv->last_moder_packets[ring] = rx_packets;
1402 priv->last_moder_bytes[ring] = rx_bytes;
c27a02cd
YP		 1403 }
1404
c27a02cd
YP		 1405 priv->last_moder_jiffies = jiffies;
1406}
1407
1408static void mlx4_en_do_get_stats(struct work_struct *work)
1409{
bf6aede7 1410 struct delayed_work *delay = to_delayed_work(work);
c27a02cd
YP		 1411 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1412 stats_task);
1413 struct mlx4_en_dev *mdev = priv->mdev;
1414 int err;
1415
c27a02cd
YP		 1416 mutex_lock(&mdev->state_lock);
1417 if (mdev->device_up) {
6123db2e
JM		 1418 if (priv->port_up) {
1419 err = mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 0);
1420 if (err)
1421 en_dbg(HW, priv, "Could not update stats\n");
2d51837f 1422
c27a02cd 1423 mlx4_en_auto_moderation(priv);
6123db2e 1424 }
c27a02cd
YP		 1425
1426 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
1427 }
d7e1a487 1428 if (mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port]) {
2695bab2 1429 mlx4_en_do_set_mac(priv, priv->current_mac);
d7e1a487
YP		 1430 mdev->mac_removed[MLX4_MAX_PORTS + 1 - priv->port] = 0;
1431 }
c27a02cd
YP		 1432 mutex_unlock(&mdev->state_lock);
1433}
1434
b6c39bfc
AV		 1435/* mlx4_en_service_task - Run service task for tasks that needed to be done
1436 * periodically
1437 */
1438static void mlx4_en_service_task(struct work_struct *work)
1439{
1440 struct delayed_work *delay = to_delayed_work(work);
1441 struct mlx4_en_priv *priv = container_of(delay, struct mlx4_en_priv,
1442 service_task);
1443 struct mlx4_en_dev *mdev = priv->mdev;
1444
1445 mutex_lock(&mdev->state_lock);
1446 if (mdev->device_up) {
dc8142ea
AV		 1447 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
1448 mlx4_en_ptp_overflow_check(mdev);
b6c39bfc 1449
07841f9d 1450 mlx4_en_recover_from_oom(priv);
b6c39bfc
AV		 1451 queue_delayed_work(mdev->workqueue, &priv->service_task,
1452 SERVICE_TASK_DELAY);
1453 }
1454 mutex_unlock(&mdev->state_lock);
1455}
1456
c27a02cd
YP		 1457static void mlx4_en_linkstate(struct work_struct *work)
1458{
1459 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1460 linkstate_task);
1461 struct mlx4_en_dev *mdev = priv->mdev;
1462 int linkstate = priv->link_state;
1463
1464 mutex_lock(&mdev->state_lock);
1465 /* If observable port state changed set carrier state and
1466 * report to system log */
1467 if (priv->last_link_state != linkstate) {
1468 if (linkstate == MLX4_DEV_EVENT_PORT_DOWN) {
e5cc44b2 1469 en_info(priv, "Link Down\n");
c27a02cd
YP		 1470 netif_carrier_off(priv->dev);
1471 } else {
e5cc44b2 1472 en_info(priv, "Link Up\n");
c27a02cd
YP		 1473 netif_carrier_on(priv->dev);
1474 }
1475 }
1476 priv->last_link_state = linkstate;
1477 mutex_unlock(&mdev->state_lock);
1478}
1479
9e311e77
YA		 1480static int mlx4_en_init_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1481{
1482 struct mlx4_en_rx_ring *ring = priv->rx_ring[ring_idx];
1483 int numa_node = priv->mdev->dev->numa_node;
9e311e77
YA		 1484
1485 if (!zalloc_cpumask_var(&ring->affinity_mask, GFP_KERNEL))
1486 return -ENOMEM;
1487
f36963c9
RR		 1488 cpumask_set_cpu(cpumask_local_spread(ring_idx, numa_node),
1489 ring->affinity_mask);
1490 return 0;
9e311e77
YA		 1491}
1492
1493static void mlx4_en_free_affinity_hint(struct mlx4_en_priv *priv, int ring_idx)
1494{
1495 free_cpumask_var(priv->rx_ring[ring_idx]->affinity_mask);
1496}
c27a02cd 1497
18cc42a3 1498int mlx4_en_start_port(struct net_device *dev)
c27a02cd
YP		 1499{
1500 struct mlx4_en_priv *priv = netdev_priv(dev);
1501 struct mlx4_en_dev *mdev = priv->mdev;
1502 struct mlx4_en_cq *cq;
1503 struct mlx4_en_tx_ring *tx_ring;
c27a02cd
YP		 1504 int rx_index = 0;
1505 int tx_index = 0;
c27a02cd
YP		 1506 int err = 0;
1507 int i;
1508 int j;
1679200f 1509 u8 mc_list[16] = {0};
c27a02cd
YP		 1510
1511 if (priv->port_up) {
453a6082 1512 en_dbg(DRV, priv, "start port called while port already up\n");
c27a02cd
YP		 1513 return 0;
1514 }
1515
6d199937
YP		 1516 INIT_LIST_HEAD(&priv->mc_list);
1517 INIT_LIST_HEAD(&priv->curr_list);
0d256c0e
HHZ		 1518 INIT_LIST_HEAD(&priv->ethtool_list);
1519 memset(&priv->ethtool_rules[0], 0,
1520 sizeof(struct ethtool_flow_id) * MAX_NUM_OF_FS_RULES);
6d199937 1521
c27a02cd
YP		 1522 /* Calculate Rx buf size */
1523 dev->mtu = min(dev->mtu, priv->max_mtu);
1524 mlx4_en_calc_rx_buf(dev);
453a6082 1525 en_dbg(DRV, priv, "Rx buf size:%d\n", priv->rx_skb_size);
38aab07c 1526
c27a02cd 1527 /* Configure rx cq's and rings */
38aab07c
YP		 1528 err = mlx4_en_activate_rx_rings(priv);
1529 if (err) {
453a6082 1530 en_err(priv, "Failed to activate RX rings\n");
38aab07c
YP		 1531 return err;
1532 }
c27a02cd 1533 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1534 cq = priv->rx_cq[i];
c27a02cd 1535
9e311e77
YA		 1536 err = mlx4_en_init_affinity_hint(priv, i);
1537 if (err) {
1538 en_err(priv, "Failed preparing IRQ affinity hint\n");
1539 goto cq_err;
1540 }
1541
76532d0c 1542 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1543 if (err) {
453a6082 1544 en_err(priv, "Failed activating Rx CQ\n");
9e311e77 1545 mlx4_en_free_affinity_hint(priv, i);
a4233304 1546 goto cq_err;
c27a02cd 1547 }
c3f2511f
IS		 1548
1549 for (j = 0; j < cq->size; j++) {
1550 struct mlx4_cqe *cqe = NULL;
1551
1552 cqe = mlx4_en_get_cqe(cq->buf, j, priv->cqe_size) +
1553 priv->cqe_factor;
1554 cqe->owner_sr_opcode = MLX4_CQE_OWNER_MASK;
1555 }
1556
c27a02cd
YP		 1557 err = mlx4_en_set_cq_moder(priv, cq);
1558 if (err) {
1a91de28 1559 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd 1560 mlx4_en_deactivate_cq(priv, cq);
9e311e77 1561 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1562 goto cq_err;
1563 }
1564 mlx4_en_arm_cq(priv, cq);
41d942d5 1565 priv->rx_ring[i]->cqn = cq->mcq.cqn;
c27a02cd
YP		 1566 ++rx_index;
1567 }
1568
ffe455ad
EE		 1569 /* Set qp number */
1570 en_dbg(DRV, priv, "Getting qp number for port %d\n", priv->port);
16a10ffd 1571 err = mlx4_en_get_qp(priv);
1679200f 1572 if (err) {
ffe455ad 1573 en_err(priv, "Failed getting eth qp\n");
1679200f
YP		 1574 goto cq_err;
1575 }
1576 mdev->mac_removed[priv->port] = 0;
1577
6de5f7f6
EBE		 1578 priv->counter_index =
1579 mlx4_get_default_counter_index(mdev->dev, priv->port);
1580
c27a02cd
YP		 1581 err = mlx4_en_config_rss_steer(priv);
1582 if (err) {
453a6082 1583 en_err(priv, "Failed configuring rss steering\n");
1679200f 1584 goto mac_err;
c27a02cd
YP		 1585 }
1586
cabdc8ee
HHZ		 1587 err = mlx4_en_create_drop_qp(priv);
1588 if (err)
1589 goto rss_err;
1590
c27a02cd
YP		 1591 /* Configure tx cq's and rings */
1592 for (i = 0; i < priv->tx_ring_num; i++) {
1593 /* Configure cq */
41d942d5 1594 cq = priv->tx_cq[i];
76532d0c 1595 err = mlx4_en_activate_cq(priv, cq, i);
c27a02cd 1596 if (err) {
453a6082 1597 en_err(priv, "Failed allocating Tx CQ\n");
c27a02cd
YP		 1598 goto tx_err;
1599 }
1600 err = mlx4_en_set_cq_moder(priv, cq);
1601 if (err) {
1a91de28 1602 en_err(priv, "Failed setting cq moderation parameters\n");
c27a02cd
YP		 1603 mlx4_en_deactivate_cq(priv, cq);
1604 goto tx_err;
1605 }
453a6082 1606 en_dbg(DRV, priv, "Resetting index of collapsed CQ:%d to -1\n", i);
c27a02cd
YP		 1607 cq->buf->wqe_index = cpu_to_be16(0xffff);
1608
1609 /* Configure ring */
41d942d5 1610 tx_ring = priv->tx_ring[i];
0e98b523 1611 err = mlx4_en_activate_tx_ring(priv, tx_ring, cq->mcq.cqn,
d317966b 1612 i / priv->num_tx_rings_p_up);
c27a02cd 1613 if (err) {
453a6082 1614 en_err(priv, "Failed allocating Tx ring\n");
c27a02cd
YP		 1615 mlx4_en_deactivate_cq(priv, cq);
1616 goto tx_err;
1617 }
5b263f53 1618 tx_ring->tx_queue = netdev_get_tx_queue(dev, i);
e22979d9
YP		 1619
1620 /* Arm CQ for TX completions */
1621 mlx4_en_arm_cq(priv, cq);
1622
c27a02cd
YP		 1623 /* Set initial ownership of all Tx TXBBs to SW (1) */
1624 for (j = 0; j < tx_ring->buf_size; j += STAMP_STRIDE)
1625 *((u32 *) (tx_ring->buf + j)) = 0xffffffff;
1626 ++tx_index;
1627 }
1628
1629 /* Configure port */
1630 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
1631 priv->rx_skb_size + ETH_FCS_LEN,
d53b93f2
YP		 1632 priv->prof->tx_pause,
1633 priv->prof->tx_ppp,
1634 priv->prof->rx_pause,
1635 priv->prof->rx_ppp);
c27a02cd 1636 if (err) {
48e551ff
YB		 1637 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
1638 priv->port, err);
c27a02cd
YP		 1639 goto tx_err;
1640 }
1641 /* Set default qp number */
1642 err = mlx4_SET_PORT_qpn_calc(mdev->dev, priv->port, priv->base_qpn, 0);
1643 if (err) {
453a6082 1644 en_err(priv, "Failed setting default qp numbers\n");
c27a02cd
YP		 1645 goto tx_err;
1646 }
c27a02cd 1647
837052d0 1648 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 1649 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 1650 if (err) {
1651 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
1652 err);
1653 goto tx_err;
1654 }
1655 }
1656
c27a02cd 1657 /* Init port */
453a6082 1658 en_dbg(HW, priv, "Initializing port\n");
c27a02cd
YP		 1659 err = mlx4_INIT_PORT(mdev->dev, priv->port);
1660 if (err) {
453a6082 1661 en_err(priv, "Failed Initializing port\n");
1679200f 1662 goto tx_err;
c27a02cd
YP		 1663 }
1664
ba4b87ae
IS		 1665 /* Set Unicast and VXLAN steering rules */
1666 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0 &&
1667 mlx4_en_set_rss_steer_rules(priv))
1668 mlx4_warn(mdev, "Failed setting steering rules\n");
1669
1679200f 1670 /* Attach rx QP to bradcast address */
c7bf7169 1671 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1672 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1673 if (mlx4_multicast_attach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65
HHZ		 1674 priv->port, 0, MLX4_PROT_ETH,
1675 &priv->broadcast_id))
1679200f
YP		 1676 mlx4_warn(mdev, "Failed Attaching Broadcast\n");
1677
b5845f98
HX		 1678 /* Must redo promiscuous mode setup. */
1679 priv->flags &= ~(MLX4_EN_FLAG_PROMISC | MLX4_EN_FLAG_MC_PROMISC);
1680
c27a02cd 1681 /* Schedule multicast task to populate multicast list */
0eb74fdd 1682 queue_work(mdev->workqueue, &priv->rx_mode_task);
c27a02cd 1683
a66132f3 1684#ifdef CONFIG_MLX4_EN_VXLAN
9737c6ab 1685 if (priv->mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1 1686 vxlan_get_rx_port(dev);
a66132f3 1687#endif
c27a02cd 1688 priv->port_up = true;
a11faac7 1689 netif_tx_start_all_queues(dev);
3484aac1
AV		 1690 netif_device_attach(dev);
1691
c27a02cd
YP		 1692 return 0;
1693
c27a02cd
YP		 1694tx_err:
1695 while (tx_index--) {
41d942d5
EE		 1696 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[tx_index]);
1697 mlx4_en_deactivate_cq(priv, priv->tx_cq[tx_index]);
c27a02cd 1698 }
cabdc8ee
HHZ		 1699 mlx4_en_destroy_drop_qp(priv);
1700rss_err:
c27a02cd 1701 mlx4_en_release_rss_steer(priv);
1679200f 1702mac_err:
16a10ffd 1703 mlx4_en_put_qp(priv);
c27a02cd 1704cq_err:
9e311e77 1705 while (rx_index--) {
41d942d5 1706 mlx4_en_deactivate_cq(priv, priv->rx_cq[rx_index]);
f94813f3 1707 mlx4_en_free_affinity_hint(priv, rx_index);
9e311e77 1708 }
38aab07c 1709 for (i = 0; i < priv->rx_ring_num; i++)
41d942d5 1710 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
c27a02cd
YP		 1711
1712 return err; /* need to close devices */
1713}
1714
1715
3484aac1 1716void mlx4_en_stop_port(struct net_device *dev, int detach)
c27a02cd
YP		 1717{
1718 struct mlx4_en_priv *priv = netdev_priv(dev);
1719 struct mlx4_en_dev *mdev = priv->mdev;
6d199937 1720 struct mlx4_en_mc_list *mclist, *tmp;
0d256c0e 1721 struct ethtool_flow_id *flow, *tmp_flow;
c27a02cd 1722 int i;
1679200f 1723 u8 mc_list[16] = {0};
c27a02cd
YP		 1724
1725 if (!priv->port_up) {
453a6082 1726 en_dbg(DRV, priv, "stop port called while port already down\n");
c27a02cd
YP		 1727 return;
1728 }
c27a02cd 1729
0cc5c8bf
EE		 1730 /* close port*/
1731 mlx4_CLOSE_PORT(mdev->dev, priv->port);
1732
c27a02cd
YP		 1733 /* Synchronize with tx routine */
1734 netif_tx_lock_bh(dev);
3484aac1
AV		 1735 if (detach)
1736 netif_device_detach(dev);
3c05f5ef 1737 netif_tx_stop_all_queues(dev);
c27a02cd
YP		 1738 netif_tx_unlock_bh(dev);
1739
3484aac1
AV		 1740 netif_tx_disable(dev);
1741
7c287380 1742 /* Set port as not active */
3c05f5ef 1743 priv->port_up = false;
6de5f7f6 1744 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
c27a02cd 1745
db0e7cba
AY		 1746 /* Promsicuous mode */
1747 if (mdev->dev->caps.steering_mode ==
1748 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1749 priv->flags &= ~(MLX4_EN_FLAG_PROMISC |
1750 MLX4_EN_FLAG_MC_PROMISC);
1751 mlx4_flow_steer_promisc_remove(mdev->dev,
1752 priv->port,
f9162539 1753 MLX4_FS_ALL_DEFAULT);
db0e7cba
AY		 1754 mlx4_flow_steer_promisc_remove(mdev->dev,
1755 priv->port,
f9162539 1756 MLX4_FS_MC_DEFAULT);
db0e7cba
AY		 1757 } else if (priv->flags & MLX4_EN_FLAG_PROMISC) {
1758 priv->flags &= ~MLX4_EN_FLAG_PROMISC;
1759
1760 /* Disable promiscouos mode */
1761 mlx4_unicast_promisc_remove(mdev->dev, priv->base_qpn,
1762 priv->port);
1763
1764 /* Disable Multicast promisc */
1765 if (priv->flags & MLX4_EN_FLAG_MC_PROMISC) {
1766 mlx4_multicast_promisc_remove(mdev->dev, priv->base_qpn,
1767 priv->port);
1768 priv->flags &= ~MLX4_EN_FLAG_MC_PROMISC;
1769 }
1770 }
1771
1679200f 1772 /* Detach All multicasts */
c7bf7169 1773 eth_broadcast_addr(&mc_list[10]);
0ff1fb65 1774 mc_list[5] = priv->port; /* needed for B0 steering support */
1679200f 1775 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp, mc_list,
0ff1fb65 1776 MLX4_PROT_ETH, priv->broadcast_id);
6d199937
YP		 1777 list_for_each_entry(mclist, &priv->curr_list, list) {
1778 memcpy(&mc_list[10], mclist->addr, ETH_ALEN);
1679200f
YP		 1779 mc_list[5] = priv->port;
1780 mlx4_multicast_detach(mdev->dev, &priv->rss_map.indir_qp,
0ff1fb65 1781 mc_list, MLX4_PROT_ETH, mclist->reg_id);
de123268
OG		 1782 if (mclist->tunnel_reg_id)
1783 mlx4_flow_detach(mdev->dev, mclist->tunnel_reg_id);
1679200f
YP		 1784 }
1785 mlx4_en_clear_list(dev);
6d199937
YP		 1786 list_for_each_entry_safe(mclist, tmp, &priv->curr_list, list) {
1787 list_del(&mclist->list);
1788 kfree(mclist);
1789 }
1790
1679200f
YP		 1791 /* Flush multicast filter */
1792 mlx4_SET_MCAST_FLTR(mdev->dev, priv->port, 0, 1, MLX4_MCAST_CONFIG);
1793
6efb5fac
HHZ		 1794 /* Remove flow steering rules for the port*/
1795 if (mdev->dev->caps.steering_mode ==
1796 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1797 ASSERT_RTNL();
1798 list_for_each_entry_safe(flow, tmp_flow,
1799 &priv->ethtool_list, list) {
1800 mlx4_flow_detach(mdev->dev, flow->id);
1801 list_del(&flow->list);
1802 }
1803 }
1804
cabdc8ee
HHZ		 1805 mlx4_en_destroy_drop_qp(priv);
1806
c27a02cd
YP		 1807 /* Free TX Rings */
1808 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1809 mlx4_en_deactivate_tx_ring(priv, priv->tx_ring[i]);
1810 mlx4_en_deactivate_cq(priv, priv->tx_cq[i]);
c27a02cd
YP		 1811 }
1812 msleep(10);
1813
1814 for (i = 0; i < priv->tx_ring_num; i++)
41d942d5 1815 mlx4_en_free_tx_buf(dev, priv->tx_ring[i]);
c27a02cd 1816
ba4b87ae
IS		 1817 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
1818 mlx4_en_delete_rss_steer_rules(priv);
1819
c27a02cd
YP		 1820 /* Free RSS qps */
1821 mlx4_en_release_rss_steer(priv);
1822
ffe455ad 1823 /* Unregister Mac address for the port */
16a10ffd 1824 mlx4_en_put_qp(priv);
5930e8d0 1825 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN))
955154fa 1826 mdev->mac_removed[priv->port] = 1;
ffe455ad 1827
c27a02cd
YP		 1828 /* Free RX Rings */
1829 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1830 struct mlx4_en_cq *cq = priv->rx_cq[i];
9e77a2b8 1831
f4a36751 1832 napi_synchronize(&cq->napi);
41d942d5 1833 mlx4_en_deactivate_rx_ring(priv, priv->rx_ring[i]);
9e77a2b8 1834 mlx4_en_deactivate_cq(priv, cq);
9e311e77
YA		 1835
1836 mlx4_en_free_affinity_hint(priv, i);
c27a02cd
YP		 1837 }
1838}
1839
1840static void mlx4_en_restart(struct work_struct *work)
1841{
1842 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
1843 watchdog_task);
1844 struct mlx4_en_dev *mdev = priv->mdev;
1845 struct net_device *dev = priv->dev;
1846
453a6082 1847 en_dbg(DRV, priv, "Watchdog task called for port %d\n", priv->port);
1e338db5
YP		 1848
1849 mutex_lock(&mdev->state_lock);
1850 if (priv->port_up) {
3484aac1 1851 mlx4_en_stop_port(dev, 1);
1e338db5 1852 if (mlx4_en_start_port(dev))
453a6082 1853 en_err(priv, "Failed restarting port %d\n", priv->port);
1e338db5
YP		 1854 }
1855 mutex_unlock(&mdev->state_lock);
c27a02cd
YP		 1856}
1857
b477ba62 1858static void mlx4_en_clear_stats(struct net_device *dev)
c27a02cd
YP		 1859{
1860 struct mlx4_en_priv *priv = netdev_priv(dev);
1861 struct mlx4_en_dev *mdev = priv->mdev;
1862 int i;
c27a02cd 1863
c27a02cd 1864 if (mlx4_en_DUMP_ETH_STATS(mdev, priv->port, 1))
453a6082 1865 en_dbg(HW, priv, "Failed dumping statistics\n");
c27a02cd
YP		 1866
1867 memset(&priv->stats, 0, sizeof(priv->stats));
1868 memset(&priv->pstats, 0, sizeof(priv->pstats));
b477ba62
EE		 1869 memset(&priv->pkstats, 0, sizeof(priv->pkstats));
1870 memset(&priv->port_stats, 0, sizeof(priv->port_stats));
0b131561
MB		 1871 memset(&priv->rx_flowstats, 0, sizeof(priv->rx_flowstats));
1872 memset(&priv->tx_flowstats, 0, sizeof(priv->tx_flowstats));
1873 memset(&priv->rx_priority_flowstats, 0,
1874 sizeof(priv->rx_priority_flowstats));
1875 memset(&priv->tx_priority_flowstats, 0,
1876 sizeof(priv->tx_priority_flowstats));
b42de4d0 1877 memset(&priv->pf_stats, 0, sizeof(priv->pf_stats));
c27a02cd
YP		 1878
1879 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5
EE		 1880 priv->tx_ring[i]->bytes = 0;
1881 priv->tx_ring[i]->packets = 0;
1882 priv->tx_ring[i]->tx_csum = 0;
c27a02cd
YP		 1883 }
1884 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5
EE		 1885 priv->rx_ring[i]->bytes = 0;
1886 priv->rx_ring[i]->packets = 0;
1887 priv->rx_ring[i]->csum_ok = 0;
1888 priv->rx_ring[i]->csum_none = 0;
f8c6455b 1889 priv->rx_ring[i]->csum_complete = 0;
c27a02cd 1890 }
b477ba62
EE		 1891}
1892
1893static int mlx4_en_open(struct net_device *dev)
1894{
1895 struct mlx4_en_priv *priv = netdev_priv(dev);
1896 struct mlx4_en_dev *mdev = priv->mdev;
1897 int err = 0;
1898
1899 mutex_lock(&mdev->state_lock);
1900
1901 if (!mdev->device_up) {
1902 en_err(priv, "Cannot open - device down/disabled\n");
1903 err = -EBUSY;
1904 goto out;
1905 }
1906
1907 /* Reset HW statistics and SW counters */
1908 mlx4_en_clear_stats(dev);
c27a02cd 1909
c27a02cd
YP		 1910 err = mlx4_en_start_port(dev);
1911 if (err)
453a6082 1912 en_err(priv, "Failed starting port:%d\n", priv->port);
c27a02cd
YP		 1913
1914out:
1915 mutex_unlock(&mdev->state_lock);
1916 return err;
1917}
1918
1919
1920static int mlx4_en_close(struct net_device *dev)
1921{
1922 struct mlx4_en_priv *priv = netdev_priv(dev);
1923 struct mlx4_en_dev *mdev = priv->mdev;
1924
453a6082 1925 en_dbg(IFDOWN, priv, "Close port called\n");
c27a02cd
YP		 1926
1927 mutex_lock(&mdev->state_lock);
1928
3484aac1 1929 mlx4_en_stop_port(dev, 0);
c27a02cd
YP		 1930 netif_carrier_off(dev);
1931
1932 mutex_unlock(&mdev->state_lock);
1933 return 0;
1934}
1935
fe0af03c 1936void mlx4_en_free_resources(struct mlx4_en_priv *priv)
c27a02cd
YP		 1937{
1938 int i;
1939
1eb8c695 1940#ifdef CONFIG_RFS_ACCEL
1eb8c695
AV		 1941 priv->dev->rx_cpu_rmap = NULL;
1942#endif
1943
c27a02cd 1944 for (i = 0; i < priv->tx_ring_num; i++) {
41d942d5 1945 if (priv->tx_ring && priv->tx_ring[i])
c27a02cd 1946 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
41d942d5 1947 if (priv->tx_cq && priv->tx_cq[i])
fe0af03c 1948 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
c27a02cd
YP		 1949 }
1950
1951 for (i = 0; i < priv->rx_ring_num; i++) {
41d942d5 1952 if (priv->rx_ring[i])
68355f71
TLSC		 1953 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
1954 priv->prof->rx_ring_size, priv->stride);
41d942d5 1955 if (priv->rx_cq[i])
fe0af03c 1956 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
c27a02cd 1957 }
044ca2a5 1958
c27a02cd
YP		 1959}
1960
18cc42a3 1961int mlx4_en_alloc_resources(struct mlx4_en_priv *priv)
c27a02cd 1962{
c27a02cd
YP		 1963 struct mlx4_en_port_profile *prof = priv->prof;
1964 int i;
163561a4 1965 int node;
87a5c389 1966
c27a02cd
YP		 1967 /* Create tx Rings */
1968 for (i = 0; i < priv->tx_ring_num; i++) {
163561a4 1969 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1970 if (mlx4_en_create_cq(priv, &priv->tx_cq[i],
163561a4 1971 prof->tx_ring_size, i, TX, node))
c27a02cd
YP		 1972 goto err;
1973
d03a68f8 1974 if (mlx4_en_create_tx_ring(priv, &priv->tx_ring[i],
d03a68f8
IS		 1975 prof->tx_ring_size, TXBB_SIZE,
1976 node, i))
c27a02cd
YP		 1977 goto err;
1978 }
1979
1980 /* Create rx Rings */
1981 for (i = 0; i < priv->rx_ring_num; i++) {
163561a4 1982 node = cpu_to_node(i % num_online_cpus());
c27a02cd 1983 if (mlx4_en_create_cq(priv, &priv->rx_cq[i],
163561a4 1984 prof->rx_ring_size, i, RX, node))
c27a02cd
YP		 1985 goto err;
1986
1987 if (mlx4_en_create_rx_ring(priv, &priv->rx_ring[i],
163561a4
EE		 1988 prof->rx_ring_size, priv->stride,
1989 node))
c27a02cd
YP		 1990 goto err;
1991 }
1992
1eb8c695 1993#ifdef CONFIG_RFS_ACCEL
c66fa19c 1994 priv->dev->rx_cpu_rmap = mlx4_get_cpu_rmap(priv->mdev->dev, priv->port);
1eb8c695
AV		 1995#endif
1996
c27a02cd
YP		 1997 return 0;
1998
1999err:
453a6082 2000 en_err(priv, "Failed to allocate NIC resources\n");
41d942d5
EE		 2001 for (i = 0; i < priv->rx_ring_num; i++) {
2002 if (priv->rx_ring[i])
2003 mlx4_en_destroy_rx_ring(priv, &priv->rx_ring[i],
2004 prof->rx_ring_size,
2005 priv->stride);
2006 if (priv->rx_cq[i])
2007 mlx4_en_destroy_cq(priv, &priv->rx_cq[i]);
2008 }
2009 for (i = 0; i < priv->tx_ring_num; i++) {
2010 if (priv->tx_ring[i])
2011 mlx4_en_destroy_tx_ring(priv, &priv->tx_ring[i]);
2012 if (priv->tx_cq[i])
2013 mlx4_en_destroy_cq(priv, &priv->tx_cq[i]);
2014 }
c27a02cd
YP		 2015 return -ENOMEM;
2016}
2017
2018
2019void mlx4_en_destroy_netdev(struct net_device *dev)
2020{
2021 struct mlx4_en_priv *priv = netdev_priv(dev);
2022 struct mlx4_en_dev *mdev = priv->mdev;
2023
453a6082 2024 en_dbg(DRV, priv, "Destroying netdev on port:%d\n", priv->port);
c27a02cd
YP		 2025
2026 /* Unregister device - this will close the port if it was up */
2027 if (priv->registered)
2028 unregister_netdev(dev);
2029
2030 if (priv->allocated)
2031 mlx4_free_hwq_res(mdev->dev, &priv->res, MLX4_EN_PAGE_SIZE);
2032
2033 cancel_delayed_work(&priv->stats_task);
b6c39bfc 2034 cancel_delayed_work(&priv->service_task);
c27a02cd
YP		 2035 /* flush any pending task for this netdev */
2036 flush_workqueue(mdev->workqueue);
2037
90683061
EE		 2038 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
2039 mlx4_en_remove_timestamp(mdev);
2040
c27a02cd
YP		 2041 /* Detach the netdev so tasks would not attempt to access it */
2042 mutex_lock(&mdev->state_lock);
2043 mdev->pndev[priv->port] = NULL;
5da03547 2044 mdev->upper[priv->port] = NULL;
c27a02cd
YP		 2045 mutex_unlock(&mdev->state_lock);
2046
fe0af03c 2047 mlx4_en_free_resources(priv);
564c274c 2048
bc6a4744
AV		 2049 kfree(priv->tx_ring);
2050 kfree(priv->tx_cq);
2051
c27a02cd
YP		 2052 free_netdev(dev);
2053}
2054
2055static int mlx4_en_change_mtu(struct net_device *dev, int new_mtu)
2056{
2057 struct mlx4_en_priv *priv = netdev_priv(dev);
2058 struct mlx4_en_dev *mdev = priv->mdev;
2059 int err = 0;
2060
453a6082 2061 en_dbg(DRV, priv, "Change MTU called - current:%d new:%d\n",
c27a02cd
YP		 2062 dev->mtu, new_mtu);
2063
2064 if ((new_mtu < MLX4_EN_MIN_MTU) || (new_mtu > priv->max_mtu)) {
453a6082 2065 en_err(priv, "Bad MTU size:%d.\n", new_mtu);
c27a02cd
YP		 2066 return -EPERM;
2067 }
2068 dev->mtu = new_mtu;
2069
2070 if (netif_running(dev)) {
2071 mutex_lock(&mdev->state_lock);
2072 if (!mdev->device_up) {
2073 /* NIC is probably restarting - let watchdog task reset
2074 * the port */
453a6082 2075 en_dbg(DRV, priv, "Change MTU called with card down!?\n");
c27a02cd 2076 } else {
3484aac1 2077 mlx4_en_stop_port(dev, 1);
c27a02cd
YP		 2078 err = mlx4_en_start_port(dev);
2079 if (err) {
453a6082 2080 en_err(priv, "Failed restarting port:%d\n",
c27a02cd
YP		 2081 priv->port);
2082 queue_work(mdev->workqueue, &priv->watchdog_task);
2083 }
2084 }
2085 mutex_unlock(&mdev->state_lock);
2086 }
2087 return 0;
2088}
2089
100dbda8 2090static int mlx4_en_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
ec693d47
AV		 2091{
2092 struct mlx4_en_priv *priv = netdev_priv(dev);
2093 struct mlx4_en_dev *mdev = priv->mdev;
2094 struct hwtstamp_config config;
2095
2096 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2097 return -EFAULT;
2098
2099 /* reserved for future extensions */
2100 if (config.flags)
2101 return -EINVAL;
2102
2103 /* device doesn't support time stamping */
2104 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS))
2105 return -EINVAL;
2106
2107 /* TX HW timestamp */
2108 switch (config.tx_type) {
2109 case HWTSTAMP_TX_OFF:
2110 case HWTSTAMP_TX_ON:
2111 break;
2112 default:
2113 return -ERANGE;
2114 }
2115
2116 /* RX HW timestamp */
2117 switch (config.rx_filter) {
2118 case HWTSTAMP_FILTER_NONE:
2119 break;
2120 case HWTSTAMP_FILTER_ALL:
2121 case HWTSTAMP_FILTER_SOME:
2122 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
2123 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
2124 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
2125 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2126 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2127 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2128 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2129 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2130 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2131 case HWTSTAMP_FILTER_PTP_V2_EVENT:
2132 case HWTSTAMP_FILTER_PTP_V2_SYNC:
2133 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2134 config.rx_filter = HWTSTAMP_FILTER_ALL;
2135 break;
2136 default:
2137 return -ERANGE;
2138 }
2139
7787fa66 2140 if (mlx4_en_reset_config(dev, config, dev->features)) {
ec693d47
AV		 2141 config.tx_type = HWTSTAMP_TX_OFF;
2142 config.rx_filter = HWTSTAMP_FILTER_NONE;
2143 }
2144
2145 return copy_to_user(ifr->ifr_data, &config,
2146 sizeof(config)) ? -EFAULT : 0;
2147}
2148
100dbda8
BH		 2149static int mlx4_en_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
2150{
2151 struct mlx4_en_priv *priv = netdev_priv(dev);
2152
2153 return copy_to_user(ifr->ifr_data, &priv->hwtstamp_config,
2154 sizeof(priv->hwtstamp_config)) ? -EFAULT : 0;
2155}
2156
ec693d47
AV		 2157static int mlx4_en_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2158{
2159 switch (cmd) {
2160 case SIOCSHWTSTAMP:
100dbda8
BH		 2161 return mlx4_en_hwtstamp_set(dev, ifr);
2162 case SIOCGHWTSTAMP:
2163 return mlx4_en_hwtstamp_get(dev, ifr);
ec693d47
AV		 2164 default:
2165 return -EOPNOTSUPP;
2166 }
2167}
2168
e38af4fa
HHZ		 2169static netdev_features_t mlx4_en_fix_features(struct net_device *netdev,
2170 netdev_features_t features)
2171{
2172 struct mlx4_en_priv *en_priv = netdev_priv(netdev);
2173 struct mlx4_en_dev *mdev = en_priv->mdev;
2174
2175 /* Since there is no support for separate RX C-TAG/S-TAG vlan accel
2176 * enable/disable make sure S-TAG flag is always in same state as
2177 * C-TAG.
2178 */
2179 if (features & NETIF_F_HW_VLAN_CTAG_RX &&
2180 !(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2181 features |= NETIF_F_HW_VLAN_STAG_RX;
2182 else
2183 features &= ~NETIF_F_HW_VLAN_STAG_RX;
2184
2185 return features;
2186}
2187
60d6fe99
AV		 2188static int mlx4_en_set_features(struct net_device *netdev,
2189 netdev_features_t features)
2190{
2191 struct mlx4_en_priv *priv = netdev_priv(netdev);
f0df3503 2192 bool reset = false;
537f6f95
SM		 2193 int ret = 0;
2194
f0df3503
MM		 2195 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXFCS)) {
2196 en_info(priv, "Turn %s RX-FCS\n",
2197 (features & NETIF_F_RXFCS) ? "ON" : "OFF");
2198 reset = true;
2199 }
2200
78500b8c
MM		 2201 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_RXALL)) {
2202 u8 ignore_fcs_value = (features & NETIF_F_RXALL) ? 1 : 0;
2203
2204 en_info(priv, "Turn %s RX-ALL\n",
2205 ignore_fcs_value ? "ON" : "OFF");
2206 ret = mlx4_SET_PORT_fcs_check(priv->mdev->dev,
2207 priv->port, ignore_fcs_value);
2208 if (ret)
2209 return ret;
2210 }
2211
537f6f95
SM		 2212 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
2213 en_info(priv, "Turn %s RX vlan strip offload\n",
2214 (features & NETIF_F_HW_VLAN_CTAG_RX) ? "ON" : "OFF");
f0df3503 2215 reset = true;
537f6f95 2216 }
60d6fe99 2217
cfb53f36
IS		 2218 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_CTAG_TX))
2219 en_info(priv, "Turn %s TX vlan strip offload\n",
2220 (features & NETIF_F_HW_VLAN_CTAG_TX) ? "ON" : "OFF");
2221
e38af4fa
HHZ		 2222 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_HW_VLAN_STAG_TX))
2223 en_info(priv, "Turn %s TX S-VLAN strip offload\n",
2224 (features & NETIF_F_HW_VLAN_STAG_TX) ? "ON" : "OFF");
2225
241a08c3
IS		 2226 if (DEV_FEATURE_CHANGED(netdev, features, NETIF_F_LOOPBACK)) {
2227 en_info(priv, "Turn %s loopback\n",
2228 (features & NETIF_F_LOOPBACK) ? "ON" : "OFF");
2229 mlx4_en_update_loopback_state(netdev, features);
2230 }
79aeaccd 2231
f0df3503
MM		 2232 if (reset) {
2233 ret = mlx4_en_reset_config(netdev, priv->hwtstamp_config,
2234 features);
2235 if (ret)
2236 return ret;
2237 }
60d6fe99 2238
f0df3503 2239 return 0;
60d6fe99
AV		 2240}
2241
8f7ba3ca
RE		 2242static int mlx4_en_set_vf_mac(struct net_device *dev, int queue, u8 *mac)
2243{
2244 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2245 struct mlx4_en_dev *mdev = en_priv->mdev;
9813337a 2246 u64 mac_u64 = mlx4_mac_to_u64(mac);
8f7ba3ca
RE		 2247
2248 if (!is_valid_ether_addr(mac))
2249 return -EINVAL;
2250
2251 return mlx4_set_vf_mac(mdev->dev, en_priv->port, queue, mac_u64);
2252}
2253
3f7fb021
RE		 2254static int mlx4_en_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos)
2255{
2256 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2257 struct mlx4_en_dev *mdev = en_priv->mdev;
2258
2259 return mlx4_set_vf_vlan(mdev->dev, en_priv->port, vf, vlan, qos);
2260}
2261
cda373f4
IS		 2262static int mlx4_en_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
2263 int max_tx_rate)
2264{
2265 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2266 struct mlx4_en_dev *mdev = en_priv->mdev;
2267
2268 return mlx4_set_vf_rate(mdev->dev, en_priv->port, vf, min_tx_rate,
2269 max_tx_rate);
2270}
2271
e6b6a231
RE		 2272static int mlx4_en_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
2273{
2274 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2275 struct mlx4_en_dev *mdev = en_priv->mdev;
2276
2277 return mlx4_set_vf_spoofchk(mdev->dev, en_priv->port, vf, setting);
2278}
2279
2cccb9e4
RE		 2280static int mlx4_en_get_vf_config(struct net_device *dev, int vf, struct ifla_vf_info *ivf)
2281{
2282 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2283 struct mlx4_en_dev *mdev = en_priv->mdev;
2284
2285 return mlx4_get_vf_config(mdev->dev, en_priv->port, vf, ivf);
2286}
8f7ba3ca 2287
948e306d
RE		 2288static int mlx4_en_set_vf_link_state(struct net_device *dev, int vf, int link_state)
2289{
2290 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2291 struct mlx4_en_dev *mdev = en_priv->mdev;
2292
2293 return mlx4_set_vf_link_state(mdev->dev, en_priv->port, vf, link_state);
2294}
84c86403 2295
62a89055
EBE		 2296static int mlx4_en_get_vf_stats(struct net_device *dev, int vf,
2297 struct ifla_vf_stats *vf_stats)
2298{
2299 struct mlx4_en_priv *en_priv = netdev_priv(dev);
2300 struct mlx4_en_dev *mdev = en_priv->mdev;
2301
2302 return mlx4_get_vf_stats(mdev->dev, en_priv->port, vf, vf_stats);
2303}
2304
84c86403
HHZ		 2305#define PORT_ID_BYTE_LEN 8
2306static int mlx4_en_get_phys_port_id(struct net_device *dev,
02637fce 2307 struct netdev_phys_item_id *ppid)
84c86403
HHZ		 2308{
2309 struct mlx4_en_priv *priv = netdev_priv(dev);
2310 struct mlx4_dev *mdev = priv->mdev->dev;
2311 int i;
2312 u64 phys_port_id = mdev->caps.phys_port_id[priv->port];
2313
2314 if (!phys_port_id)
2315 return -EOPNOTSUPP;
2316
2317 ppid->id_len = sizeof(phys_port_id);
2318 for (i = PORT_ID_BYTE_LEN - 1; i >= 0; --i) {
2319 ppid->id[i] = phys_port_id & 0xff;
2320 phys_port_id >>= 8;
2321 }
2322 return 0;
2323}
2324
a66132f3 2325#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2326static void mlx4_en_add_vxlan_offloads(struct work_struct *work)
2327{
2328 int ret;
2329 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2330 vxlan_add_task);
2331
2332 ret = mlx4_config_vxlan_port(priv->mdev->dev, priv->vxlan_port);
2333 if (ret)
2334 goto out;
2335
2336 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2337 VXLAN_STEER_BY_OUTER_MAC, 1);
2338out:
f4a1edd5 2339 if (ret) {
1b136de1 2340 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
f4a1edd5
OG		 2341 return;
2342 }
2343
2344 /* set offloads */
2345 priv->dev->hw_enc_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2346 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL;
2347 priv->dev->hw_features |= NETIF_F_GSO_UDP_TUNNEL;
2348 priv->dev->features |= NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2349}
2350
2351static void mlx4_en_del_vxlan_offloads(struct work_struct *work)
2352{
2353 int ret;
2354 struct mlx4_en_priv *priv = container_of(work, struct mlx4_en_priv,
2355 vxlan_del_task);
f4a1edd5
OG		 2356 /* unset offloads */
2357 priv->dev->hw_enc_features &= ~(NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
2358 NETIF_F_TSO | NETIF_F_GSO_UDP_TUNNEL);
2359 priv->dev->hw_features &= ~NETIF_F_GSO_UDP_TUNNEL;
2360 priv->dev->features &= ~NETIF_F_GSO_UDP_TUNNEL;
1b136de1
OG		 2361
2362 ret = mlx4_SET_PORT_VXLAN(priv->mdev->dev, priv->port,
2363 VXLAN_STEER_BY_OUTER_MAC, 0);
2364 if (ret)
2365 en_err(priv, "failed setting L2 tunnel configuration ret %d\n", ret);
2366
2367 priv->vxlan_port = 0;
2368}
2369
2370static void mlx4_en_add_vxlan_port(struct net_device *dev,
2371 sa_family_t sa_family, __be16 port)
2372{
2373 struct mlx4_en_priv *priv = netdev_priv(dev);
2374 __be16 current_port;
2375
e326f2f1 2376 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
1b136de1
OG		 2377 return;
2378
2379 if (sa_family == AF_INET6)
2380 return;
2381
2382 current_port = priv->vxlan_port;
2383 if (current_port && current_port != port) {
2384 en_warn(priv, "vxlan port %d configured, can't add port %d\n",
2385 ntohs(current_port), ntohs(port));
2386 return;
2387 }
2388
2389 priv->vxlan_port = port;
2390 queue_work(priv->mdev->workqueue, &priv->vxlan_add_task);
2391}
2392
2393static void mlx4_en_del_vxlan_port(struct net_device *dev,
2394 sa_family_t sa_family, __be16 port)
2395{
2396 struct mlx4_en_priv *priv = netdev_priv(dev);
2397 __be16 current_port;
2398
2399 if (priv->mdev->dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
2400 return;
2401
2402 if (sa_family == AF_INET6)
2403 return;
2404
2405 current_port = priv->vxlan_port;
2406 if (current_port != port) {
2407 en_dbg(DRV, priv, "vxlan port %d isn't configured, ignoring\n", ntohs(port));
2408 return;
2409 }
2410
2411 queue_work(priv->mdev->workqueue, &priv->vxlan_del_task);
2412}
956bdab2 2413
5f35227e
JG		 2414static netdev_features_t mlx4_en_features_check(struct sk_buff *skb,
2415 struct net_device *dev,
2416 netdev_features_t features)
956bdab2 2417{
8cb65d00 2418 features = vlan_features_check(skb, features);
5f35227e 2419 return vxlan_features_check(skb, features);
956bdab2 2420}
a66132f3 2421#endif
1b136de1 2422
de1cf8a7 2423static int mlx4_en_set_tx_maxrate(struct net_device *dev, int queue_index, u32 maxrate)
c10e4fc6
OG		 2424{
2425 struct mlx4_en_priv *priv = netdev_priv(dev);
2426 struct mlx4_en_tx_ring *tx_ring = priv->tx_ring[queue_index];
2427 struct mlx4_update_qp_params params;
2428 int err;
2429
2430 if (!(priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT))
2431 return -EOPNOTSUPP;
2432
2433 /* rate provided to us in Mbs, check if it fits into 12 bits, if not use Gbs */
2434 if (maxrate >> 12) {
2435 params.rate_unit = MLX4_QP_RATE_LIMIT_GBS;
2436 params.rate_val = maxrate / 1000;
2437 } else if (maxrate) {
2438 params.rate_unit = MLX4_QP_RATE_LIMIT_MBS;
2439 params.rate_val = maxrate;
2440 } else { /* zero serves to revoke the QP rate-limitation */
2441 params.rate_unit = 0;
2442 params.rate_val = 0;
2443 }
2444
2445 err = mlx4_update_qp(priv->mdev->dev, tx_ring->qpn, MLX4_UPDATE_QP_RATE_LIMIT,
2446 &params);
2447 return err;
2448}
2449
3addc568
SH		 2450static const struct net_device_ops mlx4_netdev_ops = {
2451 .ndo_open = mlx4_en_open,
2452 .ndo_stop = mlx4_en_close,
2453 .ndo_start_xmit = mlx4_en_xmit,
f813cad8 2454 .ndo_select_queue = mlx4_en_select_queue,
3addc568 2455 .ndo_get_stats = mlx4_en_get_stats,
0eb74fdd 2456 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
3addc568 2457 .ndo_set_mac_address = mlx4_en_set_mac,
52255bbe 2458 .ndo_validate_addr = eth_validate_addr,
3addc568 2459 .ndo_change_mtu = mlx4_en_change_mtu,
ec693d47 2460 .ndo_do_ioctl = mlx4_en_ioctl,
3addc568 2461 .ndo_tx_timeout = mlx4_en_tx_timeout,
3addc568
SH		 2462 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2463 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2464#ifdef CONFIG_NET_POLL_CONTROLLER
2465 .ndo_poll_controller = mlx4_en_netpoll,
2466#endif
60d6fe99 2467 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2468 .ndo_fix_features = mlx4_en_fix_features,
897d7846 2469 .ndo_setup_tc = mlx4_en_setup_tc,
1eb8c695
AV		 2470#ifdef CONFIG_RFS_ACCEL
2471 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
9e77a2b8 2472#endif
84c86403 2473 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
a66132f3 2474#ifdef CONFIG_MLX4_EN_VXLAN
1b136de1
OG		 2475 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2476 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2477 .ndo_features_check = mlx4_en_features_check,
a66132f3 2478#endif
c10e4fc6 2479 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
3addc568
SH		 2480};
2481
8f7ba3ca
RE		 2482static const struct net_device_ops mlx4_netdev_ops_master = {
2483 .ndo_open = mlx4_en_open,
2484 .ndo_stop = mlx4_en_close,
2485 .ndo_start_xmit = mlx4_en_xmit,
2486 .ndo_select_queue = mlx4_en_select_queue,
2487 .ndo_get_stats = mlx4_en_get_stats,
2488 .ndo_set_rx_mode = mlx4_en_set_rx_mode,
2489 .ndo_set_mac_address = mlx4_en_set_mac,
2490 .ndo_validate_addr = eth_validate_addr,
2491 .ndo_change_mtu = mlx4_en_change_mtu,
2492 .ndo_tx_timeout = mlx4_en_tx_timeout,
2493 .ndo_vlan_rx_add_vid = mlx4_en_vlan_rx_add_vid,
2494 .ndo_vlan_rx_kill_vid = mlx4_en_vlan_rx_kill_vid,
2495 .ndo_set_vf_mac = mlx4_en_set_vf_mac,
3f7fb021 2496 .ndo_set_vf_vlan = mlx4_en_set_vf_vlan,
cda373f4 2497 .ndo_set_vf_rate = mlx4_en_set_vf_rate,
e6b6a231 2498 .ndo_set_vf_spoofchk = mlx4_en_set_vf_spoofchk,
948e306d 2499 .ndo_set_vf_link_state = mlx4_en_set_vf_link_state,
62a89055 2500 .ndo_get_vf_stats = mlx4_en_get_vf_stats,
2cccb9e4 2501 .ndo_get_vf_config = mlx4_en_get_vf_config,
8f7ba3ca
RE		 2502#ifdef CONFIG_NET_POLL_CONTROLLER
2503 .ndo_poll_controller = mlx4_en_netpoll,
2504#endif
2505 .ndo_set_features = mlx4_en_set_features,
e38af4fa 2506 .ndo_fix_features = mlx4_en_fix_features,
8f7ba3ca
RE		 2507 .ndo_setup_tc = mlx4_en_setup_tc,
2508#ifdef CONFIG_RFS_ACCEL
2509 .ndo_rx_flow_steer = mlx4_en_filter_rfs,
2510#endif
84c86403 2511 .ndo_get_phys_port_id = mlx4_en_get_phys_port_id,
9737c6ab
OG		 2512#ifdef CONFIG_MLX4_EN_VXLAN
2513 .ndo_add_vxlan_port = mlx4_en_add_vxlan_port,
2514 .ndo_del_vxlan_port = mlx4_en_del_vxlan_port,
5f35227e 2515 .ndo_features_check = mlx4_en_features_check,
9737c6ab 2516#endif
c10e4fc6 2517 .ndo_set_tx_maxrate = mlx4_en_set_tx_maxrate,
8f7ba3ca
RE		 2518};
2519
5da03547
MS		 2520struct mlx4_en_bond {
2521 struct work_struct work;
2522 struct mlx4_en_priv *priv;
2523 int is_bonded;
2524 struct mlx4_port_map port_map;
2525};
2526
2527static void mlx4_en_bond_work(struct work_struct *work)
2528{
2529 struct mlx4_en_bond *bond = container_of(work,
2530 struct mlx4_en_bond,
2531 work);
2532 int err = 0;
2533 struct mlx4_dev *dev = bond->priv->mdev->dev;
2534
2535 if (bond->is_bonded) {
2536 if (!mlx4_is_bonded(dev)) {
2537 err = mlx4_bond(dev);
2538 if (err)
2539 en_err(bond->priv, "Fail to bond device\n");
2540 }
2541 if (!err) {
2542 err = mlx4_port_map_set(dev, &bond->port_map);
2543 if (err)
2544 en_err(bond->priv, "Fail to set port map [%d][%d]: %d\n",
2545 bond->port_map.port1,
2546 bond->port_map.port2,
2547 err);
2548 }
2549 } else if (mlx4_is_bonded(dev)) {
2550 err = mlx4_unbond(dev);
2551 if (err)
2552 en_err(bond->priv, "Fail to unbond device\n");
2553 }
2554 dev_put(bond->priv->dev);
2555 kfree(bond);
2556}
2557
2558static int mlx4_en_queue_bond_work(struct mlx4_en_priv *priv, int is_bonded,
2559 u8 v2p_p1, u8 v2p_p2)
2560{
2561 struct mlx4_en_bond *bond = NULL;
2562
2563 bond = kzalloc(sizeof(*bond), GFP_ATOMIC);
2564 if (!bond)
2565 return -ENOMEM;
2566
2567 INIT_WORK(&bond->work, mlx4_en_bond_work);
2568 bond->priv = priv;
2569 bond->is_bonded = is_bonded;
2570 bond->port_map.port1 = v2p_p1;
2571 bond->port_map.port2 = v2p_p2;
2572 dev_hold(priv->dev);
2573 queue_work(priv->mdev->workqueue, &bond->work);
2574 return 0;
2575}
2576
2577int mlx4_en_netdev_event(struct notifier_block *this,
2578 unsigned long event, void *ptr)
2579{
2580 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
2581 u8 port = 0;
2582 struct mlx4_en_dev *mdev;
2583 struct mlx4_dev *dev;
2584 int i, num_eth_ports = 0;
2585 bool do_bond = true;
2586 struct mlx4_en_priv *priv;
2587 u8 v2p_port1 = 0;
2588 u8 v2p_port2 = 0;
2589
2590 if (!net_eq(dev_net(ndev), &init_net))
2591 return NOTIFY_DONE;
2592
2593 mdev = container_of(this, struct mlx4_en_dev, nb);
2594 dev = mdev->dev;
2595
2596 /* Go into this mode only when two network devices set on two ports
2597 * of the same mlx4 device are slaves of the same bonding master
2598 */
2599 mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) {
2600 ++num_eth_ports;
2601 if (!port && (mdev->pndev[i] == ndev))
2602 port = i;
2603 mdev->upper[i] = mdev->pndev[i] ?
2604 netdev_master_upper_dev_get(mdev->pndev[i]) : NULL;
2605 /* condition not met: network device is a slave */
2606 if (!mdev->upper[i])
2607 do_bond = false;
2608 if (num_eth_ports < 2)
2609 continue;
2610 /* condition not met: same master */
2611 if (mdev->upper[i] != mdev->upper[i-1])
2612 do_bond = false;
2613 }
2614 /* condition not met: 2 salves */
2615 do_bond = (num_eth_ports == 2) ? do_bond : false;
2616
2617 /* handle only events that come with enough info */
2618 if ((do_bond && (event != NETDEV_BONDING_INFO)) || !port)
2619 return NOTIFY_DONE;
2620
2621 priv = netdev_priv(ndev);
2622 if (do_bond) {
2623 struct netdev_notifier_bonding_info *notifier_info = ptr;
2624 struct netdev_bonding_info *bonding_info =
2625 &notifier_info->bonding_info;
2626
2627 /* required mode 1, 2 or 4 */
2628 if ((bonding_info->master.bond_mode != BOND_MODE_ACTIVEBACKUP) &&
2629 (bonding_info->master.bond_mode != BOND_MODE_XOR) &&
2630 (bonding_info->master.bond_mode != BOND_MODE_8023AD))
2631 do_bond = false;
2632
2633 /* require exactly 2 slaves */
2634 if (bonding_info->master.num_slaves != 2)
2635 do_bond = false;
2636
2637 /* calc v2p */
2638 if (do_bond) {
2639 if (bonding_info->master.bond_mode ==
2640 BOND_MODE_ACTIVEBACKUP) {
2641 /* in active-backup mode virtual ports are
2642 * mapped to the physical port of the active
2643 * slave */
2644 if (bonding_info->slave.state ==
2645 BOND_STATE_BACKUP) {
2646 if (port == 1) {
2647 v2p_port1 = 2;
2648 v2p_port2 = 2;
2649 } else {
2650 v2p_port1 = 1;
2651 v2p_port2 = 1;
2652 }
2653 } else { /* BOND_STATE_ACTIVE */
2654 if (port == 1) {
2655 v2p_port1 = 1;
2656 v2p_port2 = 1;
2657 } else {
2658 v2p_port1 = 2;
2659 v2p_port2 = 2;
2660 }
2661 }
2662 } else { /* Active-Active */
2663 /* in active-active mode a virtual port is
2664 * mapped to the native physical port if and only
2665 * if the physical port is up */
2666 __s8 link = bonding_info->slave.link;
2667
2668 if (port == 1)
2669 v2p_port2 = 2;
2670 else
2671 v2p_port1 = 1;
2672 if ((link == BOND_LINK_UP) ||
2673 (link == BOND_LINK_FAIL)) {
2674 if (port == 1)
2675 v2p_port1 = 1;
2676 else
2677 v2p_port2 = 2;
2678 } else { /* BOND_LINK_DOWN || BOND_LINK_BACK */
2679 if (port == 1)
2680 v2p_port1 = 2;
2681 else
2682 v2p_port2 = 1;
2683 }
2684 }
2685 }
2686 }
2687
2688 mlx4_en_queue_bond_work(priv, do_bond,
2689 v2p_port1, v2p_port2);
2690
2691 return NOTIFY_DONE;
2692}
2693
0b131561
MB		 2694void mlx4_en_update_pfc_stats_bitmap(struct mlx4_dev *dev,
2695 struct mlx4_en_stats_bitmap *stats_bitmap,
2696 u8 rx_ppp, u8 rx_pause,
2697 u8 tx_ppp, u8 tx_pause)
2698{
b42de4d0 2699 int last_i = NUM_MAIN_STATS + NUM_PORT_STATS + NUM_PF_STATS;
0b131561
MB		 2700
2701 if (!mlx4_is_slave(dev) &&
2702 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN)) {
2703 mutex_lock(&stats_bitmap->mutex);
2704 bitmap_clear(stats_bitmap->bitmap, last_i, NUM_FLOW_STATS);
2705
2706 if (rx_ppp)
2707 bitmap_set(stats_bitmap->bitmap, last_i,
2708 NUM_FLOW_PRIORITY_STATS_RX);
2709 last_i += NUM_FLOW_PRIORITY_STATS_RX;
2710
2711 if (rx_pause && !(rx_ppp))
2712 bitmap_set(stats_bitmap->bitmap, last_i,
2713 NUM_FLOW_STATS_RX);
2714 last_i += NUM_FLOW_STATS_RX;
2715
2716 if (tx_ppp)
2717 bitmap_set(stats_bitmap->bitmap, last_i,
2718 NUM_FLOW_PRIORITY_STATS_TX);
2719 last_i += NUM_FLOW_PRIORITY_STATS_TX;
2720
2721 if (tx_pause && !(tx_ppp))
2722 bitmap_set(stats_bitmap->bitmap, last_i,
2723 NUM_FLOW_STATS_TX);
2724 last_i += NUM_FLOW_STATS_TX;
2725
2726 mutex_unlock(&stats_bitmap->mutex);
2727 }
2728}
2729
6fcd2735 2730void mlx4_en_set_stats_bitmap(struct mlx4_dev *dev,
0b131561
MB		 2731 struct mlx4_en_stats_bitmap *stats_bitmap,
2732 u8 rx_ppp, u8 rx_pause,
2733 u8 tx_ppp, u8 tx_pause)
ffa88f37 2734{
6fcd2735
EBE		 2735 int last_i = 0;
2736
3da8a36c
EBE		 2737 mutex_init(&stats_bitmap->mutex);
2738 bitmap_zero(stats_bitmap->bitmap, NUM_ALL_STATS);
6fcd2735
EBE		 2739
2740 if (mlx4_is_slave(dev)) {
3da8a36c 2741 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2742 MLX4_FIND_NETDEV_STAT(rx_packets), 1);
3da8a36c 2743 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2744 MLX4_FIND_NETDEV_STAT(tx_packets), 1);
3da8a36c 2745 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2746 MLX4_FIND_NETDEV_STAT(rx_bytes), 1);
3da8a36c 2747 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2748 MLX4_FIND_NETDEV_STAT(tx_bytes), 1);
3da8a36c 2749 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735 2750 MLX4_FIND_NETDEV_STAT(rx_dropped), 1);
3da8a36c 2751 bitmap_set(stats_bitmap->bitmap, last_i +
6fcd2735
EBE		 2752 MLX4_FIND_NETDEV_STAT(tx_dropped), 1);
2753 } else {
3da8a36c 2754 bitmap_set(stats_bitmap->bitmap, last_i, NUM_MAIN_STATS);
ffa88f37 2755 }
6fcd2735 2756 last_i += NUM_MAIN_STATS;
ffa88f37 2757
3da8a36c 2758 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PORT_STATS);
6fcd2735 2759 last_i += NUM_PORT_STATS;
ffa88f37 2760
b42de4d0
EBE		 2761 if (mlx4_is_master(dev))
2762 bitmap_set(stats_bitmap->bitmap, last_i,
2763 NUM_PF_STATS);
2764 last_i += NUM_PF_STATS;
2765
0b131561
MB		 2766 mlx4_en_update_pfc_stats_bitmap(dev, stats_bitmap,
2767 rx_ppp, rx_pause,
2768 tx_ppp, tx_pause);
2769 last_i += NUM_FLOW_STATS;
2770
6fcd2735 2771 if (!mlx4_is_slave(dev))
3da8a36c 2772 bitmap_set(stats_bitmap->bitmap, last_i, NUM_PKT_STATS);
ffa88f37
EBE		 2773}
2774
c27a02cd
YP		 2775int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
2776 struct mlx4_en_port_profile *prof)
2777{
2778 struct net_device *dev;
2779 struct mlx4_en_priv *priv;
c07cb4b0 2780 int i;
c27a02cd
YP		 2781 int err;
2782
f1593d22 2783 dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
d317966b 2784 MAX_TX_RINGS, MAX_RX_RINGS);
41de8d4c 2785 if (dev == NULL)
c27a02cd 2786 return -ENOMEM;
c27a02cd 2787
d317966b
AV		 2788 netif_set_real_num_tx_queues(dev, prof->tx_ring_num);
2789 netif_set_real_num_rx_queues(dev, prof->rx_ring_num);
2790
872bf2fb 2791 SET_NETDEV_DEV(dev, &mdev->dev->persist->pdev->dev);
76a066f2 2792 dev->dev_port = port - 1;
c27a02cd
YP		 2793
2794 /*
2795 * Initialize driver private data
2796 */
2797
2798 priv = netdev_priv(dev);
2799 memset(priv, 0, sizeof(struct mlx4_en_priv));
6de5f7f6 2800 priv->counter_index = MLX4_SINK_COUNTER_INDEX(mdev->dev);
207af6c5
EE		 2801 spin_lock_init(&priv->stats_lock);
2802 INIT_WORK(&priv->rx_mode_task, mlx4_en_do_set_rx_mode);
2803 INIT_WORK(&priv->watchdog_task, mlx4_en_restart);
2804 INIT_WORK(&priv->linkstate_task, mlx4_en_linkstate);
2805 INIT_DELAYED_WORK(&priv->stats_task, mlx4_en_do_get_stats);
2806 INIT_DELAYED_WORK(&priv->service_task, mlx4_en_service_task);
2807#ifdef CONFIG_MLX4_EN_VXLAN
2808 INIT_WORK(&priv->vxlan_add_task, mlx4_en_add_vxlan_offloads);
2809 INIT_WORK(&priv->vxlan_del_task, mlx4_en_del_vxlan_offloads);
2810#endif
2811#ifdef CONFIG_RFS_ACCEL
2812 INIT_LIST_HEAD(&priv->filters);
2813 spin_lock_init(&priv->filters_lock);
2814#endif
2815
c27a02cd
YP		 2816 priv->dev = dev;
2817 priv->mdev = mdev;
ebf8c9aa 2818 priv->ddev = &mdev->pdev->dev;
c27a02cd
YP		 2819 priv->prof = prof;
2820 priv->port = port;
2821 priv->port_up = false;
c27a02cd 2822 priv->flags = prof->flags;
0fef9d03 2823 priv->pflags = MLX4_EN_PRIV_FLAGS_BLUEFLAME;
60d6fe99
AV		 2824 priv->ctrl_flags = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE |
2825 MLX4_WQE_CTRL_SOLICITED);
d317966b 2826 priv->num_tx_rings_p_up = mdev->profile.num_tx_rings_p_up;
c27a02cd 2827 priv->tx_ring_num = prof->tx_ring_num;
fbc6daf1 2828 priv->tx_work_limit = MLX4_EN_DEFAULT_TX_WORK;
bd635c35 2829 netdev_rss_key_fill(priv->rss_key, sizeof(priv->rss_key));
d317966b 2830
41d942d5 2831 priv->tx_ring = kzalloc(sizeof(struct mlx4_en_tx_ring *) * MAX_TX_RINGS,
d317966b 2832 GFP_KERNEL);
bc6a4744
AV		 2833 if (!priv->tx_ring) {
2834 err = -ENOMEM;
2835 goto out;
2836 }
41d942d5 2837 priv->tx_cq = kzalloc(sizeof(struct mlx4_en_cq *) * MAX_TX_RINGS,
d317966b 2838 GFP_KERNEL);
bc6a4744
AV		 2839 if (!priv->tx_cq) {
2840 err = -ENOMEM;
2841 goto out;
2842 }
c27a02cd 2843 priv->rx_ring_num = prof->rx_ring_num;
08ff3235 2844 priv->cqe_factor = (mdev->dev->caps.cqe_size == 64) ? 1 : 0;
b1b6b4da 2845 priv->cqe_size = mdev->dev->caps.cqe_size;
c27a02cd
YP		 2846 priv->mac_index = -1;
2847 priv->msg_enable = MLX4_EN_MSG_LEVEL;
564c274c 2848#ifdef CONFIG_MLX4_EN_DCB
540b3a39 2849 if (!mlx4_is_slave(priv->mdev->dev)) {
3742cc65 2850 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) {
540b3a39
OG		 2851 dev->dcbnl_ops = &mlx4_en_dcbnl_ops;
2852 } else {
2853 en_info(priv, "enabling only PFC DCB ops\n");
2854 dev->dcbnl_ops = &mlx4_en_dcbnl_pfc_ops;
2855 }
2856 }
564c274c 2857#endif
c27a02cd 2858
c07cb4b0
YB		 2859 for (i = 0; i < MLX4_EN_MAC_HASH_SIZE; ++i)
2860 INIT_HLIST_HEAD(&priv->mac_hash[i]);
16a10ffd 2861
c27a02cd
YP		 2862 /* Query for default mac and max mtu */
2863 priv->max_mtu = mdev->dev->caps.eth_mtu_cap[priv->port];
6bbb6d99 2864
f8c6455b
SM		 2865 if (mdev->dev->caps.rx_checksum_flags_port[priv->port] &
2866 MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP)
2867 priv->flags |= MLX4_EN_FLAG_RX_CSUM_NON_TCP_UDP;
2868
6bbb6d99
YB		 2869 /* Set default MAC */
2870 dev->addr_len = ETH_ALEN;
2871 mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
2872 if (!is_valid_ether_addr(dev->dev_addr)) {
2b3ddf27
JM		 2873 en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
2874 priv->port, dev->dev_addr);
2875 err = -EINVAL;
2876 goto out;
2877 } else if (mlx4_is_slave(priv->mdev->dev) &&
2878 (priv->mdev->dev->port_random_macs & 1 << priv->port)) {
2879 /* Random MAC was assigned in mlx4_slave_cap
2880 * in mlx4_core module
2881 */
2882 dev->addr_assign_type |= NET_ADDR_RANDOM;
2883 en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
c27a02cd
YP		 2884 }
2885
2695bab2 2886 memcpy(priv->current_mac, dev->dev_addr, sizeof(priv->current_mac));
6bbb6d99 2887
c27a02cd
YP		 2888 priv->stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
2889 DS_SIZE * MLX4_EN_MAX_RX_FRAGS);
2890 err = mlx4_en_alloc_resources(priv);
2891 if (err)
2892 goto out;
2893
ec693d47
AV		 2894 /* Initialize time stamping config */
2895 priv->hwtstamp_config.flags = 0;
2896 priv->hwtstamp_config.tx_type = HWTSTAMP_TX_OFF;
2897 priv->hwtstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
2898
c27a02cd
YP		 2899 /* Allocate page for receive rings */
2900 err = mlx4_alloc_hwq_res(mdev->dev, &priv->res,
2901 MLX4_EN_PAGE_SIZE, MLX4_EN_PAGE_SIZE);
2902 if (err) {
453a6082 2903 en_err(priv, "Failed to allocate page for rx qps\n");
c27a02cd
YP		 2904 goto out;
2905 }
2906 priv->allocated = 1;
2907
c27a02cd
YP		 2908 /*
2909 * Initialize netdev entry points
2910 */
8f7ba3ca
RE		 2911 if (mlx4_is_master(priv->mdev->dev))
2912 dev->netdev_ops = &mlx4_netdev_ops_master;
2913 else
2914 dev->netdev_ops = &mlx4_netdev_ops;
c27a02cd 2915 dev->watchdog_timeo = MLX4_EN_WATCHDOG_TIMEOUT;
1eb63a28
BH		 2916 netif_set_real_num_tx_queues(dev, priv->tx_ring_num);
2917 netif_set_real_num_rx_queues(dev, priv->rx_ring_num);
3addc568 2918
7ad24ea4 2919 dev->ethtool_ops = &mlx4_en_ethtool_ops;
c27a02cd 2920
c27a02cd
YP		 2921 /*
2922 * Set driver features
2923 */
c8c64cff
MM		 2924 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2925 if (mdev->LSO_support)
2926 dev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6;
2927
2928 dev->vlan_features = dev->hw_features;
2929
ad86107f 2930 dev->hw_features |= NETIF_F_RXCSUM | NETIF_F_RXHASH;
c8c64cff 2931 dev->features = dev->hw_features | NETIF_F_HIGHDMA |
f646968f
PM		 2932 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
2933 NETIF_F_HW_VLAN_CTAG_FILTER;
537f6f95
SM		 2934 dev->hw_features |= NETIF_F_LOOPBACK |
2935 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
c27a02cd 2936
e38af4fa
HHZ		 2937 if (!(mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) {
2938 dev->features |= NETIF_F_HW_VLAN_STAG_RX |
2939 NETIF_F_HW_VLAN_STAG_FILTER;
2940 dev->hw_features |= NETIF_F_HW_VLAN_STAG_RX;
2941 }
2942
2943 if (mlx4_is_slave(mdev->dev)) {
2944 int phv;
2945
2946 err = get_phv_bit(mdev->dev, port, &phv);
2947 if (!err && phv) {
2948 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
2949 priv->pflags |= MLX4_EN_PRIV_FLAGS_PHV;
2950 }
2951 } else {
2952 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN &&
2953 !(mdev->dev->caps.flags2 &
2954 MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN))
2955 dev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
2956 }
2957
f0df3503
MM		 2958 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
2959 dev->hw_features |= NETIF_F_RXFCS;
2960
78500b8c
MM		 2961 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS)
2962 dev->hw_features |= NETIF_F_RXALL;
2963
1eb8c695 2964 if (mdev->dev->caps.steering_mode ==
7d077cd3
MB		 2965 MLX4_STEERING_MODE_DEVICE_MANAGED &&
2966 mdev->dev->caps.dmfs_high_steer_mode != MLX4_STEERING_DMFS_A0_STATIC)
1eb8c695
AV		 2967 dev->hw_features |= NETIF_F_NTUPLE;
2968
cc5387f7
YB		 2969 if (mdev->dev->caps.steering_mode != MLX4_STEERING_MODE_A0)
2970 dev->priv_flags |= IFF_UNICAST_FLT;
2971
947cbb0a
EP		 2972 /* Setting a default hash function value */
2973 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP) {
2974 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2975 } else if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_XOR) {
2976 priv->rss_hash_fn = ETH_RSS_HASH_XOR;
2977 } else {
2978 en_warn(priv,
2979 "No RSS hash capabilities exposed, using Toeplitz\n");
2980 priv->rss_hash_fn = ETH_RSS_HASH_TOP;
2981 }
2982
c27a02cd 2983 mdev->pndev[port] = dev;
5da03547 2984 mdev->upper[port] = NULL;
c27a02cd
YP		 2985
2986 netif_carrier_off(dev);
4801ae70
EE		 2987 mlx4_en_set_default_moderation(priv);
2988
453a6082
YP		 2989 en_warn(priv, "Using %d TX rings\n", prof->tx_ring_num);
2990 en_warn(priv, "Using %d RX rings\n", prof->rx_ring_num);
2991
79aeaccd
YB		 2992 mlx4_en_update_loopback_state(priv->dev, priv->dev->features);
2993
90822265 2994 /* Configure port */
5c8e9046 2995 mlx4_en_calc_rx_buf(dev);
90822265 2996 err = mlx4_SET_PORT_general(mdev->dev, priv->port,
5c8e9046
YP		 2997 priv->rx_skb_size + ETH_FCS_LEN,
2998 prof->tx_pause, prof->tx_ppp,
2999 prof->rx_pause, prof->rx_ppp);
90822265 3000 if (err) {
1a91de28
JP		 3001 en_err(priv, "Failed setting port general configurations for port %d, with error %d\n",
3002 priv->port, err);
90822265
YP		 3003 goto out;
3004 }
3005
837052d0 3006 if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
1b136de1 3007 err = mlx4_SET_PORT_VXLAN(mdev->dev, priv->port, VXLAN_STEER_BY_OUTER_MAC, 1);
837052d0
OG		 3008 if (err) {
3009 en_err(priv, "Failed setting port L2 tunnel configuration, err %d\n",
3010 err);
3011 goto out;
3012 }
3013 }
3014
90822265
YP		 3015 /* Init port */
3016 en_warn(priv, "Initializing port\n");
3017 err = mlx4_INIT_PORT(mdev->dev, priv->port);
3018 if (err) {
3019 en_err(priv, "Failed Initializing port\n");
3020 goto out;
3021 }
c27a02cd 3022 queue_delayed_work(mdev->workqueue, &priv->stats_task, STATS_DELAY);
dc8142ea 3023
90683061 3024 /* Initialize time stamp mechanism */
dc8142ea 3025 if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS)
90683061
EE		 3026 mlx4_en_init_timestamp(mdev);
3027
fc9f5ea9
EE		 3028 queue_delayed_work(mdev->workqueue, &priv->service_task,
3029 SERVICE_TASK_DELAY);
dc8142ea 3030
0b131561
MB		 3031 mlx4_en_set_stats_bitmap(mdev->dev, &priv->stats_bitmap,
3032 mdev->profile.prof[priv->port].rx_ppp,
3033 mdev->profile.prof[priv->port].rx_pause,
3034 mdev->profile.prof[priv->port].tx_ppp,
3035 mdev->profile.prof[priv->port].tx_pause);
39de961a 3036
e5eda89d
IS		 3037 err = register_netdev(dev);
3038 if (err) {
3039 en_err(priv, "Netdev registration failed for port %d\n", port);
3040 goto out;
3041 }
3042
3043 priv->registered = 1;
3044
c27a02cd
YP		 3045 return 0;
3046
3047out:
3048 mlx4_en_destroy_netdev(dev);
3049 return err;
3050}
3051
537f6f95
SM		 3052int mlx4_en_reset_config(struct net_device *dev,
3053 struct hwtstamp_config ts_config,
3054 netdev_features_t features)
3055{
3056 struct mlx4_en_priv *priv = netdev_priv(dev);
3057 struct mlx4_en_dev *mdev = priv->mdev;
3058 int port_up = 0;
3059 int err = 0;
3060
3061 if (priv->hwtstamp_config.tx_type == ts_config.tx_type &&
3062 priv->hwtstamp_config.rx_filter == ts_config.rx_filter &&
f0df3503
MM		 3063 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3064 !DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS))
537f6f95
SM		 3065 return 0; /* Nothing to change */
3066
3067 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX) &&
3068 (features & NETIF_F_HW_VLAN_CTAG_RX) &&
3069 (priv->hwtstamp_config.rx_filter != HWTSTAMP_FILTER_NONE)) {
3070 en_warn(priv, "Can't turn ON rx vlan offload while time-stamping rx filter is ON\n");
3071 return -EINVAL;
3072 }
3073
3074 mutex_lock(&mdev->state_lock);
3075 if (priv->port_up) {
3076 port_up = 1;
3077 mlx4_en_stop_port(dev, 1);
3078 }
3079
3080 mlx4_en_free_resources(priv);
3081
3082 en_warn(priv, "Changing device configuration rx filter(%x) rx vlan(%x)\n",
3083 ts_config.rx_filter, !!(features & NETIF_F_HW_VLAN_CTAG_RX));
3084
3085 priv->hwtstamp_config.tx_type = ts_config.tx_type;
3086 priv->hwtstamp_config.rx_filter = ts_config.rx_filter;
3087
3088 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_HW_VLAN_CTAG_RX)) {
3089 if (features & NETIF_F_HW_VLAN_CTAG_RX)
3090 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3091 else
3092 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3093 } else if (ts_config.rx_filter == HWTSTAMP_FILTER_NONE) {
3094 /* RX time-stamping is OFF, update the RX vlan offload
3095 * to the latest wanted state
3096 */
3097 if (dev->wanted_features & NETIF_F_HW_VLAN_CTAG_RX)
3098 dev->features |= NETIF_F_HW_VLAN_CTAG_RX;
3099 else
3100 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3101 }
3102
f0df3503
MM		 3103 if (DEV_FEATURE_CHANGED(dev, features, NETIF_F_RXFCS)) {
3104 if (features & NETIF_F_RXFCS)
3105 dev->features |= NETIF_F_RXFCS;
3106 else
3107 dev->features &= ~NETIF_F_RXFCS;
3108 }
3109
537f6f95
SM		 3110 /* RX vlan offload and RX time-stamping can't co-exist !
3111 * Regardless of the caller's choice,
3112 * Turn Off RX vlan offload in case of time-stamping is ON
3113 */
3114 if (ts_config.rx_filter != HWTSTAMP_FILTER_NONE) {
3115 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
3116 en_warn(priv, "Turning off RX vlan offload since RX time-stamping is ON\n");
3117 dev->features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3118 }
3119
3120 err = mlx4_en_alloc_resources(priv);
3121 if (err) {
3122 en_err(priv, "Failed reallocating port resources\n");
3123 goto out;
3124 }
3125 if (port_up) {
3126 err = mlx4_en_start_port(dev);
3127 if (err)
3128 en_err(priv, "Failed starting port\n");
3129 }
3130
3131out:
3132 mutex_unlock(&mdev->state_lock);
3133 netdev_features_change(dev);
3134 return err;
3135}
Linux kernel - Deliverables
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