Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
076bb0c8 | 34 | #include <net/busy_poll.h> |
c27a02cd | 35 | #include <linux/mlx4/cq.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
b67bfe0d | 39 | #include <linux/rculist.h> |
c27a02cd YP |
40 | #include <linux/if_ether.h> |
41 | #include <linux/if_vlan.h> | |
42 | #include <linux/vmalloc.h> | |
35f6f453 | 43 | #include <linux/irq.h> |
c27a02cd YP |
44 | |
45 | #include "mlx4_en.h" | |
46 | ||
51151a16 ED |
47 | static int mlx4_alloc_pages(struct mlx4_en_priv *priv, |
48 | struct mlx4_en_rx_alloc *page_alloc, | |
49 | const struct mlx4_en_frag_info *frag_info, | |
50 | gfp_t _gfp) | |
51 | { | |
52 | int order; | |
53 | struct page *page; | |
54 | dma_addr_t dma; | |
55 | ||
56 | for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) { | |
57 | gfp_t gfp = _gfp; | |
58 | ||
59 | if (order) | |
60 | gfp |= __GFP_COMP | __GFP_NOWARN; | |
61 | page = alloc_pages(gfp, order); | |
62 | if (likely(page)) | |
63 | break; | |
64 | if (--order < 0 || | |
65 | ((PAGE_SIZE << order) < frag_info->frag_size)) | |
66 | return -ENOMEM; | |
67 | } | |
68 | dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order, | |
69 | PCI_DMA_FROMDEVICE); | |
70 | if (dma_mapping_error(priv->ddev, dma)) { | |
71 | put_page(page); | |
72 | return -ENOMEM; | |
73 | } | |
70fbe079 | 74 | page_alloc->page_size = PAGE_SIZE << order; |
51151a16 ED |
75 | page_alloc->page = page; |
76 | page_alloc->dma = dma; | |
70fbe079 | 77 | page_alloc->page_offset = frag_info->frag_align; |
51151a16 | 78 | /* Not doing get_page() for each frag is a big win |
98226208 | 79 | * on asymetric workloads. Note we can not use atomic_set(). |
51151a16 | 80 | */ |
98226208 ED |
81 | atomic_add(page_alloc->page_size / frag_info->frag_stride - 1, |
82 | &page->_count); | |
51151a16 ED |
83 | return 0; |
84 | } | |
85 | ||
4cce66cd TLSC |
86 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
87 | struct mlx4_en_rx_desc *rx_desc, | |
88 | struct mlx4_en_rx_alloc *frags, | |
51151a16 ED |
89 | struct mlx4_en_rx_alloc *ring_alloc, |
90 | gfp_t gfp) | |
c27a02cd | 91 | { |
4cce66cd | 92 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
51151a16 | 93 | const struct mlx4_en_frag_info *frag_info; |
c27a02cd YP |
94 | struct page *page; |
95 | dma_addr_t dma; | |
4cce66cd | 96 | int i; |
c27a02cd | 97 | |
4cce66cd TLSC |
98 | for (i = 0; i < priv->num_frags; i++) { |
99 | frag_info = &priv->frag_info[i]; | |
51151a16 | 100 | page_alloc[i] = ring_alloc[i]; |
70fbe079 AV |
101 | page_alloc[i].page_offset += frag_info->frag_stride; |
102 | ||
103 | if (page_alloc[i].page_offset + frag_info->frag_stride <= | |
104 | ring_alloc[i].page_size) | |
51151a16 | 105 | continue; |
70fbe079 | 106 | |
51151a16 ED |
107 | if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp)) |
108 | goto out; | |
4cce66cd | 109 | } |
c27a02cd | 110 | |
4cce66cd TLSC |
111 | for (i = 0; i < priv->num_frags; i++) { |
112 | frags[i] = ring_alloc[i]; | |
70fbe079 | 113 | dma = ring_alloc[i].dma + ring_alloc[i].page_offset; |
4cce66cd TLSC |
114 | ring_alloc[i] = page_alloc[i]; |
115 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 116 | } |
4cce66cd | 117 | |
c27a02cd | 118 | return 0; |
4cce66cd | 119 | |
4cce66cd TLSC |
120 | out: |
121 | while (i--) { | |
122 | frag_info = &priv->frag_info[i]; | |
51151a16 | 123 | if (page_alloc[i].page != ring_alloc[i].page) { |
4cce66cd | 124 | dma_unmap_page(priv->ddev, page_alloc[i].dma, |
70fbe079 | 125 | page_alloc[i].page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
126 | page = page_alloc[i].page; |
127 | atomic_set(&page->_count, 1); | |
128 | put_page(page); | |
129 | } | |
4cce66cd TLSC |
130 | } |
131 | return -ENOMEM; | |
132 | } | |
133 | ||
134 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
135 | struct mlx4_en_rx_alloc *frags, | |
136 | int i) | |
137 | { | |
51151a16 | 138 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
021f1107 | 139 | u32 next_frag_end = frags[i].page_offset + 2 * frag_info->frag_stride; |
4cce66cd | 140 | |
021f1107 AV |
141 | |
142 | if (next_frag_end > frags[i].page_size) | |
70fbe079 AV |
143 | dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size, |
144 | PCI_DMA_FROMDEVICE); | |
51151a16 | 145 | |
4cce66cd TLSC |
146 | if (frags[i].page) |
147 | put_page(frags[i].page); | |
c27a02cd YP |
148 | } |
149 | ||
150 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
151 | struct mlx4_en_rx_ring *ring) | |
152 | { | |
c27a02cd | 153 | int i; |
51151a16 | 154 | struct mlx4_en_rx_alloc *page_alloc; |
c27a02cd YP |
155 | |
156 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 | 157 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
c27a02cd | 158 | |
51151a16 ED |
159 | if (mlx4_alloc_pages(priv, &ring->page_alloc[i], |
160 | frag_info, GFP_KERNEL)) | |
4cce66cd | 161 | goto out; |
c27a02cd YP |
162 | } |
163 | return 0; | |
164 | ||
165 | out: | |
166 | while (i--) { | |
51151a16 ED |
167 | struct page *page; |
168 | ||
c27a02cd | 169 | page_alloc = &ring->page_alloc[i]; |
4cce66cd | 170 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 | 171 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
51151a16 ED |
172 | page = page_alloc->page; |
173 | atomic_set(&page->_count, 1); | |
174 | put_page(page); | |
c27a02cd YP |
175 | page_alloc->page = NULL; |
176 | } | |
177 | return -ENOMEM; | |
178 | } | |
179 | ||
180 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
181 | struct mlx4_en_rx_ring *ring) | |
182 | { | |
183 | struct mlx4_en_rx_alloc *page_alloc; | |
184 | int i; | |
185 | ||
186 | for (i = 0; i < priv->num_frags; i++) { | |
51151a16 ED |
187 | const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; |
188 | ||
c27a02cd | 189 | page_alloc = &ring->page_alloc[i]; |
453a6082 YP |
190 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
191 | i, page_count(page_alloc->page)); | |
c27a02cd | 192 | |
4cce66cd | 193 | dma_unmap_page(priv->ddev, page_alloc->dma, |
70fbe079 AV |
194 | page_alloc->page_size, PCI_DMA_FROMDEVICE); |
195 | while (page_alloc->page_offset + frag_info->frag_stride < | |
196 | page_alloc->page_size) { | |
51151a16 | 197 | put_page(page_alloc->page); |
70fbe079 | 198 | page_alloc->page_offset += frag_info->frag_stride; |
51151a16 | 199 | } |
c27a02cd YP |
200 | page_alloc->page = NULL; |
201 | } | |
202 | } | |
203 | ||
c27a02cd YP |
204 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
205 | struct mlx4_en_rx_ring *ring, int index) | |
206 | { | |
207 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
208 | int possible_frags; |
209 | int i; | |
210 | ||
c27a02cd YP |
211 | /* Set size and memtype fields */ |
212 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
213 | rx_desc->data[i].byte_count = |
214 | cpu_to_be32(priv->frag_info[i].frag_size); | |
215 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
216 | } | |
217 | ||
218 | /* If the number of used fragments does not fill up the ring stride, | |
219 | * remaining (unused) fragments must be padded with null address/size | |
220 | * and a special memory key */ | |
221 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
222 | for (i = priv->num_frags; i < possible_frags; i++) { | |
223 | rx_desc->data[i].byte_count = 0; | |
224 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
225 | rx_desc->data[i].addr = 0; | |
226 | } | |
227 | } | |
228 | ||
c27a02cd | 229 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
51151a16 ED |
230 | struct mlx4_en_rx_ring *ring, int index, |
231 | gfp_t gfp) | |
c27a02cd YP |
232 | { |
233 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
234 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
235 | (index << priv->log_rx_info); | |
c27a02cd | 236 | |
51151a16 | 237 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp); |
c27a02cd YP |
238 | } |
239 | ||
240 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
241 | { | |
242 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
243 | } | |
244 | ||
38aab07c YP |
245 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
246 | struct mlx4_en_rx_ring *ring, | |
247 | int index) | |
248 | { | |
4cce66cd | 249 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
250 | int nr; |
251 | ||
4cce66cd | 252 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 253 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 254 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 255 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
256 | } |
257 | } | |
258 | ||
c27a02cd YP |
259 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
260 | { | |
c27a02cd YP |
261 | struct mlx4_en_rx_ring *ring; |
262 | int ring_ind; | |
263 | int buf_ind; | |
38aab07c | 264 | int new_size; |
c27a02cd YP |
265 | |
266 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
267 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 268 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
269 | |
270 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
51151a16 ED |
271 | ring->actual_size, |
272 | GFP_KERNEL)) { | |
c27a02cd | 273 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { |
1a91de28 | 274 | en_err(priv, "Failed to allocate enough rx buffers\n"); |
c27a02cd YP |
275 | return -ENOMEM; |
276 | } else { | |
38aab07c | 277 | new_size = rounddown_pow_of_two(ring->actual_size); |
1a91de28 | 278 | en_warn(priv, "Only %d buffers allocated reducing ring size to %d\n", |
453a6082 | 279 | ring->actual_size, new_size); |
38aab07c | 280 | goto reduce_rings; |
c27a02cd YP |
281 | } |
282 | } | |
283 | ring->actual_size++; | |
284 | ring->prod++; | |
285 | } | |
286 | } | |
38aab07c YP |
287 | return 0; |
288 | ||
289 | reduce_rings: | |
290 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 291 | ring = priv->rx_ring[ring_ind]; |
38aab07c YP |
292 | while (ring->actual_size > new_size) { |
293 | ring->actual_size--; | |
294 | ring->prod--; | |
295 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
296 | } | |
38aab07c YP |
297 | } |
298 | ||
c27a02cd YP |
299 | return 0; |
300 | } | |
301 | ||
c27a02cd YP |
302 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
303 | struct mlx4_en_rx_ring *ring) | |
304 | { | |
c27a02cd | 305 | int index; |
c27a02cd | 306 | |
453a6082 YP |
307 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
308 | ring->cons, ring->prod); | |
c27a02cd YP |
309 | |
310 | /* Unmap and free Rx buffers */ | |
38aab07c | 311 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
312 | while (ring->cons != ring->prod) { |
313 | index = ring->cons & ring->size_mask; | |
453a6082 | 314 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 315 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
316 | ++ring->cons; |
317 | } | |
318 | } | |
319 | ||
02512482 IS |
320 | void mlx4_en_set_num_rx_rings(struct mlx4_en_dev *mdev) |
321 | { | |
322 | int i; | |
323 | int num_of_eqs; | |
bb2146bc | 324 | int num_rx_rings; |
02512482 IS |
325 | struct mlx4_dev *dev = mdev->dev; |
326 | ||
327 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH) { | |
328 | if (!dev->caps.comp_pool) | |
329 | num_of_eqs = max_t(int, MIN_RX_RINGS, | |
330 | min_t(int, | |
331 | dev->caps.num_comp_vectors, | |
332 | DEF_RX_RINGS)); | |
333 | else | |
334 | num_of_eqs = min_t(int, MAX_MSIX_P_PORT, | |
335 | dev->caps.comp_pool/ | |
336 | dev->caps.num_ports) - 1; | |
337 | ||
ea1c1af1 AV |
338 | num_rx_rings = mlx4_low_memory_profile() ? MIN_RX_RINGS : |
339 | min_t(int, num_of_eqs, | |
340 | netif_get_num_default_rss_queues()); | |
02512482 | 341 | mdev->profile.prof[i].rx_ring_num = |
bb2146bc | 342 | rounddown_pow_of_two(num_rx_rings); |
02512482 IS |
343 | } |
344 | } | |
345 | ||
c27a02cd | 346 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
41d942d5 | 347 | struct mlx4_en_rx_ring **pring, |
163561a4 | 348 | u32 size, u16 stride, int node) |
c27a02cd YP |
349 | { |
350 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 351 | struct mlx4_en_rx_ring *ring; |
4cce66cd | 352 | int err = -ENOMEM; |
c27a02cd YP |
353 | int tmp; |
354 | ||
163561a4 | 355 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 356 | if (!ring) { |
163561a4 EE |
357 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
358 | if (!ring) { | |
359 | en_err(priv, "Failed to allocate RX ring structure\n"); | |
360 | return -ENOMEM; | |
361 | } | |
41d942d5 EE |
362 | } |
363 | ||
c27a02cd YP |
364 | ring->prod = 0; |
365 | ring->cons = 0; | |
366 | ring->size = size; | |
367 | ring->size_mask = size - 1; | |
368 | ring->stride = stride; | |
369 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 370 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
371 | |
372 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 373 | sizeof(struct mlx4_en_rx_alloc)); |
163561a4 | 374 | ring->rx_info = vmalloc_node(tmp, node); |
41d942d5 | 375 | if (!ring->rx_info) { |
163561a4 EE |
376 | ring->rx_info = vmalloc(tmp); |
377 | if (!ring->rx_info) { | |
378 | err = -ENOMEM; | |
379 | goto err_ring; | |
380 | } | |
41d942d5 | 381 | } |
e404decb | 382 | |
453a6082 | 383 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
384 | ring->rx_info, tmp); |
385 | ||
163561a4 EE |
386 | /* Allocate HW buffers on provided NUMA node */ |
387 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
388 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, |
389 | ring->buf_size, 2 * PAGE_SIZE); | |
163561a4 | 390 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 391 | if (err) |
41d942d5 | 392 | goto err_info; |
c27a02cd YP |
393 | |
394 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
395 | if (err) { | |
453a6082 | 396 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
397 | goto err_hwq; |
398 | } | |
399 | ring->buf = ring->wqres.buf.direct.buf; | |
400 | ||
ec693d47 AV |
401 | ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter; |
402 | ||
41d942d5 | 403 | *pring = ring; |
c27a02cd YP |
404 | return 0; |
405 | ||
c27a02cd YP |
406 | err_hwq: |
407 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
41d942d5 | 408 | err_info: |
c27a02cd YP |
409 | vfree(ring->rx_info); |
410 | ring->rx_info = NULL; | |
41d942d5 EE |
411 | err_ring: |
412 | kfree(ring); | |
413 | *pring = NULL; | |
414 | ||
c27a02cd YP |
415 | return err; |
416 | } | |
417 | ||
418 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
419 | { | |
c27a02cd YP |
420 | struct mlx4_en_rx_ring *ring; |
421 | int i; | |
422 | int ring_ind; | |
423 | int err; | |
424 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
425 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
426 | |
427 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 428 | ring = priv->rx_ring[ring_ind]; |
c27a02cd YP |
429 | |
430 | ring->prod = 0; | |
431 | ring->cons = 0; | |
432 | ring->actual_size = 0; | |
41d942d5 | 433 | ring->cqn = priv->rx_cq[ring_ind]->mcq.cqn; |
c27a02cd YP |
434 | |
435 | ring->stride = stride; | |
9f519f68 YP |
436 | if (ring->stride <= TXBB_SIZE) |
437 | ring->buf += TXBB_SIZE; | |
438 | ||
c27a02cd YP |
439 | ring->log_stride = ffs(ring->stride) - 1; |
440 | ring->buf_size = ring->size * ring->stride; | |
441 | ||
442 | memset(ring->buf, 0, ring->buf_size); | |
443 | mlx4_en_update_rx_prod_db(ring); | |
444 | ||
4cce66cd | 445 | /* Initialize all descriptors */ |
c27a02cd YP |
446 | for (i = 0; i < ring->size; i++) |
447 | mlx4_en_init_rx_desc(priv, ring, i); | |
448 | ||
449 | /* Initialize page allocators */ | |
450 | err = mlx4_en_init_allocator(priv, ring); | |
451 | if (err) { | |
453a6082 | 452 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
453 | if (ring->stride <= TXBB_SIZE) |
454 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
455 | ring_ind--; |
456 | goto err_allocator; | |
c27a02cd | 457 | } |
c27a02cd | 458 | } |
b58515be IM |
459 | err = mlx4_en_fill_rx_buffers(priv); |
460 | if (err) | |
c27a02cd YP |
461 | goto err_buffers; |
462 | ||
463 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
41d942d5 | 464 | ring = priv->rx_ring[ring_ind]; |
c27a02cd | 465 | |
00d7d7bc | 466 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 467 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
468 | } |
469 | ||
470 | return 0; | |
471 | ||
c27a02cd YP |
472 | err_buffers: |
473 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
41d942d5 | 474 | mlx4_en_free_rx_buf(priv, priv->rx_ring[ring_ind]); |
c27a02cd YP |
475 | |
476 | ring_ind = priv->rx_ring_num - 1; | |
477 | err_allocator: | |
478 | while (ring_ind >= 0) { | |
41d942d5 EE |
479 | if (priv->rx_ring[ring_ind]->stride <= TXBB_SIZE) |
480 | priv->rx_ring[ring_ind]->buf -= TXBB_SIZE; | |
481 | mlx4_en_destroy_allocator(priv, priv->rx_ring[ring_ind]); | |
c27a02cd YP |
482 | ring_ind--; |
483 | } | |
484 | return err; | |
485 | } | |
486 | ||
487 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
41d942d5 EE |
488 | struct mlx4_en_rx_ring **pring, |
489 | u32 size, u16 stride) | |
c27a02cd YP |
490 | { |
491 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 492 | struct mlx4_en_rx_ring *ring = *pring; |
c27a02cd | 493 | |
c27a02cd | 494 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 495 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
496 | vfree(ring->rx_info); |
497 | ring->rx_info = NULL; | |
41d942d5 EE |
498 | kfree(ring); |
499 | *pring = NULL; | |
1eb8c695 | 500 | #ifdef CONFIG_RFS_ACCEL |
41d942d5 | 501 | mlx4_en_cleanup_filters(priv); |
1eb8c695 | 502 | #endif |
c27a02cd YP |
503 | } |
504 | ||
505 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
506 | struct mlx4_en_rx_ring *ring) | |
507 | { | |
c27a02cd | 508 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
509 | if (ring->stride <= TXBB_SIZE) |
510 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
511 | mlx4_en_destroy_allocator(priv, ring); |
512 | } | |
513 | ||
514 | ||
c27a02cd YP |
515 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
516 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 517 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 518 | struct sk_buff *skb, |
c27a02cd YP |
519 | int length) |
520 | { | |
90278c9f | 521 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
522 | struct mlx4_en_frag_info *frag_info; |
523 | int nr; | |
524 | dma_addr_t dma; | |
525 | ||
4cce66cd | 526 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
527 | for (nr = 0; nr < priv->num_frags; nr++) { |
528 | frag_info = &priv->frag_info[nr]; | |
529 | if (length <= frag_info->frag_prefix_size) | |
530 | break; | |
4cce66cd TLSC |
531 | if (!frags[nr].page) |
532 | goto fail; | |
c27a02cd | 533 | |
c27a02cd | 534 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
535 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
536 | DMA_FROM_DEVICE); | |
c27a02cd | 537 | |
4cce66cd | 538 | /* Save page reference in skb */ |
4cce66cd TLSC |
539 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); |
540 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
70fbe079 | 541 | skb_frags_rx[nr].page_offset = frags[nr].page_offset; |
4cce66cd | 542 | skb->truesize += frag_info->frag_stride; |
51151a16 | 543 | frags[nr].page = NULL; |
c27a02cd YP |
544 | } |
545 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 546 | if (nr > 0) |
9e903e08 ED |
547 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
548 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
549 | return nr; |
550 | ||
551 | fail: | |
c27a02cd YP |
552 | while (nr > 0) { |
553 | nr--; | |
311761c8 | 554 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
555 | } |
556 | return 0; | |
557 | } | |
558 | ||
559 | ||
560 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
561 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 562 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
563 | unsigned int length) |
564 | { | |
c27a02cd YP |
565 | struct sk_buff *skb; |
566 | void *va; | |
567 | int used_frags; | |
568 | dma_addr_t dma; | |
569 | ||
c056b734 | 570 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 571 | if (!skb) { |
453a6082 | 572 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
573 | return NULL; |
574 | } | |
c27a02cd YP |
575 | skb_reserve(skb, NET_IP_ALIGN); |
576 | skb->len = length; | |
c27a02cd YP |
577 | |
578 | /* Get pointer to first fragment so we could copy the headers into the | |
579 | * (linear part of the) skb */ | |
70fbe079 | 580 | va = page_address(frags[0].page) + frags[0].page_offset; |
c27a02cd YP |
581 | |
582 | if (length <= SMALL_PACKET_SIZE) { | |
583 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 584 | * sync buffers for the copy */ |
c27a02cd | 585 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 586 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 587 | DMA_FROM_DEVICE); |
c27a02cd | 588 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
589 | skb->tail += length; |
590 | } else { | |
cfecec56 ED |
591 | unsigned int pull_len; |
592 | ||
c27a02cd | 593 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
594 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
595 | skb, length); | |
785a0982 YP |
596 | if (unlikely(!used_frags)) { |
597 | kfree_skb(skb); | |
598 | return NULL; | |
599 | } | |
c27a02cd YP |
600 | skb_shinfo(skb)->nr_frags = used_frags; |
601 | ||
cfecec56 | 602 | pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE); |
c27a02cd | 603 | /* Copy headers into the skb linear buffer */ |
cfecec56 ED |
604 | memcpy(skb->data, va, pull_len); |
605 | skb->tail += pull_len; | |
c27a02cd YP |
606 | |
607 | /* Skip headers in first fragment */ | |
cfecec56 | 608 | skb_shinfo(skb)->frags[0].page_offset += pull_len; |
c27a02cd YP |
609 | |
610 | /* Adjust size of first fragment */ | |
cfecec56 ED |
611 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len); |
612 | skb->data_len = length - pull_len; | |
c27a02cd YP |
613 | } |
614 | return skb; | |
615 | } | |
616 | ||
e7c1c2c4 YP |
617 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
618 | { | |
619 | int i; | |
620 | int offset = ETH_HLEN; | |
621 | ||
622 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
623 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
624 | goto out_loopback; | |
625 | } | |
626 | /* Loopback found */ | |
627 | priv->loopback_ok = 1; | |
628 | ||
629 | out_loopback: | |
630 | dev_kfree_skb_any(skb); | |
631 | } | |
c27a02cd | 632 | |
4cce66cd TLSC |
633 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
634 | struct mlx4_en_rx_ring *ring) | |
635 | { | |
636 | int index = ring->prod & ring->size_mask; | |
637 | ||
638 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
51151a16 | 639 | if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC)) |
4cce66cd TLSC |
640 | break; |
641 | ring->prod++; | |
642 | index = ring->prod & ring->size_mask; | |
643 | } | |
644 | } | |
645 | ||
c27a02cd YP |
646 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
647 | { | |
648 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
ec693d47 | 649 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd | 650 | struct mlx4_cqe *cqe; |
41d942d5 | 651 | struct mlx4_en_rx_ring *ring = priv->rx_ring[cq->ring]; |
4cce66cd | 652 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
653 | struct mlx4_en_rx_desc *rx_desc; |
654 | struct sk_buff *skb; | |
655 | int index; | |
656 | int nr; | |
657 | unsigned int length; | |
658 | int polled = 0; | |
659 | int ip_summed; | |
08ff3235 | 660 | int factor = priv->cqe_factor; |
ec693d47 | 661 | u64 timestamp; |
837052d0 | 662 | bool l2_tunnel; |
c27a02cd YP |
663 | |
664 | if (!priv->port_up) | |
665 | return 0; | |
666 | ||
38be0a34 EB |
667 | if (budget <= 0) |
668 | return polled; | |
669 | ||
c27a02cd YP |
670 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx |
671 | * descriptor offset can be deduced from the CQE index instead of | |
672 | * reading 'cqe->index' */ | |
673 | index = cq->mcq.cons_index & ring->size_mask; | |
b1b6b4da | 674 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
c27a02cd YP |
675 | |
676 | /* Process all completed CQEs */ | |
677 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
678 | cq->mcq.cons_index & cq->size)) { | |
679 | ||
4cce66cd | 680 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
681 | rx_desc = ring->buf + (index << ring->log_stride); |
682 | ||
683 | /* | |
684 | * make sure we read the CQE after we read the ownership bit | |
685 | */ | |
686 | rmb(); | |
687 | ||
688 | /* Drop packet on bad receive or bad checksum */ | |
689 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
690 | MLX4_CQE_OPCODE_ERROR)) { | |
1a91de28 JP |
691 | en_err(priv, "CQE completed in error - vendor syndrom:%d syndrom:%d\n", |
692 | ((struct mlx4_err_cqe *)cqe)->vendor_err_syndrome, | |
693 | ((struct mlx4_err_cqe *)cqe)->syndrome); | |
c27a02cd YP |
694 | goto next; |
695 | } | |
696 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 697 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
698 | goto next; |
699 | } | |
700 | ||
79aeaccd YB |
701 | /* Check if we need to drop the packet if SRIOV is not enabled |
702 | * and not performing the selftest or flb disabled | |
703 | */ | |
704 | if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) { | |
705 | struct ethhdr *ethh; | |
706 | dma_addr_t dma; | |
79aeaccd YB |
707 | /* Get pointer to first fragment since we haven't |
708 | * skb yet and cast it to ethhdr struct | |
709 | */ | |
710 | dma = be64_to_cpu(rx_desc->data[0].addr); | |
711 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
712 | DMA_FROM_DEVICE); | |
713 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
70fbe079 | 714 | frags[0].page_offset); |
79aeaccd | 715 | |
c07cb4b0 YB |
716 | if (is_multicast_ether_addr(ethh->h_dest)) { |
717 | struct mlx4_mac_entry *entry; | |
c07cb4b0 YB |
718 | struct hlist_head *bucket; |
719 | unsigned int mac_hash; | |
720 | ||
721 | /* Drop the packet, since HW loopback-ed it */ | |
722 | mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX]; | |
723 | bucket = &priv->mac_hash[mac_hash]; | |
724 | rcu_read_lock(); | |
b67bfe0d | 725 | hlist_for_each_entry_rcu(entry, bucket, hlist) { |
c07cb4b0 YB |
726 | if (ether_addr_equal_64bits(entry->mac, |
727 | ethh->h_source)) { | |
728 | rcu_read_unlock(); | |
729 | goto next; | |
730 | } | |
731 | } | |
732 | rcu_read_unlock(); | |
733 | } | |
79aeaccd | 734 | } |
5b4c4d36 | 735 | |
c27a02cd YP |
736 | /* |
737 | * Packet is OK - process it. | |
738 | */ | |
739 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 740 | length -= ring->fcs_del; |
c27a02cd YP |
741 | ring->bytes += length; |
742 | ring->packets++; | |
837052d0 OG |
743 | l2_tunnel = (dev->hw_enc_features & NETIF_F_RXCSUM) && |
744 | (cqe->vlan_my_qpn & cpu_to_be32(MLX4_CQE_L2_TUNNEL)); | |
c27a02cd | 745 | |
c8c64cff | 746 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
c27a02cd YP |
747 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && |
748 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
ad04378c | 749 | ring->csum_ok++; |
f1d29a3f | 750 | /* This packet is eligible for GRO if it is: |
c27a02cd YP |
751 | * - DIX Ethernet (type interpretation) |
752 | * - TCP/IP (v4) | |
753 | * - without IP options | |
9e77a2b8 AV |
754 | * - not an IP fragment |
755 | * - no LLS polling in progress | |
756 | */ | |
e6a76758 | 757 | if (!mlx4_en_cq_busy_polling(cq) && |
9e77a2b8 | 758 | (dev->features & NETIF_F_GRO)) { |
fa37a958 | 759 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); |
ebc872c7 YP |
760 | if (!gro_skb) |
761 | goto next; | |
c27a02cd | 762 | |
4cce66cd TLSC |
763 | nr = mlx4_en_complete_rx_desc(priv, |
764 | rx_desc, frags, gro_skb, | |
765 | length); | |
c27a02cd YP |
766 | if (!nr) |
767 | goto next; | |
768 | ||
fa37a958 YP |
769 | skb_shinfo(gro_skb)->nr_frags = nr; |
770 | gro_skb->len = length; | |
771 | gro_skb->data_len = length; | |
fa37a958 YP |
772 | gro_skb->ip_summed = CHECKSUM_UNNECESSARY; |
773 | ||
837052d0 | 774 | if (l2_tunnel) |
9ca8600e | 775 | gro_skb->csum_level = 1; |
ec693d47 AV |
776 | if ((cqe->vlan_my_qpn & |
777 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) && | |
778 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) { | |
f1b553fb JP |
779 | u16 vid = be16_to_cpu(cqe->sl_vid); |
780 | ||
86a9bad3 | 781 | __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid); |
f1b553fb JP |
782 | } |
783 | ||
ad86107f | 784 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
785 | skb_set_hash(gro_skb, |
786 | be32_to_cpu(cqe->immed_rss_invalid), | |
787 | PKT_HASH_TYPE_L3); | |
ad86107f | 788 | |
3b61008d | 789 | skb_record_rx_queue(gro_skb, cq->ring); |
32b333fe | 790 | skb_mark_napi_id(gro_skb, &cq->napi); |
c27a02cd | 791 | |
ec693d47 AV |
792 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
793 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
794 | mlx4_en_fill_hwtstamps(mdev, | |
795 | skb_hwtstamps(gro_skb), | |
796 | timestamp); | |
797 | } | |
798 | ||
799 | napi_gro_frags(&cq->napi); | |
c27a02cd YP |
800 | goto next; |
801 | } | |
802 | ||
f1d29a3f | 803 | /* GRO not possible, complete processing here */ |
c27a02cd | 804 | ip_summed = CHECKSUM_UNNECESSARY; |
c27a02cd YP |
805 | } else { |
806 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 807 | ring->csum_none++; |
c27a02cd YP |
808 | } |
809 | } else { | |
810 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 811 | ring->csum_none++; |
c27a02cd YP |
812 | } |
813 | ||
4cce66cd | 814 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd YP |
815 | if (!skb) { |
816 | priv->stats.rx_dropped++; | |
817 | goto next; | |
818 | } | |
819 | ||
e7c1c2c4 YP |
820 | if (unlikely(priv->validate_loopback)) { |
821 | validate_loopback(priv, skb); | |
822 | goto next; | |
823 | } | |
824 | ||
c27a02cd YP |
825 | skb->ip_summed = ip_summed; |
826 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 827 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 828 | |
9ca8600e TH |
829 | if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY) |
830 | skb->csum_level = 1; | |
837052d0 | 831 | |
ad86107f | 832 | if (dev->features & NETIF_F_RXHASH) |
69174416 TH |
833 | skb_set_hash(skb, |
834 | be32_to_cpu(cqe->immed_rss_invalid), | |
835 | PKT_HASH_TYPE_L3); | |
ad86107f | 836 | |
ec693d47 AV |
837 | if ((be32_to_cpu(cqe->vlan_my_qpn) & |
838 | MLX4_CQE_VLAN_PRESENT_MASK) && | |
839 | (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) | |
86a9bad3 | 840 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid)); |
f1b553fb | 841 | |
ec693d47 AV |
842 | if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) { |
843 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
844 | mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb), | |
845 | timestamp); | |
846 | } | |
847 | ||
8b80cda5 | 848 | skb_mark_napi_id(skb, &cq->napi); |
9e77a2b8 | 849 | |
e6a76758 ED |
850 | if (!mlx4_en_cq_busy_polling(cq)) |
851 | napi_gro_receive(&cq->napi, skb); | |
852 | else | |
853 | netif_receive_skb(skb); | |
c27a02cd | 854 | |
c27a02cd | 855 | next: |
4cce66cd TLSC |
856 | for (nr = 0; nr < priv->num_frags; nr++) |
857 | mlx4_en_free_frag(priv, frags, nr); | |
858 | ||
c27a02cd YP |
859 | ++cq->mcq.cons_index; |
860 | index = (cq->mcq.cons_index) & ring->size_mask; | |
b1b6b4da | 861 | cqe = mlx4_en_get_cqe(cq->buf, index, priv->cqe_size) + factor; |
f1d29a3f | 862 | if (++polled == budget) |
c27a02cd | 863 | goto out; |
c27a02cd YP |
864 | } |
865 | ||
c27a02cd YP |
866 | out: |
867 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
868 | mlx4_cq_set_ci(&cq->mcq); | |
869 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
870 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 871 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
872 | mlx4_en_update_rx_prod_db(ring); |
873 | return polled; | |
874 | } | |
875 | ||
876 | ||
877 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
878 | { | |
879 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
880 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
881 | ||
882 | if (priv->port_up) | |
288379f0 | 883 | napi_schedule(&cq->napi); |
c27a02cd YP |
884 | else |
885 | mlx4_en_arm_cq(priv, cq); | |
886 | } | |
887 | ||
888 | /* Rx CQ polling - called by NAPI */ | |
889 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
890 | { | |
891 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
892 | struct net_device *dev = cq->dev; | |
893 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
894 | int done; | |
895 | ||
9e77a2b8 AV |
896 | if (!mlx4_en_cq_lock_napi(cq)) |
897 | return budget; | |
898 | ||
c27a02cd YP |
899 | done = mlx4_en_process_rx_cq(dev, cq, budget); |
900 | ||
9e77a2b8 AV |
901 | mlx4_en_cq_unlock_napi(cq); |
902 | ||
c27a02cd | 903 | /* If we used up all the quota - we're probably not done yet... */ |
2eacc23c | 904 | if (done == budget) { |
35f6f453 AV |
905 | int cpu_curr; |
906 | const struct cpumask *aff; | |
907 | ||
c27a02cd | 908 | INC_PERF_COUNTER(priv->pstats.napi_quota); |
35f6f453 AV |
909 | |
910 | cpu_curr = smp_processor_id(); | |
911 | aff = irq_desc_get_irq_data(cq->irq_desc)->affinity; | |
912 | ||
913 | if (unlikely(!cpumask_test_cpu(cpu_curr, aff))) { | |
914 | /* Current cpu is not according to smp_irq_affinity - | |
915 | * probably affinity changed. need to stop this NAPI | |
916 | * poll, and restart it on the right CPU | |
917 | */ | |
2eacc23c YA |
918 | napi_complete(napi); |
919 | mlx4_en_arm_cq(priv, cq); | |
920 | return 0; | |
921 | } | |
922 | } else { | |
c27a02cd | 923 | /* Done for now */ |
288379f0 | 924 | napi_complete(napi); |
c27a02cd YP |
925 | mlx4_en_arm_cq(priv, cq); |
926 | } | |
927 | return done; | |
928 | } | |
929 | ||
51151a16 | 930 | static const int frag_sizes[] = { |
c27a02cd YP |
931 | FRAG_SZ0, |
932 | FRAG_SZ1, | |
933 | FRAG_SZ2, | |
934 | FRAG_SZ3 | |
935 | }; | |
936 | ||
937 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
938 | { | |
939 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
d5b8dff0 | 940 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN; |
c27a02cd YP |
941 | int buf_size = 0; |
942 | int i = 0; | |
943 | ||
944 | while (buf_size < eff_mtu) { | |
945 | priv->frag_info[i].frag_size = | |
946 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
947 | frag_sizes[i] : eff_mtu - buf_size; | |
948 | priv->frag_info[i].frag_prefix_size = buf_size; | |
949 | if (!i) { | |
950 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
951 | priv->frag_info[i].frag_stride = | |
952 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
953 | } else { | |
954 | priv->frag_info[i].frag_align = 0; | |
955 | priv->frag_info[i].frag_stride = | |
956 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
957 | } | |
c27a02cd YP |
958 | buf_size += priv->frag_info[i].frag_size; |
959 | i++; | |
960 | } | |
961 | ||
962 | priv->num_frags = i; | |
963 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 964 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 965 | |
1a91de28 JP |
966 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d num_frags:%d):\n", |
967 | eff_mtu, priv->num_frags); | |
c27a02cd | 968 | for (i = 0; i < priv->num_frags; i++) { |
51151a16 ED |
969 | en_err(priv, |
970 | " frag:%d - size:%d prefix:%d align:%d stride:%d\n", | |
971 | i, | |
972 | priv->frag_info[i].frag_size, | |
973 | priv->frag_info[i].frag_prefix_size, | |
974 | priv->frag_info[i].frag_align, | |
975 | priv->frag_info[i].frag_stride); | |
c27a02cd YP |
976 | } |
977 | } | |
978 | ||
979 | /* RSS related functions */ | |
980 | ||
9f519f68 YP |
981 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
982 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
983 | enum mlx4_qp_state *state, |
984 | struct mlx4_qp *qp) | |
985 | { | |
986 | struct mlx4_en_dev *mdev = priv->mdev; | |
987 | struct mlx4_qp_context *context; | |
988 | int err = 0; | |
989 | ||
14f8dc49 JP |
990 | context = kmalloc(sizeof(*context), GFP_KERNEL); |
991 | if (!context) | |
c27a02cd | 992 | return -ENOMEM; |
c27a02cd | 993 | |
40f2287b | 994 | err = mlx4_qp_alloc(mdev->dev, qpn, qp, GFP_KERNEL); |
c27a02cd | 995 | if (err) { |
453a6082 | 996 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 997 | goto out; |
c27a02cd YP |
998 | } |
999 | qp->event = mlx4_en_sqp_event; | |
1000 | ||
1001 | memset(context, 0, sizeof *context); | |
00d7d7bc | 1002 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 1003 | qpn, ring->cqn, -1, context); |
9f519f68 | 1004 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 1005 | |
f3a9d1f2 | 1006 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 1007 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 1008 | context->param3 |= cpu_to_be32(1 << 29); |
4a5f4dd8 YP |
1009 | ring->fcs_del = ETH_FCS_LEN; |
1010 | } else | |
1011 | ring->fcs_del = 0; | |
f3a9d1f2 | 1012 | |
9f519f68 | 1013 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
1014 | if (err) { |
1015 | mlx4_qp_remove(mdev->dev, qp); | |
1016 | mlx4_qp_free(mdev->dev, qp); | |
1017 | } | |
9f519f68 | 1018 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
1019 | out: |
1020 | kfree(context); | |
1021 | return err; | |
1022 | } | |
1023 | ||
cabdc8ee HHZ |
1024 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
1025 | { | |
1026 | int err; | |
1027 | u32 qpn; | |
1028 | ||
1029 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); | |
1030 | if (err) { | |
1031 | en_err(priv, "Failed reserving drop qpn\n"); | |
1032 | return err; | |
1033 | } | |
40f2287b | 1034 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp, GFP_KERNEL); |
cabdc8ee HHZ |
1035 | if (err) { |
1036 | en_err(priv, "Failed allocating drop qp\n"); | |
1037 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1038 | return err; | |
1039 | } | |
1040 | ||
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
1045 | { | |
1046 | u32 qpn; | |
1047 | ||
1048 | qpn = priv->drop_qp.qpn; | |
1049 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
1050 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
1051 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
1052 | } | |
1053 | ||
c27a02cd YP |
1054 | /* Allocate rx qp's and configure them according to rss map */ |
1055 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
1056 | { | |
1057 | struct mlx4_en_dev *mdev = priv->mdev; | |
1058 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1059 | struct mlx4_qp_context context; | |
876f6e67 | 1060 | struct mlx4_rss_context *rss_context; |
93d3e367 | 1061 | int rss_rings; |
c27a02cd | 1062 | void *ptr; |
876f6e67 | 1063 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 1064 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 1065 | int i, qpn; |
c27a02cd YP |
1066 | int err = 0; |
1067 | int good_qps = 0; | |
ad86107f YP |
1068 | static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, |
1069 | 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, | |
1070 | 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; | |
c27a02cd | 1071 | |
453a6082 | 1072 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
1073 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
1074 | priv->rx_ring_num, | |
1075 | &rss_map->base_qpn); | |
c27a02cd | 1076 | if (err) { |
b6b912e0 | 1077 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
1078 | return err; |
1079 | } | |
1080 | ||
b6b912e0 | 1081 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 1082 | qpn = rss_map->base_qpn + i; |
41d942d5 | 1083 | err = mlx4_en_config_rss_qp(priv, qpn, priv->rx_ring[i], |
c27a02cd YP |
1084 | &rss_map->state[i], |
1085 | &rss_map->qps[i]); | |
1086 | if (err) | |
1087 | goto rss_err; | |
1088 | ||
1089 | ++good_qps; | |
1090 | } | |
1091 | ||
1092 | /* Configure RSS indirection qp */ | |
40f2287b | 1093 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp, GFP_KERNEL); |
c27a02cd | 1094 | if (err) { |
453a6082 | 1095 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 1096 | goto rss_err; |
c27a02cd YP |
1097 | } |
1098 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
1099 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
41d942d5 | 1100 | priv->rx_ring[0]->cqn, -1, &context); |
c27a02cd | 1101 | |
93d3e367 YP |
1102 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
1103 | rss_rings = priv->rx_ring_num; | |
1104 | else | |
1105 | rss_rings = priv->prof->rss_rings; | |
1106 | ||
876f6e67 OG |
1107 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
1108 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 1109 | rss_context = ptr; |
93d3e367 | 1110 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 1111 | (rss_map->base_qpn)); |
89efea25 | 1112 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
1113 | if (priv->mdev->profile.udp_rss) { |
1114 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
1115 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
1116 | } | |
837052d0 OG |
1117 | |
1118 | if (mdev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) { | |
1119 | en_info(priv, "Setting RSS context tunnel type to RSS on inner headers\n"); | |
1120 | rss_mask |= MLX4_RSS_BY_INNER_HEADERS; | |
1121 | } | |
1122 | ||
0533943c | 1123 | rss_context->flags = rss_mask; |
876f6e67 | 1124 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
ad86107f | 1125 | for (i = 0; i < 10; i++) |
39b2c4eb | 1126 | rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); |
c27a02cd YP |
1127 | |
1128 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
1129 | &rss_map->indir_qp, &rss_map->indir_state); | |
1130 | if (err) | |
1131 | goto indir_err; | |
1132 | ||
1133 | return 0; | |
1134 | ||
1135 | indir_err: | |
1136 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1137 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1138 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1139 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
1140 | rss_err: |
1141 | for (i = 0; i < good_qps; i++) { | |
1142 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
1143 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1144 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1145 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1146 | } | |
b6b912e0 | 1147 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
1148 | return err; |
1149 | } | |
1150 | ||
1151 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
1152 | { | |
1153 | struct mlx4_en_dev *mdev = priv->mdev; | |
1154 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1155 | int i; | |
1156 | ||
1157 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1158 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1159 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1160 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1161 | |
b6b912e0 | 1162 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1163 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1164 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1165 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1166 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1167 | } | |
b6b912e0 | 1168 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1169 | } |