net/mlx4_en: Add accelerated RFS support
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / en_rx.c
CommitLineData
c27a02cd
YP
1/*
2 * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34#include <linux/mlx4/cq.h>
5a0e3ad6 35#include <linux/slab.h>
c27a02cd
YP
36#include <linux/mlx4/qp.h>
37#include <linux/skbuff.h>
38#include <linux/if_ether.h>
39#include <linux/if_vlan.h>
40#include <linux/vmalloc.h>
41
42#include "mlx4_en.h"
43
c27a02cd 44
c27a02cd
YP
45static int mlx4_en_alloc_frag(struct mlx4_en_priv *priv,
46 struct mlx4_en_rx_desc *rx_desc,
311761c8 47 struct page_frag *skb_frags,
c27a02cd
YP
48 struct mlx4_en_rx_alloc *ring_alloc,
49 int i)
50{
c27a02cd
YP
51 struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
52 struct mlx4_en_rx_alloc *page_alloc = &ring_alloc[i];
53 struct page *page;
54 dma_addr_t dma;
55
56 if (page_alloc->offset == frag_info->last_offset) {
57 /* Allocate new page */
58 page = alloc_pages(GFP_ATOMIC | __GFP_COMP, MLX4_EN_ALLOC_ORDER);
59 if (!page)
60 return -ENOMEM;
61
62 skb_frags[i].page = page_alloc->page;
311761c8 63 skb_frags[i].offset = page_alloc->offset;
c27a02cd
YP
64 page_alloc->page = page;
65 page_alloc->offset = frag_info->frag_align;
66 } else {
67 page = page_alloc->page;
68 get_page(page);
69
70 skb_frags[i].page = page;
311761c8 71 skb_frags[i].offset = page_alloc->offset;
c27a02cd
YP
72 page_alloc->offset += frag_info->frag_stride;
73 }
ebf8c9aa 74 dma = dma_map_single(priv->ddev, page_address(skb_frags[i].page) +
311761c8 75 skb_frags[i].offset, frag_info->frag_size,
c27a02cd
YP
76 PCI_DMA_FROMDEVICE);
77 rx_desc->data[i].addr = cpu_to_be64(dma);
78 return 0;
79}
80
81static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
82 struct mlx4_en_rx_ring *ring)
83{
84 struct mlx4_en_rx_alloc *page_alloc;
85 int i;
86
87 for (i = 0; i < priv->num_frags; i++) {
88 page_alloc = &ring->page_alloc[i];
89 page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP,
90 MLX4_EN_ALLOC_ORDER);
91 if (!page_alloc->page)
92 goto out;
93
94 page_alloc->offset = priv->frag_info[i].frag_align;
453a6082
YP
95 en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n",
96 i, page_alloc->page);
c27a02cd
YP
97 }
98 return 0;
99
100out:
101 while (i--) {
102 page_alloc = &ring->page_alloc[i];
103 put_page(page_alloc->page);
104 page_alloc->page = NULL;
105 }
106 return -ENOMEM;
107}
108
109static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
110 struct mlx4_en_rx_ring *ring)
111{
112 struct mlx4_en_rx_alloc *page_alloc;
113 int i;
114
115 for (i = 0; i < priv->num_frags; i++) {
116 page_alloc = &ring->page_alloc[i];
453a6082
YP
117 en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
118 i, page_count(page_alloc->page));
c27a02cd
YP
119
120 put_page(page_alloc->page);
121 page_alloc->page = NULL;
122 }
123}
124
125
126static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
127 struct mlx4_en_rx_ring *ring, int index)
128{
129 struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
130 struct skb_frag_struct *skb_frags = ring->rx_info +
131 (index << priv->log_rx_info);
132 int possible_frags;
133 int i;
134
c27a02cd
YP
135 /* Set size and memtype fields */
136 for (i = 0; i < priv->num_frags; i++) {
9e903e08 137 skb_frag_size_set(&skb_frags[i], priv->frag_info[i].frag_size);
c27a02cd
YP
138 rx_desc->data[i].byte_count =
139 cpu_to_be32(priv->frag_info[i].frag_size);
140 rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
141 }
142
143 /* If the number of used fragments does not fill up the ring stride,
144 * remaining (unused) fragments must be padded with null address/size
145 * and a special memory key */
146 possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
147 for (i = priv->num_frags; i < possible_frags; i++) {
148 rx_desc->data[i].byte_count = 0;
149 rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
150 rx_desc->data[i].addr = 0;
151 }
152}
153
154
155static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
156 struct mlx4_en_rx_ring *ring, int index)
157{
158 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
311761c8
IC
159 struct page_frag *skb_frags = ring->rx_info +
160 (index << priv->log_rx_info);
c27a02cd
YP
161 int i;
162
163 for (i = 0; i < priv->num_frags; i++)
164 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, ring->page_alloc, i))
165 goto err;
166
167 return 0;
168
169err:
7e2eb99c
TLSC
170 while (i--) {
171 dma_addr_t dma = be64_to_cpu(rx_desc->data[i].addr);
172 pci_unmap_single(priv->mdev->pdev, dma, skb_frags[i].size,
173 PCI_DMA_FROMDEVICE);
c27a02cd 174 put_page(skb_frags[i].page);
7e2eb99c 175 }
c27a02cd
YP
176 return -ENOMEM;
177}
178
179static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
180{
181 *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
182}
183
38aab07c
YP
184static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
185 struct mlx4_en_rx_ring *ring,
186 int index)
187{
311761c8 188 struct page_frag *skb_frags;
38aab07c
YP
189 struct mlx4_en_rx_desc *rx_desc = ring->buf + (index << ring->log_stride);
190 dma_addr_t dma;
191 int nr;
192
193 skb_frags = ring->rx_info + (index << priv->log_rx_info);
194 for (nr = 0; nr < priv->num_frags; nr++) {
453a6082 195 en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
38aab07c
YP
196 dma = be64_to_cpu(rx_desc->data[nr].addr);
197
af901ca1 198 en_dbg(DRV, priv, "Unmapping buffer at dma:0x%llx\n", (u64) dma);
ebf8c9aa 199 dma_unmap_single(priv->ddev, dma, skb_frags[nr].size,
38aab07c
YP
200 PCI_DMA_FROMDEVICE);
201 put_page(skb_frags[nr].page);
202 }
203}
204
c27a02cd
YP
205static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
206{
c27a02cd
YP
207 struct mlx4_en_rx_ring *ring;
208 int ring_ind;
209 int buf_ind;
38aab07c 210 int new_size;
c27a02cd
YP
211
212 for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
213 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
214 ring = &priv->rx_ring[ring_ind];
215
216 if (mlx4_en_prepare_rx_desc(priv, ring,
217 ring->actual_size)) {
218 if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
453a6082
YP
219 en_err(priv, "Failed to allocate "
220 "enough rx buffers\n");
c27a02cd
YP
221 return -ENOMEM;
222 } else {
38aab07c 223 new_size = rounddown_pow_of_two(ring->actual_size);
453a6082
YP
224 en_warn(priv, "Only %d buffers allocated "
225 "reducing ring size to %d",
226 ring->actual_size, new_size);
38aab07c 227 goto reduce_rings;
c27a02cd
YP
228 }
229 }
230 ring->actual_size++;
231 ring->prod++;
232 }
233 }
38aab07c
YP
234 return 0;
235
236reduce_rings:
237 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
238 ring = &priv->rx_ring[ring_ind];
239 while (ring->actual_size > new_size) {
240 ring->actual_size--;
241 ring->prod--;
242 mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
243 }
38aab07c
YP
244 }
245
c27a02cd
YP
246 return 0;
247}
248
c27a02cd
YP
249static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
250 struct mlx4_en_rx_ring *ring)
251{
c27a02cd 252 int index;
c27a02cd 253
453a6082
YP
254 en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
255 ring->cons, ring->prod);
c27a02cd
YP
256
257 /* Unmap and free Rx buffers */
38aab07c 258 BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
c27a02cd
YP
259 while (ring->cons != ring->prod) {
260 index = ring->cons & ring->size_mask;
453a6082 261 en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
38aab07c 262 mlx4_en_free_rx_desc(priv, ring, index);
c27a02cd
YP
263 ++ring->cons;
264 }
265}
266
c27a02cd
YP
267int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
268 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
269{
270 struct mlx4_en_dev *mdev = priv->mdev;
271 int err;
272 int tmp;
273
c27a02cd
YP
274
275 ring->prod = 0;
276 ring->cons = 0;
277 ring->size = size;
278 ring->size_mask = size - 1;
279 ring->stride = stride;
280 ring->log_stride = ffs(ring->stride) - 1;
9f519f68 281 ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
c27a02cd
YP
282
283 tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
284 sizeof(struct skb_frag_struct));
285 ring->rx_info = vmalloc(tmp);
e404decb 286 if (!ring->rx_info)
c27a02cd 287 return -ENOMEM;
e404decb 288
453a6082 289 en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
c27a02cd
YP
290 ring->rx_info, tmp);
291
292 err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
293 ring->buf_size, 2 * PAGE_SIZE);
294 if (err)
295 goto err_ring;
296
297 err = mlx4_en_map_buffer(&ring->wqres.buf);
298 if (err) {
453a6082 299 en_err(priv, "Failed to map RX buffer\n");
c27a02cd
YP
300 goto err_hwq;
301 }
302 ring->buf = ring->wqres.buf.direct.buf;
303
c27a02cd
YP
304 return 0;
305
c27a02cd
YP
306err_hwq:
307 mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
308err_ring:
309 vfree(ring->rx_info);
310 ring->rx_info = NULL;
311 return err;
312}
313
314int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
315{
c27a02cd
YP
316 struct mlx4_en_rx_ring *ring;
317 int i;
318 int ring_ind;
319 int err;
320 int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
321 DS_SIZE * priv->num_frags);
c27a02cd
YP
322
323 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
324 ring = &priv->rx_ring[ring_ind];
325
326 ring->prod = 0;
327 ring->cons = 0;
328 ring->actual_size = 0;
329 ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
330
331 ring->stride = stride;
9f519f68
YP
332 if (ring->stride <= TXBB_SIZE)
333 ring->buf += TXBB_SIZE;
334
c27a02cd
YP
335 ring->log_stride = ffs(ring->stride) - 1;
336 ring->buf_size = ring->size * ring->stride;
337
338 memset(ring->buf, 0, ring->buf_size);
339 mlx4_en_update_rx_prod_db(ring);
340
341 /* Initailize all descriptors */
342 for (i = 0; i < ring->size; i++)
343 mlx4_en_init_rx_desc(priv, ring, i);
344
345 /* Initialize page allocators */
346 err = mlx4_en_init_allocator(priv, ring);
347 if (err) {
453a6082 348 en_err(priv, "Failed initializing ring allocator\n");
60b1809f
YP
349 if (ring->stride <= TXBB_SIZE)
350 ring->buf -= TXBB_SIZE;
9a4f92a6
YP
351 ring_ind--;
352 goto err_allocator;
c27a02cd 353 }
c27a02cd 354 }
b58515be
IM
355 err = mlx4_en_fill_rx_buffers(priv);
356 if (err)
c27a02cd
YP
357 goto err_buffers;
358
359 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
360 ring = &priv->rx_ring[ring_ind];
361
00d7d7bc 362 ring->size_mask = ring->actual_size - 1;
c27a02cd 363 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP
364 }
365
366 return 0;
367
c27a02cd
YP
368err_buffers:
369 for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
370 mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
371
372 ring_ind = priv->rx_ring_num - 1;
373err_allocator:
374 while (ring_ind >= 0) {
60b1809f
YP
375 if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
376 priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
c27a02cd
YP
377 mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
378 ring_ind--;
379 }
380 return err;
381}
382
383void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
68355f71 384 struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
c27a02cd
YP
385{
386 struct mlx4_en_dev *mdev = priv->mdev;
387
c27a02cd 388 mlx4_en_unmap_buffer(&ring->wqres.buf);
68355f71 389 mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
c27a02cd
YP
390 vfree(ring->rx_info);
391 ring->rx_info = NULL;
1eb8c695
AV
392#ifdef CONFIG_RFS_ACCEL
393 mlx4_en_cleanup_filters(priv, ring);
394#endif
c27a02cd
YP
395}
396
397void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
398 struct mlx4_en_rx_ring *ring)
399{
c27a02cd 400 mlx4_en_free_rx_buf(priv, ring);
9f519f68
YP
401 if (ring->stride <= TXBB_SIZE)
402 ring->buf -= TXBB_SIZE;
c27a02cd
YP
403 mlx4_en_destroy_allocator(priv, ring);
404}
405
406
407/* Unmap a completed descriptor and free unused pages */
408static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
409 struct mlx4_en_rx_desc *rx_desc,
311761c8 410 struct page_frag *skb_frags,
90278c9f 411 struct sk_buff *skb,
c27a02cd
YP
412 struct mlx4_en_rx_alloc *page_alloc,
413 int length)
414{
90278c9f 415 struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
c27a02cd
YP
416 struct mlx4_en_frag_info *frag_info;
417 int nr;
418 dma_addr_t dma;
419
420 /* Collect used fragments while replacing them in the HW descirptors */
421 for (nr = 0; nr < priv->num_frags; nr++) {
422 frag_info = &priv->frag_info[nr];
423 if (length <= frag_info->frag_prefix_size)
424 break;
425
426 /* Save page reference in skb */
311761c8
IC
427 __skb_frag_set_page(&skb_frags_rx[nr], skb_frags[nr].page);
428 skb_frag_size_set(&skb_frags_rx[nr], skb_frags[nr].size);
429 skb_frags_rx[nr].page_offset = skb_frags[nr].offset;
90278c9f 430 skb->truesize += frag_info->frag_stride;
c27a02cd
YP
431 dma = be64_to_cpu(rx_desc->data[nr].addr);
432
433 /* Allocate a replacement page */
434 if (mlx4_en_alloc_frag(priv, rx_desc, skb_frags, page_alloc, nr))
435 goto fail;
436
437 /* Unmap buffer */
ebf8c9aa 438 dma_unmap_single(priv->ddev, dma, skb_frag_size(&skb_frags_rx[nr]),
c27a02cd
YP
439 PCI_DMA_FROMDEVICE);
440 }
441 /* Adjust size of last fragment to match actual length */
973507cb 442 if (nr > 0)
9e903e08
ED
443 skb_frag_size_set(&skb_frags_rx[nr - 1],
444 length - priv->frag_info[nr - 1].frag_prefix_size);
c27a02cd
YP
445 return nr;
446
447fail:
448 /* Drop all accumulated fragments (which have already been replaced in
449 * the descriptor) of this packet; remaining fragments are reused... */
450 while (nr > 0) {
451 nr--;
311761c8 452 __skb_frag_unref(&skb_frags_rx[nr]);
c27a02cd
YP
453 }
454 return 0;
455}
456
457
458static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
459 struct mlx4_en_rx_desc *rx_desc,
311761c8 460 struct page_frag *skb_frags,
c27a02cd
YP
461 struct mlx4_en_rx_alloc *page_alloc,
462 unsigned int length)
463{
c27a02cd
YP
464 struct sk_buff *skb;
465 void *va;
466 int used_frags;
467 dma_addr_t dma;
468
c056b734 469 skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
c27a02cd 470 if (!skb) {
453a6082 471 en_dbg(RX_ERR, priv, "Failed allocating skb\n");
c27a02cd
YP
472 return NULL;
473 }
c27a02cd
YP
474 skb_reserve(skb, NET_IP_ALIGN);
475 skb->len = length;
c27a02cd
YP
476
477 /* Get pointer to first fragment so we could copy the headers into the
478 * (linear part of the) skb */
311761c8 479 va = page_address(skb_frags[0].page) + skb_frags[0].offset;
c27a02cd
YP
480
481 if (length <= SMALL_PACKET_SIZE) {
482 /* We are copying all relevant data to the skb - temporarily
483 * synch buffers for the copy */
484 dma = be64_to_cpu(rx_desc->data[0].addr);
ebf8c9aa 485 dma_sync_single_for_cpu(priv->ddev, dma, length,
e4fc8560 486 DMA_FROM_DEVICE);
c27a02cd 487 skb_copy_to_linear_data(skb, va, length);
ebf8c9aa 488 dma_sync_single_for_device(priv->ddev, dma, length,
e4fc8560 489 DMA_FROM_DEVICE);
c27a02cd
YP
490 skb->tail += length;
491 } else {
492
493 /* Move relevant fragments to skb */
494 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, skb_frags,
90278c9f 495 skb, page_alloc, length);
785a0982
YP
496 if (unlikely(!used_frags)) {
497 kfree_skb(skb);
498 return NULL;
499 }
c27a02cd
YP
500 skb_shinfo(skb)->nr_frags = used_frags;
501
502 /* Copy headers into the skb linear buffer */
503 memcpy(skb->data, va, HEADER_COPY_SIZE);
504 skb->tail += HEADER_COPY_SIZE;
505
506 /* Skip headers in first fragment */
507 skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
508
509 /* Adjust size of first fragment */
9e903e08 510 skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
c27a02cd
YP
511 skb->data_len = length - HEADER_COPY_SIZE;
512 }
513 return skb;
514}
515
e7c1c2c4
YP
516static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
517{
518 int i;
519 int offset = ETH_HLEN;
520
521 for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
522 if (*(skb->data + offset) != (unsigned char) (i & 0xff))
523 goto out_loopback;
524 }
525 /* Loopback found */
526 priv->loopback_ok = 1;
527
528out_loopback:
529 dev_kfree_skb_any(skb);
530}
c27a02cd
YP
531
532int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
533{
534 struct mlx4_en_priv *priv = netdev_priv(dev);
c27a02cd
YP
535 struct mlx4_cqe *cqe;
536 struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
311761c8 537 struct page_frag *skb_frags;
c27a02cd
YP
538 struct mlx4_en_rx_desc *rx_desc;
539 struct sk_buff *skb;
540 int index;
541 int nr;
542 unsigned int length;
543 int polled = 0;
544 int ip_summed;
5b4c4d36
EE
545 struct ethhdr *ethh;
546 u64 s_mac;
c27a02cd
YP
547
548 if (!priv->port_up)
549 return 0;
550
551 /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
552 * descriptor offset can be deduced from the CQE index instead of
553 * reading 'cqe->index' */
554 index = cq->mcq.cons_index & ring->size_mask;
555 cqe = &cq->buf[index];
556
557 /* Process all completed CQEs */
558 while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
559 cq->mcq.cons_index & cq->size)) {
560
561 skb_frags = ring->rx_info + (index << priv->log_rx_info);
562 rx_desc = ring->buf + (index << ring->log_stride);
563
564 /*
565 * make sure we read the CQE after we read the ownership bit
566 */
567 rmb();
568
569 /* Drop packet on bad receive or bad checksum */
570 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
571 MLX4_CQE_OPCODE_ERROR)) {
453a6082 572 en_err(priv, "CQE completed in error - vendor "
c27a02cd
YP
573 "syndrom:%d syndrom:%d\n",
574 ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
575 ((struct mlx4_err_cqe *) cqe)->syndrome);
576 goto next;
577 }
578 if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
453a6082 579 en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
c27a02cd
YP
580 goto next;
581 }
582
5b4c4d36
EE
583 /* Get pointer to first fragment since we haven't skb yet and
584 * cast it to ethhdr struct */
585 ethh = (struct ethhdr *)(page_address(skb_frags[0].page) +
586 skb_frags[0].offset);
587 s_mac = mlx4_en_mac_to_u64(ethh->h_source);
588
589 /* If source MAC is equal to our own MAC and not performing
590 * the selftest or flb disabled - drop the packet */
591 if (s_mac == priv->mac &&
592 (!(dev->features & NETIF_F_LOOPBACK) ||
593 !priv->validate_loopback))
594 goto next;
595
c27a02cd
YP
596 /*
597 * Packet is OK - process it.
598 */
599 length = be32_to_cpu(cqe->byte_cnt);
4a5f4dd8 600 length -= ring->fcs_del;
c27a02cd
YP
601 ring->bytes += length;
602 ring->packets++;
603
c8c64cff 604 if (likely(dev->features & NETIF_F_RXCSUM)) {
c27a02cd
YP
605 if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
606 (cqe->checksum == cpu_to_be16(0xffff))) {
ad04378c 607 ring->csum_ok++;
c27a02cd
YP
608 /* This packet is eligible for LRO if it is:
609 * - DIX Ethernet (type interpretation)
610 * - TCP/IP (v4)
611 * - without IP options
612 * - not an IP fragment */
fa37a958
YP
613 if (dev->features & NETIF_F_GRO) {
614 struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
ebc872c7
YP
615 if (!gro_skb)
616 goto next;
c27a02cd
YP
617
618 nr = mlx4_en_complete_rx_desc(
619 priv, rx_desc,
90278c9f 620 skb_frags, gro_skb,
c27a02cd
YP
621 ring->page_alloc, length);
622 if (!nr)
623 goto next;
624
fa37a958
YP
625 skb_shinfo(gro_skb)->nr_frags = nr;
626 gro_skb->len = length;
627 gro_skb->data_len = length;
fa37a958
YP
628 gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
629
f1b553fb
JP
630 if (cqe->vlan_my_qpn &
631 cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) {
632 u16 vid = be16_to_cpu(cqe->sl_vid);
633
634 __vlan_hwaccel_put_tag(gro_skb, vid);
635 }
636
ad86107f
YP
637 if (dev->features & NETIF_F_RXHASH)
638 gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
639
3b61008d 640 skb_record_rx_queue(gro_skb, cq->ring);
f1b553fb 641 napi_gro_frags(&cq->napi);
c27a02cd
YP
642
643 goto next;
644 }
645
646 /* LRO not possible, complete processing here */
647 ip_summed = CHECKSUM_UNNECESSARY;
c27a02cd
YP
648 } else {
649 ip_summed = CHECKSUM_NONE;
ad04378c 650 ring->csum_none++;
c27a02cd
YP
651 }
652 } else {
653 ip_summed = CHECKSUM_NONE;
ad04378c 654 ring->csum_none++;
c27a02cd
YP
655 }
656
657 skb = mlx4_en_rx_skb(priv, rx_desc, skb_frags,
658 ring->page_alloc, length);
659 if (!skb) {
660 priv->stats.rx_dropped++;
661 goto next;
662 }
663
e7c1c2c4
YP
664 if (unlikely(priv->validate_loopback)) {
665 validate_loopback(priv, skb);
666 goto next;
667 }
668
c27a02cd
YP
669 skb->ip_summed = ip_summed;
670 skb->protocol = eth_type_trans(skb, dev);
0c8dfc83 671 skb_record_rx_queue(skb, cq->ring);
c27a02cd 672
ad86107f
YP
673 if (dev->features & NETIF_F_RXHASH)
674 skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
675
f1b553fb
JP
676 if (be32_to_cpu(cqe->vlan_my_qpn) &
677 MLX4_CQE_VLAN_PRESENT_MASK)
678 __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid));
679
c27a02cd 680 /* Push it up the stack */
f1b553fb 681 netif_receive_skb(skb);
c27a02cd 682
c27a02cd
YP
683next:
684 ++cq->mcq.cons_index;
685 index = (cq->mcq.cons_index) & ring->size_mask;
686 cqe = &cq->buf[index];
687 if (++polled == budget) {
688 /* We are here because we reached the NAPI budget -
689 * flush only pending LRO sessions */
c27a02cd
YP
690 goto out;
691 }
692 }
693
c27a02cd
YP
694out:
695 AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
696 mlx4_cq_set_ci(&cq->mcq);
697 wmb(); /* ensure HW sees CQ consumer before we post new buffers */
698 ring->cons = cq->mcq.cons_index;
699 ring->prod += polled; /* Polled descriptors were realocated in place */
c27a02cd
YP
700 mlx4_en_update_rx_prod_db(ring);
701 return polled;
702}
703
704
705void mlx4_en_rx_irq(struct mlx4_cq *mcq)
706{
707 struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
708 struct mlx4_en_priv *priv = netdev_priv(cq->dev);
709
710 if (priv->port_up)
288379f0 711 napi_schedule(&cq->napi);
c27a02cd
YP
712 else
713 mlx4_en_arm_cq(priv, cq);
714}
715
716/* Rx CQ polling - called by NAPI */
717int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
718{
719 struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
720 struct net_device *dev = cq->dev;
721 struct mlx4_en_priv *priv = netdev_priv(dev);
722 int done;
723
724 done = mlx4_en_process_rx_cq(dev, cq, budget);
725
726 /* If we used up all the quota - we're probably not done yet... */
727 if (done == budget)
728 INC_PERF_COUNTER(priv->pstats.napi_quota);
729 else {
730 /* Done for now */
288379f0 731 napi_complete(napi);
c27a02cd
YP
732 mlx4_en_arm_cq(priv, cq);
733 }
734 return done;
735}
736
737
25985edc 738/* Calculate the last offset position that accommodates a full fragment
c27a02cd
YP
739 * (assuming fagment size = stride-align) */
740static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align)
741{
742 u16 res = MLX4_EN_ALLOC_SIZE % stride;
743 u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align;
744
453a6082 745 en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d "
c27a02cd
YP
746 "res:%d offset:%d\n", stride, align, res, offset);
747 return offset;
748}
749
750
751static int frag_sizes[] = {
752 FRAG_SZ0,
753 FRAG_SZ1,
754 FRAG_SZ2,
755 FRAG_SZ3
756};
757
758void mlx4_en_calc_rx_buf(struct net_device *dev)
759{
760 struct mlx4_en_priv *priv = netdev_priv(dev);
761 int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
762 int buf_size = 0;
763 int i = 0;
764
765 while (buf_size < eff_mtu) {
766 priv->frag_info[i].frag_size =
767 (eff_mtu > buf_size + frag_sizes[i]) ?
768 frag_sizes[i] : eff_mtu - buf_size;
769 priv->frag_info[i].frag_prefix_size = buf_size;
770 if (!i) {
771 priv->frag_info[i].frag_align = NET_IP_ALIGN;
772 priv->frag_info[i].frag_stride =
773 ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
774 } else {
775 priv->frag_info[i].frag_align = 0;
776 priv->frag_info[i].frag_stride =
777 ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
778 }
779 priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset(
780 priv, priv->frag_info[i].frag_stride,
781 priv->frag_info[i].frag_align);
782 buf_size += priv->frag_info[i].frag_size;
783 i++;
784 }
785
786 priv->num_frags = i;
787 priv->rx_skb_size = eff_mtu;
788 priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct skb_frag_struct));
789
453a6082 790 en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
c27a02cd
YP
791 "num_frags:%d):\n", eff_mtu, priv->num_frags);
792 for (i = 0; i < priv->num_frags; i++) {
453a6082 793 en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d "
c27a02cd
YP
794 "stride:%d last_offset:%d\n", i,
795 priv->frag_info[i].frag_size,
796 priv->frag_info[i].frag_prefix_size,
797 priv->frag_info[i].frag_align,
798 priv->frag_info[i].frag_stride,
799 priv->frag_info[i].last_offset);
800 }
801}
802
803/* RSS related functions */
804
9f519f68
YP
805static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
806 struct mlx4_en_rx_ring *ring,
c27a02cd
YP
807 enum mlx4_qp_state *state,
808 struct mlx4_qp *qp)
809{
810 struct mlx4_en_dev *mdev = priv->mdev;
811 struct mlx4_qp_context *context;
812 int err = 0;
813
814 context = kmalloc(sizeof *context , GFP_KERNEL);
815 if (!context) {
453a6082 816 en_err(priv, "Failed to allocate qp context\n");
c27a02cd
YP
817 return -ENOMEM;
818 }
819
820 err = mlx4_qp_alloc(mdev->dev, qpn, qp);
821 if (err) {
453a6082 822 en_err(priv, "Failed to allocate qp #%x\n", qpn);
c27a02cd 823 goto out;
c27a02cd
YP
824 }
825 qp->event = mlx4_en_sqp_event;
826
827 memset(context, 0, sizeof *context);
00d7d7bc 828 mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
0e98b523 829 qpn, ring->cqn, -1, context);
9f519f68 830 context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
c27a02cd 831
f3a9d1f2 832 /* Cancel FCS removal if FW allows */
4a5f4dd8 833 if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
f3a9d1f2 834 context->param3 |= cpu_to_be32(1 << 29);
4a5f4dd8
YP
835 ring->fcs_del = ETH_FCS_LEN;
836 } else
837 ring->fcs_del = 0;
f3a9d1f2 838
9f519f68 839 err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
c27a02cd
YP
840 if (err) {
841 mlx4_qp_remove(mdev->dev, qp);
842 mlx4_qp_free(mdev->dev, qp);
843 }
9f519f68 844 mlx4_en_update_rx_prod_db(ring);
c27a02cd
YP
845out:
846 kfree(context);
847 return err;
848}
849
cabdc8ee
HHZ
850int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
851{
852 int err;
853 u32 qpn;
854
855 err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
856 if (err) {
857 en_err(priv, "Failed reserving drop qpn\n");
858 return err;
859 }
860 err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
861 if (err) {
862 en_err(priv, "Failed allocating drop qp\n");
863 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
864 return err;
865 }
866
867 return 0;
868}
869
870void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
871{
872 u32 qpn;
873
874 qpn = priv->drop_qp.qpn;
875 mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
876 mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
877 mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
878}
879
c27a02cd
YP
880/* Allocate rx qp's and configure them according to rss map */
881int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
882{
883 struct mlx4_en_dev *mdev = priv->mdev;
884 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
885 struct mlx4_qp_context context;
876f6e67 886 struct mlx4_rss_context *rss_context;
93d3e367 887 int rss_rings;
c27a02cd 888 void *ptr;
876f6e67 889 u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
1202d460 890 MLX4_RSS_TCP_IPV6);
9f519f68 891 int i, qpn;
c27a02cd
YP
892 int err = 0;
893 int good_qps = 0;
ad86107f
YP
894 static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
895 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
896 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
c27a02cd 897
453a6082 898 en_dbg(DRV, priv, "Configuring rss steering\n");
b6b912e0
YP
899 err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
900 priv->rx_ring_num,
901 &rss_map->base_qpn);
c27a02cd 902 if (err) {
b6b912e0 903 en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
c27a02cd
YP
904 return err;
905 }
906
b6b912e0 907 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd 908 qpn = rss_map->base_qpn + i;
9f519f68 909 err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
c27a02cd
YP
910 &rss_map->state[i],
911 &rss_map->qps[i]);
912 if (err)
913 goto rss_err;
914
915 ++good_qps;
916 }
917
918 /* Configure RSS indirection qp */
c27a02cd
YP
919 err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
920 if (err) {
453a6082 921 en_err(priv, "Failed to allocate RSS indirection QP\n");
1679200f 922 goto rss_err;
c27a02cd
YP
923 }
924 rss_map->indir_qp.event = mlx4_en_sqp_event;
925 mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
0e98b523 926 priv->rx_ring[0].cqn, -1, &context);
c27a02cd 927
93d3e367
YP
928 if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
929 rss_rings = priv->rx_ring_num;
930 else
931 rss_rings = priv->prof->rss_rings;
932
876f6e67
OG
933 ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
934 + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
43d620c8 935 rss_context = ptr;
93d3e367 936 rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
c27a02cd 937 (rss_map->base_qpn));
89efea25 938 rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
1202d460
OG
939 if (priv->mdev->profile.udp_rss) {
940 rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
941 rss_context->base_qpn_udp = rss_context->default_qpn;
942 }
0533943c 943 rss_context->flags = rss_mask;
876f6e67 944 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
ad86107f 945 for (i = 0; i < 10; i++)
39b2c4eb 946 rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
c27a02cd
YP
947
948 err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
949 &rss_map->indir_qp, &rss_map->indir_state);
950 if (err)
951 goto indir_err;
952
953 return 0;
954
955indir_err:
956 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
957 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
958 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
959 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
c27a02cd
YP
960rss_err:
961 for (i = 0; i < good_qps; i++) {
962 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
963 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
964 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
965 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
966 }
b6b912e0 967 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP
968 return err;
969}
970
971void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
972{
973 struct mlx4_en_dev *mdev = priv->mdev;
974 struct mlx4_en_rss_map *rss_map = &priv->rss_map;
975 int i;
976
977 mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
978 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
979 mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
980 mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
c27a02cd 981
b6b912e0 982 for (i = 0; i < priv->rx_ring_num; i++) {
c27a02cd
YP
983 mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
984 MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
985 mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
986 mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
987 }
b6b912e0 988 mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
c27a02cd
YP
989}
990
991
992
993
994
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