Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 35 | #include <linux/slab.h> |
c27a02cd YP |
36 | #include <linux/mlx4/qp.h> |
37 | #include <linux/skbuff.h> | |
38 | #include <linux/if_ether.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
41 | ||
42 | #include "mlx4_en.h" | |
43 | ||
4cce66cd TLSC |
44 | static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv, |
45 | struct mlx4_en_rx_desc *rx_desc, | |
46 | struct mlx4_en_rx_alloc *frags, | |
47 | struct mlx4_en_rx_alloc *ring_alloc) | |
c27a02cd | 48 | { |
4cce66cd TLSC |
49 | struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS]; |
50 | struct mlx4_en_frag_info *frag_info; | |
c27a02cd YP |
51 | struct page *page; |
52 | dma_addr_t dma; | |
4cce66cd | 53 | int i; |
c27a02cd | 54 | |
4cce66cd TLSC |
55 | for (i = 0; i < priv->num_frags; i++) { |
56 | frag_info = &priv->frag_info[i]; | |
57 | if (ring_alloc[i].offset == frag_info->last_offset) { | |
58 | page = alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
59 | MLX4_EN_ALLOC_ORDER); | |
60 | if (!page) | |
61 | goto out; | |
62 | dma = dma_map_page(priv->ddev, page, 0, | |
63 | MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
64 | if (dma_mapping_error(priv->ddev, dma)) { | |
65 | put_page(page); | |
66 | goto out; | |
67 | } | |
68 | page_alloc[i].page = page; | |
69 | page_alloc[i].dma = dma; | |
70 | page_alloc[i].offset = frag_info->frag_align; | |
71 | } else { | |
72 | page_alloc[i].page = ring_alloc[i].page; | |
73 | get_page(ring_alloc[i].page); | |
74 | page_alloc[i].dma = ring_alloc[i].dma; | |
75 | page_alloc[i].offset = ring_alloc[i].offset + | |
76 | frag_info->frag_stride; | |
77 | } | |
78 | } | |
c27a02cd | 79 | |
4cce66cd TLSC |
80 | for (i = 0; i < priv->num_frags; i++) { |
81 | frags[i] = ring_alloc[i]; | |
82 | dma = ring_alloc[i].dma + ring_alloc[i].offset; | |
83 | ring_alloc[i] = page_alloc[i]; | |
84 | rx_desc->data[i].addr = cpu_to_be64(dma); | |
c27a02cd | 85 | } |
4cce66cd | 86 | |
c27a02cd | 87 | return 0; |
4cce66cd TLSC |
88 | |
89 | ||
90 | out: | |
91 | while (i--) { | |
92 | frag_info = &priv->frag_info[i]; | |
93 | if (ring_alloc[i].offset == frag_info->last_offset) | |
94 | dma_unmap_page(priv->ddev, page_alloc[i].dma, | |
95 | MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
96 | put_page(page_alloc[i].page); | |
97 | } | |
98 | return -ENOMEM; | |
99 | } | |
100 | ||
101 | static void mlx4_en_free_frag(struct mlx4_en_priv *priv, | |
102 | struct mlx4_en_rx_alloc *frags, | |
103 | int i) | |
104 | { | |
105 | struct mlx4_en_frag_info *frag_info = &priv->frag_info[i]; | |
106 | ||
107 | if (frags[i].offset == frag_info->last_offset) { | |
108 | dma_unmap_page(priv->ddev, frags[i].dma, MLX4_EN_ALLOC_SIZE, | |
109 | PCI_DMA_FROMDEVICE); | |
110 | } | |
111 | if (frags[i].page) | |
112 | put_page(frags[i].page); | |
c27a02cd YP |
113 | } |
114 | ||
115 | static int mlx4_en_init_allocator(struct mlx4_en_priv *priv, | |
116 | struct mlx4_en_rx_ring *ring) | |
117 | { | |
118 | struct mlx4_en_rx_alloc *page_alloc; | |
119 | int i; | |
120 | ||
121 | for (i = 0; i < priv->num_frags; i++) { | |
122 | page_alloc = &ring->page_alloc[i]; | |
123 | page_alloc->page = alloc_pages(GFP_ATOMIC | __GFP_COMP, | |
124 | MLX4_EN_ALLOC_ORDER); | |
125 | if (!page_alloc->page) | |
126 | goto out; | |
127 | ||
4cce66cd TLSC |
128 | page_alloc->dma = dma_map_page(priv->ddev, page_alloc->page, 0, |
129 | MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
130 | if (dma_mapping_error(priv->ddev, page_alloc->dma)) { | |
131 | put_page(page_alloc->page); | |
132 | page_alloc->page = NULL; | |
133 | goto out; | |
134 | } | |
c27a02cd | 135 | page_alloc->offset = priv->frag_info[i].frag_align; |
453a6082 YP |
136 | en_dbg(DRV, priv, "Initialized allocator:%d with page:%p\n", |
137 | i, page_alloc->page); | |
c27a02cd YP |
138 | } |
139 | return 0; | |
140 | ||
141 | out: | |
142 | while (i--) { | |
143 | page_alloc = &ring->page_alloc[i]; | |
4cce66cd TLSC |
144 | dma_unmap_page(priv->ddev, page_alloc->dma, |
145 | MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
c27a02cd YP |
146 | put_page(page_alloc->page); |
147 | page_alloc->page = NULL; | |
148 | } | |
149 | return -ENOMEM; | |
150 | } | |
151 | ||
152 | static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv, | |
153 | struct mlx4_en_rx_ring *ring) | |
154 | { | |
155 | struct mlx4_en_rx_alloc *page_alloc; | |
156 | int i; | |
157 | ||
158 | for (i = 0; i < priv->num_frags; i++) { | |
159 | page_alloc = &ring->page_alloc[i]; | |
453a6082 YP |
160 | en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n", |
161 | i, page_count(page_alloc->page)); | |
c27a02cd | 162 | |
4cce66cd TLSC |
163 | dma_unmap_page(priv->ddev, page_alloc->dma, |
164 | MLX4_EN_ALLOC_SIZE, PCI_DMA_FROMDEVICE); | |
c27a02cd YP |
165 | put_page(page_alloc->page); |
166 | page_alloc->page = NULL; | |
167 | } | |
168 | } | |
169 | ||
c27a02cd YP |
170 | static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv, |
171 | struct mlx4_en_rx_ring *ring, int index) | |
172 | { | |
173 | struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index; | |
c27a02cd YP |
174 | int possible_frags; |
175 | int i; | |
176 | ||
c27a02cd YP |
177 | /* Set size and memtype fields */ |
178 | for (i = 0; i < priv->num_frags; i++) { | |
c27a02cd YP |
179 | rx_desc->data[i].byte_count = |
180 | cpu_to_be32(priv->frag_info[i].frag_size); | |
181 | rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key); | |
182 | } | |
183 | ||
184 | /* If the number of used fragments does not fill up the ring stride, | |
185 | * remaining (unused) fragments must be padded with null address/size | |
186 | * and a special memory key */ | |
187 | possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE; | |
188 | for (i = priv->num_frags; i < possible_frags; i++) { | |
189 | rx_desc->data[i].byte_count = 0; | |
190 | rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD); | |
191 | rx_desc->data[i].addr = 0; | |
192 | } | |
193 | } | |
194 | ||
c27a02cd YP |
195 | static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv, |
196 | struct mlx4_en_rx_ring *ring, int index) | |
197 | { | |
198 | struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride); | |
4cce66cd TLSC |
199 | struct mlx4_en_rx_alloc *frags = ring->rx_info + |
200 | (index << priv->log_rx_info); | |
c27a02cd | 201 | |
4cce66cd | 202 | return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc); |
c27a02cd YP |
203 | } |
204 | ||
205 | static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring) | |
206 | { | |
207 | *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff); | |
208 | } | |
209 | ||
38aab07c YP |
210 | static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv, |
211 | struct mlx4_en_rx_ring *ring, | |
212 | int index) | |
213 | { | |
4cce66cd | 214 | struct mlx4_en_rx_alloc *frags; |
38aab07c YP |
215 | int nr; |
216 | ||
4cce66cd | 217 | frags = ring->rx_info + (index << priv->log_rx_info); |
38aab07c | 218 | for (nr = 0; nr < priv->num_frags; nr++) { |
453a6082 | 219 | en_dbg(DRV, priv, "Freeing fragment:%d\n", nr); |
4cce66cd | 220 | mlx4_en_free_frag(priv, frags, nr); |
38aab07c YP |
221 | } |
222 | } | |
223 | ||
c27a02cd YP |
224 | static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv) |
225 | { | |
c27a02cd YP |
226 | struct mlx4_en_rx_ring *ring; |
227 | int ring_ind; | |
228 | int buf_ind; | |
38aab07c | 229 | int new_size; |
c27a02cd YP |
230 | |
231 | for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) { | |
232 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
233 | ring = &priv->rx_ring[ring_ind]; | |
234 | ||
235 | if (mlx4_en_prepare_rx_desc(priv, ring, | |
236 | ring->actual_size)) { | |
237 | if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) { | |
453a6082 YP |
238 | en_err(priv, "Failed to allocate " |
239 | "enough rx buffers\n"); | |
c27a02cd YP |
240 | return -ENOMEM; |
241 | } else { | |
38aab07c | 242 | new_size = rounddown_pow_of_two(ring->actual_size); |
453a6082 YP |
243 | en_warn(priv, "Only %d buffers allocated " |
244 | "reducing ring size to %d", | |
245 | ring->actual_size, new_size); | |
38aab07c | 246 | goto reduce_rings; |
c27a02cd YP |
247 | } |
248 | } | |
249 | ring->actual_size++; | |
250 | ring->prod++; | |
251 | } | |
252 | } | |
38aab07c YP |
253 | return 0; |
254 | ||
255 | reduce_rings: | |
256 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
257 | ring = &priv->rx_ring[ring_ind]; | |
258 | while (ring->actual_size > new_size) { | |
259 | ring->actual_size--; | |
260 | ring->prod--; | |
261 | mlx4_en_free_rx_desc(priv, ring, ring->actual_size); | |
262 | } | |
38aab07c YP |
263 | } |
264 | ||
c27a02cd YP |
265 | return 0; |
266 | } | |
267 | ||
c27a02cd YP |
268 | static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv, |
269 | struct mlx4_en_rx_ring *ring) | |
270 | { | |
c27a02cd | 271 | int index; |
c27a02cd | 272 | |
453a6082 YP |
273 | en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n", |
274 | ring->cons, ring->prod); | |
c27a02cd YP |
275 | |
276 | /* Unmap and free Rx buffers */ | |
38aab07c | 277 | BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size); |
c27a02cd YP |
278 | while (ring->cons != ring->prod) { |
279 | index = ring->cons & ring->size_mask; | |
453a6082 | 280 | en_dbg(DRV, priv, "Processing descriptor:%d\n", index); |
38aab07c | 281 | mlx4_en_free_rx_desc(priv, ring, index); |
c27a02cd YP |
282 | ++ring->cons; |
283 | } | |
284 | } | |
285 | ||
c27a02cd YP |
286 | int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv, |
287 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) | |
288 | { | |
289 | struct mlx4_en_dev *mdev = priv->mdev; | |
4cce66cd | 290 | int err = -ENOMEM; |
c27a02cd YP |
291 | int tmp; |
292 | ||
c27a02cd YP |
293 | ring->prod = 0; |
294 | ring->cons = 0; | |
295 | ring->size = size; | |
296 | ring->size_mask = size - 1; | |
297 | ring->stride = stride; | |
298 | ring->log_stride = ffs(ring->stride) - 1; | |
9f519f68 | 299 | ring->buf_size = ring->size * ring->stride + TXBB_SIZE; |
c27a02cd YP |
300 | |
301 | tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS * | |
4cce66cd | 302 | sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 303 | ring->rx_info = vmalloc(tmp); |
e404decb | 304 | if (!ring->rx_info) |
c27a02cd | 305 | return -ENOMEM; |
e404decb | 306 | |
453a6082 | 307 | en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
308 | ring->rx_info, tmp); |
309 | ||
310 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, | |
311 | ring->buf_size, 2 * PAGE_SIZE); | |
312 | if (err) | |
313 | goto err_ring; | |
314 | ||
315 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
316 | if (err) { | |
453a6082 | 317 | en_err(priv, "Failed to map RX buffer\n"); |
c27a02cd YP |
318 | goto err_hwq; |
319 | } | |
320 | ring->buf = ring->wqres.buf.direct.buf; | |
321 | ||
c27a02cd YP |
322 | return 0; |
323 | ||
c27a02cd YP |
324 | err_hwq: |
325 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
326 | err_ring: | |
327 | vfree(ring->rx_info); | |
328 | ring->rx_info = NULL; | |
329 | return err; | |
330 | } | |
331 | ||
332 | int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv) | |
333 | { | |
c27a02cd YP |
334 | struct mlx4_en_rx_ring *ring; |
335 | int i; | |
336 | int ring_ind; | |
337 | int err; | |
338 | int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) + | |
339 | DS_SIZE * priv->num_frags); | |
c27a02cd YP |
340 | |
341 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
342 | ring = &priv->rx_ring[ring_ind]; | |
343 | ||
344 | ring->prod = 0; | |
345 | ring->cons = 0; | |
346 | ring->actual_size = 0; | |
347 | ring->cqn = priv->rx_cq[ring_ind].mcq.cqn; | |
348 | ||
349 | ring->stride = stride; | |
9f519f68 YP |
350 | if (ring->stride <= TXBB_SIZE) |
351 | ring->buf += TXBB_SIZE; | |
352 | ||
c27a02cd YP |
353 | ring->log_stride = ffs(ring->stride) - 1; |
354 | ring->buf_size = ring->size * ring->stride; | |
355 | ||
356 | memset(ring->buf, 0, ring->buf_size); | |
357 | mlx4_en_update_rx_prod_db(ring); | |
358 | ||
4cce66cd | 359 | /* Initialize all descriptors */ |
c27a02cd YP |
360 | for (i = 0; i < ring->size; i++) |
361 | mlx4_en_init_rx_desc(priv, ring, i); | |
362 | ||
363 | /* Initialize page allocators */ | |
364 | err = mlx4_en_init_allocator(priv, ring); | |
365 | if (err) { | |
453a6082 | 366 | en_err(priv, "Failed initializing ring allocator\n"); |
60b1809f YP |
367 | if (ring->stride <= TXBB_SIZE) |
368 | ring->buf -= TXBB_SIZE; | |
9a4f92a6 YP |
369 | ring_ind--; |
370 | goto err_allocator; | |
c27a02cd | 371 | } |
c27a02cd | 372 | } |
b58515be IM |
373 | err = mlx4_en_fill_rx_buffers(priv); |
374 | if (err) | |
c27a02cd YP |
375 | goto err_buffers; |
376 | ||
377 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) { | |
378 | ring = &priv->rx_ring[ring_ind]; | |
379 | ||
00d7d7bc | 380 | ring->size_mask = ring->actual_size - 1; |
c27a02cd | 381 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
382 | } |
383 | ||
384 | return 0; | |
385 | ||
c27a02cd YP |
386 | err_buffers: |
387 | for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) | |
388 | mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]); | |
389 | ||
390 | ring_ind = priv->rx_ring_num - 1; | |
391 | err_allocator: | |
392 | while (ring_ind >= 0) { | |
60b1809f YP |
393 | if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE) |
394 | priv->rx_ring[ring_ind].buf -= TXBB_SIZE; | |
c27a02cd YP |
395 | mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]); |
396 | ring_ind--; | |
397 | } | |
398 | return err; | |
399 | } | |
400 | ||
401 | void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv, | |
68355f71 | 402 | struct mlx4_en_rx_ring *ring, u32 size, u16 stride) |
c27a02cd YP |
403 | { |
404 | struct mlx4_en_dev *mdev = priv->mdev; | |
405 | ||
c27a02cd | 406 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
68355f71 | 407 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE); |
c27a02cd YP |
408 | vfree(ring->rx_info); |
409 | ring->rx_info = NULL; | |
1eb8c695 AV |
410 | #ifdef CONFIG_RFS_ACCEL |
411 | mlx4_en_cleanup_filters(priv, ring); | |
412 | #endif | |
c27a02cd YP |
413 | } |
414 | ||
415 | void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv, | |
416 | struct mlx4_en_rx_ring *ring) | |
417 | { | |
c27a02cd | 418 | mlx4_en_free_rx_buf(priv, ring); |
9f519f68 YP |
419 | if (ring->stride <= TXBB_SIZE) |
420 | ring->buf -= TXBB_SIZE; | |
c27a02cd YP |
421 | mlx4_en_destroy_allocator(priv, ring); |
422 | } | |
423 | ||
424 | ||
c27a02cd YP |
425 | static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv, |
426 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 427 | struct mlx4_en_rx_alloc *frags, |
90278c9f | 428 | struct sk_buff *skb, |
c27a02cd YP |
429 | int length) |
430 | { | |
90278c9f | 431 | struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags; |
c27a02cd YP |
432 | struct mlx4_en_frag_info *frag_info; |
433 | int nr; | |
434 | dma_addr_t dma; | |
435 | ||
4cce66cd | 436 | /* Collect used fragments while replacing them in the HW descriptors */ |
c27a02cd YP |
437 | for (nr = 0; nr < priv->num_frags; nr++) { |
438 | frag_info = &priv->frag_info[nr]; | |
439 | if (length <= frag_info->frag_prefix_size) | |
440 | break; | |
4cce66cd TLSC |
441 | if (!frags[nr].page) |
442 | goto fail; | |
c27a02cd | 443 | |
c27a02cd | 444 | dma = be64_to_cpu(rx_desc->data[nr].addr); |
4cce66cd TLSC |
445 | dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size, |
446 | DMA_FROM_DEVICE); | |
c27a02cd | 447 | |
4cce66cd TLSC |
448 | /* Save page reference in skb */ |
449 | get_page(frags[nr].page); | |
450 | __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page); | |
451 | skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size); | |
452 | skb_frags_rx[nr].page_offset = frags[nr].offset; | |
453 | skb->truesize += frag_info->frag_stride; | |
c27a02cd YP |
454 | } |
455 | /* Adjust size of last fragment to match actual length */ | |
973507cb | 456 | if (nr > 0) |
9e903e08 ED |
457 | skb_frag_size_set(&skb_frags_rx[nr - 1], |
458 | length - priv->frag_info[nr - 1].frag_prefix_size); | |
c27a02cd YP |
459 | return nr; |
460 | ||
461 | fail: | |
c27a02cd YP |
462 | while (nr > 0) { |
463 | nr--; | |
311761c8 | 464 | __skb_frag_unref(&skb_frags_rx[nr]); |
c27a02cd YP |
465 | } |
466 | return 0; | |
467 | } | |
468 | ||
469 | ||
470 | static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv, | |
471 | struct mlx4_en_rx_desc *rx_desc, | |
4cce66cd | 472 | struct mlx4_en_rx_alloc *frags, |
c27a02cd YP |
473 | unsigned int length) |
474 | { | |
c27a02cd YP |
475 | struct sk_buff *skb; |
476 | void *va; | |
477 | int used_frags; | |
478 | dma_addr_t dma; | |
479 | ||
c056b734 | 480 | skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN); |
c27a02cd | 481 | if (!skb) { |
453a6082 | 482 | en_dbg(RX_ERR, priv, "Failed allocating skb\n"); |
c27a02cd YP |
483 | return NULL; |
484 | } | |
c27a02cd YP |
485 | skb_reserve(skb, NET_IP_ALIGN); |
486 | skb->len = length; | |
c27a02cd YP |
487 | |
488 | /* Get pointer to first fragment so we could copy the headers into the | |
489 | * (linear part of the) skb */ | |
4cce66cd | 490 | va = page_address(frags[0].page) + frags[0].offset; |
c27a02cd YP |
491 | |
492 | if (length <= SMALL_PACKET_SIZE) { | |
493 | /* We are copying all relevant data to the skb - temporarily | |
4cce66cd | 494 | * sync buffers for the copy */ |
c27a02cd | 495 | dma = be64_to_cpu(rx_desc->data[0].addr); |
ebf8c9aa | 496 | dma_sync_single_for_cpu(priv->ddev, dma, length, |
e4fc8560 | 497 | DMA_FROM_DEVICE); |
c27a02cd | 498 | skb_copy_to_linear_data(skb, va, length); |
c27a02cd YP |
499 | skb->tail += length; |
500 | } else { | |
c27a02cd | 501 | /* Move relevant fragments to skb */ |
4cce66cd TLSC |
502 | used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags, |
503 | skb, length); | |
785a0982 YP |
504 | if (unlikely(!used_frags)) { |
505 | kfree_skb(skb); | |
506 | return NULL; | |
507 | } | |
c27a02cd YP |
508 | skb_shinfo(skb)->nr_frags = used_frags; |
509 | ||
510 | /* Copy headers into the skb linear buffer */ | |
511 | memcpy(skb->data, va, HEADER_COPY_SIZE); | |
512 | skb->tail += HEADER_COPY_SIZE; | |
513 | ||
514 | /* Skip headers in first fragment */ | |
515 | skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE; | |
516 | ||
517 | /* Adjust size of first fragment */ | |
9e903e08 | 518 | skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE); |
c27a02cd YP |
519 | skb->data_len = length - HEADER_COPY_SIZE; |
520 | } | |
521 | return skb; | |
522 | } | |
523 | ||
e7c1c2c4 YP |
524 | static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb) |
525 | { | |
526 | int i; | |
527 | int offset = ETH_HLEN; | |
528 | ||
529 | for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) { | |
530 | if (*(skb->data + offset) != (unsigned char) (i & 0xff)) | |
531 | goto out_loopback; | |
532 | } | |
533 | /* Loopback found */ | |
534 | priv->loopback_ok = 1; | |
535 | ||
536 | out_loopback: | |
537 | dev_kfree_skb_any(skb); | |
538 | } | |
c27a02cd | 539 | |
4cce66cd TLSC |
540 | static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv, |
541 | struct mlx4_en_rx_ring *ring) | |
542 | { | |
543 | int index = ring->prod & ring->size_mask; | |
544 | ||
545 | while ((u32) (ring->prod - ring->cons) < ring->actual_size) { | |
546 | if (mlx4_en_prepare_rx_desc(priv, ring, index)) | |
547 | break; | |
548 | ring->prod++; | |
549 | index = ring->prod & ring->size_mask; | |
550 | } | |
551 | } | |
552 | ||
c27a02cd YP |
553 | int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget) |
554 | { | |
555 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
556 | struct mlx4_cqe *cqe; |
557 | struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring]; | |
4cce66cd | 558 | struct mlx4_en_rx_alloc *frags; |
c27a02cd YP |
559 | struct mlx4_en_rx_desc *rx_desc; |
560 | struct sk_buff *skb; | |
561 | int index; | |
562 | int nr; | |
563 | unsigned int length; | |
564 | int polled = 0; | |
565 | int ip_summed; | |
5b4c4d36 | 566 | struct ethhdr *ethh; |
4cce66cd | 567 | dma_addr_t dma; |
5b4c4d36 | 568 | u64 s_mac; |
c27a02cd YP |
569 | |
570 | if (!priv->port_up) | |
571 | return 0; | |
572 | ||
573 | /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx | |
574 | * descriptor offset can be deduced from the CQE index instead of | |
575 | * reading 'cqe->index' */ | |
576 | index = cq->mcq.cons_index & ring->size_mask; | |
577 | cqe = &cq->buf[index]; | |
578 | ||
579 | /* Process all completed CQEs */ | |
580 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
581 | cq->mcq.cons_index & cq->size)) { | |
582 | ||
4cce66cd | 583 | frags = ring->rx_info + (index << priv->log_rx_info); |
c27a02cd YP |
584 | rx_desc = ring->buf + (index << ring->log_stride); |
585 | ||
586 | /* | |
587 | * make sure we read the CQE after we read the ownership bit | |
588 | */ | |
589 | rmb(); | |
590 | ||
591 | /* Drop packet on bad receive or bad checksum */ | |
592 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == | |
593 | MLX4_CQE_OPCODE_ERROR)) { | |
453a6082 | 594 | en_err(priv, "CQE completed in error - vendor " |
c27a02cd YP |
595 | "syndrom:%d syndrom:%d\n", |
596 | ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome, | |
597 | ((struct mlx4_err_cqe *) cqe)->syndrome); | |
598 | goto next; | |
599 | } | |
600 | if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) { | |
453a6082 | 601 | en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n"); |
c27a02cd YP |
602 | goto next; |
603 | } | |
604 | ||
5b4c4d36 EE |
605 | /* Get pointer to first fragment since we haven't skb yet and |
606 | * cast it to ethhdr struct */ | |
4cce66cd TLSC |
607 | dma = be64_to_cpu(rx_desc->data[0].addr); |
608 | dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh), | |
609 | DMA_FROM_DEVICE); | |
610 | ethh = (struct ethhdr *)(page_address(frags[0].page) + | |
611 | frags[0].offset); | |
5b4c4d36 EE |
612 | s_mac = mlx4_en_mac_to_u64(ethh->h_source); |
613 | ||
614 | /* If source MAC is equal to our own MAC and not performing | |
615 | * the selftest or flb disabled - drop the packet */ | |
616 | if (s_mac == priv->mac && | |
c8c40b7f AV |
617 | !((dev->features & NETIF_F_LOOPBACK) || |
618 | priv->validate_loopback)) | |
5b4c4d36 EE |
619 | goto next; |
620 | ||
c27a02cd YP |
621 | /* |
622 | * Packet is OK - process it. | |
623 | */ | |
624 | length = be32_to_cpu(cqe->byte_cnt); | |
4a5f4dd8 | 625 | length -= ring->fcs_del; |
c27a02cd YP |
626 | ring->bytes += length; |
627 | ring->packets++; | |
628 | ||
c8c64cff | 629 | if (likely(dev->features & NETIF_F_RXCSUM)) { |
c27a02cd YP |
630 | if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) && |
631 | (cqe->checksum == cpu_to_be16(0xffff))) { | |
ad04378c | 632 | ring->csum_ok++; |
c27a02cd YP |
633 | /* This packet is eligible for LRO if it is: |
634 | * - DIX Ethernet (type interpretation) | |
635 | * - TCP/IP (v4) | |
636 | * - without IP options | |
637 | * - not an IP fragment */ | |
fa37a958 YP |
638 | if (dev->features & NETIF_F_GRO) { |
639 | struct sk_buff *gro_skb = napi_get_frags(&cq->napi); | |
ebc872c7 YP |
640 | if (!gro_skb) |
641 | goto next; | |
c27a02cd | 642 | |
4cce66cd TLSC |
643 | nr = mlx4_en_complete_rx_desc(priv, |
644 | rx_desc, frags, gro_skb, | |
645 | length); | |
c27a02cd YP |
646 | if (!nr) |
647 | goto next; | |
648 | ||
fa37a958 YP |
649 | skb_shinfo(gro_skb)->nr_frags = nr; |
650 | gro_skb->len = length; | |
651 | gro_skb->data_len = length; | |
fa37a958 YP |
652 | gro_skb->ip_summed = CHECKSUM_UNNECESSARY; |
653 | ||
f1b553fb JP |
654 | if (cqe->vlan_my_qpn & |
655 | cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) { | |
656 | u16 vid = be16_to_cpu(cqe->sl_vid); | |
657 | ||
658 | __vlan_hwaccel_put_tag(gro_skb, vid); | |
659 | } | |
660 | ||
ad86107f YP |
661 | if (dev->features & NETIF_F_RXHASH) |
662 | gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); | |
663 | ||
3b61008d | 664 | skb_record_rx_queue(gro_skb, cq->ring); |
f1b553fb | 665 | napi_gro_frags(&cq->napi); |
c27a02cd YP |
666 | |
667 | goto next; | |
668 | } | |
669 | ||
670 | /* LRO not possible, complete processing here */ | |
671 | ip_summed = CHECKSUM_UNNECESSARY; | |
c27a02cd YP |
672 | } else { |
673 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 674 | ring->csum_none++; |
c27a02cd YP |
675 | } |
676 | } else { | |
677 | ip_summed = CHECKSUM_NONE; | |
ad04378c | 678 | ring->csum_none++; |
c27a02cd YP |
679 | } |
680 | ||
4cce66cd | 681 | skb = mlx4_en_rx_skb(priv, rx_desc, frags, length); |
c27a02cd YP |
682 | if (!skb) { |
683 | priv->stats.rx_dropped++; | |
684 | goto next; | |
685 | } | |
686 | ||
e7c1c2c4 YP |
687 | if (unlikely(priv->validate_loopback)) { |
688 | validate_loopback(priv, skb); | |
689 | goto next; | |
690 | } | |
691 | ||
c27a02cd YP |
692 | skb->ip_summed = ip_summed; |
693 | skb->protocol = eth_type_trans(skb, dev); | |
0c8dfc83 | 694 | skb_record_rx_queue(skb, cq->ring); |
c27a02cd | 695 | |
ad86107f YP |
696 | if (dev->features & NETIF_F_RXHASH) |
697 | skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid); | |
698 | ||
f1b553fb JP |
699 | if (be32_to_cpu(cqe->vlan_my_qpn) & |
700 | MLX4_CQE_VLAN_PRESENT_MASK) | |
701 | __vlan_hwaccel_put_tag(skb, be16_to_cpu(cqe->sl_vid)); | |
702 | ||
c27a02cd | 703 | /* Push it up the stack */ |
f1b553fb | 704 | netif_receive_skb(skb); |
c27a02cd | 705 | |
c27a02cd | 706 | next: |
4cce66cd TLSC |
707 | for (nr = 0; nr < priv->num_frags; nr++) |
708 | mlx4_en_free_frag(priv, frags, nr); | |
709 | ||
c27a02cd YP |
710 | ++cq->mcq.cons_index; |
711 | index = (cq->mcq.cons_index) & ring->size_mask; | |
712 | cqe = &cq->buf[index]; | |
713 | if (++polled == budget) { | |
714 | /* We are here because we reached the NAPI budget - | |
715 | * flush only pending LRO sessions */ | |
c27a02cd YP |
716 | goto out; |
717 | } | |
718 | } | |
719 | ||
c27a02cd YP |
720 | out: |
721 | AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled); | |
722 | mlx4_cq_set_ci(&cq->mcq); | |
723 | wmb(); /* ensure HW sees CQ consumer before we post new buffers */ | |
724 | ring->cons = cq->mcq.cons_index; | |
4cce66cd | 725 | mlx4_en_refill_rx_buffers(priv, ring); |
c27a02cd YP |
726 | mlx4_en_update_rx_prod_db(ring); |
727 | return polled; | |
728 | } | |
729 | ||
730 | ||
731 | void mlx4_en_rx_irq(struct mlx4_cq *mcq) | |
732 | { | |
733 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
734 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
735 | ||
736 | if (priv->port_up) | |
288379f0 | 737 | napi_schedule(&cq->napi); |
c27a02cd YP |
738 | else |
739 | mlx4_en_arm_cq(priv, cq); | |
740 | } | |
741 | ||
742 | /* Rx CQ polling - called by NAPI */ | |
743 | int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget) | |
744 | { | |
745 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
746 | struct net_device *dev = cq->dev; | |
747 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
748 | int done; | |
749 | ||
750 | done = mlx4_en_process_rx_cq(dev, cq, budget); | |
751 | ||
752 | /* If we used up all the quota - we're probably not done yet... */ | |
753 | if (done == budget) | |
754 | INC_PERF_COUNTER(priv->pstats.napi_quota); | |
755 | else { | |
756 | /* Done for now */ | |
288379f0 | 757 | napi_complete(napi); |
c27a02cd YP |
758 | mlx4_en_arm_cq(priv, cq); |
759 | } | |
760 | return done; | |
761 | } | |
762 | ||
763 | ||
25985edc | 764 | /* Calculate the last offset position that accommodates a full fragment |
c27a02cd YP |
765 | * (assuming fagment size = stride-align) */ |
766 | static int mlx4_en_last_alloc_offset(struct mlx4_en_priv *priv, u16 stride, u16 align) | |
767 | { | |
768 | u16 res = MLX4_EN_ALLOC_SIZE % stride; | |
769 | u16 offset = MLX4_EN_ALLOC_SIZE - stride - res + align; | |
770 | ||
453a6082 | 771 | en_dbg(DRV, priv, "Calculated last offset for stride:%d align:%d " |
c27a02cd YP |
772 | "res:%d offset:%d\n", stride, align, res, offset); |
773 | return offset; | |
774 | } | |
775 | ||
776 | ||
777 | static int frag_sizes[] = { | |
778 | FRAG_SZ0, | |
779 | FRAG_SZ1, | |
780 | FRAG_SZ2, | |
781 | FRAG_SZ3 | |
782 | }; | |
783 | ||
784 | void mlx4_en_calc_rx_buf(struct net_device *dev) | |
785 | { | |
786 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
787 | int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE; | |
788 | int buf_size = 0; | |
789 | int i = 0; | |
790 | ||
791 | while (buf_size < eff_mtu) { | |
792 | priv->frag_info[i].frag_size = | |
793 | (eff_mtu > buf_size + frag_sizes[i]) ? | |
794 | frag_sizes[i] : eff_mtu - buf_size; | |
795 | priv->frag_info[i].frag_prefix_size = buf_size; | |
796 | if (!i) { | |
797 | priv->frag_info[i].frag_align = NET_IP_ALIGN; | |
798 | priv->frag_info[i].frag_stride = | |
799 | ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES); | |
800 | } else { | |
801 | priv->frag_info[i].frag_align = 0; | |
802 | priv->frag_info[i].frag_stride = | |
803 | ALIGN(frag_sizes[i], SMP_CACHE_BYTES); | |
804 | } | |
805 | priv->frag_info[i].last_offset = mlx4_en_last_alloc_offset( | |
806 | priv, priv->frag_info[i].frag_stride, | |
807 | priv->frag_info[i].frag_align); | |
808 | buf_size += priv->frag_info[i].frag_size; | |
809 | i++; | |
810 | } | |
811 | ||
812 | priv->num_frags = i; | |
813 | priv->rx_skb_size = eff_mtu; | |
4cce66cd | 814 | priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc)); |
c27a02cd | 815 | |
453a6082 | 816 | en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d " |
c27a02cd YP |
817 | "num_frags:%d):\n", eff_mtu, priv->num_frags); |
818 | for (i = 0; i < priv->num_frags; i++) { | |
453a6082 | 819 | en_dbg(DRV, priv, " frag:%d - size:%d prefix:%d align:%d " |
c27a02cd YP |
820 | "stride:%d last_offset:%d\n", i, |
821 | priv->frag_info[i].frag_size, | |
822 | priv->frag_info[i].frag_prefix_size, | |
823 | priv->frag_info[i].frag_align, | |
824 | priv->frag_info[i].frag_stride, | |
825 | priv->frag_info[i].last_offset); | |
826 | } | |
827 | } | |
828 | ||
829 | /* RSS related functions */ | |
830 | ||
9f519f68 YP |
831 | static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn, |
832 | struct mlx4_en_rx_ring *ring, | |
c27a02cd YP |
833 | enum mlx4_qp_state *state, |
834 | struct mlx4_qp *qp) | |
835 | { | |
836 | struct mlx4_en_dev *mdev = priv->mdev; | |
837 | struct mlx4_qp_context *context; | |
838 | int err = 0; | |
839 | ||
840 | context = kmalloc(sizeof *context , GFP_KERNEL); | |
841 | if (!context) { | |
453a6082 | 842 | en_err(priv, "Failed to allocate qp context\n"); |
c27a02cd YP |
843 | return -ENOMEM; |
844 | } | |
845 | ||
846 | err = mlx4_qp_alloc(mdev->dev, qpn, qp); | |
847 | if (err) { | |
453a6082 | 848 | en_err(priv, "Failed to allocate qp #%x\n", qpn); |
c27a02cd | 849 | goto out; |
c27a02cd YP |
850 | } |
851 | qp->event = mlx4_en_sqp_event; | |
852 | ||
853 | memset(context, 0, sizeof *context); | |
00d7d7bc | 854 | mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0, |
0e98b523 | 855 | qpn, ring->cqn, -1, context); |
9f519f68 | 856 | context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma); |
c27a02cd | 857 | |
f3a9d1f2 | 858 | /* Cancel FCS removal if FW allows */ |
4a5f4dd8 | 859 | if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) { |
f3a9d1f2 | 860 | context->param3 |= cpu_to_be32(1 << 29); |
4a5f4dd8 YP |
861 | ring->fcs_del = ETH_FCS_LEN; |
862 | } else | |
863 | ring->fcs_del = 0; | |
f3a9d1f2 | 864 | |
9f519f68 | 865 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state); |
c27a02cd YP |
866 | if (err) { |
867 | mlx4_qp_remove(mdev->dev, qp); | |
868 | mlx4_qp_free(mdev->dev, qp); | |
869 | } | |
9f519f68 | 870 | mlx4_en_update_rx_prod_db(ring); |
c27a02cd YP |
871 | out: |
872 | kfree(context); | |
873 | return err; | |
874 | } | |
875 | ||
cabdc8ee HHZ |
876 | int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv) |
877 | { | |
878 | int err; | |
879 | u32 qpn; | |
880 | ||
881 | err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn); | |
882 | if (err) { | |
883 | en_err(priv, "Failed reserving drop qpn\n"); | |
884 | return err; | |
885 | } | |
886 | err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp); | |
887 | if (err) { | |
888 | en_err(priv, "Failed allocating drop qp\n"); | |
889 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
890 | return err; | |
891 | } | |
892 | ||
893 | return 0; | |
894 | } | |
895 | ||
896 | void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv) | |
897 | { | |
898 | u32 qpn; | |
899 | ||
900 | qpn = priv->drop_qp.qpn; | |
901 | mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp); | |
902 | mlx4_qp_free(priv->mdev->dev, &priv->drop_qp); | |
903 | mlx4_qp_release_range(priv->mdev->dev, qpn, 1); | |
904 | } | |
905 | ||
c27a02cd YP |
906 | /* Allocate rx qp's and configure them according to rss map */ |
907 | int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv) | |
908 | { | |
909 | struct mlx4_en_dev *mdev = priv->mdev; | |
910 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
911 | struct mlx4_qp_context context; | |
876f6e67 | 912 | struct mlx4_rss_context *rss_context; |
93d3e367 | 913 | int rss_rings; |
c27a02cd | 914 | void *ptr; |
876f6e67 | 915 | u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 | |
1202d460 | 916 | MLX4_RSS_TCP_IPV6); |
9f519f68 | 917 | int i, qpn; |
c27a02cd YP |
918 | int err = 0; |
919 | int good_qps = 0; | |
ad86107f YP |
920 | static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC, |
921 | 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD, | |
922 | 0x593D56D9, 0xF3253C06, 0x2ADC1FFC}; | |
c27a02cd | 923 | |
453a6082 | 924 | en_dbg(DRV, priv, "Configuring rss steering\n"); |
b6b912e0 YP |
925 | err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num, |
926 | priv->rx_ring_num, | |
927 | &rss_map->base_qpn); | |
c27a02cd | 928 | if (err) { |
b6b912e0 | 929 | en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num); |
c27a02cd YP |
930 | return err; |
931 | } | |
932 | ||
b6b912e0 | 933 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd | 934 | qpn = rss_map->base_qpn + i; |
9f519f68 | 935 | err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i], |
c27a02cd YP |
936 | &rss_map->state[i], |
937 | &rss_map->qps[i]); | |
938 | if (err) | |
939 | goto rss_err; | |
940 | ||
941 | ++good_qps; | |
942 | } | |
943 | ||
944 | /* Configure RSS indirection qp */ | |
c27a02cd YP |
945 | err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp); |
946 | if (err) { | |
453a6082 | 947 | en_err(priv, "Failed to allocate RSS indirection QP\n"); |
1679200f | 948 | goto rss_err; |
c27a02cd YP |
949 | } |
950 | rss_map->indir_qp.event = mlx4_en_sqp_event; | |
951 | mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn, | |
0e98b523 | 952 | priv->rx_ring[0].cqn, -1, &context); |
c27a02cd | 953 | |
93d3e367 YP |
954 | if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num) |
955 | rss_rings = priv->rx_ring_num; | |
956 | else | |
957 | rss_rings = priv->prof->rss_rings; | |
958 | ||
876f6e67 OG |
959 | ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path) |
960 | + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH; | |
43d620c8 | 961 | rss_context = ptr; |
93d3e367 | 962 | rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 | |
c27a02cd | 963 | (rss_map->base_qpn)); |
89efea25 | 964 | rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn); |
1202d460 OG |
965 | if (priv->mdev->profile.udp_rss) { |
966 | rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6; | |
967 | rss_context->base_qpn_udp = rss_context->default_qpn; | |
968 | } | |
0533943c | 969 | rss_context->flags = rss_mask; |
876f6e67 | 970 | rss_context->hash_fn = MLX4_RSS_HASH_TOP; |
ad86107f | 971 | for (i = 0; i < 10; i++) |
39b2c4eb | 972 | rss_context->rss_key[i] = cpu_to_be32(rsskey[i]); |
c27a02cd YP |
973 | |
974 | err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context, | |
975 | &rss_map->indir_qp, &rss_map->indir_state); | |
976 | if (err) | |
977 | goto indir_err; | |
978 | ||
979 | return 0; | |
980 | ||
981 | indir_err: | |
982 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
983 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
984 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
985 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd YP |
986 | rss_err: |
987 | for (i = 0; i < good_qps; i++) { | |
988 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], | |
989 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
990 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
991 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
992 | } | |
b6b912e0 | 993 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd YP |
994 | return err; |
995 | } | |
996 | ||
997 | void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv) | |
998 | { | |
999 | struct mlx4_en_dev *mdev = priv->mdev; | |
1000 | struct mlx4_en_rss_map *rss_map = &priv->rss_map; | |
1001 | int i; | |
1002 | ||
1003 | mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state, | |
1004 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp); | |
1005 | mlx4_qp_remove(mdev->dev, &rss_map->indir_qp); | |
1006 | mlx4_qp_free(mdev->dev, &rss_map->indir_qp); | |
c27a02cd | 1007 | |
b6b912e0 | 1008 | for (i = 0; i < priv->rx_ring_num; i++) { |
c27a02cd YP |
1009 | mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i], |
1010 | MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]); | |
1011 | mlx4_qp_remove(mdev->dev, &rss_map->qps[i]); | |
1012 | mlx4_qp_free(mdev->dev, &rss_map->qps[i]); | |
1013 | } | |
b6b912e0 | 1014 | mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num); |
c27a02cd | 1015 | } |