Commit | Line | Data |
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c27a02cd YP |
1 | /* |
2 | * Copyright (c) 2007 Mellanox Technologies. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | * | |
32 | */ | |
33 | ||
34 | #include <asm/page.h> | |
35 | #include <linux/mlx4/cq.h> | |
5a0e3ad6 | 36 | #include <linux/slab.h> |
c27a02cd YP |
37 | #include <linux/mlx4/qp.h> |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/if_vlan.h> | |
40 | #include <linux/vmalloc.h> | |
fa37a958 | 41 | #include <linux/tcp.h> |
837052d0 | 42 | #include <linux/ip.h> |
6eb07caf | 43 | #include <linux/moduleparam.h> |
c27a02cd YP |
44 | |
45 | #include "mlx4_en.h" | |
46 | ||
47 | enum { | |
48 | MAX_INLINE = 104, /* 128 - 16 - 4 - 4 */ | |
87a5c389 | 49 | MAX_BF = 256, |
c27a02cd YP |
50 | }; |
51 | ||
52 | static int inline_thold __read_mostly = MAX_INLINE; | |
53 | ||
54 | module_param_named(inline_thold, inline_thold, int, 0444); | |
af901ca1 | 55 | MODULE_PARM_DESC(inline_thold, "threshold for using inline data"); |
c27a02cd YP |
56 | |
57 | int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 58 | struct mlx4_en_tx_ring **pring, int qpn, u32 size, |
d03a68f8 | 59 | u16 stride, int node, int queue_index) |
c27a02cd YP |
60 | { |
61 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 62 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
63 | int tmp; |
64 | int err; | |
65 | ||
163561a4 | 66 | ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, node); |
41d942d5 | 67 | if (!ring) { |
163561a4 EE |
68 | ring = kzalloc(sizeof(*ring), GFP_KERNEL); |
69 | if (!ring) { | |
70 | en_err(priv, "Failed allocating TX ring\n"); | |
71 | return -ENOMEM; | |
72 | } | |
41d942d5 EE |
73 | } |
74 | ||
c27a02cd YP |
75 | ring->size = size; |
76 | ring->size_mask = size - 1; | |
77 | ring->stride = stride; | |
78 | ||
79 | inline_thold = min(inline_thold, MAX_INLINE); | |
80 | ||
c27a02cd | 81 | tmp = size * sizeof(struct mlx4_en_tx_info); |
163561a4 | 82 | ring->tx_info = vmalloc_node(tmp, node); |
41d942d5 | 83 | if (!ring->tx_info) { |
163561a4 EE |
84 | ring->tx_info = vmalloc(tmp); |
85 | if (!ring->tx_info) { | |
86 | err = -ENOMEM; | |
87 | goto err_ring; | |
88 | } | |
41d942d5 | 89 | } |
e404decb | 90 | |
453a6082 | 91 | en_dbg(DRV, priv, "Allocated tx_info ring at addr:%p size:%d\n", |
c27a02cd YP |
92 | ring->tx_info, tmp); |
93 | ||
163561a4 | 94 | ring->bounce_buf = kmalloc_node(MAX_DESC_SIZE, GFP_KERNEL, node); |
c27a02cd | 95 | if (!ring->bounce_buf) { |
163561a4 EE |
96 | ring->bounce_buf = kmalloc(MAX_DESC_SIZE, GFP_KERNEL); |
97 | if (!ring->bounce_buf) { | |
98 | err = -ENOMEM; | |
99 | goto err_info; | |
100 | } | |
c27a02cd YP |
101 | } |
102 | ring->buf_size = ALIGN(size * ring->stride, MLX4_EN_PAGE_SIZE); | |
103 | ||
163561a4 EE |
104 | /* Allocate HW buffers on provided NUMA node */ |
105 | set_dev_node(&mdev->dev->pdev->dev, node); | |
c27a02cd YP |
106 | err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres, ring->buf_size, |
107 | 2 * PAGE_SIZE); | |
163561a4 | 108 | set_dev_node(&mdev->dev->pdev->dev, mdev->dev->numa_node); |
c27a02cd | 109 | if (err) { |
453a6082 | 110 | en_err(priv, "Failed allocating hwq resources\n"); |
c27a02cd YP |
111 | goto err_bounce; |
112 | } | |
113 | ||
114 | err = mlx4_en_map_buffer(&ring->wqres.buf); | |
115 | if (err) { | |
453a6082 | 116 | en_err(priv, "Failed to map TX buffer\n"); |
c27a02cd YP |
117 | goto err_hwq_res; |
118 | } | |
119 | ||
120 | ring->buf = ring->wqres.buf.direct.buf; | |
121 | ||
453a6082 YP |
122 | en_dbg(DRV, priv, "Allocated TX ring (addr:%p) - buf:%p size:%d " |
123 | "buf_size:%d dma:%llx\n", ring, ring->buf, ring->size, | |
124 | ring->buf_size, (unsigned long long) ring->wqres.buf.direct.map); | |
c27a02cd | 125 | |
87a5c389 | 126 | ring->qpn = qpn; |
c27a02cd YP |
127 | err = mlx4_qp_alloc(mdev->dev, ring->qpn, &ring->qp); |
128 | if (err) { | |
453a6082 | 129 | en_err(priv, "Failed allocating qp %d\n", ring->qpn); |
87a5c389 | 130 | goto err_map; |
c27a02cd | 131 | } |
966508f7 | 132 | ring->qp.event = mlx4_en_sqp_event; |
c27a02cd | 133 | |
163561a4 | 134 | err = mlx4_bf_alloc(mdev->dev, &ring->bf, node); |
87a5c389 YP |
135 | if (err) { |
136 | en_dbg(DRV, priv, "working without blueflame (%d)", err); | |
137 | ring->bf.uar = &mdev->priv_uar; | |
138 | ring->bf.uar->map = mdev->uar_map; | |
139 | ring->bf_enabled = false; | |
140 | } else | |
141 | ring->bf_enabled = true; | |
142 | ||
ec693d47 | 143 | ring->hwtstamp_tx_type = priv->hwtstamp_config.tx_type; |
d03a68f8 IS |
144 | ring->queue_index = queue_index; |
145 | ||
146 | if (queue_index < priv->num_tx_rings_p_up && cpu_online(queue_index)) | |
147 | cpumask_set_cpu(queue_index, &ring->affinity_mask); | |
ec693d47 | 148 | |
41d942d5 | 149 | *pring = ring; |
c27a02cd YP |
150 | return 0; |
151 | ||
c27a02cd YP |
152 | err_map: |
153 | mlx4_en_unmap_buffer(&ring->wqres.buf); | |
154 | err_hwq_res: | |
155 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
156 | err_bounce: | |
157 | kfree(ring->bounce_buf); | |
158 | ring->bounce_buf = NULL; | |
41d942d5 | 159 | err_info: |
c27a02cd YP |
160 | vfree(ring->tx_info); |
161 | ring->tx_info = NULL; | |
41d942d5 EE |
162 | err_ring: |
163 | kfree(ring); | |
164 | *pring = NULL; | |
c27a02cd YP |
165 | return err; |
166 | } | |
167 | ||
168 | void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, | |
41d942d5 | 169 | struct mlx4_en_tx_ring **pring) |
c27a02cd YP |
170 | { |
171 | struct mlx4_en_dev *mdev = priv->mdev; | |
41d942d5 | 172 | struct mlx4_en_tx_ring *ring = *pring; |
453a6082 | 173 | en_dbg(DRV, priv, "Destroying tx ring, qpn: %d\n", ring->qpn); |
c27a02cd | 174 | |
87a5c389 YP |
175 | if (ring->bf_enabled) |
176 | mlx4_bf_free(mdev->dev, &ring->bf); | |
c27a02cd YP |
177 | mlx4_qp_remove(mdev->dev, &ring->qp); |
178 | mlx4_qp_free(mdev->dev, &ring->qp); | |
c27a02cd YP |
179 | mlx4_en_unmap_buffer(&ring->wqres.buf); |
180 | mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size); | |
181 | kfree(ring->bounce_buf); | |
182 | ring->bounce_buf = NULL; | |
183 | vfree(ring->tx_info); | |
184 | ring->tx_info = NULL; | |
41d942d5 EE |
185 | kfree(ring); |
186 | *pring = NULL; | |
c27a02cd YP |
187 | } |
188 | ||
189 | int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv, | |
190 | struct mlx4_en_tx_ring *ring, | |
0e98b523 | 191 | int cq, int user_prio) |
c27a02cd YP |
192 | { |
193 | struct mlx4_en_dev *mdev = priv->mdev; | |
194 | int err; | |
195 | ||
196 | ring->cqn = cq; | |
197 | ring->prod = 0; | |
198 | ring->cons = 0xffffffff; | |
199 | ring->last_nr_txbb = 1; | |
200 | ring->poll_cnt = 0; | |
c27a02cd YP |
201 | memset(ring->tx_info, 0, ring->size * sizeof(struct mlx4_en_tx_info)); |
202 | memset(ring->buf, 0, ring->buf_size); | |
203 | ||
204 | ring->qp_state = MLX4_QP_STATE_RST; | |
c5d6136e | 205 | ring->doorbell_qpn = ring->qp.qpn << 8; |
c27a02cd YP |
206 | |
207 | mlx4_en_fill_qp_context(priv, ring->size, ring->stride, 1, 0, ring->qpn, | |
0e98b523 | 208 | ring->cqn, user_prio, &ring->context); |
87a5c389 YP |
209 | if (ring->bf_enabled) |
210 | ring->context.usr_page = cpu_to_be32(ring->bf.uar->index); | |
c27a02cd YP |
211 | |
212 | err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, &ring->context, | |
213 | &ring->qp, &ring->qp_state); | |
d03a68f8 IS |
214 | if (!user_prio && cpu_online(ring->queue_index)) |
215 | netif_set_xps_queue(priv->dev, &ring->affinity_mask, | |
216 | ring->queue_index); | |
c27a02cd YP |
217 | |
218 | return err; | |
219 | } | |
220 | ||
221 | void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv, | |
222 | struct mlx4_en_tx_ring *ring) | |
223 | { | |
224 | struct mlx4_en_dev *mdev = priv->mdev; | |
225 | ||
226 | mlx4_qp_modify(mdev->dev, NULL, ring->qp_state, | |
227 | MLX4_QP_STATE_RST, NULL, 0, 0, &ring->qp); | |
228 | } | |
229 | ||
2d4b6466 EE |
230 | static void mlx4_en_stamp_wqe(struct mlx4_en_priv *priv, |
231 | struct mlx4_en_tx_ring *ring, int index, | |
232 | u8 owner) | |
233 | { | |
234 | __be32 stamp = cpu_to_be32(STAMP_VAL | (!!owner << STAMP_SHIFT)); | |
235 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
236 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; | |
237 | void *end = ring->buf + ring->buf_size; | |
238 | __be32 *ptr = (__be32 *)tx_desc; | |
239 | int i; | |
240 | ||
241 | /* Optimize the common case when there are no wraparounds */ | |
242 | if (likely((void *)tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
243 | /* Stamp the freed descriptor */ | |
244 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
245 | i += STAMP_STRIDE) { | |
246 | *ptr = stamp; | |
247 | ptr += STAMP_DWORDS; | |
248 | } | |
249 | } else { | |
250 | /* Stamp the freed descriptor */ | |
251 | for (i = 0; i < tx_info->nr_txbb * TXBB_SIZE; | |
252 | i += STAMP_STRIDE) { | |
253 | *ptr = stamp; | |
254 | ptr += STAMP_DWORDS; | |
255 | if ((void *)ptr >= end) { | |
256 | ptr = ring->buf; | |
257 | stamp ^= cpu_to_be32(0x80000000); | |
258 | } | |
259 | } | |
260 | } | |
261 | } | |
262 | ||
c27a02cd YP |
263 | |
264 | static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv, | |
265 | struct mlx4_en_tx_ring *ring, | |
ec693d47 | 266 | int index, u8 owner, u64 timestamp) |
c27a02cd | 267 | { |
ec693d47 | 268 | struct mlx4_en_dev *mdev = priv->mdev; |
c27a02cd YP |
269 | struct mlx4_en_tx_info *tx_info = &ring->tx_info[index]; |
270 | struct mlx4_en_tx_desc *tx_desc = ring->buf + index * TXBB_SIZE; | |
271 | struct mlx4_wqe_data_seg *data = (void *) tx_desc + tx_info->data_offset; | |
272 | struct sk_buff *skb = tx_info->skb; | |
273 | struct skb_frag_struct *frag; | |
274 | void *end = ring->buf + ring->buf_size; | |
275 | int frags = skb_shinfo(skb)->nr_frags; | |
276 | int i; | |
ec693d47 AV |
277 | struct skb_shared_hwtstamps hwts; |
278 | ||
279 | if (timestamp) { | |
280 | mlx4_en_fill_hwtstamps(mdev, &hwts, timestamp); | |
281 | skb_tstamp_tx(skb, &hwts); | |
282 | } | |
c27a02cd YP |
283 | |
284 | /* Optimize the common case when there are no wraparounds */ | |
285 | if (likely((void *) tx_desc + tx_info->nr_txbb * TXBB_SIZE <= end)) { | |
41efea5a YP |
286 | if (!tx_info->inl) { |
287 | if (tx_info->linear) { | |
ebf8c9aa | 288 | dma_unmap_single(priv->ddev, |
41efea5a | 289 | (dma_addr_t) be64_to_cpu(data->addr), |
c27a02cd YP |
290 | be32_to_cpu(data->byte_count), |
291 | PCI_DMA_TODEVICE); | |
41efea5a YP |
292 | ++data; |
293 | } | |
c27a02cd | 294 | |
41efea5a YP |
295 | for (i = 0; i < frags; i++) { |
296 | frag = &skb_shinfo(skb)->frags[i]; | |
ebf8c9aa | 297 | dma_unmap_page(priv->ddev, |
41efea5a | 298 | (dma_addr_t) be64_to_cpu(data[i].addr), |
9e903e08 | 299 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
41efea5a | 300 | } |
c27a02cd | 301 | } |
c27a02cd | 302 | } else { |
41efea5a YP |
303 | if (!tx_info->inl) { |
304 | if ((void *) data >= end) { | |
43d620c8 | 305 | data = ring->buf + ((void *)data - end); |
41efea5a | 306 | } |
c27a02cd | 307 | |
41efea5a | 308 | if (tx_info->linear) { |
ebf8c9aa | 309 | dma_unmap_single(priv->ddev, |
41efea5a | 310 | (dma_addr_t) be64_to_cpu(data->addr), |
c27a02cd YP |
311 | be32_to_cpu(data->byte_count), |
312 | PCI_DMA_TODEVICE); | |
41efea5a YP |
313 | ++data; |
314 | } | |
c27a02cd | 315 | |
41efea5a YP |
316 | for (i = 0; i < frags; i++) { |
317 | /* Check for wraparound before unmapping */ | |
318 | if ((void *) data >= end) | |
43d620c8 | 319 | data = ring->buf; |
41efea5a | 320 | frag = &skb_shinfo(skb)->frags[i]; |
ebf8c9aa | 321 | dma_unmap_page(priv->ddev, |
c27a02cd | 322 | (dma_addr_t) be64_to_cpu(data->addr), |
9e903e08 | 323 | skb_frag_size(frag), PCI_DMA_TODEVICE); |
eb4ad826 | 324 | ++data; |
41efea5a | 325 | } |
c27a02cd | 326 | } |
c27a02cd | 327 | } |
0276a330 | 328 | dev_kfree_skb(skb); |
c27a02cd YP |
329 | return tx_info->nr_txbb; |
330 | } | |
331 | ||
332 | ||
333 | int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring) | |
334 | { | |
335 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
336 | int cnt = 0; | |
337 | ||
338 | /* Skip last polled descriptor */ | |
339 | ring->cons += ring->last_nr_txbb; | |
453a6082 | 340 | en_dbg(DRV, priv, "Freeing Tx buf - cons:0x%x prod:0x%x\n", |
c27a02cd YP |
341 | ring->cons, ring->prod); |
342 | ||
343 | if ((u32) (ring->prod - ring->cons) > ring->size) { | |
344 | if (netif_msg_tx_err(priv)) | |
453a6082 | 345 | en_warn(priv, "Tx consumer passed producer!\n"); |
c27a02cd YP |
346 | return 0; |
347 | } | |
348 | ||
349 | while (ring->cons != ring->prod) { | |
350 | ring->last_nr_txbb = mlx4_en_free_tx_desc(priv, ring, | |
351 | ring->cons & ring->size_mask, | |
ec693d47 | 352 | !!(ring->cons & ring->size), 0); |
c27a02cd YP |
353 | ring->cons += ring->last_nr_txbb; |
354 | cnt++; | |
355 | } | |
356 | ||
41b74920 TH |
357 | netdev_tx_reset_queue(ring->tx_queue); |
358 | ||
c27a02cd | 359 | if (cnt) |
453a6082 | 360 | en_dbg(DRV, priv, "Freed %d uncompleted tx descriptors\n", cnt); |
c27a02cd YP |
361 | |
362 | return cnt; | |
363 | } | |
364 | ||
0276a330 EE |
365 | static int mlx4_en_process_tx_cq(struct net_device *dev, |
366 | struct mlx4_en_cq *cq, | |
367 | int budget) | |
c27a02cd YP |
368 | { |
369 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
370 | struct mlx4_cq *mcq = &cq->mcq; | |
41d942d5 | 371 | struct mlx4_en_tx_ring *ring = priv->tx_ring[cq->ring]; |
f0ab34f0 | 372 | struct mlx4_cqe *cqe; |
c27a02cd | 373 | u16 index; |
2d4b6466 | 374 | u16 new_index, ring_index, stamp_index; |
c27a02cd | 375 | u32 txbbs_skipped = 0; |
2d4b6466 | 376 | u32 txbbs_stamp = 0; |
f0ab34f0 YP |
377 | u32 cons_index = mcq->cons_index; |
378 | int size = cq->size; | |
379 | u32 size_mask = ring->size_mask; | |
380 | struct mlx4_cqe *buf = cq->buf; | |
5b263f53 YP |
381 | u32 packets = 0; |
382 | u32 bytes = 0; | |
08ff3235 | 383 | int factor = priv->cqe_factor; |
ec693d47 | 384 | u64 timestamp = 0; |
0276a330 | 385 | int done = 0; |
c27a02cd YP |
386 | |
387 | if (!priv->port_up) | |
0276a330 | 388 | return 0; |
c27a02cd | 389 | |
f0ab34f0 | 390 | index = cons_index & size_mask; |
08ff3235 | 391 | cqe = &buf[(index << factor) + factor]; |
f0ab34f0 | 392 | ring_index = ring->cons & size_mask; |
2d4b6466 | 393 | stamp_index = ring_index; |
f0ab34f0 YP |
394 | |
395 | /* Process all completed CQEs */ | |
396 | while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK, | |
0276a330 | 397 | cons_index & size) && (done < budget)) { |
f0ab34f0 YP |
398 | /* |
399 | * make sure we read the CQE after we read the | |
400 | * ownership bit | |
401 | */ | |
402 | rmb(); | |
403 | ||
bd2f631d AV |
404 | if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == |
405 | MLX4_CQE_OPCODE_ERROR)) { | |
406 | struct mlx4_err_cqe *cqe_err = (struct mlx4_err_cqe *)cqe; | |
407 | ||
408 | en_err(priv, "CQE error - vendor syndrome: 0x%x syndrome: 0x%x\n", | |
409 | cqe_err->vendor_err_syndrome, | |
410 | cqe_err->syndrome); | |
411 | } | |
412 | ||
f0ab34f0 YP |
413 | /* Skip over last polled CQE */ |
414 | new_index = be16_to_cpu(cqe->wqe_index) & size_mask; | |
415 | ||
c27a02cd | 416 | do { |
c27a02cd | 417 | txbbs_skipped += ring->last_nr_txbb; |
f0ab34f0 | 418 | ring_index = (ring_index + ring->last_nr_txbb) & size_mask; |
ec693d47 AV |
419 | if (ring->tx_info[ring_index].ts_requested) |
420 | timestamp = mlx4_en_get_cqe_ts(cqe); | |
421 | ||
f0ab34f0 | 422 | /* free next descriptor */ |
c27a02cd | 423 | ring->last_nr_txbb = mlx4_en_free_tx_desc( |
f0ab34f0 YP |
424 | priv, ring, ring_index, |
425 | !!((ring->cons + txbbs_skipped) & | |
ec693d47 | 426 | ring->size), timestamp); |
2d4b6466 EE |
427 | |
428 | mlx4_en_stamp_wqe(priv, ring, stamp_index, | |
429 | !!((ring->cons + txbbs_stamp) & | |
430 | ring->size)); | |
431 | stamp_index = ring_index; | |
432 | txbbs_stamp = txbbs_skipped; | |
5b263f53 YP |
433 | packets++; |
434 | bytes += ring->tx_info[ring_index].nr_bytes; | |
0276a330 | 435 | } while ((++done < budget) && (ring_index != new_index)); |
f0ab34f0 YP |
436 | |
437 | ++cons_index; | |
438 | index = cons_index & size_mask; | |
08ff3235 | 439 | cqe = &buf[(index << factor) + factor]; |
f0ab34f0 | 440 | } |
c27a02cd | 441 | |
c27a02cd YP |
442 | |
443 | /* | |
444 | * To prevent CQ overflow we first update CQ consumer and only then | |
445 | * the ring consumer. | |
446 | */ | |
f0ab34f0 | 447 | mcq->cons_index = cons_index; |
c27a02cd YP |
448 | mlx4_cq_set_ci(mcq); |
449 | wmb(); | |
450 | ring->cons += txbbs_skipped; | |
5b263f53 | 451 | netdev_tx_completed_queue(ring->tx_queue, packets, bytes); |
c27a02cd | 452 | |
c18520bd YP |
453 | /* |
454 | * Wakeup Tx queue if this stopped, and at least 1 packet | |
455 | * was completed | |
456 | */ | |
457 | if (netif_tx_queue_stopped(ring->tx_queue) && txbbs_skipped > 0) { | |
458 | netif_tx_wake_queue(ring->tx_queue); | |
459 | priv->port_stats.wake_queue++; | |
c27a02cd | 460 | } |
0276a330 | 461 | return done; |
c27a02cd YP |
462 | } |
463 | ||
464 | void mlx4_en_tx_irq(struct mlx4_cq *mcq) | |
465 | { | |
466 | struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq); | |
467 | struct mlx4_en_priv *priv = netdev_priv(cq->dev); | |
c27a02cd | 468 | |
0276a330 EE |
469 | if (priv->port_up) |
470 | napi_schedule(&cq->napi); | |
471 | else | |
472 | mlx4_en_arm_cq(priv, cq); | |
c27a02cd YP |
473 | } |
474 | ||
0276a330 EE |
475 | /* TX CQ polling - called by NAPI */ |
476 | int mlx4_en_poll_tx_cq(struct napi_struct *napi, int budget) | |
477 | { | |
478 | struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi); | |
479 | struct net_device *dev = cq->dev; | |
480 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
481 | int done; | |
482 | ||
483 | done = mlx4_en_process_tx_cq(dev, cq, budget); | |
484 | ||
485 | /* If we used up all the quota - we're probably not done yet... */ | |
486 | if (done < budget) { | |
487 | /* Done for now */ | |
488 | napi_complete(napi); | |
489 | mlx4_en_arm_cq(priv, cq); | |
490 | return done; | |
491 | } | |
492 | return budget; | |
493 | } | |
c27a02cd | 494 | |
c27a02cd YP |
495 | static struct mlx4_en_tx_desc *mlx4_en_bounce_to_desc(struct mlx4_en_priv *priv, |
496 | struct mlx4_en_tx_ring *ring, | |
497 | u32 index, | |
498 | unsigned int desc_size) | |
499 | { | |
500 | u32 copy = (ring->size - index) * TXBB_SIZE; | |
501 | int i; | |
502 | ||
503 | for (i = desc_size - copy - 4; i >= 0; i -= 4) { | |
504 | if ((i & (TXBB_SIZE - 1)) == 0) | |
505 | wmb(); | |
506 | ||
507 | *((u32 *) (ring->buf + i)) = | |
508 | *((u32 *) (ring->bounce_buf + copy + i)); | |
509 | } | |
510 | ||
511 | for (i = copy - 4; i >= 4 ; i -= 4) { | |
512 | if ((i & (TXBB_SIZE - 1)) == 0) | |
513 | wmb(); | |
514 | ||
515 | *((u32 *) (ring->buf + index * TXBB_SIZE + i)) = | |
516 | *((u32 *) (ring->bounce_buf + i)); | |
517 | } | |
518 | ||
519 | /* Return real descriptor location */ | |
520 | return ring->buf + index * TXBB_SIZE; | |
521 | } | |
522 | ||
c27a02cd YP |
523 | static int is_inline(struct sk_buff *skb, void **pfrag) |
524 | { | |
525 | void *ptr; | |
526 | ||
527 | if (inline_thold && !skb_is_gso(skb) && skb->len <= inline_thold) { | |
528 | if (skb_shinfo(skb)->nr_frags == 1) { | |
311761c8 | 529 | ptr = skb_frag_address_safe(&skb_shinfo(skb)->frags[0]); |
c27a02cd YP |
530 | if (unlikely(!ptr)) |
531 | return 0; | |
532 | ||
533 | if (pfrag) | |
534 | *pfrag = ptr; | |
535 | ||
536 | return 1; | |
537 | } else if (unlikely(skb_shinfo(skb)->nr_frags)) | |
538 | return 0; | |
539 | else | |
540 | return 1; | |
541 | } | |
542 | ||
543 | return 0; | |
544 | } | |
545 | ||
546 | static int inline_size(struct sk_buff *skb) | |
547 | { | |
548 | if (skb->len + CTRL_SIZE + sizeof(struct mlx4_wqe_inline_seg) | |
549 | <= MLX4_INLINE_ALIGN) | |
550 | return ALIGN(skb->len + CTRL_SIZE + | |
551 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
552 | else | |
553 | return ALIGN(skb->len + CTRL_SIZE + 2 * | |
554 | sizeof(struct mlx4_wqe_inline_seg), 16); | |
555 | } | |
556 | ||
557 | static int get_real_size(struct sk_buff *skb, struct net_device *dev, | |
558 | int *lso_header_size) | |
559 | { | |
560 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
c27a02cd YP |
561 | int real_size; |
562 | ||
563 | if (skb_is_gso(skb)) { | |
837052d0 OG |
564 | if (skb->encapsulation) |
565 | *lso_header_size = (skb_inner_transport_header(skb) - skb->data) + inner_tcp_hdrlen(skb); | |
566 | else | |
567 | *lso_header_size = skb_transport_offset(skb) + tcp_hdrlen(skb); | |
c27a02cd YP |
568 | real_size = CTRL_SIZE + skb_shinfo(skb)->nr_frags * DS_SIZE + |
569 | ALIGN(*lso_header_size + 4, DS_SIZE); | |
570 | if (unlikely(*lso_header_size != skb_headlen(skb))) { | |
571 | /* We add a segment for the skb linear buffer only if | |
572 | * it contains data */ | |
573 | if (*lso_header_size < skb_headlen(skb)) | |
574 | real_size += DS_SIZE; | |
575 | else { | |
576 | if (netif_msg_tx_err(priv)) | |
453a6082 | 577 | en_warn(priv, "Non-linear headers\n"); |
c27a02cd YP |
578 | return 0; |
579 | } | |
580 | } | |
c27a02cd YP |
581 | } else { |
582 | *lso_header_size = 0; | |
583 | if (!is_inline(skb, NULL)) | |
584 | real_size = CTRL_SIZE + (skb_shinfo(skb)->nr_frags + 1) * DS_SIZE; | |
585 | else | |
586 | real_size = inline_size(skb); | |
587 | } | |
588 | ||
589 | return real_size; | |
590 | } | |
591 | ||
592 | static void build_inline_wqe(struct mlx4_en_tx_desc *tx_desc, struct sk_buff *skb, | |
593 | int real_size, u16 *vlan_tag, int tx_ind, void *fragptr) | |
594 | { | |
595 | struct mlx4_wqe_inline_seg *inl = &tx_desc->inl; | |
596 | int spc = MLX4_INLINE_ALIGN - CTRL_SIZE - sizeof *inl; | |
597 | ||
598 | if (skb->len <= spc) { | |
599 | inl->byte_count = cpu_to_be32(1 << 31 | skb->len); | |
600 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
601 | if (skb_shinfo(skb)->nr_frags) | |
602 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), fragptr, | |
9e903e08 | 603 | skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
604 | |
605 | } else { | |
606 | inl->byte_count = cpu_to_be32(1 << 31 | spc); | |
607 | if (skb_headlen(skb) <= spc) { | |
608 | skb_copy_from_linear_data(skb, inl + 1, skb_headlen(skb)); | |
609 | if (skb_headlen(skb) < spc) { | |
610 | memcpy(((void *)(inl + 1)) + skb_headlen(skb), | |
611 | fragptr, spc - skb_headlen(skb)); | |
612 | fragptr += spc - skb_headlen(skb); | |
613 | } | |
614 | inl = (void *) (inl + 1) + spc; | |
615 | memcpy(((void *)(inl + 1)), fragptr, skb->len - spc); | |
616 | } else { | |
617 | skb_copy_from_linear_data(skb, inl + 1, spc); | |
618 | inl = (void *) (inl + 1) + spc; | |
619 | skb_copy_from_linear_data_offset(skb, spc, inl + 1, | |
620 | skb_headlen(skb) - spc); | |
621 | if (skb_shinfo(skb)->nr_frags) | |
622 | memcpy(((void *)(inl + 1)) + skb_headlen(skb) - spc, | |
9e903e08 | 623 | fragptr, skb_frag_size(&skb_shinfo(skb)->frags[0])); |
c27a02cd YP |
624 | } |
625 | ||
626 | wmb(); | |
627 | inl->byte_count = cpu_to_be32(1 << 31 | (skb->len - spc)); | |
628 | } | |
c27a02cd YP |
629 | } |
630 | ||
f663dd9a | 631 | u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb, |
99932d4f | 632 | void *accel_priv, select_queue_fallback_t fallback) |
c27a02cd | 633 | { |
bc6a4744 | 634 | struct mlx4_en_priv *priv = netdev_priv(dev); |
d317966b | 635 | u16 rings_p_up = priv->num_tx_rings_p_up; |
bc6a4744 | 636 | u8 up = 0; |
c27a02cd | 637 | |
bc6a4744 AV |
638 | if (dev->num_tc) |
639 | return skb_tx_hash(dev, skb); | |
640 | ||
641 | if (vlan_tx_tag_present(skb)) | |
642 | up = vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT; | |
f813cad8 | 643 | |
99932d4f | 644 | return fallback(dev, skb) % rings_p_up + up * rings_p_up; |
c27a02cd YP |
645 | } |
646 | ||
966684d5 | 647 | static void mlx4_bf_copy(void __iomem *dst, unsigned long *src, unsigned bytecnt) |
87a5c389 YP |
648 | { |
649 | __iowrite64_copy(dst, src, bytecnt / 8); | |
650 | } | |
651 | ||
61357325 | 652 | netdev_tx_t mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev) |
c27a02cd YP |
653 | { |
654 | struct mlx4_en_priv *priv = netdev_priv(dev); | |
655 | struct mlx4_en_dev *mdev = priv->mdev; | |
237a3a3b | 656 | struct device *ddev = priv->ddev; |
c27a02cd | 657 | struct mlx4_en_tx_ring *ring; |
c27a02cd YP |
658 | struct mlx4_en_tx_desc *tx_desc; |
659 | struct mlx4_wqe_data_seg *data; | |
c27a02cd YP |
660 | struct mlx4_en_tx_info *tx_info; |
661 | int tx_ind = 0; | |
662 | int nr_txbb; | |
663 | int desc_size; | |
664 | int real_size; | |
87a5c389 | 665 | u32 index, bf_index; |
c27a02cd | 666 | __be32 op_own; |
f813cad8 | 667 | u16 vlan_tag = 0; |
c27a02cd YP |
668 | int i; |
669 | int lso_header_size; | |
670 | void *fragptr; | |
87a5c389 | 671 | bool bounce = false; |
c27a02cd | 672 | |
3005ad40 YP |
673 | if (!priv->port_up) |
674 | goto tx_drop; | |
675 | ||
c27a02cd YP |
676 | real_size = get_real_size(skb, dev, &lso_header_size); |
677 | if (unlikely(!real_size)) | |
7e230913 | 678 | goto tx_drop; |
c27a02cd | 679 | |
25985edc | 680 | /* Align descriptor to TXBB size */ |
c27a02cd YP |
681 | desc_size = ALIGN(real_size, TXBB_SIZE); |
682 | nr_txbb = desc_size / TXBB_SIZE; | |
683 | if (unlikely(nr_txbb > MAX_DESC_TXBBS)) { | |
684 | if (netif_msg_tx_err(priv)) | |
453a6082 | 685 | en_warn(priv, "Oversized header or SG list\n"); |
7e230913 | 686 | goto tx_drop; |
c27a02cd YP |
687 | } |
688 | ||
f813cad8 | 689 | tx_ind = skb->queue_mapping; |
41d942d5 | 690 | ring = priv->tx_ring[tx_ind]; |
eab6d18d | 691 | if (vlan_tx_tag_present(skb)) |
f813cad8 | 692 | vlan_tag = vlan_tx_tag_get(skb); |
c27a02cd YP |
693 | |
694 | /* Check available TXBBs And 2K spare for prefetch */ | |
695 | if (unlikely(((int)(ring->prod - ring->cons)) > | |
696 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
f813cad8 | 697 | /* every full Tx ring stops queue */ |
5b263f53 | 698 | netif_tx_stop_queue(ring->tx_queue); |
c27a02cd YP |
699 | priv->port_stats.queue_stopped++; |
700 | ||
72259225 AV |
701 | /* If queue was emptied after the if, and before the |
702 | * stop_queue - need to wake the queue, or else it will remain | |
703 | * stopped forever. | |
704 | * Need a memory barrier to make sure ring->cons was not | |
705 | * updated before queue was stopped. | |
706 | */ | |
707 | wmb(); | |
708 | ||
709 | if (unlikely(((int)(ring->prod - ring->cons)) <= | |
710 | ring->size - HEADROOM - MAX_DESC_TXBBS)) { | |
711 | netif_tx_wake_queue(ring->tx_queue); | |
712 | priv->port_stats.wake_queue++; | |
713 | } else { | |
714 | return NETDEV_TX_BUSY; | |
715 | } | |
c27a02cd YP |
716 | } |
717 | ||
c27a02cd YP |
718 | /* Track current inflight packets for performance analysis */ |
719 | AVG_PERF_COUNTER(priv->pstats.inflight_avg, | |
720 | (u32) (ring->prod - ring->cons - 1)); | |
721 | ||
722 | /* Packet is good - grab an index and transmit it */ | |
723 | index = ring->prod & ring->size_mask; | |
87a5c389 | 724 | bf_index = ring->prod; |
c27a02cd YP |
725 | |
726 | /* See if we have enough space for whole descriptor TXBB for setting | |
727 | * SW ownership on next descriptor; if not, use a bounce buffer. */ | |
728 | if (likely(index + nr_txbb <= ring->size)) | |
729 | tx_desc = ring->buf + index * TXBB_SIZE; | |
87a5c389 | 730 | else { |
c27a02cd | 731 | tx_desc = (struct mlx4_en_tx_desc *) ring->bounce_buf; |
87a5c389 YP |
732 | bounce = true; |
733 | } | |
c27a02cd YP |
734 | |
735 | /* Save skb in tx_info ring */ | |
736 | tx_info = &ring->tx_info[index]; | |
737 | tx_info->skb = skb; | |
738 | tx_info->nr_txbb = nr_txbb; | |
739 | ||
237a3a3b AV |
740 | if (lso_header_size) |
741 | data = ((void *)&tx_desc->lso + ALIGN(lso_header_size + 4, | |
742 | DS_SIZE)); | |
743 | else | |
744 | data = &tx_desc->data; | |
745 | ||
746 | /* valid only for none inline segments */ | |
747 | tx_info->data_offset = (void *)data - (void *)tx_desc; | |
748 | ||
749 | tx_info->linear = (lso_header_size < skb_headlen(skb) && | |
750 | !is_inline(skb, NULL)) ? 1 : 0; | |
751 | ||
752 | data += skb_shinfo(skb)->nr_frags + tx_info->linear - 1; | |
753 | ||
754 | if (is_inline(skb, &fragptr)) { | |
755 | tx_info->inl = 1; | |
756 | } else { | |
757 | /* Map fragments */ | |
758 | for (i = skb_shinfo(skb)->nr_frags - 1; i >= 0; i--) { | |
5f1cd200 AV |
759 | struct skb_frag_struct *frag; |
760 | dma_addr_t dma; | |
761 | ||
237a3a3b AV |
762 | frag = &skb_shinfo(skb)->frags[i]; |
763 | dma = skb_frag_dma_map(ddev, frag, | |
764 | 0, skb_frag_size(frag), | |
765 | DMA_TO_DEVICE); | |
766 | if (dma_mapping_error(ddev, dma)) | |
767 | goto tx_drop_unmap; | |
768 | ||
769 | data->addr = cpu_to_be64(dma); | |
770 | data->lkey = cpu_to_be32(mdev->mr.key); | |
771 | wmb(); | |
772 | data->byte_count = cpu_to_be32(skb_frag_size(frag)); | |
773 | --data; | |
774 | } | |
775 | ||
776 | /* Map linear part */ | |
777 | if (tx_info->linear) { | |
778 | u32 byte_count = skb_headlen(skb) - lso_header_size; | |
5f1cd200 AV |
779 | dma_addr_t dma; |
780 | ||
237a3a3b AV |
781 | dma = dma_map_single(ddev, skb->data + |
782 | lso_header_size, byte_count, | |
783 | PCI_DMA_TODEVICE); | |
784 | if (dma_mapping_error(ddev, dma)) | |
785 | goto tx_drop_unmap; | |
786 | ||
787 | data->addr = cpu_to_be64(dma); | |
788 | data->lkey = cpu_to_be32(mdev->mr.key); | |
789 | wmb(); | |
790 | data->byte_count = cpu_to_be32(byte_count); | |
791 | } | |
792 | tx_info->inl = 0; | |
793 | } | |
794 | ||
ec693d47 AV |
795 | /* |
796 | * For timestamping add flag to skb_shinfo and | |
797 | * set flag for further reference | |
798 | */ | |
799 | if (ring->hwtstamp_tx_type == HWTSTAMP_TX_ON && | |
800 | skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { | |
801 | skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; | |
802 | tx_info->ts_requested = 1; | |
803 | } | |
804 | ||
c27a02cd YP |
805 | /* Prepare ctrl segement apart opcode+ownership, which depends on |
806 | * whether LSO is used */ | |
807 | tx_desc->ctrl.vlan_tag = cpu_to_be16(vlan_tag); | |
c140d769 AV |
808 | tx_desc->ctrl.ins_vlan = MLX4_WQE_CTRL_INS_VLAN * |
809 | !!vlan_tx_tag_present(skb); | |
c27a02cd | 810 | tx_desc->ctrl.fence_size = (real_size / 16) & 0x3f; |
60d6fe99 | 811 | tx_desc->ctrl.srcrb_flags = priv->ctrl_flags; |
c27a02cd YP |
812 | if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { |
813 | tx_desc->ctrl.srcrb_flags |= cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM | | |
814 | MLX4_WQE_CTRL_TCP_UDP_CSUM); | |
ad04378c | 815 | ring->tx_csum++; |
c27a02cd YP |
816 | } |
817 | ||
79aeaccd | 818 | if (priv->flags & MLX4_EN_FLAG_ENABLE_HW_LOOPBACK) { |
5f1cd200 AV |
819 | struct ethhdr *ethh; |
820 | ||
213815a1 YB |
821 | /* Copy dst mac address to wqe. This allows loopback in eSwitch, |
822 | * so that VFs and PF can communicate with each other | |
823 | */ | |
824 | ethh = (struct ethhdr *)skb->data; | |
825 | tx_desc->ctrl.srcrb_flags16[0] = get_unaligned((__be16 *)ethh->h_dest); | |
826 | tx_desc->ctrl.imm = get_unaligned((__be32 *)(ethh->h_dest + 2)); | |
827 | } | |
828 | ||
c27a02cd YP |
829 | /* Handle LSO (TSO) packets */ |
830 | if (lso_header_size) { | |
831 | /* Mark opcode as LSO */ | |
832 | op_own = cpu_to_be32(MLX4_OPCODE_LSO | (1 << 6)) | | |
833 | ((ring->prod & ring->size) ? | |
834 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
835 | ||
836 | /* Fill in the LSO prefix */ | |
837 | tx_desc->lso.mss_hdr_size = cpu_to_be32( | |
838 | skb_shinfo(skb)->gso_size << 16 | lso_header_size); | |
839 | ||
840 | /* Copy headers; | |
841 | * note that we already verified that it is linear */ | |
842 | memcpy(tx_desc->lso.header, skb->data, lso_header_size); | |
c27a02cd YP |
843 | |
844 | priv->port_stats.tso_packets++; | |
845 | i = ((skb->len - lso_header_size) / skb_shinfo(skb)->gso_size) + | |
846 | !!((skb->len - lso_header_size) % skb_shinfo(skb)->gso_size); | |
5b263f53 | 847 | tx_info->nr_bytes = skb->len + (i - 1) * lso_header_size; |
c27a02cd YP |
848 | ring->packets += i; |
849 | } else { | |
850 | /* Normal (Non LSO) packet */ | |
851 | op_own = cpu_to_be32(MLX4_OPCODE_SEND) | | |
852 | ((ring->prod & ring->size) ? | |
853 | cpu_to_be32(MLX4_EN_BIT_DESC_OWN) : 0); | |
5b263f53 | 854 | tx_info->nr_bytes = max_t(unsigned int, skb->len, ETH_ZLEN); |
c27a02cd YP |
855 | ring->packets++; |
856 | ||
857 | } | |
5b263f53 YP |
858 | ring->bytes += tx_info->nr_bytes; |
859 | netdev_tx_sent_queue(ring->tx_queue, tx_info->nr_bytes); | |
c27a02cd YP |
860 | AVG_PERF_COUNTER(priv->pstats.tx_pktsz_avg, skb->len); |
861 | ||
237a3a3b | 862 | if (tx_info->inl) { |
c27a02cd | 863 | build_inline_wqe(tx_desc, skb, real_size, &vlan_tag, tx_ind, fragptr); |
41efea5a YP |
864 | tx_info->inl = 1; |
865 | } | |
c27a02cd | 866 | |
837052d0 OG |
867 | if (skb->encapsulation) { |
868 | struct iphdr *ipv4 = (struct iphdr *)skb_inner_network_header(skb); | |
869 | if (ipv4->protocol == IPPROTO_TCP || ipv4->protocol == IPPROTO_UDP) | |
870 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP | MLX4_WQE_CTRL_ILP); | |
871 | else | |
872 | op_own |= cpu_to_be32(MLX4_WQE_CTRL_IIP); | |
873 | } | |
874 | ||
c27a02cd YP |
875 | ring->prod += nr_txbb; |
876 | ||
877 | /* If we used a bounce buffer then copy descriptor back into place */ | |
87a5c389 | 878 | if (bounce) |
c27a02cd YP |
879 | tx_desc = mlx4_en_bounce_to_desc(priv, ring, index, desc_size); |
880 | ||
eb0cabbd AV |
881 | skb_tx_timestamp(skb); |
882 | ||
2b39a061 | 883 | if (ring->bf_enabled && desc_size <= MAX_BF && !bounce && !vlan_tx_tag_present(skb)) { |
c5d6136e | 884 | *(__be32 *) (&tx_desc->ctrl.vlan_tag) |= cpu_to_be32(ring->doorbell_qpn); |
87a5c389 YP |
885 | op_own |= htonl((bf_index & 0xffff) << 8); |
886 | /* Ensure new descirptor hits memory | |
887 | * before setting ownership of this descriptor to HW */ | |
888 | wmb(); | |
889 | tx_desc->ctrl.owner_opcode = op_own; | |
c27a02cd | 890 | |
87a5c389 YP |
891 | wmb(); |
892 | ||
893 | mlx4_bf_copy(ring->bf.reg + ring->bf.offset, (unsigned long *) &tx_desc->ctrl, | |
894 | desc_size); | |
895 | ||
896 | wmb(); | |
897 | ||
898 | ring->bf.offset ^= ring->bf.buf_size; | |
899 | } else { | |
900 | /* Ensure new descirptor hits memory | |
901 | * before setting ownership of this descriptor to HW */ | |
902 | wmb(); | |
903 | tx_desc->ctrl.owner_opcode = op_own; | |
904 | wmb(); | |
c5d6136e | 905 | iowrite32be(ring->doorbell_qpn, ring->bf.uar->map + MLX4_SEND_DOORBELL); |
87a5c389 | 906 | } |
c27a02cd | 907 | |
ec634fe3 | 908 | return NETDEV_TX_OK; |
7e230913 | 909 | |
237a3a3b AV |
910 | tx_drop_unmap: |
911 | en_err(priv, "DMA mapping error\n"); | |
912 | ||
913 | for (i++; i < skb_shinfo(skb)->nr_frags; i++) { | |
914 | data++; | |
915 | dma_unmap_page(ddev, (dma_addr_t) be64_to_cpu(data->addr), | |
916 | be32_to_cpu(data->byte_count), | |
917 | PCI_DMA_TODEVICE); | |
918 | } | |
919 | ||
7e230913 YP |
920 | tx_drop: |
921 | dev_kfree_skb_any(skb); | |
922 | priv->stats.tx_dropped++; | |
923 | return NETDEV_TX_OK; | |
c27a02cd YP |
924 | } |
925 |