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net/mlx4: Change QP allocation scheme
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567 138 [9] = "Device managed flow steering IPoIB support",
114840c3 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 142 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c 143 [14] = "Ethernet protocol control support",
d475c95b 144 [15] = "Ethernet Backplane autoneg support",
7ae0e400 145 [16] = "CONFIG DEV support",
de966c59
MB		 146 [17] = "Asymmetric EQs support",
147 [18] = "More than 80 VFs support"
b3416f44
SP		 148 };
149 int i;
150
151 for (i = 0; i < ARRAY_SIZE(fname); ++i)
152 if (fname[i] && (flags & (1LL << i)))
153 mlx4_dbg(dev, " %s\n", fname[i]);
154}
155
2d928651
VS		 156int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
157{
158 struct mlx4_cmd_mailbox *mailbox;
159 u32 *inbox;
160 int err = 0;
161
162#define MOD_STAT_CFG_IN_SIZE 0x100
163
164#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
165#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
166
167 mailbox = mlx4_alloc_cmd_mailbox(dev);
168 if (IS_ERR(mailbox))
169 return PTR_ERR(mailbox);
170 inbox = mailbox->buf;
171
2d928651
VS		 172 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
173 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
174
175 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 176 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 177
178 mlx4_free_cmd_mailbox(dev, mailbox);
179 return err;
180}
181
e8c4265b
MB		 182int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave)
183{
184 struct mlx4_cmd_mailbox *mailbox;
185 u32 *outbox;
186 u8 in_modifier;
187 u8 field;
188 u16 field16;
189 int err;
190
191#define QUERY_FUNC_BUS_OFFSET 0x00
192#define QUERY_FUNC_DEVICE_OFFSET 0x01
193#define QUERY_FUNC_FUNCTION_OFFSET 0x01
194#define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03
195#define QUERY_FUNC_RSVD_EQS_OFFSET 0x04
196#define QUERY_FUNC_MAX_EQ_OFFSET 0x06
197#define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b
198
199 mailbox = mlx4_alloc_cmd_mailbox(dev);
200 if (IS_ERR(mailbox))
201 return PTR_ERR(mailbox);
202 outbox = mailbox->buf;
203
204 in_modifier = slave;
e8c4265b
MB		 205
206 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0,
207 MLX4_CMD_QUERY_FUNC,
208 MLX4_CMD_TIME_CLASS_A,
209 MLX4_CMD_NATIVE);
210 if (err)
211 goto out;
212
213 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
214 func->bus = field & 0xf;
215 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
216 func->device = field & 0xf1;
217 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
218 func->function = field & 0x7;
219 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
220 func->physical_function = field & 0xf;
221 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
222 func->rsvd_eqs = field16 & 0xffff;
223 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
224 func->max_eq = field16 & 0xffff;
225 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
226 func->rsvd_uars = field & 0x0f;
227
228 mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n",
229 func->bus, func->device, func->function, func->physical_function,
230 func->max_eq, func->rsvd_eqs, func->rsvd_uars);
231
232out:
233 mlx4_free_cmd_mailbox(dev, mailbox);
234 return err;
235}
236
5cc914f1
MA		 237int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
238 struct mlx4_vhcr *vhcr,
239 struct mlx4_cmd_mailbox *inbox,
240 struct mlx4_cmd_mailbox *outbox,
241 struct mlx4_cmd_info *cmd)
242{
5a0d0a61 243 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 244 u8 field, port;
245 u32 size, proxy_qp, qkey;
5cc914f1 246 int err = 0;
7ae0e400 247 struct mlx4_func func;
5cc914f1
MA		 248
249#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
250#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 251#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 252#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 253#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
254#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
255#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
256#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
257#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
258#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 259#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 260#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 261
eb456a68
JM		 262#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
263#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
264#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
265#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
266#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
267#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
268
ddae0349
EE		 269#define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c
270
105c320f
JM		 271#define QUERY_FUNC_CAP_FMR_FLAG 0x80
272#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
273#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 274#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
ddae0349
EE		 275#define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04
276
277#define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31)
105c320f
JM		 278
279/* when opcode modifier = 1 */
5cc914f1 280#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 281#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 282#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
283#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 284
47605df9
JM		 285#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
286#define QUERY_FUNC_CAP_QP0_PROXY 0x14
287#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
288#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 289#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 290
73e74ab4
HHZ		 291#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
292#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 293#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 294#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 295
73e74ab4 296#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
7ae0e400 297#define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31)
105c320f 298
5cc914f1 299 if (vhcr->op_modifier == 1) {
449fc488
MB		 300 struct mlx4_active_ports actv_ports =
301 mlx4_get_active_ports(dev, slave);
302 int converted_port = mlx4_slave_convert_port(
303 dev, slave, vhcr->in_modifier);
304
305 if (converted_port < 0)
306 return -EINVAL;
307
308 vhcr->in_modifier = converted_port;
449fc488
MB		 309 /* phys-port = logical-port */
310 field = vhcr->in_modifier -
311 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 312 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
313
99ec41d0
JM		 314 port = vhcr->in_modifier;
315 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
316
317 /* Set nic_info bit to mark new fields support */
318 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
319
320 if (mlx4_vf_smi_enabled(dev, slave, port) &&
321 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
322 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
323 MLX4_PUT(outbox->buf, qkey,
324 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
325 }
326 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
327
47605df9 328 /* size is now the QP number */
99ec41d0 329 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 330 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
331
332 size += 2;
333 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
334
99ec41d0
JM		 335 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
336 proxy_qp += 2;
337 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 338
8e1a28e8
HHZ		 339 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
340 QUERY_FUNC_CAP_PHYS_PORT_ID);
341
5cc914f1 342 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 343 struct mlx4_active_ports actv_ports =
344 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 345 /* enable rdma and ethernet interfaces, and new quota locations */
346 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
ddae0349 347 QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX);
5cc914f1
MA		 348 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
349
449fc488
MB		 350 field = min(
351 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
352 dev->caps.num_ports);
5cc914f1
MA		 353 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
354
08ff3235 355 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 356 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
357
105c320f
JM		 358 field = 0; /* protected FMR support not available as yet */
359 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
360
5a0d0a61 361 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 362 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 363 size = dev->caps.num_qps;
364 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 365
5a0d0a61 366 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 367 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 368 size = dev->caps.num_srqs;
369 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 370
5a0d0a61 371 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 372 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 373 size = dev->caps.num_cqs;
374 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1 375
7ae0e400
MB		 376 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) ||
377 mlx4_QUERY_FUNC(dev, &func, slave)) {
378 size = vhcr->in_modifier &
379 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
380 dev->caps.num_eqs :
381 rounddown_pow_of_two(dev->caps.num_eqs);
382 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
383 size = dev->caps.reserved_eqs;
384 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
385 } else {
386 size = vhcr->in_modifier &
387 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ?
388 func.max_eq :
389 rounddown_pow_of_two(func.max_eq);
390 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
391 size = func.rsvd_eqs;
392 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
393 }
5cc914f1 394
5a0d0a61 395 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 396 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 397 size = dev->caps.num_mpts;
398 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 399
5a0d0a61 400 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 401 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 402 size = dev->caps.num_mtts;
403 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 404
405 size = dev->caps.num_mgms + dev->caps.num_amgms;
406 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 407 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1 408
ddae0349
EE		 409 size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG;
410 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
5cc914f1
MA		 411 } else
412 err = -EINVAL;
413
414 return err;
415}
416
225c6c8c 417int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port,
47605df9 418 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 419{
420 struct mlx4_cmd_mailbox *mailbox;
421 u32 *outbox;
47605df9 422 u8 field, op_modifier;
99ec41d0 423 u32 size, qkey;
eb456a68 424 int err = 0, quotas = 0;
7ae0e400 425 u32 in_modifier;
5cc914f1 426
47605df9 427 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
7ae0e400
MB		 428 in_modifier = op_modifier ? gen_or_port :
429 QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS;
5cc914f1
MA		 430
431 mailbox = mlx4_alloc_cmd_mailbox(dev);
432 if (IS_ERR(mailbox))
433 return PTR_ERR(mailbox);
434
7ae0e400 435 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier,
47605df9 436 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 437 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
438 if (err)
439 goto out;
440
441 outbox = mailbox->buf;
442
47605df9
JM		 443 if (!op_modifier) {
444 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
445 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
446 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
447 err = -EPROTONOSUPPORT;
448 goto out;
449 }
450 func_cap->flags = field;
eb456a68 451 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 452
47605df9
JM		 453 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
454 func_cap->num_ports = field;
5cc914f1 455
47605df9
JM		 456 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
457 func_cap->pf_context_behaviour = size;
5cc914f1 458
eb456a68
JM		 459 if (quotas) {
460 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
461 func_cap->qp_quota = size & 0xFFFFFF;
462
463 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
464 func_cap->srq_quota = size & 0xFFFFFF;
465
466 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
467 func_cap->cq_quota = size & 0xFFFFFF;
468
469 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
470 func_cap->mpt_quota = size & 0xFFFFFF;
471
472 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
473 func_cap->mtt_quota = size & 0xFFFFFF;
474
475 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
476 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 477
eb456a68
JM		 478 } else {
479 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
480 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 481
eb456a68
JM		 482 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
483 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 484
eb456a68
JM		 485 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
486 func_cap->cq_quota = size & 0xFFFFFF;
487
488 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
489 func_cap->mpt_quota = size & 0xFFFFFF;
490
491 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
492 func_cap->mtt_quota = size & 0xFFFFFF;
493
494 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
495 func_cap->mcg_quota = size & 0xFFFFFF;
496 }
47605df9
JM		 497 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
498 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 499
47605df9
JM		 500 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
501 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 502
ddae0349
EE		 503 func_cap->extra_flags = 0;
504
505 /* Mailbox data from 0x6c and onward should only be treated if
506 * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags
507 */
508 if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) {
509 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
510 if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG)
511 func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP;
512 }
513
47605df9
JM		 514 goto out;
515 }
5cc914f1 516
47605df9
JM		 517 /* logical port query */
518 if (gen_or_port > dev->caps.num_ports) {
519 err = -EINVAL;
520 goto out;
521 }
5cc914f1 522
eb17711b 523 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 524 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 525 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 526 mlx4_err(dev, "VLAN is enforced on this port\n");
527 err = -EPROTONOSUPPORT;
5cc914f1 528 goto out;
47605df9 529 }
5cc914f1 530
eb17711b 531 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 532 mlx4_err(dev, "Force mac is enabled on this port\n");
533 err = -EPROTONOSUPPORT;
534 goto out;
5cc914f1 535 }
47605df9 536 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 537 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
538 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 539 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 540 err = -EPROTONOSUPPORT;
541 goto out;
542 }
543 }
5cc914f1 544
47605df9
JM		 545 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
546 func_cap->physical_port = field;
547 if (func_cap->physical_port != gen_or_port) {
548 err = -ENOSYS;
549 goto out;
5cc914f1
MA		 550 }
551
99ec41d0
JM		 552 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
553 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
554 func_cap->qp0_qkey = qkey;
555 } else {
556 func_cap->qp0_qkey = 0;
557 }
558
47605df9
JM		 559 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
560 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
561
562 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
563 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
564
565 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
566 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
567
568 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
569 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
570
8e1a28e8
HHZ		 571 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
572 MLX4_GET(func_cap->phys_port_id, outbox,
573 QUERY_FUNC_CAP_PHYS_PORT_ID);
574
5cc914f1
MA		 575 /* All other resources are allocated by the master, but we still report
576 * 'num' and 'reserved' capabilities as follows:
577 * - num remains the maximum resource index
578 * - 'num - reserved' is the total available objects of a resource, but
579 * resource indices may be less than 'reserved'
580 * TODO: set per-resource quotas */
581
582out:
583 mlx4_free_cmd_mailbox(dev, mailbox);
584
585 return err;
586}
587
225c7b1f
RD		 588int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
589{
590 struct mlx4_cmd_mailbox *mailbox;
591 u32 *outbox;
592 u8 field;
ccf86321 593 u32 field32, flags, ext_flags;
225c7b1f
RD		 594 u16 size;
595 u16 stat_rate;
596 int err;
5ae2a7a8 597 int i;
225c7b1f
RD		 598
599#define QUERY_DEV_CAP_OUT_SIZE 0x100
600#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
601#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
602#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
603#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
604#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
605#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
606#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
607#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
608#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
609#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
610#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
611#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
612#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
613#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
614#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
615#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
616#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
617#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
7ae0e400 618#define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26
225c7b1f
RD		 619#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
620#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
621#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 622#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 623#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 624#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
625#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
626#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
627#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
628#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 629#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 630#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
631#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 632#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 633#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 634#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 635#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
636#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
637#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
638#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
639#define QUERY_DEV_CAP_BF_OFFSET 0x4c
640#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
641#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
642#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
643#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
644#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
645#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
646#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
647#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
648#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
649#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
650#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
651#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 652#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
653#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 654#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 655#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 656#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 657#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
658#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 659#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 660#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 661#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
662#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
663#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
664#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
665#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
666#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
667#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
668#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
669#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
670#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 671#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
d475c95b 672#define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94
225c7b1f
RD		 673#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
674#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 675#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 676#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 677#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 678#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
225c7b1f 679
b3416f44 680 dev_cap->flags2 = 0;
225c7b1f
RD		 681 mailbox = mlx4_alloc_cmd_mailbox(dev);
682 if (IS_ERR(mailbox))
683 return PTR_ERR(mailbox);
684 outbox = mailbox->buf;
685
686 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 687 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 688 if (err)
689 goto out;
690
691 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
692 dev_cap->reserved_qps = 1 << (field & 0xf);
693 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
694 dev_cap->max_qps = 1 << (field & 0x1f);
695 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
696 dev_cap->reserved_srqs = 1 << (field >> 4);
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
698 dev_cap->max_srqs = 1 << (field & 0x1f);
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
700 dev_cap->max_cq_sz = 1 << field;
701 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
702 dev_cap->reserved_cqs = 1 << (field & 0xf);
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
704 dev_cap->max_cqs = 1 << (field & 0x1f);
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
706 dev_cap->max_mpts = 1 << (field & 0x3f);
707 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
7c68dd43 708 dev_cap->reserved_eqs = 1 << (field & 0xf);
225c7b1f 709 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 710 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 711 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
712 dev_cap->reserved_mtts = 1 << (field >> 4);
713 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
714 dev_cap->max_mrw_sz = 1 << field;
715 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
716 dev_cap->reserved_mrws = 1 << (field & 0xf);
717 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
718 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
7ae0e400
MB		 719 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
720 dev_cap->num_sys_eqs = size & 0xfff;
225c7b1f
RD		 721 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
722 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
723 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
724 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
726 field &= 0x1f;
727 if (!field)
728 dev_cap->max_gso_sz = 0;
729 else
730 dev_cap->max_gso_sz = 1 << field;
731
b3416f44
SP		 732 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
733 if (field & 0x20)
734 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
735 if (field & 0x10)
736 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
737 field &= 0xf;
738 if (field) {
739 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
740 dev_cap->max_rss_tbl_sz = 1 << field;
741 } else
742 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 743 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
744 dev_cap->max_rdma_global = 1 << (field & 0x3f);
745 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
746 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 747 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 748 dev_cap->num_ports = field & 0xf;
149983af
DB		 749 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
750 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 751 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
752 if (field & 0x80)
753 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
754 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 755 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
756 if (field & 0x80)
757 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 758 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
759 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 760 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
761 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 762 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
763 if (field & 0x80)
764 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 765 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 766 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 767 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 768 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
769 dev_cap->reserved_uars = field >> 4;
770 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
771 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
772 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
773 dev_cap->min_page_sz = 1 << field;
774
775 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
776 if (field & 0x80) {
777 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
778 dev_cap->bf_reg_size = 1 << (field & 0x1f);
779 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 780 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 781 field = 3;
225c7b1f
RD		 782 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
783 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
784 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
785 } else {
786 dev_cap->bf_reg_size = 0;
787 mlx4_dbg(dev, "BlueFlame not available\n");
788 }
789
790 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
791 dev_cap->max_sq_sg = field;
792 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
793 dev_cap->max_sq_desc_sz = size;
794
795 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
796 dev_cap->max_qp_per_mcg = 1 << field;
797 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
798 dev_cap->reserved_mgms = field & 0xf;
799 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
800 dev_cap->max_mcgs = 1 << field;
801 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
802 dev_cap->reserved_pds = field >> 4;
803 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
804 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 805 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
806 dev_cap->reserved_xrcds = field >> 4;
426dd00d 807 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 808 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 809
810 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
811 dev_cap->rdmarc_entry_sz = size;
812 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
813 dev_cap->qpc_entry_sz = size;
814 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
815 dev_cap->aux_entry_sz = size;
816 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
817 dev_cap->altc_entry_sz = size;
818 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
819 dev_cap->eqc_entry_sz = size;
820 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
821 dev_cap->cqc_entry_sz = size;
822 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
823 dev_cap->srq_entry_sz = size;
824 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
825 dev_cap->cmpt_entry_sz = size;
826 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
827 dev_cap->mtt_entry_sz = size;
828 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
829 dev_cap->dmpt_entry_sz = size;
830
831 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
832 dev_cap->max_srq_sz = 1 << field;
833 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
834 dev_cap->max_qp_sz = 1 << field;
835 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
836 dev_cap->resize_srq = field & 1;
837 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
838 dev_cap->max_rq_sg = field;
839 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
840 dev_cap->max_rq_desc_sz = size;
77507aa2 841 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 842 if (field & (1 << 5))
843 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 844 if (field & (1 << 6))
845 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
846 if (field & (1 << 7))
847 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 848 MLX4_GET(dev_cap->bmme_flags, outbox,
849 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
d475c95b
MB		 850 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
851 if (field & 0x20)
852 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV;
225c7b1f
RD		 853 MLX4_GET(dev_cap->reserved_lkey, outbox,
854 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 855 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
856 if (field32 & (1 << 0))
857 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
955154fa
MB		 858 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
859 if (field & 1<<6)
5930e8d0 860 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 861 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
862 if (field & 1<<3)
863 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 864 MLX4_GET(dev_cap->max_icm_sz, outbox,
865 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 866 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
867 MLX4_GET(dev_cap->max_counters, outbox,
868 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 869
114840c3
JM		 870 MLX4_GET(field32, outbox,
871 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
872 if (field32 & (1 << 0))
873 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
874
3f7fb021 875 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 876 if (field32 & (1 << 16))
877 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 878 if (field32 & (1 << 26))
879 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 880 if (field32 & (1 << 20))
881 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
de966c59
MB		 882 if (field32 & (1 << 21))
883 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS;
3f7fb021 884
5ae2a7a8
RD		 885 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
886 for (i = 1; i <= dev_cap->num_ports; ++i) {
887 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
888 dev_cap->max_vl[i] = field >> 4;
889 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 890 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 891 dev_cap->max_port_width[i] = field & 0xf;
892 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
893 dev_cap->max_gids[i] = 1 << (field & 0xf);
894 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
895 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
896 }
897 } else {
7ff93f8b 898#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 899#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 900#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 901#define QUERY_PORT_WIDTH_OFFSET 0x06
902#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 903#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 904#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 905#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 906#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
907#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
908#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 909
910 for (i = 1; i <= dev_cap->num_ports; ++i) {
911 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 912 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 913 if (err)
914 goto out;
915
7ff93f8b
YP		 916 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
917 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 918 dev_cap->suggested_type[i] = (field >> 3) & 1;
919 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 920 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 921 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 922 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
923 dev_cap->max_port_width[i] = field & 0xf;
924 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
925 dev_cap->max_gids[i] = 1 << (field >> 4);
926 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
927 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
928 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 929 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
930 dev_cap->log_max_macs[i] = field & 0xf;
931 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 932 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
933 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 934 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
935 dev_cap->trans_type[i] = field32 >> 24;
936 dev_cap->vendor_oui[i] = field32 & 0xffffff;
937 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
938 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 939 }
940 }
941
95d04f07
RD		 942 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
943 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 944
945 /*
946 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
947 * we can't use any EQs whose doorbell falls on that page,
948 * even if the EQ itself isn't reserved.
949 */
7ae0e400
MB		 950 if (dev_cap->num_sys_eqs == 0)
951 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
952 dev_cap->reserved_eqs);
953 else
954 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS;
225c7b1f
RD		 955
956 mlx4_dbg(dev, "Max ICM size %lld MB\n",
957 (unsigned long long) dev_cap->max_icm_sz >> 20);
958 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
959 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
960 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
961 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
962 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
963 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
7ae0e400
MB		 964 mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n",
965 dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs,
966 dev_cap->eqc_entry_sz);
225c7b1f
RD		 967 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
968 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
969 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
970 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
971 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
972 dev_cap->max_pds, dev_cap->reserved_mgms);
973 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
974 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
975 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 976 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 977 dev_cap->max_port_width[1]);
225c7b1f
RD		 978 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
979 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
980 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
981 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 982 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 983 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 984 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 985
986 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 987 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 988
989out:
990 mlx4_free_cmd_mailbox(dev, mailbox);
991 return err;
992}
993
383677da
OG		 994#define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26)
995#define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21)
996#define DEV_CAP_EXT_2_FLAG_FSM (1 << 20)
997
b91cb3eb
JM		 998int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
999 struct mlx4_vhcr *vhcr,
1000 struct mlx4_cmd_mailbox *inbox,
1001 struct mlx4_cmd_mailbox *outbox,
1002 struct mlx4_cmd_info *cmd)
1003{
2a4fae14 1004 u64 flags;
b91cb3eb
JM		 1005 int err = 0;
1006 u8 field;
383677da 1007 u32 bmme_flags, field32;
449fc488
MB		 1008 int real_port;
1009 int slave_port;
1010 int first_port;
1011 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 1012
1013 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1014 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1015 if (err)
1016 return err;
1017
cc1ade94
SM		 1018 /* add port mng change event capability and disable mw type 1
1019 * unconditionally to slaves
1020 */
2a4fae14
JM		 1021 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1022 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 1023 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 1024 actv_ports = mlx4_get_active_ports(dev, slave);
1025 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
1026 for (slave_port = 0, real_port = first_port;
1027 real_port < first_port +
1028 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
1029 ++real_port, ++slave_port) {
1030 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
1031 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
1032 else
1033 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
1034 }
1035 for (; slave_port < dev->caps.num_ports; ++slave_port)
1036 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 1037 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1038
449fc488
MB		 1039 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1040 field &= ~0x0F;
1041 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
1042 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1043
30b40c31
AV		 1044 /* For guests, disable timestamp */
1045 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1046 field &= 0x7f;
1047 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1048
7ffdf726 1049 /* For guests, disable vxlan tunneling */
57352ef4 1050 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 1051 field &= 0xf7;
1052 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1053
b91cb3eb
JM		 1054 /* For guests, report Blueflame disabled */
1055 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1056 field &= 0x7f;
1057 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1058
cc1ade94 1059 /* For guests, disable mw type 2 */
57352ef4 1060 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 1061 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
1062 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1063
0081c8f3
JM		 1064 /* turn off device-managed steering capability if not enabled */
1065 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1066 MLX4_GET(field, outbox->buf,
1067 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1068 field &= 0x7f;
1069 MLX4_PUT(outbox->buf, field,
1070 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
1071 }
4de65803
MB		 1072
1073 /* turn off ipoib managed steering for guests */
57352ef4 1074 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 1075 field &= ~0x80;
1076 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1077
383677da
OG		 1078 /* turn off host side virt features (VST, FSM, etc) for guests */
1079 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1080 field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS |
1081 DEV_CAP_EXT_2_FLAG_FSM);
1082 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1083
b91cb3eb
JM		 1084 return 0;
1085}
1086
5cc914f1
MA		 1087int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1088 struct mlx4_vhcr *vhcr,
1089 struct mlx4_cmd_mailbox *inbox,
1090 struct mlx4_cmd_mailbox *outbox,
1091 struct mlx4_cmd_info *cmd)
1092{
0eb62b93 1093 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 1094 u64 def_mac;
1095 u8 port_type;
6634961c 1096 u16 short_field;
5cc914f1 1097 int err;
948e306d 1098 int admin_link_state;
449fc488
MB		 1099 int port = mlx4_slave_convert_port(dev, slave,
1100 vhcr->in_modifier & 0xFF);
5cc914f1 1101
105c320f 1102#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 1103#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 1104#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
1105#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 1106
449fc488
MB		 1107 if (port < 0)
1108 return -EINVAL;
1109
a7401b9c
JM		 1110 /* Protect against untrusted guests: enforce that this is the
1111 * QUERY_PORT general query.
1112 */
1113 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
1114 return -EINVAL;
1115
1116 vhcr->in_modifier = port;
449fc488 1117
5cc914f1
MA		 1118 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1119 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1120 MLX4_CMD_NATIVE);
1121
1122 if (!err && dev->caps.function != slave) {
0508ad64 1123 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1124 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1125
1126 /* get port type - currently only eth is enabled */
1127 MLX4_GET(port_type, outbox->buf,
1128 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1129
105c320f
JM		 1130 /* No link sensing allowed */
1131 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1132 /* set port type to currently operating port type */
1133 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1134
948e306d
RE		 1135 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1136 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1137 port_type |= MLX4_PORT_LINK_UP_MASK;
1138 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1139 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1140
5cc914f1
MA		 1141 MLX4_PUT(outbox->buf, port_type,
1142 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1143
b6ffaeff 1144 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1145 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1146 else
1147 short_field = 1; /* slave max gids */
6634961c
JM		 1148 MLX4_PUT(outbox->buf, short_field,
1149 QUERY_PORT_CUR_MAX_GID_OFFSET);
1150
1151 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1152 MLX4_PUT(outbox->buf, short_field,
1153 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1154 }
1155
1156 return err;
1157}
1158
6634961c
JM		 1159int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1160 int *gid_tbl_len, int *pkey_tbl_len)
1161{
1162 struct mlx4_cmd_mailbox *mailbox;
1163 u32 *outbox;
1164 u16 field;
1165 int err;
1166
1167 mailbox = mlx4_alloc_cmd_mailbox(dev);
1168 if (IS_ERR(mailbox))
1169 return PTR_ERR(mailbox);
1170
1171 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1172 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1173 MLX4_CMD_WRAPPED);
1174 if (err)
1175 goto out;
1176
1177 outbox = mailbox->buf;
1178
1179 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1180 *gid_tbl_len = field;
1181
1182 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1183 *pkey_tbl_len = field;
1184
1185out:
1186 mlx4_free_cmd_mailbox(dev, mailbox);
1187 return err;
1188}
1189EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1190
225c7b1f
RD		 1191int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1192{
1193 struct mlx4_cmd_mailbox *mailbox;
1194 struct mlx4_icm_iter iter;
1195 __be64 *pages;
1196 int lg;
1197 int nent = 0;
1198 int i;
1199 int err = 0;
1200 int ts = 0, tc = 0;
1201
1202 mailbox = mlx4_alloc_cmd_mailbox(dev);
1203 if (IS_ERR(mailbox))
1204 return PTR_ERR(mailbox);
225c7b1f
RD		 1205 pages = mailbox->buf;
1206
1207 for (mlx4_icm_first(icm, &iter);
1208 !mlx4_icm_last(&iter);
1209 mlx4_icm_next(&iter)) {
1210 /*
1211 * We have to pass pages that are aligned to their
1212 * size, so find the least significant 1 in the
1213 * address or size and use that as our log2 size.
1214 */
1215 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1216 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1217 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1218 MLX4_ICM_PAGE_SIZE,
1219 (unsigned long long) mlx4_icm_addr(&iter),
1220 mlx4_icm_size(&iter));
225c7b1f
RD		 1221 err = -EINVAL;
1222 goto out;
1223 }
1224
1225 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1226 if (virt != -1) {
1227 pages[nent * 2] = cpu_to_be64(virt);
1228 virt += 1 << lg;
1229 }
1230
1231 pages[nent * 2 + 1] =
1232 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1233 (lg - MLX4_ICM_PAGE_SHIFT));
1234 ts += 1 << (lg - 10);
1235 ++tc;
1236
1237 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1238 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1239 MLX4_CMD_TIME_CLASS_B,
1240 MLX4_CMD_NATIVE);
225c7b1f
RD		 1241 if (err)
1242 goto out;
1243 nent = 0;
1244 }
1245 }
1246 }
1247
1248 if (nent)
f9baff50
JM		 1249 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1250 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1251 if (err)
1252 goto out;
1253
1254 switch (op) {
1255 case MLX4_CMD_MAP_FA:
1a91de28 1256 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1257 break;
1258 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1259 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1260 break;
1261 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1262 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1263 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1264 break;
1265 }
1266
1267out:
1268 mlx4_free_cmd_mailbox(dev, mailbox);
1269 return err;
1270}
1271
1272int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1273{
1274 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1275}
1276
1277int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1278{
f9baff50
JM		 1279 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1280 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1281}
1282
1283
1284int mlx4_RUN_FW(struct mlx4_dev *dev)
1285{
f9baff50
JM		 1286 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1287 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1288}
1289
1290int mlx4_QUERY_FW(struct mlx4_dev *dev)
1291{
1292 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1293 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1294 struct mlx4_cmd_mailbox *mailbox;
1295 u32 *outbox;
1296 int err = 0;
1297 u64 fw_ver;
fe40900f 1298 u16 cmd_if_rev;
225c7b1f
RD		 1299 u8 lg;
1300
1301#define QUERY_FW_OUT_SIZE 0x100
1302#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1303#define QUERY_FW_PPF_ID 0x09
fe40900f 1304#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1305#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1306#define QUERY_FW_ERR_START_OFFSET 0x30
1307#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1308#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1309
1310#define QUERY_FW_SIZE_OFFSET 0x00
1311#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1312#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1313
5cc914f1
MA		 1314#define QUERY_FW_COMM_BASE_OFFSET 0x40
1315#define QUERY_FW_COMM_BAR_OFFSET 0x48
1316
ddd8a6c1
EE		 1317#define QUERY_FW_CLOCK_OFFSET 0x50
1318#define QUERY_FW_CLOCK_BAR 0x58
1319
225c7b1f
RD		 1320 mailbox = mlx4_alloc_cmd_mailbox(dev);
1321 if (IS_ERR(mailbox))
1322 return PTR_ERR(mailbox);
1323 outbox = mailbox->buf;
1324
1325 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1326 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1327 if (err)
1328 goto out;
1329
1330 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1331 /*
3e1db334 1332 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1333 * version, so swap here.
1334 */
1335 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1336 ((fw_ver & 0xffff0000ull) >> 16) |
1337 ((fw_ver & 0x0000ffffull) << 16);
1338
752a50ca
JM		 1339 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1340 dev->caps.function = lg;
1341
b91cb3eb
JM		 1342 if (mlx4_is_slave(dev))
1343 goto out;
1344
5cc914f1 1345
fe40900f 1346 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1347 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1348 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1349 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1350 cmd_if_rev);
1351 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1352 (int) (dev->caps.fw_ver >> 32),
1353 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1354 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1355 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1356 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1357 err = -ENODEV;
1358 goto out;
1359 }
1360
5ae2a7a8
RD		 1361 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1362 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1363
225c7b1f
RD		 1364 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1365 cmd->max_cmds = 1 << lg;
1366
fe40900f 1367 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1368 (int) (dev->caps.fw_ver >> 32),
1369 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1370 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1371 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1372
1373 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1374 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1375 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1376 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1377
1378 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1379 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1380
1381 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1382 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1383 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1384 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1385
5cc914f1
MA		 1386 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1387 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1388 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1389 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1390 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1391 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1392
ddd8a6c1
EE		 1393 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1394 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1395 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1396 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1397 fw->clock_bar, fw->clock_offset);
1398
225c7b1f
RD		 1399 /*
1400 * Round up number of system pages needed in case
1401 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1402 */
1403 fw->fw_pages =
1404 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1405 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1406
1407 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1408 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1409
1410out:
1411 mlx4_free_cmd_mailbox(dev, mailbox);
1412 return err;
1413}
1414
b91cb3eb
JM		 1415int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1416 struct mlx4_vhcr *vhcr,
1417 struct mlx4_cmd_mailbox *inbox,
1418 struct mlx4_cmd_mailbox *outbox,
1419 struct mlx4_cmd_info *cmd)
1420{
1421 u8 *outbuf;
1422 int err;
1423
1424 outbuf = outbox->buf;
1425 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1426 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1427 if (err)
1428 return err;
1429
752a50ca
JM		 1430 /* for slaves, set pci PPF ID to invalid and zero out everything
1431 * else except FW version */
b91cb3eb
JM		 1432 outbuf[0] = outbuf[1] = 0;
1433 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1434 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1435
b91cb3eb
JM		 1436 return 0;
1437}
1438
225c7b1f
RD		 1439static void get_board_id(void *vsd, char *board_id)
1440{
1441 int i;
1442
1443#define VSD_OFFSET_SIG1 0x00
1444#define VSD_OFFSET_SIG2 0xde
1445#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1446#define VSD_OFFSET_TS_BOARD_ID 0x20
1447
1448#define VSD_SIGNATURE_TOPSPIN 0x5ad
1449
1450 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1451
1452 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1453 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1454 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1455 } else {
1456 /*
1457 * The board ID is a string but the firmware byte
1458 * swaps each 4-byte word before passing it back to
1459 * us. Therefore we need to swab it before printing.
1460 */
1461 for (i = 0; i < 4; ++i)
1462 ((u32 *) board_id)[i] =
1463 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1464 }
1465}
1466
1467int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1468{
1469 struct mlx4_cmd_mailbox *mailbox;
1470 u32 *outbox;
1471 int err;
1472
1473#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1474#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1475#define QUERY_ADAPTER_VSD_OFFSET 0x20
1476
1477 mailbox = mlx4_alloc_cmd_mailbox(dev);
1478 if (IS_ERR(mailbox))
1479 return PTR_ERR(mailbox);
1480 outbox = mailbox->buf;
1481
1482 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1483 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1484 if (err)
1485 goto out;
1486
225c7b1f
RD		 1487 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1488
1489 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1490 adapter->board_id);
1491
1492out:
1493 mlx4_free_cmd_mailbox(dev, mailbox);
1494 return err;
1495}
1496
1497int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1498{
1499 struct mlx4_cmd_mailbox *mailbox;
1500 __be32 *inbox;
1501 int err;
1502
1503#define INIT_HCA_IN_SIZE 0x200
1504#define INIT_HCA_VERSION_OFFSET 0x000
1505#define INIT_HCA_VERSION 2
7ffdf726 1506#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1507#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1508#define INIT_HCA_FLAGS_OFFSET 0x014
1509#define INIT_HCA_QPC_OFFSET 0x020
1510#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1511#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1512#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1513#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1514#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1515#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1516#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1517#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1518#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1519#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1520#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1521#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
7ae0e400 1522#define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a)
225c7b1f
RD		 1523#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1524#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1525#define INIT_HCA_MCAST_OFFSET 0x0c0
1526#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1527#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1528#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1529#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1530#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1531#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1532#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1533#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1534#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1535#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1536#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1537#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1538#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1539#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1540#define INIT_HCA_TPT_OFFSET 0x0f0
1541#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1542#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1543#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1544#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1545#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1546#define INIT_HCA_UAR_OFFSET 0x120
1547#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1548#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1549
1550 mailbox = mlx4_alloc_cmd_mailbox(dev);
1551 if (IS_ERR(mailbox))
1552 return PTR_ERR(mailbox);
1553 inbox = mailbox->buf;
1554
225c7b1f
RD		 1555 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1556
c57e20dc
EC		 1557 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1558 (ilog2(cache_line_size()) - 4) << 5;
1559
225c7b1f
RD		 1560#if defined(__LITTLE_ENDIAN)
1561 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1562#elif defined(__BIG_ENDIAN)
1563 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1564#else
1565#error Host endianness not defined
1566#endif
1567 /* Check port for UD address vector: */
1568 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1569
8ff095ec
EC		 1570 /* Enable IPoIB checksumming if we can: */
1571 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1572 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1573
51f5f0ee
JM		 1574 /* Enable QoS support if module parameter set */
1575 if (enable_qos)
1576 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1577
f2a3f6a3
OG		 1578 /* enable counters */
1579 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1580 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1581
08ff3235
OG		 1582 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1583 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1584 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1585 dev->caps.eqe_size = 64;
1586 dev->caps.eqe_factor = 1;
1587 } else {
1588 dev->caps.eqe_size = 32;
1589 dev->caps.eqe_factor = 0;
1590 }
1591
1592 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1593 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1594 dev->caps.cqe_size = 64;
77507aa2 1595 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1596 } else {
1597 dev->caps.cqe_size = 32;
1598 }
1599
77507aa2
IS		 1600 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1601 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1602 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1603 dev->caps.eqe_size = cache_line_size();
1604 dev->caps.cqe_size = cache_line_size();
1605 dev->caps.eqe_factor = 0;
1606 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1607 (ilog2(dev->caps.eqe_size) - 5)),
1608 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1609
1610 /* User still need to know to support CQE > 32B */
1611 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1612 }
1613
225c7b1f
RD		 1614 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1615
1616 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1617 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1618 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1619 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1620 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1621 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1622 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1623 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1624 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1625 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1626 MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET);
225c7b1f
RD		 1627 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1628 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1629
0ff1fb65
HHZ		 1630 /* steering attributes */
1631 if (dev->caps.steering_mode ==
1632 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1633 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1634 cpu_to_be32(1 <<
1635 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1636
1637 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1638 MLX4_PUT(inbox, param->log_mc_entry_sz,
1639 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1640 MLX4_PUT(inbox, param->log_mc_table_sz,
1641 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1642 /* Enable Ethernet flow steering
1643 * with udp unicast and tcp unicast
1644 */
23537b73 1645 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1646 INIT_HCA_FS_ETH_BITS_OFFSET);
1647 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1648 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1649 /* Enable IPoIB flow steering
1650 * with udp unicast and tcp unicast
1651 */
23537b73 1652 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1653 INIT_HCA_FS_IB_BITS_OFFSET);
1654 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1655 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1656 } else {
1657 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1658 MLX4_PUT(inbox, param->log_mc_entry_sz,
1659 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1660 MLX4_PUT(inbox, param->log_mc_hash_sz,
1661 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1662 MLX4_PUT(inbox, param->log_mc_table_sz,
1663 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1664 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1665 MLX4_PUT(inbox, (u8) (1 << 3),
1666 INIT_HCA_UC_STEERING_OFFSET);
1667 }
225c7b1f
RD		 1668
1669 /* TPT attributes */
1670
1671 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1672 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1673 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1674 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1675 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1676
1677 /* UAR attributes */
1678
ab9c17a0 1679 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1680 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1681
7ffdf726
OG		 1682 /* set parser VXLAN attributes */
1683 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1684 u8 parser_params = 0;
1685 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1686 }
1687
f9baff50
JM		 1688 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1689 MLX4_CMD_NATIVE);
225c7b1f
RD		 1690
1691 if (err)
1692 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1693
1694 mlx4_free_cmd_mailbox(dev, mailbox);
1695 return err;
1696}
1697
ab9c17a0
JM		 1698int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1699 struct mlx4_init_hca_param *param)
1700{
1701 struct mlx4_cmd_mailbox *mailbox;
1702 __be32 *outbox;
7b8157be 1703 u32 dword_field;
ab9c17a0 1704 int err;
08ff3235 1705 u8 byte_field;
ab9c17a0
JM		 1706
1707#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1708#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1709
1710 mailbox = mlx4_alloc_cmd_mailbox(dev);
1711 if (IS_ERR(mailbox))
1712 return PTR_ERR(mailbox);
1713 outbox = mailbox->buf;
1714
1715 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1716 MLX4_CMD_QUERY_HCA,
1717 MLX4_CMD_TIME_CLASS_B,
1718 !mlx4_is_slave(dev));
1719 if (err)
1720 goto out;
1721
1722 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1723 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1724
1725 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1726
1727 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1728 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1729 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1730 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1731 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1732 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1733 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1734 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1735 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1736 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
7ae0e400 1737 MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
ab9c17a0
JM		 1738 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1739 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1740
7b8157be
JM		 1741 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1742 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1743 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1744 } else {
1745 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1746 if (byte_field & 0x8)
1747 param->steering_mode = MLX4_STEERING_MODE_B0;
1748 else
1749 param->steering_mode = MLX4_STEERING_MODE_A0;
1750 }
0ff1fb65 1751 /* steering attributes */
7b8157be 1752 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1753 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1754 MLX4_GET(param->log_mc_entry_sz, outbox,
1755 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1756 MLX4_GET(param->log_mc_table_sz, outbox,
1757 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1758 } else {
1759 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1760 MLX4_GET(param->log_mc_entry_sz, outbox,
1761 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1762 MLX4_GET(param->log_mc_hash_sz, outbox,
1763 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1764 MLX4_GET(param->log_mc_table_sz, outbox,
1765 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1766 }
ab9c17a0 1767
08ff3235
OG		 1768 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1769 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1770 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1771 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1772 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1773 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1774
77507aa2
IS		 1775 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1776 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1777 if (byte_field) {
1778 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1779 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1780 param->cqe_size = 1 << ((byte_field &
1781 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1782 param->eqe_size = 1 << (((byte_field &
1783 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1784 }
1785
ab9c17a0
JM		 1786 /* TPT attributes */
1787
1788 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1789 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1790 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1791 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1792 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1793
1794 /* UAR attributes */
1795
1796 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1797 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1798
1799out:
1800 mlx4_free_cmd_mailbox(dev, mailbox);
1801
1802 return err;
1803}
1804
980e9001
JM		 1805/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1806 * and real QP0 are active, so that the paravirtualized QP0 is ready
1807 * to operate */
1808static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1809{
1810 struct mlx4_priv *priv = mlx4_priv(dev);
1811 /* irrelevant if not infiniband */
1812 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1813 priv->mfunc.master.qp0_state[port].qp0_active)
1814 return 1;
1815 return 0;
1816}
1817
5cc914f1
MA		 1818int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1819 struct mlx4_vhcr *vhcr,
1820 struct mlx4_cmd_mailbox *inbox,
1821 struct mlx4_cmd_mailbox *outbox,
1822 struct mlx4_cmd_info *cmd)
1823{
1824 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1825 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1826 int err;
1827
449fc488
MB		 1828 if (port < 0)
1829 return -EINVAL;
1830
5cc914f1
MA		 1831 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1832 return 0;
1833
980e9001
JM		 1834 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1835 /* Enable port only if it was previously disabled */
1836 if (!priv->mfunc.master.init_port_ref[port]) {
1837 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1838 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1839 if (err)
1840 return err;
1841 }
1842 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1843 } else {
1844 if (slave == mlx4_master_func_num(dev)) {
1845 if (check_qp0_state(dev, slave, port) &&
1846 !priv->mfunc.master.qp0_state[port].port_active) {
1847 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1848 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1849 if (err)
1850 return err;
1851 priv->mfunc.master.qp0_state[port].port_active = 1;
1852 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1853 }
1854 } else
1855 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1856 }
1857 ++priv->mfunc.master.init_port_ref[port];
1858 return 0;
1859}
1860
5ae2a7a8 1861int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1862{
1863 struct mlx4_cmd_mailbox *mailbox;
1864 u32 *inbox;
1865 int err;
1866 u32 flags;
5ae2a7a8 1867 u16 field;
225c7b1f 1868
5ae2a7a8 1869 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1870#define INIT_PORT_IN_SIZE 256
1871#define INIT_PORT_FLAGS_OFFSET 0x00
1872#define INIT_PORT_FLAG_SIG (1 << 18)
1873#define INIT_PORT_FLAG_NG (1 << 17)
1874#define INIT_PORT_FLAG_G0 (1 << 16)
1875#define INIT_PORT_VL_SHIFT 4
1876#define INIT_PORT_PORT_WIDTH_SHIFT 8
1877#define INIT_PORT_MTU_OFFSET 0x04
1878#define INIT_PORT_MAX_GID_OFFSET 0x06
1879#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1880#define INIT_PORT_GUID0_OFFSET 0x10
1881#define INIT_PORT_NODE_GUID_OFFSET 0x18
1882#define INIT_PORT_SI_GUID_OFFSET 0x20
1883
5ae2a7a8
RD		 1884 mailbox = mlx4_alloc_cmd_mailbox(dev);
1885 if (IS_ERR(mailbox))
1886 return PTR_ERR(mailbox);
1887 inbox = mailbox->buf;
225c7b1f 1888
5ae2a7a8
RD		 1889 flags = 0;
1890 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1891 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1892 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1893
b79acb49 1894 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1895 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1896 field = dev->caps.gid_table_len[port];
1897 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1898 field = dev->caps.pkey_table_len[port];
1899 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1900
5ae2a7a8 1901 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1902 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1903
5ae2a7a8
RD		 1904 mlx4_free_cmd_mailbox(dev, mailbox);
1905 } else
1906 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1907 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1908
1909 return err;
1910}
1911EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1912
5cc914f1
MA		 1913int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1914 struct mlx4_vhcr *vhcr,
1915 struct mlx4_cmd_mailbox *inbox,
1916 struct mlx4_cmd_mailbox *outbox,
1917 struct mlx4_cmd_info *cmd)
1918{
1919 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1920 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1921 int err;
1922
449fc488
MB		 1923 if (port < 0)
1924 return -EINVAL;
1925
5cc914f1
MA		 1926 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1927 (1 << port)))
1928 return 0;
1929
980e9001
JM		 1930 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1931 if (priv->mfunc.master.init_port_ref[port] == 1) {
1932 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1933 1000, MLX4_CMD_NATIVE);
1934 if (err)
1935 return err;
1936 }
1937 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1938 } else {
1939 /* infiniband port */
1940 if (slave == mlx4_master_func_num(dev)) {
1941 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1942 priv->mfunc.master.qp0_state[port].port_active) {
1943 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1944 1000, MLX4_CMD_NATIVE);
1945 if (err)
1946 return err;
1947 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1948 priv->mfunc.master.qp0_state[port].port_active = 0;
1949 }
1950 } else
1951 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1952 }
5cc914f1
MA		 1953 --priv->mfunc.master.init_port_ref[port];
1954 return 0;
1955}
1956
225c7b1f
RD		 1957int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1958{
f9baff50
JM		 1959 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1960 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1961}
1962EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1963
1964int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1965{
f9baff50
JM		 1966 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1967 MLX4_CMD_NATIVE);
225c7b1f
RD		 1968}
1969
d18f141a
OG		 1970struct mlx4_config_dev {
1971 __be32 update_flags;
d475c95b 1972 __be32 rsvd1[3];
d18f141a
OG		 1973 __be16 vxlan_udp_dport;
1974 __be16 rsvd2;
d475c95b
MB		 1975 __be32 rsvd3[27];
1976 __be16 rsvd4;
1977 u8 rsvd5;
1978 u8 rx_checksum_val;
d18f141a
OG		 1979};
1980
1981#define MLX4_VXLAN_UDP_DPORT (1 << 0)
1982
d475c95b 1983static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
d18f141a
OG		 1984{
1985 int err;
1986 struct mlx4_cmd_mailbox *mailbox;
1987
1988 mailbox = mlx4_alloc_cmd_mailbox(dev);
1989 if (IS_ERR(mailbox))
1990 return PTR_ERR(mailbox);
1991
1992 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1993
1994 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1995 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1996
1997 mlx4_free_cmd_mailbox(dev, mailbox);
1998 return err;
1999}
2000
d475c95b
MB		 2001static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
2002{
2003 int err;
2004 struct mlx4_cmd_mailbox *mailbox;
2005
2006 mailbox = mlx4_alloc_cmd_mailbox(dev);
2007 if (IS_ERR(mailbox))
2008 return PTR_ERR(mailbox);
2009
2010 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV,
2011 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2012
2013 if (!err)
2014 memcpy(config_dev, mailbox->buf, sizeof(*config_dev));
2015
2016 mlx4_free_cmd_mailbox(dev, mailbox);
2017 return err;
2018}
2019
2020/* Conversion between the HW values and the actual functionality.
2021 * The value represented by the array index,
2022 * and the functionality determined by the flags.
2023 */
2024static const u8 config_dev_csum_flags[] = {
2025 [0] = 0,
2026 [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP,
2027 [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP |
2028 MLX4_RX_CSUM_MODE_L4,
2029 [3] = MLX4_RX_CSUM_MODE_L4 |
2030 MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP |
2031 MLX4_RX_CSUM_MODE_MULTI_VLAN
2032};
2033
2034int mlx4_config_dev_retrieval(struct mlx4_dev *dev,
2035 struct mlx4_config_dev_params *params)
2036{
2037 struct mlx4_config_dev config_dev;
2038 int err;
2039 u8 csum_mask;
2040
2041#define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7
2042#define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0
2043#define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4
2044
2045 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV))
2046 return -ENOTSUPP;
2047
2048 err = mlx4_CONFIG_DEV_get(dev, &config_dev);
2049 if (err)
2050 return err;
2051
2052 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) &
2053 CONFIG_DEV_RX_CSUM_MODE_MASK;
2054
2055 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2056 return -EINVAL;
2057 params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask];
2058
2059 csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) &
2060 CONFIG_DEV_RX_CSUM_MODE_MASK;
2061
2062 if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0]))
2063 return -EINVAL;
2064 params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask];
2065
2066 params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport);
2067
2068 return 0;
2069}
2070EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval);
2071
d18f141a
OG		 2072int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
2073{
2074 struct mlx4_config_dev config_dev;
2075
2076 memset(&config_dev, 0, sizeof(config_dev));
2077 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
2078 config_dev.vxlan_udp_dport = udp_port;
2079
d475c95b 2080 return mlx4_CONFIG_DEV_set(dev, &config_dev);
d18f141a
OG		 2081}
2082EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
2083
2084
225c7b1f
RD		 2085int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
2086{
2087 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
2088 MLX4_CMD_SET_ICM_SIZE,
f9baff50 2089 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 2090 if (ret)
2091 return ret;
2092
2093 /*
2094 * Round up number of system pages needed in case
2095 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
2096 */
2097 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
2098 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
2099
2100 return 0;
2101}
2102
2103int mlx4_NOP(struct mlx4_dev *dev)
2104{
2105 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 2106 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 2107}
14c07b13 2108
8e1a28e8
HHZ		 2109int mlx4_get_phys_port_id(struct mlx4_dev *dev)
2110{
2111 u8 port;
2112 u32 *outbox;
2113 struct mlx4_cmd_mailbox *mailbox;
2114 u32 in_mod;
2115 u32 guid_hi, guid_lo;
2116 int err, ret = 0;
2117#define MOD_STAT_CFG_PORT_OFFSET 8
2118#define MOD_STAT_CFG_GUID_H 0X14
2119#define MOD_STAT_CFG_GUID_L 0X1c
2120
2121 mailbox = mlx4_alloc_cmd_mailbox(dev);
2122 if (IS_ERR(mailbox))
2123 return PTR_ERR(mailbox);
2124 outbox = mailbox->buf;
2125
2126 for (port = 1; port <= dev->caps.num_ports; port++) {
2127 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
2128 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
2129 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2130 MLX4_CMD_NATIVE);
2131 if (err) {
2132 mlx4_err(dev, "Fail to get port %d uplink guid\n",
2133 port);
2134 ret = err;
2135 } else {
2136 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2137 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2138 dev->caps.phys_port_id[port] = (u64)guid_lo |
2139 (u64)guid_hi << 32;
2140 }
2141 }
2142 mlx4_free_cmd_mailbox(dev, mailbox);
2143 return ret;
2144}
2145
14c07b13
YP		 2146#define MLX4_WOL_SETUP_MODE (5 << 28)
2147int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
2148{
2149 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2150
2151 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 2152 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
2153 MLX4_CMD_NATIVE);
14c07b13
YP		 2154}
2155EXPORT_SYMBOL_GPL(mlx4_wol_read);
2156
2157int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
2158{
2159 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
2160
2161 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 2162 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 2163}
2164EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 2165
2166enum {
2167 ADD_TO_MCG = 0x26,
2168};
2169
2170
2171void mlx4_opreq_action(struct work_struct *work)
2172{
2173 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
2174 opreq_task);
2175 struct mlx4_dev *dev = &priv->dev;
2176 int num_tasks = atomic_read(&priv->opreq_count);
2177 struct mlx4_cmd_mailbox *mailbox;
2178 struct mlx4_mgm *mgm;
2179 u32 *outbox;
2180 u32 modifier;
2181 u16 token;
fe6f700d
YP		 2182 u16 type;
2183 int err;
2184 u32 num_qps;
2185 struct mlx4_qp qp;
2186 int i;
2187 u8 rem_mcg;
2188 u8 prot;
2189
2190#define GET_OP_REQ_MODIFIER_OFFSET 0x08
2191#define GET_OP_REQ_TOKEN_OFFSET 0x14
2192#define GET_OP_REQ_TYPE_OFFSET 0x1a
2193#define GET_OP_REQ_DATA_OFFSET 0x20
2194
2195 mailbox = mlx4_alloc_cmd_mailbox(dev);
2196 if (IS_ERR(mailbox)) {
2197 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2198 return;
2199 }
2200 outbox = mailbox->buf;
2201
2202 while (num_tasks) {
2203 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2204 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2205 MLX4_CMD_NATIVE);
2206 if (err) {
6d3be300 2207 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2208 err);
2209 return;
2210 }
2211 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2212 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2213 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2214 type &= 0xfff;
2215
2216 switch (type) {
2217 case ADD_TO_MCG:
2218 if (dev->caps.steering_mode ==
2219 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2220 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2221 err = EPERM;
2222 break;
2223 }
2224 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2225 GET_OP_REQ_DATA_OFFSET);
2226 num_qps = be32_to_cpu(mgm->members_count) &
2227 MGM_QPN_MASK;
2228 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2229 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2230
2231 for (i = 0; i < num_qps; i++) {
2232 qp.qpn = be32_to_cpu(mgm->qp[i]);
2233 if (rem_mcg)
2234 err = mlx4_multicast_detach(dev, &qp,
2235 mgm->gid,
2236 prot, 0);
2237 else
2238 err = mlx4_multicast_attach(dev, &qp,
2239 mgm->gid,
2240 mgm->gid[5]
2241 , 0, prot,
2242 NULL);
2243 if (err)
2244 break;
2245 }
2246 break;
2247 default:
2248 mlx4_warn(dev, "Bad type for required operation\n");
2249 err = EINVAL;
2250 break;
2251 }
28d222bb
EP		 2252 err = mlx4_cmd(dev, 0, ((u32) err |
2253 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2254 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2255 MLX4_CMD_NATIVE);
2256 if (err) {
2257 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2258 err);
2259 goto out;
2260 }
2261 memset(outbox, 0, 0xffc);
2262 num_tasks = atomic_dec_return(&priv->opreq_count);
2263 }
2264
2265out:
2266 mlx4_free_cmd_mailbox(dev, mailbox);
2267}
114840c3
JM		 2268
2269static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2270 struct mlx4_cmd_mailbox *mailbox)
2271{
2272#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2273#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2274#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2275#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2276
2277 u32 set_attr_mask, getresp_attr_mask;
2278 u32 trap_attr_mask, traprepress_attr_mask;
2279
2280 MLX4_GET(set_attr_mask, mailbox->buf,
2281 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2282 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2283 set_attr_mask);
2284
2285 MLX4_GET(getresp_attr_mask, mailbox->buf,
2286 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2287 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2288 getresp_attr_mask);
2289
2290 MLX4_GET(trap_attr_mask, mailbox->buf,
2291 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2292 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2293 trap_attr_mask);
2294
2295 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2296 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2297 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2298 traprepress_attr_mask);
2299
2300 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2301 traprepress_attr_mask)
2302 return 1;
2303
2304 return 0;
2305}
2306
2307int mlx4_config_mad_demux(struct mlx4_dev *dev)
2308{
2309 struct mlx4_cmd_mailbox *mailbox;
2310 int secure_host_active;
2311 int err;
2312
2313 /* Check if mad_demux is supported */
2314 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2315 return 0;
2316
2317 mailbox = mlx4_alloc_cmd_mailbox(dev);
2318 if (IS_ERR(mailbox)) {
2319 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2320 return -ENOMEM;
2321 }
2322
2323 /* Query mad_demux to find out which MADs are handled by internal sma */
2324 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2325 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2326 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2327 if (err) {
2328 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2329 err);
2330 goto out;
2331 }
2332
2333 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2334
2335 /* Config mad_demux to handle all MADs returned by the query above */
2336 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2337 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2338 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2339 if (err) {
2340 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2341 goto out;
2342 }
2343
2344 if (secure_host_active)
2345 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2346out:
2347 mlx4_free_cmd_mailbox(dev, mailbox);
2348 return err;
2349}
adbc7ac5
SM		 2350
2351/* Access Reg commands */
2352enum mlx4_access_reg_masks {
2353 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2354 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2355 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2356};
2357
2358struct mlx4_access_reg {
2359 __be16 constant1;
2360 u8 status;
2361 u8 resrvd1;
2362 __be16 reg_id;
2363 u8 method;
2364 u8 constant2;
2365 __be32 resrvd2[2];
2366 __be16 len_const;
2367 __be16 resrvd3;
2368#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2369 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2370} __attribute__((__packed__));
2371
2372/**
2373 * mlx4_ACCESS_REG - Generic access reg command.
2374 * @dev: mlx4_dev.
2375 * @reg_id: register ID to access.
2376 * @method: Access method Read/Write.
2377 * @reg_len: register length to Read/Write in bytes.
2378 * @reg_data: reg_data pointer to Read/Write From/To.
2379 *
2380 * Access ConnectX registers FW command.
2381 * Returns 0 on success and copies outbox mlx4_access_reg data
2382 * field into reg_data or a negative error code.
2383 */
2384static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2385 enum mlx4_access_reg_method method,
2386 u16 reg_len, void *reg_data)
2387{
2388 struct mlx4_cmd_mailbox *inbox, *outbox;
2389 struct mlx4_access_reg *inbuf, *outbuf;
2390 int err;
2391
2392 inbox = mlx4_alloc_cmd_mailbox(dev);
2393 if (IS_ERR(inbox))
2394 return PTR_ERR(inbox);
2395
2396 outbox = mlx4_alloc_cmd_mailbox(dev);
2397 if (IS_ERR(outbox)) {
2398 mlx4_free_cmd_mailbox(dev, inbox);
2399 return PTR_ERR(outbox);
2400 }
2401
2402 inbuf = inbox->buf;
2403 outbuf = outbox->buf;
2404
2405 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2406 inbuf->constant2 = 0x1;
2407 inbuf->reg_id = cpu_to_be16(reg_id);
2408 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2409
2410 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2411 inbuf->len_const =
2412 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2413 ((0x3) << 12));
2414
2415 memcpy(inbuf->reg_data, reg_data, reg_len);
2416 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2417 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2418 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2419 if (err)
2420 goto out;
2421
2422 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2423 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2424 mlx4_err(dev,
2425 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2426 reg_id, err);
2427 goto out;
2428 }
2429
2430 memcpy(reg_data, outbuf->reg_data, reg_len);
2431out:
2432 mlx4_free_cmd_mailbox(dev, inbox);
2433 mlx4_free_cmd_mailbox(dev, outbox);
2434 return err;
2435}
2436
2437/* ConnectX registers IDs */
2438enum mlx4_reg_id {
2439 MLX4_REG_ID_PTYS = 0x5004,
2440};
2441
2442/**
2443 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2444 * register
2445 * @dev: mlx4_dev.
2446 * @method: Access method Read/Write.
2447 * @ptys_reg: PTYS register data pointer.
2448 *
2449 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2450 * configuration
2451 * Returns 0 on success or a negative error code.
2452 */
2453int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2454 enum mlx4_access_reg_method method,
2455 struct mlx4_ptys_reg *ptys_reg)
2456{
2457 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2458 method, sizeof(*ptys_reg), ptys_reg);
2459}
2460EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2461
2462int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2463 struct mlx4_vhcr *vhcr,
2464 struct mlx4_cmd_mailbox *inbox,
2465 struct mlx4_cmd_mailbox *outbox,
2466 struct mlx4_cmd_info *cmd)
2467{
2468 struct mlx4_access_reg *inbuf = inbox->buf;
2469 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2470 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2471
2472 if (slave != mlx4_master_func_num(dev) &&
2473 method == MLX4_ACCESS_REG_WRITE)
2474 return -EPERM;
2475
2476 if (reg_id == MLX4_REG_ID_PTYS) {
2477 struct mlx4_ptys_reg *ptys_reg =
2478 (struct mlx4_ptys_reg *)inbuf->reg_data;
2479
2480 ptys_reg->local_port =
2481 mlx4_slave_convert_port(dev, slave,
2482 ptys_reg->local_port);
2483 }
2484
2485 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2486 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2487 MLX4_CMD_NATIVE);
2488}
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