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net/mlx4_en: Implement ndo_get_phys_port_id
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
955154fa 132 [3] = "Device manage flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca
JM		 136 [7] = "FSM (MAC anti-spoofing) support",
137 [8] = "Dynamic QP updates support"
b3416f44
SP		 138 };
139 int i;
140
141 for (i = 0; i < ARRAY_SIZE(fname); ++i)
142 if (fname[i] && (flags & (1LL << i)))
143 mlx4_dbg(dev, " %s\n", fname[i]);
144}
145
2d928651
VS		 146int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
147{
148 struct mlx4_cmd_mailbox *mailbox;
149 u32 *inbox;
150 int err = 0;
151
152#define MOD_STAT_CFG_IN_SIZE 0x100
153
154#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
155#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
156
157 mailbox = mlx4_alloc_cmd_mailbox(dev);
158 if (IS_ERR(mailbox))
159 return PTR_ERR(mailbox);
160 inbox = mailbox->buf;
161
2d928651
VS		 162 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
163 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
164
165 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 166 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 167
168 mlx4_free_cmd_mailbox(dev, mailbox);
169 return err;
170}
171
5cc914f1
MA		 172int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
173 struct mlx4_vhcr *vhcr,
174 struct mlx4_cmd_mailbox *inbox,
175 struct mlx4_cmd_mailbox *outbox,
176 struct mlx4_cmd_info *cmd)
177{
5a0d0a61 178 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 179 u8 field;
180 u32 size;
181 int err = 0;
182
183#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
184#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 185#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 186#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 187#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
188#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
189#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
190#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
191#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
192#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 193#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 194#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 195
eb456a68
JM		 196#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
197#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
198#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
199#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
200#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
201#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
202
105c320f
JM		 203#define QUERY_FUNC_CAP_FMR_FLAG 0x80
204#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
205#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 206#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
105c320f
JM		 207
208/* when opcode modifier = 1 */
5cc914f1 209#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
73e74ab4
HHZ		 210#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
211#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 212
47605df9
JM		 213#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
214#define QUERY_FUNC_CAP_QP0_PROXY 0x14
215#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
216#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 217#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 218
73e74ab4
HHZ		 219#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
220#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 221#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
105c320f 222
73e74ab4 223#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
105c320f 224
5cc914f1 225 if (vhcr->op_modifier == 1) {
eb17711b
HHZ		 226 /* Set nic_info bit to mark new fields support */
227 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
228 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
229
47605df9
JM		 230 field = vhcr->in_modifier; /* phys-port = logical-port */
231 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
232
233 /* size is now the QP number */
234 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
235 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
236
237 size += 2;
238 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
239
240 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
241 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
242
243 size += 2;
244 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
245
8e1a28e8
HHZ		 246 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
247 QUERY_FUNC_CAP_PHYS_PORT_ID);
248
5cc914f1 249 } else if (vhcr->op_modifier == 0) {
eb456a68
JM		 250 /* enable rdma and ethernet interfaces, and new quota locations */
251 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
252 QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1
MA		 253 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
254
5cc914f1
MA		 255 field = dev->caps.num_ports;
256 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
257
08ff3235 258 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 259 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
260
105c320f
JM		 261 field = 0; /* protected FMR support not available as yet */
262 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
263
5a0d0a61 264 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 265 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 266 size = dev->caps.num_qps;
267 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 268
5a0d0a61 269 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 270 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 271 size = dev->caps.num_srqs;
272 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 273
5a0d0a61 274 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 275 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 276 size = dev->caps.num_cqs;
277 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1
MA		 278
279 size = dev->caps.num_eqs;
280 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
281
282 size = dev->caps.reserved_eqs;
283 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
284
5a0d0a61 285 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 286 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 287 size = dev->caps.num_mpts;
288 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 289
5a0d0a61 290 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 291 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 292 size = dev->caps.num_mtts;
293 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 294
295 size = dev->caps.num_mgms + dev->caps.num_amgms;
296 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 297 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1
MA		 298
299 } else
300 err = -EINVAL;
301
302 return err;
303}
304
47605df9
JM		 305int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
306 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 307{
308 struct mlx4_cmd_mailbox *mailbox;
309 u32 *outbox;
47605df9 310 u8 field, op_modifier;
5cc914f1 311 u32 size;
eb456a68 312 int err = 0, quotas = 0;
5cc914f1 313
47605df9 314 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 315
316 mailbox = mlx4_alloc_cmd_mailbox(dev);
317 if (IS_ERR(mailbox))
318 return PTR_ERR(mailbox);
319
47605df9
JM		 320 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
321 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 322 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
323 if (err)
324 goto out;
325
326 outbox = mailbox->buf;
327
47605df9
JM		 328 if (!op_modifier) {
329 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
330 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
331 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
332 err = -EPROTONOSUPPORT;
333 goto out;
334 }
335 func_cap->flags = field;
eb456a68 336 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 337
47605df9
JM		 338 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
339 func_cap->num_ports = field;
5cc914f1 340
47605df9
JM		 341 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
342 func_cap->pf_context_behaviour = size;
5cc914f1 343
eb456a68
JM		 344 if (quotas) {
345 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
346 func_cap->qp_quota = size & 0xFFFFFF;
347
348 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
349 func_cap->srq_quota = size & 0xFFFFFF;
350
351 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
352 func_cap->cq_quota = size & 0xFFFFFF;
353
354 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
355 func_cap->mpt_quota = size & 0xFFFFFF;
356
357 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
358 func_cap->mtt_quota = size & 0xFFFFFF;
359
360 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
361 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 362
eb456a68
JM		 363 } else {
364 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
365 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 366
eb456a68
JM		 367 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
368 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 369
eb456a68
JM		 370 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
371 func_cap->cq_quota = size & 0xFFFFFF;
372
373 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
374 func_cap->mpt_quota = size & 0xFFFFFF;
375
376 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
377 func_cap->mtt_quota = size & 0xFFFFFF;
378
379 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
380 func_cap->mcg_quota = size & 0xFFFFFF;
381 }
47605df9
JM		 382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
383 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 384
47605df9
JM		 385 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
386 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 387
47605df9
JM		 388 goto out;
389 }
5cc914f1 390
47605df9
JM		 391 /* logical port query */
392 if (gen_or_port > dev->caps.num_ports) {
393 err = -EINVAL;
394 goto out;
395 }
5cc914f1 396
eb17711b 397 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 398 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
eb17711b 399 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_OFFSET) {
47605df9
JM		 400 mlx4_err(dev, "VLAN is enforced on this port\n");
401 err = -EPROTONOSUPPORT;
5cc914f1 402 goto out;
47605df9 403 }
5cc914f1 404
eb17711b 405 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 406 mlx4_err(dev, "Force mac is enabled on this port\n");
407 err = -EPROTONOSUPPORT;
408 goto out;
5cc914f1 409 }
47605df9 410 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 411 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
412 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
47605df9
JM		 413 mlx4_err(dev, "phy_wqe_gid is "
414 "enforced on this ib port\n");
415 err = -EPROTONOSUPPORT;
416 goto out;
417 }
418 }
5cc914f1 419
47605df9
JM		 420 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
421 func_cap->physical_port = field;
422 if (func_cap->physical_port != gen_or_port) {
423 err = -ENOSYS;
424 goto out;
5cc914f1
MA		 425 }
426
47605df9
JM		 427 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
428 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
429
430 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
431 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
432
433 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
434 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
435
436 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
437 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
438
8e1a28e8
HHZ		 439 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
440 MLX4_GET(func_cap->phys_port_id, outbox,
441 QUERY_FUNC_CAP_PHYS_PORT_ID);
442
5cc914f1
MA		 443 /* All other resources are allocated by the master, but we still report
444 * 'num' and 'reserved' capabilities as follows:
445 * - num remains the maximum resource index
446 * - 'num - reserved' is the total available objects of a resource, but
447 * resource indices may be less than 'reserved'
448 * TODO: set per-resource quotas */
449
450out:
451 mlx4_free_cmd_mailbox(dev, mailbox);
452
453 return err;
454}
455
225c7b1f
RD		 456int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
457{
458 struct mlx4_cmd_mailbox *mailbox;
459 u32 *outbox;
460 u8 field;
ccf86321 461 u32 field32, flags, ext_flags;
225c7b1f
RD		 462 u16 size;
463 u16 stat_rate;
464 int err;
5ae2a7a8 465 int i;
225c7b1f
RD		 466
467#define QUERY_DEV_CAP_OUT_SIZE 0x100
468#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
469#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
470#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
471#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
472#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
473#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
474#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
475#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
476#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
477#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
478#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
479#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
480#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
481#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
482#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
483#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
484#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
485#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
486#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
487#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
488#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 489#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 490#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 491#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
492#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
493#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
494#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
495#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 496#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 497#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
498#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 499#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 500#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 501#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 502#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
503#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
504#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
505#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
506#define QUERY_DEV_CAP_BF_OFFSET 0x4c
507#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
508#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
509#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
510#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
511#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
512#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
513#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
514#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
515#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
516#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
517#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
518#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 519#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
520#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 521#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 522#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
0ff1fb65
HHZ		 523#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
524#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 525#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
526#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
527#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
528#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
529#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
530#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
531#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
532#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
533#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
534#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 535#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 536#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
537#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
955154fa 538#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
225c7b1f 539
b3416f44 540 dev_cap->flags2 = 0;
225c7b1f
RD		 541 mailbox = mlx4_alloc_cmd_mailbox(dev);
542 if (IS_ERR(mailbox))
543 return PTR_ERR(mailbox);
544 outbox = mailbox->buf;
545
546 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 547 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 548 if (err)
549 goto out;
550
551 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
552 dev_cap->reserved_qps = 1 << (field & 0xf);
553 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
554 dev_cap->max_qps = 1 << (field & 0x1f);
555 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
556 dev_cap->reserved_srqs = 1 << (field >> 4);
557 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
558 dev_cap->max_srqs = 1 << (field & 0x1f);
559 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
560 dev_cap->max_cq_sz = 1 << field;
561 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
562 dev_cap->reserved_cqs = 1 << (field & 0xf);
563 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
564 dev_cap->max_cqs = 1 << (field & 0x1f);
565 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
566 dev_cap->max_mpts = 1 << (field & 0x3f);
567 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 568 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 569 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 570 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 571 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
572 dev_cap->reserved_mtts = 1 << (field >> 4);
573 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
574 dev_cap->max_mrw_sz = 1 << field;
575 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
576 dev_cap->reserved_mrws = 1 << (field & 0xf);
577 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
578 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
579 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
580 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
581 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
582 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 583 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
584 field &= 0x1f;
585 if (!field)
586 dev_cap->max_gso_sz = 0;
587 else
588 dev_cap->max_gso_sz = 1 << field;
589
b3416f44
SP		 590 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
591 if (field & 0x20)
592 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
593 if (field & 0x10)
594 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
595 field &= 0xf;
596 if (field) {
597 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
598 dev_cap->max_rss_tbl_sz = 1 << field;
599 } else
600 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 601 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
602 dev_cap->max_rdma_global = 1 << (field & 0x3f);
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
604 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 605 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 606 dev_cap->num_ports = field & 0xf;
149983af
DB		 607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
608 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 609 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
610 if (field & 0x80)
611 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
612 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
613 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
614 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 615 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
616 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 617 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
618 if (field & 0x80)
619 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 620 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 621 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 622 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 623 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
624 dev_cap->reserved_uars = field >> 4;
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
626 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
627 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
628 dev_cap->min_page_sz = 1 << field;
629
630 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
631 if (field & 0x80) {
632 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
633 dev_cap->bf_reg_size = 1 << (field & 0x1f);
634 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 635 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 636 field = 3;
225c7b1f
RD		 637 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
638 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
639 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
640 } else {
641 dev_cap->bf_reg_size = 0;
642 mlx4_dbg(dev, "BlueFlame not available\n");
643 }
644
645 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
646 dev_cap->max_sq_sg = field;
647 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
648 dev_cap->max_sq_desc_sz = size;
649
650 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
651 dev_cap->max_qp_per_mcg = 1 << field;
652 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
653 dev_cap->reserved_mgms = field & 0xf;
654 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
655 dev_cap->max_mcgs = 1 << field;
656 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
657 dev_cap->reserved_pds = field >> 4;
658 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
659 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 660 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
661 dev_cap->reserved_xrcds = field >> 4;
426dd00d 662 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 663 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 664
665 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
666 dev_cap->rdmarc_entry_sz = size;
667 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
668 dev_cap->qpc_entry_sz = size;
669 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
670 dev_cap->aux_entry_sz = size;
671 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
672 dev_cap->altc_entry_sz = size;
673 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
674 dev_cap->eqc_entry_sz = size;
675 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
676 dev_cap->cqc_entry_sz = size;
677 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
678 dev_cap->srq_entry_sz = size;
679 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
680 dev_cap->cmpt_entry_sz = size;
681 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
682 dev_cap->mtt_entry_sz = size;
683 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
684 dev_cap->dmpt_entry_sz = size;
685
686 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
687 dev_cap->max_srq_sz = 1 << field;
688 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
689 dev_cap->max_qp_sz = 1 << field;
690 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
691 dev_cap->resize_srq = field & 1;
692 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
693 dev_cap->max_rq_sg = field;
694 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
695 dev_cap->max_rq_desc_sz = size;
696
697 MLX4_GET(dev_cap->bmme_flags, outbox,
698 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
699 MLX4_GET(dev_cap->reserved_lkey, outbox,
700 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
955154fa
MB		 701 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
702 if (field & 1<<6)
5930e8d0 703 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
225c7b1f
RD		 704 MLX4_GET(dev_cap->max_icm_sz, outbox,
705 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 706 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
707 MLX4_GET(dev_cap->max_counters, outbox,
708 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 709
3f7fb021 710 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 711 if (field32 & (1 << 16))
712 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 713 if (field32 & (1 << 26))
714 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 715 if (field32 & (1 << 20))
716 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
3f7fb021 717
5ae2a7a8
RD		 718 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
719 for (i = 1; i <= dev_cap->num_ports; ++i) {
720 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
721 dev_cap->max_vl[i] = field >> 4;
722 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 723 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 724 dev_cap->max_port_width[i] = field & 0xf;
725 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
726 dev_cap->max_gids[i] = 1 << (field & 0xf);
727 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
728 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
729 }
730 } else {
7ff93f8b 731#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 732#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 733#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 734#define QUERY_PORT_WIDTH_OFFSET 0x06
735#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 736#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 737#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 738#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 739#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
740#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
741#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 742
743 for (i = 1; i <= dev_cap->num_ports; ++i) {
744 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 745 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 746 if (err)
747 goto out;
748
7ff93f8b
YP		 749 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
750 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 751 dev_cap->suggested_type[i] = (field >> 3) & 1;
752 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 753 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 754 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 755 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
756 dev_cap->max_port_width[i] = field & 0xf;
757 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
758 dev_cap->max_gids[i] = 1 << (field >> 4);
759 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
760 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
761 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 762 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
763 dev_cap->log_max_macs[i] = field & 0xf;
764 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 765 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
766 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 767 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
768 dev_cap->trans_type[i] = field32 >> 24;
769 dev_cap->vendor_oui[i] = field32 & 0xffffff;
770 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
771 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 772 }
773 }
774
95d04f07
RD		 775 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
776 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 777
778 /*
779 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
780 * we can't use any EQs whose doorbell falls on that page,
781 * even if the EQ itself isn't reserved.
782 */
783 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
784 dev_cap->reserved_eqs);
785
786 mlx4_dbg(dev, "Max ICM size %lld MB\n",
787 (unsigned long long) dev_cap->max_icm_sz >> 20);
788 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
789 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
790 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
791 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
792 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
793 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
794 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
795 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
796 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
797 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
798 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
799 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
800 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
801 dev_cap->max_pds, dev_cap->reserved_mgms);
802 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
803 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
804 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 805 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 806 dev_cap->max_port_width[1]);
225c7b1f
RD		 807 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
808 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
809 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
810 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 811 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 812 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 813 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 814
815 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 816 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 817
818out:
819 mlx4_free_cmd_mailbox(dev, mailbox);
820 return err;
821}
822
b91cb3eb
JM		 823int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
824 struct mlx4_vhcr *vhcr,
825 struct mlx4_cmd_mailbox *inbox,
826 struct mlx4_cmd_mailbox *outbox,
827 struct mlx4_cmd_info *cmd)
828{
2a4fae14 829 u64 flags;
b91cb3eb
JM		 830 int err = 0;
831 u8 field;
cc1ade94 832 u32 bmme_flags;
b91cb3eb
JM		 833
834 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
835 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
836 if (err)
837 return err;
838
cc1ade94
SM		 839 /* add port mng change event capability and disable mw type 1
840 * unconditionally to slaves
841 */
2a4fae14
JM		 842 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
843 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 844 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
2a4fae14
JM		 845 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
846
30b40c31
AV		 847 /* For guests, disable timestamp */
848 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
849 field &= 0x7f;
850 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
851
b91cb3eb
JM		 852 /* For guests, report Blueflame disabled */
853 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
854 field &= 0x7f;
855 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
856
cc1ade94
SM		 857 /* For guests, disable mw type 2 */
858 MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
859 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
860 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
861
0081c8f3
JM		 862 /* turn off device-managed steering capability if not enabled */
863 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
864 MLX4_GET(field, outbox->buf,
865 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
866 field &= 0x7f;
867 MLX4_PUT(outbox->buf, field,
868 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
869 }
b91cb3eb
JM		 870 return 0;
871}
872
5cc914f1
MA		 873int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
874 struct mlx4_vhcr *vhcr,
875 struct mlx4_cmd_mailbox *inbox,
876 struct mlx4_cmd_mailbox *outbox,
877 struct mlx4_cmd_info *cmd)
878{
0eb62b93 879 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 880 u64 def_mac;
881 u8 port_type;
6634961c 882 u16 short_field;
5cc914f1 883 int err;
948e306d 884 int admin_link_state;
5cc914f1 885
105c320f 886#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 887#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 888#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
889#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 890
5cc914f1
MA		 891 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
892 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
893 MLX4_CMD_NATIVE);
894
895 if (!err && dev->caps.function != slave) {
0508ad64 896 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 897 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
898
899 /* get port type - currently only eth is enabled */
900 MLX4_GET(port_type, outbox->buf,
901 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
902
105c320f
JM		 903 /* No link sensing allowed */
904 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
905 /* set port type to currently operating port type */
906 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 907
948e306d
RE		 908 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
909 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
910 port_type |= MLX4_PORT_LINK_UP_MASK;
911 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
912 port_type &= ~MLX4_PORT_LINK_UP_MASK;
913
5cc914f1
MA		 914 MLX4_PUT(outbox->buf, port_type,
915 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c
JM		 916
917 short_field = 1; /* slave max gids */
918 MLX4_PUT(outbox->buf, short_field,
919 QUERY_PORT_CUR_MAX_GID_OFFSET);
920
921 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
922 MLX4_PUT(outbox->buf, short_field,
923 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 924 }
925
926 return err;
927}
928
6634961c
JM		 929int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
930 int *gid_tbl_len, int *pkey_tbl_len)
931{
932 struct mlx4_cmd_mailbox *mailbox;
933 u32 *outbox;
934 u16 field;
935 int err;
936
937 mailbox = mlx4_alloc_cmd_mailbox(dev);
938 if (IS_ERR(mailbox))
939 return PTR_ERR(mailbox);
940
941 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
942 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
943 MLX4_CMD_WRAPPED);
944 if (err)
945 goto out;
946
947 outbox = mailbox->buf;
948
949 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
950 *gid_tbl_len = field;
951
952 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
953 *pkey_tbl_len = field;
954
955out:
956 mlx4_free_cmd_mailbox(dev, mailbox);
957 return err;
958}
959EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
960
225c7b1f
RD		 961int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
962{
963 struct mlx4_cmd_mailbox *mailbox;
964 struct mlx4_icm_iter iter;
965 __be64 *pages;
966 int lg;
967 int nent = 0;
968 int i;
969 int err = 0;
970 int ts = 0, tc = 0;
971
972 mailbox = mlx4_alloc_cmd_mailbox(dev);
973 if (IS_ERR(mailbox))
974 return PTR_ERR(mailbox);
225c7b1f
RD		 975 pages = mailbox->buf;
976
977 for (mlx4_icm_first(icm, &iter);
978 !mlx4_icm_last(&iter);
979 mlx4_icm_next(&iter)) {
980 /*
981 * We have to pass pages that are aligned to their
982 * size, so find the least significant 1 in the
983 * address or size and use that as our log2 size.
984 */
985 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
986 if (lg < MLX4_ICM_PAGE_SHIFT) {
987 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
988 MLX4_ICM_PAGE_SIZE,
989 (unsigned long long) mlx4_icm_addr(&iter),
990 mlx4_icm_size(&iter));
991 err = -EINVAL;
992 goto out;
993 }
994
995 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
996 if (virt != -1) {
997 pages[nent * 2] = cpu_to_be64(virt);
998 virt += 1 << lg;
999 }
1000
1001 pages[nent * 2 + 1] =
1002 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1003 (lg - MLX4_ICM_PAGE_SHIFT));
1004 ts += 1 << (lg - 10);
1005 ++tc;
1006
1007 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1008 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1009 MLX4_CMD_TIME_CLASS_B,
1010 MLX4_CMD_NATIVE);
225c7b1f
RD		 1011 if (err)
1012 goto out;
1013 nent = 0;
1014 }
1015 }
1016 }
1017
1018 if (nent)
f9baff50
JM		 1019 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1020 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1021 if (err)
1022 goto out;
1023
1024 switch (op) {
1025 case MLX4_CMD_MAP_FA:
1026 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
1027 break;
1028 case MLX4_CMD_MAP_ICM_AUX:
1029 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
1030 break;
1031 case MLX4_CMD_MAP_ICM:
1032 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
1033 tc, ts, (unsigned long long) virt - (ts << 10));
1034 break;
1035 }
1036
1037out:
1038 mlx4_free_cmd_mailbox(dev, mailbox);
1039 return err;
1040}
1041
1042int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1043{
1044 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1045}
1046
1047int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1048{
f9baff50
JM		 1049 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1050 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1051}
1052
1053
1054int mlx4_RUN_FW(struct mlx4_dev *dev)
1055{
f9baff50
JM		 1056 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1057 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1058}
1059
1060int mlx4_QUERY_FW(struct mlx4_dev *dev)
1061{
1062 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1063 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1064 struct mlx4_cmd_mailbox *mailbox;
1065 u32 *outbox;
1066 int err = 0;
1067 u64 fw_ver;
fe40900f 1068 u16 cmd_if_rev;
225c7b1f
RD		 1069 u8 lg;
1070
1071#define QUERY_FW_OUT_SIZE 0x100
1072#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1073#define QUERY_FW_PPF_ID 0x09
fe40900f 1074#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1075#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1076#define QUERY_FW_ERR_START_OFFSET 0x30
1077#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1078#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1079
1080#define QUERY_FW_SIZE_OFFSET 0x00
1081#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1082#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1083
5cc914f1
MA		 1084#define QUERY_FW_COMM_BASE_OFFSET 0x40
1085#define QUERY_FW_COMM_BAR_OFFSET 0x48
1086
ddd8a6c1
EE		 1087#define QUERY_FW_CLOCK_OFFSET 0x50
1088#define QUERY_FW_CLOCK_BAR 0x58
1089
225c7b1f
RD		 1090 mailbox = mlx4_alloc_cmd_mailbox(dev);
1091 if (IS_ERR(mailbox))
1092 return PTR_ERR(mailbox);
1093 outbox = mailbox->buf;
1094
1095 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1096 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1097 if (err)
1098 goto out;
1099
1100 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1101 /*
3e1db334 1102 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1103 * version, so swap here.
1104 */
1105 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1106 ((fw_ver & 0xffff0000ull) >> 16) |
1107 ((fw_ver & 0x0000ffffull) << 16);
1108
752a50ca
JM		 1109 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1110 dev->caps.function = lg;
1111
b91cb3eb
JM		 1112 if (mlx4_is_slave(dev))
1113 goto out;
1114
5cc914f1 1115
fe40900f 1116 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1117 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1118 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 1119 mlx4_err(dev, "Installed FW has unsupported "
1120 "command interface revision %d.\n",
1121 cmd_if_rev);
1122 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1123 (int) (dev->caps.fw_ver >> 32),
1124 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1125 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 1126 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1127 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1128 err = -ENODEV;
1129 goto out;
1130 }
1131
5ae2a7a8
RD		 1132 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1133 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1134
225c7b1f
RD		 1135 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1136 cmd->max_cmds = 1 << lg;
1137
fe40900f 1138 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1139 (int) (dev->caps.fw_ver >> 32),
1140 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1141 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1142 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1143
1144 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1145 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1146 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1147 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1148
1149 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1150 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1151
1152 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1153 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1154 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1155 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1156
5cc914f1
MA		 1157 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1158 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1159 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1160 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1161 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1162 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1163
ddd8a6c1
EE		 1164 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1165 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1166 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1167 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1168 fw->clock_bar, fw->clock_offset);
1169
225c7b1f
RD		 1170 /*
1171 * Round up number of system pages needed in case
1172 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1173 */
1174 fw->fw_pages =
1175 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1176 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1177
1178 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1179 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1180
1181out:
1182 mlx4_free_cmd_mailbox(dev, mailbox);
1183 return err;
1184}
1185
b91cb3eb
JM		 1186int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1187 struct mlx4_vhcr *vhcr,
1188 struct mlx4_cmd_mailbox *inbox,
1189 struct mlx4_cmd_mailbox *outbox,
1190 struct mlx4_cmd_info *cmd)
1191{
1192 u8 *outbuf;
1193 int err;
1194
1195 outbuf = outbox->buf;
1196 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1197 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1198 if (err)
1199 return err;
1200
752a50ca
JM		 1201 /* for slaves, set pci PPF ID to invalid and zero out everything
1202 * else except FW version */
b91cb3eb
JM		 1203 outbuf[0] = outbuf[1] = 0;
1204 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1205 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1206
b91cb3eb
JM		 1207 return 0;
1208}
1209
225c7b1f
RD		 1210static void get_board_id(void *vsd, char *board_id)
1211{
1212 int i;
1213
1214#define VSD_OFFSET_SIG1 0x00
1215#define VSD_OFFSET_SIG2 0xde
1216#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1217#define VSD_OFFSET_TS_BOARD_ID 0x20
1218
1219#define VSD_SIGNATURE_TOPSPIN 0x5ad
1220
1221 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1222
1223 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1224 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1225 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1226 } else {
1227 /*
1228 * The board ID is a string but the firmware byte
1229 * swaps each 4-byte word before passing it back to
1230 * us. Therefore we need to swab it before printing.
1231 */
1232 for (i = 0; i < 4; ++i)
1233 ((u32 *) board_id)[i] =
1234 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1235 }
1236}
1237
1238int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1239{
1240 struct mlx4_cmd_mailbox *mailbox;
1241 u32 *outbox;
1242 int err;
1243
1244#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1245#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1246#define QUERY_ADAPTER_VSD_OFFSET 0x20
1247
1248 mailbox = mlx4_alloc_cmd_mailbox(dev);
1249 if (IS_ERR(mailbox))
1250 return PTR_ERR(mailbox);
1251 outbox = mailbox->buf;
1252
1253 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1254 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1255 if (err)
1256 goto out;
1257
225c7b1f
RD		 1258 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1259
1260 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1261 adapter->board_id);
1262
1263out:
1264 mlx4_free_cmd_mailbox(dev, mailbox);
1265 return err;
1266}
1267
1268int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1269{
1270 struct mlx4_cmd_mailbox *mailbox;
1271 __be32 *inbox;
1272 int err;
1273
1274#define INIT_HCA_IN_SIZE 0x200
1275#define INIT_HCA_VERSION_OFFSET 0x000
1276#define INIT_HCA_VERSION 2
c57e20dc 1277#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1278#define INIT_HCA_FLAGS_OFFSET 0x014
1279#define INIT_HCA_QPC_OFFSET 0x020
1280#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1281#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1282#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1283#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1284#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1285#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1286#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1287#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1288#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1289#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1290#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1291#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1292#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1293#define INIT_HCA_MCAST_OFFSET 0x0c0
1294#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1295#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1296#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1297#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1298#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1299#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1300#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1301#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1302#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1303#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1304#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1305#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1306#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1307#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1308#define INIT_HCA_TPT_OFFSET 0x0f0
1309#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1310#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1311#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1312#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1313#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1314#define INIT_HCA_UAR_OFFSET 0x120
1315#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1316#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1317
1318 mailbox = mlx4_alloc_cmd_mailbox(dev);
1319 if (IS_ERR(mailbox))
1320 return PTR_ERR(mailbox);
1321 inbox = mailbox->buf;
1322
225c7b1f
RD		 1323 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1324
c57e20dc
EC		 1325 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1326 (ilog2(cache_line_size()) - 4) << 5;
1327
225c7b1f
RD		 1328#if defined(__LITTLE_ENDIAN)
1329 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1330#elif defined(__BIG_ENDIAN)
1331 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1332#else
1333#error Host endianness not defined
1334#endif
1335 /* Check port for UD address vector: */
1336 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1337
8ff095ec
EC		 1338 /* Enable IPoIB checksumming if we can: */
1339 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1340 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1341
51f5f0ee
JM		 1342 /* Enable QoS support if module parameter set */
1343 if (enable_qos)
1344 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1345
f2a3f6a3
OG		 1346 /* enable counters */
1347 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1348 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1349
08ff3235
OG		 1350 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1351 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1352 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1353 dev->caps.eqe_size = 64;
1354 dev->caps.eqe_factor = 1;
1355 } else {
1356 dev->caps.eqe_size = 32;
1357 dev->caps.eqe_factor = 0;
1358 }
1359
1360 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1361 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1362 dev->caps.cqe_size = 64;
1363 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1364 } else {
1365 dev->caps.cqe_size = 32;
1366 }
1367
225c7b1f
RD		 1368 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1369
1370 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1371 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1372 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1373 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1374 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1375 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1376 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1377 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1378 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1379 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1380 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1381 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1382
0ff1fb65
HHZ		 1383 /* steering attributes */
1384 if (dev->caps.steering_mode ==
1385 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1386 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1387 cpu_to_be32(1 <<
1388 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1389
1390 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1391 MLX4_PUT(inbox, param->log_mc_entry_sz,
1392 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1393 MLX4_PUT(inbox, param->log_mc_table_sz,
1394 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1395 /* Enable Ethernet flow steering
1396 * with udp unicast and tcp unicast
1397 */
23537b73 1398 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1399 INIT_HCA_FS_ETH_BITS_OFFSET);
1400 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1401 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1402 /* Enable IPoIB flow steering
1403 * with udp unicast and tcp unicast
1404 */
23537b73 1405 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1406 INIT_HCA_FS_IB_BITS_OFFSET);
1407 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1408 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1409 } else {
1410 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1411 MLX4_PUT(inbox, param->log_mc_entry_sz,
1412 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1413 MLX4_PUT(inbox, param->log_mc_hash_sz,
1414 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1415 MLX4_PUT(inbox, param->log_mc_table_sz,
1416 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1417 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1418 MLX4_PUT(inbox, (u8) (1 << 3),
1419 INIT_HCA_UC_STEERING_OFFSET);
1420 }
225c7b1f
RD		 1421
1422 /* TPT attributes */
1423
1424 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1425 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1426 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1427 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1428 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1429
1430 /* UAR attributes */
1431
ab9c17a0 1432 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1433 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1434
f9baff50
JM		 1435 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1436 MLX4_CMD_NATIVE);
225c7b1f
RD		 1437
1438 if (err)
1439 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1440
1441 mlx4_free_cmd_mailbox(dev, mailbox);
1442 return err;
1443}
1444
ab9c17a0
JM		 1445int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1446 struct mlx4_init_hca_param *param)
1447{
1448 struct mlx4_cmd_mailbox *mailbox;
1449 __be32 *outbox;
7b8157be 1450 u32 dword_field;
ab9c17a0 1451 int err;
08ff3235 1452 u8 byte_field;
ab9c17a0
JM		 1453
1454#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1455#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1456
1457 mailbox = mlx4_alloc_cmd_mailbox(dev);
1458 if (IS_ERR(mailbox))
1459 return PTR_ERR(mailbox);
1460 outbox = mailbox->buf;
1461
1462 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1463 MLX4_CMD_QUERY_HCA,
1464 MLX4_CMD_TIME_CLASS_B,
1465 !mlx4_is_slave(dev));
1466 if (err)
1467 goto out;
1468
1469 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1470 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1471
1472 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1473
1474 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1475 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1476 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1477 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1478 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1479 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1480 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1481 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1482 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1483 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1484 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1485 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1486
7b8157be
JM		 1487 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1488 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1489 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1490 } else {
1491 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1492 if (byte_field & 0x8)
1493 param->steering_mode = MLX4_STEERING_MODE_B0;
1494 else
1495 param->steering_mode = MLX4_STEERING_MODE_A0;
1496 }
0ff1fb65 1497 /* steering attributes */
7b8157be 1498 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1499 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1500 MLX4_GET(param->log_mc_entry_sz, outbox,
1501 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1502 MLX4_GET(param->log_mc_table_sz, outbox,
1503 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1504 } else {
1505 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1506 MLX4_GET(param->log_mc_entry_sz, outbox,
1507 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1508 MLX4_GET(param->log_mc_hash_sz, outbox,
1509 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1510 MLX4_GET(param->log_mc_table_sz, outbox,
1511 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1512 }
ab9c17a0 1513
08ff3235
OG		 1514 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1515 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1516 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1517 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1518 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1519 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1520
ab9c17a0
JM		 1521 /* TPT attributes */
1522
1523 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1524 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1525 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1526 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1527 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1528
1529 /* UAR attributes */
1530
1531 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1532 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1533
1534out:
1535 mlx4_free_cmd_mailbox(dev, mailbox);
1536
1537 return err;
1538}
1539
980e9001
JM		 1540/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1541 * and real QP0 are active, so that the paravirtualized QP0 is ready
1542 * to operate */
1543static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1544{
1545 struct mlx4_priv *priv = mlx4_priv(dev);
1546 /* irrelevant if not infiniband */
1547 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1548 priv->mfunc.master.qp0_state[port].qp0_active)
1549 return 1;
1550 return 0;
1551}
1552
5cc914f1
MA		 1553int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1554 struct mlx4_vhcr *vhcr,
1555 struct mlx4_cmd_mailbox *inbox,
1556 struct mlx4_cmd_mailbox *outbox,
1557 struct mlx4_cmd_info *cmd)
1558{
1559 struct mlx4_priv *priv = mlx4_priv(dev);
1560 int port = vhcr->in_modifier;
1561 int err;
1562
1563 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1564 return 0;
1565
980e9001
JM		 1566 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1567 /* Enable port only if it was previously disabled */
1568 if (!priv->mfunc.master.init_port_ref[port]) {
1569 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1570 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1571 if (err)
1572 return err;
1573 }
1574 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1575 } else {
1576 if (slave == mlx4_master_func_num(dev)) {
1577 if (check_qp0_state(dev, slave, port) &&
1578 !priv->mfunc.master.qp0_state[port].port_active) {
1579 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1580 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1581 if (err)
1582 return err;
1583 priv->mfunc.master.qp0_state[port].port_active = 1;
1584 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1585 }
1586 } else
1587 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1588 }
1589 ++priv->mfunc.master.init_port_ref[port];
1590 return 0;
1591}
1592
5ae2a7a8 1593int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1594{
1595 struct mlx4_cmd_mailbox *mailbox;
1596 u32 *inbox;
1597 int err;
1598 u32 flags;
5ae2a7a8 1599 u16 field;
225c7b1f 1600
5ae2a7a8 1601 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1602#define INIT_PORT_IN_SIZE 256
1603#define INIT_PORT_FLAGS_OFFSET 0x00
1604#define INIT_PORT_FLAG_SIG (1 << 18)
1605#define INIT_PORT_FLAG_NG (1 << 17)
1606#define INIT_PORT_FLAG_G0 (1 << 16)
1607#define INIT_PORT_VL_SHIFT 4
1608#define INIT_PORT_PORT_WIDTH_SHIFT 8
1609#define INIT_PORT_MTU_OFFSET 0x04
1610#define INIT_PORT_MAX_GID_OFFSET 0x06
1611#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1612#define INIT_PORT_GUID0_OFFSET 0x10
1613#define INIT_PORT_NODE_GUID_OFFSET 0x18
1614#define INIT_PORT_SI_GUID_OFFSET 0x20
1615
5ae2a7a8
RD		 1616 mailbox = mlx4_alloc_cmd_mailbox(dev);
1617 if (IS_ERR(mailbox))
1618 return PTR_ERR(mailbox);
1619 inbox = mailbox->buf;
225c7b1f 1620
5ae2a7a8
RD		 1621 flags = 0;
1622 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1623 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1624 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1625
b79acb49 1626 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1627 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1628 field = dev->caps.gid_table_len[port];
1629 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1630 field = dev->caps.pkey_table_len[port];
1631 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1632
5ae2a7a8 1633 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1634 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1635
5ae2a7a8
RD		 1636 mlx4_free_cmd_mailbox(dev, mailbox);
1637 } else
1638 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1639 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1640
1641 return err;
1642}
1643EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1644
5cc914f1
MA		 1645int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1646 struct mlx4_vhcr *vhcr,
1647 struct mlx4_cmd_mailbox *inbox,
1648 struct mlx4_cmd_mailbox *outbox,
1649 struct mlx4_cmd_info *cmd)
1650{
1651 struct mlx4_priv *priv = mlx4_priv(dev);
1652 int port = vhcr->in_modifier;
1653 int err;
1654
1655 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1656 (1 << port)))
1657 return 0;
1658
980e9001
JM		 1659 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1660 if (priv->mfunc.master.init_port_ref[port] == 1) {
1661 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1662 1000, MLX4_CMD_NATIVE);
1663 if (err)
1664 return err;
1665 }
1666 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1667 } else {
1668 /* infiniband port */
1669 if (slave == mlx4_master_func_num(dev)) {
1670 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1671 priv->mfunc.master.qp0_state[port].port_active) {
1672 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1673 1000, MLX4_CMD_NATIVE);
1674 if (err)
1675 return err;
1676 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1677 priv->mfunc.master.qp0_state[port].port_active = 0;
1678 }
1679 } else
1680 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1681 }
5cc914f1
MA		 1682 --priv->mfunc.master.init_port_ref[port];
1683 return 0;
1684}
1685
225c7b1f
RD		 1686int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1687{
f9baff50
JM		 1688 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1689 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1690}
1691EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1692
1693int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1694{
f9baff50
JM		 1695 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1696 MLX4_CMD_NATIVE);
225c7b1f
RD		 1697}
1698
1699int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1700{
1701 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1702 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1703 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1704 if (ret)
1705 return ret;
1706
1707 /*
1708 * Round up number of system pages needed in case
1709 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1710 */
1711 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1712 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1713
1714 return 0;
1715}
1716
1717int mlx4_NOP(struct mlx4_dev *dev)
1718{
1719 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1720 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1721}
14c07b13 1722
8e1a28e8
HHZ		 1723int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1724{
1725 u8 port;
1726 u32 *outbox;
1727 struct mlx4_cmd_mailbox *mailbox;
1728 u32 in_mod;
1729 u32 guid_hi, guid_lo;
1730 int err, ret = 0;
1731#define MOD_STAT_CFG_PORT_OFFSET 8
1732#define MOD_STAT_CFG_GUID_H 0X14
1733#define MOD_STAT_CFG_GUID_L 0X1c
1734
1735 mailbox = mlx4_alloc_cmd_mailbox(dev);
1736 if (IS_ERR(mailbox))
1737 return PTR_ERR(mailbox);
1738 outbox = mailbox->buf;
1739
1740 for (port = 1; port <= dev->caps.num_ports; port++) {
1741 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1742 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1743 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1744 MLX4_CMD_NATIVE);
1745 if (err) {
1746 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1747 port);
1748 ret = err;
1749 } else {
1750 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1751 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1752 dev->caps.phys_port_id[port] = (u64)guid_lo |
1753 (u64)guid_hi << 32;
1754 }
1755 }
1756 mlx4_free_cmd_mailbox(dev, mailbox);
1757 return ret;
1758}
1759
14c07b13
YP		 1760#define MLX4_WOL_SETUP_MODE (5 << 28)
1761int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1762{
1763 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1764
1765 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1766 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1767 MLX4_CMD_NATIVE);
14c07b13
YP		 1768}
1769EXPORT_SYMBOL_GPL(mlx4_wol_read);
1770
1771int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1772{
1773 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1774
1775 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1776 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1777}
1778EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 1779
1780enum {
1781 ADD_TO_MCG = 0x26,
1782};
1783
1784
1785void mlx4_opreq_action(struct work_struct *work)
1786{
1787 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1788 opreq_task);
1789 struct mlx4_dev *dev = &priv->dev;
1790 int num_tasks = atomic_read(&priv->opreq_count);
1791 struct mlx4_cmd_mailbox *mailbox;
1792 struct mlx4_mgm *mgm;
1793 u32 *outbox;
1794 u32 modifier;
1795 u16 token;
fe6f700d
YP		 1796 u16 type;
1797 int err;
1798 u32 num_qps;
1799 struct mlx4_qp qp;
1800 int i;
1801 u8 rem_mcg;
1802 u8 prot;
1803
1804#define GET_OP_REQ_MODIFIER_OFFSET 0x08
1805#define GET_OP_REQ_TOKEN_OFFSET 0x14
1806#define GET_OP_REQ_TYPE_OFFSET 0x1a
1807#define GET_OP_REQ_DATA_OFFSET 0x20
1808
1809 mailbox = mlx4_alloc_cmd_mailbox(dev);
1810 if (IS_ERR(mailbox)) {
1811 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1812 return;
1813 }
1814 outbox = mailbox->buf;
1815
1816 while (num_tasks) {
1817 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1818 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1819 MLX4_CMD_NATIVE);
1820 if (err) {
6d3be300 1821 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 1822 err);
1823 return;
1824 }
1825 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1826 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1827 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 1828 type &= 0xfff;
1829
1830 switch (type) {
1831 case ADD_TO_MCG:
1832 if (dev->caps.steering_mode ==
1833 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1834 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1835 err = EPERM;
1836 break;
1837 }
1838 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1839 GET_OP_REQ_DATA_OFFSET);
1840 num_qps = be32_to_cpu(mgm->members_count) &
1841 MGM_QPN_MASK;
1842 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1843 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1844
1845 for (i = 0; i < num_qps; i++) {
1846 qp.qpn = be32_to_cpu(mgm->qp[i]);
1847 if (rem_mcg)
1848 err = mlx4_multicast_detach(dev, &qp,
1849 mgm->gid,
1850 prot, 0);
1851 else
1852 err = mlx4_multicast_attach(dev, &qp,
1853 mgm->gid,
1854 mgm->gid[5]
1855 , 0, prot,
1856 NULL);
1857 if (err)
1858 break;
1859 }
1860 break;
1861 default:
1862 mlx4_warn(dev, "Bad type for required operation\n");
1863 err = EINVAL;
1864 break;
1865 }
1866 err = mlx4_cmd(dev, 0, ((u32) err | cpu_to_be32(token) << 16),
1867 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1868 MLX4_CMD_NATIVE);
1869 if (err) {
1870 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1871 err);
1872 goto out;
1873 }
1874 memset(outbox, 0, 0xffc);
1875 num_tasks = atomic_dec_return(&priv->opreq_count);
1876 }
1877
1878out:
1879 mlx4_free_cmd_mailbox(dev, mailbox);
1880}
Linux kernel - Deliverables
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