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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
5cc914f1 | 35 | #include <linux/etherdevice.h> |
225c7b1f | 36 | #include <linux/mlx4/cmd.h> |
9d9779e7 | 37 | #include <linux/module.h> |
c57e20dc | 38 | #include <linux/cache.h> |
225c7b1f RD |
39 | |
40 | #include "fw.h" | |
41 | #include "icm.h" | |
42 | ||
fe40900f | 43 | enum { |
5ae2a7a8 RD |
44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, | |
46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, | |
fe40900f RD |
47 | }; |
48 | ||
225c7b1f RD |
49 | extern void __buggy_use_of_MLX4_GET(void); |
50 | extern void __buggy_use_of_MLX4_PUT(void); | |
51 | ||
eb939922 | 52 | static bool enable_qos; |
51f5f0ee JM |
53 | module_param(enable_qos, bool, 0444); |
54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); | |
55 | ||
225c7b1f RD |
56 | #define MLX4_GET(dest, source, offset) \ |
57 | do { \ | |
58 | void *__p = (char *) (source) + (offset); \ | |
59 | switch (sizeof (dest)) { \ | |
60 | case 1: (dest) = *(u8 *) __p; break; \ | |
61 | case 2: (dest) = be16_to_cpup(__p); break; \ | |
62 | case 4: (dest) = be32_to_cpup(__p); break; \ | |
63 | case 8: (dest) = be64_to_cpup(__p); break; \ | |
64 | default: __buggy_use_of_MLX4_GET(); \ | |
65 | } \ | |
66 | } while (0) | |
67 | ||
68 | #define MLX4_PUT(dest, source, offset) \ | |
69 | do { \ | |
70 | void *__d = ((char *) (dest) + (offset)); \ | |
71 | switch (sizeof(source)) { \ | |
72 | case 1: *(u8 *) __d = (source); break; \ | |
73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ | |
74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ | |
75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ | |
76 | default: __buggy_use_of_MLX4_PUT(); \ | |
77 | } \ | |
78 | } while (0) | |
79 | ||
52eafc68 | 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
225c7b1f RD |
81 | { |
82 | static const char *fname[] = { | |
83 | [ 0] = "RC transport", | |
84 | [ 1] = "UC transport", | |
85 | [ 2] = "UD transport", | |
ea98054f | 86 | [ 3] = "XRC transport", |
225c7b1f RD |
87 | [ 4] = "reliable multicast", |
88 | [ 5] = "FCoIB support", | |
89 | [ 6] = "SRQ support", | |
90 | [ 7] = "IPoIB checksum offload", | |
91 | [ 8] = "P_Key violation counter", | |
92 | [ 9] = "Q_Key violation counter", | |
93 | [10] = "VMM", | |
4d531aa8 | 94 | [12] = "Dual Port Different Protocol (DPDP) support", |
417608c2 | 95 | [15] = "Big LSO headers", |
225c7b1f RD |
96 | [16] = "MW support", |
97 | [17] = "APM support", | |
98 | [18] = "Atomic ops support", | |
99 | [19] = "Raw multicast support", | |
100 | [20] = "Address vector port checking support", | |
101 | [21] = "UD multicast support", | |
102 | [24] = "Demand paging support", | |
96dfa684 | 103 | [25] = "Router support", |
ccf86321 OG |
104 | [30] = "IBoE support", |
105 | [32] = "Unicast loopback support", | |
f3a9d1f2 | 106 | [34] = "FCS header control", |
ccf86321 OG |
107 | [38] = "Wake On LAN support", |
108 | [40] = "UDP RSS support", | |
109 | [41] = "Unicast VEP steering support", | |
f2a3f6a3 OG |
110 | [42] = "Multicast VEP steering support", |
111 | [48] = "Counters support", | |
540b3a39 | 112 | [53] = "Port ETS Scheduler support", |
4d531aa8 | 113 | [55] = "Port link type sensing support", |
00f5ce99 | 114 | [59] = "Port management change event support", |
08ff3235 OG |
115 | [61] = "64 byte EQE support", |
116 | [62] = "64 byte CQE support", | |
225c7b1f RD |
117 | }; |
118 | int i; | |
119 | ||
120 | mlx4_dbg(dev, "DEV_CAP flags:\n"); | |
23c15c21 | 121 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
52eafc68 | 122 | if (fname[i] && (flags & (1LL << i))) |
225c7b1f RD |
123 | mlx4_dbg(dev, " %s\n", fname[i]); |
124 | } | |
125 | ||
b3416f44 SP |
126 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
127 | { | |
128 | static const char * const fname[] = { | |
129 | [0] = "RSS support", | |
130 | [1] = "RSS Toeplitz Hash Function support", | |
0ff1fb65 | 131 | [2] = "RSS XOR Hash Function support", |
955154fa | 132 | [3] = "Device manage flow steering support", |
d998735f | 133 | [4] = "Automatic MAC reassignment support", |
4e8cf5b8 OG |
134 | [5] = "Time stamping support", |
135 | [6] = "VST (control vlan insertion/stripping) support", | |
136 | [7] = "FSM (MAC anti-spoofing) support" | |
b3416f44 SP |
137 | }; |
138 | int i; | |
139 | ||
140 | for (i = 0; i < ARRAY_SIZE(fname); ++i) | |
141 | if (fname[i] && (flags & (1LL << i))) | |
142 | mlx4_dbg(dev, " %s\n", fname[i]); | |
143 | } | |
144 | ||
2d928651 VS |
145 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
146 | { | |
147 | struct mlx4_cmd_mailbox *mailbox; | |
148 | u32 *inbox; | |
149 | int err = 0; | |
150 | ||
151 | #define MOD_STAT_CFG_IN_SIZE 0x100 | |
152 | ||
153 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 | |
154 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 | |
155 | ||
156 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
157 | if (IS_ERR(mailbox)) | |
158 | return PTR_ERR(mailbox); | |
159 | inbox = mailbox->buf; | |
160 | ||
161 | memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); | |
162 | ||
163 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); | |
164 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); | |
165 | ||
166 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 167 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
2d928651 VS |
168 | |
169 | mlx4_free_cmd_mailbox(dev, mailbox); | |
170 | return err; | |
171 | } | |
172 | ||
5cc914f1 MA |
173 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
174 | struct mlx4_vhcr *vhcr, | |
175 | struct mlx4_cmd_mailbox *inbox, | |
176 | struct mlx4_cmd_mailbox *outbox, | |
177 | struct mlx4_cmd_info *cmd) | |
178 | { | |
179 | u8 field; | |
180 | u32 size; | |
181 | int err = 0; | |
182 | ||
183 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 | |
184 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 | |
5cc914f1 | 185 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
105c320f | 186 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
5cc914f1 MA |
187 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 |
188 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 | |
189 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 | |
190 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 | |
191 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 | |
192 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 | |
193 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c | |
69612b9f | 194 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
5cc914f1 | 195 | |
105c320f JM |
196 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
197 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 | |
198 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 | |
199 | ||
200 | /* when opcode modifier = 1 */ | |
5cc914f1 | 201 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
105c320f | 202 | #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 |
5cc914f1 MA |
203 | #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc |
204 | ||
47605df9 JM |
205 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
206 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 | |
207 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 | |
208 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c | |
209 | ||
105c320f JM |
210 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 |
211 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 | |
212 | ||
213 | #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 | |
214 | ||
5cc914f1 | 215 | if (vhcr->op_modifier == 1) { |
105c320f JM |
216 | field = 0; |
217 | /* ensure force vlan and force mac bits are not set */ | |
5cc914f1 | 218 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); |
105c320f JM |
219 | /* ensure that phy_wqe_gid bit is not set */ |
220 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); | |
221 | ||
47605df9 JM |
222 | field = vhcr->in_modifier; /* phys-port = logical-port */ |
223 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); | |
224 | ||
225 | /* size is now the QP number */ | |
226 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; | |
227 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); | |
228 | ||
229 | size += 2; | |
230 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); | |
231 | ||
232 | size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; | |
233 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); | |
234 | ||
235 | size += 2; | |
236 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); | |
237 | ||
5cc914f1 | 238 | } else if (vhcr->op_modifier == 0) { |
105c320f JM |
239 | /* enable rdma and ethernet interfaces */ |
240 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); | |
5cc914f1 MA |
241 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
242 | ||
5cc914f1 MA |
243 | field = dev->caps.num_ports; |
244 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); | |
245 | ||
08ff3235 | 246 | size = dev->caps.function_caps; /* set PF behaviours */ |
5cc914f1 MA |
247 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
248 | ||
105c320f JM |
249 | field = 0; /* protected FMR support not available as yet */ |
250 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); | |
251 | ||
5cc914f1 MA |
252 | size = dev->caps.num_qps; |
253 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); | |
254 | ||
255 | size = dev->caps.num_srqs; | |
256 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); | |
257 | ||
258 | size = dev->caps.num_cqs; | |
259 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); | |
260 | ||
261 | size = dev->caps.num_eqs; | |
262 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); | |
263 | ||
264 | size = dev->caps.reserved_eqs; | |
265 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); | |
266 | ||
267 | size = dev->caps.num_mpts; | |
268 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); | |
269 | ||
2b8fb286 | 270 | size = dev->caps.num_mtts; |
5cc914f1 MA |
271 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
272 | ||
273 | size = dev->caps.num_mgms + dev->caps.num_amgms; | |
274 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); | |
275 | ||
276 | } else | |
277 | err = -EINVAL; | |
278 | ||
279 | return err; | |
280 | } | |
281 | ||
47605df9 JM |
282 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, |
283 | struct mlx4_func_cap *func_cap) | |
5cc914f1 MA |
284 | { |
285 | struct mlx4_cmd_mailbox *mailbox; | |
286 | u32 *outbox; | |
47605df9 | 287 | u8 field, op_modifier; |
5cc914f1 | 288 | u32 size; |
5cc914f1 MA |
289 | int err = 0; |
290 | ||
47605df9 | 291 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
5cc914f1 MA |
292 | |
293 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
294 | if (IS_ERR(mailbox)) | |
295 | return PTR_ERR(mailbox); | |
296 | ||
47605df9 JM |
297 | err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, |
298 | MLX4_CMD_QUERY_FUNC_CAP, | |
5cc914f1 MA |
299 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
300 | if (err) | |
301 | goto out; | |
302 | ||
303 | outbox = mailbox->buf; | |
304 | ||
47605df9 JM |
305 | if (!op_modifier) { |
306 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); | |
307 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { | |
308 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); | |
309 | err = -EPROTONOSUPPORT; | |
310 | goto out; | |
311 | } | |
312 | func_cap->flags = field; | |
5cc914f1 | 313 | |
47605df9 JM |
314 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
315 | func_cap->num_ports = field; | |
5cc914f1 | 316 | |
47605df9 JM |
317 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
318 | func_cap->pf_context_behaviour = size; | |
5cc914f1 | 319 | |
47605df9 JM |
320 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
321 | func_cap->qp_quota = size & 0xFFFFFF; | |
5cc914f1 | 322 | |
47605df9 JM |
323 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
324 | func_cap->srq_quota = size & 0xFFFFFF; | |
5cc914f1 | 325 | |
47605df9 JM |
326 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
327 | func_cap->cq_quota = size & 0xFFFFFF; | |
5cc914f1 | 328 | |
47605df9 JM |
329 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
330 | func_cap->max_eq = size & 0xFFFFFF; | |
5cc914f1 | 331 | |
47605df9 JM |
332 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
333 | func_cap->reserved_eq = size & 0xFFFFFF; | |
5cc914f1 | 334 | |
47605df9 JM |
335 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
336 | func_cap->mpt_quota = size & 0xFFFFFF; | |
5cc914f1 | 337 | |
47605df9 JM |
338 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
339 | func_cap->mtt_quota = size & 0xFFFFFF; | |
5cc914f1 | 340 | |
47605df9 JM |
341 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
342 | func_cap->mcg_quota = size & 0xFFFFFF; | |
343 | goto out; | |
344 | } | |
5cc914f1 | 345 | |
47605df9 JM |
346 | /* logical port query */ |
347 | if (gen_or_port > dev->caps.num_ports) { | |
348 | err = -EINVAL; | |
349 | goto out; | |
350 | } | |
5cc914f1 | 351 | |
47605df9 JM |
352 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
353 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); | |
354 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { | |
355 | mlx4_err(dev, "VLAN is enforced on this port\n"); | |
356 | err = -EPROTONOSUPPORT; | |
5cc914f1 | 357 | goto out; |
47605df9 | 358 | } |
5cc914f1 | 359 | |
47605df9 JM |
360 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { |
361 | mlx4_err(dev, "Force mac is enabled on this port\n"); | |
362 | err = -EPROTONOSUPPORT; | |
363 | goto out; | |
5cc914f1 | 364 | } |
47605df9 JM |
365 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
366 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); | |
367 | if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { | |
368 | mlx4_err(dev, "phy_wqe_gid is " | |
369 | "enforced on this ib port\n"); | |
370 | err = -EPROTONOSUPPORT; | |
371 | goto out; | |
372 | } | |
373 | } | |
5cc914f1 | 374 | |
47605df9 JM |
375 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
376 | func_cap->physical_port = field; | |
377 | if (func_cap->physical_port != gen_or_port) { | |
378 | err = -ENOSYS; | |
379 | goto out; | |
5cc914f1 MA |
380 | } |
381 | ||
47605df9 JM |
382 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
383 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; | |
384 | ||
385 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); | |
386 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; | |
387 | ||
388 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); | |
389 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; | |
390 | ||
391 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); | |
392 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; | |
393 | ||
5cc914f1 MA |
394 | /* All other resources are allocated by the master, but we still report |
395 | * 'num' and 'reserved' capabilities as follows: | |
396 | * - num remains the maximum resource index | |
397 | * - 'num - reserved' is the total available objects of a resource, but | |
398 | * resource indices may be less than 'reserved' | |
399 | * TODO: set per-resource quotas */ | |
400 | ||
401 | out: | |
402 | mlx4_free_cmd_mailbox(dev, mailbox); | |
403 | ||
404 | return err; | |
405 | } | |
406 | ||
225c7b1f RD |
407 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
408 | { | |
409 | struct mlx4_cmd_mailbox *mailbox; | |
410 | u32 *outbox; | |
411 | u8 field; | |
ccf86321 | 412 | u32 field32, flags, ext_flags; |
225c7b1f RD |
413 | u16 size; |
414 | u16 stat_rate; | |
415 | int err; | |
5ae2a7a8 | 416 | int i; |
225c7b1f RD |
417 | |
418 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 | |
419 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 | |
420 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 | |
421 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 | |
422 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 | |
423 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 | |
424 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 | |
425 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 | |
426 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 | |
427 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 | |
428 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a | |
429 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b | |
430 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d | |
431 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e | |
432 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f | |
433 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 | |
434 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 | |
435 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 | |
436 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 | |
437 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 | |
438 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 | |
439 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b | |
b832be1e | 440 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
b3416f44 | 441 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
225c7b1f RD |
442 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
443 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 | |
444 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 | |
445 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 | |
446 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 | |
149983af | 447 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
225c7b1f RD |
448 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
449 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c | |
d998735f | 450 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
225c7b1f | 451 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
ccf86321 | 452 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
225c7b1f RD |
453 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
454 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 | |
455 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 | |
456 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b | |
457 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c | |
458 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d | |
459 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e | |
460 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f | |
461 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 | |
462 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 | |
463 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 | |
464 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
465 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 | |
466 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 | |
467 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 | |
468 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 | |
469 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 | |
012a8ff5 SH |
470 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
471 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 | |
f2a3f6a3 | 472 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
3f7fb021 | 473 | #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 |
0ff1fb65 HHZ |
474 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
475 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 | |
225c7b1f RD |
476 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
477 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 | |
478 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 | |
479 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 | |
480 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 | |
481 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a | |
482 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c | |
483 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e | |
484 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 | |
485 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 | |
95d04f07 | 486 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
225c7b1f RD |
487 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
488 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 | |
955154fa | 489 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
225c7b1f | 490 | |
b3416f44 | 491 | dev_cap->flags2 = 0; |
225c7b1f RD |
492 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
493 | if (IS_ERR(mailbox)) | |
494 | return PTR_ERR(mailbox); | |
495 | outbox = mailbox->buf; | |
496 | ||
497 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
401453a3 | 498 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
499 | if (err) |
500 | goto out; | |
501 | ||
502 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); | |
503 | dev_cap->reserved_qps = 1 << (field & 0xf); | |
504 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); | |
505 | dev_cap->max_qps = 1 << (field & 0x1f); | |
506 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); | |
507 | dev_cap->reserved_srqs = 1 << (field >> 4); | |
508 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); | |
509 | dev_cap->max_srqs = 1 << (field & 0x1f); | |
510 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); | |
511 | dev_cap->max_cq_sz = 1 << field; | |
512 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); | |
513 | dev_cap->reserved_cqs = 1 << (field & 0xf); | |
514 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); | |
515 | dev_cap->max_cqs = 1 << (field & 0x1f); | |
516 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); | |
517 | dev_cap->max_mpts = 1 << (field & 0x3f); | |
518 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); | |
be504b0b | 519 | dev_cap->reserved_eqs = field & 0xf; |
225c7b1f | 520 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
5920869f | 521 | dev_cap->max_eqs = 1 << (field & 0xf); |
225c7b1f RD |
522 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
523 | dev_cap->reserved_mtts = 1 << (field >> 4); | |
524 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); | |
525 | dev_cap->max_mrw_sz = 1 << field; | |
526 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); | |
527 | dev_cap->reserved_mrws = 1 << (field & 0xf); | |
528 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); | |
529 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); | |
530 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); | |
531 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); | |
532 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); | |
533 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); | |
b832be1e EC |
534 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
535 | field &= 0x1f; | |
536 | if (!field) | |
537 | dev_cap->max_gso_sz = 0; | |
538 | else | |
539 | dev_cap->max_gso_sz = 1 << field; | |
540 | ||
b3416f44 SP |
541 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
542 | if (field & 0x20) | |
543 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; | |
544 | if (field & 0x10) | |
545 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; | |
546 | field &= 0xf; | |
547 | if (field) { | |
548 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; | |
549 | dev_cap->max_rss_tbl_sz = 1 << field; | |
550 | } else | |
551 | dev_cap->max_rss_tbl_sz = 0; | |
225c7b1f RD |
552 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
553 | dev_cap->max_rdma_global = 1 << (field & 0x3f); | |
554 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); | |
555 | dev_cap->local_ca_ack_delay = field & 0x1f; | |
225c7b1f | 556 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
225c7b1f | 557 | dev_cap->num_ports = field & 0xf; |
149983af DB |
558 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
559 | dev_cap->max_msg_sz = 1 << (field & 0x1f); | |
0ff1fb65 HHZ |
560 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
561 | if (field & 0x80) | |
562 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; | |
563 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; | |
564 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); | |
565 | dev_cap->fs_max_num_qp_per_entry = field; | |
225c7b1f RD |
566 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
567 | dev_cap->stat_rate_support = stat_rate; | |
d998735f EE |
568 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
569 | if (field & 0x80) | |
570 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; | |
ccf86321 | 571 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
52eafc68 | 572 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
ccf86321 | 573 | dev_cap->flags = flags | (u64)ext_flags << 32; |
225c7b1f RD |
574 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
575 | dev_cap->reserved_uars = field >> 4; | |
576 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); | |
577 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); | |
578 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); | |
579 | dev_cap->min_page_sz = 1 << field; | |
580 | ||
581 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); | |
582 | if (field & 0x80) { | |
583 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); | |
584 | dev_cap->bf_reg_size = 1 << (field & 0x1f); | |
585 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); | |
f5a49539 | 586 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
58d74bb1 | 587 | field = 3; |
225c7b1f RD |
588 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
589 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", | |
590 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); | |
591 | } else { | |
592 | dev_cap->bf_reg_size = 0; | |
593 | mlx4_dbg(dev, "BlueFlame not available\n"); | |
594 | } | |
595 | ||
596 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); | |
597 | dev_cap->max_sq_sg = field; | |
598 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); | |
599 | dev_cap->max_sq_desc_sz = size; | |
600 | ||
601 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); | |
602 | dev_cap->max_qp_per_mcg = 1 << field; | |
603 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); | |
604 | dev_cap->reserved_mgms = field & 0xf; | |
605 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); | |
606 | dev_cap->max_mcgs = 1 << field; | |
607 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); | |
608 | dev_cap->reserved_pds = field >> 4; | |
609 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
610 | dev_cap->max_pds = 1 << (field & 0x3f); | |
012a8ff5 SH |
611 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
612 | dev_cap->reserved_xrcds = field >> 4; | |
426dd00d | 613 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
012a8ff5 | 614 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
225c7b1f RD |
615 | |
616 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); | |
617 | dev_cap->rdmarc_entry_sz = size; | |
618 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); | |
619 | dev_cap->qpc_entry_sz = size; | |
620 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); | |
621 | dev_cap->aux_entry_sz = size; | |
622 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); | |
623 | dev_cap->altc_entry_sz = size; | |
624 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); | |
625 | dev_cap->eqc_entry_sz = size; | |
626 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); | |
627 | dev_cap->cqc_entry_sz = size; | |
628 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); | |
629 | dev_cap->srq_entry_sz = size; | |
630 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); | |
631 | dev_cap->cmpt_entry_sz = size; | |
632 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); | |
633 | dev_cap->mtt_entry_sz = size; | |
634 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); | |
635 | dev_cap->dmpt_entry_sz = size; | |
636 | ||
637 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); | |
638 | dev_cap->max_srq_sz = 1 << field; | |
639 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); | |
640 | dev_cap->max_qp_sz = 1 << field; | |
641 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); | |
642 | dev_cap->resize_srq = field & 1; | |
643 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); | |
644 | dev_cap->max_rq_sg = field; | |
645 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); | |
646 | dev_cap->max_rq_desc_sz = size; | |
647 | ||
648 | MLX4_GET(dev_cap->bmme_flags, outbox, | |
649 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
650 | MLX4_GET(dev_cap->reserved_lkey, outbox, | |
651 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); | |
955154fa MB |
652 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
653 | if (field & 1<<6) | |
654 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN; | |
225c7b1f RD |
655 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
656 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); | |
f2a3f6a3 OG |
657 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
658 | MLX4_GET(dev_cap->max_counters, outbox, | |
659 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); | |
225c7b1f | 660 | |
3f7fb021 RE |
661 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
662 | if (field32 & (1 << 26)) | |
663 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; | |
e6b6a231 RE |
664 | if (field32 & (1 << 20)) |
665 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; | |
3f7fb021 | 666 | |
5ae2a7a8 RD |
667 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
668 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
669 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); | |
670 | dev_cap->max_vl[i] = field >> 4; | |
671 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); | |
b79acb49 | 672 | dev_cap->ib_mtu[i] = field >> 4; |
5ae2a7a8 RD |
673 | dev_cap->max_port_width[i] = field & 0xf; |
674 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); | |
675 | dev_cap->max_gids[i] = 1 << (field & 0xf); | |
676 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); | |
677 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
678 | } | |
679 | } else { | |
7ff93f8b | 680 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
5ae2a7a8 | 681 | #define QUERY_PORT_MTU_OFFSET 0x01 |
b79acb49 | 682 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
5ae2a7a8 RD |
683 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
684 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 | |
93fc9e1b | 685 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
5ae2a7a8 | 686 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
e65b9591 | 687 | #define QUERY_PORT_MAC_OFFSET 0x10 |
7699517d YP |
688 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
689 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c | |
690 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 | |
5ae2a7a8 RD |
691 | |
692 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
693 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, | |
401453a3 | 694 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
5ae2a7a8 RD |
695 | if (err) |
696 | goto out; | |
697 | ||
7ff93f8b YP |
698 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
699 | dev_cap->supported_port_types[i] = field & 3; | |
8d0fc7b6 YP |
700 | dev_cap->suggested_type[i] = (field >> 3) & 1; |
701 | dev_cap->default_sense[i] = (field >> 4) & 1; | |
5ae2a7a8 | 702 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
b79acb49 | 703 | dev_cap->ib_mtu[i] = field & 0xf; |
5ae2a7a8 RD |
704 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
705 | dev_cap->max_port_width[i] = field & 0xf; | |
706 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); | |
707 | dev_cap->max_gids[i] = 1 << (field >> 4); | |
708 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
709 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); | |
710 | dev_cap->max_vl[i] = field & 0xf; | |
93fc9e1b YP |
711 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
712 | dev_cap->log_max_macs[i] = field & 0xf; | |
713 | dev_cap->log_max_vlans[i] = field >> 4; | |
b79acb49 YP |
714 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
715 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); | |
7699517d YP |
716 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
717 | dev_cap->trans_type[i] = field32 >> 24; | |
718 | dev_cap->vendor_oui[i] = field32 & 0xffffff; | |
719 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); | |
720 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); | |
5ae2a7a8 RD |
721 | } |
722 | } | |
723 | ||
95d04f07 RD |
724 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
725 | dev_cap->bmme_flags, dev_cap->reserved_lkey); | |
225c7b1f RD |
726 | |
727 | /* | |
728 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then | |
729 | * we can't use any EQs whose doorbell falls on that page, | |
730 | * even if the EQ itself isn't reserved. | |
731 | */ | |
732 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, | |
733 | dev_cap->reserved_eqs); | |
734 | ||
735 | mlx4_dbg(dev, "Max ICM size %lld MB\n", | |
736 | (unsigned long long) dev_cap->max_icm_sz >> 20); | |
737 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", | |
738 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); | |
739 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
740 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); | |
741 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
742 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); | |
743 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
744 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); | |
745 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
746 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); | |
747 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
748 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); | |
749 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
750 | dev_cap->max_pds, dev_cap->reserved_mgms); | |
751 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
752 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); | |
753 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", | |
b79acb49 | 754 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
5ae2a7a8 | 755 | dev_cap->max_port_width[1]); |
225c7b1f RD |
756 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
757 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); | |
758 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", | |
759 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); | |
b832be1e | 760 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
f2a3f6a3 | 761 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
b3416f44 | 762 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
225c7b1f RD |
763 | |
764 | dump_dev_cap_flags(dev, dev_cap->flags); | |
b3416f44 | 765 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
225c7b1f RD |
766 | |
767 | out: | |
768 | mlx4_free_cmd_mailbox(dev, mailbox); | |
769 | return err; | |
770 | } | |
771 | ||
b91cb3eb JM |
772 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
773 | struct mlx4_vhcr *vhcr, | |
774 | struct mlx4_cmd_mailbox *inbox, | |
775 | struct mlx4_cmd_mailbox *outbox, | |
776 | struct mlx4_cmd_info *cmd) | |
777 | { | |
2a4fae14 | 778 | u64 flags; |
b91cb3eb JM |
779 | int err = 0; |
780 | u8 field; | |
cc1ade94 | 781 | u32 bmme_flags; |
b91cb3eb JM |
782 | |
783 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
784 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
785 | if (err) | |
786 | return err; | |
787 | ||
cc1ade94 SM |
788 | /* add port mng change event capability and disable mw type 1 |
789 | * unconditionally to slaves | |
790 | */ | |
2a4fae14 JM |
791 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
792 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; | |
cc1ade94 | 793 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
2a4fae14 JM |
794 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
795 | ||
30b40c31 AV |
796 | /* For guests, disable timestamp */ |
797 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); | |
798 | field &= 0x7f; | |
799 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); | |
800 | ||
b91cb3eb JM |
801 | /* For guests, report Blueflame disabled */ |
802 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); | |
803 | field &= 0x7f; | |
804 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); | |
805 | ||
cc1ade94 SM |
806 | /* For guests, disable mw type 2 */ |
807 | MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
808 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; | |
809 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
810 | ||
0081c8f3 JM |
811 | /* turn off device-managed steering capability if not enabled */ |
812 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
813 | MLX4_GET(field, outbox->buf, | |
814 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); | |
815 | field &= 0x7f; | |
816 | MLX4_PUT(outbox->buf, field, | |
817 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); | |
818 | } | |
b91cb3eb JM |
819 | return 0; |
820 | } | |
821 | ||
5cc914f1 MA |
822 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
823 | struct mlx4_vhcr *vhcr, | |
824 | struct mlx4_cmd_mailbox *inbox, | |
825 | struct mlx4_cmd_mailbox *outbox, | |
826 | struct mlx4_cmd_info *cmd) | |
827 | { | |
0eb62b93 | 828 | struct mlx4_priv *priv = mlx4_priv(dev); |
5cc914f1 MA |
829 | u64 def_mac; |
830 | u8 port_type; | |
6634961c | 831 | u16 short_field; |
5cc914f1 | 832 | int err; |
948e306d | 833 | int admin_link_state; |
5cc914f1 | 834 | |
105c320f | 835 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
948e306d | 836 | #define MLX4_PORT_LINK_UP_MASK 0x80 |
6634961c JM |
837 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
838 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e | |
95f56e7a | 839 | |
5cc914f1 MA |
840 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
841 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
842 | MLX4_CMD_NATIVE); | |
843 | ||
844 | if (!err && dev->caps.function != slave) { | |
0eb62b93 RE |
845 | /* if config MAC in DB use it */ |
846 | if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac) | |
847 | def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; | |
c418253f OG |
848 | else { |
849 | /* set slave default_mac address */ | |
850 | MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); | |
851 | def_mac += slave << 8; | |
852 | priv->mfunc.master.vf_admin[slave].vport[vhcr->in_modifier].mac = def_mac; | |
853 | } | |
854 | ||
5cc914f1 MA |
855 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
856 | ||
857 | /* get port type - currently only eth is enabled */ | |
858 | MLX4_GET(port_type, outbox->buf, | |
859 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
860 | ||
105c320f JM |
861 | /* No link sensing allowed */ |
862 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; | |
863 | /* set port type to currently operating port type */ | |
864 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); | |
5cc914f1 | 865 | |
948e306d RE |
866 | admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; |
867 | if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) | |
868 | port_type |= MLX4_PORT_LINK_UP_MASK; | |
869 | else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) | |
870 | port_type &= ~MLX4_PORT_LINK_UP_MASK; | |
871 | ||
5cc914f1 MA |
872 | MLX4_PUT(outbox->buf, port_type, |
873 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
6634961c JM |
874 | |
875 | short_field = 1; /* slave max gids */ | |
876 | MLX4_PUT(outbox->buf, short_field, | |
877 | QUERY_PORT_CUR_MAX_GID_OFFSET); | |
878 | ||
879 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; | |
880 | MLX4_PUT(outbox->buf, short_field, | |
881 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); | |
5cc914f1 MA |
882 | } |
883 | ||
884 | return err; | |
885 | } | |
886 | ||
6634961c JM |
887 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
888 | int *gid_tbl_len, int *pkey_tbl_len) | |
889 | { | |
890 | struct mlx4_cmd_mailbox *mailbox; | |
891 | u32 *outbox; | |
892 | u16 field; | |
893 | int err; | |
894 | ||
895 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
896 | if (IS_ERR(mailbox)) | |
897 | return PTR_ERR(mailbox); | |
898 | ||
899 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, | |
900 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
901 | MLX4_CMD_WRAPPED); | |
902 | if (err) | |
903 | goto out; | |
904 | ||
905 | outbox = mailbox->buf; | |
906 | ||
907 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); | |
908 | *gid_tbl_len = field; | |
909 | ||
910 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); | |
911 | *pkey_tbl_len = field; | |
912 | ||
913 | out: | |
914 | mlx4_free_cmd_mailbox(dev, mailbox); | |
915 | return err; | |
916 | } | |
917 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); | |
918 | ||
225c7b1f RD |
919 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
920 | { | |
921 | struct mlx4_cmd_mailbox *mailbox; | |
922 | struct mlx4_icm_iter iter; | |
923 | __be64 *pages; | |
924 | int lg; | |
925 | int nent = 0; | |
926 | int i; | |
927 | int err = 0; | |
928 | int ts = 0, tc = 0; | |
929 | ||
930 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
931 | if (IS_ERR(mailbox)) | |
932 | return PTR_ERR(mailbox); | |
933 | memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); | |
934 | pages = mailbox->buf; | |
935 | ||
936 | for (mlx4_icm_first(icm, &iter); | |
937 | !mlx4_icm_last(&iter); | |
938 | mlx4_icm_next(&iter)) { | |
939 | /* | |
940 | * We have to pass pages that are aligned to their | |
941 | * size, so find the least significant 1 in the | |
942 | * address or size and use that as our log2 size. | |
943 | */ | |
944 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; | |
945 | if (lg < MLX4_ICM_PAGE_SHIFT) { | |
946 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
947 | MLX4_ICM_PAGE_SIZE, | |
948 | (unsigned long long) mlx4_icm_addr(&iter), | |
949 | mlx4_icm_size(&iter)); | |
950 | err = -EINVAL; | |
951 | goto out; | |
952 | } | |
953 | ||
954 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { | |
955 | if (virt != -1) { | |
956 | pages[nent * 2] = cpu_to_be64(virt); | |
957 | virt += 1 << lg; | |
958 | } | |
959 | ||
960 | pages[nent * 2 + 1] = | |
961 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | | |
962 | (lg - MLX4_ICM_PAGE_SHIFT)); | |
963 | ts += 1 << (lg - 10); | |
964 | ++tc; | |
965 | ||
966 | if (++nent == MLX4_MAILBOX_SIZE / 16) { | |
967 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, | |
f9baff50 JM |
968 | MLX4_CMD_TIME_CLASS_B, |
969 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
970 | if (err) |
971 | goto out; | |
972 | nent = 0; | |
973 | } | |
974 | } | |
975 | } | |
976 | ||
977 | if (nent) | |
f9baff50 JM |
978 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
979 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
980 | if (err) |
981 | goto out; | |
982 | ||
983 | switch (op) { | |
984 | case MLX4_CMD_MAP_FA: | |
985 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
986 | break; | |
987 | case MLX4_CMD_MAP_ICM_AUX: | |
988 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
989 | break; | |
990 | case MLX4_CMD_MAP_ICM: | |
991 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
992 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
993 | break; | |
994 | } | |
995 | ||
996 | out: | |
997 | mlx4_free_cmd_mailbox(dev, mailbox); | |
998 | return err; | |
999 | } | |
1000 | ||
1001 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) | |
1002 | { | |
1003 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); | |
1004 | } | |
1005 | ||
1006 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) | |
1007 | { | |
f9baff50 JM |
1008 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
1009 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
1010 | } |
1011 | ||
1012 | ||
1013 | int mlx4_RUN_FW(struct mlx4_dev *dev) | |
1014 | { | |
f9baff50 JM |
1015 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
1016 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
225c7b1f RD |
1017 | } |
1018 | ||
1019 | int mlx4_QUERY_FW(struct mlx4_dev *dev) | |
1020 | { | |
1021 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; | |
1022 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
1023 | struct mlx4_cmd_mailbox *mailbox; | |
1024 | u32 *outbox; | |
1025 | int err = 0; | |
1026 | u64 fw_ver; | |
fe40900f | 1027 | u16 cmd_if_rev; |
225c7b1f RD |
1028 | u8 lg; |
1029 | ||
1030 | #define QUERY_FW_OUT_SIZE 0x100 | |
1031 | #define QUERY_FW_VER_OFFSET 0x00 | |
5cc914f1 | 1032 | #define QUERY_FW_PPF_ID 0x09 |
fe40900f | 1033 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
225c7b1f RD |
1034 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
1035 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
1036 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
1037 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c | |
1038 | ||
1039 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
1040 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
1041 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 | |
1042 | ||
5cc914f1 MA |
1043 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
1044 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 | |
1045 | ||
ddd8a6c1 EE |
1046 | #define QUERY_FW_CLOCK_OFFSET 0x50 |
1047 | #define QUERY_FW_CLOCK_BAR 0x58 | |
1048 | ||
225c7b1f RD |
1049 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1050 | if (IS_ERR(mailbox)) | |
1051 | return PTR_ERR(mailbox); | |
1052 | outbox = mailbox->buf; | |
1053 | ||
1054 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
f9baff50 | 1055 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1056 | if (err) |
1057 | goto out; | |
1058 | ||
1059 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
1060 | /* | |
3e1db334 | 1061 | * FW subminor version is at more significant bits than minor |
225c7b1f RD |
1062 | * version, so swap here. |
1063 | */ | |
1064 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | | |
1065 | ((fw_ver & 0xffff0000ull) >> 16) | | |
1066 | ((fw_ver & 0x0000ffffull) << 16); | |
1067 | ||
752a50ca JM |
1068 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
1069 | dev->caps.function = lg; | |
1070 | ||
b91cb3eb JM |
1071 | if (mlx4_is_slave(dev)) |
1072 | goto out; | |
1073 | ||
5cc914f1 | 1074 | |
fe40900f | 1075 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
5ae2a7a8 RD |
1076 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
1077 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { | |
fe40900f RD |
1078 | mlx4_err(dev, "Installed FW has unsupported " |
1079 | "command interface revision %d.\n", | |
1080 | cmd_if_rev); | |
1081 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", | |
1082 | (int) (dev->caps.fw_ver >> 32), | |
1083 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
1084 | (int) dev->caps.fw_ver & 0xffff); | |
5ae2a7a8 RD |
1085 | mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", |
1086 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); | |
fe40900f RD |
1087 | err = -ENODEV; |
1088 | goto out; | |
1089 | } | |
1090 | ||
5ae2a7a8 RD |
1091 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
1092 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; | |
1093 | ||
225c7b1f RD |
1094 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
1095 | cmd->max_cmds = 1 << lg; | |
1096 | ||
fe40900f | 1097 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
225c7b1f RD |
1098 | (int) (dev->caps.fw_ver >> 32), |
1099 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
1100 | (int) dev->caps.fw_ver & 0xffff, | |
fe40900f | 1101 | cmd_if_rev, cmd->max_cmds); |
225c7b1f RD |
1102 | |
1103 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); | |
1104 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
1105 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); | |
1106 | fw->catas_bar = (fw->catas_bar >> 6) * 2; | |
1107 | ||
1108 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", | |
1109 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); | |
1110 | ||
1111 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); | |
1112 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
1113 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); | |
1114 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; | |
1115 | ||
5cc914f1 MA |
1116 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
1117 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); | |
1118 | fw->comm_bar = (fw->comm_bar >> 6) * 2; | |
1119 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", | |
1120 | fw->comm_bar, fw->comm_base); | |
225c7b1f RD |
1121 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
1122 | ||
ddd8a6c1 EE |
1123 | MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); |
1124 | MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); | |
1125 | fw->clock_bar = (fw->clock_bar >> 6) * 2; | |
1126 | mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", | |
1127 | fw->clock_bar, fw->clock_offset); | |
1128 | ||
225c7b1f RD |
1129 | /* |
1130 | * Round up number of system pages needed in case | |
1131 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1132 | */ | |
1133 | fw->fw_pages = | |
1134 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1135 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1136 | ||
1137 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", | |
1138 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); | |
1139 | ||
1140 | out: | |
1141 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1142 | return err; | |
1143 | } | |
1144 | ||
b91cb3eb JM |
1145 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
1146 | struct mlx4_vhcr *vhcr, | |
1147 | struct mlx4_cmd_mailbox *inbox, | |
1148 | struct mlx4_cmd_mailbox *outbox, | |
1149 | struct mlx4_cmd_info *cmd) | |
1150 | { | |
1151 | u8 *outbuf; | |
1152 | int err; | |
1153 | ||
1154 | outbuf = outbox->buf; | |
1155 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
1156 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1157 | if (err) | |
1158 | return err; | |
1159 | ||
752a50ca JM |
1160 | /* for slaves, set pci PPF ID to invalid and zero out everything |
1161 | * else except FW version */ | |
b91cb3eb JM |
1162 | outbuf[0] = outbuf[1] = 0; |
1163 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); | |
752a50ca JM |
1164 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
1165 | ||
b91cb3eb JM |
1166 | return 0; |
1167 | } | |
1168 | ||
225c7b1f RD |
1169 | static void get_board_id(void *vsd, char *board_id) |
1170 | { | |
1171 | int i; | |
1172 | ||
1173 | #define VSD_OFFSET_SIG1 0x00 | |
1174 | #define VSD_OFFSET_SIG2 0xde | |
1175 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
1176 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
1177 | ||
1178 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
1179 | ||
1180 | memset(board_id, 0, MLX4_BOARD_ID_LEN); | |
1181 | ||
1182 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
1183 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
1184 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); | |
1185 | } else { | |
1186 | /* | |
1187 | * The board ID is a string but the firmware byte | |
1188 | * swaps each 4-byte word before passing it back to | |
1189 | * us. Therefore we need to swab it before printing. | |
1190 | */ | |
1191 | for (i = 0; i < 4; ++i) | |
1192 | ((u32 *) board_id)[i] = | |
1193 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
1194 | } | |
1195 | } | |
1196 | ||
1197 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) | |
1198 | { | |
1199 | struct mlx4_cmd_mailbox *mailbox; | |
1200 | u32 *outbox; | |
1201 | int err; | |
1202 | ||
1203 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
225c7b1f RD |
1204 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
1205 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 | |
1206 | ||
1207 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1208 | if (IS_ERR(mailbox)) | |
1209 | return PTR_ERR(mailbox); | |
1210 | outbox = mailbox->buf; | |
1211 | ||
1212 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, | |
f9baff50 | 1213 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1214 | if (err) |
1215 | goto out; | |
1216 | ||
225c7b1f RD |
1217 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
1218 | ||
1219 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, | |
1220 | adapter->board_id); | |
1221 | ||
1222 | out: | |
1223 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1224 | return err; | |
1225 | } | |
1226 | ||
1227 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) | |
1228 | { | |
1229 | struct mlx4_cmd_mailbox *mailbox; | |
1230 | __be32 *inbox; | |
1231 | int err; | |
1232 | ||
1233 | #define INIT_HCA_IN_SIZE 0x200 | |
1234 | #define INIT_HCA_VERSION_OFFSET 0x000 | |
1235 | #define INIT_HCA_VERSION 2 | |
c57e20dc | 1236 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
225c7b1f RD |
1237 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
1238 | #define INIT_HCA_QPC_OFFSET 0x020 | |
1239 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
1240 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
1241 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
1242 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
1243 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
1244 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
5cc914f1 | 1245 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
225c7b1f RD |
1246 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
1247 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
1248 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
1249 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
1250 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
1251 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) | |
1252 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
1253 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
1254 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
1255 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1679200f | 1256 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
225c7b1f | 1257 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
0ff1fb65 HHZ |
1258 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
1259 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 | |
1260 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) | |
1261 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) | |
1262 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) | |
1263 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) | |
1264 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) | |
1265 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) | |
1266 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) | |
225c7b1f RD |
1267 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
1268 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
e448834e | 1269 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
225c7b1f RD |
1270 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
1271 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1272 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) | |
1273 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1274 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1275 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1276 | ||
1277 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1278 | if (IS_ERR(mailbox)) | |
1279 | return PTR_ERR(mailbox); | |
1280 | inbox = mailbox->buf; | |
1281 | ||
1282 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1283 | ||
1284 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; | |
1285 | ||
c57e20dc EC |
1286 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
1287 | (ilog2(cache_line_size()) - 4) << 5; | |
1288 | ||
225c7b1f RD |
1289 | #if defined(__LITTLE_ENDIAN) |
1290 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); | |
1291 | #elif defined(__BIG_ENDIAN) | |
1292 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); | |
1293 | #else | |
1294 | #error Host endianness not defined | |
1295 | #endif | |
1296 | /* Check port for UD address vector: */ | |
1297 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); | |
1298 | ||
8ff095ec EC |
1299 | /* Enable IPoIB checksumming if we can: */ |
1300 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) | |
1301 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); | |
1302 | ||
51f5f0ee JM |
1303 | /* Enable QoS support if module parameter set */ |
1304 | if (enable_qos) | |
1305 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); | |
1306 | ||
f2a3f6a3 OG |
1307 | /* enable counters */ |
1308 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) | |
1309 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); | |
1310 | ||
08ff3235 OG |
1311 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
1312 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { | |
1313 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); | |
1314 | dev->caps.eqe_size = 64; | |
1315 | dev->caps.eqe_factor = 1; | |
1316 | } else { | |
1317 | dev->caps.eqe_size = 32; | |
1318 | dev->caps.eqe_factor = 0; | |
1319 | } | |
1320 | ||
1321 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { | |
1322 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); | |
1323 | dev->caps.cqe_size = 64; | |
1324 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; | |
1325 | } else { | |
1326 | dev->caps.cqe_size = 32; | |
1327 | } | |
1328 | ||
225c7b1f RD |
1329 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
1330 | ||
1331 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1332 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1333 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1334 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1335 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1336 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1337 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); | |
1338 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); | |
1339 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1340 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1341 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); | |
1342 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); | |
1343 | ||
0ff1fb65 HHZ |
1344 | /* steering attributes */ |
1345 | if (dev->caps.steering_mode == | |
1346 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1347 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= | |
1348 | cpu_to_be32(1 << | |
1349 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); | |
1350 | ||
1351 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); | |
1352 | MLX4_PUT(inbox, param->log_mc_entry_sz, | |
1353 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); | |
1354 | MLX4_PUT(inbox, param->log_mc_table_sz, | |
1355 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); | |
1356 | /* Enable Ethernet flow steering | |
1357 | * with udp unicast and tcp unicast | |
1358 | */ | |
23537b73 | 1359 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
0ff1fb65 HHZ |
1360 | INIT_HCA_FS_ETH_BITS_OFFSET); |
1361 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, | |
1362 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); | |
1363 | /* Enable IPoIB flow steering | |
1364 | * with udp unicast and tcp unicast | |
1365 | */ | |
23537b73 | 1366 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
0ff1fb65 HHZ |
1367 | INIT_HCA_FS_IB_BITS_OFFSET); |
1368 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, | |
1369 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); | |
1370 | } else { | |
1371 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1372 | MLX4_PUT(inbox, param->log_mc_entry_sz, | |
1373 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1374 | MLX4_PUT(inbox, param->log_mc_hash_sz, | |
1375 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1376 | MLX4_PUT(inbox, param->log_mc_table_sz, | |
1377 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1378 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) | |
1379 | MLX4_PUT(inbox, (u8) (1 << 3), | |
1380 | INIT_HCA_UC_STEERING_OFFSET); | |
1381 | } | |
225c7b1f RD |
1382 | |
1383 | /* TPT attributes */ | |
1384 | ||
1385 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); | |
e448834e | 1386 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
225c7b1f RD |
1387 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
1388 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1389 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); | |
1390 | ||
1391 | /* UAR attributes */ | |
1392 | ||
ab9c17a0 | 1393 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
225c7b1f RD |
1394 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
1395 | ||
f9baff50 JM |
1396 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
1397 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1398 | |
1399 | if (err) | |
1400 | mlx4_err(dev, "INIT_HCA returns %d\n", err); | |
1401 | ||
1402 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1403 | return err; | |
1404 | } | |
1405 | ||
ab9c17a0 JM |
1406 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
1407 | struct mlx4_init_hca_param *param) | |
1408 | { | |
1409 | struct mlx4_cmd_mailbox *mailbox; | |
1410 | __be32 *outbox; | |
7b8157be | 1411 | u32 dword_field; |
ab9c17a0 | 1412 | int err; |
08ff3235 | 1413 | u8 byte_field; |
ab9c17a0 JM |
1414 | |
1415 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 | |
ddd8a6c1 | 1416 | #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c |
ab9c17a0 JM |
1417 | |
1418 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1419 | if (IS_ERR(mailbox)) | |
1420 | return PTR_ERR(mailbox); | |
1421 | outbox = mailbox->buf; | |
1422 | ||
1423 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, | |
1424 | MLX4_CMD_QUERY_HCA, | |
1425 | MLX4_CMD_TIME_CLASS_B, | |
1426 | !mlx4_is_slave(dev)); | |
1427 | if (err) | |
1428 | goto out; | |
1429 | ||
1430 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); | |
ddd8a6c1 | 1431 | MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
ab9c17a0 JM |
1432 | |
1433 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ | |
1434 | ||
1435 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); | |
1436 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); | |
1437 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); | |
1438 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); | |
1439 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); | |
1440 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); | |
1441 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); | |
1442 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); | |
1443 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); | |
1444 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); | |
1445 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); | |
1446 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); | |
1447 | ||
7b8157be JM |
1448 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
1449 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { | |
1450 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; | |
1451 | } else { | |
1452 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); | |
1453 | if (byte_field & 0x8) | |
1454 | param->steering_mode = MLX4_STEERING_MODE_B0; | |
1455 | else | |
1456 | param->steering_mode = MLX4_STEERING_MODE_A0; | |
1457 | } | |
0ff1fb65 | 1458 | /* steering attributes */ |
7b8157be | 1459 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
0ff1fb65 HHZ |
1460 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
1461 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1462 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); | |
1463 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1464 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); | |
1465 | } else { | |
1466 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); | |
1467 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1468 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1469 | MLX4_GET(param->log_mc_hash_sz, outbox, | |
1470 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1471 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1472 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1473 | } | |
ab9c17a0 | 1474 | |
08ff3235 OG |
1475 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
1476 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); | |
1477 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ | |
1478 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; | |
1479 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ | |
1480 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; | |
1481 | ||
ab9c17a0 JM |
1482 | /* TPT attributes */ |
1483 | ||
1484 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); | |
e448834e | 1485 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
ab9c17a0 JM |
1486 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
1487 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); | |
1488 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); | |
1489 | ||
1490 | /* UAR attributes */ | |
1491 | ||
1492 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1493 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1494 | ||
1495 | out: | |
1496 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1497 | ||
1498 | return err; | |
1499 | } | |
1500 | ||
980e9001 JM |
1501 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
1502 | * and real QP0 are active, so that the paravirtualized QP0 is ready | |
1503 | * to operate */ | |
1504 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) | |
1505 | { | |
1506 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1507 | /* irrelevant if not infiniband */ | |
1508 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && | |
1509 | priv->mfunc.master.qp0_state[port].qp0_active) | |
1510 | return 1; | |
1511 | return 0; | |
1512 | } | |
1513 | ||
5cc914f1 MA |
1514 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1515 | struct mlx4_vhcr *vhcr, | |
1516 | struct mlx4_cmd_mailbox *inbox, | |
1517 | struct mlx4_cmd_mailbox *outbox, | |
1518 | struct mlx4_cmd_info *cmd) | |
1519 | { | |
1520 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1521 | int port = vhcr->in_modifier; | |
1522 | int err; | |
1523 | ||
1524 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) | |
1525 | return 0; | |
1526 | ||
980e9001 JM |
1527 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
1528 | /* Enable port only if it was previously disabled */ | |
1529 | if (!priv->mfunc.master.init_port_ref[port]) { | |
1530 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1531 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1532 | if (err) | |
1533 | return err; | |
1534 | } | |
1535 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
1536 | } else { | |
1537 | if (slave == mlx4_master_func_num(dev)) { | |
1538 | if (check_qp0_state(dev, slave, port) && | |
1539 | !priv->mfunc.master.qp0_state[port].port_active) { | |
1540 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1541 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1542 | if (err) | |
1543 | return err; | |
1544 | priv->mfunc.master.qp0_state[port].port_active = 1; | |
1545 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
1546 | } | |
1547 | } else | |
1548 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
5cc914f1 MA |
1549 | } |
1550 | ++priv->mfunc.master.init_port_ref[port]; | |
1551 | return 0; | |
1552 | } | |
1553 | ||
5ae2a7a8 | 1554 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
225c7b1f RD |
1555 | { |
1556 | struct mlx4_cmd_mailbox *mailbox; | |
1557 | u32 *inbox; | |
1558 | int err; | |
1559 | u32 flags; | |
5ae2a7a8 | 1560 | u16 field; |
225c7b1f | 1561 | |
5ae2a7a8 | 1562 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
225c7b1f RD |
1563 | #define INIT_PORT_IN_SIZE 256 |
1564 | #define INIT_PORT_FLAGS_OFFSET 0x00 | |
1565 | #define INIT_PORT_FLAG_SIG (1 << 18) | |
1566 | #define INIT_PORT_FLAG_NG (1 << 17) | |
1567 | #define INIT_PORT_FLAG_G0 (1 << 16) | |
1568 | #define INIT_PORT_VL_SHIFT 4 | |
1569 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 | |
1570 | #define INIT_PORT_MTU_OFFSET 0x04 | |
1571 | #define INIT_PORT_MAX_GID_OFFSET 0x06 | |
1572 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a | |
1573 | #define INIT_PORT_GUID0_OFFSET 0x10 | |
1574 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 | |
1575 | #define INIT_PORT_SI_GUID_OFFSET 0x20 | |
1576 | ||
5ae2a7a8 RD |
1577 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1578 | if (IS_ERR(mailbox)) | |
1579 | return PTR_ERR(mailbox); | |
1580 | inbox = mailbox->buf; | |
225c7b1f | 1581 | |
5ae2a7a8 | 1582 | memset(inbox, 0, INIT_PORT_IN_SIZE); |
225c7b1f | 1583 | |
5ae2a7a8 RD |
1584 | flags = 0; |
1585 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; | |
1586 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; | |
1587 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); | |
225c7b1f | 1588 | |
b79acb49 | 1589 | field = 128 << dev->caps.ib_mtu_cap[port]; |
5ae2a7a8 RD |
1590 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
1591 | field = dev->caps.gid_table_len[port]; | |
1592 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); | |
1593 | field = dev->caps.pkey_table_len[port]; | |
1594 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); | |
225c7b1f | 1595 | |
5ae2a7a8 | 1596 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
f9baff50 | 1597 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f | 1598 | |
5ae2a7a8 RD |
1599 | mlx4_free_cmd_mailbox(dev, mailbox); |
1600 | } else | |
1601 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
f9baff50 | 1602 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
225c7b1f RD |
1603 | |
1604 | return err; | |
1605 | } | |
1606 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); | |
1607 | ||
5cc914f1 MA |
1608 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1609 | struct mlx4_vhcr *vhcr, | |
1610 | struct mlx4_cmd_mailbox *inbox, | |
1611 | struct mlx4_cmd_mailbox *outbox, | |
1612 | struct mlx4_cmd_info *cmd) | |
1613 | { | |
1614 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1615 | int port = vhcr->in_modifier; | |
1616 | int err; | |
1617 | ||
1618 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & | |
1619 | (1 << port))) | |
1620 | return 0; | |
1621 | ||
980e9001 JM |
1622 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
1623 | if (priv->mfunc.master.init_port_ref[port] == 1) { | |
1624 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, | |
1625 | 1000, MLX4_CMD_NATIVE); | |
1626 | if (err) | |
1627 | return err; | |
1628 | } | |
1629 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1630 | } else { | |
1631 | /* infiniband port */ | |
1632 | if (slave == mlx4_master_func_num(dev)) { | |
1633 | if (!priv->mfunc.master.qp0_state[port].qp0_active && | |
1634 | priv->mfunc.master.qp0_state[port].port_active) { | |
1635 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, | |
1636 | 1000, MLX4_CMD_NATIVE); | |
1637 | if (err) | |
1638 | return err; | |
1639 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1640 | priv->mfunc.master.qp0_state[port].port_active = 0; | |
1641 | } | |
1642 | } else | |
1643 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
5cc914f1 | 1644 | } |
5cc914f1 MA |
1645 | --priv->mfunc.master.init_port_ref[port]; |
1646 | return 0; | |
1647 | } | |
1648 | ||
225c7b1f RD |
1649 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
1650 | { | |
f9baff50 JM |
1651 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
1652 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
1653 | } |
1654 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); | |
1655 | ||
1656 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) | |
1657 | { | |
f9baff50 JM |
1658 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
1659 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1660 | } |
1661 | ||
1662 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) | |
1663 | { | |
1664 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, | |
1665 | MLX4_CMD_SET_ICM_SIZE, | |
f9baff50 | 1666 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1667 | if (ret) |
1668 | return ret; | |
1669 | ||
1670 | /* | |
1671 | * Round up number of system pages needed in case | |
1672 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1673 | */ | |
1674 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1675 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1676 | ||
1677 | return 0; | |
1678 | } | |
1679 | ||
1680 | int mlx4_NOP(struct mlx4_dev *dev) | |
1681 | { | |
1682 | /* Input modifier of 0x1f means "finish as soon as possible." */ | |
f9baff50 | 1683 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
225c7b1f | 1684 | } |
14c07b13 YP |
1685 | |
1686 | #define MLX4_WOL_SETUP_MODE (5 << 28) | |
1687 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) | |
1688 | { | |
1689 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1690 | ||
1691 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, | |
f9baff50 JM |
1692 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
1693 | MLX4_CMD_NATIVE); | |
14c07b13 YP |
1694 | } |
1695 | EXPORT_SYMBOL_GPL(mlx4_wol_read); | |
1696 | ||
1697 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) | |
1698 | { | |
1699 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1700 | ||
1701 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 1702 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
14c07b13 YP |
1703 | } |
1704 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |