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{NET, IB}/mlx4: Add device managed flow steering firmware API
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
7ff93f8b 94 [12] = "DPDP",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
225c7b1f
RD		 112 };
113 int i;
114
115 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 116 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 117 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 118 mlx4_dbg(dev, " %s\n", fname[i]);
119}
120
b3416f44
SP		 121static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
122{
123 static const char * const fname[] = {
124 [0] = "RSS support",
125 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65
HHZ		 126 [2] = "RSS XOR Hash Function support",
127 [3] = "Device manage flow steering support"
b3416f44
SP		 128 };
129 int i;
130
131 for (i = 0; i < ARRAY_SIZE(fname); ++i)
132 if (fname[i] && (flags & (1LL << i)))
133 mlx4_dbg(dev, " %s\n", fname[i]);
134}
135
2d928651
VS		 136int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
137{
138 struct mlx4_cmd_mailbox *mailbox;
139 u32 *inbox;
140 int err = 0;
141
142#define MOD_STAT_CFG_IN_SIZE 0x100
143
144#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
145#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
146
147 mailbox = mlx4_alloc_cmd_mailbox(dev);
148 if (IS_ERR(mailbox))
149 return PTR_ERR(mailbox);
150 inbox = mailbox->buf;
151
152 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
153
154 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
155 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
156
157 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 158 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 159
160 mlx4_free_cmd_mailbox(dev, mailbox);
161 return err;
162}
163
5cc914f1
MA		 164int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
165 struct mlx4_vhcr *vhcr,
166 struct mlx4_cmd_mailbox *inbox,
167 struct mlx4_cmd_mailbox *outbox,
168 struct mlx4_cmd_info *cmd)
169{
170 u8 field;
171 u32 size;
172 int err = 0;
173
174#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
175#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1
MA		 176#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
177#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
178#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
179#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
180#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
181#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
182#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
183#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
184#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
185
186#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
187#define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
188
189 if (vhcr->op_modifier == 1) {
190 field = vhcr->in_modifier;
191 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
192
193 field = 0; /* ensure fvl bit is not set */
194 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
195 } else if (vhcr->op_modifier == 0) {
196 field = 1 << 7; /* enable only ethernet interface */
197 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
198
5cc914f1
MA		 199 field = dev->caps.num_ports;
200 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
201
202 size = 0; /* no PF behavious is set for now */
203 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
204
205 size = dev->caps.num_qps;
206 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
207
208 size = dev->caps.num_srqs;
209 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
210
211 size = dev->caps.num_cqs;
212 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
213
214 size = dev->caps.num_eqs;
215 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
216
217 size = dev->caps.reserved_eqs;
218 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
219
220 size = dev->caps.num_mpts;
221 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
222
2b8fb286 223 size = dev->caps.num_mtts;
5cc914f1
MA		 224 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
225
226 size = dev->caps.num_mgms + dev->caps.num_amgms;
227 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
228
229 } else
230 err = -EINVAL;
231
232 return err;
233}
234
235int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
236{
237 struct mlx4_cmd_mailbox *mailbox;
238 u32 *outbox;
239 u8 field;
240 u32 size;
241 int i;
242 int err = 0;
243
244
245 mailbox = mlx4_alloc_cmd_mailbox(dev);
246 if (IS_ERR(mailbox))
247 return PTR_ERR(mailbox);
248
249 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
250 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
251 if (err)
252 goto out;
253
254 outbox = mailbox->buf;
255
256 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
257 if (!(field & (1 << 7))) {
258 mlx4_err(dev, "The host doesn't support eth interface\n");
259 err = -EPROTONOSUPPORT;
260 goto out;
261 }
262
5cc914f1
MA		 263 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
264 func_cap->num_ports = field;
265
266 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
267 func_cap->pf_context_behaviour = size;
268
269 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
270 func_cap->qp_quota = size & 0xFFFFFF;
271
272 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
273 func_cap->srq_quota = size & 0xFFFFFF;
274
275 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
276 func_cap->cq_quota = size & 0xFFFFFF;
277
278 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
279 func_cap->max_eq = size & 0xFFFFFF;
280
281 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
282 func_cap->reserved_eq = size & 0xFFFFFF;
283
284 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
285 func_cap->mpt_quota = size & 0xFFFFFF;
286
287 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
288 func_cap->mtt_quota = size & 0xFFFFFF;
289
290 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
291 func_cap->mcg_quota = size & 0xFFFFFF;
292
293 for (i = 1; i <= func_cap->num_ports; ++i) {
294 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
295 MLX4_CMD_QUERY_FUNC_CAP,
296 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
297 if (err)
298 goto out;
299
300 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
301 if (field & (1 << 7)) {
302 mlx4_err(dev, "VLAN is enforced on this port\n");
303 err = -EPROTONOSUPPORT;
304 goto out;
305 }
306
307 if (field & (1 << 6)) {
308 mlx4_err(dev, "Force mac is enabled on this port\n");
309 err = -EPROTONOSUPPORT;
310 goto out;
311 }
312
313 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
314 func_cap->physical_port[i] = field;
315 }
316
317 /* All other resources are allocated by the master, but we still report
318 * 'num' and 'reserved' capabilities as follows:
319 * - num remains the maximum resource index
320 * - 'num - reserved' is the total available objects of a resource, but
321 * resource indices may be less than 'reserved'
322 * TODO: set per-resource quotas */
323
324out:
325 mlx4_free_cmd_mailbox(dev, mailbox);
326
327 return err;
328}
329
225c7b1f
RD		 330int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
331{
332 struct mlx4_cmd_mailbox *mailbox;
333 u32 *outbox;
334 u8 field;
ccf86321 335 u32 field32, flags, ext_flags;
225c7b1f
RD		 336 u16 size;
337 u16 stat_rate;
338 int err;
5ae2a7a8 339 int i;
225c7b1f
RD		 340
341#define QUERY_DEV_CAP_OUT_SIZE 0x100
342#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
343#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
344#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
345#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
346#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
347#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
348#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
349#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
350#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
351#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
352#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
353#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
354#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
355#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
356#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
357#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
358#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
359#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
360#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
361#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
362#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 363#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 364#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 365#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
366#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
367#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
368#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
369#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 370#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 371#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
372#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
373#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 374#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 375#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
376#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
377#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
378#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
379#define QUERY_DEV_CAP_BF_OFFSET 0x4c
380#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
381#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
382#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
383#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
384#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
385#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
386#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
387#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
388#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
389#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
390#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
391#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 392#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
393#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 394#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
0ff1fb65
HHZ		 395#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
396#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 397#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
398#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
399#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
400#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
401#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
402#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
403#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
404#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
405#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
406#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 407#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 408#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
409#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
410
b3416f44 411 dev_cap->flags2 = 0;
225c7b1f
RD		 412 mailbox = mlx4_alloc_cmd_mailbox(dev);
413 if (IS_ERR(mailbox))
414 return PTR_ERR(mailbox);
415 outbox = mailbox->buf;
416
417 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 418 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 419 if (err)
420 goto out;
421
422 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
423 dev_cap->reserved_qps = 1 << (field & 0xf);
424 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
425 dev_cap->max_qps = 1 << (field & 0x1f);
426 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
427 dev_cap->reserved_srqs = 1 << (field >> 4);
428 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
429 dev_cap->max_srqs = 1 << (field & 0x1f);
430 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
431 dev_cap->max_cq_sz = 1 << field;
432 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
433 dev_cap->reserved_cqs = 1 << (field & 0xf);
434 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
435 dev_cap->max_cqs = 1 << (field & 0x1f);
436 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
437 dev_cap->max_mpts = 1 << (field & 0x3f);
438 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 439 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 440 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 441 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 442 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
443 dev_cap->reserved_mtts = 1 << (field >> 4);
444 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
445 dev_cap->max_mrw_sz = 1 << field;
446 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
447 dev_cap->reserved_mrws = 1 << (field & 0xf);
448 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
449 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
450 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
451 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
452 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
453 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 454 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
455 field &= 0x1f;
456 if (!field)
457 dev_cap->max_gso_sz = 0;
458 else
459 dev_cap->max_gso_sz = 1 << field;
460
b3416f44
SP		 461 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
462 if (field & 0x20)
463 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
464 if (field & 0x10)
465 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
466 field &= 0xf;
467 if (field) {
468 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
469 dev_cap->max_rss_tbl_sz = 1 << field;
470 } else
471 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 472 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
473 dev_cap->max_rdma_global = 1 << (field & 0x3f);
474 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
475 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 476 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 477 dev_cap->num_ports = field & 0xf;
149983af
DB		 478 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
479 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 480 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
481 if (field & 0x80)
482 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
483 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
484 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
485 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 486 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
487 dev_cap->stat_rate_support = stat_rate;
ccf86321 488 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 489 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 490 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 491 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
492 dev_cap->reserved_uars = field >> 4;
493 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
494 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
495 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
496 dev_cap->min_page_sz = 1 << field;
497
498 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
499 if (field & 0x80) {
500 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
501 dev_cap->bf_reg_size = 1 << (field & 0x1f);
502 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 503 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 504 field = 3;
225c7b1f
RD		 505 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
506 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
507 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
508 } else {
509 dev_cap->bf_reg_size = 0;
510 mlx4_dbg(dev, "BlueFlame not available\n");
511 }
512
513 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
514 dev_cap->max_sq_sg = field;
515 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
516 dev_cap->max_sq_desc_sz = size;
517
518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
519 dev_cap->max_qp_per_mcg = 1 << field;
520 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
521 dev_cap->reserved_mgms = field & 0xf;
522 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
523 dev_cap->max_mcgs = 1 << field;
524 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
525 dev_cap->reserved_pds = field >> 4;
526 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
527 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 528 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
529 dev_cap->reserved_xrcds = field >> 4;
530 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
531 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 532
533 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
534 dev_cap->rdmarc_entry_sz = size;
535 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
536 dev_cap->qpc_entry_sz = size;
537 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
538 dev_cap->aux_entry_sz = size;
539 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
540 dev_cap->altc_entry_sz = size;
541 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
542 dev_cap->eqc_entry_sz = size;
543 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
544 dev_cap->cqc_entry_sz = size;
545 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
546 dev_cap->srq_entry_sz = size;
547 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
548 dev_cap->cmpt_entry_sz = size;
549 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
550 dev_cap->mtt_entry_sz = size;
551 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
552 dev_cap->dmpt_entry_sz = size;
553
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
555 dev_cap->max_srq_sz = 1 << field;
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
557 dev_cap->max_qp_sz = 1 << field;
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
559 dev_cap->resize_srq = field & 1;
560 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
561 dev_cap->max_rq_sg = field;
562 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
563 dev_cap->max_rq_desc_sz = size;
564
565 MLX4_GET(dev_cap->bmme_flags, outbox,
566 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
567 MLX4_GET(dev_cap->reserved_lkey, outbox,
568 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
569 MLX4_GET(dev_cap->max_icm_sz, outbox,
570 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 571 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
572 MLX4_GET(dev_cap->max_counters, outbox,
573 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 574
5ae2a7a8
RD		 575 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
576 for (i = 1; i <= dev_cap->num_ports; ++i) {
577 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
578 dev_cap->max_vl[i] = field >> 4;
579 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 580 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 581 dev_cap->max_port_width[i] = field & 0xf;
582 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
583 dev_cap->max_gids[i] = 1 << (field & 0xf);
584 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
585 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
586 }
587 } else {
7ff93f8b 588#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 589#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 590#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 591#define QUERY_PORT_WIDTH_OFFSET 0x06
592#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 593#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 594#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 595#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 596#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
597#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
598#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 599
600 for (i = 1; i <= dev_cap->num_ports; ++i) {
601 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 602 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 603 if (err)
604 goto out;
605
7ff93f8b
YP		 606 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
607 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 608 dev_cap->suggested_type[i] = (field >> 3) & 1;
609 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 610 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 611 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 612 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
613 dev_cap->max_port_width[i] = field & 0xf;
614 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
615 dev_cap->max_gids[i] = 1 << (field >> 4);
616 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
617 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
618 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 619 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
620 dev_cap->log_max_macs[i] = field & 0xf;
621 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 622 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
623 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 624 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
625 dev_cap->trans_type[i] = field32 >> 24;
626 dev_cap->vendor_oui[i] = field32 & 0xffffff;
627 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
628 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 629 }
630 }
631
95d04f07
RD		 632 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
633 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 634
635 /*
636 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
637 * we can't use any EQs whose doorbell falls on that page,
638 * even if the EQ itself isn't reserved.
639 */
640 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
641 dev_cap->reserved_eqs);
642
643 mlx4_dbg(dev, "Max ICM size %lld MB\n",
644 (unsigned long long) dev_cap->max_icm_sz >> 20);
645 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
646 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
647 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
648 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
649 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
650 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
651 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
652 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
653 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
654 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
655 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
656 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
657 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
658 dev_cap->max_pds, dev_cap->reserved_mgms);
659 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
660 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
661 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 662 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 663 dev_cap->max_port_width[1]);
225c7b1f
RD		 664 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
665 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
666 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
667 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 668 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 669 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 670 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 671
672 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 673 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 674
675out:
676 mlx4_free_cmd_mailbox(dev, mailbox);
677 return err;
678}
679
b91cb3eb
JM		 680int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
681 struct mlx4_vhcr *vhcr,
682 struct mlx4_cmd_mailbox *inbox,
683 struct mlx4_cmd_mailbox *outbox,
684 struct mlx4_cmd_info *cmd)
685{
686 int err = 0;
687 u8 field;
688
689 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
690 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
691 if (err)
692 return err;
693
694 /* For guests, report Blueflame disabled */
695 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
696 field &= 0x7f;
697 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
698
699 return 0;
700}
701
5cc914f1
MA		 702int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
703 struct mlx4_vhcr *vhcr,
704 struct mlx4_cmd_mailbox *inbox,
705 struct mlx4_cmd_mailbox *outbox,
706 struct mlx4_cmd_info *cmd)
707{
708 u64 def_mac;
709 u8 port_type;
710 int err;
711
1c015b3b
YP		 712#define MLX4_PORT_SUPPORT_IB (1 << 0)
713#define MLX4_PORT_SUGGEST_TYPE (1 << 3)
714#define MLX4_PORT_DEFAULT_SENSE (1 << 4)
715#define MLX4_VF_PORT_ETH_ONLY_MASK (0xff & ~MLX4_PORT_SUPPORT_IB & \
716 ~MLX4_PORT_SUGGEST_TYPE & \
717 ~MLX4_PORT_DEFAULT_SENSE)
95f56e7a 718
5cc914f1
MA		 719 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
720 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
721 MLX4_CMD_NATIVE);
722
723 if (!err && dev->caps.function != slave) {
724 /* set slave default_mac address */
725 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
726 def_mac += slave << 8;
727 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
728
729 /* get port type - currently only eth is enabled */
730 MLX4_GET(port_type, outbox->buf,
731 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
732
95f56e7a
YP		 733 /* Allow only Eth port, no link sensing allowed */
734 port_type &= MLX4_VF_PORT_ETH_ONLY_MASK;
5cc914f1
MA		 735
736 /* check eth is enabled for this port */
737 if (!(port_type & 2))
738 mlx4_dbg(dev, "QUERY PORT: eth not supported by host");
739
740 MLX4_PUT(outbox->buf, port_type,
741 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
742 }
743
744 return err;
745}
746
225c7b1f
RD		 747int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
748{
749 struct mlx4_cmd_mailbox *mailbox;
750 struct mlx4_icm_iter iter;
751 __be64 *pages;
752 int lg;
753 int nent = 0;
754 int i;
755 int err = 0;
756 int ts = 0, tc = 0;
757
758 mailbox = mlx4_alloc_cmd_mailbox(dev);
759 if (IS_ERR(mailbox))
760 return PTR_ERR(mailbox);
761 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
762 pages = mailbox->buf;
763
764 for (mlx4_icm_first(icm, &iter);
765 !mlx4_icm_last(&iter);
766 mlx4_icm_next(&iter)) {
767 /*
768 * We have to pass pages that are aligned to their
769 * size, so find the least significant 1 in the
770 * address or size and use that as our log2 size.
771 */
772 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
773 if (lg < MLX4_ICM_PAGE_SHIFT) {
774 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
775 MLX4_ICM_PAGE_SIZE,
776 (unsigned long long) mlx4_icm_addr(&iter),
777 mlx4_icm_size(&iter));
778 err = -EINVAL;
779 goto out;
780 }
781
782 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
783 if (virt != -1) {
784 pages[nent * 2] = cpu_to_be64(virt);
785 virt += 1 << lg;
786 }
787
788 pages[nent * 2 + 1] =
789 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
790 (lg - MLX4_ICM_PAGE_SHIFT));
791 ts += 1 << (lg - 10);
792 ++tc;
793
794 if (++nent == MLX4_MAILBOX_SIZE / 16) {
795 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 796 MLX4_CMD_TIME_CLASS_B,
797 MLX4_CMD_NATIVE);
225c7b1f
RD		 798 if (err)
799 goto out;
800 nent = 0;
801 }
802 }
803 }
804
805 if (nent)
f9baff50
JM		 806 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
807 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 808 if (err)
809 goto out;
810
811 switch (op) {
812 case MLX4_CMD_MAP_FA:
813 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
814 break;
815 case MLX4_CMD_MAP_ICM_AUX:
816 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
817 break;
818 case MLX4_CMD_MAP_ICM:
819 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
820 tc, ts, (unsigned long long) virt - (ts << 10));
821 break;
822 }
823
824out:
825 mlx4_free_cmd_mailbox(dev, mailbox);
826 return err;
827}
828
829int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
830{
831 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
832}
833
834int mlx4_UNMAP_FA(struct mlx4_dev *dev)
835{
f9baff50
JM		 836 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
837 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 838}
839
840
841int mlx4_RUN_FW(struct mlx4_dev *dev)
842{
f9baff50
JM		 843 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
844 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 845}
846
847int mlx4_QUERY_FW(struct mlx4_dev *dev)
848{
849 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
850 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
851 struct mlx4_cmd_mailbox *mailbox;
852 u32 *outbox;
853 int err = 0;
854 u64 fw_ver;
fe40900f 855 u16 cmd_if_rev;
225c7b1f
RD		 856 u8 lg;
857
858#define QUERY_FW_OUT_SIZE 0x100
859#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 860#define QUERY_FW_PPF_ID 0x09
fe40900f 861#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 862#define QUERY_FW_MAX_CMD_OFFSET 0x0f
863#define QUERY_FW_ERR_START_OFFSET 0x30
864#define QUERY_FW_ERR_SIZE_OFFSET 0x38
865#define QUERY_FW_ERR_BAR_OFFSET 0x3c
866
867#define QUERY_FW_SIZE_OFFSET 0x00
868#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
869#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
870
5cc914f1
MA		 871#define QUERY_FW_COMM_BASE_OFFSET 0x40
872#define QUERY_FW_COMM_BAR_OFFSET 0x48
873
225c7b1f
RD		 874 mailbox = mlx4_alloc_cmd_mailbox(dev);
875 if (IS_ERR(mailbox))
876 return PTR_ERR(mailbox);
877 outbox = mailbox->buf;
878
879 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 880 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 881 if (err)
882 goto out;
883
884 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
885 /*
3e1db334 886 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 887 * version, so swap here.
888 */
889 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
890 ((fw_ver & 0xffff0000ull) >> 16) |
891 ((fw_ver & 0x0000ffffull) << 16);
892
b91cb3eb
JM		 893 if (mlx4_is_slave(dev))
894 goto out;
895
5cc914f1
MA		 896 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
897 dev->caps.function = lg;
898
fe40900f 899 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 900 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
901 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 902 mlx4_err(dev, "Installed FW has unsupported "
903 "command interface revision %d.\n",
904 cmd_if_rev);
905 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
906 (int) (dev->caps.fw_ver >> 32),
907 (int) (dev->caps.fw_ver >> 16) & 0xffff,
908 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 909 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
910 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 911 err = -ENODEV;
912 goto out;
913 }
914
5ae2a7a8
RD		 915 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
916 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
917
225c7b1f
RD		 918 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
919 cmd->max_cmds = 1 << lg;
920
fe40900f 921 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 922 (int) (dev->caps.fw_ver >> 32),
923 (int) (dev->caps.fw_ver >> 16) & 0xffff,
924 (int) dev->caps.fw_ver & 0xffff,
fe40900f 925 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 926
927 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
928 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
929 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
930 fw->catas_bar = (fw->catas_bar >> 6) * 2;
931
932 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
933 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
934
935 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
936 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
937 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
938 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
939
5cc914f1
MA		 940 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
941 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
942 fw->comm_bar = (fw->comm_bar >> 6) * 2;
943 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
944 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 945 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
946
947 /*
948 * Round up number of system pages needed in case
949 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
950 */
951 fw->fw_pages =
952 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
953 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
954
955 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
956 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
957
958out:
959 mlx4_free_cmd_mailbox(dev, mailbox);
960 return err;
961}
962
b91cb3eb
JM		 963int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
964 struct mlx4_vhcr *vhcr,
965 struct mlx4_cmd_mailbox *inbox,
966 struct mlx4_cmd_mailbox *outbox,
967 struct mlx4_cmd_info *cmd)
968{
969 u8 *outbuf;
970 int err;
971
972 outbuf = outbox->buf;
973 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
974 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
975 if (err)
976 return err;
977
978 /* for slaves, zero out everything except FW version */
979 outbuf[0] = outbuf[1] = 0;
980 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
981 return 0;
982}
983
225c7b1f
RD		 984static void get_board_id(void *vsd, char *board_id)
985{
986 int i;
987
988#define VSD_OFFSET_SIG1 0x00
989#define VSD_OFFSET_SIG2 0xde
990#define VSD_OFFSET_MLX_BOARD_ID 0xd0
991#define VSD_OFFSET_TS_BOARD_ID 0x20
992
993#define VSD_SIGNATURE_TOPSPIN 0x5ad
994
995 memset(board_id, 0, MLX4_BOARD_ID_LEN);
996
997 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
998 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
999 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1000 } else {
1001 /*
1002 * The board ID is a string but the firmware byte
1003 * swaps each 4-byte word before passing it back to
1004 * us. Therefore we need to swab it before printing.
1005 */
1006 for (i = 0; i < 4; ++i)
1007 ((u32 *) board_id)[i] =
1008 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1009 }
1010}
1011
1012int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1013{
1014 struct mlx4_cmd_mailbox *mailbox;
1015 u32 *outbox;
1016 int err;
1017
1018#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1019#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1020#define QUERY_ADAPTER_VSD_OFFSET 0x20
1021
1022 mailbox = mlx4_alloc_cmd_mailbox(dev);
1023 if (IS_ERR(mailbox))
1024 return PTR_ERR(mailbox);
1025 outbox = mailbox->buf;
1026
1027 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1028 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1029 if (err)
1030 goto out;
1031
225c7b1f
RD		 1032 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1033
1034 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1035 adapter->board_id);
1036
1037out:
1038 mlx4_free_cmd_mailbox(dev, mailbox);
1039 return err;
1040}
1041
1042int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1043{
1044 struct mlx4_cmd_mailbox *mailbox;
1045 __be32 *inbox;
1046 int err;
1047
1048#define INIT_HCA_IN_SIZE 0x200
1049#define INIT_HCA_VERSION_OFFSET 0x000
1050#define INIT_HCA_VERSION 2
c57e20dc 1051#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1052#define INIT_HCA_FLAGS_OFFSET 0x014
1053#define INIT_HCA_QPC_OFFSET 0x020
1054#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1055#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1056#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1057#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1058#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1059#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1060#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1061#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1062#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1063#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1064#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1065#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1066#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1067#define INIT_HCA_MCAST_OFFSET 0x0c0
1068#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1069#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1070#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1071#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1072#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1073#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1074#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1075#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1076#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1077#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1078#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1079#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1080#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1081#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1082#define INIT_HCA_TPT_OFFSET 0x0f0
1083#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1084#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1085#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1086#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1087#define INIT_HCA_UAR_OFFSET 0x120
1088#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1089#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1090
1091 mailbox = mlx4_alloc_cmd_mailbox(dev);
1092 if (IS_ERR(mailbox))
1093 return PTR_ERR(mailbox);
1094 inbox = mailbox->buf;
1095
1096 memset(inbox, 0, INIT_HCA_IN_SIZE);
1097
1098 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1099
c57e20dc
EC		 1100 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1101 (ilog2(cache_line_size()) - 4) << 5;
1102
225c7b1f
RD		 1103#if defined(__LITTLE_ENDIAN)
1104 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1105#elif defined(__BIG_ENDIAN)
1106 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1107#else
1108#error Host endianness not defined
1109#endif
1110 /* Check port for UD address vector: */
1111 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1112
8ff095ec
EC		 1113 /* Enable IPoIB checksumming if we can: */
1114 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1115 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1116
51f5f0ee
JM		 1117 /* Enable QoS support if module parameter set */
1118 if (enable_qos)
1119 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1120
f2a3f6a3
OG		 1121 /* enable counters */
1122 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1123 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1124
225c7b1f
RD		 1125 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1126
1127 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1128 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1129 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1130 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1131 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1132 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1133 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1134 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1135 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1136 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1137 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1138 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1139
0ff1fb65
HHZ		 1140 /* steering attributes */
1141 if (dev->caps.steering_mode ==
1142 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1143 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1144 cpu_to_be32(1 <<
1145 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1146
1147 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1148 MLX4_PUT(inbox, param->log_mc_entry_sz,
1149 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1150 MLX4_PUT(inbox, param->log_mc_table_sz,
1151 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1152 /* Enable Ethernet flow steering
1153 * with udp unicast and tcp unicast
1154 */
1155 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1156 INIT_HCA_FS_ETH_BITS_OFFSET);
1157 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1158 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1159 /* Enable IPoIB flow steering
1160 * with udp unicast and tcp unicast
1161 */
1162 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1163 INIT_HCA_FS_IB_BITS_OFFSET);
1164 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1165 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1166 } else {
1167 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1168 MLX4_PUT(inbox, param->log_mc_entry_sz,
1169 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1170 MLX4_PUT(inbox, param->log_mc_hash_sz,
1171 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1172 MLX4_PUT(inbox, param->log_mc_table_sz,
1173 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1174 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1175 MLX4_PUT(inbox, (u8) (1 << 3),
1176 INIT_HCA_UC_STEERING_OFFSET);
1177 }
225c7b1f
RD		 1178
1179 /* TPT attributes */
1180
1181 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1182 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1183 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1184 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1185
1186 /* UAR attributes */
1187
ab9c17a0 1188 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1189 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1190
f9baff50
JM		 1191 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1192 MLX4_CMD_NATIVE);
225c7b1f
RD		 1193
1194 if (err)
1195 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1196
1197 mlx4_free_cmd_mailbox(dev, mailbox);
1198 return err;
1199}
1200
ab9c17a0
JM		 1201int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1202 struct mlx4_init_hca_param *param)
1203{
1204 struct mlx4_cmd_mailbox *mailbox;
1205 __be32 *outbox;
1206 int err;
1207
1208#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1209
1210 mailbox = mlx4_alloc_cmd_mailbox(dev);
1211 if (IS_ERR(mailbox))
1212 return PTR_ERR(mailbox);
1213 outbox = mailbox->buf;
1214
1215 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1216 MLX4_CMD_QUERY_HCA,
1217 MLX4_CMD_TIME_CLASS_B,
1218 !mlx4_is_slave(dev));
1219 if (err)
1220 goto out;
1221
1222 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1223
1224 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1225
1226 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1227 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1228 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1229 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1230 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1231 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1232 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1233 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1234 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1235 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1236 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1237 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1238
0ff1fb65
HHZ		 1239 /* steering attributes */
1240 if (dev->caps.steering_mode ==
1241 MLX4_STEERING_MODE_DEVICE_MANAGED) {
ab9c17a0 1242
0ff1fb65
HHZ		 1243 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1244 MLX4_GET(param->log_mc_entry_sz, outbox,
1245 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1246 MLX4_GET(param->log_mc_table_sz, outbox,
1247 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1248 } else {
1249 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1250 MLX4_GET(param->log_mc_entry_sz, outbox,
1251 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1252 MLX4_GET(param->log_mc_hash_sz, outbox,
1253 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1254 MLX4_GET(param->log_mc_table_sz, outbox,
1255 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1256 }
ab9c17a0
JM		 1257
1258 /* TPT attributes */
1259
1260 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1261 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1262 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1263 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1264
1265 /* UAR attributes */
1266
1267 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1268 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1269
1270out:
1271 mlx4_free_cmd_mailbox(dev, mailbox);
1272
1273 return err;
1274}
1275
5cc914f1
MA		 1276int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1277 struct mlx4_vhcr *vhcr,
1278 struct mlx4_cmd_mailbox *inbox,
1279 struct mlx4_cmd_mailbox *outbox,
1280 struct mlx4_cmd_info *cmd)
1281{
1282 struct mlx4_priv *priv = mlx4_priv(dev);
1283 int port = vhcr->in_modifier;
1284 int err;
1285
1286 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1287 return 0;
1288
1289 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1290 return -ENODEV;
1291
1292 /* Enable port only if it was previously disabled */
1293 if (!priv->mfunc.master.init_port_ref[port]) {
1294 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1295 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1296 if (err)
1297 return err;
5cc914f1 1298 }
8bac9ede 1299 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1300 ++priv->mfunc.master.init_port_ref[port];
1301 return 0;
1302}
1303
5ae2a7a8 1304int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1305{
1306 struct mlx4_cmd_mailbox *mailbox;
1307 u32 *inbox;
1308 int err;
1309 u32 flags;
5ae2a7a8 1310 u16 field;
225c7b1f 1311
5ae2a7a8 1312 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1313#define INIT_PORT_IN_SIZE 256
1314#define INIT_PORT_FLAGS_OFFSET 0x00
1315#define INIT_PORT_FLAG_SIG (1 << 18)
1316#define INIT_PORT_FLAG_NG (1 << 17)
1317#define INIT_PORT_FLAG_G0 (1 << 16)
1318#define INIT_PORT_VL_SHIFT 4
1319#define INIT_PORT_PORT_WIDTH_SHIFT 8
1320#define INIT_PORT_MTU_OFFSET 0x04
1321#define INIT_PORT_MAX_GID_OFFSET 0x06
1322#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1323#define INIT_PORT_GUID0_OFFSET 0x10
1324#define INIT_PORT_NODE_GUID_OFFSET 0x18
1325#define INIT_PORT_SI_GUID_OFFSET 0x20
1326
5ae2a7a8
RD		 1327 mailbox = mlx4_alloc_cmd_mailbox(dev);
1328 if (IS_ERR(mailbox))
1329 return PTR_ERR(mailbox);
1330 inbox = mailbox->buf;
225c7b1f 1331
5ae2a7a8 1332 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 1333
5ae2a7a8
RD		 1334 flags = 0;
1335 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1336 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1337 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1338
b79acb49 1339 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1340 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1341 field = dev->caps.gid_table_len[port];
1342 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1343 field = dev->caps.pkey_table_len[port];
1344 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1345
5ae2a7a8 1346 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1347 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1348
5ae2a7a8
RD		 1349 mlx4_free_cmd_mailbox(dev, mailbox);
1350 } else
1351 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1352 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1353
1354 return err;
1355}
1356EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1357
5cc914f1
MA		 1358int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1359 struct mlx4_vhcr *vhcr,
1360 struct mlx4_cmd_mailbox *inbox,
1361 struct mlx4_cmd_mailbox *outbox,
1362 struct mlx4_cmd_info *cmd)
1363{
1364 struct mlx4_priv *priv = mlx4_priv(dev);
1365 int port = vhcr->in_modifier;
1366 int err;
1367
1368 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1369 (1 << port)))
1370 return 0;
1371
1372 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1373 return -ENODEV;
1374 if (priv->mfunc.master.init_port_ref[port] == 1) {
1375 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1376 MLX4_CMD_NATIVE);
1377 if (err)
1378 return err;
1379 }
1380 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1381 --priv->mfunc.master.init_port_ref[port];
1382 return 0;
1383}
1384
225c7b1f
RD		 1385int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1386{
f9baff50
JM		 1387 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1388 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1389}
1390EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1391
1392int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1393{
f9baff50
JM		 1394 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1395 MLX4_CMD_NATIVE);
225c7b1f
RD		 1396}
1397
1398int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1399{
1400 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1401 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1402 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1403 if (ret)
1404 return ret;
1405
1406 /*
1407 * Round up number of system pages needed in case
1408 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1409 */
1410 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1411 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1412
1413 return 0;
1414}
1415
1416int mlx4_NOP(struct mlx4_dev *dev)
1417{
1418 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1419 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1420}
14c07b13
YP		 1421
1422#define MLX4_WOL_SETUP_MODE (5 << 28)
1423int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1424{
1425 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1426
1427 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1428 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1429 MLX4_CMD_NATIVE);
14c07b13
YP		 1430}
1431EXPORT_SYMBOL_GPL(mlx4_wol_read);
1432
1433int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1434{
1435 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1436
1437 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1438 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1439}
1440EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux kernel - Deliverables
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