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net/mlx4: Address build warnings on set but not used variables
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
7ff93f8b 94 [12] = "DPDP",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
225c7b1f
RD		 112 };
113 int i;
114
115 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 116 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 117 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 118 mlx4_dbg(dev, " %s\n", fname[i]);
119}
120
2d928651
VS		 121int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
122{
123 struct mlx4_cmd_mailbox *mailbox;
124 u32 *inbox;
125 int err = 0;
126
127#define MOD_STAT_CFG_IN_SIZE 0x100
128
129#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
130#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
131
132 mailbox = mlx4_alloc_cmd_mailbox(dev);
133 if (IS_ERR(mailbox))
134 return PTR_ERR(mailbox);
135 inbox = mailbox->buf;
136
137 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
138
139 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
140 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
141
142 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 143 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 144
145 mlx4_free_cmd_mailbox(dev, mailbox);
146 return err;
147}
148
5cc914f1
MA		 149int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
150 struct mlx4_vhcr *vhcr,
151 struct mlx4_cmd_mailbox *inbox,
152 struct mlx4_cmd_mailbox *outbox,
153 struct mlx4_cmd_info *cmd)
154{
155 u8 field;
156 u32 size;
157 int err = 0;
158
159#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
160#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1
MA		 161#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
162#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
163#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
164#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
165#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
166#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
167#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
168#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
169#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
170
171#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
172#define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
173
174 if (vhcr->op_modifier == 1) {
175 field = vhcr->in_modifier;
176 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
177
178 field = 0; /* ensure fvl bit is not set */
179 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
180 } else if (vhcr->op_modifier == 0) {
181 field = 1 << 7; /* enable only ethernet interface */
182 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
183
5cc914f1
MA		 184 field = dev->caps.num_ports;
185 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
186
187 size = 0; /* no PF behavious is set for now */
188 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
189
190 size = dev->caps.num_qps;
191 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
192
193 size = dev->caps.num_srqs;
194 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
195
196 size = dev->caps.num_cqs;
197 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
198
199 size = dev->caps.num_eqs;
200 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
201
202 size = dev->caps.reserved_eqs;
203 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
204
205 size = dev->caps.num_mpts;
206 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
207
2b8fb286 208 size = dev->caps.num_mtts;
5cc914f1
MA		 209 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
210
211 size = dev->caps.num_mgms + dev->caps.num_amgms;
212 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
213
214 } else
215 err = -EINVAL;
216
217 return err;
218}
219
220int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
221{
222 struct mlx4_cmd_mailbox *mailbox;
223 u32 *outbox;
224 u8 field;
225 u32 size;
226 int i;
227 int err = 0;
228
229
230 mailbox = mlx4_alloc_cmd_mailbox(dev);
231 if (IS_ERR(mailbox))
232 return PTR_ERR(mailbox);
233
234 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
235 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
236 if (err)
237 goto out;
238
239 outbox = mailbox->buf;
240
241 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
242 if (!(field & (1 << 7))) {
243 mlx4_err(dev, "The host doesn't support eth interface\n");
244 err = -EPROTONOSUPPORT;
245 goto out;
246 }
247
5cc914f1
MA		 248 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
249 func_cap->num_ports = field;
250
251 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
252 func_cap->pf_context_behaviour = size;
253
254 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
255 func_cap->qp_quota = size & 0xFFFFFF;
256
257 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
258 func_cap->srq_quota = size & 0xFFFFFF;
259
260 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
261 func_cap->cq_quota = size & 0xFFFFFF;
262
263 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
264 func_cap->max_eq = size & 0xFFFFFF;
265
266 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
267 func_cap->reserved_eq = size & 0xFFFFFF;
268
269 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
270 func_cap->mpt_quota = size & 0xFFFFFF;
271
272 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
273 func_cap->mtt_quota = size & 0xFFFFFF;
274
275 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
276 func_cap->mcg_quota = size & 0xFFFFFF;
277
278 for (i = 1; i <= func_cap->num_ports; ++i) {
279 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
280 MLX4_CMD_QUERY_FUNC_CAP,
281 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
282 if (err)
283 goto out;
284
285 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
286 if (field & (1 << 7)) {
287 mlx4_err(dev, "VLAN is enforced on this port\n");
288 err = -EPROTONOSUPPORT;
289 goto out;
290 }
291
292 if (field & (1 << 6)) {
293 mlx4_err(dev, "Force mac is enabled on this port\n");
294 err = -EPROTONOSUPPORT;
295 goto out;
296 }
297
298 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
299 func_cap->physical_port[i] = field;
300 }
301
302 /* All other resources are allocated by the master, but we still report
303 * 'num' and 'reserved' capabilities as follows:
304 * - num remains the maximum resource index
305 * - 'num - reserved' is the total available objects of a resource, but
306 * resource indices may be less than 'reserved'
307 * TODO: set per-resource quotas */
308
309out:
310 mlx4_free_cmd_mailbox(dev, mailbox);
311
312 return err;
313}
314
225c7b1f
RD		 315int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
316{
317 struct mlx4_cmd_mailbox *mailbox;
318 u32 *outbox;
319 u8 field;
ccf86321 320 u32 field32, flags, ext_flags;
225c7b1f
RD		 321 u16 size;
322 u16 stat_rate;
323 int err;
5ae2a7a8 324 int i;
225c7b1f
RD		 325
326#define QUERY_DEV_CAP_OUT_SIZE 0x100
327#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
328#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
329#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
330#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
331#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
332#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
333#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
334#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
335#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
336#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
337#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
338#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
339#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
340#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
341#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
342#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
343#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
344#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
345#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
346#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
347#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 348#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
225c7b1f
RD		 349#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
350#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
351#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
352#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
353#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 354#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 355#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
356#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
357#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 358#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 359#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
360#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
361#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
362#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
363#define QUERY_DEV_CAP_BF_OFFSET 0x4c
364#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
365#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
366#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
367#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
368#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
369#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
370#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
371#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
372#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
373#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
374#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
375#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 376#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
377#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 378#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
225c7b1f
RD		 379#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
380#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
381#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
382#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
383#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
384#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
385#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
386#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
387#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
388#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 389#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 390#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
391#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
392
393 mailbox = mlx4_alloc_cmd_mailbox(dev);
394 if (IS_ERR(mailbox))
395 return PTR_ERR(mailbox);
396 outbox = mailbox->buf;
397
398 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
f9baff50 399 MLX4_CMD_TIME_CLASS_A, !mlx4_is_slave(dev));
225c7b1f
RD		 400 if (err)
401 goto out;
402
403 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
404 dev_cap->reserved_qps = 1 << (field & 0xf);
405 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
406 dev_cap->max_qps = 1 << (field & 0x1f);
407 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
408 dev_cap->reserved_srqs = 1 << (field >> 4);
409 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
410 dev_cap->max_srqs = 1 << (field & 0x1f);
411 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
412 dev_cap->max_cq_sz = 1 << field;
413 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
414 dev_cap->reserved_cqs = 1 << (field & 0xf);
415 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
416 dev_cap->max_cqs = 1 << (field & 0x1f);
417 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
418 dev_cap->max_mpts = 1 << (field & 0x3f);
419 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 420 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 421 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 422 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 423 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
424 dev_cap->reserved_mtts = 1 << (field >> 4);
425 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
426 dev_cap->max_mrw_sz = 1 << field;
427 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
428 dev_cap->reserved_mrws = 1 << (field & 0xf);
429 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
430 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
431 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
432 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
433 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
434 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 435 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
436 field &= 0x1f;
437 if (!field)
438 dev_cap->max_gso_sz = 0;
439 else
440 dev_cap->max_gso_sz = 1 << field;
441
225c7b1f
RD		 442 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
443 dev_cap->max_rdma_global = 1 << (field & 0x3f);
444 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
445 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 446 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 447 dev_cap->num_ports = field & 0xf;
149983af
DB		 448 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
449 dev_cap->max_msg_sz = 1 << (field & 0x1f);
225c7b1f
RD		 450 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
451 dev_cap->stat_rate_support = stat_rate;
ccf86321 452 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 453 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 454 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 455 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
456 dev_cap->reserved_uars = field >> 4;
457 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
458 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
459 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
460 dev_cap->min_page_sz = 1 << field;
461
462 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
463 if (field & 0x80) {
464 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
465 dev_cap->bf_reg_size = 1 << (field & 0x1f);
466 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 467 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 468 field = 3;
225c7b1f
RD		 469 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
470 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
471 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
472 } else {
473 dev_cap->bf_reg_size = 0;
474 mlx4_dbg(dev, "BlueFlame not available\n");
475 }
476
477 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
478 dev_cap->max_sq_sg = field;
479 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
480 dev_cap->max_sq_desc_sz = size;
481
482 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
483 dev_cap->max_qp_per_mcg = 1 << field;
484 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
485 dev_cap->reserved_mgms = field & 0xf;
486 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
487 dev_cap->max_mcgs = 1 << field;
488 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
489 dev_cap->reserved_pds = field >> 4;
490 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
491 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 492 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
493 dev_cap->reserved_xrcds = field >> 4;
494 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
495 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 496
497 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
498 dev_cap->rdmarc_entry_sz = size;
499 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
500 dev_cap->qpc_entry_sz = size;
501 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
502 dev_cap->aux_entry_sz = size;
503 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
504 dev_cap->altc_entry_sz = size;
505 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
506 dev_cap->eqc_entry_sz = size;
507 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
508 dev_cap->cqc_entry_sz = size;
509 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
510 dev_cap->srq_entry_sz = size;
511 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
512 dev_cap->cmpt_entry_sz = size;
513 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
514 dev_cap->mtt_entry_sz = size;
515 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
516 dev_cap->dmpt_entry_sz = size;
517
518 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
519 dev_cap->max_srq_sz = 1 << field;
520 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
521 dev_cap->max_qp_sz = 1 << field;
522 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
523 dev_cap->resize_srq = field & 1;
524 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
525 dev_cap->max_rq_sg = field;
526 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
527 dev_cap->max_rq_desc_sz = size;
528
529 MLX4_GET(dev_cap->bmme_flags, outbox,
530 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
531 MLX4_GET(dev_cap->reserved_lkey, outbox,
532 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
533 MLX4_GET(dev_cap->max_icm_sz, outbox,
534 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 535 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
536 MLX4_GET(dev_cap->max_counters, outbox,
537 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 538
5ae2a7a8
RD		 539 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
540 for (i = 1; i <= dev_cap->num_ports; ++i) {
541 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
542 dev_cap->max_vl[i] = field >> 4;
543 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 544 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 545 dev_cap->max_port_width[i] = field & 0xf;
546 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
547 dev_cap->max_gids[i] = 1 << (field & 0xf);
548 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
549 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
550 }
551 } else {
7ff93f8b 552#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 553#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 554#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 555#define QUERY_PORT_WIDTH_OFFSET 0x06
556#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 557#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 558#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 559#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 560#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
561#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
562#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 563
564 for (i = 1; i <= dev_cap->num_ports; ++i) {
565 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
f9baff50
JM		 566 MLX4_CMD_TIME_CLASS_B,
567 !mlx4_is_slave(dev));
5ae2a7a8
RD		 568 if (err)
569 goto out;
570
7ff93f8b
YP		 571 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
572 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 573 dev_cap->suggested_type[i] = (field >> 3) & 1;
574 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 575 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 576 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 577 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
578 dev_cap->max_port_width[i] = field & 0xf;
579 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
580 dev_cap->max_gids[i] = 1 << (field >> 4);
581 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
582 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
583 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 584 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
585 dev_cap->log_max_macs[i] = field & 0xf;
586 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 587 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
588 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 589 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
590 dev_cap->trans_type[i] = field32 >> 24;
591 dev_cap->vendor_oui[i] = field32 & 0xffffff;
592 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
593 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 594 }
595 }
596
95d04f07
RD		 597 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
598 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 599
600 /*
601 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
602 * we can't use any EQs whose doorbell falls on that page,
603 * even if the EQ itself isn't reserved.
604 */
605 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
606 dev_cap->reserved_eqs);
607
608 mlx4_dbg(dev, "Max ICM size %lld MB\n",
609 (unsigned long long) dev_cap->max_icm_sz >> 20);
610 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
611 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
612 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
613 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
614 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
615 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
616 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
617 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
618 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
619 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
620 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
621 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
622 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
623 dev_cap->max_pds, dev_cap->reserved_mgms);
624 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
625 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
626 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 627 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 628 dev_cap->max_port_width[1]);
225c7b1f
RD		 629 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
630 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
631 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
632 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 633 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 634 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
225c7b1f
RD		 635
636 dump_dev_cap_flags(dev, dev_cap->flags);
637
638out:
639 mlx4_free_cmd_mailbox(dev, mailbox);
640 return err;
641}
642
5cc914f1
MA		 643int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
644 struct mlx4_vhcr *vhcr,
645 struct mlx4_cmd_mailbox *inbox,
646 struct mlx4_cmd_mailbox *outbox,
647 struct mlx4_cmd_info *cmd)
648{
649 u64 def_mac;
650 u8 port_type;
651 int err;
652
1c015b3b
YP		 653#define MLX4_PORT_SUPPORT_IB (1 << 0)
654#define MLX4_PORT_SUGGEST_TYPE (1 << 3)
655#define MLX4_PORT_DEFAULT_SENSE (1 << 4)
656#define MLX4_VF_PORT_ETH_ONLY_MASK (0xff & ~MLX4_PORT_SUPPORT_IB & \
657 ~MLX4_PORT_SUGGEST_TYPE & \
658 ~MLX4_PORT_DEFAULT_SENSE)
95f56e7a 659
5cc914f1
MA		 660 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
661 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
662 MLX4_CMD_NATIVE);
663
664 if (!err && dev->caps.function != slave) {
665 /* set slave default_mac address */
666 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
667 def_mac += slave << 8;
668 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
669
670 /* get port type - currently only eth is enabled */
671 MLX4_GET(port_type, outbox->buf,
672 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
673
95f56e7a
YP		 674 /* Allow only Eth port, no link sensing allowed */
675 port_type &= MLX4_VF_PORT_ETH_ONLY_MASK;
5cc914f1
MA		 676
677 /* check eth is enabled for this port */
678 if (!(port_type & 2))
679 mlx4_dbg(dev, "QUERY PORT: eth not supported by host");
680
681 MLX4_PUT(outbox->buf, port_type,
682 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
683 }
684
685 return err;
686}
687
225c7b1f
RD		 688int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
689{
690 struct mlx4_cmd_mailbox *mailbox;
691 struct mlx4_icm_iter iter;
692 __be64 *pages;
693 int lg;
694 int nent = 0;
695 int i;
696 int err = 0;
697 int ts = 0, tc = 0;
698
699 mailbox = mlx4_alloc_cmd_mailbox(dev);
700 if (IS_ERR(mailbox))
701 return PTR_ERR(mailbox);
702 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
703 pages = mailbox->buf;
704
705 for (mlx4_icm_first(icm, &iter);
706 !mlx4_icm_last(&iter);
707 mlx4_icm_next(&iter)) {
708 /*
709 * We have to pass pages that are aligned to their
710 * size, so find the least significant 1 in the
711 * address or size and use that as our log2 size.
712 */
713 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
714 if (lg < MLX4_ICM_PAGE_SHIFT) {
715 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
716 MLX4_ICM_PAGE_SIZE,
717 (unsigned long long) mlx4_icm_addr(&iter),
718 mlx4_icm_size(&iter));
719 err = -EINVAL;
720 goto out;
721 }
722
723 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
724 if (virt != -1) {
725 pages[nent * 2] = cpu_to_be64(virt);
726 virt += 1 << lg;
727 }
728
729 pages[nent * 2 + 1] =
730 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
731 (lg - MLX4_ICM_PAGE_SHIFT));
732 ts += 1 << (lg - 10);
733 ++tc;
734
735 if (++nent == MLX4_MAILBOX_SIZE / 16) {
736 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 737 MLX4_CMD_TIME_CLASS_B,
738 MLX4_CMD_NATIVE);
225c7b1f
RD		 739 if (err)
740 goto out;
741 nent = 0;
742 }
743 }
744 }
745
746 if (nent)
f9baff50
JM		 747 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
748 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 749 if (err)
750 goto out;
751
752 switch (op) {
753 case MLX4_CMD_MAP_FA:
754 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
755 break;
756 case MLX4_CMD_MAP_ICM_AUX:
757 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
758 break;
759 case MLX4_CMD_MAP_ICM:
760 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
761 tc, ts, (unsigned long long) virt - (ts << 10));
762 break;
763 }
764
765out:
766 mlx4_free_cmd_mailbox(dev, mailbox);
767 return err;
768}
769
770int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
771{
772 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
773}
774
775int mlx4_UNMAP_FA(struct mlx4_dev *dev)
776{
f9baff50
JM		 777 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
778 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 779}
780
781
782int mlx4_RUN_FW(struct mlx4_dev *dev)
783{
f9baff50
JM		 784 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
785 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 786}
787
788int mlx4_QUERY_FW(struct mlx4_dev *dev)
789{
790 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
791 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
792 struct mlx4_cmd_mailbox *mailbox;
793 u32 *outbox;
794 int err = 0;
795 u64 fw_ver;
fe40900f 796 u16 cmd_if_rev;
225c7b1f
RD		 797 u8 lg;
798
799#define QUERY_FW_OUT_SIZE 0x100
800#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 801#define QUERY_FW_PPF_ID 0x09
fe40900f 802#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 803#define QUERY_FW_MAX_CMD_OFFSET 0x0f
804#define QUERY_FW_ERR_START_OFFSET 0x30
805#define QUERY_FW_ERR_SIZE_OFFSET 0x38
806#define QUERY_FW_ERR_BAR_OFFSET 0x3c
807
808#define QUERY_FW_SIZE_OFFSET 0x00
809#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
810#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
811
5cc914f1
MA		 812#define QUERY_FW_COMM_BASE_OFFSET 0x40
813#define QUERY_FW_COMM_BAR_OFFSET 0x48
814
225c7b1f
RD		 815 mailbox = mlx4_alloc_cmd_mailbox(dev);
816 if (IS_ERR(mailbox))
817 return PTR_ERR(mailbox);
818 outbox = mailbox->buf;
819
820 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 821 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 822 if (err)
823 goto out;
824
825 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
826 /*
3e1db334 827 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 828 * version, so swap here.
829 */
830 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
831 ((fw_ver & 0xffff0000ull) >> 16) |
832 ((fw_ver & 0x0000ffffull) << 16);
833
5cc914f1
MA		 834 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
835 dev->caps.function = lg;
836
fe40900f 837 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 838 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
839 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 840 mlx4_err(dev, "Installed FW has unsupported "
841 "command interface revision %d.\n",
842 cmd_if_rev);
843 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
844 (int) (dev->caps.fw_ver >> 32),
845 (int) (dev->caps.fw_ver >> 16) & 0xffff,
846 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 847 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
848 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 849 err = -ENODEV;
850 goto out;
851 }
852
5ae2a7a8
RD		 853 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
854 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
855
225c7b1f
RD		 856 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
857 cmd->max_cmds = 1 << lg;
858
fe40900f 859 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 860 (int) (dev->caps.fw_ver >> 32),
861 (int) (dev->caps.fw_ver >> 16) & 0xffff,
862 (int) dev->caps.fw_ver & 0xffff,
fe40900f 863 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 864
865 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
866 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
867 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
868 fw->catas_bar = (fw->catas_bar >> 6) * 2;
869
870 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
871 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
872
873 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
874 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
875 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
876 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
877
5cc914f1
MA		 878 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
879 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
880 fw->comm_bar = (fw->comm_bar >> 6) * 2;
881 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
882 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 883 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
884
885 /*
886 * Round up number of system pages needed in case
887 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
888 */
889 fw->fw_pages =
890 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
891 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
892
893 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
894 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
895
896out:
897 mlx4_free_cmd_mailbox(dev, mailbox);
898 return err;
899}
900
901static void get_board_id(void *vsd, char *board_id)
902{
903 int i;
904
905#define VSD_OFFSET_SIG1 0x00
906#define VSD_OFFSET_SIG2 0xde
907#define VSD_OFFSET_MLX_BOARD_ID 0xd0
908#define VSD_OFFSET_TS_BOARD_ID 0x20
909
910#define VSD_SIGNATURE_TOPSPIN 0x5ad
911
912 memset(board_id, 0, MLX4_BOARD_ID_LEN);
913
914 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
915 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
916 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
917 } else {
918 /*
919 * The board ID is a string but the firmware byte
920 * swaps each 4-byte word before passing it back to
921 * us. Therefore we need to swab it before printing.
922 */
923 for (i = 0; i < 4; ++i)
924 ((u32 *) board_id)[i] =
925 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
926 }
927}
928
929int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
930{
931 struct mlx4_cmd_mailbox *mailbox;
932 u32 *outbox;
933 int err;
934
935#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 936#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
937#define QUERY_ADAPTER_VSD_OFFSET 0x20
938
939 mailbox = mlx4_alloc_cmd_mailbox(dev);
940 if (IS_ERR(mailbox))
941 return PTR_ERR(mailbox);
942 outbox = mailbox->buf;
943
944 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 945 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 946 if (err)
947 goto out;
948
225c7b1f
RD		 949 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
950
951 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
952 adapter->board_id);
953
954out:
955 mlx4_free_cmd_mailbox(dev, mailbox);
956 return err;
957}
958
959int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
960{
961 struct mlx4_cmd_mailbox *mailbox;
962 __be32 *inbox;
963 int err;
964
965#define INIT_HCA_IN_SIZE 0x200
966#define INIT_HCA_VERSION_OFFSET 0x000
967#define INIT_HCA_VERSION 2
c57e20dc 968#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 969#define INIT_HCA_FLAGS_OFFSET 0x014
970#define INIT_HCA_QPC_OFFSET 0x020
971#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
972#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
973#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
974#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
975#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
976#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 977#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 978#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
979#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
980#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
981#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
982#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
983#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
984#define INIT_HCA_MCAST_OFFSET 0x0c0
985#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
986#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
987#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 988#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f
RD		 989#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
990#define INIT_HCA_TPT_OFFSET 0x0f0
991#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
992#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
993#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
994#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
995#define INIT_HCA_UAR_OFFSET 0x120
996#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
997#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
998
999 mailbox = mlx4_alloc_cmd_mailbox(dev);
1000 if (IS_ERR(mailbox))
1001 return PTR_ERR(mailbox);
1002 inbox = mailbox->buf;
1003
1004 memset(inbox, 0, INIT_HCA_IN_SIZE);
1005
1006 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1007
c57e20dc
EC		 1008 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1009 (ilog2(cache_line_size()) - 4) << 5;
1010
225c7b1f
RD		 1011#if defined(__LITTLE_ENDIAN)
1012 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1013#elif defined(__BIG_ENDIAN)
1014 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1015#else
1016#error Host endianness not defined
1017#endif
1018 /* Check port for UD address vector: */
1019 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1020
8ff095ec
EC		 1021 /* Enable IPoIB checksumming if we can: */
1022 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1023 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1024
51f5f0ee
JM		 1025 /* Enable QoS support if module parameter set */
1026 if (enable_qos)
1027 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1028
f2a3f6a3
OG		 1029 /* enable counters */
1030 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1031 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1032
225c7b1f
RD		 1033 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1034
1035 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1036 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1037 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1038 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1039 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1040 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1041 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1042 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1043 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1044 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1045 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1046 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1047
1048 /* multicast attributes */
1049
1050 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1051 MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1052 MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
ccf86321 1053 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
1679200f 1054 MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET);
225c7b1f
RD		 1055 MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1056
1057 /* TPT attributes */
1058
1059 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1060 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1061 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1062 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1063
1064 /* UAR attributes */
1065
ab9c17a0 1066 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1067 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1068
f9baff50
JM		 1069 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1070 MLX4_CMD_NATIVE);
225c7b1f
RD		 1071
1072 if (err)
1073 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1074
1075 mlx4_free_cmd_mailbox(dev, mailbox);
1076 return err;
1077}
1078
ab9c17a0
JM		 1079int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1080 struct mlx4_init_hca_param *param)
1081{
1082 struct mlx4_cmd_mailbox *mailbox;
1083 __be32 *outbox;
1084 int err;
1085
1086#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1087
1088 mailbox = mlx4_alloc_cmd_mailbox(dev);
1089 if (IS_ERR(mailbox))
1090 return PTR_ERR(mailbox);
1091 outbox = mailbox->buf;
1092
1093 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1094 MLX4_CMD_QUERY_HCA,
1095 MLX4_CMD_TIME_CLASS_B,
1096 !mlx4_is_slave(dev));
1097 if (err)
1098 goto out;
1099
1100 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1101
1102 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1103
1104 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1105 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1106 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1107 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1108 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1109 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1110 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1111 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1112 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1113 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1114 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1115 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1116
1117 /* multicast attributes */
1118
1119 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1120 MLX4_GET(param->log_mc_entry_sz, outbox,
1121 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1122 MLX4_GET(param->log_mc_hash_sz, outbox,
1123 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1124 MLX4_GET(param->log_mc_table_sz, outbox,
1125 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1126
1127 /* TPT attributes */
1128
1129 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1130 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1131 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1132 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1133
1134 /* UAR attributes */
1135
1136 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1137 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1138
1139out:
1140 mlx4_free_cmd_mailbox(dev, mailbox);
1141
1142 return err;
1143}
1144
5cc914f1
MA		 1145int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1146 struct mlx4_vhcr *vhcr,
1147 struct mlx4_cmd_mailbox *inbox,
1148 struct mlx4_cmd_mailbox *outbox,
1149 struct mlx4_cmd_info *cmd)
1150{
1151 struct mlx4_priv *priv = mlx4_priv(dev);
1152 int port = vhcr->in_modifier;
1153 int err;
1154
1155 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1156 return 0;
1157
1158 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1159 return -ENODEV;
1160
1161 /* Enable port only if it was previously disabled */
1162 if (!priv->mfunc.master.init_port_ref[port]) {
1163 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1164 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1165 if (err)
1166 return err;
1167 priv->mfunc.master.slave_state[slave].init_port_mask |=
1168 (1 << port);
1169 }
1170 ++priv->mfunc.master.init_port_ref[port];
1171 return 0;
1172}
1173
5ae2a7a8 1174int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1175{
1176 struct mlx4_cmd_mailbox *mailbox;
1177 u32 *inbox;
1178 int err;
1179 u32 flags;
5ae2a7a8 1180 u16 field;
225c7b1f 1181
5ae2a7a8 1182 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1183#define INIT_PORT_IN_SIZE 256
1184#define INIT_PORT_FLAGS_OFFSET 0x00
1185#define INIT_PORT_FLAG_SIG (1 << 18)
1186#define INIT_PORT_FLAG_NG (1 << 17)
1187#define INIT_PORT_FLAG_G0 (1 << 16)
1188#define INIT_PORT_VL_SHIFT 4
1189#define INIT_PORT_PORT_WIDTH_SHIFT 8
1190#define INIT_PORT_MTU_OFFSET 0x04
1191#define INIT_PORT_MAX_GID_OFFSET 0x06
1192#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1193#define INIT_PORT_GUID0_OFFSET 0x10
1194#define INIT_PORT_NODE_GUID_OFFSET 0x18
1195#define INIT_PORT_SI_GUID_OFFSET 0x20
1196
5ae2a7a8
RD		 1197 mailbox = mlx4_alloc_cmd_mailbox(dev);
1198 if (IS_ERR(mailbox))
1199 return PTR_ERR(mailbox);
1200 inbox = mailbox->buf;
225c7b1f 1201
5ae2a7a8 1202 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 1203
5ae2a7a8
RD		 1204 flags = 0;
1205 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1206 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1207 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1208
b79acb49 1209 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1210 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1211 field = dev->caps.gid_table_len[port];
1212 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1213 field = dev->caps.pkey_table_len[port];
1214 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1215
5ae2a7a8 1216 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1217 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1218
5ae2a7a8
RD		 1219 mlx4_free_cmd_mailbox(dev, mailbox);
1220 } else
1221 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1222 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1223
1224 return err;
1225}
1226EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1227
5cc914f1
MA		 1228int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1229 struct mlx4_vhcr *vhcr,
1230 struct mlx4_cmd_mailbox *inbox,
1231 struct mlx4_cmd_mailbox *outbox,
1232 struct mlx4_cmd_info *cmd)
1233{
1234 struct mlx4_priv *priv = mlx4_priv(dev);
1235 int port = vhcr->in_modifier;
1236 int err;
1237
1238 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1239 (1 << port)))
1240 return 0;
1241
1242 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1243 return -ENODEV;
1244 if (priv->mfunc.master.init_port_ref[port] == 1) {
1245 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1246 MLX4_CMD_NATIVE);
1247 if (err)
1248 return err;
1249 }
1250 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1251 --priv->mfunc.master.init_port_ref[port];
1252 return 0;
1253}
1254
225c7b1f
RD		 1255int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1256{
f9baff50
JM		 1257 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1258 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1259}
1260EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1261
1262int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1263{
f9baff50
JM		 1264 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1265 MLX4_CMD_NATIVE);
225c7b1f
RD		 1266}
1267
1268int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1269{
1270 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1271 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1272 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1273 if (ret)
1274 return ret;
1275
1276 /*
1277 * Round up number of system pages needed in case
1278 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1279 */
1280 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1281 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1282
1283 return 0;
1284}
1285
1286int mlx4_NOP(struct mlx4_dev *dev)
1287{
1288 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1289 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1290}
14c07b13
YP		 1291
1292#define MLX4_WOL_SETUP_MODE (5 << 28)
1293int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1294{
1295 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1296
1297 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1298 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1299 MLX4_CMD_NATIVE);
14c07b13
YP		 1300}
1301EXPORT_SYMBOL_GPL(mlx4_wol_read);
1302
1303int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1304{
1305 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1306
1307 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1308 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1309}
1310EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux kernel - Deliverables
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