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mellanox: Logging message cleanups
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567
OG		 138 [9] = "Device managed flow steering IPoIB support",
139 [10] = "TCP/IP offloads/flow-steering for VXLAN support"
b3416f44
SP		 140 };
141 int i;
142
143 for (i = 0; i < ARRAY_SIZE(fname); ++i)
144 if (fname[i] && (flags & (1LL << i)))
145 mlx4_dbg(dev, " %s\n", fname[i]);
146}
147
2d928651
VS		 148int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
149{
150 struct mlx4_cmd_mailbox *mailbox;
151 u32 *inbox;
152 int err = 0;
153
154#define MOD_STAT_CFG_IN_SIZE 0x100
155
156#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
157#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
158
159 mailbox = mlx4_alloc_cmd_mailbox(dev);
160 if (IS_ERR(mailbox))
161 return PTR_ERR(mailbox);
162 inbox = mailbox->buf;
163
2d928651
VS		 164 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
165 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
166
167 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 168 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 169
170 mlx4_free_cmd_mailbox(dev, mailbox);
171 return err;
172}
173
5cc914f1
MA		 174int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
175 struct mlx4_vhcr *vhcr,
176 struct mlx4_cmd_mailbox *inbox,
177 struct mlx4_cmd_mailbox *outbox,
178 struct mlx4_cmd_info *cmd)
179{
5a0d0a61 180 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 181 u8 field;
182 u32 size;
183 int err = 0;
184
185#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
186#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 187#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 188#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 189#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
190#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
191#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
192#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
193#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
194#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 195#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 196#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 197
eb456a68
JM		 198#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
199#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
200#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
201#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
202#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
203#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
204
105c320f
JM		 205#define QUERY_FUNC_CAP_FMR_FLAG 0x80
206#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
207#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 208#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
105c320f
JM		 209
210/* when opcode modifier = 1 */
5cc914f1 211#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
73e74ab4
HHZ		 212#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
213#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 214
47605df9
JM		 215#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
216#define QUERY_FUNC_CAP_QP0_PROXY 0x14
217#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
218#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 219#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 220
73e74ab4
HHZ		 221#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
222#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 223#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
105c320f 224
73e74ab4 225#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
105c320f 226
5cc914f1 227 if (vhcr->op_modifier == 1) {
449fc488
MB		 228 struct mlx4_active_ports actv_ports =
229 mlx4_get_active_ports(dev, slave);
230 int converted_port = mlx4_slave_convert_port(
231 dev, slave, vhcr->in_modifier);
232
233 if (converted_port < 0)
234 return -EINVAL;
235
236 vhcr->in_modifier = converted_port;
eb17711b
HHZ		 237 /* Set nic_info bit to mark new fields support */
238 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
239 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
105c320f 240
449fc488
MB		 241 /* phys-port = logical-port */
242 field = vhcr->in_modifier -
243 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 244 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
245
449fc488 246 field = vhcr->in_modifier;
47605df9
JM		 247 /* size is now the QP number */
248 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
249 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
250
251 size += 2;
252 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
253
254 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
255 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
256
257 size += 2;
258 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
259
8e1a28e8
HHZ		 260 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
261 QUERY_FUNC_CAP_PHYS_PORT_ID);
262
5cc914f1 263 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 264 struct mlx4_active_ports actv_ports =
265 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 266 /* enable rdma and ethernet interfaces, and new quota locations */
267 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
268 QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1
MA		 269 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
270
449fc488
MB		 271 field = min(
272 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
273 dev->caps.num_ports);
5cc914f1
MA		 274 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
275
08ff3235 276 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 277 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
278
105c320f
JM		 279 field = 0; /* protected FMR support not available as yet */
280 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
281
5a0d0a61 282 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 283 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 284 size = dev->caps.num_qps;
285 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 286
5a0d0a61 287 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 288 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 289 size = dev->caps.num_srqs;
290 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 291
5a0d0a61 292 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 293 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 294 size = dev->caps.num_cqs;
295 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1
MA		 296
297 size = dev->caps.num_eqs;
298 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
299
300 size = dev->caps.reserved_eqs;
301 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
302
5a0d0a61 303 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 304 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 305 size = dev->caps.num_mpts;
306 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 307
5a0d0a61 308 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 309 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 310 size = dev->caps.num_mtts;
311 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 312
313 size = dev->caps.num_mgms + dev->caps.num_amgms;
314 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 315 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1
MA		 316
317 } else
318 err = -EINVAL;
319
320 return err;
321}
322
47605df9
JM		 323int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
324 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 325{
326 struct mlx4_cmd_mailbox *mailbox;
327 u32 *outbox;
47605df9 328 u8 field, op_modifier;
5cc914f1 329 u32 size;
eb456a68 330 int err = 0, quotas = 0;
5cc914f1 331
47605df9 332 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 333
334 mailbox = mlx4_alloc_cmd_mailbox(dev);
335 if (IS_ERR(mailbox))
336 return PTR_ERR(mailbox);
337
47605df9
JM		 338 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
339 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 340 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
341 if (err)
342 goto out;
343
344 outbox = mailbox->buf;
345
47605df9
JM		 346 if (!op_modifier) {
347 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
348 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
349 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
350 err = -EPROTONOSUPPORT;
351 goto out;
352 }
353 func_cap->flags = field;
eb456a68 354 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 355
47605df9
JM		 356 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
357 func_cap->num_ports = field;
5cc914f1 358
47605df9
JM		 359 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
360 func_cap->pf_context_behaviour = size;
5cc914f1 361
eb456a68
JM		 362 if (quotas) {
363 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
364 func_cap->qp_quota = size & 0xFFFFFF;
365
366 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
367 func_cap->srq_quota = size & 0xFFFFFF;
368
369 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
370 func_cap->cq_quota = size & 0xFFFFFF;
371
372 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
373 func_cap->mpt_quota = size & 0xFFFFFF;
374
375 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
376 func_cap->mtt_quota = size & 0xFFFFFF;
377
378 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
379 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 380
eb456a68
JM		 381 } else {
382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
383 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 384
eb456a68
JM		 385 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
386 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 387
eb456a68
JM		 388 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
389 func_cap->cq_quota = size & 0xFFFFFF;
390
391 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
392 func_cap->mpt_quota = size & 0xFFFFFF;
393
394 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
395 func_cap->mtt_quota = size & 0xFFFFFF;
396
397 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
398 func_cap->mcg_quota = size & 0xFFFFFF;
399 }
47605df9
JM		 400 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
401 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 402
47605df9
JM		 403 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
404 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 405
47605df9
JM		 406 goto out;
407 }
5cc914f1 408
47605df9
JM		 409 /* logical port query */
410 if (gen_or_port > dev->caps.num_ports) {
411 err = -EINVAL;
412 goto out;
413 }
5cc914f1 414
eb17711b 415 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 416 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
eb17711b 417 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_OFFSET) {
47605df9
JM		 418 mlx4_err(dev, "VLAN is enforced on this port\n");
419 err = -EPROTONOSUPPORT;
5cc914f1 420 goto out;
47605df9 421 }
5cc914f1 422
eb17711b 423 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 424 mlx4_err(dev, "Force mac is enabled on this port\n");
425 err = -EPROTONOSUPPORT;
426 goto out;
5cc914f1 427 }
47605df9 428 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 429 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
430 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 431 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 432 err = -EPROTONOSUPPORT;
433 goto out;
434 }
435 }
5cc914f1 436
47605df9
JM		 437 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
438 func_cap->physical_port = field;
439 if (func_cap->physical_port != gen_or_port) {
440 err = -ENOSYS;
441 goto out;
5cc914f1
MA		 442 }
443
47605df9
JM		 444 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
445 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
446
447 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
448 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
449
450 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
451 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
452
453 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
454 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
455
8e1a28e8
HHZ		 456 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
457 MLX4_GET(func_cap->phys_port_id, outbox,
458 QUERY_FUNC_CAP_PHYS_PORT_ID);
459
5cc914f1
MA		 460 /* All other resources are allocated by the master, but we still report
461 * 'num' and 'reserved' capabilities as follows:
462 * - num remains the maximum resource index
463 * - 'num - reserved' is the total available objects of a resource, but
464 * resource indices may be less than 'reserved'
465 * TODO: set per-resource quotas */
466
467out:
468 mlx4_free_cmd_mailbox(dev, mailbox);
469
470 return err;
471}
472
225c7b1f
RD		 473int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
474{
475 struct mlx4_cmd_mailbox *mailbox;
476 u32 *outbox;
477 u8 field;
ccf86321 478 u32 field32, flags, ext_flags;
225c7b1f
RD		 479 u16 size;
480 u16 stat_rate;
481 int err;
5ae2a7a8 482 int i;
225c7b1f
RD		 483
484#define QUERY_DEV_CAP_OUT_SIZE 0x100
485#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
486#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
487#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
488#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
489#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
490#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
491#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
492#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
493#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
494#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
495#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
496#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
497#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
498#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
499#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
500#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
501#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
502#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
503#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
504#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
505#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 506#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 507#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 508#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
509#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
510#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
511#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
512#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 513#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 514#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
515#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 516#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 517#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 518#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 519#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
520#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
521#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
522#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
523#define QUERY_DEV_CAP_BF_OFFSET 0x4c
524#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
525#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
526#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
527#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
528#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
529#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
530#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
531#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
532#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
533#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
534#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
535#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 536#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
537#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 538#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 539#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 540#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 541#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
542#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 543#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
544#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
545#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
546#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
547#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
548#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
549#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
550#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
551#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
552#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 553#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 554#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
555#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
955154fa 556#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 557#define QUERY_DEV_CAP_VXLAN 0x9e
225c7b1f 558
b3416f44 559 dev_cap->flags2 = 0;
225c7b1f
RD		 560 mailbox = mlx4_alloc_cmd_mailbox(dev);
561 if (IS_ERR(mailbox))
562 return PTR_ERR(mailbox);
563 outbox = mailbox->buf;
564
565 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 566 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 567 if (err)
568 goto out;
569
570 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
571 dev_cap->reserved_qps = 1 << (field & 0xf);
572 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
573 dev_cap->max_qps = 1 << (field & 0x1f);
574 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
575 dev_cap->reserved_srqs = 1 << (field >> 4);
576 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
577 dev_cap->max_srqs = 1 << (field & 0x1f);
578 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
579 dev_cap->max_cq_sz = 1 << field;
580 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
581 dev_cap->reserved_cqs = 1 << (field & 0xf);
582 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
583 dev_cap->max_cqs = 1 << (field & 0x1f);
584 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
585 dev_cap->max_mpts = 1 << (field & 0x3f);
586 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 587 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 588 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 589 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 590 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
591 dev_cap->reserved_mtts = 1 << (field >> 4);
592 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
593 dev_cap->max_mrw_sz = 1 << field;
594 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
595 dev_cap->reserved_mrws = 1 << (field & 0xf);
596 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
597 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
598 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
599 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
600 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
601 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 602 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
603 field &= 0x1f;
604 if (!field)
605 dev_cap->max_gso_sz = 0;
606 else
607 dev_cap->max_gso_sz = 1 << field;
608
b3416f44
SP		 609 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
610 if (field & 0x20)
611 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
612 if (field & 0x10)
613 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
614 field &= 0xf;
615 if (field) {
616 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
617 dev_cap->max_rss_tbl_sz = 1 << field;
618 } else
619 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 620 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
621 dev_cap->max_rdma_global = 1 << (field & 0x3f);
622 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
623 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 624 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 625 dev_cap->num_ports = field & 0xf;
149983af
DB		 626 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
627 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 628 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
629 if (field & 0x80)
630 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
631 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 632 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
633 if (field & 0x80)
634 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 635 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
636 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 637 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
638 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 639 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
640 if (field & 0x80)
641 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 642 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 643 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 644 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 645 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
646 dev_cap->reserved_uars = field >> 4;
647 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
648 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
649 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
650 dev_cap->min_page_sz = 1 << field;
651
652 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
653 if (field & 0x80) {
654 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
655 dev_cap->bf_reg_size = 1 << (field & 0x1f);
656 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 657 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 658 field = 3;
225c7b1f
RD		 659 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
660 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
661 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
662 } else {
663 dev_cap->bf_reg_size = 0;
664 mlx4_dbg(dev, "BlueFlame not available\n");
665 }
666
667 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
668 dev_cap->max_sq_sg = field;
669 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
670 dev_cap->max_sq_desc_sz = size;
671
672 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
673 dev_cap->max_qp_per_mcg = 1 << field;
674 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
675 dev_cap->reserved_mgms = field & 0xf;
676 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
677 dev_cap->max_mcgs = 1 << field;
678 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
679 dev_cap->reserved_pds = field >> 4;
680 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
681 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 682 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
683 dev_cap->reserved_xrcds = field >> 4;
426dd00d 684 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 685 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 686
687 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
688 dev_cap->rdmarc_entry_sz = size;
689 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
690 dev_cap->qpc_entry_sz = size;
691 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
692 dev_cap->aux_entry_sz = size;
693 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
694 dev_cap->altc_entry_sz = size;
695 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
696 dev_cap->eqc_entry_sz = size;
697 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
698 dev_cap->cqc_entry_sz = size;
699 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
700 dev_cap->srq_entry_sz = size;
701 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
702 dev_cap->cmpt_entry_sz = size;
703 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
704 dev_cap->mtt_entry_sz = size;
705 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
706 dev_cap->dmpt_entry_sz = size;
707
708 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
709 dev_cap->max_srq_sz = 1 << field;
710 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
711 dev_cap->max_qp_sz = 1 << field;
712 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
713 dev_cap->resize_srq = field & 1;
714 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
715 dev_cap->max_rq_sg = field;
716 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
717 dev_cap->max_rq_desc_sz = size;
718
719 MLX4_GET(dev_cap->bmme_flags, outbox,
720 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
721 MLX4_GET(dev_cap->reserved_lkey, outbox,
722 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
955154fa
MB		 723 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
724 if (field & 1<<6)
5930e8d0 725 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 726 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
727 if (field & 1<<3)
728 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 729 MLX4_GET(dev_cap->max_icm_sz, outbox,
730 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 731 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
732 MLX4_GET(dev_cap->max_counters, outbox,
733 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 734
3f7fb021 735 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 736 if (field32 & (1 << 16))
737 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 738 if (field32 & (1 << 26))
739 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 740 if (field32 & (1 << 20))
741 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
3f7fb021 742
5ae2a7a8
RD		 743 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
744 for (i = 1; i <= dev_cap->num_ports; ++i) {
745 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
746 dev_cap->max_vl[i] = field >> 4;
747 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 748 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 749 dev_cap->max_port_width[i] = field & 0xf;
750 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
751 dev_cap->max_gids[i] = 1 << (field & 0xf);
752 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
753 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
754 }
755 } else {
7ff93f8b 756#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 757#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 758#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 759#define QUERY_PORT_WIDTH_OFFSET 0x06
760#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 761#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 762#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 763#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 764#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
765#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
766#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 767
768 for (i = 1; i <= dev_cap->num_ports; ++i) {
769 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 770 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 771 if (err)
772 goto out;
773
7ff93f8b
YP		 774 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
775 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 776 dev_cap->suggested_type[i] = (field >> 3) & 1;
777 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 778 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 779 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 780 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
781 dev_cap->max_port_width[i] = field & 0xf;
782 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
783 dev_cap->max_gids[i] = 1 << (field >> 4);
784 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
785 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
786 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 787 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
788 dev_cap->log_max_macs[i] = field & 0xf;
789 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 790 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
791 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 792 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
793 dev_cap->trans_type[i] = field32 >> 24;
794 dev_cap->vendor_oui[i] = field32 & 0xffffff;
795 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
796 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 797 }
798 }
799
95d04f07
RD		 800 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
801 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 802
803 /*
804 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
805 * we can't use any EQs whose doorbell falls on that page,
806 * even if the EQ itself isn't reserved.
807 */
808 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
809 dev_cap->reserved_eqs);
810
811 mlx4_dbg(dev, "Max ICM size %lld MB\n",
812 (unsigned long long) dev_cap->max_icm_sz >> 20);
813 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
814 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
815 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
816 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
817 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
818 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
819 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
820 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
821 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
822 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
823 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
824 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
825 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
826 dev_cap->max_pds, dev_cap->reserved_mgms);
827 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
828 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
829 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 830 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 831 dev_cap->max_port_width[1]);
225c7b1f
RD		 832 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
833 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
834 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
835 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 836 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 837 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 838 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 839
840 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 841 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 842
843out:
844 mlx4_free_cmd_mailbox(dev, mailbox);
845 return err;
846}
847
b91cb3eb
JM		 848int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
849 struct mlx4_vhcr *vhcr,
850 struct mlx4_cmd_mailbox *inbox,
851 struct mlx4_cmd_mailbox *outbox,
852 struct mlx4_cmd_info *cmd)
853{
2a4fae14 854 u64 flags;
b91cb3eb
JM		 855 int err = 0;
856 u8 field;
cc1ade94 857 u32 bmme_flags;
449fc488
MB		 858 int real_port;
859 int slave_port;
860 int first_port;
861 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 862
863 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
864 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
865 if (err)
866 return err;
867
cc1ade94
SM		 868 /* add port mng change event capability and disable mw type 1
869 * unconditionally to slaves
870 */
2a4fae14
JM		 871 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
872 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 873 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 874 actv_ports = mlx4_get_active_ports(dev, slave);
875 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
876 for (slave_port = 0, real_port = first_port;
877 real_port < first_port +
878 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
879 ++real_port, ++slave_port) {
880 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
881 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
882 else
883 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
884 }
885 for (; slave_port < dev->caps.num_ports; ++slave_port)
886 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 887 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
888
449fc488
MB		 889 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
890 field &= ~0x0F;
891 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
892 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
893
30b40c31
AV		 894 /* For guests, disable timestamp */
895 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
896 field &= 0x7f;
897 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
898
7ffdf726 899 /* For guests, disable vxlan tunneling */
57352ef4 900 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 901 field &= 0xf7;
902 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
903
b91cb3eb
JM		 904 /* For guests, report Blueflame disabled */
905 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
906 field &= 0x7f;
907 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
908
cc1ade94 909 /* For guests, disable mw type 2 */
57352ef4 910 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 911 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
912 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
913
0081c8f3
JM		 914 /* turn off device-managed steering capability if not enabled */
915 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
916 MLX4_GET(field, outbox->buf,
917 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
918 field &= 0x7f;
919 MLX4_PUT(outbox->buf, field,
920 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
921 }
4de65803
MB		 922
923 /* turn off ipoib managed steering for guests */
57352ef4 924 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 925 field &= ~0x80;
926 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
927
b91cb3eb
JM		 928 return 0;
929}
930
5cc914f1
MA		 931int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
932 struct mlx4_vhcr *vhcr,
933 struct mlx4_cmd_mailbox *inbox,
934 struct mlx4_cmd_mailbox *outbox,
935 struct mlx4_cmd_info *cmd)
936{
0eb62b93 937 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 938 u64 def_mac;
939 u8 port_type;
6634961c 940 u16 short_field;
5cc914f1 941 int err;
948e306d 942 int admin_link_state;
449fc488
MB		 943 int port = mlx4_slave_convert_port(dev, slave,
944 vhcr->in_modifier & 0xFF);
5cc914f1 945
105c320f 946#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 947#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 948#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
949#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 950
449fc488
MB		 951 if (port < 0)
952 return -EINVAL;
953
954 vhcr->in_modifier = (vhcr->in_modifier & ~0xFF) |
955 (port & 0xFF);
956
5cc914f1
MA		 957 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
958 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
959 MLX4_CMD_NATIVE);
960
961 if (!err && dev->caps.function != slave) {
0508ad64 962 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 963 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
964
965 /* get port type - currently only eth is enabled */
966 MLX4_GET(port_type, outbox->buf,
967 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
968
105c320f
JM		 969 /* No link sensing allowed */
970 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
971 /* set port type to currently operating port type */
972 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 973
948e306d
RE		 974 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
975 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
976 port_type |= MLX4_PORT_LINK_UP_MASK;
977 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
978 port_type &= ~MLX4_PORT_LINK_UP_MASK;
979
5cc914f1
MA		 980 MLX4_PUT(outbox->buf, port_type,
981 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 982
b6ffaeff 983 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 984 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 985 else
986 short_field = 1; /* slave max gids */
6634961c
JM		 987 MLX4_PUT(outbox->buf, short_field,
988 QUERY_PORT_CUR_MAX_GID_OFFSET);
989
990 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
991 MLX4_PUT(outbox->buf, short_field,
992 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 993 }
994
995 return err;
996}
997
6634961c
JM		 998int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
999 int *gid_tbl_len, int *pkey_tbl_len)
1000{
1001 struct mlx4_cmd_mailbox *mailbox;
1002 u32 *outbox;
1003 u16 field;
1004 int err;
1005
1006 mailbox = mlx4_alloc_cmd_mailbox(dev);
1007 if (IS_ERR(mailbox))
1008 return PTR_ERR(mailbox);
1009
1010 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1011 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1012 MLX4_CMD_WRAPPED);
1013 if (err)
1014 goto out;
1015
1016 outbox = mailbox->buf;
1017
1018 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1019 *gid_tbl_len = field;
1020
1021 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1022 *pkey_tbl_len = field;
1023
1024out:
1025 mlx4_free_cmd_mailbox(dev, mailbox);
1026 return err;
1027}
1028EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1029
225c7b1f
RD		 1030int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1031{
1032 struct mlx4_cmd_mailbox *mailbox;
1033 struct mlx4_icm_iter iter;
1034 __be64 *pages;
1035 int lg;
1036 int nent = 0;
1037 int i;
1038 int err = 0;
1039 int ts = 0, tc = 0;
1040
1041 mailbox = mlx4_alloc_cmd_mailbox(dev);
1042 if (IS_ERR(mailbox))
1043 return PTR_ERR(mailbox);
225c7b1f
RD		 1044 pages = mailbox->buf;
1045
1046 for (mlx4_icm_first(icm, &iter);
1047 !mlx4_icm_last(&iter);
1048 mlx4_icm_next(&iter)) {
1049 /*
1050 * We have to pass pages that are aligned to their
1051 * size, so find the least significant 1 in the
1052 * address or size and use that as our log2 size.
1053 */
1054 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1055 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1056 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1057 MLX4_ICM_PAGE_SIZE,
1058 (unsigned long long) mlx4_icm_addr(&iter),
1059 mlx4_icm_size(&iter));
225c7b1f
RD		 1060 err = -EINVAL;
1061 goto out;
1062 }
1063
1064 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1065 if (virt != -1) {
1066 pages[nent * 2] = cpu_to_be64(virt);
1067 virt += 1 << lg;
1068 }
1069
1070 pages[nent * 2 + 1] =
1071 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1072 (lg - MLX4_ICM_PAGE_SHIFT));
1073 ts += 1 << (lg - 10);
1074 ++tc;
1075
1076 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1077 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1078 MLX4_CMD_TIME_CLASS_B,
1079 MLX4_CMD_NATIVE);
225c7b1f
RD		 1080 if (err)
1081 goto out;
1082 nent = 0;
1083 }
1084 }
1085 }
1086
1087 if (nent)
f9baff50
JM		 1088 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1089 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1090 if (err)
1091 goto out;
1092
1093 switch (op) {
1094 case MLX4_CMD_MAP_FA:
1a91de28 1095 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1096 break;
1097 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1098 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1099 break;
1100 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1101 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1102 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1103 break;
1104 }
1105
1106out:
1107 mlx4_free_cmd_mailbox(dev, mailbox);
1108 return err;
1109}
1110
1111int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1112{
1113 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1114}
1115
1116int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1117{
f9baff50
JM		 1118 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1119 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1120}
1121
1122
1123int mlx4_RUN_FW(struct mlx4_dev *dev)
1124{
f9baff50
JM		 1125 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1126 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1127}
1128
1129int mlx4_QUERY_FW(struct mlx4_dev *dev)
1130{
1131 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1132 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1133 struct mlx4_cmd_mailbox *mailbox;
1134 u32 *outbox;
1135 int err = 0;
1136 u64 fw_ver;
fe40900f 1137 u16 cmd_if_rev;
225c7b1f
RD		 1138 u8 lg;
1139
1140#define QUERY_FW_OUT_SIZE 0x100
1141#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1142#define QUERY_FW_PPF_ID 0x09
fe40900f 1143#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1144#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1145#define QUERY_FW_ERR_START_OFFSET 0x30
1146#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1147#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1148
1149#define QUERY_FW_SIZE_OFFSET 0x00
1150#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1151#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1152
5cc914f1
MA		 1153#define QUERY_FW_COMM_BASE_OFFSET 0x40
1154#define QUERY_FW_COMM_BAR_OFFSET 0x48
1155
ddd8a6c1
EE		 1156#define QUERY_FW_CLOCK_OFFSET 0x50
1157#define QUERY_FW_CLOCK_BAR 0x58
1158
225c7b1f
RD		 1159 mailbox = mlx4_alloc_cmd_mailbox(dev);
1160 if (IS_ERR(mailbox))
1161 return PTR_ERR(mailbox);
1162 outbox = mailbox->buf;
1163
1164 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1165 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1166 if (err)
1167 goto out;
1168
1169 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1170 /*
3e1db334 1171 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1172 * version, so swap here.
1173 */
1174 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1175 ((fw_ver & 0xffff0000ull) >> 16) |
1176 ((fw_ver & 0x0000ffffull) << 16);
1177
752a50ca
JM		 1178 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1179 dev->caps.function = lg;
1180
b91cb3eb
JM		 1181 if (mlx4_is_slave(dev))
1182 goto out;
1183
5cc914f1 1184
fe40900f 1185 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1186 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1187 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1188 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1189 cmd_if_rev);
1190 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1191 (int) (dev->caps.fw_ver >> 32),
1192 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1193 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1194 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1195 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1196 err = -ENODEV;
1197 goto out;
1198 }
1199
5ae2a7a8
RD		 1200 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1201 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1202
225c7b1f
RD		 1203 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1204 cmd->max_cmds = 1 << lg;
1205
fe40900f 1206 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1207 (int) (dev->caps.fw_ver >> 32),
1208 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1209 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1210 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1211
1212 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1213 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1214 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1215 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1216
1217 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1218 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1219
1220 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1221 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1222 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1223 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1224
5cc914f1
MA		 1225 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1226 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1227 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1228 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1229 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1230 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1231
ddd8a6c1
EE		 1232 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1233 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1234 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1235 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1236 fw->clock_bar, fw->clock_offset);
1237
225c7b1f
RD		 1238 /*
1239 * Round up number of system pages needed in case
1240 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1241 */
1242 fw->fw_pages =
1243 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1244 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1245
1246 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1247 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1248
1249out:
1250 mlx4_free_cmd_mailbox(dev, mailbox);
1251 return err;
1252}
1253
b91cb3eb
JM		 1254int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1255 struct mlx4_vhcr *vhcr,
1256 struct mlx4_cmd_mailbox *inbox,
1257 struct mlx4_cmd_mailbox *outbox,
1258 struct mlx4_cmd_info *cmd)
1259{
1260 u8 *outbuf;
1261 int err;
1262
1263 outbuf = outbox->buf;
1264 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1265 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1266 if (err)
1267 return err;
1268
752a50ca
JM		 1269 /* for slaves, set pci PPF ID to invalid and zero out everything
1270 * else except FW version */
b91cb3eb
JM		 1271 outbuf[0] = outbuf[1] = 0;
1272 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1273 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1274
b91cb3eb
JM		 1275 return 0;
1276}
1277
225c7b1f
RD		 1278static void get_board_id(void *vsd, char *board_id)
1279{
1280 int i;
1281
1282#define VSD_OFFSET_SIG1 0x00
1283#define VSD_OFFSET_SIG2 0xde
1284#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1285#define VSD_OFFSET_TS_BOARD_ID 0x20
1286
1287#define VSD_SIGNATURE_TOPSPIN 0x5ad
1288
1289 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1290
1291 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1292 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1293 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1294 } else {
1295 /*
1296 * The board ID is a string but the firmware byte
1297 * swaps each 4-byte word before passing it back to
1298 * us. Therefore we need to swab it before printing.
1299 */
1300 for (i = 0; i < 4; ++i)
1301 ((u32 *) board_id)[i] =
1302 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1303 }
1304}
1305
1306int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1307{
1308 struct mlx4_cmd_mailbox *mailbox;
1309 u32 *outbox;
1310 int err;
1311
1312#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1313#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1314#define QUERY_ADAPTER_VSD_OFFSET 0x20
1315
1316 mailbox = mlx4_alloc_cmd_mailbox(dev);
1317 if (IS_ERR(mailbox))
1318 return PTR_ERR(mailbox);
1319 outbox = mailbox->buf;
1320
1321 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1322 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1323 if (err)
1324 goto out;
1325
225c7b1f
RD		 1326 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1327
1328 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1329 adapter->board_id);
1330
1331out:
1332 mlx4_free_cmd_mailbox(dev, mailbox);
1333 return err;
1334}
1335
1336int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1337{
1338 struct mlx4_cmd_mailbox *mailbox;
1339 __be32 *inbox;
1340 int err;
1341
1342#define INIT_HCA_IN_SIZE 0x200
1343#define INIT_HCA_VERSION_OFFSET 0x000
1344#define INIT_HCA_VERSION 2
7ffdf726 1345#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1346#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1347#define INIT_HCA_FLAGS_OFFSET 0x014
1348#define INIT_HCA_QPC_OFFSET 0x020
1349#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1350#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1351#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1352#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1353#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1354#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1355#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1356#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1357#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1358#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1359#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1360#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1361#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1362#define INIT_HCA_MCAST_OFFSET 0x0c0
1363#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1364#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1365#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1366#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1367#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1368#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1369#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1370#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1371#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1372#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1373#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1374#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1375#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1376#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1377#define INIT_HCA_TPT_OFFSET 0x0f0
1378#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1379#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1380#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1381#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1382#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1383#define INIT_HCA_UAR_OFFSET 0x120
1384#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1385#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1386
1387 mailbox = mlx4_alloc_cmd_mailbox(dev);
1388 if (IS_ERR(mailbox))
1389 return PTR_ERR(mailbox);
1390 inbox = mailbox->buf;
1391
225c7b1f
RD		 1392 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1393
c57e20dc
EC		 1394 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1395 (ilog2(cache_line_size()) - 4) << 5;
1396
225c7b1f
RD		 1397#if defined(__LITTLE_ENDIAN)
1398 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1399#elif defined(__BIG_ENDIAN)
1400 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1401#else
1402#error Host endianness not defined
1403#endif
1404 /* Check port for UD address vector: */
1405 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1406
8ff095ec
EC		 1407 /* Enable IPoIB checksumming if we can: */
1408 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1409 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1410
51f5f0ee
JM		 1411 /* Enable QoS support if module parameter set */
1412 if (enable_qos)
1413 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1414
f2a3f6a3
OG		 1415 /* enable counters */
1416 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1417 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1418
08ff3235
OG		 1419 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1420 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1421 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1422 dev->caps.eqe_size = 64;
1423 dev->caps.eqe_factor = 1;
1424 } else {
1425 dev->caps.eqe_size = 32;
1426 dev->caps.eqe_factor = 0;
1427 }
1428
1429 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1430 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1431 dev->caps.cqe_size = 64;
1432 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1433 } else {
1434 dev->caps.cqe_size = 32;
1435 }
1436
225c7b1f
RD		 1437 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1438
1439 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1440 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1441 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1442 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1443 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1444 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1445 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1446 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1447 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1448 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1449 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1450 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1451
0ff1fb65
HHZ		 1452 /* steering attributes */
1453 if (dev->caps.steering_mode ==
1454 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1455 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1456 cpu_to_be32(1 <<
1457 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1458
1459 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1460 MLX4_PUT(inbox, param->log_mc_entry_sz,
1461 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1462 MLX4_PUT(inbox, param->log_mc_table_sz,
1463 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1464 /* Enable Ethernet flow steering
1465 * with udp unicast and tcp unicast
1466 */
23537b73 1467 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1468 INIT_HCA_FS_ETH_BITS_OFFSET);
1469 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1470 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1471 /* Enable IPoIB flow steering
1472 * with udp unicast and tcp unicast
1473 */
23537b73 1474 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1475 INIT_HCA_FS_IB_BITS_OFFSET);
1476 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1477 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1478 } else {
1479 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1480 MLX4_PUT(inbox, param->log_mc_entry_sz,
1481 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1482 MLX4_PUT(inbox, param->log_mc_hash_sz,
1483 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1484 MLX4_PUT(inbox, param->log_mc_table_sz,
1485 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1486 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1487 MLX4_PUT(inbox, (u8) (1 << 3),
1488 INIT_HCA_UC_STEERING_OFFSET);
1489 }
225c7b1f
RD		 1490
1491 /* TPT attributes */
1492
1493 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1494 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1495 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1496 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1497 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1498
1499 /* UAR attributes */
1500
ab9c17a0 1501 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1502 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1503
7ffdf726
OG		 1504 /* set parser VXLAN attributes */
1505 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1506 u8 parser_params = 0;
1507 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1508 }
1509
f9baff50
JM		 1510 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1511 MLX4_CMD_NATIVE);
225c7b1f
RD		 1512
1513 if (err)
1514 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1515
1516 mlx4_free_cmd_mailbox(dev, mailbox);
1517 return err;
1518}
1519
ab9c17a0
JM		 1520int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1521 struct mlx4_init_hca_param *param)
1522{
1523 struct mlx4_cmd_mailbox *mailbox;
1524 __be32 *outbox;
7b8157be 1525 u32 dword_field;
ab9c17a0 1526 int err;
08ff3235 1527 u8 byte_field;
ab9c17a0
JM		 1528
1529#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1530#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1531
1532 mailbox = mlx4_alloc_cmd_mailbox(dev);
1533 if (IS_ERR(mailbox))
1534 return PTR_ERR(mailbox);
1535 outbox = mailbox->buf;
1536
1537 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1538 MLX4_CMD_QUERY_HCA,
1539 MLX4_CMD_TIME_CLASS_B,
1540 !mlx4_is_slave(dev));
1541 if (err)
1542 goto out;
1543
1544 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1545 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1546
1547 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1548
1549 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1550 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1551 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1552 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1553 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1554 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1555 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1556 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1557 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1558 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1559 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1560 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1561
7b8157be
JM		 1562 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1563 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1564 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1565 } else {
1566 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1567 if (byte_field & 0x8)
1568 param->steering_mode = MLX4_STEERING_MODE_B0;
1569 else
1570 param->steering_mode = MLX4_STEERING_MODE_A0;
1571 }
0ff1fb65 1572 /* steering attributes */
7b8157be 1573 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1574 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1575 MLX4_GET(param->log_mc_entry_sz, outbox,
1576 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1577 MLX4_GET(param->log_mc_table_sz, outbox,
1578 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1579 } else {
1580 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1581 MLX4_GET(param->log_mc_entry_sz, outbox,
1582 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1583 MLX4_GET(param->log_mc_hash_sz, outbox,
1584 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1585 MLX4_GET(param->log_mc_table_sz, outbox,
1586 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1587 }
ab9c17a0 1588
08ff3235
OG		 1589 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1590 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1591 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1592 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1593 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1594 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1595
ab9c17a0
JM		 1596 /* TPT attributes */
1597
1598 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1599 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1600 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1601 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1602 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1603
1604 /* UAR attributes */
1605
1606 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1607 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1608
1609out:
1610 mlx4_free_cmd_mailbox(dev, mailbox);
1611
1612 return err;
1613}
1614
980e9001
JM		 1615/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1616 * and real QP0 are active, so that the paravirtualized QP0 is ready
1617 * to operate */
1618static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1619{
1620 struct mlx4_priv *priv = mlx4_priv(dev);
1621 /* irrelevant if not infiniband */
1622 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1623 priv->mfunc.master.qp0_state[port].qp0_active)
1624 return 1;
1625 return 0;
1626}
1627
5cc914f1
MA		 1628int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1629 struct mlx4_vhcr *vhcr,
1630 struct mlx4_cmd_mailbox *inbox,
1631 struct mlx4_cmd_mailbox *outbox,
1632 struct mlx4_cmd_info *cmd)
1633{
1634 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1635 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1636 int err;
1637
449fc488
MB		 1638 if (port < 0)
1639 return -EINVAL;
1640
5cc914f1
MA		 1641 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1642 return 0;
1643
980e9001
JM		 1644 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1645 /* Enable port only if it was previously disabled */
1646 if (!priv->mfunc.master.init_port_ref[port]) {
1647 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1648 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1649 if (err)
1650 return err;
1651 }
1652 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1653 } else {
1654 if (slave == mlx4_master_func_num(dev)) {
1655 if (check_qp0_state(dev, slave, port) &&
1656 !priv->mfunc.master.qp0_state[port].port_active) {
1657 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1658 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1659 if (err)
1660 return err;
1661 priv->mfunc.master.qp0_state[port].port_active = 1;
1662 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1663 }
1664 } else
1665 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1666 }
1667 ++priv->mfunc.master.init_port_ref[port];
1668 return 0;
1669}
1670
5ae2a7a8 1671int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1672{
1673 struct mlx4_cmd_mailbox *mailbox;
1674 u32 *inbox;
1675 int err;
1676 u32 flags;
5ae2a7a8 1677 u16 field;
225c7b1f 1678
5ae2a7a8 1679 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1680#define INIT_PORT_IN_SIZE 256
1681#define INIT_PORT_FLAGS_OFFSET 0x00
1682#define INIT_PORT_FLAG_SIG (1 << 18)
1683#define INIT_PORT_FLAG_NG (1 << 17)
1684#define INIT_PORT_FLAG_G0 (1 << 16)
1685#define INIT_PORT_VL_SHIFT 4
1686#define INIT_PORT_PORT_WIDTH_SHIFT 8
1687#define INIT_PORT_MTU_OFFSET 0x04
1688#define INIT_PORT_MAX_GID_OFFSET 0x06
1689#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1690#define INIT_PORT_GUID0_OFFSET 0x10
1691#define INIT_PORT_NODE_GUID_OFFSET 0x18
1692#define INIT_PORT_SI_GUID_OFFSET 0x20
1693
5ae2a7a8
RD		 1694 mailbox = mlx4_alloc_cmd_mailbox(dev);
1695 if (IS_ERR(mailbox))
1696 return PTR_ERR(mailbox);
1697 inbox = mailbox->buf;
225c7b1f 1698
5ae2a7a8
RD		 1699 flags = 0;
1700 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1701 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1702 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1703
b79acb49 1704 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1705 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1706 field = dev->caps.gid_table_len[port];
1707 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1708 field = dev->caps.pkey_table_len[port];
1709 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1710
5ae2a7a8 1711 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1712 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1713
5ae2a7a8
RD		 1714 mlx4_free_cmd_mailbox(dev, mailbox);
1715 } else
1716 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1717 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1718
1719 return err;
1720}
1721EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1722
5cc914f1
MA		 1723int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1724 struct mlx4_vhcr *vhcr,
1725 struct mlx4_cmd_mailbox *inbox,
1726 struct mlx4_cmd_mailbox *outbox,
1727 struct mlx4_cmd_info *cmd)
1728{
1729 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1730 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1731 int err;
1732
449fc488
MB		 1733 if (port < 0)
1734 return -EINVAL;
1735
5cc914f1
MA		 1736 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1737 (1 << port)))
1738 return 0;
1739
980e9001
JM		 1740 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1741 if (priv->mfunc.master.init_port_ref[port] == 1) {
1742 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1743 1000, MLX4_CMD_NATIVE);
1744 if (err)
1745 return err;
1746 }
1747 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1748 } else {
1749 /* infiniband port */
1750 if (slave == mlx4_master_func_num(dev)) {
1751 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1752 priv->mfunc.master.qp0_state[port].port_active) {
1753 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1754 1000, MLX4_CMD_NATIVE);
1755 if (err)
1756 return err;
1757 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1758 priv->mfunc.master.qp0_state[port].port_active = 0;
1759 }
1760 } else
1761 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1762 }
5cc914f1
MA		 1763 --priv->mfunc.master.init_port_ref[port];
1764 return 0;
1765}
1766
225c7b1f
RD		 1767int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1768{
f9baff50
JM		 1769 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1770 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1771}
1772EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1773
1774int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1775{
f9baff50
JM		 1776 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1777 MLX4_CMD_NATIVE);
225c7b1f
RD		 1778}
1779
d18f141a
OG		 1780struct mlx4_config_dev {
1781 __be32 update_flags;
1782 __be32 rsdv1[3];
1783 __be16 vxlan_udp_dport;
1784 __be16 rsvd2;
1785};
1786
1787#define MLX4_VXLAN_UDP_DPORT (1 << 0)
1788
1789static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1790{
1791 int err;
1792 struct mlx4_cmd_mailbox *mailbox;
1793
1794 mailbox = mlx4_alloc_cmd_mailbox(dev);
1795 if (IS_ERR(mailbox))
1796 return PTR_ERR(mailbox);
1797
1798 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1799
1800 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1801 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1802
1803 mlx4_free_cmd_mailbox(dev, mailbox);
1804 return err;
1805}
1806
1807int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
1808{
1809 struct mlx4_config_dev config_dev;
1810
1811 memset(&config_dev, 0, sizeof(config_dev));
1812 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
1813 config_dev.vxlan_udp_dport = udp_port;
1814
1815 return mlx4_CONFIG_DEV(dev, &config_dev);
1816}
1817EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
1818
1819
225c7b1f
RD		 1820int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1821{
1822 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1823 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1824 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1825 if (ret)
1826 return ret;
1827
1828 /*
1829 * Round up number of system pages needed in case
1830 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1831 */
1832 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1833 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1834
1835 return 0;
1836}
1837
1838int mlx4_NOP(struct mlx4_dev *dev)
1839{
1840 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1841 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1842}
14c07b13 1843
8e1a28e8
HHZ		 1844int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1845{
1846 u8 port;
1847 u32 *outbox;
1848 struct mlx4_cmd_mailbox *mailbox;
1849 u32 in_mod;
1850 u32 guid_hi, guid_lo;
1851 int err, ret = 0;
1852#define MOD_STAT_CFG_PORT_OFFSET 8
1853#define MOD_STAT_CFG_GUID_H 0X14
1854#define MOD_STAT_CFG_GUID_L 0X1c
1855
1856 mailbox = mlx4_alloc_cmd_mailbox(dev);
1857 if (IS_ERR(mailbox))
1858 return PTR_ERR(mailbox);
1859 outbox = mailbox->buf;
1860
1861 for (port = 1; port <= dev->caps.num_ports; port++) {
1862 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1863 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1864 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1865 MLX4_CMD_NATIVE);
1866 if (err) {
1867 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1868 port);
1869 ret = err;
1870 } else {
1871 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1872 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1873 dev->caps.phys_port_id[port] = (u64)guid_lo |
1874 (u64)guid_hi << 32;
1875 }
1876 }
1877 mlx4_free_cmd_mailbox(dev, mailbox);
1878 return ret;
1879}
1880
14c07b13
YP		 1881#define MLX4_WOL_SETUP_MODE (5 << 28)
1882int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1883{
1884 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1885
1886 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1887 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1888 MLX4_CMD_NATIVE);
14c07b13
YP		 1889}
1890EXPORT_SYMBOL_GPL(mlx4_wol_read);
1891
1892int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1893{
1894 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1895
1896 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1897 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1898}
1899EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 1900
1901enum {
1902 ADD_TO_MCG = 0x26,
1903};
1904
1905
1906void mlx4_opreq_action(struct work_struct *work)
1907{
1908 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1909 opreq_task);
1910 struct mlx4_dev *dev = &priv->dev;
1911 int num_tasks = atomic_read(&priv->opreq_count);
1912 struct mlx4_cmd_mailbox *mailbox;
1913 struct mlx4_mgm *mgm;
1914 u32 *outbox;
1915 u32 modifier;
1916 u16 token;
fe6f700d
YP		 1917 u16 type;
1918 int err;
1919 u32 num_qps;
1920 struct mlx4_qp qp;
1921 int i;
1922 u8 rem_mcg;
1923 u8 prot;
1924
1925#define GET_OP_REQ_MODIFIER_OFFSET 0x08
1926#define GET_OP_REQ_TOKEN_OFFSET 0x14
1927#define GET_OP_REQ_TYPE_OFFSET 0x1a
1928#define GET_OP_REQ_DATA_OFFSET 0x20
1929
1930 mailbox = mlx4_alloc_cmd_mailbox(dev);
1931 if (IS_ERR(mailbox)) {
1932 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
1933 return;
1934 }
1935 outbox = mailbox->buf;
1936
1937 while (num_tasks) {
1938 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1939 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1940 MLX4_CMD_NATIVE);
1941 if (err) {
6d3be300 1942 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 1943 err);
1944 return;
1945 }
1946 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
1947 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
1948 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 1949 type &= 0xfff;
1950
1951 switch (type) {
1952 case ADD_TO_MCG:
1953 if (dev->caps.steering_mode ==
1954 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1955 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
1956 err = EPERM;
1957 break;
1958 }
1959 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
1960 GET_OP_REQ_DATA_OFFSET);
1961 num_qps = be32_to_cpu(mgm->members_count) &
1962 MGM_QPN_MASK;
1963 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
1964 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
1965
1966 for (i = 0; i < num_qps; i++) {
1967 qp.qpn = be32_to_cpu(mgm->qp[i]);
1968 if (rem_mcg)
1969 err = mlx4_multicast_detach(dev, &qp,
1970 mgm->gid,
1971 prot, 0);
1972 else
1973 err = mlx4_multicast_attach(dev, &qp,
1974 mgm->gid,
1975 mgm->gid[5]
1976 , 0, prot,
1977 NULL);
1978 if (err)
1979 break;
1980 }
1981 break;
1982 default:
1983 mlx4_warn(dev, "Bad type for required operation\n");
1984 err = EINVAL;
1985 break;
1986 }
28d222bb
EP		 1987 err = mlx4_cmd(dev, 0, ((u32) err |
1988 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 1989 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
1990 MLX4_CMD_NATIVE);
1991 if (err) {
1992 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
1993 err);
1994 goto out;
1995 }
1996 memset(outbox, 0, 0xffc);
1997 num_tasks = atomic_dec_return(&priv->opreq_count);
1998 }
1999
2000out:
2001 mlx4_free_cmd_mailbox(dev, mailbox);
2002}
Linux kernel - Deliverables
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