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mlx4_core: Fix error flow in the flow steering wrapper
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
7ff93f8b 94 [12] = "DPDP",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
00f5ce99 112 [59] = "Port management change event support",
08ff3235
OG		 113 [61] = "64 byte EQE support",
114 [62] = "64 byte CQE support",
225c7b1f
RD		 115 };
116 int i;
117
118 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 119 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 120 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 121 mlx4_dbg(dev, " %s\n", fname[i]);
122}
123
b3416f44
SP		 124static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
125{
126 static const char * const fname[] = {
127 [0] = "RSS support",
128 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65
HHZ		 129 [2] = "RSS XOR Hash Function support",
130 [3] = "Device manage flow steering support"
b3416f44
SP		 131 };
132 int i;
133
134 for (i = 0; i < ARRAY_SIZE(fname); ++i)
135 if (fname[i] && (flags & (1LL << i)))
136 mlx4_dbg(dev, " %s\n", fname[i]);
137}
138
2d928651
VS		 139int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
140{
141 struct mlx4_cmd_mailbox *mailbox;
142 u32 *inbox;
143 int err = 0;
144
145#define MOD_STAT_CFG_IN_SIZE 0x100
146
147#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
148#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
149
150 mailbox = mlx4_alloc_cmd_mailbox(dev);
151 if (IS_ERR(mailbox))
152 return PTR_ERR(mailbox);
153 inbox = mailbox->buf;
154
155 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
156
157 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
158 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
159
160 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 161 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 162
163 mlx4_free_cmd_mailbox(dev, mailbox);
164 return err;
165}
166
5cc914f1
MA		 167int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
168 struct mlx4_vhcr *vhcr,
169 struct mlx4_cmd_mailbox *inbox,
170 struct mlx4_cmd_mailbox *outbox,
171 struct mlx4_cmd_info *cmd)
172{
173 u8 field;
174 u32 size;
175 int err = 0;
176
177#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
178#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 179#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 180#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
5cc914f1
MA		 181#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
182#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
183#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
184#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
185#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
186#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
187#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 188#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 189
105c320f
JM		 190#define QUERY_FUNC_CAP_FMR_FLAG 0x80
191#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
192#define QUERY_FUNC_CAP_FLAG_ETH 0x80
193
194/* when opcode modifier = 1 */
5cc914f1 195#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
105c320f 196#define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
5cc914f1
MA		 197#define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
198
47605df9
JM		 199#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
200#define QUERY_FUNC_CAP_QP0_PROXY 0x14
201#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
202#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
203
105c320f
JM		 204#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
205#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
206
207#define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
208
5cc914f1 209 if (vhcr->op_modifier == 1) {
105c320f
JM		 210 field = 0;
211 /* ensure force vlan and force mac bits are not set */
5cc914f1 212 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
105c320f
JM		 213 /* ensure that phy_wqe_gid bit is not set */
214 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
215
47605df9
JM		 216 field = vhcr->in_modifier; /* phys-port = logical-port */
217 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
218
219 /* size is now the QP number */
220 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1;
221 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
222
223 size += 2;
224 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
225
226 size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1;
227 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY);
228
229 size += 2;
230 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY);
231
5cc914f1 232 } else if (vhcr->op_modifier == 0) {
105c320f
JM		 233 /* enable rdma and ethernet interfaces */
234 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
5cc914f1
MA		 235 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
236
5cc914f1
MA		 237 field = dev->caps.num_ports;
238 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
239
08ff3235 240 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 241 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
242
105c320f
JM		 243 field = 0; /* protected FMR support not available as yet */
244 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
245
5cc914f1
MA		 246 size = dev->caps.num_qps;
247 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
248
249 size = dev->caps.num_srqs;
250 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
251
252 size = dev->caps.num_cqs;
253 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
254
255 size = dev->caps.num_eqs;
256 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
257
258 size = dev->caps.reserved_eqs;
259 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
260
261 size = dev->caps.num_mpts;
262 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
263
2b8fb286 264 size = dev->caps.num_mtts;
5cc914f1
MA		 265 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
266
267 size = dev->caps.num_mgms + dev->caps.num_amgms;
268 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
269
270 } else
271 err = -EINVAL;
272
273 return err;
274}
275
47605df9
JM		 276int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
277 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 278{
279 struct mlx4_cmd_mailbox *mailbox;
280 u32 *outbox;
47605df9 281 u8 field, op_modifier;
5cc914f1 282 u32 size;
5cc914f1
MA		 283 int err = 0;
284
47605df9 285 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 286
287 mailbox = mlx4_alloc_cmd_mailbox(dev);
288 if (IS_ERR(mailbox))
289 return PTR_ERR(mailbox);
290
47605df9
JM		 291 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
292 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 293 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
294 if (err)
295 goto out;
296
297 outbox = mailbox->buf;
298
47605df9
JM		 299 if (!op_modifier) {
300 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
301 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
302 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
303 err = -EPROTONOSUPPORT;
304 goto out;
305 }
306 func_cap->flags = field;
5cc914f1 307
47605df9
JM		 308 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
309 func_cap->num_ports = field;
5cc914f1 310
47605df9
JM		 311 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
312 func_cap->pf_context_behaviour = size;
5cc914f1 313
47605df9
JM		 314 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
315 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 316
47605df9
JM		 317 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
318 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 319
47605df9
JM		 320 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
321 func_cap->cq_quota = size & 0xFFFFFF;
5cc914f1 322
47605df9
JM		 323 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
324 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 325
47605df9
JM		 326 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
327 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 328
47605df9
JM		 329 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
330 func_cap->mpt_quota = size & 0xFFFFFF;
5cc914f1 331
47605df9
JM		 332 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
333 func_cap->mtt_quota = size & 0xFFFFFF;
5cc914f1 334
47605df9
JM		 335 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
336 func_cap->mcg_quota = size & 0xFFFFFF;
337 goto out;
338 }
5cc914f1 339
47605df9
JM		 340 /* logical port query */
341 if (gen_or_port > dev->caps.num_ports) {
342 err = -EINVAL;
343 goto out;
344 }
5cc914f1 345
47605df9
JM		 346 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
347 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
348 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
349 mlx4_err(dev, "VLAN is enforced on this port\n");
350 err = -EPROTONOSUPPORT;
5cc914f1 351 goto out;
47605df9 352 }
5cc914f1 353
47605df9
JM		 354 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
355 mlx4_err(dev, "Force mac is enabled on this port\n");
356 err = -EPROTONOSUPPORT;
357 goto out;
5cc914f1 358 }
47605df9
JM		 359 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
360 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
361 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
362 mlx4_err(dev, "phy_wqe_gid is "
363 "enforced on this ib port\n");
364 err = -EPROTONOSUPPORT;
365 goto out;
366 }
367 }
5cc914f1 368
47605df9
JM		 369 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
370 func_cap->physical_port = field;
371 if (func_cap->physical_port != gen_or_port) {
372 err = -ENOSYS;
373 goto out;
5cc914f1
MA		 374 }
375
47605df9
JM		 376 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
377 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
378
379 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
380 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
381
382 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
383 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
384
385 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
386 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
387
5cc914f1
MA		 388 /* All other resources are allocated by the master, but we still report
389 * 'num' and 'reserved' capabilities as follows:
390 * - num remains the maximum resource index
391 * - 'num - reserved' is the total available objects of a resource, but
392 * resource indices may be less than 'reserved'
393 * TODO: set per-resource quotas */
394
395out:
396 mlx4_free_cmd_mailbox(dev, mailbox);
397
398 return err;
399}
400
225c7b1f
RD		 401int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
402{
403 struct mlx4_cmd_mailbox *mailbox;
404 u32 *outbox;
405 u8 field;
ccf86321 406 u32 field32, flags, ext_flags;
225c7b1f
RD		 407 u16 size;
408 u16 stat_rate;
409 int err;
5ae2a7a8 410 int i;
225c7b1f
RD		 411
412#define QUERY_DEV_CAP_OUT_SIZE 0x100
413#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
414#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
415#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
416#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
417#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
418#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
419#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
420#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
421#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
422#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
423#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
424#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
425#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
426#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
427#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
428#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
429#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
430#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
431#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
432#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
433#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 434#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 435#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 436#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
437#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
438#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
439#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
440#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 441#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 442#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
443#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
444#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 445#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 446#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
447#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
448#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
449#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
450#define QUERY_DEV_CAP_BF_OFFSET 0x4c
451#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
452#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
453#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
454#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
455#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
456#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
457#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
458#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
459#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
460#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
461#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
462#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 463#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
464#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 465#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
0ff1fb65
HHZ		 466#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
467#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 468#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
469#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
470#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
471#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
472#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
473#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
474#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
475#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
476#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
477#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 478#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 479#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
480#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
481
b3416f44 482 dev_cap->flags2 = 0;
225c7b1f
RD		 483 mailbox = mlx4_alloc_cmd_mailbox(dev);
484 if (IS_ERR(mailbox))
485 return PTR_ERR(mailbox);
486 outbox = mailbox->buf;
487
488 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 489 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 490 if (err)
491 goto out;
492
493 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
494 dev_cap->reserved_qps = 1 << (field & 0xf);
495 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
496 dev_cap->max_qps = 1 << (field & 0x1f);
497 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
498 dev_cap->reserved_srqs = 1 << (field >> 4);
499 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
500 dev_cap->max_srqs = 1 << (field & 0x1f);
501 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
502 dev_cap->max_cq_sz = 1 << field;
503 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
504 dev_cap->reserved_cqs = 1 << (field & 0xf);
505 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
506 dev_cap->max_cqs = 1 << (field & 0x1f);
507 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
508 dev_cap->max_mpts = 1 << (field & 0x3f);
509 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 510 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 511 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 512 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 513 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
514 dev_cap->reserved_mtts = 1 << (field >> 4);
515 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
516 dev_cap->max_mrw_sz = 1 << field;
517 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
518 dev_cap->reserved_mrws = 1 << (field & 0xf);
519 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
520 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
521 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
522 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
523 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
524 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 525 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
526 field &= 0x1f;
527 if (!field)
528 dev_cap->max_gso_sz = 0;
529 else
530 dev_cap->max_gso_sz = 1 << field;
531
b3416f44
SP		 532 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
533 if (field & 0x20)
534 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
535 if (field & 0x10)
536 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
537 field &= 0xf;
538 if (field) {
539 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
540 dev_cap->max_rss_tbl_sz = 1 << field;
541 } else
542 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 543 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
544 dev_cap->max_rdma_global = 1 << (field & 0x3f);
545 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
546 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 547 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 548 dev_cap->num_ports = field & 0xf;
149983af
DB		 549 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
550 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 551 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
552 if (field & 0x80)
553 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
554 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
555 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
556 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 557 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
558 dev_cap->stat_rate_support = stat_rate;
ccf86321 559 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 560 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 561 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 562 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
563 dev_cap->reserved_uars = field >> 4;
564 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
565 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
566 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
567 dev_cap->min_page_sz = 1 << field;
568
569 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
570 if (field & 0x80) {
571 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
572 dev_cap->bf_reg_size = 1 << (field & 0x1f);
573 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 574 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 575 field = 3;
225c7b1f
RD		 576 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
577 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
578 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
579 } else {
580 dev_cap->bf_reg_size = 0;
581 mlx4_dbg(dev, "BlueFlame not available\n");
582 }
583
584 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
585 dev_cap->max_sq_sg = field;
586 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
587 dev_cap->max_sq_desc_sz = size;
588
589 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
590 dev_cap->max_qp_per_mcg = 1 << field;
591 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
592 dev_cap->reserved_mgms = field & 0xf;
593 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
594 dev_cap->max_mcgs = 1 << field;
595 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
596 dev_cap->reserved_pds = field >> 4;
597 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
598 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 599 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
600 dev_cap->reserved_xrcds = field >> 4;
426dd00d 601 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 602 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 603
604 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
605 dev_cap->rdmarc_entry_sz = size;
606 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
607 dev_cap->qpc_entry_sz = size;
608 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
609 dev_cap->aux_entry_sz = size;
610 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
611 dev_cap->altc_entry_sz = size;
612 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
613 dev_cap->eqc_entry_sz = size;
614 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
615 dev_cap->cqc_entry_sz = size;
616 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
617 dev_cap->srq_entry_sz = size;
618 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
619 dev_cap->cmpt_entry_sz = size;
620 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
621 dev_cap->mtt_entry_sz = size;
622 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
623 dev_cap->dmpt_entry_sz = size;
624
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
626 dev_cap->max_srq_sz = 1 << field;
627 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
628 dev_cap->max_qp_sz = 1 << field;
629 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
630 dev_cap->resize_srq = field & 1;
631 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
632 dev_cap->max_rq_sg = field;
633 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
634 dev_cap->max_rq_desc_sz = size;
635
636 MLX4_GET(dev_cap->bmme_flags, outbox,
637 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
638 MLX4_GET(dev_cap->reserved_lkey, outbox,
639 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
640 MLX4_GET(dev_cap->max_icm_sz, outbox,
641 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 642 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
643 MLX4_GET(dev_cap->max_counters, outbox,
644 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 645
5ae2a7a8
RD		 646 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
647 for (i = 1; i <= dev_cap->num_ports; ++i) {
648 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
649 dev_cap->max_vl[i] = field >> 4;
650 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 651 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 652 dev_cap->max_port_width[i] = field & 0xf;
653 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
654 dev_cap->max_gids[i] = 1 << (field & 0xf);
655 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
656 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
657 }
658 } else {
7ff93f8b 659#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 660#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 661#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 662#define QUERY_PORT_WIDTH_OFFSET 0x06
663#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 664#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 665#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 666#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 667#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
668#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
669#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 670
671 for (i = 1; i <= dev_cap->num_ports; ++i) {
672 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 673 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 674 if (err)
675 goto out;
676
7ff93f8b
YP		 677 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
678 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 679 dev_cap->suggested_type[i] = (field >> 3) & 1;
680 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 681 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 682 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 683 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
684 dev_cap->max_port_width[i] = field & 0xf;
685 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
686 dev_cap->max_gids[i] = 1 << (field >> 4);
687 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
688 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
689 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 690 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
691 dev_cap->log_max_macs[i] = field & 0xf;
692 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 693 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
694 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 695 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
696 dev_cap->trans_type[i] = field32 >> 24;
697 dev_cap->vendor_oui[i] = field32 & 0xffffff;
698 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
699 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 700 }
701 }
702
95d04f07
RD		 703 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
704 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 705
706 /*
707 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
708 * we can't use any EQs whose doorbell falls on that page,
709 * even if the EQ itself isn't reserved.
710 */
711 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
712 dev_cap->reserved_eqs);
713
714 mlx4_dbg(dev, "Max ICM size %lld MB\n",
715 (unsigned long long) dev_cap->max_icm_sz >> 20);
716 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
717 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
718 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
719 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
720 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
721 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
722 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
723 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
724 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
725 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
726 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
727 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
728 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
729 dev_cap->max_pds, dev_cap->reserved_mgms);
730 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
731 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
732 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 733 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 734 dev_cap->max_port_width[1]);
225c7b1f
RD		 735 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
736 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
737 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
738 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 739 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 740 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 741 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 742
743 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 744 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 745
746out:
747 mlx4_free_cmd_mailbox(dev, mailbox);
748 return err;
749}
750
b91cb3eb
JM		 751int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
752 struct mlx4_vhcr *vhcr,
753 struct mlx4_cmd_mailbox *inbox,
754 struct mlx4_cmd_mailbox *outbox,
755 struct mlx4_cmd_info *cmd)
756{
2a4fae14 757 u64 flags;
b91cb3eb
JM		 758 int err = 0;
759 u8 field;
760
761 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
762 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
763 if (err)
764 return err;
765
2a4fae14
JM		 766 /* add port mng change event capability unconditionally to slaves */
767 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
768 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
769 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
770
b91cb3eb
JM		 771 /* For guests, report Blueflame disabled */
772 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
773 field &= 0x7f;
774 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
775
776 return 0;
777}
778
5cc914f1
MA		 779int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
780 struct mlx4_vhcr *vhcr,
781 struct mlx4_cmd_mailbox *inbox,
782 struct mlx4_cmd_mailbox *outbox,
783 struct mlx4_cmd_info *cmd)
784{
785 u64 def_mac;
786 u8 port_type;
6634961c 787 u16 short_field;
5cc914f1
MA		 788 int err;
789
105c320f 790#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
6634961c
JM		 791#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
792#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 793
5cc914f1
MA		 794 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
795 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
796 MLX4_CMD_NATIVE);
797
798 if (!err && dev->caps.function != slave) {
799 /* set slave default_mac address */
800 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
801 def_mac += slave << 8;
802 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
803
804 /* get port type - currently only eth is enabled */
805 MLX4_GET(port_type, outbox->buf,
806 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
807
105c320f
JM		 808 /* No link sensing allowed */
809 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
810 /* set port type to currently operating port type */
811 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1
MA		 812
813 MLX4_PUT(outbox->buf, port_type,
814 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c
JM		 815
816 short_field = 1; /* slave max gids */
817 MLX4_PUT(outbox->buf, short_field,
818 QUERY_PORT_CUR_MAX_GID_OFFSET);
819
820 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
821 MLX4_PUT(outbox->buf, short_field,
822 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 823 }
824
825 return err;
826}
827
6634961c
JM		 828int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
829 int *gid_tbl_len, int *pkey_tbl_len)
830{
831 struct mlx4_cmd_mailbox *mailbox;
832 u32 *outbox;
833 u16 field;
834 int err;
835
836 mailbox = mlx4_alloc_cmd_mailbox(dev);
837 if (IS_ERR(mailbox))
838 return PTR_ERR(mailbox);
839
840 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
841 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
842 MLX4_CMD_WRAPPED);
843 if (err)
844 goto out;
845
846 outbox = mailbox->buf;
847
848 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
849 *gid_tbl_len = field;
850
851 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
852 *pkey_tbl_len = field;
853
854out:
855 mlx4_free_cmd_mailbox(dev, mailbox);
856 return err;
857}
858EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
859
225c7b1f
RD		 860int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
861{
862 struct mlx4_cmd_mailbox *mailbox;
863 struct mlx4_icm_iter iter;
864 __be64 *pages;
865 int lg;
866 int nent = 0;
867 int i;
868 int err = 0;
869 int ts = 0, tc = 0;
870
871 mailbox = mlx4_alloc_cmd_mailbox(dev);
872 if (IS_ERR(mailbox))
873 return PTR_ERR(mailbox);
874 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
875 pages = mailbox->buf;
876
877 for (mlx4_icm_first(icm, &iter);
878 !mlx4_icm_last(&iter);
879 mlx4_icm_next(&iter)) {
880 /*
881 * We have to pass pages that are aligned to their
882 * size, so find the least significant 1 in the
883 * address or size and use that as our log2 size.
884 */
885 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
886 if (lg < MLX4_ICM_PAGE_SHIFT) {
887 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
888 MLX4_ICM_PAGE_SIZE,
889 (unsigned long long) mlx4_icm_addr(&iter),
890 mlx4_icm_size(&iter));
891 err = -EINVAL;
892 goto out;
893 }
894
895 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
896 if (virt != -1) {
897 pages[nent * 2] = cpu_to_be64(virt);
898 virt += 1 << lg;
899 }
900
901 pages[nent * 2 + 1] =
902 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
903 (lg - MLX4_ICM_PAGE_SHIFT));
904 ts += 1 << (lg - 10);
905 ++tc;
906
907 if (++nent == MLX4_MAILBOX_SIZE / 16) {
908 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 909 MLX4_CMD_TIME_CLASS_B,
910 MLX4_CMD_NATIVE);
225c7b1f
RD		 911 if (err)
912 goto out;
913 nent = 0;
914 }
915 }
916 }
917
918 if (nent)
f9baff50
JM		 919 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
920 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 921 if (err)
922 goto out;
923
924 switch (op) {
925 case MLX4_CMD_MAP_FA:
926 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
927 break;
928 case MLX4_CMD_MAP_ICM_AUX:
929 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
930 break;
931 case MLX4_CMD_MAP_ICM:
932 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
933 tc, ts, (unsigned long long) virt - (ts << 10));
934 break;
935 }
936
937out:
938 mlx4_free_cmd_mailbox(dev, mailbox);
939 return err;
940}
941
942int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
943{
944 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
945}
946
947int mlx4_UNMAP_FA(struct mlx4_dev *dev)
948{
f9baff50
JM		 949 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
950 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 951}
952
953
954int mlx4_RUN_FW(struct mlx4_dev *dev)
955{
f9baff50
JM		 956 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
957 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 958}
959
960int mlx4_QUERY_FW(struct mlx4_dev *dev)
961{
962 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
963 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
964 struct mlx4_cmd_mailbox *mailbox;
965 u32 *outbox;
966 int err = 0;
967 u64 fw_ver;
fe40900f 968 u16 cmd_if_rev;
225c7b1f
RD		 969 u8 lg;
970
971#define QUERY_FW_OUT_SIZE 0x100
972#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 973#define QUERY_FW_PPF_ID 0x09
fe40900f 974#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 975#define QUERY_FW_MAX_CMD_OFFSET 0x0f
976#define QUERY_FW_ERR_START_OFFSET 0x30
977#define QUERY_FW_ERR_SIZE_OFFSET 0x38
978#define QUERY_FW_ERR_BAR_OFFSET 0x3c
979
980#define QUERY_FW_SIZE_OFFSET 0x00
981#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
982#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
983
5cc914f1
MA		 984#define QUERY_FW_COMM_BASE_OFFSET 0x40
985#define QUERY_FW_COMM_BAR_OFFSET 0x48
986
225c7b1f
RD		 987 mailbox = mlx4_alloc_cmd_mailbox(dev);
988 if (IS_ERR(mailbox))
989 return PTR_ERR(mailbox);
990 outbox = mailbox->buf;
991
992 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 993 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 994 if (err)
995 goto out;
996
997 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
998 /*
3e1db334 999 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1000 * version, so swap here.
1001 */
1002 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1003 ((fw_ver & 0xffff0000ull) >> 16) |
1004 ((fw_ver & 0x0000ffffull) << 16);
1005
752a50ca
JM		 1006 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1007 dev->caps.function = lg;
1008
b91cb3eb
JM		 1009 if (mlx4_is_slave(dev))
1010 goto out;
1011
5cc914f1 1012
fe40900f 1013 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1014 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1015 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 1016 mlx4_err(dev, "Installed FW has unsupported "
1017 "command interface revision %d.\n",
1018 cmd_if_rev);
1019 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1020 (int) (dev->caps.fw_ver >> 32),
1021 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1022 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 1023 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
1024 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1025 err = -ENODEV;
1026 goto out;
1027 }
1028
5ae2a7a8
RD		 1029 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1030 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1031
225c7b1f
RD		 1032 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1033 cmd->max_cmds = 1 << lg;
1034
fe40900f 1035 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1036 (int) (dev->caps.fw_ver >> 32),
1037 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1038 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1039 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1040
1041 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1042 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1043 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1044 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1045
1046 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1047 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1048
1049 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1050 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1051 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1052 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1053
5cc914f1
MA		 1054 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1055 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1056 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1057 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1058 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1059 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1060
1061 /*
1062 * Round up number of system pages needed in case
1063 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1064 */
1065 fw->fw_pages =
1066 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1067 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1068
1069 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1070 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1071
1072out:
1073 mlx4_free_cmd_mailbox(dev, mailbox);
1074 return err;
1075}
1076
b91cb3eb
JM		 1077int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1078 struct mlx4_vhcr *vhcr,
1079 struct mlx4_cmd_mailbox *inbox,
1080 struct mlx4_cmd_mailbox *outbox,
1081 struct mlx4_cmd_info *cmd)
1082{
1083 u8 *outbuf;
1084 int err;
1085
1086 outbuf = outbox->buf;
1087 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1088 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1089 if (err)
1090 return err;
1091
752a50ca
JM		 1092 /* for slaves, set pci PPF ID to invalid and zero out everything
1093 * else except FW version */
b91cb3eb
JM		 1094 outbuf[0] = outbuf[1] = 0;
1095 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1096 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1097
b91cb3eb
JM		 1098 return 0;
1099}
1100
225c7b1f
RD		 1101static void get_board_id(void *vsd, char *board_id)
1102{
1103 int i;
1104
1105#define VSD_OFFSET_SIG1 0x00
1106#define VSD_OFFSET_SIG2 0xde
1107#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1108#define VSD_OFFSET_TS_BOARD_ID 0x20
1109
1110#define VSD_SIGNATURE_TOPSPIN 0x5ad
1111
1112 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1113
1114 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1115 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1116 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1117 } else {
1118 /*
1119 * The board ID is a string but the firmware byte
1120 * swaps each 4-byte word before passing it back to
1121 * us. Therefore we need to swab it before printing.
1122 */
1123 for (i = 0; i < 4; ++i)
1124 ((u32 *) board_id)[i] =
1125 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1126 }
1127}
1128
1129int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1130{
1131 struct mlx4_cmd_mailbox *mailbox;
1132 u32 *outbox;
1133 int err;
1134
1135#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1136#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1137#define QUERY_ADAPTER_VSD_OFFSET 0x20
1138
1139 mailbox = mlx4_alloc_cmd_mailbox(dev);
1140 if (IS_ERR(mailbox))
1141 return PTR_ERR(mailbox);
1142 outbox = mailbox->buf;
1143
1144 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1145 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1146 if (err)
1147 goto out;
1148
225c7b1f
RD		 1149 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1150
1151 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1152 adapter->board_id);
1153
1154out:
1155 mlx4_free_cmd_mailbox(dev, mailbox);
1156 return err;
1157}
1158
1159int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1160{
1161 struct mlx4_cmd_mailbox *mailbox;
1162 __be32 *inbox;
1163 int err;
1164
1165#define INIT_HCA_IN_SIZE 0x200
1166#define INIT_HCA_VERSION_OFFSET 0x000
1167#define INIT_HCA_VERSION 2
c57e20dc 1168#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1169#define INIT_HCA_FLAGS_OFFSET 0x014
1170#define INIT_HCA_QPC_OFFSET 0x020
1171#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1172#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1173#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1174#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1175#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1176#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1177#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1178#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1179#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1180#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1181#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1182#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1183#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1184#define INIT_HCA_MCAST_OFFSET 0x0c0
1185#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1186#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1187#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1188#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1189#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1190#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1191#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1192#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1193#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1194#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1195#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1196#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1197#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1198#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1199#define INIT_HCA_TPT_OFFSET 0x0f0
1200#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1201#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1202#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1203#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1204#define INIT_HCA_UAR_OFFSET 0x120
1205#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1206#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1207
1208 mailbox = mlx4_alloc_cmd_mailbox(dev);
1209 if (IS_ERR(mailbox))
1210 return PTR_ERR(mailbox);
1211 inbox = mailbox->buf;
1212
1213 memset(inbox, 0, INIT_HCA_IN_SIZE);
1214
1215 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1216
c57e20dc
EC		 1217 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1218 (ilog2(cache_line_size()) - 4) << 5;
1219
225c7b1f
RD		 1220#if defined(__LITTLE_ENDIAN)
1221 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1222#elif defined(__BIG_ENDIAN)
1223 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1224#else
1225#error Host endianness not defined
1226#endif
1227 /* Check port for UD address vector: */
1228 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1229
8ff095ec
EC		 1230 /* Enable IPoIB checksumming if we can: */
1231 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1232 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1233
51f5f0ee
JM		 1234 /* Enable QoS support if module parameter set */
1235 if (enable_qos)
1236 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1237
f2a3f6a3
OG		 1238 /* enable counters */
1239 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1240 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1241
08ff3235
OG		 1242 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1243 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1244 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1245 dev->caps.eqe_size = 64;
1246 dev->caps.eqe_factor = 1;
1247 } else {
1248 dev->caps.eqe_size = 32;
1249 dev->caps.eqe_factor = 0;
1250 }
1251
1252 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1253 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1254 dev->caps.cqe_size = 64;
1255 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE;
1256 } else {
1257 dev->caps.cqe_size = 32;
1258 }
1259
225c7b1f
RD		 1260 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1261
1262 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1263 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1264 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1265 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1266 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1267 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1268 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1269 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1270 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1271 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1272 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1273 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1274
0ff1fb65
HHZ		 1275 /* steering attributes */
1276 if (dev->caps.steering_mode ==
1277 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1278 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1279 cpu_to_be32(1 <<
1280 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1281
1282 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1283 MLX4_PUT(inbox, param->log_mc_entry_sz,
1284 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1285 MLX4_PUT(inbox, param->log_mc_table_sz,
1286 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1287 /* Enable Ethernet flow steering
1288 * with udp unicast and tcp unicast
1289 */
1290 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1291 INIT_HCA_FS_ETH_BITS_OFFSET);
1292 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1293 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1294 /* Enable IPoIB flow steering
1295 * with udp unicast and tcp unicast
1296 */
1297 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1298 INIT_HCA_FS_IB_BITS_OFFSET);
1299 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1300 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1301 } else {
1302 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1303 MLX4_PUT(inbox, param->log_mc_entry_sz,
1304 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1305 MLX4_PUT(inbox, param->log_mc_hash_sz,
1306 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1307 MLX4_PUT(inbox, param->log_mc_table_sz,
1308 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1309 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1310 MLX4_PUT(inbox, (u8) (1 << 3),
1311 INIT_HCA_UC_STEERING_OFFSET);
1312 }
225c7b1f
RD		 1313
1314 /* TPT attributes */
1315
1316 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1317 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1318 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1319 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1320
1321 /* UAR attributes */
1322
ab9c17a0 1323 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1324 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1325
f9baff50
JM		 1326 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1327 MLX4_CMD_NATIVE);
225c7b1f
RD		 1328
1329 if (err)
1330 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1331
1332 mlx4_free_cmd_mailbox(dev, mailbox);
1333 return err;
1334}
1335
ab9c17a0
JM		 1336int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1337 struct mlx4_init_hca_param *param)
1338{
1339 struct mlx4_cmd_mailbox *mailbox;
1340 __be32 *outbox;
1341 int err;
08ff3235 1342 u8 byte_field;
ab9c17a0
JM		 1343
1344#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1345
1346 mailbox = mlx4_alloc_cmd_mailbox(dev);
1347 if (IS_ERR(mailbox))
1348 return PTR_ERR(mailbox);
1349 outbox = mailbox->buf;
1350
1351 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1352 MLX4_CMD_QUERY_HCA,
1353 MLX4_CMD_TIME_CLASS_B,
1354 !mlx4_is_slave(dev));
1355 if (err)
1356 goto out;
1357
1358 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1359
1360 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1361
1362 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1363 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1364 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1365 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1366 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1367 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1368 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1369 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1370 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1371 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1372 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1373 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1374
0ff1fb65
HHZ		 1375 /* steering attributes */
1376 if (dev->caps.steering_mode ==
1377 MLX4_STEERING_MODE_DEVICE_MANAGED) {
ab9c17a0 1378
0ff1fb65
HHZ		 1379 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1380 MLX4_GET(param->log_mc_entry_sz, outbox,
1381 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1382 MLX4_GET(param->log_mc_table_sz, outbox,
1383 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1384 } else {
1385 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1386 MLX4_GET(param->log_mc_entry_sz, outbox,
1387 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1388 MLX4_GET(param->log_mc_hash_sz, outbox,
1389 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1390 MLX4_GET(param->log_mc_table_sz, outbox,
1391 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1392 }
ab9c17a0 1393
08ff3235
OG		 1394 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1395 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1396 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1397 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1398 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1399 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1400
ab9c17a0
JM		 1401 /* TPT attributes */
1402
1403 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1404 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1405 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1406 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1407
1408 /* UAR attributes */
1409
1410 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1411 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1412
1413out:
1414 mlx4_free_cmd_mailbox(dev, mailbox);
1415
1416 return err;
1417}
1418
980e9001
JM		 1419/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1420 * and real QP0 are active, so that the paravirtualized QP0 is ready
1421 * to operate */
1422static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1423{
1424 struct mlx4_priv *priv = mlx4_priv(dev);
1425 /* irrelevant if not infiniband */
1426 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1427 priv->mfunc.master.qp0_state[port].qp0_active)
1428 return 1;
1429 return 0;
1430}
1431
5cc914f1
MA		 1432int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1433 struct mlx4_vhcr *vhcr,
1434 struct mlx4_cmd_mailbox *inbox,
1435 struct mlx4_cmd_mailbox *outbox,
1436 struct mlx4_cmd_info *cmd)
1437{
1438 struct mlx4_priv *priv = mlx4_priv(dev);
1439 int port = vhcr->in_modifier;
1440 int err;
1441
1442 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1443 return 0;
1444
980e9001
JM		 1445 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1446 /* Enable port only if it was previously disabled */
1447 if (!priv->mfunc.master.init_port_ref[port]) {
1448 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1449 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1450 if (err)
1451 return err;
1452 }
1453 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1454 } else {
1455 if (slave == mlx4_master_func_num(dev)) {
1456 if (check_qp0_state(dev, slave, port) &&
1457 !priv->mfunc.master.qp0_state[port].port_active) {
1458 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1459 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1460 if (err)
1461 return err;
1462 priv->mfunc.master.qp0_state[port].port_active = 1;
1463 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1464 }
1465 } else
1466 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1467 }
1468 ++priv->mfunc.master.init_port_ref[port];
1469 return 0;
1470}
1471
5ae2a7a8 1472int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1473{
1474 struct mlx4_cmd_mailbox *mailbox;
1475 u32 *inbox;
1476 int err;
1477 u32 flags;
5ae2a7a8 1478 u16 field;
225c7b1f 1479
5ae2a7a8 1480 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1481#define INIT_PORT_IN_SIZE 256
1482#define INIT_PORT_FLAGS_OFFSET 0x00
1483#define INIT_PORT_FLAG_SIG (1 << 18)
1484#define INIT_PORT_FLAG_NG (1 << 17)
1485#define INIT_PORT_FLAG_G0 (1 << 16)
1486#define INIT_PORT_VL_SHIFT 4
1487#define INIT_PORT_PORT_WIDTH_SHIFT 8
1488#define INIT_PORT_MTU_OFFSET 0x04
1489#define INIT_PORT_MAX_GID_OFFSET 0x06
1490#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1491#define INIT_PORT_GUID0_OFFSET 0x10
1492#define INIT_PORT_NODE_GUID_OFFSET 0x18
1493#define INIT_PORT_SI_GUID_OFFSET 0x20
1494
5ae2a7a8
RD		 1495 mailbox = mlx4_alloc_cmd_mailbox(dev);
1496 if (IS_ERR(mailbox))
1497 return PTR_ERR(mailbox);
1498 inbox = mailbox->buf;
225c7b1f 1499
5ae2a7a8 1500 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 1501
5ae2a7a8
RD		 1502 flags = 0;
1503 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1504 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1505 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1506
b79acb49 1507 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1508 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1509 field = dev->caps.gid_table_len[port];
1510 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1511 field = dev->caps.pkey_table_len[port];
1512 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1513
5ae2a7a8 1514 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1515 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1516
5ae2a7a8
RD		 1517 mlx4_free_cmd_mailbox(dev, mailbox);
1518 } else
1519 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1520 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1521
1522 return err;
1523}
1524EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1525
5cc914f1
MA		 1526int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1527 struct mlx4_vhcr *vhcr,
1528 struct mlx4_cmd_mailbox *inbox,
1529 struct mlx4_cmd_mailbox *outbox,
1530 struct mlx4_cmd_info *cmd)
1531{
1532 struct mlx4_priv *priv = mlx4_priv(dev);
1533 int port = vhcr->in_modifier;
1534 int err;
1535
1536 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1537 (1 << port)))
1538 return 0;
1539
980e9001
JM		 1540 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1541 if (priv->mfunc.master.init_port_ref[port] == 1) {
1542 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1543 1000, MLX4_CMD_NATIVE);
1544 if (err)
1545 return err;
1546 }
1547 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1548 } else {
1549 /* infiniband port */
1550 if (slave == mlx4_master_func_num(dev)) {
1551 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1552 priv->mfunc.master.qp0_state[port].port_active) {
1553 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1554 1000, MLX4_CMD_NATIVE);
1555 if (err)
1556 return err;
1557 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1558 priv->mfunc.master.qp0_state[port].port_active = 0;
1559 }
1560 } else
1561 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1562 }
5cc914f1
MA		 1563 --priv->mfunc.master.init_port_ref[port];
1564 return 0;
1565}
1566
225c7b1f
RD		 1567int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1568{
f9baff50
JM		 1569 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1570 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1571}
1572EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1573
1574int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1575{
f9baff50
JM		 1576 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1577 MLX4_CMD_NATIVE);
225c7b1f
RD		 1578}
1579
1580int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1581{
1582 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1583 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1584 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1585 if (ret)
1586 return ret;
1587
1588 /*
1589 * Round up number of system pages needed in case
1590 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1591 */
1592 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1593 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1594
1595 return 0;
1596}
1597
1598int mlx4_NOP(struct mlx4_dev *dev)
1599{
1600 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1601 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1602}
14c07b13
YP		 1603
1604#define MLX4_WOL_SETUP_MODE (5 << 28)
1605int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1606{
1607 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1608
1609 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1610 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1611 MLX4_CMD_NATIVE);
14c07b13
YP		 1612}
1613EXPORT_SYMBOL_GPL(mlx4_wol_read);
1614
1615int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1616{
1617 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1618
1619 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1620 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1621}
1622EXPORT_SYMBOL_GPL(mlx4_wol_write);
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