Commit | Line | Data |
---|---|---|
225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
5cc914f1 | 35 | #include <linux/etherdevice.h> |
225c7b1f | 36 | #include <linux/mlx4/cmd.h> |
9d9779e7 | 37 | #include <linux/module.h> |
c57e20dc | 38 | #include <linux/cache.h> |
225c7b1f RD |
39 | |
40 | #include "fw.h" | |
41 | #include "icm.h" | |
42 | ||
fe40900f | 43 | enum { |
5ae2a7a8 RD |
44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, | |
46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, | |
fe40900f RD |
47 | }; |
48 | ||
225c7b1f RD |
49 | extern void __buggy_use_of_MLX4_GET(void); |
50 | extern void __buggy_use_of_MLX4_PUT(void); | |
51 | ||
eb939922 | 52 | static bool enable_qos; |
51f5f0ee JM |
53 | module_param(enable_qos, bool, 0444); |
54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); | |
55 | ||
225c7b1f RD |
56 | #define MLX4_GET(dest, source, offset) \ |
57 | do { \ | |
58 | void *__p = (char *) (source) + (offset); \ | |
59 | switch (sizeof (dest)) { \ | |
60 | case 1: (dest) = *(u8 *) __p; break; \ | |
61 | case 2: (dest) = be16_to_cpup(__p); break; \ | |
62 | case 4: (dest) = be32_to_cpup(__p); break; \ | |
63 | case 8: (dest) = be64_to_cpup(__p); break; \ | |
64 | default: __buggy_use_of_MLX4_GET(); \ | |
65 | } \ | |
66 | } while (0) | |
67 | ||
68 | #define MLX4_PUT(dest, source, offset) \ | |
69 | do { \ | |
70 | void *__d = ((char *) (dest) + (offset)); \ | |
71 | switch (sizeof(source)) { \ | |
72 | case 1: *(u8 *) __d = (source); break; \ | |
73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ | |
74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ | |
75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ | |
76 | default: __buggy_use_of_MLX4_PUT(); \ | |
77 | } \ | |
78 | } while (0) | |
79 | ||
52eafc68 | 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
225c7b1f RD |
81 | { |
82 | static const char *fname[] = { | |
83 | [ 0] = "RC transport", | |
84 | [ 1] = "UC transport", | |
85 | [ 2] = "UD transport", | |
ea98054f | 86 | [ 3] = "XRC transport", |
225c7b1f RD |
87 | [ 4] = "reliable multicast", |
88 | [ 5] = "FCoIB support", | |
89 | [ 6] = "SRQ support", | |
90 | [ 7] = "IPoIB checksum offload", | |
91 | [ 8] = "P_Key violation counter", | |
92 | [ 9] = "Q_Key violation counter", | |
93 | [10] = "VMM", | |
7ff93f8b | 94 | [12] = "DPDP", |
417608c2 | 95 | [15] = "Big LSO headers", |
225c7b1f RD |
96 | [16] = "MW support", |
97 | [17] = "APM support", | |
98 | [18] = "Atomic ops support", | |
99 | [19] = "Raw multicast support", | |
100 | [20] = "Address vector port checking support", | |
101 | [21] = "UD multicast support", | |
102 | [24] = "Demand paging support", | |
96dfa684 | 103 | [25] = "Router support", |
ccf86321 OG |
104 | [30] = "IBoE support", |
105 | [32] = "Unicast loopback support", | |
f3a9d1f2 | 106 | [34] = "FCS header control", |
ccf86321 OG |
107 | [38] = "Wake On LAN support", |
108 | [40] = "UDP RSS support", | |
109 | [41] = "Unicast VEP steering support", | |
f2a3f6a3 OG |
110 | [42] = "Multicast VEP steering support", |
111 | [48] = "Counters support", | |
00f5ce99 | 112 | [59] = "Port management change event support", |
225c7b1f RD |
113 | }; |
114 | int i; | |
115 | ||
116 | mlx4_dbg(dev, "DEV_CAP flags:\n"); | |
23c15c21 | 117 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
52eafc68 | 118 | if (fname[i] && (flags & (1LL << i))) |
225c7b1f RD |
119 | mlx4_dbg(dev, " %s\n", fname[i]); |
120 | } | |
121 | ||
b3416f44 SP |
122 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
123 | { | |
124 | static const char * const fname[] = { | |
125 | [0] = "RSS support", | |
126 | [1] = "RSS Toeplitz Hash Function support", | |
0ff1fb65 HHZ |
127 | [2] = "RSS XOR Hash Function support", |
128 | [3] = "Device manage flow steering support" | |
b3416f44 SP |
129 | }; |
130 | int i; | |
131 | ||
132 | for (i = 0; i < ARRAY_SIZE(fname); ++i) | |
133 | if (fname[i] && (flags & (1LL << i))) | |
134 | mlx4_dbg(dev, " %s\n", fname[i]); | |
135 | } | |
136 | ||
2d928651 VS |
137 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
138 | { | |
139 | struct mlx4_cmd_mailbox *mailbox; | |
140 | u32 *inbox; | |
141 | int err = 0; | |
142 | ||
143 | #define MOD_STAT_CFG_IN_SIZE 0x100 | |
144 | ||
145 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 | |
146 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 | |
147 | ||
148 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
149 | if (IS_ERR(mailbox)) | |
150 | return PTR_ERR(mailbox); | |
151 | inbox = mailbox->buf; | |
152 | ||
153 | memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); | |
154 | ||
155 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); | |
156 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); | |
157 | ||
158 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 159 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
2d928651 VS |
160 | |
161 | mlx4_free_cmd_mailbox(dev, mailbox); | |
162 | return err; | |
163 | } | |
164 | ||
5cc914f1 MA |
165 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
166 | struct mlx4_vhcr *vhcr, | |
167 | struct mlx4_cmd_mailbox *inbox, | |
168 | struct mlx4_cmd_mailbox *outbox, | |
169 | struct mlx4_cmd_info *cmd) | |
170 | { | |
171 | u8 field; | |
172 | u32 size; | |
173 | int err = 0; | |
174 | ||
175 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 | |
176 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 | |
5cc914f1 | 177 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
105c320f | 178 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
5cc914f1 MA |
179 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 |
180 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 | |
181 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 | |
182 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 | |
183 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 | |
184 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 | |
185 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c | |
186 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30 | |
187 | ||
105c320f JM |
188 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
189 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 | |
190 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 | |
191 | ||
192 | /* when opcode modifier = 1 */ | |
5cc914f1 | 193 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
105c320f | 194 | #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 |
5cc914f1 MA |
195 | #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc |
196 | ||
47605df9 JM |
197 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
198 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 | |
199 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 | |
200 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c | |
201 | ||
105c320f JM |
202 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 |
203 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 | |
204 | ||
205 | #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 | |
206 | ||
5cc914f1 | 207 | if (vhcr->op_modifier == 1) { |
105c320f JM |
208 | field = 0; |
209 | /* ensure force vlan and force mac bits are not set */ | |
5cc914f1 | 210 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); |
105c320f JM |
211 | /* ensure that phy_wqe_gid bit is not set */ |
212 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); | |
213 | ||
47605df9 JM |
214 | field = vhcr->in_modifier; /* phys-port = logical-port */ |
215 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); | |
216 | ||
217 | /* size is now the QP number */ | |
218 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; | |
219 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); | |
220 | ||
221 | size += 2; | |
222 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); | |
223 | ||
224 | size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; | |
225 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); | |
226 | ||
227 | size += 2; | |
228 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); | |
229 | ||
5cc914f1 | 230 | } else if (vhcr->op_modifier == 0) { |
105c320f JM |
231 | /* enable rdma and ethernet interfaces */ |
232 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); | |
5cc914f1 MA |
233 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
234 | ||
5cc914f1 MA |
235 | field = dev->caps.num_ports; |
236 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); | |
237 | ||
105c320f | 238 | size = 0; /* no PF behaviour is set for now */ |
5cc914f1 MA |
239 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
240 | ||
105c320f JM |
241 | field = 0; /* protected FMR support not available as yet */ |
242 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); | |
243 | ||
5cc914f1 MA |
244 | size = dev->caps.num_qps; |
245 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); | |
246 | ||
247 | size = dev->caps.num_srqs; | |
248 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); | |
249 | ||
250 | size = dev->caps.num_cqs; | |
251 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); | |
252 | ||
253 | size = dev->caps.num_eqs; | |
254 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); | |
255 | ||
256 | size = dev->caps.reserved_eqs; | |
257 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); | |
258 | ||
259 | size = dev->caps.num_mpts; | |
260 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); | |
261 | ||
2b8fb286 | 262 | size = dev->caps.num_mtts; |
5cc914f1 MA |
263 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
264 | ||
265 | size = dev->caps.num_mgms + dev->caps.num_amgms; | |
266 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); | |
267 | ||
268 | } else | |
269 | err = -EINVAL; | |
270 | ||
271 | return err; | |
272 | } | |
273 | ||
47605df9 JM |
274 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, |
275 | struct mlx4_func_cap *func_cap) | |
5cc914f1 MA |
276 | { |
277 | struct mlx4_cmd_mailbox *mailbox; | |
278 | u32 *outbox; | |
47605df9 | 279 | u8 field, op_modifier; |
5cc914f1 | 280 | u32 size; |
5cc914f1 MA |
281 | int err = 0; |
282 | ||
47605df9 | 283 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
5cc914f1 MA |
284 | |
285 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
286 | if (IS_ERR(mailbox)) | |
287 | return PTR_ERR(mailbox); | |
288 | ||
47605df9 JM |
289 | err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, |
290 | MLX4_CMD_QUERY_FUNC_CAP, | |
5cc914f1 MA |
291 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
292 | if (err) | |
293 | goto out; | |
294 | ||
295 | outbox = mailbox->buf; | |
296 | ||
47605df9 JM |
297 | if (!op_modifier) { |
298 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); | |
299 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { | |
300 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); | |
301 | err = -EPROTONOSUPPORT; | |
302 | goto out; | |
303 | } | |
304 | func_cap->flags = field; | |
5cc914f1 | 305 | |
47605df9 JM |
306 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
307 | func_cap->num_ports = field; | |
5cc914f1 | 308 | |
47605df9 JM |
309 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
310 | func_cap->pf_context_behaviour = size; | |
5cc914f1 | 311 | |
47605df9 JM |
312 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
313 | func_cap->qp_quota = size & 0xFFFFFF; | |
5cc914f1 | 314 | |
47605df9 JM |
315 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
316 | func_cap->srq_quota = size & 0xFFFFFF; | |
5cc914f1 | 317 | |
47605df9 JM |
318 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
319 | func_cap->cq_quota = size & 0xFFFFFF; | |
5cc914f1 | 320 | |
47605df9 JM |
321 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
322 | func_cap->max_eq = size & 0xFFFFFF; | |
5cc914f1 | 323 | |
47605df9 JM |
324 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
325 | func_cap->reserved_eq = size & 0xFFFFFF; | |
5cc914f1 | 326 | |
47605df9 JM |
327 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
328 | func_cap->mpt_quota = size & 0xFFFFFF; | |
5cc914f1 | 329 | |
47605df9 JM |
330 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
331 | func_cap->mtt_quota = size & 0xFFFFFF; | |
5cc914f1 | 332 | |
47605df9 JM |
333 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
334 | func_cap->mcg_quota = size & 0xFFFFFF; | |
335 | goto out; | |
336 | } | |
e2c76824 | 337 | |
47605df9 JM |
338 | /* logical port query */ |
339 | if (gen_or_port > dev->caps.num_ports) { | |
340 | err = -EINVAL; | |
341 | goto out; | |
342 | } | |
e2c76824 | 343 | |
47605df9 JM |
344 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
345 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); | |
346 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { | |
347 | mlx4_err(dev, "VLAN is enforced on this port\n"); | |
348 | err = -EPROTONOSUPPORT; | |
5cc914f1 | 349 | goto out; |
47605df9 | 350 | } |
5cc914f1 | 351 | |
47605df9 JM |
352 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { |
353 | mlx4_err(dev, "Force mac is enabled on this port\n"); | |
354 | err = -EPROTONOSUPPORT; | |
355 | goto out; | |
5cc914f1 | 356 | } |
47605df9 JM |
357 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
358 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); | |
359 | if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { | |
360 | mlx4_err(dev, "phy_wqe_gid is " | |
361 | "enforced on this ib port\n"); | |
362 | err = -EPROTONOSUPPORT; | |
363 | goto out; | |
364 | } | |
365 | } | |
5cc914f1 | 366 | |
47605df9 JM |
367 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
368 | func_cap->physical_port = field; | |
369 | if (func_cap->physical_port != gen_or_port) { | |
370 | err = -ENOSYS; | |
371 | goto out; | |
5cc914f1 MA |
372 | } |
373 | ||
47605df9 JM |
374 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
375 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; | |
376 | ||
377 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); | |
378 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; | |
379 | ||
380 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); | |
381 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; | |
382 | ||
383 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); | |
384 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; | |
385 | ||
5cc914f1 MA |
386 | /* All other resources are allocated by the master, but we still report |
387 | * 'num' and 'reserved' capabilities as follows: | |
388 | * - num remains the maximum resource index | |
389 | * - 'num - reserved' is the total available objects of a resource, but | |
390 | * resource indices may be less than 'reserved' | |
391 | * TODO: set per-resource quotas */ | |
392 | ||
393 | out: | |
394 | mlx4_free_cmd_mailbox(dev, mailbox); | |
395 | ||
396 | return err; | |
397 | } | |
398 | ||
225c7b1f RD |
399 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
400 | { | |
401 | struct mlx4_cmd_mailbox *mailbox; | |
402 | u32 *outbox; | |
403 | u8 field; | |
ccf86321 | 404 | u32 field32, flags, ext_flags; |
225c7b1f RD |
405 | u16 size; |
406 | u16 stat_rate; | |
407 | int err; | |
5ae2a7a8 | 408 | int i; |
225c7b1f RD |
409 | |
410 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 | |
411 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 | |
412 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 | |
413 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 | |
414 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 | |
415 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 | |
416 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 | |
417 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 | |
418 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 | |
419 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 | |
420 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a | |
421 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b | |
422 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d | |
423 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e | |
424 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f | |
425 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 | |
426 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 | |
427 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 | |
428 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 | |
429 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 | |
430 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 | |
431 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b | |
b832be1e | 432 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
b3416f44 | 433 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
225c7b1f RD |
434 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
435 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 | |
436 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 | |
437 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 | |
438 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 | |
149983af | 439 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
225c7b1f RD |
440 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
441 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c | |
442 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f | |
ccf86321 | 443 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
225c7b1f RD |
444 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
445 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 | |
446 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 | |
447 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b | |
448 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c | |
449 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d | |
450 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e | |
451 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f | |
452 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 | |
453 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 | |
454 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 | |
455 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
456 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 | |
457 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 | |
458 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 | |
459 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 | |
460 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 | |
012a8ff5 SH |
461 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
462 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 | |
f2a3f6a3 | 463 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
0ff1fb65 HHZ |
464 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
465 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 | |
225c7b1f RD |
466 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
467 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 | |
468 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 | |
469 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 | |
470 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 | |
471 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a | |
472 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c | |
473 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e | |
474 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 | |
475 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 | |
95d04f07 | 476 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
225c7b1f RD |
477 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
478 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 | |
479 | ||
b3416f44 | 480 | dev_cap->flags2 = 0; |
225c7b1f RD |
481 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
482 | if (IS_ERR(mailbox)) | |
483 | return PTR_ERR(mailbox); | |
484 | outbox = mailbox->buf; | |
485 | ||
486 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
401453a3 | 487 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
488 | if (err) |
489 | goto out; | |
490 | ||
491 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); | |
492 | dev_cap->reserved_qps = 1 << (field & 0xf); | |
493 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); | |
494 | dev_cap->max_qps = 1 << (field & 0x1f); | |
495 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); | |
496 | dev_cap->reserved_srqs = 1 << (field >> 4); | |
497 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); | |
498 | dev_cap->max_srqs = 1 << (field & 0x1f); | |
499 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); | |
500 | dev_cap->max_cq_sz = 1 << field; | |
501 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); | |
502 | dev_cap->reserved_cqs = 1 << (field & 0xf); | |
503 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); | |
504 | dev_cap->max_cqs = 1 << (field & 0x1f); | |
505 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); | |
506 | dev_cap->max_mpts = 1 << (field & 0x3f); | |
507 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); | |
be504b0b | 508 | dev_cap->reserved_eqs = field & 0xf; |
225c7b1f | 509 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
5920869f | 510 | dev_cap->max_eqs = 1 << (field & 0xf); |
225c7b1f RD |
511 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
512 | dev_cap->reserved_mtts = 1 << (field >> 4); | |
513 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); | |
514 | dev_cap->max_mrw_sz = 1 << field; | |
515 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); | |
516 | dev_cap->reserved_mrws = 1 << (field & 0xf); | |
517 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); | |
518 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); | |
519 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); | |
520 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); | |
521 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); | |
522 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); | |
b832be1e EC |
523 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
524 | field &= 0x1f; | |
525 | if (!field) | |
526 | dev_cap->max_gso_sz = 0; | |
527 | else | |
528 | dev_cap->max_gso_sz = 1 << field; | |
529 | ||
b3416f44 SP |
530 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
531 | if (field & 0x20) | |
532 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; | |
533 | if (field & 0x10) | |
534 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; | |
535 | field &= 0xf; | |
536 | if (field) { | |
537 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; | |
538 | dev_cap->max_rss_tbl_sz = 1 << field; | |
539 | } else | |
540 | dev_cap->max_rss_tbl_sz = 0; | |
225c7b1f RD |
541 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
542 | dev_cap->max_rdma_global = 1 << (field & 0x3f); | |
543 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); | |
544 | dev_cap->local_ca_ack_delay = field & 0x1f; | |
225c7b1f | 545 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
225c7b1f | 546 | dev_cap->num_ports = field & 0xf; |
149983af DB |
547 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
548 | dev_cap->max_msg_sz = 1 << (field & 0x1f); | |
0ff1fb65 HHZ |
549 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
550 | if (field & 0x80) | |
551 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; | |
552 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; | |
553 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); | |
554 | dev_cap->fs_max_num_qp_per_entry = field; | |
225c7b1f RD |
555 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
556 | dev_cap->stat_rate_support = stat_rate; | |
ccf86321 | 557 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
52eafc68 | 558 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
ccf86321 | 559 | dev_cap->flags = flags | (u64)ext_flags << 32; |
225c7b1f RD |
560 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
561 | dev_cap->reserved_uars = field >> 4; | |
562 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); | |
563 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); | |
564 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); | |
565 | dev_cap->min_page_sz = 1 << field; | |
566 | ||
567 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); | |
568 | if (field & 0x80) { | |
569 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); | |
570 | dev_cap->bf_reg_size = 1 << (field & 0x1f); | |
571 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); | |
f5a49539 | 572 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
58d74bb1 | 573 | field = 3; |
225c7b1f RD |
574 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
575 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", | |
576 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); | |
577 | } else { | |
578 | dev_cap->bf_reg_size = 0; | |
579 | mlx4_dbg(dev, "BlueFlame not available\n"); | |
580 | } | |
581 | ||
582 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); | |
583 | dev_cap->max_sq_sg = field; | |
584 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); | |
585 | dev_cap->max_sq_desc_sz = size; | |
586 | ||
587 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); | |
588 | dev_cap->max_qp_per_mcg = 1 << field; | |
589 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); | |
590 | dev_cap->reserved_mgms = field & 0xf; | |
591 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); | |
592 | dev_cap->max_mcgs = 1 << field; | |
593 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); | |
594 | dev_cap->reserved_pds = field >> 4; | |
595 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
596 | dev_cap->max_pds = 1 << (field & 0x3f); | |
012a8ff5 SH |
597 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
598 | dev_cap->reserved_xrcds = field >> 4; | |
599 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
600 | dev_cap->max_xrcds = 1 << (field & 0x1f); | |
225c7b1f RD |
601 | |
602 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); | |
603 | dev_cap->rdmarc_entry_sz = size; | |
604 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); | |
605 | dev_cap->qpc_entry_sz = size; | |
606 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); | |
607 | dev_cap->aux_entry_sz = size; | |
608 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); | |
609 | dev_cap->altc_entry_sz = size; | |
610 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); | |
611 | dev_cap->eqc_entry_sz = size; | |
612 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); | |
613 | dev_cap->cqc_entry_sz = size; | |
614 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); | |
615 | dev_cap->srq_entry_sz = size; | |
616 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); | |
617 | dev_cap->cmpt_entry_sz = size; | |
618 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); | |
619 | dev_cap->mtt_entry_sz = size; | |
620 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); | |
621 | dev_cap->dmpt_entry_sz = size; | |
622 | ||
623 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); | |
624 | dev_cap->max_srq_sz = 1 << field; | |
625 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); | |
626 | dev_cap->max_qp_sz = 1 << field; | |
627 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); | |
628 | dev_cap->resize_srq = field & 1; | |
629 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); | |
630 | dev_cap->max_rq_sg = field; | |
631 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); | |
632 | dev_cap->max_rq_desc_sz = size; | |
633 | ||
634 | MLX4_GET(dev_cap->bmme_flags, outbox, | |
635 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
636 | MLX4_GET(dev_cap->reserved_lkey, outbox, | |
637 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); | |
638 | MLX4_GET(dev_cap->max_icm_sz, outbox, | |
639 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); | |
f2a3f6a3 OG |
640 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
641 | MLX4_GET(dev_cap->max_counters, outbox, | |
642 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); | |
225c7b1f | 643 | |
5ae2a7a8 RD |
644 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
645 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
646 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); | |
647 | dev_cap->max_vl[i] = field >> 4; | |
648 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); | |
b79acb49 | 649 | dev_cap->ib_mtu[i] = field >> 4; |
5ae2a7a8 RD |
650 | dev_cap->max_port_width[i] = field & 0xf; |
651 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); | |
652 | dev_cap->max_gids[i] = 1 << (field & 0xf); | |
653 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); | |
654 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
655 | } | |
656 | } else { | |
7ff93f8b | 657 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
5ae2a7a8 | 658 | #define QUERY_PORT_MTU_OFFSET 0x01 |
b79acb49 | 659 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
5ae2a7a8 RD |
660 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
661 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 | |
93fc9e1b | 662 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
5ae2a7a8 | 663 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
e65b9591 | 664 | #define QUERY_PORT_MAC_OFFSET 0x10 |
7699517d YP |
665 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
666 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c | |
667 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 | |
5ae2a7a8 RD |
668 | |
669 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
670 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, | |
401453a3 | 671 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
5ae2a7a8 RD |
672 | if (err) |
673 | goto out; | |
674 | ||
7ff93f8b YP |
675 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
676 | dev_cap->supported_port_types[i] = field & 3; | |
8d0fc7b6 YP |
677 | dev_cap->suggested_type[i] = (field >> 3) & 1; |
678 | dev_cap->default_sense[i] = (field >> 4) & 1; | |
5ae2a7a8 | 679 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
b79acb49 | 680 | dev_cap->ib_mtu[i] = field & 0xf; |
5ae2a7a8 RD |
681 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
682 | dev_cap->max_port_width[i] = field & 0xf; | |
683 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); | |
684 | dev_cap->max_gids[i] = 1 << (field >> 4); | |
685 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
686 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); | |
687 | dev_cap->max_vl[i] = field & 0xf; | |
93fc9e1b YP |
688 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
689 | dev_cap->log_max_macs[i] = field & 0xf; | |
690 | dev_cap->log_max_vlans[i] = field >> 4; | |
b79acb49 YP |
691 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
692 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); | |
7699517d YP |
693 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
694 | dev_cap->trans_type[i] = field32 >> 24; | |
695 | dev_cap->vendor_oui[i] = field32 & 0xffffff; | |
696 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); | |
697 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); | |
5ae2a7a8 RD |
698 | } |
699 | } | |
700 | ||
95d04f07 RD |
701 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
702 | dev_cap->bmme_flags, dev_cap->reserved_lkey); | |
225c7b1f RD |
703 | |
704 | /* | |
705 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then | |
706 | * we can't use any EQs whose doorbell falls on that page, | |
707 | * even if the EQ itself isn't reserved. | |
708 | */ | |
709 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, | |
710 | dev_cap->reserved_eqs); | |
711 | ||
712 | mlx4_dbg(dev, "Max ICM size %lld MB\n", | |
713 | (unsigned long long) dev_cap->max_icm_sz >> 20); | |
714 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", | |
715 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); | |
716 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
717 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); | |
718 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
719 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); | |
720 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
721 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); | |
722 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
723 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); | |
724 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
725 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); | |
726 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
727 | dev_cap->max_pds, dev_cap->reserved_mgms); | |
728 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
729 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); | |
730 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", | |
b79acb49 | 731 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
5ae2a7a8 | 732 | dev_cap->max_port_width[1]); |
225c7b1f RD |
733 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
734 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); | |
735 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", | |
736 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); | |
b832be1e | 737 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
f2a3f6a3 | 738 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
b3416f44 | 739 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
225c7b1f RD |
740 | |
741 | dump_dev_cap_flags(dev, dev_cap->flags); | |
b3416f44 | 742 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
225c7b1f RD |
743 | |
744 | out: | |
745 | mlx4_free_cmd_mailbox(dev, mailbox); | |
746 | return err; | |
747 | } | |
748 | ||
b91cb3eb JM |
749 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
750 | struct mlx4_vhcr *vhcr, | |
751 | struct mlx4_cmd_mailbox *inbox, | |
752 | struct mlx4_cmd_mailbox *outbox, | |
753 | struct mlx4_cmd_info *cmd) | |
754 | { | |
2a4fae14 | 755 | u64 flags; |
b91cb3eb JM |
756 | int err = 0; |
757 | u8 field; | |
758 | ||
759 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
760 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
761 | if (err) | |
762 | return err; | |
763 | ||
2a4fae14 JM |
764 | /* add port mng change event capability unconditionally to slaves */ |
765 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); | |
766 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; | |
767 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); | |
768 | ||
b91cb3eb JM |
769 | /* For guests, report Blueflame disabled */ |
770 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); | |
771 | field &= 0x7f; | |
772 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); | |
773 | ||
774 | return 0; | |
775 | } | |
776 | ||
5cc914f1 MA |
777 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
778 | struct mlx4_vhcr *vhcr, | |
779 | struct mlx4_cmd_mailbox *inbox, | |
780 | struct mlx4_cmd_mailbox *outbox, | |
781 | struct mlx4_cmd_info *cmd) | |
782 | { | |
783 | u64 def_mac; | |
784 | u8 port_type; | |
6634961c | 785 | u16 short_field; |
5cc914f1 MA |
786 | int err; |
787 | ||
105c320f | 788 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
6634961c JM |
789 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
790 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e | |
95f56e7a | 791 | |
5cc914f1 MA |
792 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
793 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
794 | MLX4_CMD_NATIVE); | |
795 | ||
796 | if (!err && dev->caps.function != slave) { | |
797 | /* set slave default_mac address */ | |
798 | MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); | |
799 | def_mac += slave << 8; | |
800 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); | |
801 | ||
802 | /* get port type - currently only eth is enabled */ | |
803 | MLX4_GET(port_type, outbox->buf, | |
804 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
805 | ||
105c320f JM |
806 | /* No link sensing allowed */ |
807 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; | |
808 | /* set port type to currently operating port type */ | |
809 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); | |
5cc914f1 MA |
810 | |
811 | MLX4_PUT(outbox->buf, port_type, | |
812 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
6634961c JM |
813 | |
814 | short_field = 1; /* slave max gids */ | |
815 | MLX4_PUT(outbox->buf, short_field, | |
816 | QUERY_PORT_CUR_MAX_GID_OFFSET); | |
817 | ||
818 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; | |
819 | MLX4_PUT(outbox->buf, short_field, | |
820 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); | |
5cc914f1 MA |
821 | } |
822 | ||
823 | return err; | |
824 | } | |
825 | ||
6634961c JM |
826 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
827 | int *gid_tbl_len, int *pkey_tbl_len) | |
828 | { | |
829 | struct mlx4_cmd_mailbox *mailbox; | |
830 | u32 *outbox; | |
831 | u16 field; | |
832 | int err; | |
833 | ||
834 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
835 | if (IS_ERR(mailbox)) | |
836 | return PTR_ERR(mailbox); | |
837 | ||
838 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, | |
839 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
840 | MLX4_CMD_WRAPPED); | |
841 | if (err) | |
842 | goto out; | |
843 | ||
844 | outbox = mailbox->buf; | |
845 | ||
846 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); | |
847 | *gid_tbl_len = field; | |
848 | ||
849 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); | |
850 | *pkey_tbl_len = field; | |
851 | ||
852 | out: | |
853 | mlx4_free_cmd_mailbox(dev, mailbox); | |
854 | return err; | |
855 | } | |
856 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); | |
857 | ||
225c7b1f RD |
858 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
859 | { | |
860 | struct mlx4_cmd_mailbox *mailbox; | |
861 | struct mlx4_icm_iter iter; | |
862 | __be64 *pages; | |
863 | int lg; | |
864 | int nent = 0; | |
865 | int i; | |
866 | int err = 0; | |
867 | int ts = 0, tc = 0; | |
868 | ||
869 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
870 | if (IS_ERR(mailbox)) | |
871 | return PTR_ERR(mailbox); | |
872 | memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); | |
873 | pages = mailbox->buf; | |
874 | ||
875 | for (mlx4_icm_first(icm, &iter); | |
876 | !mlx4_icm_last(&iter); | |
877 | mlx4_icm_next(&iter)) { | |
878 | /* | |
879 | * We have to pass pages that are aligned to their | |
880 | * size, so find the least significant 1 in the | |
881 | * address or size and use that as our log2 size. | |
882 | */ | |
883 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; | |
884 | if (lg < MLX4_ICM_PAGE_SHIFT) { | |
885 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
886 | MLX4_ICM_PAGE_SIZE, | |
887 | (unsigned long long) mlx4_icm_addr(&iter), | |
888 | mlx4_icm_size(&iter)); | |
889 | err = -EINVAL; | |
890 | goto out; | |
891 | } | |
892 | ||
893 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { | |
894 | if (virt != -1) { | |
895 | pages[nent * 2] = cpu_to_be64(virt); | |
896 | virt += 1 << lg; | |
897 | } | |
898 | ||
899 | pages[nent * 2 + 1] = | |
900 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | | |
901 | (lg - MLX4_ICM_PAGE_SHIFT)); | |
902 | ts += 1 << (lg - 10); | |
903 | ++tc; | |
904 | ||
905 | if (++nent == MLX4_MAILBOX_SIZE / 16) { | |
906 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, | |
f9baff50 JM |
907 | MLX4_CMD_TIME_CLASS_B, |
908 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
909 | if (err) |
910 | goto out; | |
911 | nent = 0; | |
912 | } | |
913 | } | |
914 | } | |
915 | ||
916 | if (nent) | |
f9baff50 JM |
917 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
918 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
919 | if (err) |
920 | goto out; | |
921 | ||
922 | switch (op) { | |
923 | case MLX4_CMD_MAP_FA: | |
924 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
925 | break; | |
926 | case MLX4_CMD_MAP_ICM_AUX: | |
927 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
928 | break; | |
929 | case MLX4_CMD_MAP_ICM: | |
930 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
931 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
932 | break; | |
933 | } | |
934 | ||
935 | out: | |
936 | mlx4_free_cmd_mailbox(dev, mailbox); | |
937 | return err; | |
938 | } | |
939 | ||
940 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) | |
941 | { | |
942 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); | |
943 | } | |
944 | ||
945 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) | |
946 | { | |
f9baff50 JM |
947 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
948 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
949 | } |
950 | ||
951 | ||
952 | int mlx4_RUN_FW(struct mlx4_dev *dev) | |
953 | { | |
f9baff50 JM |
954 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
955 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
225c7b1f RD |
956 | } |
957 | ||
958 | int mlx4_QUERY_FW(struct mlx4_dev *dev) | |
959 | { | |
960 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; | |
961 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
962 | struct mlx4_cmd_mailbox *mailbox; | |
963 | u32 *outbox; | |
964 | int err = 0; | |
965 | u64 fw_ver; | |
fe40900f | 966 | u16 cmd_if_rev; |
225c7b1f RD |
967 | u8 lg; |
968 | ||
969 | #define QUERY_FW_OUT_SIZE 0x100 | |
970 | #define QUERY_FW_VER_OFFSET 0x00 | |
5cc914f1 | 971 | #define QUERY_FW_PPF_ID 0x09 |
fe40900f | 972 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
225c7b1f RD |
973 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
974 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
975 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
976 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c | |
977 | ||
978 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
979 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
980 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 | |
981 | ||
5cc914f1 MA |
982 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
983 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 | |
984 | ||
225c7b1f RD |
985 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
986 | if (IS_ERR(mailbox)) | |
987 | return PTR_ERR(mailbox); | |
988 | outbox = mailbox->buf; | |
989 | ||
990 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
f9baff50 | 991 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
992 | if (err) |
993 | goto out; | |
994 | ||
995 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
996 | /* | |
3e1db334 | 997 | * FW subminor version is at more significant bits than minor |
225c7b1f RD |
998 | * version, so swap here. |
999 | */ | |
1000 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | | |
1001 | ((fw_ver & 0xffff0000ull) >> 16) | | |
1002 | ((fw_ver & 0x0000ffffull) << 16); | |
1003 | ||
752a50ca JM |
1004 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
1005 | dev->caps.function = lg; | |
1006 | ||
b91cb3eb JM |
1007 | if (mlx4_is_slave(dev)) |
1008 | goto out; | |
1009 | ||
5cc914f1 | 1010 | |
fe40900f | 1011 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
5ae2a7a8 RD |
1012 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
1013 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { | |
fe40900f RD |
1014 | mlx4_err(dev, "Installed FW has unsupported " |
1015 | "command interface revision %d.\n", | |
1016 | cmd_if_rev); | |
1017 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", | |
1018 | (int) (dev->caps.fw_ver >> 32), | |
1019 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
1020 | (int) dev->caps.fw_ver & 0xffff); | |
5ae2a7a8 RD |
1021 | mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", |
1022 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); | |
fe40900f RD |
1023 | err = -ENODEV; |
1024 | goto out; | |
1025 | } | |
1026 | ||
5ae2a7a8 RD |
1027 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
1028 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; | |
1029 | ||
225c7b1f RD |
1030 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
1031 | cmd->max_cmds = 1 << lg; | |
1032 | ||
fe40900f | 1033 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
225c7b1f RD |
1034 | (int) (dev->caps.fw_ver >> 32), |
1035 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
1036 | (int) dev->caps.fw_ver & 0xffff, | |
fe40900f | 1037 | cmd_if_rev, cmd->max_cmds); |
225c7b1f RD |
1038 | |
1039 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); | |
1040 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
1041 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); | |
1042 | fw->catas_bar = (fw->catas_bar >> 6) * 2; | |
1043 | ||
1044 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", | |
1045 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); | |
1046 | ||
1047 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); | |
1048 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
1049 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); | |
1050 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; | |
1051 | ||
5cc914f1 MA |
1052 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
1053 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); | |
1054 | fw->comm_bar = (fw->comm_bar >> 6) * 2; | |
1055 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", | |
1056 | fw->comm_bar, fw->comm_base); | |
225c7b1f RD |
1057 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
1058 | ||
1059 | /* | |
1060 | * Round up number of system pages needed in case | |
1061 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1062 | */ | |
1063 | fw->fw_pages = | |
1064 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1065 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1066 | ||
1067 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", | |
1068 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); | |
1069 | ||
1070 | out: | |
1071 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1072 | return err; | |
1073 | } | |
1074 | ||
b91cb3eb JM |
1075 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
1076 | struct mlx4_vhcr *vhcr, | |
1077 | struct mlx4_cmd_mailbox *inbox, | |
1078 | struct mlx4_cmd_mailbox *outbox, | |
1079 | struct mlx4_cmd_info *cmd) | |
1080 | { | |
1081 | u8 *outbuf; | |
1082 | int err; | |
1083 | ||
1084 | outbuf = outbox->buf; | |
1085 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
1086 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1087 | if (err) | |
1088 | return err; | |
1089 | ||
752a50ca JM |
1090 | /* for slaves, set pci PPF ID to invalid and zero out everything |
1091 | * else except FW version */ | |
b91cb3eb JM |
1092 | outbuf[0] = outbuf[1] = 0; |
1093 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); | |
752a50ca JM |
1094 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
1095 | ||
b91cb3eb JM |
1096 | return 0; |
1097 | } | |
1098 | ||
225c7b1f RD |
1099 | static void get_board_id(void *vsd, char *board_id) |
1100 | { | |
1101 | int i; | |
1102 | ||
1103 | #define VSD_OFFSET_SIG1 0x00 | |
1104 | #define VSD_OFFSET_SIG2 0xde | |
1105 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
1106 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
1107 | ||
1108 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
1109 | ||
1110 | memset(board_id, 0, MLX4_BOARD_ID_LEN); | |
1111 | ||
1112 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
1113 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
1114 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); | |
1115 | } else { | |
1116 | /* | |
1117 | * The board ID is a string but the firmware byte | |
1118 | * swaps each 4-byte word before passing it back to | |
1119 | * us. Therefore we need to swab it before printing. | |
1120 | */ | |
1121 | for (i = 0; i < 4; ++i) | |
1122 | ((u32 *) board_id)[i] = | |
1123 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
1124 | } | |
1125 | } | |
1126 | ||
1127 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) | |
1128 | { | |
1129 | struct mlx4_cmd_mailbox *mailbox; | |
1130 | u32 *outbox; | |
1131 | int err; | |
1132 | ||
1133 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
225c7b1f RD |
1134 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
1135 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 | |
1136 | ||
1137 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1138 | if (IS_ERR(mailbox)) | |
1139 | return PTR_ERR(mailbox); | |
1140 | outbox = mailbox->buf; | |
1141 | ||
1142 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, | |
f9baff50 | 1143 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1144 | if (err) |
1145 | goto out; | |
1146 | ||
225c7b1f RD |
1147 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
1148 | ||
1149 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, | |
1150 | adapter->board_id); | |
1151 | ||
1152 | out: | |
1153 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1154 | return err; | |
1155 | } | |
1156 | ||
1157 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) | |
1158 | { | |
1159 | struct mlx4_cmd_mailbox *mailbox; | |
1160 | __be32 *inbox; | |
1161 | int err; | |
1162 | ||
1163 | #define INIT_HCA_IN_SIZE 0x200 | |
1164 | #define INIT_HCA_VERSION_OFFSET 0x000 | |
1165 | #define INIT_HCA_VERSION 2 | |
c57e20dc | 1166 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
225c7b1f RD |
1167 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
1168 | #define INIT_HCA_QPC_OFFSET 0x020 | |
1169 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
1170 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
1171 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
1172 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
1173 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
1174 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
5cc914f1 | 1175 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
225c7b1f RD |
1176 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
1177 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
1178 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
1179 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
1180 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
1181 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) | |
1182 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
1183 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
1184 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
1185 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1679200f | 1186 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
225c7b1f | 1187 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
0ff1fb65 HHZ |
1188 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
1189 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 | |
1190 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) | |
1191 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) | |
1192 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) | |
1193 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) | |
1194 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) | |
1195 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) | |
1196 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) | |
225c7b1f RD |
1197 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
1198 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
1199 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) | |
1200 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1201 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) | |
1202 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1203 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1204 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1205 | ||
1206 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1207 | if (IS_ERR(mailbox)) | |
1208 | return PTR_ERR(mailbox); | |
1209 | inbox = mailbox->buf; | |
1210 | ||
1211 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1212 | ||
1213 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; | |
1214 | ||
c57e20dc EC |
1215 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
1216 | (ilog2(cache_line_size()) - 4) << 5; | |
1217 | ||
225c7b1f RD |
1218 | #if defined(__LITTLE_ENDIAN) |
1219 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); | |
1220 | #elif defined(__BIG_ENDIAN) | |
1221 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); | |
1222 | #else | |
1223 | #error Host endianness not defined | |
1224 | #endif | |
1225 | /* Check port for UD address vector: */ | |
1226 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); | |
1227 | ||
8ff095ec EC |
1228 | /* Enable IPoIB checksumming if we can: */ |
1229 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) | |
1230 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); | |
1231 | ||
51f5f0ee JM |
1232 | /* Enable QoS support if module parameter set */ |
1233 | if (enable_qos) | |
1234 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); | |
1235 | ||
f2a3f6a3 OG |
1236 | /* enable counters */ |
1237 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) | |
1238 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); | |
1239 | ||
225c7b1f RD |
1240 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
1241 | ||
1242 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1243 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1244 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1245 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1246 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1247 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1248 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); | |
1249 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); | |
1250 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1251 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1252 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); | |
1253 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); | |
1254 | ||
0ff1fb65 HHZ |
1255 | /* steering attributes */ |
1256 | if (dev->caps.steering_mode == | |
1257 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1258 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= | |
1259 | cpu_to_be32(1 << | |
1260 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); | |
1261 | ||
1262 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); | |
1263 | MLX4_PUT(inbox, param->log_mc_entry_sz, | |
1264 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); | |
1265 | MLX4_PUT(inbox, param->log_mc_table_sz, | |
1266 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); | |
1267 | /* Enable Ethernet flow steering | |
1268 | * with udp unicast and tcp unicast | |
1269 | */ | |
1270 | MLX4_PUT(inbox, param->fs_hash_enable_bits, | |
1271 | INIT_HCA_FS_ETH_BITS_OFFSET); | |
1272 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, | |
1273 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); | |
1274 | /* Enable IPoIB flow steering | |
1275 | * with udp unicast and tcp unicast | |
1276 | */ | |
1277 | MLX4_PUT(inbox, param->fs_hash_enable_bits, | |
1278 | INIT_HCA_FS_IB_BITS_OFFSET); | |
1279 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, | |
1280 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); | |
1281 | } else { | |
1282 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1283 | MLX4_PUT(inbox, param->log_mc_entry_sz, | |
1284 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1285 | MLX4_PUT(inbox, param->log_mc_hash_sz, | |
1286 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1287 | MLX4_PUT(inbox, param->log_mc_table_sz, | |
1288 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1289 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) | |
1290 | MLX4_PUT(inbox, (u8) (1 << 3), | |
1291 | INIT_HCA_UC_STEERING_OFFSET); | |
1292 | } | |
225c7b1f RD |
1293 | |
1294 | /* TPT attributes */ | |
1295 | ||
1296 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); | |
1297 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1298 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1299 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); | |
1300 | ||
1301 | /* UAR attributes */ | |
1302 | ||
ab9c17a0 | 1303 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
225c7b1f RD |
1304 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
1305 | ||
f9baff50 JM |
1306 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
1307 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1308 | |
1309 | if (err) | |
1310 | mlx4_err(dev, "INIT_HCA returns %d\n", err); | |
1311 | ||
1312 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1313 | return err; | |
1314 | } | |
1315 | ||
ab9c17a0 JM |
1316 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
1317 | struct mlx4_init_hca_param *param) | |
1318 | { | |
1319 | struct mlx4_cmd_mailbox *mailbox; | |
1320 | __be32 *outbox; | |
1321 | int err; | |
1322 | ||
1323 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 | |
1324 | ||
1325 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1326 | if (IS_ERR(mailbox)) | |
1327 | return PTR_ERR(mailbox); | |
1328 | outbox = mailbox->buf; | |
1329 | ||
1330 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, | |
1331 | MLX4_CMD_QUERY_HCA, | |
1332 | MLX4_CMD_TIME_CLASS_B, | |
1333 | !mlx4_is_slave(dev)); | |
1334 | if (err) | |
1335 | goto out; | |
1336 | ||
1337 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); | |
1338 | ||
1339 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ | |
1340 | ||
1341 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); | |
1342 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); | |
1343 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); | |
1344 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); | |
1345 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); | |
1346 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); | |
1347 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); | |
1348 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); | |
1349 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); | |
1350 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); | |
1351 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); | |
1352 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); | |
1353 | ||
0ff1fb65 HHZ |
1354 | /* steering attributes */ |
1355 | if (dev->caps.steering_mode == | |
1356 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
ab9c17a0 | 1357 | |
0ff1fb65 HHZ |
1358 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
1359 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1360 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); | |
1361 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1362 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); | |
1363 | } else { | |
1364 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); | |
1365 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1366 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1367 | MLX4_GET(param->log_mc_hash_sz, outbox, | |
1368 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1369 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1370 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1371 | } | |
ab9c17a0 JM |
1372 | |
1373 | /* TPT attributes */ | |
1374 | ||
1375 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); | |
1376 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1377 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); | |
1378 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); | |
1379 | ||
1380 | /* UAR attributes */ | |
1381 | ||
1382 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1383 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1384 | ||
1385 | out: | |
1386 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1387 | ||
1388 | return err; | |
1389 | } | |
1390 | ||
980e9001 JM |
1391 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
1392 | * and real QP0 are active, so that the paravirtualized QP0 is ready | |
1393 | * to operate */ | |
1394 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) | |
1395 | { | |
1396 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1397 | /* irrelevant if not infiniband */ | |
1398 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && | |
1399 | priv->mfunc.master.qp0_state[port].qp0_active) | |
1400 | return 1; | |
1401 | return 0; | |
1402 | } | |
1403 | ||
5cc914f1 MA |
1404 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1405 | struct mlx4_vhcr *vhcr, | |
1406 | struct mlx4_cmd_mailbox *inbox, | |
1407 | struct mlx4_cmd_mailbox *outbox, | |
1408 | struct mlx4_cmd_info *cmd) | |
1409 | { | |
1410 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1411 | int port = vhcr->in_modifier; | |
1412 | int err; | |
1413 | ||
1414 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) | |
1415 | return 0; | |
1416 | ||
980e9001 JM |
1417 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
1418 | /* Enable port only if it was previously disabled */ | |
1419 | if (!priv->mfunc.master.init_port_ref[port]) { | |
1420 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1421 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1422 | if (err) | |
1423 | return err; | |
1424 | } | |
1425 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
1426 | } else { | |
1427 | if (slave == mlx4_master_func_num(dev)) { | |
1428 | if (check_qp0_state(dev, slave, port) && | |
1429 | !priv->mfunc.master.qp0_state[port].port_active) { | |
1430 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1431 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1432 | if (err) | |
1433 | return err; | |
1434 | priv->mfunc.master.qp0_state[port].port_active = 1; | |
1435 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
1436 | } | |
1437 | } else | |
1438 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
5cc914f1 MA |
1439 | } |
1440 | ++priv->mfunc.master.init_port_ref[port]; | |
1441 | return 0; | |
1442 | } | |
1443 | ||
5ae2a7a8 | 1444 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
225c7b1f RD |
1445 | { |
1446 | struct mlx4_cmd_mailbox *mailbox; | |
1447 | u32 *inbox; | |
1448 | int err; | |
1449 | u32 flags; | |
5ae2a7a8 | 1450 | u16 field; |
225c7b1f | 1451 | |
5ae2a7a8 | 1452 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
225c7b1f RD |
1453 | #define INIT_PORT_IN_SIZE 256 |
1454 | #define INIT_PORT_FLAGS_OFFSET 0x00 | |
1455 | #define INIT_PORT_FLAG_SIG (1 << 18) | |
1456 | #define INIT_PORT_FLAG_NG (1 << 17) | |
1457 | #define INIT_PORT_FLAG_G0 (1 << 16) | |
1458 | #define INIT_PORT_VL_SHIFT 4 | |
1459 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 | |
1460 | #define INIT_PORT_MTU_OFFSET 0x04 | |
1461 | #define INIT_PORT_MAX_GID_OFFSET 0x06 | |
1462 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a | |
1463 | #define INIT_PORT_GUID0_OFFSET 0x10 | |
1464 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 | |
1465 | #define INIT_PORT_SI_GUID_OFFSET 0x20 | |
1466 | ||
5ae2a7a8 RD |
1467 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1468 | if (IS_ERR(mailbox)) | |
1469 | return PTR_ERR(mailbox); | |
1470 | inbox = mailbox->buf; | |
225c7b1f | 1471 | |
5ae2a7a8 | 1472 | memset(inbox, 0, INIT_PORT_IN_SIZE); |
225c7b1f | 1473 | |
5ae2a7a8 RD |
1474 | flags = 0; |
1475 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; | |
1476 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; | |
1477 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); | |
225c7b1f | 1478 | |
b79acb49 | 1479 | field = 128 << dev->caps.ib_mtu_cap[port]; |
5ae2a7a8 RD |
1480 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
1481 | field = dev->caps.gid_table_len[port]; | |
1482 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); | |
1483 | field = dev->caps.pkey_table_len[port]; | |
1484 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); | |
225c7b1f | 1485 | |
5ae2a7a8 | 1486 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
f9baff50 | 1487 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f | 1488 | |
5ae2a7a8 RD |
1489 | mlx4_free_cmd_mailbox(dev, mailbox); |
1490 | } else | |
1491 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
f9baff50 | 1492 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
225c7b1f RD |
1493 | |
1494 | return err; | |
1495 | } | |
1496 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); | |
1497 | ||
5cc914f1 MA |
1498 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1499 | struct mlx4_vhcr *vhcr, | |
1500 | struct mlx4_cmd_mailbox *inbox, | |
1501 | struct mlx4_cmd_mailbox *outbox, | |
1502 | struct mlx4_cmd_info *cmd) | |
1503 | { | |
1504 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1505 | int port = vhcr->in_modifier; | |
1506 | int err; | |
1507 | ||
1508 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & | |
1509 | (1 << port))) | |
1510 | return 0; | |
1511 | ||
980e9001 JM |
1512 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
1513 | if (priv->mfunc.master.init_port_ref[port] == 1) { | |
1514 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, | |
1515 | 1000, MLX4_CMD_NATIVE); | |
1516 | if (err) | |
1517 | return err; | |
1518 | } | |
1519 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1520 | } else { | |
1521 | /* infiniband port */ | |
1522 | if (slave == mlx4_master_func_num(dev)) { | |
1523 | if (!priv->mfunc.master.qp0_state[port].qp0_active && | |
1524 | priv->mfunc.master.qp0_state[port].port_active) { | |
1525 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, | |
1526 | 1000, MLX4_CMD_NATIVE); | |
1527 | if (err) | |
1528 | return err; | |
1529 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1530 | priv->mfunc.master.qp0_state[port].port_active = 0; | |
1531 | } | |
1532 | } else | |
1533 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
5cc914f1 | 1534 | } |
5cc914f1 MA |
1535 | --priv->mfunc.master.init_port_ref[port]; |
1536 | return 0; | |
1537 | } | |
1538 | ||
225c7b1f RD |
1539 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
1540 | { | |
f9baff50 JM |
1541 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
1542 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
1543 | } |
1544 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); | |
1545 | ||
1546 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) | |
1547 | { | |
f9baff50 JM |
1548 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
1549 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1550 | } |
1551 | ||
1552 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) | |
1553 | { | |
1554 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, | |
1555 | MLX4_CMD_SET_ICM_SIZE, | |
f9baff50 | 1556 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1557 | if (ret) |
1558 | return ret; | |
1559 | ||
1560 | /* | |
1561 | * Round up number of system pages needed in case | |
1562 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1563 | */ | |
1564 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1565 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1566 | ||
1567 | return 0; | |
1568 | } | |
1569 | ||
1570 | int mlx4_NOP(struct mlx4_dev *dev) | |
1571 | { | |
1572 | /* Input modifier of 0x1f means "finish as soon as possible." */ | |
f9baff50 | 1573 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
225c7b1f | 1574 | } |
14c07b13 YP |
1575 | |
1576 | #define MLX4_WOL_SETUP_MODE (5 << 28) | |
1577 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) | |
1578 | { | |
1579 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1580 | ||
1581 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, | |
f9baff50 JM |
1582 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
1583 | MLX4_CMD_NATIVE); | |
14c07b13 YP |
1584 | } |
1585 | EXPORT_SYMBOL_GPL(mlx4_wol_read); | |
1586 | ||
1587 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) | |
1588 | { | |
1589 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1590 | ||
1591 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 1592 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
14c07b13 YP |
1593 | } |
1594 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |