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IB/mlx4: Fill in sq_sig_type in query QP
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
7ff93f8b 94 [12] = "DPDP",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
00f5ce99 112 [59] = "Port management change event support",
225c7b1f
RD		 113 };
114 int i;
115
116 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 117 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 118 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 119 mlx4_dbg(dev, " %s\n", fname[i]);
120}
121
b3416f44
SP		 122static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
123{
124 static const char * const fname[] = {
125 [0] = "RSS support",
126 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65
HHZ		 127 [2] = "RSS XOR Hash Function support",
128 [3] = "Device manage flow steering support"
b3416f44
SP		 129 };
130 int i;
131
132 for (i = 0; i < ARRAY_SIZE(fname); ++i)
133 if (fname[i] && (flags & (1LL << i)))
134 mlx4_dbg(dev, " %s\n", fname[i]);
135}
136
2d928651
VS		 137int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
138{
139 struct mlx4_cmd_mailbox *mailbox;
140 u32 *inbox;
141 int err = 0;
142
143#define MOD_STAT_CFG_IN_SIZE 0x100
144
145#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
146#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
147
148 mailbox = mlx4_alloc_cmd_mailbox(dev);
149 if (IS_ERR(mailbox))
150 return PTR_ERR(mailbox);
151 inbox = mailbox->buf;
152
153 memset(inbox, 0, MOD_STAT_CFG_IN_SIZE);
154
155 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
156 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
157
158 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 159 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 160
161 mlx4_free_cmd_mailbox(dev, mailbox);
162 return err;
163}
164
5cc914f1
MA		 165int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
166 struct mlx4_vhcr *vhcr,
167 struct mlx4_cmd_mailbox *inbox,
168 struct mlx4_cmd_mailbox *outbox,
169 struct mlx4_cmd_info *cmd)
170{
171 u8 field;
172 u32 size;
173 int err = 0;
174
175#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
176#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 177#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 178#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
5cc914f1
MA		 179#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10
180#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14
181#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18
182#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20
183#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24
184#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28
185#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
186#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30
187
105c320f
JM		 188#define QUERY_FUNC_CAP_FMR_FLAG 0x80
189#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
190#define QUERY_FUNC_CAP_FLAG_ETH 0x80
191
192/* when opcode modifier = 1 */
5cc914f1 193#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
105c320f 194#define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8
5cc914f1
MA		 195#define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc
196
105c320f
JM		 197#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40
198#define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80
199
200#define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80
201
5cc914f1
MA		 202 if (vhcr->op_modifier == 1) {
203 field = vhcr->in_modifier;
204 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
205
105c320f
JM		 206 field = 0;
207 /* ensure force vlan and force mac bits are not set */
5cc914f1 208 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
105c320f
JM		 209 /* ensure that phy_wqe_gid bit is not set */
210 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
211
5cc914f1 212 } else if (vhcr->op_modifier == 0) {
105c320f
JM		 213 /* enable rdma and ethernet interfaces */
214 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA);
5cc914f1
MA		 215 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
216
5cc914f1
MA		 217 field = dev->caps.num_ports;
218 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
219
105c320f 220 size = 0; /* no PF behaviour is set for now */
5cc914f1
MA		 221 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
222
105c320f
JM		 223 field = 0; /* protected FMR support not available as yet */
224 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
225
5cc914f1
MA		 226 size = dev->caps.num_qps;
227 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
228
229 size = dev->caps.num_srqs;
230 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
231
232 size = dev->caps.num_cqs;
233 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
234
235 size = dev->caps.num_eqs;
236 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
237
238 size = dev->caps.reserved_eqs;
239 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
240
241 size = dev->caps.num_mpts;
242 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
243
2b8fb286 244 size = dev->caps.num_mtts;
5cc914f1
MA		 245 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
246
247 size = dev->caps.num_mgms + dev->caps.num_amgms;
248 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
249
250 } else
251 err = -EINVAL;
252
253 return err;
254}
255
256int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap)
257{
258 struct mlx4_cmd_mailbox *mailbox;
259 u32 *outbox;
260 u8 field;
261 u32 size;
262 int i;
263 int err = 0;
264
265
266 mailbox = mlx4_alloc_cmd_mailbox(dev);
267 if (IS_ERR(mailbox))
268 return PTR_ERR(mailbox);
269
270 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP,
271 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
272 if (err)
273 goto out;
274
275 outbox = mailbox->buf;
276
277 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
105c320f
JM		 278 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
279 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
5cc914f1
MA		 280 err = -EPROTONOSUPPORT;
281 goto out;
282 }
105c320f 283 func_cap->flags = field;
5cc914f1 284
5cc914f1
MA		 285 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
286 func_cap->num_ports = field;
287
288 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
289 func_cap->pf_context_behaviour = size;
290
291 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
292 func_cap->qp_quota = size & 0xFFFFFF;
293
294 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
295 func_cap->srq_quota = size & 0xFFFFFF;
296
297 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
298 func_cap->cq_quota = size & 0xFFFFFF;
299
300 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
301 func_cap->max_eq = size & 0xFFFFFF;
302
303 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
304 func_cap->reserved_eq = size & 0xFFFFFF;
305
306 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
307 func_cap->mpt_quota = size & 0xFFFFFF;
308
309 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
310 func_cap->mtt_quota = size & 0xFFFFFF;
311
312 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
313 func_cap->mcg_quota = size & 0xFFFFFF;
314
315 for (i = 1; i <= func_cap->num_ports; ++i) {
316 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1,
317 MLX4_CMD_QUERY_FUNC_CAP,
318 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
319 if (err)
320 goto out;
321
105c320f
JM		 322 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) {
323 MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET);
324 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) {
325 mlx4_err(dev, "VLAN is enforced on this port\n");
326 err = -EPROTONOSUPPORT;
327 goto out;
328 }
5cc914f1 329
105c320f
JM		 330 if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) {
331 mlx4_err(dev, "Force mac is enabled on this port\n");
332 err = -EPROTONOSUPPORT;
333 goto out;
334 }
335 } else if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB) {
336 MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET);
337 if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) {
338 mlx4_err(dev, "phy_wqe_gid is "
339 "enforced on this ib port\n");
340 err = -EPROTONOSUPPORT;
341 goto out;
342 }
5cc914f1
MA		 343 }
344
345 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
346 func_cap->physical_port[i] = field;
347 }
348
349 /* All other resources are allocated by the master, but we still report
350 * 'num' and 'reserved' capabilities as follows:
351 * - num remains the maximum resource index
352 * - 'num - reserved' is the total available objects of a resource, but
353 * resource indices may be less than 'reserved'
354 * TODO: set per-resource quotas */
355
356out:
357 mlx4_free_cmd_mailbox(dev, mailbox);
358
359 return err;
360}
361
225c7b1f
RD		 362int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
363{
364 struct mlx4_cmd_mailbox *mailbox;
365 u32 *outbox;
366 u8 field;
ccf86321 367 u32 field32, flags, ext_flags;
225c7b1f
RD		 368 u16 size;
369 u16 stat_rate;
370 int err;
5ae2a7a8 371 int i;
225c7b1f
RD		 372
373#define QUERY_DEV_CAP_OUT_SIZE 0x100
374#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
375#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
376#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
377#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
378#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
379#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
380#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
381#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
382#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
383#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
384#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
385#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
386#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
387#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
388#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
389#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
390#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
391#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
392#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
393#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
394#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 395#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 396#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 397#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
398#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
399#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
400#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
401#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 402#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 403#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
404#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
405#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 406#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 407#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
408#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
409#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
410#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
411#define QUERY_DEV_CAP_BF_OFFSET 0x4c
412#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
413#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
414#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
415#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
416#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
417#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
418#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
419#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
420#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
421#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
422#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
423#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 424#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
425#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 426#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
0ff1fb65
HHZ		 427#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
428#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
225c7b1f
RD		 429#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
430#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
431#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
432#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
433#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
434#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
435#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
436#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
437#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
438#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 439#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 440#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
441#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
442
b3416f44 443 dev_cap->flags2 = 0;
225c7b1f
RD		 444 mailbox = mlx4_alloc_cmd_mailbox(dev);
445 if (IS_ERR(mailbox))
446 return PTR_ERR(mailbox);
447 outbox = mailbox->buf;
448
449 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 450 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 451 if (err)
452 goto out;
453
454 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
455 dev_cap->reserved_qps = 1 << (field & 0xf);
456 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
457 dev_cap->max_qps = 1 << (field & 0x1f);
458 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
459 dev_cap->reserved_srqs = 1 << (field >> 4);
460 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
461 dev_cap->max_srqs = 1 << (field & 0x1f);
462 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
463 dev_cap->max_cq_sz = 1 << field;
464 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
465 dev_cap->reserved_cqs = 1 << (field & 0xf);
466 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
467 dev_cap->max_cqs = 1 << (field & 0x1f);
468 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
469 dev_cap->max_mpts = 1 << (field & 0x3f);
470 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 471 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 472 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 473 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 474 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
475 dev_cap->reserved_mtts = 1 << (field >> 4);
476 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
477 dev_cap->max_mrw_sz = 1 << field;
478 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
479 dev_cap->reserved_mrws = 1 << (field & 0xf);
480 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
481 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
482 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
483 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
484 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
485 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 486 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
487 field &= 0x1f;
488 if (!field)
489 dev_cap->max_gso_sz = 0;
490 else
491 dev_cap->max_gso_sz = 1 << field;
492
b3416f44
SP		 493 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
494 if (field & 0x20)
495 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
496 if (field & 0x10)
497 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
498 field &= 0xf;
499 if (field) {
500 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
501 dev_cap->max_rss_tbl_sz = 1 << field;
502 } else
503 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 504 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
505 dev_cap->max_rdma_global = 1 << (field & 0x3f);
506 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
507 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 508 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 509 dev_cap->num_ports = field & 0xf;
149983af
DB		 510 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
511 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 512 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
513 if (field & 0x80)
514 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
515 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
516 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
517 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 518 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
519 dev_cap->stat_rate_support = stat_rate;
ccf86321 520 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 521 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 522 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 523 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
524 dev_cap->reserved_uars = field >> 4;
525 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
526 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
527 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
528 dev_cap->min_page_sz = 1 << field;
529
530 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
531 if (field & 0x80) {
532 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
533 dev_cap->bf_reg_size = 1 << (field & 0x1f);
534 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 535 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 536 field = 3;
225c7b1f
RD		 537 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
538 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
539 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
540 } else {
541 dev_cap->bf_reg_size = 0;
542 mlx4_dbg(dev, "BlueFlame not available\n");
543 }
544
545 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
546 dev_cap->max_sq_sg = field;
547 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
548 dev_cap->max_sq_desc_sz = size;
549
550 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
551 dev_cap->max_qp_per_mcg = 1 << field;
552 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
553 dev_cap->reserved_mgms = field & 0xf;
554 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
555 dev_cap->max_mcgs = 1 << field;
556 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
557 dev_cap->reserved_pds = field >> 4;
558 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
559 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 560 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
561 dev_cap->reserved_xrcds = field >> 4;
562 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
563 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 564
565 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
566 dev_cap->rdmarc_entry_sz = size;
567 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
568 dev_cap->qpc_entry_sz = size;
569 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
570 dev_cap->aux_entry_sz = size;
571 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
572 dev_cap->altc_entry_sz = size;
573 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
574 dev_cap->eqc_entry_sz = size;
575 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
576 dev_cap->cqc_entry_sz = size;
577 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
578 dev_cap->srq_entry_sz = size;
579 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
580 dev_cap->cmpt_entry_sz = size;
581 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
582 dev_cap->mtt_entry_sz = size;
583 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
584 dev_cap->dmpt_entry_sz = size;
585
586 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
587 dev_cap->max_srq_sz = 1 << field;
588 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
589 dev_cap->max_qp_sz = 1 << field;
590 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
591 dev_cap->resize_srq = field & 1;
592 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
593 dev_cap->max_rq_sg = field;
594 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
595 dev_cap->max_rq_desc_sz = size;
596
597 MLX4_GET(dev_cap->bmme_flags, outbox,
598 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
599 MLX4_GET(dev_cap->reserved_lkey, outbox,
600 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
601 MLX4_GET(dev_cap->max_icm_sz, outbox,
602 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 603 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
604 MLX4_GET(dev_cap->max_counters, outbox,
605 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 606
5ae2a7a8
RD		 607 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
608 for (i = 1; i <= dev_cap->num_ports; ++i) {
609 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
610 dev_cap->max_vl[i] = field >> 4;
611 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 612 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 613 dev_cap->max_port_width[i] = field & 0xf;
614 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
615 dev_cap->max_gids[i] = 1 << (field & 0xf);
616 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
617 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
618 }
619 } else {
7ff93f8b 620#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 621#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 622#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 623#define QUERY_PORT_WIDTH_OFFSET 0x06
624#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 625#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 626#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 627#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 628#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
629#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
630#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 631
632 for (i = 1; i <= dev_cap->num_ports; ++i) {
633 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 634 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 635 if (err)
636 goto out;
637
7ff93f8b
YP		 638 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
639 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 640 dev_cap->suggested_type[i] = (field >> 3) & 1;
641 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 642 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 643 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 644 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
645 dev_cap->max_port_width[i] = field & 0xf;
646 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
647 dev_cap->max_gids[i] = 1 << (field >> 4);
648 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
649 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
650 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 651 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
652 dev_cap->log_max_macs[i] = field & 0xf;
653 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 654 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
655 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 656 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
657 dev_cap->trans_type[i] = field32 >> 24;
658 dev_cap->vendor_oui[i] = field32 & 0xffffff;
659 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
660 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 661 }
662 }
663
95d04f07
RD		 664 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
665 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 666
667 /*
668 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
669 * we can't use any EQs whose doorbell falls on that page,
670 * even if the EQ itself isn't reserved.
671 */
672 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
673 dev_cap->reserved_eqs);
674
675 mlx4_dbg(dev, "Max ICM size %lld MB\n",
676 (unsigned long long) dev_cap->max_icm_sz >> 20);
677 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
678 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
679 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
680 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
681 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
682 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
683 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
684 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
685 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
686 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
687 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
688 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
689 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
690 dev_cap->max_pds, dev_cap->reserved_mgms);
691 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
692 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
693 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 694 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 695 dev_cap->max_port_width[1]);
225c7b1f
RD		 696 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
697 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
698 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
699 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 700 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 701 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 702 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 703
704 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 705 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 706
707out:
708 mlx4_free_cmd_mailbox(dev, mailbox);
709 return err;
710}
711
b91cb3eb
JM		 712int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
713 struct mlx4_vhcr *vhcr,
714 struct mlx4_cmd_mailbox *inbox,
715 struct mlx4_cmd_mailbox *outbox,
716 struct mlx4_cmd_info *cmd)
717{
718 int err = 0;
719 u8 field;
720
721 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
722 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
723 if (err)
724 return err;
725
726 /* For guests, report Blueflame disabled */
727 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
728 field &= 0x7f;
729 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
730
731 return 0;
732}
733
5cc914f1
MA		 734int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
735 struct mlx4_vhcr *vhcr,
736 struct mlx4_cmd_mailbox *inbox,
737 struct mlx4_cmd_mailbox *outbox,
738 struct mlx4_cmd_info *cmd)
739{
740 u64 def_mac;
741 u8 port_type;
6634961c 742 u16 short_field;
5cc914f1
MA		 743 int err;
744
105c320f 745#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
6634961c
JM		 746#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
747#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 748
5cc914f1
MA		 749 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
750 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
751 MLX4_CMD_NATIVE);
752
753 if (!err && dev->caps.function != slave) {
754 /* set slave default_mac address */
755 MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
756 def_mac += slave << 8;
757 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
758
759 /* get port type - currently only eth is enabled */
760 MLX4_GET(port_type, outbox->buf,
761 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
762
105c320f
JM		 763 /* No link sensing allowed */
764 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
765 /* set port type to currently operating port type */
766 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1
MA		 767
768 MLX4_PUT(outbox->buf, port_type,
769 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c
JM		 770
771 short_field = 1; /* slave max gids */
772 MLX4_PUT(outbox->buf, short_field,
773 QUERY_PORT_CUR_MAX_GID_OFFSET);
774
775 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
776 MLX4_PUT(outbox->buf, short_field,
777 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 778 }
779
780 return err;
781}
782
6634961c
JM		 783int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
784 int *gid_tbl_len, int *pkey_tbl_len)
785{
786 struct mlx4_cmd_mailbox *mailbox;
787 u32 *outbox;
788 u16 field;
789 int err;
790
791 mailbox = mlx4_alloc_cmd_mailbox(dev);
792 if (IS_ERR(mailbox))
793 return PTR_ERR(mailbox);
794
795 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
796 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
797 MLX4_CMD_WRAPPED);
798 if (err)
799 goto out;
800
801 outbox = mailbox->buf;
802
803 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
804 *gid_tbl_len = field;
805
806 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
807 *pkey_tbl_len = field;
808
809out:
810 mlx4_free_cmd_mailbox(dev, mailbox);
811 return err;
812}
813EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
814
225c7b1f
RD		 815int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
816{
817 struct mlx4_cmd_mailbox *mailbox;
818 struct mlx4_icm_iter iter;
819 __be64 *pages;
820 int lg;
821 int nent = 0;
822 int i;
823 int err = 0;
824 int ts = 0, tc = 0;
825
826 mailbox = mlx4_alloc_cmd_mailbox(dev);
827 if (IS_ERR(mailbox))
828 return PTR_ERR(mailbox);
829 memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE);
830 pages = mailbox->buf;
831
832 for (mlx4_icm_first(icm, &iter);
833 !mlx4_icm_last(&iter);
834 mlx4_icm_next(&iter)) {
835 /*
836 * We have to pass pages that are aligned to their
837 * size, so find the least significant 1 in the
838 * address or size and use that as our log2 size.
839 */
840 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
841 if (lg < MLX4_ICM_PAGE_SHIFT) {
842 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n",
843 MLX4_ICM_PAGE_SIZE,
844 (unsigned long long) mlx4_icm_addr(&iter),
845 mlx4_icm_size(&iter));
846 err = -EINVAL;
847 goto out;
848 }
849
850 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
851 if (virt != -1) {
852 pages[nent * 2] = cpu_to_be64(virt);
853 virt += 1 << lg;
854 }
855
856 pages[nent * 2 + 1] =
857 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
858 (lg - MLX4_ICM_PAGE_SHIFT));
859 ts += 1 << (lg - 10);
860 ++tc;
861
862 if (++nent == MLX4_MAILBOX_SIZE / 16) {
863 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 864 MLX4_CMD_TIME_CLASS_B,
865 MLX4_CMD_NATIVE);
225c7b1f
RD		 866 if (err)
867 goto out;
868 nent = 0;
869 }
870 }
871 }
872
873 if (nent)
f9baff50
JM		 874 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
875 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 876 if (err)
877 goto out;
878
879 switch (op) {
880 case MLX4_CMD_MAP_FA:
881 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts);
882 break;
883 case MLX4_CMD_MAP_ICM_AUX:
884 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts);
885 break;
886 case MLX4_CMD_MAP_ICM:
887 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n",
888 tc, ts, (unsigned long long) virt - (ts << 10));
889 break;
890 }
891
892out:
893 mlx4_free_cmd_mailbox(dev, mailbox);
894 return err;
895}
896
897int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
898{
899 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
900}
901
902int mlx4_UNMAP_FA(struct mlx4_dev *dev)
903{
f9baff50
JM		 904 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
905 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 906}
907
908
909int mlx4_RUN_FW(struct mlx4_dev *dev)
910{
f9baff50
JM		 911 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
912 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 913}
914
915int mlx4_QUERY_FW(struct mlx4_dev *dev)
916{
917 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
918 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
919 struct mlx4_cmd_mailbox *mailbox;
920 u32 *outbox;
921 int err = 0;
922 u64 fw_ver;
fe40900f 923 u16 cmd_if_rev;
225c7b1f
RD		 924 u8 lg;
925
926#define QUERY_FW_OUT_SIZE 0x100
927#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 928#define QUERY_FW_PPF_ID 0x09
fe40900f 929#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 930#define QUERY_FW_MAX_CMD_OFFSET 0x0f
931#define QUERY_FW_ERR_START_OFFSET 0x30
932#define QUERY_FW_ERR_SIZE_OFFSET 0x38
933#define QUERY_FW_ERR_BAR_OFFSET 0x3c
934
935#define QUERY_FW_SIZE_OFFSET 0x00
936#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
937#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
938
5cc914f1
MA		 939#define QUERY_FW_COMM_BASE_OFFSET 0x40
940#define QUERY_FW_COMM_BAR_OFFSET 0x48
941
225c7b1f
RD		 942 mailbox = mlx4_alloc_cmd_mailbox(dev);
943 if (IS_ERR(mailbox))
944 return PTR_ERR(mailbox);
945 outbox = mailbox->buf;
946
947 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 948 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 949 if (err)
950 goto out;
951
952 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
953 /*
3e1db334 954 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 955 * version, so swap here.
956 */
957 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
958 ((fw_ver & 0xffff0000ull) >> 16) |
959 ((fw_ver & 0x0000ffffull) << 16);
960
752a50ca
JM		 961 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
962 dev->caps.function = lg;
963
b91cb3eb
JM		 964 if (mlx4_is_slave(dev))
965 goto out;
966
5cc914f1 967
fe40900f 968 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 969 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
970 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
fe40900f
RD		 971 mlx4_err(dev, "Installed FW has unsupported "
972 "command interface revision %d.\n",
973 cmd_if_rev);
974 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
975 (int) (dev->caps.fw_ver >> 32),
976 (int) (dev->caps.fw_ver >> 16) & 0xffff,
977 (int) dev->caps.fw_ver & 0xffff);
5ae2a7a8
RD		 978 mlx4_err(dev, "This driver version supports only revisions %d to %d.\n",
979 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 980 err = -ENODEV;
981 goto out;
982 }
983
5ae2a7a8
RD		 984 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
985 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
986
225c7b1f
RD		 987 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
988 cmd->max_cmds = 1 << lg;
989
fe40900f 990 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 991 (int) (dev->caps.fw_ver >> 32),
992 (int) (dev->caps.fw_ver >> 16) & 0xffff,
993 (int) dev->caps.fw_ver & 0xffff,
fe40900f 994 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 995
996 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
997 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
998 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
999 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1000
1001 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1002 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1003
1004 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1005 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1006 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1007 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1008
5cc914f1
MA		 1009 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1010 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1011 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1012 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1013 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1014 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1015
1016 /*
1017 * Round up number of system pages needed in case
1018 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1019 */
1020 fw->fw_pages =
1021 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1022 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1023
1024 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1025 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1026
1027out:
1028 mlx4_free_cmd_mailbox(dev, mailbox);
1029 return err;
1030}
1031
b91cb3eb
JM		 1032int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1033 struct mlx4_vhcr *vhcr,
1034 struct mlx4_cmd_mailbox *inbox,
1035 struct mlx4_cmd_mailbox *outbox,
1036 struct mlx4_cmd_info *cmd)
1037{
1038 u8 *outbuf;
1039 int err;
1040
1041 outbuf = outbox->buf;
1042 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1043 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1044 if (err)
1045 return err;
1046
752a50ca
JM		 1047 /* for slaves, set pci PPF ID to invalid and zero out everything
1048 * else except FW version */
b91cb3eb
JM		 1049 outbuf[0] = outbuf[1] = 0;
1050 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1051 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1052
b91cb3eb
JM		 1053 return 0;
1054}
1055
225c7b1f
RD		 1056static void get_board_id(void *vsd, char *board_id)
1057{
1058 int i;
1059
1060#define VSD_OFFSET_SIG1 0x00
1061#define VSD_OFFSET_SIG2 0xde
1062#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1063#define VSD_OFFSET_TS_BOARD_ID 0x20
1064
1065#define VSD_SIGNATURE_TOPSPIN 0x5ad
1066
1067 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1068
1069 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1070 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1071 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1072 } else {
1073 /*
1074 * The board ID is a string but the firmware byte
1075 * swaps each 4-byte word before passing it back to
1076 * us. Therefore we need to swab it before printing.
1077 */
1078 for (i = 0; i < 4; ++i)
1079 ((u32 *) board_id)[i] =
1080 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1081 }
1082}
1083
1084int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1085{
1086 struct mlx4_cmd_mailbox *mailbox;
1087 u32 *outbox;
1088 int err;
1089
1090#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1091#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1092#define QUERY_ADAPTER_VSD_OFFSET 0x20
1093
1094 mailbox = mlx4_alloc_cmd_mailbox(dev);
1095 if (IS_ERR(mailbox))
1096 return PTR_ERR(mailbox);
1097 outbox = mailbox->buf;
1098
1099 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1100 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1101 if (err)
1102 goto out;
1103
225c7b1f
RD		 1104 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1105
1106 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1107 adapter->board_id);
1108
1109out:
1110 mlx4_free_cmd_mailbox(dev, mailbox);
1111 return err;
1112}
1113
1114int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1115{
1116 struct mlx4_cmd_mailbox *mailbox;
1117 __be32 *inbox;
1118 int err;
1119
1120#define INIT_HCA_IN_SIZE 0x200
1121#define INIT_HCA_VERSION_OFFSET 0x000
1122#define INIT_HCA_VERSION 2
c57e20dc 1123#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1124#define INIT_HCA_FLAGS_OFFSET 0x014
1125#define INIT_HCA_QPC_OFFSET 0x020
1126#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1127#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1128#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1129#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1130#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1131#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1132#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
225c7b1f
RD		 1133#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1134#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1135#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1136#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1137#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1138#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1139#define INIT_HCA_MCAST_OFFSET 0x0c0
1140#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1141#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1142#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1143#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1144#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1145#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1146#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1147#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1148#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1149#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1150#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1151#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1152#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1153#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1154#define INIT_HCA_TPT_OFFSET 0x0f0
1155#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1156#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1157#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1158#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1159#define INIT_HCA_UAR_OFFSET 0x120
1160#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1161#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1162
1163 mailbox = mlx4_alloc_cmd_mailbox(dev);
1164 if (IS_ERR(mailbox))
1165 return PTR_ERR(mailbox);
1166 inbox = mailbox->buf;
1167
1168 memset(inbox, 0, INIT_HCA_IN_SIZE);
1169
1170 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1171
c57e20dc
EC		 1172 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1173 (ilog2(cache_line_size()) - 4) << 5;
1174
225c7b1f
RD		 1175#if defined(__LITTLE_ENDIAN)
1176 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1177#elif defined(__BIG_ENDIAN)
1178 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1179#else
1180#error Host endianness not defined
1181#endif
1182 /* Check port for UD address vector: */
1183 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1184
8ff095ec
EC		 1185 /* Enable IPoIB checksumming if we can: */
1186 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1187 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1188
51f5f0ee
JM		 1189 /* Enable QoS support if module parameter set */
1190 if (enable_qos)
1191 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1192
f2a3f6a3
OG		 1193 /* enable counters */
1194 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1195 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1196
225c7b1f
RD		 1197 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1198
1199 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1200 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1201 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1202 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1203 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1204 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1205 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1206 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1207 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1208 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1209 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1210 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1211
0ff1fb65
HHZ		 1212 /* steering attributes */
1213 if (dev->caps.steering_mode ==
1214 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1215 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1216 cpu_to_be32(1 <<
1217 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1218
1219 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1220 MLX4_PUT(inbox, param->log_mc_entry_sz,
1221 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1222 MLX4_PUT(inbox, param->log_mc_table_sz,
1223 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1224 /* Enable Ethernet flow steering
1225 * with udp unicast and tcp unicast
1226 */
1227 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1228 INIT_HCA_FS_ETH_BITS_OFFSET);
1229 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1230 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1231 /* Enable IPoIB flow steering
1232 * with udp unicast and tcp unicast
1233 */
1234 MLX4_PUT(inbox, param->fs_hash_enable_bits,
1235 INIT_HCA_FS_IB_BITS_OFFSET);
1236 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1237 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1238 } else {
1239 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1240 MLX4_PUT(inbox, param->log_mc_entry_sz,
1241 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1242 MLX4_PUT(inbox, param->log_mc_hash_sz,
1243 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1244 MLX4_PUT(inbox, param->log_mc_table_sz,
1245 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1246 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1247 MLX4_PUT(inbox, (u8) (1 << 3),
1248 INIT_HCA_UC_STEERING_OFFSET);
1249 }
225c7b1f
RD		 1250
1251 /* TPT attributes */
1252
1253 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
1254 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1255 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1256 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1257
1258 /* UAR attributes */
1259
ab9c17a0 1260 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1261 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1262
f9baff50
JM		 1263 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1264 MLX4_CMD_NATIVE);
225c7b1f
RD		 1265
1266 if (err)
1267 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1268
1269 mlx4_free_cmd_mailbox(dev, mailbox);
1270 return err;
1271}
1272
ab9c17a0
JM		 1273int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1274 struct mlx4_init_hca_param *param)
1275{
1276 struct mlx4_cmd_mailbox *mailbox;
1277 __be32 *outbox;
1278 int err;
1279
1280#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
1281
1282 mailbox = mlx4_alloc_cmd_mailbox(dev);
1283 if (IS_ERR(mailbox))
1284 return PTR_ERR(mailbox);
1285 outbox = mailbox->buf;
1286
1287 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1288 MLX4_CMD_QUERY_HCA,
1289 MLX4_CMD_TIME_CLASS_B,
1290 !mlx4_is_slave(dev));
1291 if (err)
1292 goto out;
1293
1294 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
1295
1296 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1297
1298 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1299 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1300 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1301 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1302 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1303 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1304 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1305 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1306 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1307 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1308 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1309 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1310
0ff1fb65
HHZ		 1311 /* steering attributes */
1312 if (dev->caps.steering_mode ==
1313 MLX4_STEERING_MODE_DEVICE_MANAGED) {
ab9c17a0 1314
0ff1fb65
HHZ		 1315 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1316 MLX4_GET(param->log_mc_entry_sz, outbox,
1317 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1318 MLX4_GET(param->log_mc_table_sz, outbox,
1319 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1320 } else {
1321 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1322 MLX4_GET(param->log_mc_entry_sz, outbox,
1323 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1324 MLX4_GET(param->log_mc_hash_sz, outbox,
1325 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1326 MLX4_GET(param->log_mc_table_sz, outbox,
1327 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1328 }
ab9c17a0
JM		 1329
1330 /* TPT attributes */
1331
1332 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
1333 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1334 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1335 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1336
1337 /* UAR attributes */
1338
1339 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1340 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1341
1342out:
1343 mlx4_free_cmd_mailbox(dev, mailbox);
1344
1345 return err;
1346}
1347
5cc914f1
MA		 1348int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1349 struct mlx4_vhcr *vhcr,
1350 struct mlx4_cmd_mailbox *inbox,
1351 struct mlx4_cmd_mailbox *outbox,
1352 struct mlx4_cmd_info *cmd)
1353{
1354 struct mlx4_priv *priv = mlx4_priv(dev);
1355 int port = vhcr->in_modifier;
1356 int err;
1357
1358 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1359 return 0;
1360
1361 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1362 return -ENODEV;
1363
1364 /* Enable port only if it was previously disabled */
1365 if (!priv->mfunc.master.init_port_ref[port]) {
1366 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1367 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1368 if (err)
1369 return err;
5cc914f1 1370 }
8bac9ede 1371 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1372 ++priv->mfunc.master.init_port_ref[port];
1373 return 0;
1374}
1375
5ae2a7a8 1376int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1377{
1378 struct mlx4_cmd_mailbox *mailbox;
1379 u32 *inbox;
1380 int err;
1381 u32 flags;
5ae2a7a8 1382 u16 field;
225c7b1f 1383
5ae2a7a8 1384 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1385#define INIT_PORT_IN_SIZE 256
1386#define INIT_PORT_FLAGS_OFFSET 0x00
1387#define INIT_PORT_FLAG_SIG (1 << 18)
1388#define INIT_PORT_FLAG_NG (1 << 17)
1389#define INIT_PORT_FLAG_G0 (1 << 16)
1390#define INIT_PORT_VL_SHIFT 4
1391#define INIT_PORT_PORT_WIDTH_SHIFT 8
1392#define INIT_PORT_MTU_OFFSET 0x04
1393#define INIT_PORT_MAX_GID_OFFSET 0x06
1394#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1395#define INIT_PORT_GUID0_OFFSET 0x10
1396#define INIT_PORT_NODE_GUID_OFFSET 0x18
1397#define INIT_PORT_SI_GUID_OFFSET 0x20
1398
5ae2a7a8
RD		 1399 mailbox = mlx4_alloc_cmd_mailbox(dev);
1400 if (IS_ERR(mailbox))
1401 return PTR_ERR(mailbox);
1402 inbox = mailbox->buf;
225c7b1f 1403
5ae2a7a8 1404 memset(inbox, 0, INIT_PORT_IN_SIZE);
225c7b1f 1405
5ae2a7a8
RD		 1406 flags = 0;
1407 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1408 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1409 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1410
b79acb49 1411 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1412 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1413 field = dev->caps.gid_table_len[port];
1414 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1415 field = dev->caps.pkey_table_len[port];
1416 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1417
5ae2a7a8 1418 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1419 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1420
5ae2a7a8
RD		 1421 mlx4_free_cmd_mailbox(dev, mailbox);
1422 } else
1423 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1424 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1425
1426 return err;
1427}
1428EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1429
5cc914f1
MA		 1430int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1431 struct mlx4_vhcr *vhcr,
1432 struct mlx4_cmd_mailbox *inbox,
1433 struct mlx4_cmd_mailbox *outbox,
1434 struct mlx4_cmd_info *cmd)
1435{
1436 struct mlx4_priv *priv = mlx4_priv(dev);
1437 int port = vhcr->in_modifier;
1438 int err;
1439
1440 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1441 (1 << port)))
1442 return 0;
1443
1444 if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB)
1445 return -ENODEV;
1446 if (priv->mfunc.master.init_port_ref[port] == 1) {
1447 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1448 MLX4_CMD_NATIVE);
1449 if (err)
1450 return err;
1451 }
1452 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1453 --priv->mfunc.master.init_port_ref[port];
1454 return 0;
1455}
1456
225c7b1f
RD		 1457int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1458{
f9baff50
JM		 1459 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1460 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1461}
1462EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1463
1464int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1465{
f9baff50
JM		 1466 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1467 MLX4_CMD_NATIVE);
225c7b1f
RD		 1468}
1469
1470int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1471{
1472 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1473 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1474 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1475 if (ret)
1476 return ret;
1477
1478 /*
1479 * Round up number of system pages needed in case
1480 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1481 */
1482 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1483 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1484
1485 return 0;
1486}
1487
1488int mlx4_NOP(struct mlx4_dev *dev)
1489{
1490 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1491 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1492}
14c07b13
YP		 1493
1494#define MLX4_WOL_SETUP_MODE (5 << 28)
1495int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1496{
1497 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1498
1499 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1500 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1501 MLX4_CMD_NATIVE);
14c07b13
YP		 1502}
1503EXPORT_SYMBOL_GPL(mlx4_wol_read);
1504
1505int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1506{
1507 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1508
1509 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1510 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1511}
1512EXPORT_SYMBOL_GPL(mlx4_wol_write);
Linux kernel - Deliverables
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