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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
5cc914f1 | 35 | #include <linux/etherdevice.h> |
225c7b1f | 36 | #include <linux/mlx4/cmd.h> |
9d9779e7 | 37 | #include <linux/module.h> |
c57e20dc | 38 | #include <linux/cache.h> |
225c7b1f RD |
39 | |
40 | #include "fw.h" | |
41 | #include "icm.h" | |
42 | ||
fe40900f | 43 | enum { |
5ae2a7a8 RD |
44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, | |
46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, | |
fe40900f RD |
47 | }; |
48 | ||
225c7b1f RD |
49 | extern void __buggy_use_of_MLX4_GET(void); |
50 | extern void __buggy_use_of_MLX4_PUT(void); | |
51 | ||
51f5f0ee JM |
52 | static int enable_qos; |
53 | module_param(enable_qos, bool, 0444); | |
54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); | |
55 | ||
225c7b1f RD |
56 | #define MLX4_GET(dest, source, offset) \ |
57 | do { \ | |
58 | void *__p = (char *) (source) + (offset); \ | |
59 | switch (sizeof (dest)) { \ | |
60 | case 1: (dest) = *(u8 *) __p; break; \ | |
61 | case 2: (dest) = be16_to_cpup(__p); break; \ | |
62 | case 4: (dest) = be32_to_cpup(__p); break; \ | |
63 | case 8: (dest) = be64_to_cpup(__p); break; \ | |
64 | default: __buggy_use_of_MLX4_GET(); \ | |
65 | } \ | |
66 | } while (0) | |
67 | ||
68 | #define MLX4_PUT(dest, source, offset) \ | |
69 | do { \ | |
70 | void *__d = ((char *) (dest) + (offset)); \ | |
71 | switch (sizeof(source)) { \ | |
72 | case 1: *(u8 *) __d = (source); break; \ | |
73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ | |
74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ | |
75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ | |
76 | default: __buggy_use_of_MLX4_PUT(); \ | |
77 | } \ | |
78 | } while (0) | |
79 | ||
52eafc68 | 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
225c7b1f RD |
81 | { |
82 | static const char *fname[] = { | |
83 | [ 0] = "RC transport", | |
84 | [ 1] = "UC transport", | |
85 | [ 2] = "UD transport", | |
ea98054f | 86 | [ 3] = "XRC transport", |
225c7b1f RD |
87 | [ 4] = "reliable multicast", |
88 | [ 5] = "FCoIB support", | |
89 | [ 6] = "SRQ support", | |
90 | [ 7] = "IPoIB checksum offload", | |
91 | [ 8] = "P_Key violation counter", | |
92 | [ 9] = "Q_Key violation counter", | |
93 | [10] = "VMM", | |
7ff93f8b | 94 | [12] = "DPDP", |
417608c2 | 95 | [15] = "Big LSO headers", |
225c7b1f RD |
96 | [16] = "MW support", |
97 | [17] = "APM support", | |
98 | [18] = "Atomic ops support", | |
99 | [19] = "Raw multicast support", | |
100 | [20] = "Address vector port checking support", | |
101 | [21] = "UD multicast support", | |
102 | [24] = "Demand paging support", | |
96dfa684 | 103 | [25] = "Router support", |
ccf86321 OG |
104 | [30] = "IBoE support", |
105 | [32] = "Unicast loopback support", | |
f3a9d1f2 | 106 | [34] = "FCS header control", |
ccf86321 OG |
107 | [38] = "Wake On LAN support", |
108 | [40] = "UDP RSS support", | |
109 | [41] = "Unicast VEP steering support", | |
f2a3f6a3 OG |
110 | [42] = "Multicast VEP steering support", |
111 | [48] = "Counters support", | |
225c7b1f RD |
112 | }; |
113 | int i; | |
114 | ||
115 | mlx4_dbg(dev, "DEV_CAP flags:\n"); | |
23c15c21 | 116 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
52eafc68 | 117 | if (fname[i] && (flags & (1LL << i))) |
225c7b1f RD |
118 | mlx4_dbg(dev, " %s\n", fname[i]); |
119 | } | |
120 | ||
2d928651 VS |
121 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
122 | { | |
123 | struct mlx4_cmd_mailbox *mailbox; | |
124 | u32 *inbox; | |
125 | int err = 0; | |
126 | ||
127 | #define MOD_STAT_CFG_IN_SIZE 0x100 | |
128 | ||
129 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 | |
130 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 | |
131 | ||
132 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
133 | if (IS_ERR(mailbox)) | |
134 | return PTR_ERR(mailbox); | |
135 | inbox = mailbox->buf; | |
136 | ||
137 | memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); | |
138 | ||
139 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); | |
140 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); | |
141 | ||
142 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 143 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
2d928651 VS |
144 | |
145 | mlx4_free_cmd_mailbox(dev, mailbox); | |
146 | return err; | |
147 | } | |
148 | ||
5cc914f1 MA |
149 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
150 | struct mlx4_vhcr *vhcr, | |
151 | struct mlx4_cmd_mailbox *inbox, | |
152 | struct mlx4_cmd_mailbox *outbox, | |
153 | struct mlx4_cmd_info *cmd) | |
154 | { | |
155 | u8 field; | |
156 | u32 size; | |
157 | int err = 0; | |
158 | ||
159 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 | |
160 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 | |
161 | #define QUERY_FUNC_CAP_FUNCTION_OFFSET 0x3 | |
162 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 | |
163 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 | |
164 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 | |
165 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 | |
166 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 | |
167 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 | |
168 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 | |
169 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c | |
170 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0X30 | |
171 | ||
172 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 | |
173 | #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc | |
174 | ||
175 | if (vhcr->op_modifier == 1) { | |
176 | field = vhcr->in_modifier; | |
177 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); | |
178 | ||
179 | field = 0; /* ensure fvl bit is not set */ | |
180 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); | |
181 | } else if (vhcr->op_modifier == 0) { | |
182 | field = 1 << 7; /* enable only ethernet interface */ | |
183 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); | |
184 | ||
185 | field = slave; | |
186 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FUNCTION_OFFSET); | |
187 | ||
188 | field = dev->caps.num_ports; | |
189 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); | |
190 | ||
191 | size = 0; /* no PF behavious is set for now */ | |
192 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); | |
193 | ||
194 | size = dev->caps.num_qps; | |
195 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); | |
196 | ||
197 | size = dev->caps.num_srqs; | |
198 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); | |
199 | ||
200 | size = dev->caps.num_cqs; | |
201 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); | |
202 | ||
203 | size = dev->caps.num_eqs; | |
204 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); | |
205 | ||
206 | size = dev->caps.reserved_eqs; | |
207 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); | |
208 | ||
209 | size = dev->caps.num_mpts; | |
210 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); | |
211 | ||
2b8fb286 | 212 | size = dev->caps.num_mtts; |
5cc914f1 MA |
213 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
214 | ||
215 | size = dev->caps.num_mgms + dev->caps.num_amgms; | |
216 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); | |
217 | ||
218 | } else | |
219 | err = -EINVAL; | |
220 | ||
221 | return err; | |
222 | } | |
223 | ||
224 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, struct mlx4_func_cap *func_cap) | |
225 | { | |
226 | struct mlx4_cmd_mailbox *mailbox; | |
227 | u32 *outbox; | |
228 | u8 field; | |
229 | u32 size; | |
230 | int i; | |
231 | int err = 0; | |
232 | ||
233 | ||
234 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
235 | if (IS_ERR(mailbox)) | |
236 | return PTR_ERR(mailbox); | |
237 | ||
238 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FUNC_CAP, | |
239 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
240 | if (err) | |
241 | goto out; | |
242 | ||
243 | outbox = mailbox->buf; | |
244 | ||
245 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); | |
246 | if (!(field & (1 << 7))) { | |
247 | mlx4_err(dev, "The host doesn't support eth interface\n"); | |
248 | err = -EPROTONOSUPPORT; | |
249 | goto out; | |
250 | } | |
251 | ||
252 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FUNCTION_OFFSET); | |
253 | func_cap->function = field; | |
254 | ||
255 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); | |
256 | func_cap->num_ports = field; | |
257 | ||
258 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); | |
259 | func_cap->pf_context_behaviour = size; | |
260 | ||
261 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); | |
262 | func_cap->qp_quota = size & 0xFFFFFF; | |
263 | ||
264 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); | |
265 | func_cap->srq_quota = size & 0xFFFFFF; | |
266 | ||
267 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); | |
268 | func_cap->cq_quota = size & 0xFFFFFF; | |
269 | ||
270 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); | |
271 | func_cap->max_eq = size & 0xFFFFFF; | |
272 | ||
273 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); | |
274 | func_cap->reserved_eq = size & 0xFFFFFF; | |
275 | ||
276 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); | |
277 | func_cap->mpt_quota = size & 0xFFFFFF; | |
278 | ||
279 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); | |
280 | func_cap->mtt_quota = size & 0xFFFFFF; | |
281 | ||
282 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); | |
283 | func_cap->mcg_quota = size & 0xFFFFFF; | |
284 | ||
285 | for (i = 1; i <= func_cap->num_ports; ++i) { | |
286 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 1, | |
287 | MLX4_CMD_QUERY_FUNC_CAP, | |
288 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
289 | if (err) | |
290 | goto out; | |
291 | ||
292 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); | |
293 | if (field & (1 << 7)) { | |
294 | mlx4_err(dev, "VLAN is enforced on this port\n"); | |
295 | err = -EPROTONOSUPPORT; | |
296 | goto out; | |
297 | } | |
298 | ||
299 | if (field & (1 << 6)) { | |
300 | mlx4_err(dev, "Force mac is enabled on this port\n"); | |
301 | err = -EPROTONOSUPPORT; | |
302 | goto out; | |
303 | } | |
304 | ||
305 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); | |
306 | func_cap->physical_port[i] = field; | |
307 | } | |
308 | ||
309 | /* All other resources are allocated by the master, but we still report | |
310 | * 'num' and 'reserved' capabilities as follows: | |
311 | * - num remains the maximum resource index | |
312 | * - 'num - reserved' is the total available objects of a resource, but | |
313 | * resource indices may be less than 'reserved' | |
314 | * TODO: set per-resource quotas */ | |
315 | ||
316 | out: | |
317 | mlx4_free_cmd_mailbox(dev, mailbox); | |
318 | ||
319 | return err; | |
320 | } | |
321 | ||
225c7b1f RD |
322 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
323 | { | |
324 | struct mlx4_cmd_mailbox *mailbox; | |
325 | u32 *outbox; | |
326 | u8 field; | |
ccf86321 | 327 | u32 field32, flags, ext_flags; |
225c7b1f RD |
328 | u16 size; |
329 | u16 stat_rate; | |
330 | int err; | |
5ae2a7a8 | 331 | int i; |
225c7b1f RD |
332 | |
333 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 | |
334 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 | |
335 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 | |
336 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 | |
337 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 | |
338 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 | |
339 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 | |
340 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 | |
341 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 | |
342 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 | |
343 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a | |
344 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b | |
345 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d | |
346 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e | |
347 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f | |
348 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 | |
349 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 | |
350 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 | |
351 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 | |
352 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 | |
353 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 | |
354 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b | |
b832be1e | 355 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
225c7b1f RD |
356 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
357 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 | |
358 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 | |
359 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 | |
360 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 | |
149983af | 361 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
225c7b1f RD |
362 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
363 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c | |
364 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f | |
ccf86321 | 365 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
225c7b1f RD |
366 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
367 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 | |
368 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 | |
369 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b | |
370 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c | |
371 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d | |
372 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e | |
373 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f | |
374 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 | |
375 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 | |
376 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 | |
377 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
378 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 | |
379 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 | |
380 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 | |
381 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 | |
382 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 | |
012a8ff5 SH |
383 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
384 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 | |
f2a3f6a3 | 385 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
225c7b1f RD |
386 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
387 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 | |
388 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 | |
389 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 | |
390 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 | |
391 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a | |
392 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c | |
393 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e | |
394 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 | |
395 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 | |
95d04f07 | 396 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
225c7b1f RD |
397 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
398 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 | |
399 | ||
400 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
401 | if (IS_ERR(mailbox)) | |
402 | return PTR_ERR(mailbox); | |
403 | outbox = mailbox->buf; | |
404 | ||
405 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
f9baff50 | 406 | MLX4_CMD_TIME_CLASS_A, !mlx4_is_slave(dev)); |
225c7b1f RD |
407 | if (err) |
408 | goto out; | |
409 | ||
410 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); | |
411 | dev_cap->reserved_qps = 1 << (field & 0xf); | |
412 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); | |
413 | dev_cap->max_qps = 1 << (field & 0x1f); | |
414 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); | |
415 | dev_cap->reserved_srqs = 1 << (field >> 4); | |
416 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); | |
417 | dev_cap->max_srqs = 1 << (field & 0x1f); | |
418 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); | |
419 | dev_cap->max_cq_sz = 1 << field; | |
420 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); | |
421 | dev_cap->reserved_cqs = 1 << (field & 0xf); | |
422 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); | |
423 | dev_cap->max_cqs = 1 << (field & 0x1f); | |
424 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); | |
425 | dev_cap->max_mpts = 1 << (field & 0x3f); | |
426 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); | |
be504b0b | 427 | dev_cap->reserved_eqs = field & 0xf; |
225c7b1f | 428 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
5920869f | 429 | dev_cap->max_eqs = 1 << (field & 0xf); |
225c7b1f RD |
430 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
431 | dev_cap->reserved_mtts = 1 << (field >> 4); | |
432 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); | |
433 | dev_cap->max_mrw_sz = 1 << field; | |
434 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); | |
435 | dev_cap->reserved_mrws = 1 << (field & 0xf); | |
436 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); | |
437 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); | |
438 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); | |
439 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); | |
440 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); | |
441 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); | |
b832be1e EC |
442 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
443 | field &= 0x1f; | |
444 | if (!field) | |
445 | dev_cap->max_gso_sz = 0; | |
446 | else | |
447 | dev_cap->max_gso_sz = 1 << field; | |
448 | ||
225c7b1f RD |
449 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
450 | dev_cap->max_rdma_global = 1 << (field & 0x3f); | |
451 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); | |
452 | dev_cap->local_ca_ack_delay = field & 0x1f; | |
225c7b1f | 453 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
225c7b1f | 454 | dev_cap->num_ports = field & 0xf; |
149983af DB |
455 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
456 | dev_cap->max_msg_sz = 1 << (field & 0x1f); | |
225c7b1f RD |
457 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
458 | dev_cap->stat_rate_support = stat_rate; | |
ccf86321 | 459 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
52eafc68 | 460 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
ccf86321 | 461 | dev_cap->flags = flags | (u64)ext_flags << 32; |
225c7b1f RD |
462 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
463 | dev_cap->reserved_uars = field >> 4; | |
464 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); | |
465 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); | |
466 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); | |
467 | dev_cap->min_page_sz = 1 << field; | |
468 | ||
469 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); | |
470 | if (field & 0x80) { | |
471 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); | |
472 | dev_cap->bf_reg_size = 1 << (field & 0x1f); | |
473 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); | |
f5a49539 | 474 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
58d74bb1 | 475 | field = 3; |
225c7b1f RD |
476 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
477 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", | |
478 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); | |
479 | } else { | |
480 | dev_cap->bf_reg_size = 0; | |
481 | mlx4_dbg(dev, "BlueFlame not available\n"); | |
482 | } | |
483 | ||
484 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); | |
485 | dev_cap->max_sq_sg = field; | |
486 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); | |
487 | dev_cap->max_sq_desc_sz = size; | |
488 | ||
489 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); | |
490 | dev_cap->max_qp_per_mcg = 1 << field; | |
491 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); | |
492 | dev_cap->reserved_mgms = field & 0xf; | |
493 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); | |
494 | dev_cap->max_mcgs = 1 << field; | |
495 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); | |
496 | dev_cap->reserved_pds = field >> 4; | |
497 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
498 | dev_cap->max_pds = 1 << (field & 0x3f); | |
012a8ff5 SH |
499 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
500 | dev_cap->reserved_xrcds = field >> 4; | |
501 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
502 | dev_cap->max_xrcds = 1 << (field & 0x1f); | |
225c7b1f RD |
503 | |
504 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); | |
505 | dev_cap->rdmarc_entry_sz = size; | |
506 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); | |
507 | dev_cap->qpc_entry_sz = size; | |
508 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); | |
509 | dev_cap->aux_entry_sz = size; | |
510 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); | |
511 | dev_cap->altc_entry_sz = size; | |
512 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); | |
513 | dev_cap->eqc_entry_sz = size; | |
514 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); | |
515 | dev_cap->cqc_entry_sz = size; | |
516 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); | |
517 | dev_cap->srq_entry_sz = size; | |
518 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); | |
519 | dev_cap->cmpt_entry_sz = size; | |
520 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); | |
521 | dev_cap->mtt_entry_sz = size; | |
522 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); | |
523 | dev_cap->dmpt_entry_sz = size; | |
524 | ||
525 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); | |
526 | dev_cap->max_srq_sz = 1 << field; | |
527 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); | |
528 | dev_cap->max_qp_sz = 1 << field; | |
529 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); | |
530 | dev_cap->resize_srq = field & 1; | |
531 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); | |
532 | dev_cap->max_rq_sg = field; | |
533 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); | |
534 | dev_cap->max_rq_desc_sz = size; | |
535 | ||
536 | MLX4_GET(dev_cap->bmme_flags, outbox, | |
537 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
538 | MLX4_GET(dev_cap->reserved_lkey, outbox, | |
539 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); | |
540 | MLX4_GET(dev_cap->max_icm_sz, outbox, | |
541 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); | |
f2a3f6a3 OG |
542 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
543 | MLX4_GET(dev_cap->max_counters, outbox, | |
544 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); | |
225c7b1f | 545 | |
5ae2a7a8 RD |
546 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
547 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
548 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); | |
549 | dev_cap->max_vl[i] = field >> 4; | |
550 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); | |
b79acb49 | 551 | dev_cap->ib_mtu[i] = field >> 4; |
5ae2a7a8 RD |
552 | dev_cap->max_port_width[i] = field & 0xf; |
553 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); | |
554 | dev_cap->max_gids[i] = 1 << (field & 0xf); | |
555 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); | |
556 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
557 | } | |
558 | } else { | |
7ff93f8b | 559 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
5ae2a7a8 | 560 | #define QUERY_PORT_MTU_OFFSET 0x01 |
b79acb49 | 561 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
5ae2a7a8 RD |
562 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
563 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 | |
93fc9e1b | 564 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
5ae2a7a8 | 565 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
e65b9591 | 566 | #define QUERY_PORT_MAC_OFFSET 0x10 |
7699517d YP |
567 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
568 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c | |
569 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 | |
5ae2a7a8 RD |
570 | |
571 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
572 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, | |
f9baff50 JM |
573 | MLX4_CMD_TIME_CLASS_B, |
574 | !mlx4_is_slave(dev)); | |
5ae2a7a8 RD |
575 | if (err) |
576 | goto out; | |
577 | ||
7ff93f8b YP |
578 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
579 | dev_cap->supported_port_types[i] = field & 3; | |
5ae2a7a8 | 580 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
b79acb49 | 581 | dev_cap->ib_mtu[i] = field & 0xf; |
5ae2a7a8 RD |
582 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
583 | dev_cap->max_port_width[i] = field & 0xf; | |
584 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); | |
585 | dev_cap->max_gids[i] = 1 << (field >> 4); | |
586 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
587 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); | |
588 | dev_cap->max_vl[i] = field & 0xf; | |
93fc9e1b YP |
589 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
590 | dev_cap->log_max_macs[i] = field & 0xf; | |
591 | dev_cap->log_max_vlans[i] = field >> 4; | |
b79acb49 YP |
592 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
593 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); | |
7699517d YP |
594 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
595 | dev_cap->trans_type[i] = field32 >> 24; | |
596 | dev_cap->vendor_oui[i] = field32 & 0xffffff; | |
597 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); | |
598 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); | |
5ae2a7a8 RD |
599 | } |
600 | } | |
601 | ||
95d04f07 RD |
602 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
603 | dev_cap->bmme_flags, dev_cap->reserved_lkey); | |
225c7b1f RD |
604 | |
605 | /* | |
606 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then | |
607 | * we can't use any EQs whose doorbell falls on that page, | |
608 | * even if the EQ itself isn't reserved. | |
609 | */ | |
610 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, | |
611 | dev_cap->reserved_eqs); | |
612 | ||
613 | mlx4_dbg(dev, "Max ICM size %lld MB\n", | |
614 | (unsigned long long) dev_cap->max_icm_sz >> 20); | |
615 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", | |
616 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); | |
617 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
618 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); | |
619 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
620 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); | |
621 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
622 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); | |
623 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
624 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); | |
625 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
626 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); | |
627 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
628 | dev_cap->max_pds, dev_cap->reserved_mgms); | |
629 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
630 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); | |
631 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", | |
b79acb49 | 632 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
5ae2a7a8 | 633 | dev_cap->max_port_width[1]); |
225c7b1f RD |
634 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
635 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); | |
636 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", | |
637 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); | |
b832be1e | 638 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
f2a3f6a3 | 639 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
225c7b1f RD |
640 | |
641 | dump_dev_cap_flags(dev, dev_cap->flags); | |
642 | ||
643 | out: | |
644 | mlx4_free_cmd_mailbox(dev, mailbox); | |
645 | return err; | |
646 | } | |
647 | ||
5cc914f1 MA |
648 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
649 | struct mlx4_vhcr *vhcr, | |
650 | struct mlx4_cmd_mailbox *inbox, | |
651 | struct mlx4_cmd_mailbox *outbox, | |
652 | struct mlx4_cmd_info *cmd) | |
653 | { | |
654 | u64 def_mac; | |
655 | u8 port_type; | |
656 | int err; | |
657 | ||
658 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, | |
659 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
660 | MLX4_CMD_NATIVE); | |
661 | ||
662 | if (!err && dev->caps.function != slave) { | |
663 | /* set slave default_mac address */ | |
664 | MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); | |
665 | def_mac += slave << 8; | |
666 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); | |
667 | ||
668 | /* get port type - currently only eth is enabled */ | |
669 | MLX4_GET(port_type, outbox->buf, | |
670 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
671 | ||
672 | /* disable ib */ | |
673 | port_type &= 0xFE; | |
674 | ||
675 | /* check eth is enabled for this port */ | |
676 | if (!(port_type & 2)) | |
677 | mlx4_dbg(dev, "QUERY PORT: eth not supported by host"); | |
678 | ||
679 | MLX4_PUT(outbox->buf, port_type, | |
680 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
681 | } | |
682 | ||
683 | return err; | |
684 | } | |
685 | ||
686 | static int mlx4_QUERY_PORT(struct mlx4_dev *dev, void *ptr, u8 port) | |
687 | { | |
688 | struct mlx4_cmd_mailbox *outbox = ptr; | |
689 | ||
690 | return mlx4_cmd_box(dev, 0, outbox->dma, port, 0, | |
691 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
692 | MLX4_CMD_WRAPPED); | |
693 | } | |
694 | EXPORT_SYMBOL_GPL(mlx4_QUERY_PORT); | |
695 | ||
225c7b1f RD |
696 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
697 | { | |
698 | struct mlx4_cmd_mailbox *mailbox; | |
699 | struct mlx4_icm_iter iter; | |
700 | __be64 *pages; | |
701 | int lg; | |
702 | int nent = 0; | |
703 | int i; | |
704 | int err = 0; | |
705 | int ts = 0, tc = 0; | |
706 | ||
707 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
708 | if (IS_ERR(mailbox)) | |
709 | return PTR_ERR(mailbox); | |
710 | memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); | |
711 | pages = mailbox->buf; | |
712 | ||
713 | for (mlx4_icm_first(icm, &iter); | |
714 | !mlx4_icm_last(&iter); | |
715 | mlx4_icm_next(&iter)) { | |
716 | /* | |
717 | * We have to pass pages that are aligned to their | |
718 | * size, so find the least significant 1 in the | |
719 | * address or size and use that as our log2 size. | |
720 | */ | |
721 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; | |
722 | if (lg < MLX4_ICM_PAGE_SHIFT) { | |
723 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
724 | MLX4_ICM_PAGE_SIZE, | |
725 | (unsigned long long) mlx4_icm_addr(&iter), | |
726 | mlx4_icm_size(&iter)); | |
727 | err = -EINVAL; | |
728 | goto out; | |
729 | } | |
730 | ||
731 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { | |
732 | if (virt != -1) { | |
733 | pages[nent * 2] = cpu_to_be64(virt); | |
734 | virt += 1 << lg; | |
735 | } | |
736 | ||
737 | pages[nent * 2 + 1] = | |
738 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | | |
739 | (lg - MLX4_ICM_PAGE_SHIFT)); | |
740 | ts += 1 << (lg - 10); | |
741 | ++tc; | |
742 | ||
743 | if (++nent == MLX4_MAILBOX_SIZE / 16) { | |
744 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, | |
f9baff50 JM |
745 | MLX4_CMD_TIME_CLASS_B, |
746 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
747 | if (err) |
748 | goto out; | |
749 | nent = 0; | |
750 | } | |
751 | } | |
752 | } | |
753 | ||
754 | if (nent) | |
f9baff50 JM |
755 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
756 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
757 | if (err) |
758 | goto out; | |
759 | ||
760 | switch (op) { | |
761 | case MLX4_CMD_MAP_FA: | |
762 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
763 | break; | |
764 | case MLX4_CMD_MAP_ICM_AUX: | |
765 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
766 | break; | |
767 | case MLX4_CMD_MAP_ICM: | |
768 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
769 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
770 | break; | |
771 | } | |
772 | ||
773 | out: | |
774 | mlx4_free_cmd_mailbox(dev, mailbox); | |
775 | return err; | |
776 | } | |
777 | ||
778 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) | |
779 | { | |
780 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); | |
781 | } | |
782 | ||
783 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) | |
784 | { | |
f9baff50 JM |
785 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
786 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
787 | } |
788 | ||
789 | ||
790 | int mlx4_RUN_FW(struct mlx4_dev *dev) | |
791 | { | |
f9baff50 JM |
792 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
793 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
225c7b1f RD |
794 | } |
795 | ||
796 | int mlx4_QUERY_FW(struct mlx4_dev *dev) | |
797 | { | |
798 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; | |
799 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
800 | struct mlx4_cmd_mailbox *mailbox; | |
801 | u32 *outbox; | |
802 | int err = 0; | |
803 | u64 fw_ver; | |
fe40900f | 804 | u16 cmd_if_rev; |
225c7b1f RD |
805 | u8 lg; |
806 | ||
807 | #define QUERY_FW_OUT_SIZE 0x100 | |
808 | #define QUERY_FW_VER_OFFSET 0x00 | |
5cc914f1 | 809 | #define QUERY_FW_PPF_ID 0x09 |
fe40900f | 810 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
225c7b1f RD |
811 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
812 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
813 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
814 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c | |
815 | ||
816 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
817 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
818 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 | |
819 | ||
5cc914f1 MA |
820 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
821 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 | |
822 | ||
225c7b1f RD |
823 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
824 | if (IS_ERR(mailbox)) | |
825 | return PTR_ERR(mailbox); | |
826 | outbox = mailbox->buf; | |
827 | ||
828 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
f9baff50 | 829 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
830 | if (err) |
831 | goto out; | |
832 | ||
833 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
834 | /* | |
3e1db334 | 835 | * FW subminor version is at more significant bits than minor |
225c7b1f RD |
836 | * version, so swap here. |
837 | */ | |
838 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | | |
839 | ((fw_ver & 0xffff0000ull) >> 16) | | |
840 | ((fw_ver & 0x0000ffffull) << 16); | |
841 | ||
5cc914f1 MA |
842 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
843 | dev->caps.function = lg; | |
844 | ||
fe40900f | 845 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
5ae2a7a8 RD |
846 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
847 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { | |
fe40900f RD |
848 | mlx4_err(dev, "Installed FW has unsupported " |
849 | "command interface revision %d.\n", | |
850 | cmd_if_rev); | |
851 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", | |
852 | (int) (dev->caps.fw_ver >> 32), | |
853 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
854 | (int) dev->caps.fw_ver & 0xffff); | |
5ae2a7a8 RD |
855 | mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", |
856 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); | |
fe40900f RD |
857 | err = -ENODEV; |
858 | goto out; | |
859 | } | |
860 | ||
5ae2a7a8 RD |
861 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
862 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; | |
863 | ||
225c7b1f RD |
864 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
865 | cmd->max_cmds = 1 << lg; | |
866 | ||
fe40900f | 867 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
225c7b1f RD |
868 | (int) (dev->caps.fw_ver >> 32), |
869 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
870 | (int) dev->caps.fw_ver & 0xffff, | |
fe40900f | 871 | cmd_if_rev, cmd->max_cmds); |
225c7b1f RD |
872 | |
873 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); | |
874 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
875 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); | |
876 | fw->catas_bar = (fw->catas_bar >> 6) * 2; | |
877 | ||
878 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", | |
879 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); | |
880 | ||
881 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); | |
882 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
883 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); | |
884 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; | |
885 | ||
5cc914f1 MA |
886 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
887 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); | |
888 | fw->comm_bar = (fw->comm_bar >> 6) * 2; | |
889 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", | |
890 | fw->comm_bar, fw->comm_base); | |
225c7b1f RD |
891 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
892 | ||
893 | /* | |
894 | * Round up number of system pages needed in case | |
895 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
896 | */ | |
897 | fw->fw_pages = | |
898 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
899 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
900 | ||
901 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", | |
902 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); | |
903 | ||
904 | out: | |
905 | mlx4_free_cmd_mailbox(dev, mailbox); | |
906 | return err; | |
907 | } | |
908 | ||
909 | static void get_board_id(void *vsd, char *board_id) | |
910 | { | |
911 | int i; | |
912 | ||
913 | #define VSD_OFFSET_SIG1 0x00 | |
914 | #define VSD_OFFSET_SIG2 0xde | |
915 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
916 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
917 | ||
918 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
919 | ||
920 | memset(board_id, 0, MLX4_BOARD_ID_LEN); | |
921 | ||
922 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
923 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
924 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); | |
925 | } else { | |
926 | /* | |
927 | * The board ID is a string but the firmware byte | |
928 | * swaps each 4-byte word before passing it back to | |
929 | * us. Therefore we need to swab it before printing. | |
930 | */ | |
931 | for (i = 0; i < 4; ++i) | |
932 | ((u32 *) board_id)[i] = | |
933 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
934 | } | |
935 | } | |
936 | ||
937 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) | |
938 | { | |
939 | struct mlx4_cmd_mailbox *mailbox; | |
940 | u32 *outbox; | |
941 | int err; | |
942 | ||
943 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
225c7b1f RD |
944 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
945 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 | |
946 | ||
947 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
948 | if (IS_ERR(mailbox)) | |
949 | return PTR_ERR(mailbox); | |
950 | outbox = mailbox->buf; | |
951 | ||
952 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, | |
f9baff50 | 953 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
954 | if (err) |
955 | goto out; | |
956 | ||
225c7b1f RD |
957 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
958 | ||
959 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, | |
960 | adapter->board_id); | |
961 | ||
962 | out: | |
963 | mlx4_free_cmd_mailbox(dev, mailbox); | |
964 | return err; | |
965 | } | |
966 | ||
967 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) | |
968 | { | |
969 | struct mlx4_cmd_mailbox *mailbox; | |
970 | __be32 *inbox; | |
971 | int err; | |
972 | ||
973 | #define INIT_HCA_IN_SIZE 0x200 | |
974 | #define INIT_HCA_VERSION_OFFSET 0x000 | |
975 | #define INIT_HCA_VERSION 2 | |
c57e20dc | 976 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
225c7b1f RD |
977 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
978 | #define INIT_HCA_QPC_OFFSET 0x020 | |
979 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
980 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
981 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
982 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
983 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
984 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
5cc914f1 | 985 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
225c7b1f RD |
986 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
987 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
988 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
989 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
990 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
991 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) | |
992 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
993 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
994 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
995 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1679200f | 996 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
225c7b1f RD |
997 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
998 | #define INIT_HCA_TPT_OFFSET 0x0f0 | |
999 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
1000 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) | |
1001 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1002 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) | |
1003 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1004 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1005 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1006 | ||
1007 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1008 | if (IS_ERR(mailbox)) | |
1009 | return PTR_ERR(mailbox); | |
1010 | inbox = mailbox->buf; | |
1011 | ||
1012 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1013 | ||
1014 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; | |
1015 | ||
c57e20dc EC |
1016 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
1017 | (ilog2(cache_line_size()) - 4) << 5; | |
1018 | ||
225c7b1f RD |
1019 | #if defined(__LITTLE_ENDIAN) |
1020 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); | |
1021 | #elif defined(__BIG_ENDIAN) | |
1022 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); | |
1023 | #else | |
1024 | #error Host endianness not defined | |
1025 | #endif | |
1026 | /* Check port for UD address vector: */ | |
1027 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); | |
1028 | ||
8ff095ec EC |
1029 | /* Enable IPoIB checksumming if we can: */ |
1030 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) | |
1031 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); | |
1032 | ||
51f5f0ee JM |
1033 | /* Enable QoS support if module parameter set */ |
1034 | if (enable_qos) | |
1035 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); | |
1036 | ||
f2a3f6a3 OG |
1037 | /* enable counters */ |
1038 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) | |
1039 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); | |
1040 | ||
225c7b1f RD |
1041 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
1042 | ||
1043 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1044 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1045 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1046 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1047 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1048 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1049 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); | |
1050 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); | |
1051 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1052 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1053 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); | |
1054 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); | |
1055 | ||
1056 | /* multicast attributes */ | |
1057 | ||
1058 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1059 | MLX4_PUT(inbox, param->log_mc_entry_sz, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1060 | MLX4_PUT(inbox, param->log_mc_hash_sz, INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
ccf86321 | 1061 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) |
1679200f | 1062 | MLX4_PUT(inbox, (u8) (1 << 3), INIT_HCA_UC_STEERING_OFFSET); |
225c7b1f RD |
1063 | MLX4_PUT(inbox, param->log_mc_table_sz, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
1064 | ||
1065 | /* TPT attributes */ | |
1066 | ||
1067 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); | |
1068 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1069 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1070 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); | |
1071 | ||
1072 | /* UAR attributes */ | |
1073 | ||
ab9c17a0 | 1074 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
225c7b1f RD |
1075 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
1076 | ||
f9baff50 JM |
1077 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
1078 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1079 | |
1080 | if (err) | |
1081 | mlx4_err(dev, "INIT_HCA returns %d\n", err); | |
1082 | ||
1083 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1084 | return err; | |
1085 | } | |
1086 | ||
ab9c17a0 JM |
1087 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
1088 | struct mlx4_init_hca_param *param) | |
1089 | { | |
1090 | struct mlx4_cmd_mailbox *mailbox; | |
1091 | __be32 *outbox; | |
1092 | int err; | |
1093 | ||
1094 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 | |
1095 | ||
1096 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1097 | if (IS_ERR(mailbox)) | |
1098 | return PTR_ERR(mailbox); | |
1099 | outbox = mailbox->buf; | |
1100 | ||
1101 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, | |
1102 | MLX4_CMD_QUERY_HCA, | |
1103 | MLX4_CMD_TIME_CLASS_B, | |
1104 | !mlx4_is_slave(dev)); | |
1105 | if (err) | |
1106 | goto out; | |
1107 | ||
1108 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); | |
1109 | ||
1110 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ | |
1111 | ||
1112 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); | |
1113 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); | |
1114 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); | |
1115 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); | |
1116 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); | |
1117 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); | |
1118 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); | |
1119 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); | |
1120 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); | |
1121 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); | |
1122 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); | |
1123 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); | |
1124 | ||
1125 | /* multicast attributes */ | |
1126 | ||
1127 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); | |
1128 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1129 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1130 | MLX4_GET(param->log_mc_hash_sz, outbox, | |
1131 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1132 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1133 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1134 | ||
1135 | /* TPT attributes */ | |
1136 | ||
1137 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); | |
1138 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); | |
1139 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); | |
1140 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); | |
1141 | ||
1142 | /* UAR attributes */ | |
1143 | ||
1144 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1145 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1146 | ||
1147 | out: | |
1148 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1149 | ||
1150 | return err; | |
1151 | } | |
1152 | ||
5cc914f1 MA |
1153 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1154 | struct mlx4_vhcr *vhcr, | |
1155 | struct mlx4_cmd_mailbox *inbox, | |
1156 | struct mlx4_cmd_mailbox *outbox, | |
1157 | struct mlx4_cmd_info *cmd) | |
1158 | { | |
1159 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1160 | int port = vhcr->in_modifier; | |
1161 | int err; | |
1162 | ||
1163 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) | |
1164 | return 0; | |
1165 | ||
1166 | if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB) | |
1167 | return -ENODEV; | |
1168 | ||
1169 | /* Enable port only if it was previously disabled */ | |
1170 | if (!priv->mfunc.master.init_port_ref[port]) { | |
1171 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1172 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1173 | if (err) | |
1174 | return err; | |
1175 | priv->mfunc.master.slave_state[slave].init_port_mask |= | |
1176 | (1 << port); | |
1177 | } | |
1178 | ++priv->mfunc.master.init_port_ref[port]; | |
1179 | return 0; | |
1180 | } | |
1181 | ||
5ae2a7a8 | 1182 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
225c7b1f RD |
1183 | { |
1184 | struct mlx4_cmd_mailbox *mailbox; | |
1185 | u32 *inbox; | |
1186 | int err; | |
1187 | u32 flags; | |
5ae2a7a8 | 1188 | u16 field; |
225c7b1f | 1189 | |
5ae2a7a8 | 1190 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
225c7b1f RD |
1191 | #define INIT_PORT_IN_SIZE 256 |
1192 | #define INIT_PORT_FLAGS_OFFSET 0x00 | |
1193 | #define INIT_PORT_FLAG_SIG (1 << 18) | |
1194 | #define INIT_PORT_FLAG_NG (1 << 17) | |
1195 | #define INIT_PORT_FLAG_G0 (1 << 16) | |
1196 | #define INIT_PORT_VL_SHIFT 4 | |
1197 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 | |
1198 | #define INIT_PORT_MTU_OFFSET 0x04 | |
1199 | #define INIT_PORT_MAX_GID_OFFSET 0x06 | |
1200 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a | |
1201 | #define INIT_PORT_GUID0_OFFSET 0x10 | |
1202 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 | |
1203 | #define INIT_PORT_SI_GUID_OFFSET 0x20 | |
1204 | ||
5ae2a7a8 RD |
1205 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1206 | if (IS_ERR(mailbox)) | |
1207 | return PTR_ERR(mailbox); | |
1208 | inbox = mailbox->buf; | |
225c7b1f | 1209 | |
5ae2a7a8 | 1210 | memset(inbox, 0, INIT_PORT_IN_SIZE); |
225c7b1f | 1211 | |
5ae2a7a8 RD |
1212 | flags = 0; |
1213 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; | |
1214 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; | |
1215 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); | |
225c7b1f | 1216 | |
b79acb49 | 1217 | field = 128 << dev->caps.ib_mtu_cap[port]; |
5ae2a7a8 RD |
1218 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
1219 | field = dev->caps.gid_table_len[port]; | |
1220 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); | |
1221 | field = dev->caps.pkey_table_len[port]; | |
1222 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); | |
225c7b1f | 1223 | |
5ae2a7a8 | 1224 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
f9baff50 | 1225 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f | 1226 | |
5ae2a7a8 RD |
1227 | mlx4_free_cmd_mailbox(dev, mailbox); |
1228 | } else | |
1229 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
f9baff50 | 1230 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
225c7b1f RD |
1231 | |
1232 | return err; | |
1233 | } | |
1234 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); | |
1235 | ||
5cc914f1 MA |
1236 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1237 | struct mlx4_vhcr *vhcr, | |
1238 | struct mlx4_cmd_mailbox *inbox, | |
1239 | struct mlx4_cmd_mailbox *outbox, | |
1240 | struct mlx4_cmd_info *cmd) | |
1241 | { | |
1242 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1243 | int port = vhcr->in_modifier; | |
1244 | int err; | |
1245 | ||
1246 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & | |
1247 | (1 << port))) | |
1248 | return 0; | |
1249 | ||
1250 | if (dev->caps.port_mask[port] == MLX4_PORT_TYPE_IB) | |
1251 | return -ENODEV; | |
1252 | if (priv->mfunc.master.init_port_ref[port] == 1) { | |
1253 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, | |
1254 | MLX4_CMD_NATIVE); | |
1255 | if (err) | |
1256 | return err; | |
1257 | } | |
1258 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1259 | --priv->mfunc.master.init_port_ref[port]; | |
1260 | return 0; | |
1261 | } | |
1262 | ||
225c7b1f RD |
1263 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
1264 | { | |
f9baff50 JM |
1265 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
1266 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
1267 | } |
1268 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); | |
1269 | ||
1270 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) | |
1271 | { | |
f9baff50 JM |
1272 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
1273 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1274 | } |
1275 | ||
1276 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) | |
1277 | { | |
1278 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, | |
1279 | MLX4_CMD_SET_ICM_SIZE, | |
f9baff50 | 1280 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1281 | if (ret) |
1282 | return ret; | |
1283 | ||
1284 | /* | |
1285 | * Round up number of system pages needed in case | |
1286 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1287 | */ | |
1288 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1289 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1290 | ||
1291 | return 0; | |
1292 | } | |
1293 | ||
1294 | int mlx4_NOP(struct mlx4_dev *dev) | |
1295 | { | |
1296 | /* Input modifier of 0x1f means "finish as soon as possible." */ | |
f9baff50 | 1297 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
225c7b1f | 1298 | } |
14c07b13 YP |
1299 | |
1300 | #define MLX4_WOL_SETUP_MODE (5 << 28) | |
1301 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) | |
1302 | { | |
1303 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1304 | ||
1305 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, | |
f9baff50 JM |
1306 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
1307 | MLX4_CMD_NATIVE); | |
14c07b13 YP |
1308 | } |
1309 | EXPORT_SYMBOL_GPL(mlx4_wol_read); | |
1310 | ||
1311 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) | |
1312 | { | |
1313 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1314 | ||
1315 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 1316 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
14c07b13 YP |
1317 | } |
1318 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |