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net/mlx4_core: Prevent VF from changing port configuration
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / fw.c
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
51a379d0 3 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 4 * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
5cc914f1 35#include <linux/etherdevice.h>
225c7b1f 36#include <linux/mlx4/cmd.h>
9d9779e7 37#include <linux/module.h>
c57e20dc 38#include <linux/cache.h>
225c7b1f
RD		 39
40#include "fw.h"
41#include "icm.h"
42
fe40900f 43enum {
5ae2a7a8
RD		 44 MLX4_COMMAND_INTERFACE_MIN_REV = 2,
45 MLX4_COMMAND_INTERFACE_MAX_REV = 3,
46 MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3,
fe40900f
RD		 47};
48
225c7b1f
RD		 49extern void __buggy_use_of_MLX4_GET(void);
50extern void __buggy_use_of_MLX4_PUT(void);
51
eb939922 52static bool enable_qos;
51f5f0ee
JM		 53module_param(enable_qos, bool, 0444);
54MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)");
55
225c7b1f
RD		 56#define MLX4_GET(dest, source, offset) \
57 do { \
58 void *__p = (char *) (source) + (offset); \
59 switch (sizeof (dest)) { \
60 case 1: (dest) = *(u8 *) __p; break; \
61 case 2: (dest) = be16_to_cpup(__p); break; \
62 case 4: (dest) = be32_to_cpup(__p); break; \
63 case 8: (dest) = be64_to_cpup(__p); break; \
64 default: __buggy_use_of_MLX4_GET(); \
65 } \
66 } while (0)
67
68#define MLX4_PUT(dest, source, offset) \
69 do { \
70 void *__d = ((char *) (dest) + (offset)); \
71 switch (sizeof(source)) { \
72 case 1: *(u8 *) __d = (source); break; \
73 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
74 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
75 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
76 default: __buggy_use_of_MLX4_PUT(); \
77 } \
78 } while (0)
79
52eafc68 80static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags)
225c7b1f
RD		 81{
82 static const char *fname[] = {
83 [ 0] = "RC transport",
84 [ 1] = "UC transport",
85 [ 2] = "UD transport",
ea98054f 86 [ 3] = "XRC transport",
225c7b1f
RD		 87 [ 4] = "reliable multicast",
88 [ 5] = "FCoIB support",
89 [ 6] = "SRQ support",
90 [ 7] = "IPoIB checksum offload",
91 [ 8] = "P_Key violation counter",
92 [ 9] = "Q_Key violation counter",
93 [10] = "VMM",
4d531aa8 94 [12] = "Dual Port Different Protocol (DPDP) support",
417608c2 95 [15] = "Big LSO headers",
225c7b1f
RD		 96 [16] = "MW support",
97 [17] = "APM support",
98 [18] = "Atomic ops support",
99 [19] = "Raw multicast support",
100 [20] = "Address vector port checking support",
101 [21] = "UD multicast support",
102 [24] = "Demand paging support",
96dfa684 103 [25] = "Router support",
ccf86321
OG		 104 [30] = "IBoE support",
105 [32] = "Unicast loopback support",
f3a9d1f2 106 [34] = "FCS header control",
ccf86321
OG		 107 [38] = "Wake On LAN support",
108 [40] = "UDP RSS support",
109 [41] = "Unicast VEP steering support",
f2a3f6a3
OG		 110 [42] = "Multicast VEP steering support",
111 [48] = "Counters support",
540b3a39 112 [53] = "Port ETS Scheduler support",
4d531aa8 113 [55] = "Port link type sensing support",
00f5ce99 114 [59] = "Port management change event support",
08ff3235
OG		 115 [61] = "64 byte EQE support",
116 [62] = "64 byte CQE support",
225c7b1f
RD		 117 };
118 int i;
119
120 mlx4_dbg(dev, "DEV_CAP flags:\n");
23c15c21 121 for (i = 0; i < ARRAY_SIZE(fname); ++i)
52eafc68 122 if (fname[i] && (flags & (1LL << i)))
225c7b1f
RD		 123 mlx4_dbg(dev, " %s\n", fname[i]);
124}
125
b3416f44
SP		 126static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags)
127{
128 static const char * const fname[] = {
129 [0] = "RSS support",
130 [1] = "RSS Toeplitz Hash Function support",
0ff1fb65 131 [2] = "RSS XOR Hash Function support",
56cb4567 132 [3] = "Device managed flow steering support",
d998735f 133 [4] = "Automatic MAC reassignment support",
4e8cf5b8
OG		 134 [5] = "Time stamping support",
135 [6] = "VST (control vlan insertion/stripping) support",
b01978ca 136 [7] = "FSM (MAC anti-spoofing) support",
7ffdf726 137 [8] = "Dynamic QP updates support",
56cb4567 138 [9] = "Device managed flow steering IPoIB support",
114840c3 139 [10] = "TCP/IP offloads/flow-steering for VXLAN support",
77507aa2
IS		 140 [11] = "MAD DEMUX (Secure-Host) support",
141 [12] = "Large cache line (>64B) CQE stride support",
adbc7ac5 142 [13] = "Large cache line (>64B) EQE stride support",
a53e3e8c
SM		 143 [14] = "Ethernet protocol control support",
144 [15] = "Ethernet Backplane autoneg support"
b3416f44
SP		 145 };
146 int i;
147
148 for (i = 0; i < ARRAY_SIZE(fname); ++i)
149 if (fname[i] && (flags & (1LL << i)))
150 mlx4_dbg(dev, " %s\n", fname[i]);
151}
152
2d928651
VS		 153int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg)
154{
155 struct mlx4_cmd_mailbox *mailbox;
156 u32 *inbox;
157 int err = 0;
158
159#define MOD_STAT_CFG_IN_SIZE 0x100
160
161#define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002
162#define MOD_STAT_CFG_PG_SZ_OFFSET 0x003
163
164 mailbox = mlx4_alloc_cmd_mailbox(dev);
165 if (IS_ERR(mailbox))
166 return PTR_ERR(mailbox);
167 inbox = mailbox->buf;
168
2d928651
VS		 169 MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET);
170 MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET);
171
172 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG,
f9baff50 173 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
2d928651
VS		 174
175 mlx4_free_cmd_mailbox(dev, mailbox);
176 return err;
177}
178
5cc914f1
MA		 179int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave,
180 struct mlx4_vhcr *vhcr,
181 struct mlx4_cmd_mailbox *inbox,
182 struct mlx4_cmd_mailbox *outbox,
183 struct mlx4_cmd_info *cmd)
184{
5a0d0a61 185 struct mlx4_priv *priv = mlx4_priv(dev);
99ec41d0
JM		 186 u8 field, port;
187 u32 size, proxy_qp, qkey;
5cc914f1
MA		 188 int err = 0;
189
190#define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0
191#define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1
5cc914f1 192#define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4
105c320f 193#define QUERY_FUNC_CAP_FMR_OFFSET 0x8
eb456a68
JM		 194#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10
195#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14
196#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18
197#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20
198#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24
199#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28
5cc914f1 200#define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c
69612b9f 201#define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30
5cc914f1 202
eb456a68
JM		 203#define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50
204#define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54
205#define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58
206#define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60
207#define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64
208#define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68
209
105c320f
JM		 210#define QUERY_FUNC_CAP_FMR_FLAG 0x80
211#define QUERY_FUNC_CAP_FLAG_RDMA 0x40
212#define QUERY_FUNC_CAP_FLAG_ETH 0x80
eb456a68 213#define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10
105c320f
JM		 214
215/* when opcode modifier = 1 */
5cc914f1 216#define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3
99ec41d0 217#define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4
73e74ab4
HHZ		 218#define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8
219#define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc
5cc914f1 220
47605df9
JM		 221#define QUERY_FUNC_CAP_QP0_TUNNEL 0x10
222#define QUERY_FUNC_CAP_QP0_PROXY 0x14
223#define QUERY_FUNC_CAP_QP1_TUNNEL 0x18
224#define QUERY_FUNC_CAP_QP1_PROXY 0x1c
8e1a28e8 225#define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28
47605df9 226
73e74ab4
HHZ		 227#define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40
228#define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80
eb17711b 229#define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10
99ec41d0 230#define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08
105c320f 231
73e74ab4 232#define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80
105c320f 233
5cc914f1 234 if (vhcr->op_modifier == 1) {
449fc488
MB		 235 struct mlx4_active_ports actv_ports =
236 mlx4_get_active_ports(dev, slave);
237 int converted_port = mlx4_slave_convert_port(
238 dev, slave, vhcr->in_modifier);
239
240 if (converted_port < 0)
241 return -EINVAL;
242
243 vhcr->in_modifier = converted_port;
449fc488
MB		 244 /* phys-port = logical-port */
245 field = vhcr->in_modifier -
246 find_first_bit(actv_ports.ports, dev->caps.num_ports);
47605df9
JM		 247 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
248
99ec41d0
JM		 249 port = vhcr->in_modifier;
250 proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1;
251
252 /* Set nic_info bit to mark new fields support */
253 field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO;
254
255 if (mlx4_vf_smi_enabled(dev, slave, port) &&
256 !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) {
257 field |= QUERY_FUNC_CAP_VF_ENABLE_QP0;
258 MLX4_PUT(outbox->buf, qkey,
259 QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
260 }
261 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
262
47605df9 263 /* size is now the QP number */
99ec41d0 264 size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1;
47605df9
JM		 265 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
266
267 size += 2;
268 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
269
99ec41d0
JM		 270 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
271 proxy_qp += 2;
272 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
47605df9 273
8e1a28e8
HHZ		 274 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
275 QUERY_FUNC_CAP_PHYS_PORT_ID);
276
5cc914f1 277 } else if (vhcr->op_modifier == 0) {
449fc488
MB		 278 struct mlx4_active_ports actv_ports =
279 mlx4_get_active_ports(dev, slave);
eb456a68
JM		 280 /* enable rdma and ethernet interfaces, and new quota locations */
281 field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA |
282 QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1
MA		 283 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
284
449fc488
MB		 285 field = min(
286 bitmap_weight(actv_ports.ports, dev->caps.num_ports),
287 dev->caps.num_ports);
5cc914f1
MA		 288 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
289
08ff3235 290 size = dev->caps.function_caps; /* set PF behaviours */
5cc914f1
MA		 291 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
292
105c320f
JM		 293 field = 0; /* protected FMR support not available as yet */
294 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
295
5a0d0a61 296 size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave];
5cc914f1 297 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
eb456a68
JM		 298 size = dev->caps.num_qps;
299 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
5cc914f1 300
5a0d0a61 301 size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave];
5cc914f1 302 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
eb456a68
JM		 303 size = dev->caps.num_srqs;
304 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
5cc914f1 305
5a0d0a61 306 size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave];
5cc914f1 307 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
eb456a68
JM		 308 size = dev->caps.num_cqs;
309 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
5cc914f1
MA		 310
311 size = dev->caps.num_eqs;
312 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
313
314 size = dev->caps.reserved_eqs;
315 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
316
5a0d0a61 317 size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave];
5cc914f1 318 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
eb456a68
JM		 319 size = dev->caps.num_mpts;
320 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
5cc914f1 321
5a0d0a61 322 size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave];
5cc914f1 323 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
eb456a68
JM		 324 size = dev->caps.num_mtts;
325 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
5cc914f1
MA		 326
327 size = dev->caps.num_mgms + dev->caps.num_amgms;
328 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
eb456a68 329 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
5cc914f1
MA		 330
331 } else
332 err = -EINVAL;
333
334 return err;
335}
336
47605df9
JM		 337int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port,
338 struct mlx4_func_cap *func_cap)
5cc914f1
MA		 339{
340 struct mlx4_cmd_mailbox *mailbox;
341 u32 *outbox;
47605df9 342 u8 field, op_modifier;
99ec41d0 343 u32 size, qkey;
eb456a68 344 int err = 0, quotas = 0;
5cc914f1 345
47605df9 346 op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */
5cc914f1
MA		 347
348 mailbox = mlx4_alloc_cmd_mailbox(dev);
349 if (IS_ERR(mailbox))
350 return PTR_ERR(mailbox);
351
47605df9
JM		 352 err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier,
353 MLX4_CMD_QUERY_FUNC_CAP,
5cc914f1
MA		 354 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
355 if (err)
356 goto out;
357
358 outbox = mailbox->buf;
359
47605df9
JM		 360 if (!op_modifier) {
361 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
362 if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) {
363 mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n");
364 err = -EPROTONOSUPPORT;
365 goto out;
366 }
367 func_cap->flags = field;
eb456a68 368 quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS);
5cc914f1 369
47605df9
JM		 370 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
371 func_cap->num_ports = field;
5cc914f1 372
47605df9
JM		 373 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
374 func_cap->pf_context_behaviour = size;
5cc914f1 375
eb456a68
JM		 376 if (quotas) {
377 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
378 func_cap->qp_quota = size & 0xFFFFFF;
379
380 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
381 func_cap->srq_quota = size & 0xFFFFFF;
382
383 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
384 func_cap->cq_quota = size & 0xFFFFFF;
385
386 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
387 func_cap->mpt_quota = size & 0xFFFFFF;
388
389 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
390 func_cap->mtt_quota = size & 0xFFFFFF;
391
392 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
393 func_cap->mcg_quota = size & 0xFFFFFF;
5cc914f1 394
eb456a68
JM		 395 } else {
396 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
397 func_cap->qp_quota = size & 0xFFFFFF;
5cc914f1 398
eb456a68
JM		 399 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
400 func_cap->srq_quota = size & 0xFFFFFF;
5cc914f1 401
eb456a68
JM		 402 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
403 func_cap->cq_quota = size & 0xFFFFFF;
404
405 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
406 func_cap->mpt_quota = size & 0xFFFFFF;
407
408 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
409 func_cap->mtt_quota = size & 0xFFFFFF;
410
411 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
412 func_cap->mcg_quota = size & 0xFFFFFF;
413 }
47605df9
JM		 414 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
415 func_cap->max_eq = size & 0xFFFFFF;
5cc914f1 416
47605df9
JM		 417 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
418 func_cap->reserved_eq = size & 0xFFFFFF;
5cc914f1 419
47605df9
JM		 420 goto out;
421 }
5cc914f1 422
47605df9
JM		 423 /* logical port query */
424 if (gen_or_port > dev->caps.num_ports) {
425 err = -EINVAL;
426 goto out;
427 }
5cc914f1 428
eb17711b 429 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
47605df9 430 if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) {
bc82878b 431 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) {
47605df9
JM		 432 mlx4_err(dev, "VLAN is enforced on this port\n");
433 err = -EPROTONOSUPPORT;
5cc914f1 434 goto out;
47605df9 435 }
5cc914f1 436
eb17711b 437 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) {
47605df9
JM		 438 mlx4_err(dev, "Force mac is enabled on this port\n");
439 err = -EPROTONOSUPPORT;
440 goto out;
5cc914f1 441 }
47605df9 442 } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) {
73e74ab4
HHZ		 443 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
444 if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) {
1a91de28 445 mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n");
47605df9
JM		 446 err = -EPROTONOSUPPORT;
447 goto out;
448 }
449 }
5cc914f1 450
47605df9
JM		 451 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
452 func_cap->physical_port = field;
453 if (func_cap->physical_port != gen_or_port) {
454 err = -ENOSYS;
455 goto out;
5cc914f1
MA		 456 }
457
99ec41d0
JM		 458 if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) {
459 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
460 func_cap->qp0_qkey = qkey;
461 } else {
462 func_cap->qp0_qkey = 0;
463 }
464
47605df9
JM		 465 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
466 func_cap->qp0_tunnel_qpn = size & 0xFFFFFF;
467
468 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
469 func_cap->qp0_proxy_qpn = size & 0xFFFFFF;
470
471 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
472 func_cap->qp1_tunnel_qpn = size & 0xFFFFFF;
473
474 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
475 func_cap->qp1_proxy_qpn = size & 0xFFFFFF;
476
8e1a28e8
HHZ		 477 if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO)
478 MLX4_GET(func_cap->phys_port_id, outbox,
479 QUERY_FUNC_CAP_PHYS_PORT_ID);
480
5cc914f1
MA		 481 /* All other resources are allocated by the master, but we still report
482 * 'num' and 'reserved' capabilities as follows:
483 * - num remains the maximum resource index
484 * - 'num - reserved' is the total available objects of a resource, but
485 * resource indices may be less than 'reserved'
486 * TODO: set per-resource quotas */
487
488out:
489 mlx4_free_cmd_mailbox(dev, mailbox);
490
491 return err;
492}
493
225c7b1f
RD		 494int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
495{
496 struct mlx4_cmd_mailbox *mailbox;
497 u32 *outbox;
498 u8 field;
ccf86321 499 u32 field32, flags, ext_flags;
225c7b1f
RD		 500 u16 size;
501 u16 stat_rate;
502 int err;
5ae2a7a8 503 int i;
225c7b1f
RD		 504
505#define QUERY_DEV_CAP_OUT_SIZE 0x100
506#define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10
507#define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11
508#define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12
509#define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13
510#define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14
511#define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15
512#define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16
513#define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17
514#define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19
515#define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a
516#define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b
517#define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d
518#define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e
519#define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f
520#define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20
521#define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21
522#define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22
523#define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23
524#define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27
525#define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29
526#define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b
b832be1e 527#define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d
b3416f44 528#define QUERY_DEV_CAP_RSS_OFFSET 0x2e
225c7b1f
RD		 529#define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f
530#define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33
531#define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35
532#define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36
533#define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37
149983af 534#define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38
225c7b1f
RD		 535#define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b
536#define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c
d998735f 537#define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e
225c7b1f 538#define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f
ccf86321 539#define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40
225c7b1f
RD		 540#define QUERY_DEV_CAP_FLAGS_OFFSET 0x44
541#define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48
542#define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49
543#define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b
544#define QUERY_DEV_CAP_BF_OFFSET 0x4c
545#define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d
546#define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e
547#define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f
548#define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51
549#define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52
550#define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55
551#define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56
552#define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61
553#define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62
554#define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63
555#define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64
556#define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65
012a8ff5
SH		 557#define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66
558#define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67
f2a3f6a3 559#define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68
3f7fb021 560#define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70
4de65803 561#define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74
0ff1fb65
HHZ		 562#define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76
563#define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77
77507aa2 564#define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a
adbc7ac5 565#define QUERY_DEV_CAP_ETH_PROT_CTRL_OFFSET 0x7a
225c7b1f
RD		 566#define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80
567#define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82
568#define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84
569#define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86
570#define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88
571#define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a
572#define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c
573#define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e
574#define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90
575#define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92
95d04f07 576#define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94
225c7b1f
RD		 577#define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98
578#define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0
a53e3e8c 579#define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c
955154fa 580#define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d
7ffdf726 581#define QUERY_DEV_CAP_VXLAN 0x9e
114840c3 582#define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0
225c7b1f 583
b3416f44 584 dev_cap->flags2 = 0;
225c7b1f
RD		 585 mailbox = mlx4_alloc_cmd_mailbox(dev);
586 if (IS_ERR(mailbox))
587 return PTR_ERR(mailbox);
588 outbox = mailbox->buf;
589
590 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
401453a3 591 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 592 if (err)
593 goto out;
594
595 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
596 dev_cap->reserved_qps = 1 << (field & 0xf);
597 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
598 dev_cap->max_qps = 1 << (field & 0x1f);
599 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
600 dev_cap->reserved_srqs = 1 << (field >> 4);
601 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
602 dev_cap->max_srqs = 1 << (field & 0x1f);
603 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
604 dev_cap->max_cq_sz = 1 << field;
605 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
606 dev_cap->reserved_cqs = 1 << (field & 0xf);
607 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
608 dev_cap->max_cqs = 1 << (field & 0x1f);
609 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
610 dev_cap->max_mpts = 1 << (field & 0x3f);
611 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
be504b0b 612 dev_cap->reserved_eqs = field & 0xf;
225c7b1f 613 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
5920869f 614 dev_cap->max_eqs = 1 << (field & 0xf);
225c7b1f
RD		 615 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
616 dev_cap->reserved_mtts = 1 << (field >> 4);
617 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET);
618 dev_cap->max_mrw_sz = 1 << field;
619 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
620 dev_cap->reserved_mrws = 1 << (field & 0xf);
621 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET);
622 dev_cap->max_mtt_seg = 1 << (field & 0x3f);
623 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
624 dev_cap->max_requester_per_qp = 1 << (field & 0x3f);
625 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
626 dev_cap->max_responder_per_qp = 1 << (field & 0x3f);
b832be1e
EC		 627 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
628 field &= 0x1f;
629 if (!field)
630 dev_cap->max_gso_sz = 0;
631 else
632 dev_cap->max_gso_sz = 1 << field;
633
b3416f44
SP		 634 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
635 if (field & 0x20)
636 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR;
637 if (field & 0x10)
638 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP;
639 field &= 0xf;
640 if (field) {
641 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS;
642 dev_cap->max_rss_tbl_sz = 1 << field;
643 } else
644 dev_cap->max_rss_tbl_sz = 0;
225c7b1f
RD		 645 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
646 dev_cap->max_rdma_global = 1 << (field & 0x3f);
647 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
648 dev_cap->local_ca_ack_delay = field & 0x1f;
225c7b1f 649 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
225c7b1f 650 dev_cap->num_ports = field & 0xf;
149983af
DB		 651 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
652 dev_cap->max_msg_sz = 1 << (field & 0x1f);
0ff1fb65
HHZ		 653 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
654 if (field & 0x80)
655 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN;
656 dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f;
4de65803
MB		 657 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
658 if (field & 0x80)
659 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB;
0ff1fb65
HHZ		 660 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
661 dev_cap->fs_max_num_qp_per_entry = field;
225c7b1f
RD		 662 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
663 dev_cap->stat_rate_support = stat_rate;
d998735f
EE		 664 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
665 if (field & 0x80)
666 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS;
ccf86321 667 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
52eafc68 668 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
ccf86321 669 dev_cap->flags = flags | (u64)ext_flags << 32;
225c7b1f
RD		 670 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
671 dev_cap->reserved_uars = field >> 4;
672 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
673 dev_cap->uar_size = 1 << ((field & 0x3f) + 20);
674 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
675 dev_cap->min_page_sz = 1 << field;
676
677 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
678 if (field & 0x80) {
679 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
680 dev_cap->bf_reg_size = 1 << (field & 0x1f);
681 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
f5a49539 682 if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size))
58d74bb1 683 field = 3;
225c7b1f
RD		 684 dev_cap->bf_regs_per_page = 1 << (field & 0x3f);
685 mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n",
686 dev_cap->bf_reg_size, dev_cap->bf_regs_per_page);
687 } else {
688 dev_cap->bf_reg_size = 0;
689 mlx4_dbg(dev, "BlueFlame not available\n");
690 }
691
692 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
693 dev_cap->max_sq_sg = field;
694 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
695 dev_cap->max_sq_desc_sz = size;
696
697 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
698 dev_cap->max_qp_per_mcg = 1 << field;
699 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
700 dev_cap->reserved_mgms = field & 0xf;
701 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
702 dev_cap->max_mcgs = 1 << field;
703 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
704 dev_cap->reserved_pds = field >> 4;
705 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
706 dev_cap->max_pds = 1 << (field & 0x3f);
012a8ff5
SH		 707 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
708 dev_cap->reserved_xrcds = field >> 4;
426dd00d 709 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
012a8ff5 710 dev_cap->max_xrcds = 1 << (field & 0x1f);
225c7b1f
RD		 711
712 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
713 dev_cap->rdmarc_entry_sz = size;
714 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
715 dev_cap->qpc_entry_sz = size;
716 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
717 dev_cap->aux_entry_sz = size;
718 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
719 dev_cap->altc_entry_sz = size;
720 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
721 dev_cap->eqc_entry_sz = size;
722 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
723 dev_cap->cqc_entry_sz = size;
724 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
725 dev_cap->srq_entry_sz = size;
726 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
727 dev_cap->cmpt_entry_sz = size;
728 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
729 dev_cap->mtt_entry_sz = size;
730 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
731 dev_cap->dmpt_entry_sz = size;
732
733 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
734 dev_cap->max_srq_sz = 1 << field;
735 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
736 dev_cap->max_qp_sz = 1 << field;
737 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
738 dev_cap->resize_srq = field & 1;
739 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
740 dev_cap->max_rq_sg = field;
741 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
742 dev_cap->max_rq_desc_sz = size;
77507aa2 743 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
adbc7ac5
SM		 744 if (field & (1 << 5))
745 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL;
77507aa2
IS		 746 if (field & (1 << 6))
747 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
748 if (field & (1 << 7))
749 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
225c7b1f
RD		 750 MLX4_GET(dev_cap->bmme_flags, outbox,
751 QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
752 MLX4_GET(dev_cap->reserved_lkey, outbox,
753 QUERY_DEV_CAP_RSVD_LKEY_OFFSET);
a53e3e8c
SM		 754 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
755 if (field32 & (1 << 0))
756 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP;
955154fa
MB		 757 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
758 if (field & 1<<6)
5930e8d0 759 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN;
7ffdf726
OG		 760 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
761 if (field & 1<<3)
762 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS;
225c7b1f
RD		 763 MLX4_GET(dev_cap->max_icm_sz, outbox,
764 QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET);
f2a3f6a3
OG		 765 if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS)
766 MLX4_GET(dev_cap->max_counters, outbox,
767 QUERY_DEV_CAP_MAX_COUNTERS_OFFSET);
225c7b1f 768
114840c3
JM		 769 MLX4_GET(field32, outbox,
770 QUERY_DEV_CAP_MAD_DEMUX_OFFSET);
771 if (field32 & (1 << 0))
772 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX;
773
3f7fb021 774 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
b01978ca
JM		 775 if (field32 & (1 << 16))
776 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP;
3f7fb021
RE		 777 if (field32 & (1 << 26))
778 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL;
e6b6a231
RE		 779 if (field32 & (1 << 20))
780 dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM;
3f7fb021 781
5ae2a7a8
RD		 782 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
783 for (i = 1; i <= dev_cap->num_ports; ++i) {
784 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
785 dev_cap->max_vl[i] = field >> 4;
786 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
b79acb49 787 dev_cap->ib_mtu[i] = field >> 4;
5ae2a7a8
RD		 788 dev_cap->max_port_width[i] = field & 0xf;
789 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
790 dev_cap->max_gids[i] = 1 << (field & 0xf);
791 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
792 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
793 }
794 } else {
7ff93f8b 795#define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00
5ae2a7a8 796#define QUERY_PORT_MTU_OFFSET 0x01
b79acb49 797#define QUERY_PORT_ETH_MTU_OFFSET 0x02
5ae2a7a8
RD		 798#define QUERY_PORT_WIDTH_OFFSET 0x06
799#define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07
93fc9e1b 800#define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a
5ae2a7a8 801#define QUERY_PORT_MAX_VL_OFFSET 0x0b
e65b9591 802#define QUERY_PORT_MAC_OFFSET 0x10
7699517d
YP		 803#define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18
804#define QUERY_PORT_WAVELENGTH_OFFSET 0x1c
805#define QUERY_PORT_TRANS_CODE_OFFSET 0x20
5ae2a7a8
RD		 806
807 for (i = 1; i <= dev_cap->num_ports; ++i) {
808 err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT,
401453a3 809 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
5ae2a7a8
RD		 810 if (err)
811 goto out;
812
7ff93f8b
YP		 813 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
814 dev_cap->supported_port_types[i] = field & 3;
8d0fc7b6
YP		 815 dev_cap->suggested_type[i] = (field >> 3) & 1;
816 dev_cap->default_sense[i] = (field >> 4) & 1;
5ae2a7a8 817 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
b79acb49 818 dev_cap->ib_mtu[i] = field & 0xf;
5ae2a7a8
RD		 819 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
820 dev_cap->max_port_width[i] = field & 0xf;
821 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
822 dev_cap->max_gids[i] = 1 << (field >> 4);
823 dev_cap->max_pkeys[i] = 1 << (field & 0xf);
824 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
825 dev_cap->max_vl[i] = field & 0xf;
93fc9e1b
YP		 826 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
827 dev_cap->log_max_macs[i] = field & 0xf;
828 dev_cap->log_max_vlans[i] = field >> 4;
b79acb49
YP		 829 MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET);
830 MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET);
7699517d
YP		 831 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
832 dev_cap->trans_type[i] = field32 >> 24;
833 dev_cap->vendor_oui[i] = field32 & 0xffffff;
834 MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET);
835 MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET);
5ae2a7a8
RD		 836 }
837 }
838
95d04f07
RD		 839 mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n",
840 dev_cap->bmme_flags, dev_cap->reserved_lkey);
225c7b1f
RD		 841
842 /*
843 * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then
844 * we can't use any EQs whose doorbell falls on that page,
845 * even if the EQ itself isn't reserved.
846 */
847 dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4,
848 dev_cap->reserved_eqs);
849
850 mlx4_dbg(dev, "Max ICM size %lld MB\n",
851 (unsigned long long) dev_cap->max_icm_sz >> 20);
852 mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
853 dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz);
854 mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
855 dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz);
856 mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
857 dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz);
858 mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
859 dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz);
860 mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n",
861 dev_cap->reserved_mrws, dev_cap->reserved_mtts);
862 mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
863 dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars);
864 mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n",
865 dev_cap->max_pds, dev_cap->reserved_mgms);
866 mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
867 dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz);
868 mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n",
b79acb49 869 dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1],
5ae2a7a8 870 dev_cap->max_port_width[1]);
225c7b1f
RD		 871 mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n",
872 dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg);
873 mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n",
874 dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg);
b832be1e 875 mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz);
f2a3f6a3 876 mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters);
b3416f44 877 mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz);
225c7b1f
RD		 878
879 dump_dev_cap_flags(dev, dev_cap->flags);
b3416f44 880 dump_dev_cap_flags2(dev, dev_cap->flags2);
225c7b1f
RD		 881
882out:
883 mlx4_free_cmd_mailbox(dev, mailbox);
884 return err;
885}
886
b91cb3eb
JM		 887int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave,
888 struct mlx4_vhcr *vhcr,
889 struct mlx4_cmd_mailbox *inbox,
890 struct mlx4_cmd_mailbox *outbox,
891 struct mlx4_cmd_info *cmd)
892{
2a4fae14 893 u64 flags;
b91cb3eb
JM		 894 int err = 0;
895 u8 field;
cc1ade94 896 u32 bmme_flags;
449fc488
MB		 897 int real_port;
898 int slave_port;
899 int first_port;
900 struct mlx4_active_ports actv_ports;
b91cb3eb
JM		 901
902 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
903 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
904 if (err)
905 return err;
906
cc1ade94
SM		 907 /* add port mng change event capability and disable mw type 1
908 * unconditionally to slaves
909 */
2a4fae14
JM		 910 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
911 flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV;
cc1ade94 912 flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW;
449fc488
MB		 913 actv_ports = mlx4_get_active_ports(dev, slave);
914 first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
915 for (slave_port = 0, real_port = first_port;
916 real_port < first_port +
917 bitmap_weight(actv_ports.ports, dev->caps.num_ports);
918 ++real_port, ++slave_port) {
919 if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port))
920 flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port;
921 else
922 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
923 }
924 for (; slave_port < dev->caps.num_ports; ++slave_port)
925 flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port);
2a4fae14
JM		 926 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
927
449fc488
MB		 928 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
929 field &= ~0x0F;
930 field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F;
931 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
932
30b40c31
AV		 933 /* For guests, disable timestamp */
934 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
935 field &= 0x7f;
936 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
937
7ffdf726 938 /* For guests, disable vxlan tunneling */
57352ef4 939 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
7ffdf726
OG		 940 field &= 0xf7;
941 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
942
b91cb3eb
JM		 943 /* For guests, report Blueflame disabled */
944 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
945 field &= 0x7f;
946 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
947
cc1ade94 948 /* For guests, disable mw type 2 */
57352ef4 949 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
cc1ade94
SM		 950 bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN;
951 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
952
0081c8f3
JM		 953 /* turn off device-managed steering capability if not enabled */
954 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
955 MLX4_GET(field, outbox->buf,
956 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
957 field &= 0x7f;
958 MLX4_PUT(outbox->buf, field,
959 QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
960 }
4de65803
MB		 961
962 /* turn off ipoib managed steering for guests */
57352ef4 963 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
4de65803
MB		 964 field &= ~0x80;
965 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
966
b91cb3eb
JM		 967 return 0;
968}
969
5cc914f1
MA		 970int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
971 struct mlx4_vhcr *vhcr,
972 struct mlx4_cmd_mailbox *inbox,
973 struct mlx4_cmd_mailbox *outbox,
974 struct mlx4_cmd_info *cmd)
975{
0eb62b93 976 struct mlx4_priv *priv = mlx4_priv(dev);
5cc914f1
MA		 977 u64 def_mac;
978 u8 port_type;
6634961c 979 u16 short_field;
5cc914f1 980 int err;
948e306d 981 int admin_link_state;
449fc488
MB		 982 int port = mlx4_slave_convert_port(dev, slave,
983 vhcr->in_modifier & 0xFF);
5cc914f1 984
105c320f 985#define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0
948e306d 986#define MLX4_PORT_LINK_UP_MASK 0x80
6634961c
JM		 987#define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c
988#define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e
95f56e7a 989
449fc488
MB		 990 if (port < 0)
991 return -EINVAL;
992
a7401b9c
JM		 993 /* Protect against untrusted guests: enforce that this is the
994 * QUERY_PORT general query.
995 */
996 if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF)
997 return -EINVAL;
998
999 vhcr->in_modifier = port;
449fc488 1000
5cc914f1
MA		 1001 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1002 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1003 MLX4_CMD_NATIVE);
1004
1005 if (!err && dev->caps.function != slave) {
0508ad64 1006 def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
5cc914f1
MA		 1007 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1008
1009 /* get port type - currently only eth is enabled */
1010 MLX4_GET(port_type, outbox->buf,
1011 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1012
105c320f
JM		 1013 /* No link sensing allowed */
1014 port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK;
1015 /* set port type to currently operating port type */
1016 port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3);
5cc914f1 1017
948e306d
RE		 1018 admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state;
1019 if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state)
1020 port_type |= MLX4_PORT_LINK_UP_MASK;
1021 else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state)
1022 port_type &= ~MLX4_PORT_LINK_UP_MASK;
1023
5cc914f1
MA		 1024 MLX4_PUT(outbox->buf, port_type,
1025 QUERY_PORT_SUPPORTED_TYPE_OFFSET);
6634961c 1026
b6ffaeff 1027 if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH)
449fc488 1028 short_field = mlx4_get_slave_num_gids(dev, slave, port);
b6ffaeff
JM		 1029 else
1030 short_field = 1; /* slave max gids */
6634961c
JM		 1031 MLX4_PUT(outbox->buf, short_field,
1032 QUERY_PORT_CUR_MAX_GID_OFFSET);
1033
1034 short_field = dev->caps.pkey_table_len[vhcr->in_modifier];
1035 MLX4_PUT(outbox->buf, short_field,
1036 QUERY_PORT_CUR_MAX_PKEY_OFFSET);
5cc914f1
MA		 1037 }
1038
1039 return err;
1040}
1041
6634961c
JM		 1042int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port,
1043 int *gid_tbl_len, int *pkey_tbl_len)
1044{
1045 struct mlx4_cmd_mailbox *mailbox;
1046 u32 *outbox;
1047 u16 field;
1048 int err;
1049
1050 mailbox = mlx4_alloc_cmd_mailbox(dev);
1051 if (IS_ERR(mailbox))
1052 return PTR_ERR(mailbox);
1053
1054 err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0,
1055 MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
1056 MLX4_CMD_WRAPPED);
1057 if (err)
1058 goto out;
1059
1060 outbox = mailbox->buf;
1061
1062 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1063 *gid_tbl_len = field;
1064
1065 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1066 *pkey_tbl_len = field;
1067
1068out:
1069 mlx4_free_cmd_mailbox(dev, mailbox);
1070 return err;
1071}
1072EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len);
1073
225c7b1f
RD		 1074int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt)
1075{
1076 struct mlx4_cmd_mailbox *mailbox;
1077 struct mlx4_icm_iter iter;
1078 __be64 *pages;
1079 int lg;
1080 int nent = 0;
1081 int i;
1082 int err = 0;
1083 int ts = 0, tc = 0;
1084
1085 mailbox = mlx4_alloc_cmd_mailbox(dev);
1086 if (IS_ERR(mailbox))
1087 return PTR_ERR(mailbox);
225c7b1f
RD		 1088 pages = mailbox->buf;
1089
1090 for (mlx4_icm_first(icm, &iter);
1091 !mlx4_icm_last(&iter);
1092 mlx4_icm_next(&iter)) {
1093 /*
1094 * We have to pass pages that are aligned to their
1095 * size, so find the least significant 1 in the
1096 * address or size and use that as our log2 size.
1097 */
1098 lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1;
1099 if (lg < MLX4_ICM_PAGE_SHIFT) {
1a91de28
JP		 1100 mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n",
1101 MLX4_ICM_PAGE_SIZE,
1102 (unsigned long long) mlx4_icm_addr(&iter),
1103 mlx4_icm_size(&iter));
225c7b1f
RD		 1104 err = -EINVAL;
1105 goto out;
1106 }
1107
1108 for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) {
1109 if (virt != -1) {
1110 pages[nent * 2] = cpu_to_be64(virt);
1111 virt += 1 << lg;
1112 }
1113
1114 pages[nent * 2 + 1] =
1115 cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) |
1116 (lg - MLX4_ICM_PAGE_SHIFT));
1117 ts += 1 << (lg - 10);
1118 ++tc;
1119
1120 if (++nent == MLX4_MAILBOX_SIZE / 16) {
1121 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
f9baff50
JM		 1122 MLX4_CMD_TIME_CLASS_B,
1123 MLX4_CMD_NATIVE);
225c7b1f
RD		 1124 if (err)
1125 goto out;
1126 nent = 0;
1127 }
1128 }
1129 }
1130
1131 if (nent)
f9baff50
JM		 1132 err = mlx4_cmd(dev, mailbox->dma, nent, 0, op,
1133 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1134 if (err)
1135 goto out;
1136
1137 switch (op) {
1138 case MLX4_CMD_MAP_FA:
1a91de28 1139 mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts);
225c7b1f
RD		 1140 break;
1141 case MLX4_CMD_MAP_ICM_AUX:
1a91de28 1142 mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts);
225c7b1f
RD		 1143 break;
1144 case MLX4_CMD_MAP_ICM:
1a91de28
JP		 1145 mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n",
1146 tc, ts, (unsigned long long) virt - (ts << 10));
225c7b1f
RD		 1147 break;
1148 }
1149
1150out:
1151 mlx4_free_cmd_mailbox(dev, mailbox);
1152 return err;
1153}
1154
1155int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm)
1156{
1157 return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1);
1158}
1159
1160int mlx4_UNMAP_FA(struct mlx4_dev *dev)
1161{
f9baff50
JM		 1162 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA,
1163 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
225c7b1f
RD		 1164}
1165
1166
1167int mlx4_RUN_FW(struct mlx4_dev *dev)
1168{
f9baff50
JM		 1169 return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW,
1170 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1171}
1172
1173int mlx4_QUERY_FW(struct mlx4_dev *dev)
1174{
1175 struct mlx4_fw *fw = &mlx4_priv(dev)->fw;
1176 struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd;
1177 struct mlx4_cmd_mailbox *mailbox;
1178 u32 *outbox;
1179 int err = 0;
1180 u64 fw_ver;
fe40900f 1181 u16 cmd_if_rev;
225c7b1f
RD		 1182 u8 lg;
1183
1184#define QUERY_FW_OUT_SIZE 0x100
1185#define QUERY_FW_VER_OFFSET 0x00
5cc914f1 1186#define QUERY_FW_PPF_ID 0x09
fe40900f 1187#define QUERY_FW_CMD_IF_REV_OFFSET 0x0a
225c7b1f
RD		 1188#define QUERY_FW_MAX_CMD_OFFSET 0x0f
1189#define QUERY_FW_ERR_START_OFFSET 0x30
1190#define QUERY_FW_ERR_SIZE_OFFSET 0x38
1191#define QUERY_FW_ERR_BAR_OFFSET 0x3c
1192
1193#define QUERY_FW_SIZE_OFFSET 0x00
1194#define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
1195#define QUERY_FW_CLR_INT_BAR_OFFSET 0x28
1196
5cc914f1
MA		 1197#define QUERY_FW_COMM_BASE_OFFSET 0x40
1198#define QUERY_FW_COMM_BAR_OFFSET 0x48
1199
ddd8a6c1
EE		 1200#define QUERY_FW_CLOCK_OFFSET 0x50
1201#define QUERY_FW_CLOCK_BAR 0x58
1202
225c7b1f
RD		 1203 mailbox = mlx4_alloc_cmd_mailbox(dev);
1204 if (IS_ERR(mailbox))
1205 return PTR_ERR(mailbox);
1206 outbox = mailbox->buf;
1207
1208 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
f9baff50 1209 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1210 if (err)
1211 goto out;
1212
1213 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1214 /*
3e1db334 1215 * FW subminor version is at more significant bits than minor
225c7b1f
RD		 1216 * version, so swap here.
1217 */
1218 dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) |
1219 ((fw_ver & 0xffff0000ull) >> 16) |
1220 ((fw_ver & 0x0000ffffull) << 16);
1221
752a50ca
JM		 1222 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1223 dev->caps.function = lg;
1224
b91cb3eb
JM		 1225 if (mlx4_is_slave(dev))
1226 goto out;
1227
5cc914f1 1228
fe40900f 1229 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
5ae2a7a8
RD		 1230 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV ||
1231 cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) {
1a91de28 1232 mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n",
fe40900f
RD		 1233 cmd_if_rev);
1234 mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n",
1235 (int) (dev->caps.fw_ver >> 32),
1236 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1237 (int) dev->caps.fw_ver & 0xffff);
1a91de28 1238 mlx4_err(dev, "This driver version supports only revisions %d to %d\n",
5ae2a7a8 1239 MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV);
fe40900f
RD		 1240 err = -ENODEV;
1241 goto out;
1242 }
1243
5ae2a7a8
RD		 1244 if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS)
1245 dev->flags |= MLX4_FLAG_OLD_PORT_CMDS;
1246
225c7b1f
RD		 1247 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1248 cmd->max_cmds = 1 << lg;
1249
fe40900f 1250 mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n",
225c7b1f
RD		 1251 (int) (dev->caps.fw_ver >> 32),
1252 (int) (dev->caps.fw_ver >> 16) & 0xffff,
1253 (int) dev->caps.fw_ver & 0xffff,
fe40900f 1254 cmd_if_rev, cmd->max_cmds);
225c7b1f
RD		 1255
1256 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1257 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1258 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1259 fw->catas_bar = (fw->catas_bar >> 6) * 2;
1260
1261 mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n",
1262 (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar);
1263
1264 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1265 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1266 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1267 fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2;
1268
5cc914f1
MA		 1269 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1270 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1271 fw->comm_bar = (fw->comm_bar >> 6) * 2;
1272 mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n",
1273 fw->comm_bar, fw->comm_base);
225c7b1f
RD		 1274 mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2);
1275
ddd8a6c1
EE		 1276 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1277 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1278 fw->clock_bar = (fw->clock_bar >> 6) * 2;
1279 mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n",
1280 fw->clock_bar, fw->clock_offset);
1281
225c7b1f
RD		 1282 /*
1283 * Round up number of system pages needed in case
1284 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1285 */
1286 fw->fw_pages =
1287 ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1288 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1289
1290 mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n",
1291 (unsigned long long) fw->clr_int_base, fw->clr_int_bar);
1292
1293out:
1294 mlx4_free_cmd_mailbox(dev, mailbox);
1295 return err;
1296}
1297
b91cb3eb
JM		 1298int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave,
1299 struct mlx4_vhcr *vhcr,
1300 struct mlx4_cmd_mailbox *inbox,
1301 struct mlx4_cmd_mailbox *outbox,
1302 struct mlx4_cmd_info *cmd)
1303{
1304 u8 *outbuf;
1305 int err;
1306
1307 outbuf = outbox->buf;
1308 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1309 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1310 if (err)
1311 return err;
1312
752a50ca
JM		 1313 /* for slaves, set pci PPF ID to invalid and zero out everything
1314 * else except FW version */
b91cb3eb
JM		 1315 outbuf[0] = outbuf[1] = 0;
1316 memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8);
752a50ca
JM		 1317 outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID;
1318
b91cb3eb
JM		 1319 return 0;
1320}
1321
225c7b1f
RD		 1322static void get_board_id(void *vsd, char *board_id)
1323{
1324 int i;
1325
1326#define VSD_OFFSET_SIG1 0x00
1327#define VSD_OFFSET_SIG2 0xde
1328#define VSD_OFFSET_MLX_BOARD_ID 0xd0
1329#define VSD_OFFSET_TS_BOARD_ID 0x20
1330
1331#define VSD_SIGNATURE_TOPSPIN 0x5ad
1332
1333 memset(board_id, 0, MLX4_BOARD_ID_LEN);
1334
1335 if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN &&
1336 be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) {
1337 strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN);
1338 } else {
1339 /*
1340 * The board ID is a string but the firmware byte
1341 * swaps each 4-byte word before passing it back to
1342 * us. Therefore we need to swab it before printing.
1343 */
1344 for (i = 0; i < 4; ++i)
1345 ((u32 *) board_id)[i] =
1346 swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4));
1347 }
1348}
1349
1350int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter)
1351{
1352 struct mlx4_cmd_mailbox *mailbox;
1353 u32 *outbox;
1354 int err;
1355
1356#define QUERY_ADAPTER_OUT_SIZE 0x100
225c7b1f
RD		 1357#define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1358#define QUERY_ADAPTER_VSD_OFFSET 0x20
1359
1360 mailbox = mlx4_alloc_cmd_mailbox(dev);
1361 if (IS_ERR(mailbox))
1362 return PTR_ERR(mailbox);
1363 outbox = mailbox->buf;
1364
1365 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER,
f9baff50 1366 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1367 if (err)
1368 goto out;
1369
225c7b1f
RD		 1370 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1371
1372 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
1373 adapter->board_id);
1374
1375out:
1376 mlx4_free_cmd_mailbox(dev, mailbox);
1377 return err;
1378}
1379
1380int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param)
1381{
1382 struct mlx4_cmd_mailbox *mailbox;
1383 __be32 *inbox;
1384 int err;
1385
1386#define INIT_HCA_IN_SIZE 0x200
1387#define INIT_HCA_VERSION_OFFSET 0x000
1388#define INIT_HCA_VERSION 2
7ffdf726 1389#define INIT_HCA_VXLAN_OFFSET 0x0c
c57e20dc 1390#define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e
225c7b1f
RD		 1391#define INIT_HCA_FLAGS_OFFSET 0x014
1392#define INIT_HCA_QPC_OFFSET 0x020
1393#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1394#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1395#define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1396#define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1397#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1398#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
5cc914f1 1399#define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38)
77507aa2 1400#define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b)
225c7b1f
RD		 1401#define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1402#define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1403#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1404#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1405#define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1406#define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77)
1407#define INIT_HCA_MCAST_OFFSET 0x0c0
1408#define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1409#define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1410#define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1679200f 1411#define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18)
225c7b1f 1412#define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
0ff1fb65
HHZ		 1413#define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6
1414#define INIT_HCA_FS_PARAM_OFFSET 0x1d0
1415#define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00)
1416#define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12)
1417#define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b)
1418#define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21)
1419#define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22)
1420#define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25)
1421#define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26)
225c7b1f
RD		 1422#define INIT_HCA_TPT_OFFSET 0x0f0
1423#define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
e448834e 1424#define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08)
225c7b1f
RD		 1425#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1426#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1427#define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18)
1428#define INIT_HCA_UAR_OFFSET 0x120
1429#define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1430#define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1431
1432 mailbox = mlx4_alloc_cmd_mailbox(dev);
1433 if (IS_ERR(mailbox))
1434 return PTR_ERR(mailbox);
1435 inbox = mailbox->buf;
1436
225c7b1f
RD		 1437 *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION;
1438
c57e20dc
EC		 1439 *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) =
1440 (ilog2(cache_line_size()) - 4) << 5;
1441
225c7b1f
RD		 1442#if defined(__LITTLE_ENDIAN)
1443 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1);
1444#elif defined(__BIG_ENDIAN)
1445 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1);
1446#else
1447#error Host endianness not defined
1448#endif
1449 /* Check port for UD address vector: */
1450 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1);
1451
8ff095ec
EC		 1452 /* Enable IPoIB checksumming if we can: */
1453 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
1454 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3);
1455
51f5f0ee
JM		 1456 /* Enable QoS support if module parameter set */
1457 if (enable_qos)
1458 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2);
1459
f2a3f6a3
OG		 1460 /* enable counters */
1461 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)
1462 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4);
1463
08ff3235
OG		 1464 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1465 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) {
1466 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29);
1467 dev->caps.eqe_size = 64;
1468 dev->caps.eqe_factor = 1;
1469 } else {
1470 dev->caps.eqe_size = 32;
1471 dev->caps.eqe_factor = 0;
1472 }
1473
1474 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) {
1475 *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30);
1476 dev->caps.cqe_size = 64;
77507aa2 1477 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
08ff3235
OG		 1478 } else {
1479 dev->caps.cqe_size = 32;
1480 }
1481
77507aa2
IS		 1482 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1483 if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) &&
1484 (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) {
1485 dev->caps.eqe_size = cache_line_size();
1486 dev->caps.cqe_size = cache_line_size();
1487 dev->caps.eqe_factor = 0;
1488 MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 |
1489 (ilog2(dev->caps.eqe_size) - 5)),
1490 INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1491
1492 /* User still need to know to support CQE > 32B */
1493 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1494 }
1495
225c7b1f
RD		 1496 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1497
1498 MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET);
1499 MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET);
1500 MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET);
1501 MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET);
1502 MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET);
1503 MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET);
1504 MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET);
1505 MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET);
1506 MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET);
1507 MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET);
1508 MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET);
1509 MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET);
1510
0ff1fb65
HHZ		 1511 /* steering attributes */
1512 if (dev->caps.steering_mode ==
1513 MLX4_STEERING_MODE_DEVICE_MANAGED) {
1514 *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |=
1515 cpu_to_be32(1 <<
1516 INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN);
1517
1518 MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET);
1519 MLX4_PUT(inbox, param->log_mc_entry_sz,
1520 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1521 MLX4_PUT(inbox, param->log_mc_table_sz,
1522 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1523 /* Enable Ethernet flow steering
1524 * with udp unicast and tcp unicast
1525 */
23537b73 1526 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1527 INIT_HCA_FS_ETH_BITS_OFFSET);
1528 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1529 INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET);
1530 /* Enable IPoIB flow steering
1531 * with udp unicast and tcp unicast
1532 */
23537b73 1533 MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN),
0ff1fb65
HHZ		 1534 INIT_HCA_FS_IB_BITS_OFFSET);
1535 MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR,
1536 INIT_HCA_FS_IB_NUM_ADDRS_OFFSET);
1537 } else {
1538 MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET);
1539 MLX4_PUT(inbox, param->log_mc_entry_sz,
1540 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1541 MLX4_PUT(inbox, param->log_mc_hash_sz,
1542 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1543 MLX4_PUT(inbox, param->log_mc_table_sz,
1544 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1545 if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0)
1546 MLX4_PUT(inbox, (u8) (1 << 3),
1547 INIT_HCA_UC_STEERING_OFFSET);
1548 }
225c7b1f
RD		 1549
1550 /* TPT attributes */
1551
1552 MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1553 MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET);
225c7b1f
RD		 1554 MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET);
1555 MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET);
1556 MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET);
1557
1558 /* UAR attributes */
1559
ab9c17a0 1560 MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET);
225c7b1f
RD		 1561 MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET);
1562
7ffdf726
OG		 1563 /* set parser VXLAN attributes */
1564 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) {
1565 u8 parser_params = 0;
1566 MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET);
1567 }
1568
f9baff50
JM		 1569 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000,
1570 MLX4_CMD_NATIVE);
225c7b1f
RD		 1571
1572 if (err)
1573 mlx4_err(dev, "INIT_HCA returns %d\n", err);
1574
1575 mlx4_free_cmd_mailbox(dev, mailbox);
1576 return err;
1577}
1578
ab9c17a0
JM		 1579int mlx4_QUERY_HCA(struct mlx4_dev *dev,
1580 struct mlx4_init_hca_param *param)
1581{
1582 struct mlx4_cmd_mailbox *mailbox;
1583 __be32 *outbox;
7b8157be 1584 u32 dword_field;
ab9c17a0 1585 int err;
08ff3235 1586 u8 byte_field;
ab9c17a0
JM		 1587
1588#define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04
ddd8a6c1 1589#define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c
ab9c17a0
JM		 1590
1591 mailbox = mlx4_alloc_cmd_mailbox(dev);
1592 if (IS_ERR(mailbox))
1593 return PTR_ERR(mailbox);
1594 outbox = mailbox->buf;
1595
1596 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
1597 MLX4_CMD_QUERY_HCA,
1598 MLX4_CMD_TIME_CLASS_B,
1599 !mlx4_is_slave(dev));
1600 if (err)
1601 goto out;
1602
1603 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
ddd8a6c1 1604 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
ab9c17a0
JM		 1605
1606 /* QPC/EEC/CQC/EQC/RDMARC attributes */
1607
1608 MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET);
1609 MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET);
1610 MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET);
1611 MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET);
1612 MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET);
1613 MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET);
1614 MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET);
1615 MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET);
1616 MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET);
1617 MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET);
1618 MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
1619 MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET);
1620
7b8157be
JM		 1621 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
1622 if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) {
1623 param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
1624 } else {
1625 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
1626 if (byte_field & 0x8)
1627 param->steering_mode = MLX4_STEERING_MODE_B0;
1628 else
1629 param->steering_mode = MLX4_STEERING_MODE_A0;
1630 }
0ff1fb65 1631 /* steering attributes */
7b8157be 1632 if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
0ff1fb65
HHZ		 1633 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
1634 MLX4_GET(param->log_mc_entry_sz, outbox,
1635 INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
1636 MLX4_GET(param->log_mc_table_sz, outbox,
1637 INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
1638 } else {
1639 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
1640 MLX4_GET(param->log_mc_entry_sz, outbox,
1641 INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
1642 MLX4_GET(param->log_mc_hash_sz, outbox,
1643 INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
1644 MLX4_GET(param->log_mc_table_sz, outbox,
1645 INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
1646 }
ab9c17a0 1647
08ff3235
OG		 1648 /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */
1649 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
1650 if (byte_field & 0x20) /* 64-bytes eqe enabled */
1651 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1652 if (byte_field & 0x40) /* 64-bytes cqe enabled */
1653 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1654
77507aa2
IS		 1655 /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */
1656 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
1657 if (byte_field) {
1658 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED;
1659 param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED;
1660 param->cqe_size = 1 << ((byte_field &
1661 MLX4_CQE_SIZE_MASK_STRIDE) + 5);
1662 param->eqe_size = 1 << (((byte_field &
1663 MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5);
1664 }
1665
ab9c17a0
JM		 1666 /* TPT attributes */
1667
1668 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
e448834e 1669 MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET);
ab9c17a0
JM		 1670 MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
1671 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
1672 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
1673
1674 /* UAR attributes */
1675
1676 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
1677 MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
1678
1679out:
1680 mlx4_free_cmd_mailbox(dev, mailbox);
1681
1682 return err;
1683}
1684
980e9001
JM		 1685/* for IB-type ports only in SRIOV mode. Checks that both proxy QP0
1686 * and real QP0 are active, so that the paravirtualized QP0 is ready
1687 * to operate */
1688static int check_qp0_state(struct mlx4_dev *dev, int function, int port)
1689{
1690 struct mlx4_priv *priv = mlx4_priv(dev);
1691 /* irrelevant if not infiniband */
1692 if (priv->mfunc.master.qp0_state[port].proxy_qp0_active &&
1693 priv->mfunc.master.qp0_state[port].qp0_active)
1694 return 1;
1695 return 0;
1696}
1697
5cc914f1
MA		 1698int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1699 struct mlx4_vhcr *vhcr,
1700 struct mlx4_cmd_mailbox *inbox,
1701 struct mlx4_cmd_mailbox *outbox,
1702 struct mlx4_cmd_info *cmd)
1703{
1704 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1705 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1706 int err;
1707
449fc488
MB		 1708 if (port < 0)
1709 return -EINVAL;
1710
5cc914f1
MA		 1711 if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port))
1712 return 0;
1713
980e9001
JM		 1714 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1715 /* Enable port only if it was previously disabled */
1716 if (!priv->mfunc.master.init_port_ref[port]) {
1717 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1718 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1719 if (err)
1720 return err;
1721 }
1722 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1723 } else {
1724 if (slave == mlx4_master_func_num(dev)) {
1725 if (check_qp0_state(dev, slave, port) &&
1726 !priv->mfunc.master.qp0_state[port].port_active) {
1727 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
1728 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1729 if (err)
1730 return err;
1731 priv->mfunc.master.qp0_state[port].port_active = 1;
1732 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
1733 }
1734 } else
1735 priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port);
5cc914f1
MA		 1736 }
1737 ++priv->mfunc.master.init_port_ref[port];
1738 return 0;
1739}
1740
5ae2a7a8 1741int mlx4_INIT_PORT(struct mlx4_dev *dev, int port)
225c7b1f
RD		 1742{
1743 struct mlx4_cmd_mailbox *mailbox;
1744 u32 *inbox;
1745 int err;
1746 u32 flags;
5ae2a7a8 1747 u16 field;
225c7b1f 1748
5ae2a7a8 1749 if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
225c7b1f
RD		 1750#define INIT_PORT_IN_SIZE 256
1751#define INIT_PORT_FLAGS_OFFSET 0x00
1752#define INIT_PORT_FLAG_SIG (1 << 18)
1753#define INIT_PORT_FLAG_NG (1 << 17)
1754#define INIT_PORT_FLAG_G0 (1 << 16)
1755#define INIT_PORT_VL_SHIFT 4
1756#define INIT_PORT_PORT_WIDTH_SHIFT 8
1757#define INIT_PORT_MTU_OFFSET 0x04
1758#define INIT_PORT_MAX_GID_OFFSET 0x06
1759#define INIT_PORT_MAX_PKEY_OFFSET 0x0a
1760#define INIT_PORT_GUID0_OFFSET 0x10
1761#define INIT_PORT_NODE_GUID_OFFSET 0x18
1762#define INIT_PORT_SI_GUID_OFFSET 0x20
1763
5ae2a7a8
RD		 1764 mailbox = mlx4_alloc_cmd_mailbox(dev);
1765 if (IS_ERR(mailbox))
1766 return PTR_ERR(mailbox);
1767 inbox = mailbox->buf;
225c7b1f 1768
5ae2a7a8
RD		 1769 flags = 0;
1770 flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT;
1771 flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT;
1772 MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET);
225c7b1f 1773
b79acb49 1774 field = 128 << dev->caps.ib_mtu_cap[port];
5ae2a7a8
RD		 1775 MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET);
1776 field = dev->caps.gid_table_len[port];
1777 MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET);
1778 field = dev->caps.pkey_table_len[port];
1779 MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET);
225c7b1f 1780
5ae2a7a8 1781 err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1782 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f 1783
5ae2a7a8
RD		 1784 mlx4_free_cmd_mailbox(dev, mailbox);
1785 } else
1786 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT,
f9baff50 1787 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
225c7b1f
RD		 1788
1789 return err;
1790}
1791EXPORT_SYMBOL_GPL(mlx4_INIT_PORT);
1792
5cc914f1
MA		 1793int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1794 struct mlx4_vhcr *vhcr,
1795 struct mlx4_cmd_mailbox *inbox,
1796 struct mlx4_cmd_mailbox *outbox,
1797 struct mlx4_cmd_info *cmd)
1798{
1799 struct mlx4_priv *priv = mlx4_priv(dev);
449fc488 1800 int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier);
5cc914f1
MA		 1801 int err;
1802
449fc488
MB		 1803 if (port < 0)
1804 return -EINVAL;
1805
5cc914f1
MA		 1806 if (!(priv->mfunc.master.slave_state[slave].init_port_mask &
1807 (1 << port)))
1808 return 0;
1809
980e9001
JM		 1810 if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) {
1811 if (priv->mfunc.master.init_port_ref[port] == 1) {
1812 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1813 1000, MLX4_CMD_NATIVE);
1814 if (err)
1815 return err;
1816 }
1817 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1818 } else {
1819 /* infiniband port */
1820 if (slave == mlx4_master_func_num(dev)) {
1821 if (!priv->mfunc.master.qp0_state[port].qp0_active &&
1822 priv->mfunc.master.qp0_state[port].port_active) {
1823 err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT,
1824 1000, MLX4_CMD_NATIVE);
1825 if (err)
1826 return err;
1827 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
1828 priv->mfunc.master.qp0_state[port].port_active = 0;
1829 }
1830 } else
1831 priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port);
5cc914f1 1832 }
5cc914f1
MA		 1833 --priv->mfunc.master.init_port_ref[port];
1834 return 0;
1835}
1836
225c7b1f
RD		 1837int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port)
1838{
f9baff50
JM		 1839 return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000,
1840 MLX4_CMD_WRAPPED);
225c7b1f
RD		 1841}
1842EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT);
1843
1844int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic)
1845{
f9baff50
JM		 1846 return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000,
1847 MLX4_CMD_NATIVE);
225c7b1f
RD		 1848}
1849
d18f141a
OG		 1850struct mlx4_config_dev {
1851 __be32 update_flags;
1852 __be32 rsdv1[3];
1853 __be16 vxlan_udp_dport;
1854 __be16 rsvd2;
1855};
1856
1857#define MLX4_VXLAN_UDP_DPORT (1 << 0)
1858
1859static int mlx4_CONFIG_DEV(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev)
1860{
1861 int err;
1862 struct mlx4_cmd_mailbox *mailbox;
1863
1864 mailbox = mlx4_alloc_cmd_mailbox(dev);
1865 if (IS_ERR(mailbox))
1866 return PTR_ERR(mailbox);
1867
1868 memcpy(mailbox->buf, config_dev, sizeof(*config_dev));
1869
1870 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV,
1871 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
1872
1873 mlx4_free_cmd_mailbox(dev, mailbox);
1874 return err;
1875}
1876
1877int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port)
1878{
1879 struct mlx4_config_dev config_dev;
1880
1881 memset(&config_dev, 0, sizeof(config_dev));
1882 config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT);
1883 config_dev.vxlan_udp_dport = udp_port;
1884
1885 return mlx4_CONFIG_DEV(dev, &config_dev);
1886}
1887EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port);
1888
1889
225c7b1f
RD		 1890int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages)
1891{
1892 int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0,
1893 MLX4_CMD_SET_ICM_SIZE,
f9baff50 1894 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
225c7b1f
RD		 1895 if (ret)
1896 return ret;
1897
1898 /*
1899 * Round up number of system pages needed in case
1900 * MLX4_ICM_PAGE_SIZE < PAGE_SIZE.
1901 */
1902 *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >>
1903 (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT);
1904
1905 return 0;
1906}
1907
1908int mlx4_NOP(struct mlx4_dev *dev)
1909{
1910 /* Input modifier of 0x1f means "finish as soon as possible." */
f9baff50 1911 return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE);
225c7b1f 1912}
14c07b13 1913
8e1a28e8
HHZ		 1914int mlx4_get_phys_port_id(struct mlx4_dev *dev)
1915{
1916 u8 port;
1917 u32 *outbox;
1918 struct mlx4_cmd_mailbox *mailbox;
1919 u32 in_mod;
1920 u32 guid_hi, guid_lo;
1921 int err, ret = 0;
1922#define MOD_STAT_CFG_PORT_OFFSET 8
1923#define MOD_STAT_CFG_GUID_H 0X14
1924#define MOD_STAT_CFG_GUID_L 0X1c
1925
1926 mailbox = mlx4_alloc_cmd_mailbox(dev);
1927 if (IS_ERR(mailbox))
1928 return PTR_ERR(mailbox);
1929 outbox = mailbox->buf;
1930
1931 for (port = 1; port <= dev->caps.num_ports; port++) {
1932 in_mod = port << MOD_STAT_CFG_PORT_OFFSET;
1933 err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2,
1934 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1935 MLX4_CMD_NATIVE);
1936 if (err) {
1937 mlx4_err(dev, "Fail to get port %d uplink guid\n",
1938 port);
1939 ret = err;
1940 } else {
1941 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
1942 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
1943 dev->caps.phys_port_id[port] = (u64)guid_lo |
1944 (u64)guid_hi << 32;
1945 }
1946 }
1947 mlx4_free_cmd_mailbox(dev, mailbox);
1948 return ret;
1949}
1950
14c07b13
YP		 1951#define MLX4_WOL_SETUP_MODE (5 << 28)
1952int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port)
1953{
1954 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1955
1956 return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3,
f9baff50
JM		 1957 MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A,
1958 MLX4_CMD_NATIVE);
14c07b13
YP		 1959}
1960EXPORT_SYMBOL_GPL(mlx4_wol_read);
1961
1962int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port)
1963{
1964 u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8;
1965
1966 return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG,
f9baff50 1967 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
14c07b13
YP		 1968}
1969EXPORT_SYMBOL_GPL(mlx4_wol_write);
fe6f700d
YP		 1970
1971enum {
1972 ADD_TO_MCG = 0x26,
1973};
1974
1975
1976void mlx4_opreq_action(struct work_struct *work)
1977{
1978 struct mlx4_priv *priv = container_of(work, struct mlx4_priv,
1979 opreq_task);
1980 struct mlx4_dev *dev = &priv->dev;
1981 int num_tasks = atomic_read(&priv->opreq_count);
1982 struct mlx4_cmd_mailbox *mailbox;
1983 struct mlx4_mgm *mgm;
1984 u32 *outbox;
1985 u32 modifier;
1986 u16 token;
fe6f700d
YP		 1987 u16 type;
1988 int err;
1989 u32 num_qps;
1990 struct mlx4_qp qp;
1991 int i;
1992 u8 rem_mcg;
1993 u8 prot;
1994
1995#define GET_OP_REQ_MODIFIER_OFFSET 0x08
1996#define GET_OP_REQ_TOKEN_OFFSET 0x14
1997#define GET_OP_REQ_TYPE_OFFSET 0x1a
1998#define GET_OP_REQ_DATA_OFFSET 0x20
1999
2000 mailbox = mlx4_alloc_cmd_mailbox(dev);
2001 if (IS_ERR(mailbox)) {
2002 mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n");
2003 return;
2004 }
2005 outbox = mailbox->buf;
2006
2007 while (num_tasks) {
2008 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0,
2009 MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2010 MLX4_CMD_NATIVE);
2011 if (err) {
6d3be300 2012 mlx4_err(dev, "Failed to retrieve required operation: %d\n",
fe6f700d
YP		 2013 err);
2014 return;
2015 }
2016 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2017 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2018 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
fe6f700d
YP		 2019 type &= 0xfff;
2020
2021 switch (type) {
2022 case ADD_TO_MCG:
2023 if (dev->caps.steering_mode ==
2024 MLX4_STEERING_MODE_DEVICE_MANAGED) {
2025 mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n");
2026 err = EPERM;
2027 break;
2028 }
2029 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2030 GET_OP_REQ_DATA_OFFSET);
2031 num_qps = be32_to_cpu(mgm->members_count) &
2032 MGM_QPN_MASK;
2033 rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1;
2034 prot = ((u8 *)(&mgm->members_count))[0] >> 6;
2035
2036 for (i = 0; i < num_qps; i++) {
2037 qp.qpn = be32_to_cpu(mgm->qp[i]);
2038 if (rem_mcg)
2039 err = mlx4_multicast_detach(dev, &qp,
2040 mgm->gid,
2041 prot, 0);
2042 else
2043 err = mlx4_multicast_attach(dev, &qp,
2044 mgm->gid,
2045 mgm->gid[5]
2046 , 0, prot,
2047 NULL);
2048 if (err)
2049 break;
2050 }
2051 break;
2052 default:
2053 mlx4_warn(dev, "Bad type for required operation\n");
2054 err = EINVAL;
2055 break;
2056 }
28d222bb
EP		 2057 err = mlx4_cmd(dev, 0, ((u32) err |
2058 (__force u32)cpu_to_be32(token) << 16),
fe6f700d
YP		 2059 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A,
2060 MLX4_CMD_NATIVE);
2061 if (err) {
2062 mlx4_err(dev, "Failed to acknowledge required request: %d\n",
2063 err);
2064 goto out;
2065 }
2066 memset(outbox, 0, 0xffc);
2067 num_tasks = atomic_dec_return(&priv->opreq_count);
2068 }
2069
2070out:
2071 mlx4_free_cmd_mailbox(dev, mailbox);
2072}
114840c3
JM		 2073
2074static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev,
2075 struct mlx4_cmd_mailbox *mailbox)
2076{
2077#define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10
2078#define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20
2079#define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40
2080#define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70
2081
2082 u32 set_attr_mask, getresp_attr_mask;
2083 u32 trap_attr_mask, traprepress_attr_mask;
2084
2085 MLX4_GET(set_attr_mask, mailbox->buf,
2086 MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET);
2087 mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n",
2088 set_attr_mask);
2089
2090 MLX4_GET(getresp_attr_mask, mailbox->buf,
2091 MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET);
2092 mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n",
2093 getresp_attr_mask);
2094
2095 MLX4_GET(trap_attr_mask, mailbox->buf,
2096 MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET);
2097 mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n",
2098 trap_attr_mask);
2099
2100 MLX4_GET(traprepress_attr_mask, mailbox->buf,
2101 MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET);
2102 mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n",
2103 traprepress_attr_mask);
2104
2105 if (set_attr_mask && getresp_attr_mask && trap_attr_mask &&
2106 traprepress_attr_mask)
2107 return 1;
2108
2109 return 0;
2110}
2111
2112int mlx4_config_mad_demux(struct mlx4_dev *dev)
2113{
2114 struct mlx4_cmd_mailbox *mailbox;
2115 int secure_host_active;
2116 int err;
2117
2118 /* Check if mad_demux is supported */
2119 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX))
2120 return 0;
2121
2122 mailbox = mlx4_alloc_cmd_mailbox(dev);
2123 if (IS_ERR(mailbox)) {
2124 mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX");
2125 return -ENOMEM;
2126 }
2127
2128 /* Query mad_demux to find out which MADs are handled by internal sma */
2129 err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */,
2130 MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX,
2131 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2132 if (err) {
2133 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n",
2134 err);
2135 goto out;
2136 }
2137
2138 secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox);
2139
2140 /* Config mad_demux to handle all MADs returned by the query above */
2141 err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */,
2142 MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX,
2143 MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE);
2144 if (err) {
2145 mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err);
2146 goto out;
2147 }
2148
2149 if (secure_host_active)
2150 mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n");
2151out:
2152 mlx4_free_cmd_mailbox(dev, mailbox);
2153 return err;
2154}
adbc7ac5
SM		 2155
2156/* Access Reg commands */
2157enum mlx4_access_reg_masks {
2158 MLX4_ACCESS_REG_STATUS_MASK = 0x7f,
2159 MLX4_ACCESS_REG_METHOD_MASK = 0x7f,
2160 MLX4_ACCESS_REG_LEN_MASK = 0x7ff
2161};
2162
2163struct mlx4_access_reg {
2164 __be16 constant1;
2165 u8 status;
2166 u8 resrvd1;
2167 __be16 reg_id;
2168 u8 method;
2169 u8 constant2;
2170 __be32 resrvd2[2];
2171 __be16 len_const;
2172 __be16 resrvd3;
2173#define MLX4_ACCESS_REG_HEADER_SIZE (20)
2174 u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE];
2175} __attribute__((__packed__));
2176
2177/**
2178 * mlx4_ACCESS_REG - Generic access reg command.
2179 * @dev: mlx4_dev.
2180 * @reg_id: register ID to access.
2181 * @method: Access method Read/Write.
2182 * @reg_len: register length to Read/Write in bytes.
2183 * @reg_data: reg_data pointer to Read/Write From/To.
2184 *
2185 * Access ConnectX registers FW command.
2186 * Returns 0 on success and copies outbox mlx4_access_reg data
2187 * field into reg_data or a negative error code.
2188 */
2189static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id,
2190 enum mlx4_access_reg_method method,
2191 u16 reg_len, void *reg_data)
2192{
2193 struct mlx4_cmd_mailbox *inbox, *outbox;
2194 struct mlx4_access_reg *inbuf, *outbuf;
2195 int err;
2196
2197 inbox = mlx4_alloc_cmd_mailbox(dev);
2198 if (IS_ERR(inbox))
2199 return PTR_ERR(inbox);
2200
2201 outbox = mlx4_alloc_cmd_mailbox(dev);
2202 if (IS_ERR(outbox)) {
2203 mlx4_free_cmd_mailbox(dev, inbox);
2204 return PTR_ERR(outbox);
2205 }
2206
2207 inbuf = inbox->buf;
2208 outbuf = outbox->buf;
2209
2210 inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4);
2211 inbuf->constant2 = 0x1;
2212 inbuf->reg_id = cpu_to_be16(reg_id);
2213 inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK;
2214
2215 reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data)));
2216 inbuf->len_const =
2217 cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) |
2218 ((0x3) << 12));
2219
2220 memcpy(inbuf->reg_data, reg_data, reg_len);
2221 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2222 MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
6e806699 2223 MLX4_CMD_WRAPPED);
adbc7ac5
SM		 2224 if (err)
2225 goto out;
2226
2227 if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) {
2228 err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK;
2229 mlx4_err(dev,
2230 "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n",
2231 reg_id, err);
2232 goto out;
2233 }
2234
2235 memcpy(reg_data, outbuf->reg_data, reg_len);
2236out:
2237 mlx4_free_cmd_mailbox(dev, inbox);
2238 mlx4_free_cmd_mailbox(dev, outbox);
2239 return err;
2240}
2241
2242/* ConnectX registers IDs */
2243enum mlx4_reg_id {
2244 MLX4_REG_ID_PTYS = 0x5004,
2245};
2246
2247/**
2248 * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed)
2249 * register
2250 * @dev: mlx4_dev.
2251 * @method: Access method Read/Write.
2252 * @ptys_reg: PTYS register data pointer.
2253 *
2254 * Access ConnectX PTYS register, to Read/Write Port Type/Speed
2255 * configuration
2256 * Returns 0 on success or a negative error code.
2257 */
2258int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev,
2259 enum mlx4_access_reg_method method,
2260 struct mlx4_ptys_reg *ptys_reg)
2261{
2262 return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS,
2263 method, sizeof(*ptys_reg), ptys_reg);
2264}
2265EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG);
6e806699
SM		 2266
2267int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave,
2268 struct mlx4_vhcr *vhcr,
2269 struct mlx4_cmd_mailbox *inbox,
2270 struct mlx4_cmd_mailbox *outbox,
2271 struct mlx4_cmd_info *cmd)
2272{
2273 struct mlx4_access_reg *inbuf = inbox->buf;
2274 u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK;
2275 u16 reg_id = be16_to_cpu(inbuf->reg_id);
2276
2277 if (slave != mlx4_master_func_num(dev) &&
2278 method == MLX4_ACCESS_REG_WRITE)
2279 return -EPERM;
2280
2281 if (reg_id == MLX4_REG_ID_PTYS) {
2282 struct mlx4_ptys_reg *ptys_reg =
2283 (struct mlx4_ptys_reg *)inbuf->reg_data;
2284
2285 ptys_reg->local_port =
2286 mlx4_slave_convert_port(dev, slave,
2287 ptys_reg->local_port);
2288 }
2289
2290 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,
2291 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C,
2292 MLX4_CMD_NATIVE);
2293}
Linux kernel - Deliverables
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