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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
51a379d0 | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
5 | * | |
6 | * This software is available to you under a choice of one of two | |
7 | * licenses. You may choose to be licensed under the terms of the GNU | |
8 | * General Public License (GPL) Version 2, available from the file | |
9 | * COPYING in the main directory of this source tree, or the | |
10 | * OpenIB.org BSD license below: | |
11 | * | |
12 | * Redistribution and use in source and binary forms, with or | |
13 | * without modification, are permitted provided that the following | |
14 | * conditions are met: | |
15 | * | |
16 | * - Redistributions of source code must retain the above | |
17 | * copyright notice, this list of conditions and the following | |
18 | * disclaimer. | |
19 | * | |
20 | * - Redistributions in binary form must reproduce the above | |
21 | * copyright notice, this list of conditions and the following | |
22 | * disclaimer in the documentation and/or other materials | |
23 | * provided with the distribution. | |
24 | * | |
25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
32 | * SOFTWARE. | |
33 | */ | |
34 | ||
5cc914f1 | 35 | #include <linux/etherdevice.h> |
225c7b1f | 36 | #include <linux/mlx4/cmd.h> |
9d9779e7 | 37 | #include <linux/module.h> |
c57e20dc | 38 | #include <linux/cache.h> |
225c7b1f RD |
39 | |
40 | #include "fw.h" | |
41 | #include "icm.h" | |
42 | ||
fe40900f | 43 | enum { |
5ae2a7a8 RD |
44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, | |
46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, | |
fe40900f RD |
47 | }; |
48 | ||
225c7b1f RD |
49 | extern void __buggy_use_of_MLX4_GET(void); |
50 | extern void __buggy_use_of_MLX4_PUT(void); | |
51 | ||
eb939922 | 52 | static bool enable_qos; |
51f5f0ee JM |
53 | module_param(enable_qos, bool, 0444); |
54 | MODULE_PARM_DESC(enable_qos, "Enable Quality of Service support in the HCA (default: off)"); | |
55 | ||
225c7b1f RD |
56 | #define MLX4_GET(dest, source, offset) \ |
57 | do { \ | |
58 | void *__p = (char *) (source) + (offset); \ | |
59 | switch (sizeof (dest)) { \ | |
60 | case 1: (dest) = *(u8 *) __p; break; \ | |
61 | case 2: (dest) = be16_to_cpup(__p); break; \ | |
62 | case 4: (dest) = be32_to_cpup(__p); break; \ | |
63 | case 8: (dest) = be64_to_cpup(__p); break; \ | |
64 | default: __buggy_use_of_MLX4_GET(); \ | |
65 | } \ | |
66 | } while (0) | |
67 | ||
68 | #define MLX4_PUT(dest, source, offset) \ | |
69 | do { \ | |
70 | void *__d = ((char *) (dest) + (offset)); \ | |
71 | switch (sizeof(source)) { \ | |
72 | case 1: *(u8 *) __d = (source); break; \ | |
73 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ | |
74 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ | |
75 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ | |
76 | default: __buggy_use_of_MLX4_PUT(); \ | |
77 | } \ | |
78 | } while (0) | |
79 | ||
52eafc68 | 80 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
225c7b1f RD |
81 | { |
82 | static const char *fname[] = { | |
83 | [ 0] = "RC transport", | |
84 | [ 1] = "UC transport", | |
85 | [ 2] = "UD transport", | |
ea98054f | 86 | [ 3] = "XRC transport", |
225c7b1f RD |
87 | [ 4] = "reliable multicast", |
88 | [ 5] = "FCoIB support", | |
89 | [ 6] = "SRQ support", | |
90 | [ 7] = "IPoIB checksum offload", | |
91 | [ 8] = "P_Key violation counter", | |
92 | [ 9] = "Q_Key violation counter", | |
93 | [10] = "VMM", | |
4d531aa8 | 94 | [12] = "Dual Port Different Protocol (DPDP) support", |
417608c2 | 95 | [15] = "Big LSO headers", |
225c7b1f RD |
96 | [16] = "MW support", |
97 | [17] = "APM support", | |
98 | [18] = "Atomic ops support", | |
99 | [19] = "Raw multicast support", | |
100 | [20] = "Address vector port checking support", | |
101 | [21] = "UD multicast support", | |
102 | [24] = "Demand paging support", | |
96dfa684 | 103 | [25] = "Router support", |
ccf86321 OG |
104 | [30] = "IBoE support", |
105 | [32] = "Unicast loopback support", | |
f3a9d1f2 | 106 | [34] = "FCS header control", |
ccf86321 OG |
107 | [38] = "Wake On LAN support", |
108 | [40] = "UDP RSS support", | |
109 | [41] = "Unicast VEP steering support", | |
f2a3f6a3 OG |
110 | [42] = "Multicast VEP steering support", |
111 | [48] = "Counters support", | |
540b3a39 | 112 | [53] = "Port ETS Scheduler support", |
4d531aa8 | 113 | [55] = "Port link type sensing support", |
00f5ce99 | 114 | [59] = "Port management change event support", |
08ff3235 OG |
115 | [61] = "64 byte EQE support", |
116 | [62] = "64 byte CQE support", | |
225c7b1f RD |
117 | }; |
118 | int i; | |
119 | ||
120 | mlx4_dbg(dev, "DEV_CAP flags:\n"); | |
23c15c21 | 121 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
52eafc68 | 122 | if (fname[i] && (flags & (1LL << i))) |
225c7b1f RD |
123 | mlx4_dbg(dev, " %s\n", fname[i]); |
124 | } | |
125 | ||
b3416f44 SP |
126 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
127 | { | |
128 | static const char * const fname[] = { | |
129 | [0] = "RSS support", | |
130 | [1] = "RSS Toeplitz Hash Function support", | |
0ff1fb65 | 131 | [2] = "RSS XOR Hash Function support", |
955154fa | 132 | [3] = "Device manage flow steering support", |
d998735f | 133 | [4] = "Automatic MAC reassignment support", |
4e8cf5b8 OG |
134 | [5] = "Time stamping support", |
135 | [6] = "VST (control vlan insertion/stripping) support", | |
b01978ca JM |
136 | [7] = "FSM (MAC anti-spoofing) support", |
137 | [8] = "Dynamic QP updates support" | |
b3416f44 SP |
138 | }; |
139 | int i; | |
140 | ||
141 | for (i = 0; i < ARRAY_SIZE(fname); ++i) | |
142 | if (fname[i] && (flags & (1LL << i))) | |
143 | mlx4_dbg(dev, " %s\n", fname[i]); | |
144 | } | |
145 | ||
2d928651 VS |
146 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
147 | { | |
148 | struct mlx4_cmd_mailbox *mailbox; | |
149 | u32 *inbox; | |
150 | int err = 0; | |
151 | ||
152 | #define MOD_STAT_CFG_IN_SIZE 0x100 | |
153 | ||
154 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 | |
155 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 | |
156 | ||
157 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
158 | if (IS_ERR(mailbox)) | |
159 | return PTR_ERR(mailbox); | |
160 | inbox = mailbox->buf; | |
161 | ||
162 | memset(inbox, 0, MOD_STAT_CFG_IN_SIZE); | |
163 | ||
164 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); | |
165 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); | |
166 | ||
167 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 168 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
2d928651 VS |
169 | |
170 | mlx4_free_cmd_mailbox(dev, mailbox); | |
171 | return err; | |
172 | } | |
173 | ||
5cc914f1 MA |
174 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
175 | struct mlx4_vhcr *vhcr, | |
176 | struct mlx4_cmd_mailbox *inbox, | |
177 | struct mlx4_cmd_mailbox *outbox, | |
178 | struct mlx4_cmd_info *cmd) | |
179 | { | |
180 | u8 field; | |
181 | u32 size; | |
182 | int err = 0; | |
183 | ||
184 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 | |
185 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 | |
5cc914f1 | 186 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
105c320f | 187 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
5cc914f1 MA |
188 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x10 |
189 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x14 | |
190 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x18 | |
191 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x20 | |
192 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x24 | |
193 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x28 | |
194 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c | |
69612b9f | 195 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
5cc914f1 | 196 | |
105c320f JM |
197 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
198 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 | |
199 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 | |
200 | ||
201 | /* when opcode modifier = 1 */ | |
5cc914f1 | 202 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
105c320f | 203 | #define QUERY_FUNC_CAP_RDMA_PROPS_OFFSET 0x8 |
5cc914f1 MA |
204 | #define QUERY_FUNC_CAP_ETH_PROPS_OFFSET 0xc |
205 | ||
47605df9 JM |
206 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
207 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 | |
208 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 | |
209 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c | |
210 | ||
105c320f JM |
211 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC 0x40 |
212 | #define QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN 0x80 | |
213 | ||
214 | #define QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID 0x80 | |
215 | ||
5cc914f1 | 216 | if (vhcr->op_modifier == 1) { |
105c320f JM |
217 | field = 0; |
218 | /* ensure force vlan and force mac bits are not set */ | |
5cc914f1 | 219 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); |
105c320f JM |
220 | /* ensure that phy_wqe_gid bit is not set */ |
221 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); | |
222 | ||
47605df9 JM |
223 | field = vhcr->in_modifier; /* phys-port = logical-port */ |
224 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); | |
225 | ||
226 | /* size is now the QP number */ | |
227 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + field - 1; | |
228 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); | |
229 | ||
230 | size += 2; | |
231 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); | |
232 | ||
233 | size = dev->phys_caps.base_proxy_sqpn + 8 * slave + field - 1; | |
234 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_PROXY); | |
235 | ||
236 | size += 2; | |
237 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_PROXY); | |
238 | ||
5cc914f1 | 239 | } else if (vhcr->op_modifier == 0) { |
105c320f JM |
240 | /* enable rdma and ethernet interfaces */ |
241 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA); | |
5cc914f1 MA |
242 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
243 | ||
5cc914f1 MA |
244 | field = dev->caps.num_ports; |
245 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); | |
246 | ||
08ff3235 | 247 | size = dev->caps.function_caps; /* set PF behaviours */ |
5cc914f1 MA |
248 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
249 | ||
105c320f JM |
250 | field = 0; /* protected FMR support not available as yet */ |
251 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); | |
252 | ||
5cc914f1 MA |
253 | size = dev->caps.num_qps; |
254 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); | |
255 | ||
256 | size = dev->caps.num_srqs; | |
257 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); | |
258 | ||
259 | size = dev->caps.num_cqs; | |
260 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); | |
261 | ||
262 | size = dev->caps.num_eqs; | |
263 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); | |
264 | ||
265 | size = dev->caps.reserved_eqs; | |
266 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); | |
267 | ||
268 | size = dev->caps.num_mpts; | |
269 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); | |
270 | ||
2b8fb286 | 271 | size = dev->caps.num_mtts; |
5cc914f1 MA |
272 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
273 | ||
274 | size = dev->caps.num_mgms + dev->caps.num_amgms; | |
275 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); | |
276 | ||
277 | } else | |
278 | err = -EINVAL; | |
279 | ||
280 | return err; | |
281 | } | |
282 | ||
47605df9 JM |
283 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u32 gen_or_port, |
284 | struct mlx4_func_cap *func_cap) | |
5cc914f1 MA |
285 | { |
286 | struct mlx4_cmd_mailbox *mailbox; | |
287 | u32 *outbox; | |
47605df9 | 288 | u8 field, op_modifier; |
5cc914f1 | 289 | u32 size; |
5cc914f1 MA |
290 | int err = 0; |
291 | ||
47605df9 | 292 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
5cc914f1 MA |
293 | |
294 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
295 | if (IS_ERR(mailbox)) | |
296 | return PTR_ERR(mailbox); | |
297 | ||
47605df9 JM |
298 | err = mlx4_cmd_box(dev, 0, mailbox->dma, gen_or_port, op_modifier, |
299 | MLX4_CMD_QUERY_FUNC_CAP, | |
5cc914f1 MA |
300 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
301 | if (err) | |
302 | goto out; | |
303 | ||
304 | outbox = mailbox->buf; | |
305 | ||
47605df9 JM |
306 | if (!op_modifier) { |
307 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); | |
308 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { | |
309 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); | |
310 | err = -EPROTONOSUPPORT; | |
311 | goto out; | |
312 | } | |
313 | func_cap->flags = field; | |
5cc914f1 | 314 | |
47605df9 JM |
315 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
316 | func_cap->num_ports = field; | |
5cc914f1 | 317 | |
47605df9 JM |
318 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
319 | func_cap->pf_context_behaviour = size; | |
5cc914f1 | 320 | |
47605df9 JM |
321 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
322 | func_cap->qp_quota = size & 0xFFFFFF; | |
5cc914f1 | 323 | |
47605df9 JM |
324 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
325 | func_cap->srq_quota = size & 0xFFFFFF; | |
5cc914f1 | 326 | |
47605df9 JM |
327 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
328 | func_cap->cq_quota = size & 0xFFFFFF; | |
5cc914f1 | 329 | |
47605df9 JM |
330 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
331 | func_cap->max_eq = size & 0xFFFFFF; | |
5cc914f1 | 332 | |
47605df9 JM |
333 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
334 | func_cap->reserved_eq = size & 0xFFFFFF; | |
5cc914f1 | 335 | |
47605df9 JM |
336 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
337 | func_cap->mpt_quota = size & 0xFFFFFF; | |
5cc914f1 | 338 | |
47605df9 JM |
339 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
340 | func_cap->mtt_quota = size & 0xFFFFFF; | |
5cc914f1 | 341 | |
47605df9 JM |
342 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
343 | func_cap->mcg_quota = size & 0xFFFFFF; | |
344 | goto out; | |
345 | } | |
5cc914f1 | 346 | |
47605df9 JM |
347 | /* logical port query */ |
348 | if (gen_or_port > dev->caps.num_ports) { | |
349 | err = -EINVAL; | |
350 | goto out; | |
351 | } | |
5cc914f1 | 352 | |
47605df9 JM |
353 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
354 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_ETH_PROPS_OFFSET); | |
355 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_VLAN) { | |
356 | mlx4_err(dev, "VLAN is enforced on this port\n"); | |
357 | err = -EPROTONOSUPPORT; | |
5cc914f1 | 358 | goto out; |
47605df9 | 359 | } |
5cc914f1 | 360 | |
47605df9 JM |
361 | if (field & QUERY_FUNC_CAP_ETH_PROPS_FORCE_MAC) { |
362 | mlx4_err(dev, "Force mac is enabled on this port\n"); | |
363 | err = -EPROTONOSUPPORT; | |
364 | goto out; | |
5cc914f1 | 365 | } |
47605df9 JM |
366 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
367 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_RDMA_PROPS_OFFSET); | |
368 | if (field & QUERY_FUNC_CAP_RDMA_PROPS_FORCE_PHY_WQE_GID) { | |
369 | mlx4_err(dev, "phy_wqe_gid is " | |
370 | "enforced on this ib port\n"); | |
371 | err = -EPROTONOSUPPORT; | |
372 | goto out; | |
373 | } | |
374 | } | |
5cc914f1 | 375 | |
47605df9 JM |
376 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
377 | func_cap->physical_port = field; | |
378 | if (func_cap->physical_port != gen_or_port) { | |
379 | err = -ENOSYS; | |
380 | goto out; | |
5cc914f1 MA |
381 | } |
382 | ||
47605df9 JM |
383 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
384 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; | |
385 | ||
386 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); | |
387 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; | |
388 | ||
389 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); | |
390 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; | |
391 | ||
392 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); | |
393 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; | |
394 | ||
5cc914f1 MA |
395 | /* All other resources are allocated by the master, but we still report |
396 | * 'num' and 'reserved' capabilities as follows: | |
397 | * - num remains the maximum resource index | |
398 | * - 'num - reserved' is the total available objects of a resource, but | |
399 | * resource indices may be less than 'reserved' | |
400 | * TODO: set per-resource quotas */ | |
401 | ||
402 | out: | |
403 | mlx4_free_cmd_mailbox(dev, mailbox); | |
404 | ||
405 | return err; | |
406 | } | |
407 | ||
225c7b1f RD |
408 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
409 | { | |
410 | struct mlx4_cmd_mailbox *mailbox; | |
411 | u32 *outbox; | |
412 | u8 field; | |
ccf86321 | 413 | u32 field32, flags, ext_flags; |
225c7b1f RD |
414 | u16 size; |
415 | u16 stat_rate; | |
416 | int err; | |
5ae2a7a8 | 417 | int i; |
225c7b1f RD |
418 | |
419 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 | |
420 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 | |
421 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 | |
422 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 | |
423 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 | |
424 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 | |
425 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 | |
426 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 | |
427 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 | |
428 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 | |
429 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a | |
430 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b | |
431 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d | |
432 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e | |
433 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f | |
434 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 | |
435 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 | |
436 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 | |
437 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 | |
438 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 | |
439 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 | |
440 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b | |
b832be1e | 441 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
b3416f44 | 442 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
225c7b1f RD |
443 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
444 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 | |
445 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 | |
446 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 | |
447 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 | |
149983af | 448 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
225c7b1f RD |
449 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
450 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c | |
d998735f | 451 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
225c7b1f | 452 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
ccf86321 | 453 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
225c7b1f RD |
454 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
455 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 | |
456 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 | |
457 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b | |
458 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c | |
459 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d | |
460 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e | |
461 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f | |
462 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 | |
463 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 | |
464 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 | |
465 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 | |
466 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 | |
467 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 | |
468 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 | |
469 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 | |
470 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 | |
012a8ff5 SH |
471 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
472 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 | |
f2a3f6a3 | 473 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
3f7fb021 | 474 | #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 |
0ff1fb65 HHZ |
475 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
476 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 | |
225c7b1f RD |
477 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
478 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 | |
479 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 | |
480 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 | |
481 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 | |
482 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a | |
483 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c | |
484 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e | |
485 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 | |
486 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 | |
95d04f07 | 487 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
225c7b1f RD |
488 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
489 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 | |
955154fa | 490 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
225c7b1f | 491 | |
b3416f44 | 492 | dev_cap->flags2 = 0; |
225c7b1f RD |
493 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
494 | if (IS_ERR(mailbox)) | |
495 | return PTR_ERR(mailbox); | |
496 | outbox = mailbox->buf; | |
497 | ||
498 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
401453a3 | 499 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
500 | if (err) |
501 | goto out; | |
502 | ||
503 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); | |
504 | dev_cap->reserved_qps = 1 << (field & 0xf); | |
505 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); | |
506 | dev_cap->max_qps = 1 << (field & 0x1f); | |
507 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); | |
508 | dev_cap->reserved_srqs = 1 << (field >> 4); | |
509 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); | |
510 | dev_cap->max_srqs = 1 << (field & 0x1f); | |
511 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); | |
512 | dev_cap->max_cq_sz = 1 << field; | |
513 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); | |
514 | dev_cap->reserved_cqs = 1 << (field & 0xf); | |
515 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); | |
516 | dev_cap->max_cqs = 1 << (field & 0x1f); | |
517 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); | |
518 | dev_cap->max_mpts = 1 << (field & 0x3f); | |
519 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); | |
be504b0b | 520 | dev_cap->reserved_eqs = field & 0xf; |
225c7b1f | 521 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
5920869f | 522 | dev_cap->max_eqs = 1 << (field & 0xf); |
225c7b1f RD |
523 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
524 | dev_cap->reserved_mtts = 1 << (field >> 4); | |
525 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); | |
526 | dev_cap->max_mrw_sz = 1 << field; | |
527 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); | |
528 | dev_cap->reserved_mrws = 1 << (field & 0xf); | |
529 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); | |
530 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); | |
531 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); | |
532 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); | |
533 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); | |
534 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); | |
b832be1e EC |
535 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
536 | field &= 0x1f; | |
537 | if (!field) | |
538 | dev_cap->max_gso_sz = 0; | |
539 | else | |
540 | dev_cap->max_gso_sz = 1 << field; | |
541 | ||
b3416f44 SP |
542 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
543 | if (field & 0x20) | |
544 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; | |
545 | if (field & 0x10) | |
546 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; | |
547 | field &= 0xf; | |
548 | if (field) { | |
549 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; | |
550 | dev_cap->max_rss_tbl_sz = 1 << field; | |
551 | } else | |
552 | dev_cap->max_rss_tbl_sz = 0; | |
225c7b1f RD |
553 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
554 | dev_cap->max_rdma_global = 1 << (field & 0x3f); | |
555 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); | |
556 | dev_cap->local_ca_ack_delay = field & 0x1f; | |
225c7b1f | 557 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
225c7b1f | 558 | dev_cap->num_ports = field & 0xf; |
149983af DB |
559 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
560 | dev_cap->max_msg_sz = 1 << (field & 0x1f); | |
0ff1fb65 HHZ |
561 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
562 | if (field & 0x80) | |
563 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; | |
564 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; | |
565 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); | |
566 | dev_cap->fs_max_num_qp_per_entry = field; | |
225c7b1f RD |
567 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
568 | dev_cap->stat_rate_support = stat_rate; | |
d998735f EE |
569 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
570 | if (field & 0x80) | |
571 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; | |
ccf86321 | 572 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
52eafc68 | 573 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
ccf86321 | 574 | dev_cap->flags = flags | (u64)ext_flags << 32; |
225c7b1f RD |
575 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
576 | dev_cap->reserved_uars = field >> 4; | |
577 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); | |
578 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); | |
579 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); | |
580 | dev_cap->min_page_sz = 1 << field; | |
581 | ||
582 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); | |
583 | if (field & 0x80) { | |
584 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); | |
585 | dev_cap->bf_reg_size = 1 << (field & 0x1f); | |
586 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); | |
f5a49539 | 587 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
58d74bb1 | 588 | field = 3; |
225c7b1f RD |
589 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
590 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", | |
591 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); | |
592 | } else { | |
593 | dev_cap->bf_reg_size = 0; | |
594 | mlx4_dbg(dev, "BlueFlame not available\n"); | |
595 | } | |
596 | ||
597 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); | |
598 | dev_cap->max_sq_sg = field; | |
599 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); | |
600 | dev_cap->max_sq_desc_sz = size; | |
601 | ||
602 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); | |
603 | dev_cap->max_qp_per_mcg = 1 << field; | |
604 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); | |
605 | dev_cap->reserved_mgms = field & 0xf; | |
606 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); | |
607 | dev_cap->max_mcgs = 1 << field; | |
608 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); | |
609 | dev_cap->reserved_pds = field >> 4; | |
610 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); | |
611 | dev_cap->max_pds = 1 << (field & 0x3f); | |
012a8ff5 SH |
612 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
613 | dev_cap->reserved_xrcds = field >> 4; | |
426dd00d | 614 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
012a8ff5 | 615 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
225c7b1f RD |
616 | |
617 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); | |
618 | dev_cap->rdmarc_entry_sz = size; | |
619 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); | |
620 | dev_cap->qpc_entry_sz = size; | |
621 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); | |
622 | dev_cap->aux_entry_sz = size; | |
623 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); | |
624 | dev_cap->altc_entry_sz = size; | |
625 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); | |
626 | dev_cap->eqc_entry_sz = size; | |
627 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); | |
628 | dev_cap->cqc_entry_sz = size; | |
629 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); | |
630 | dev_cap->srq_entry_sz = size; | |
631 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); | |
632 | dev_cap->cmpt_entry_sz = size; | |
633 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); | |
634 | dev_cap->mtt_entry_sz = size; | |
635 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); | |
636 | dev_cap->dmpt_entry_sz = size; | |
637 | ||
638 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); | |
639 | dev_cap->max_srq_sz = 1 << field; | |
640 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); | |
641 | dev_cap->max_qp_sz = 1 << field; | |
642 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); | |
643 | dev_cap->resize_srq = field & 1; | |
644 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); | |
645 | dev_cap->max_rq_sg = field; | |
646 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); | |
647 | dev_cap->max_rq_desc_sz = size; | |
648 | ||
649 | MLX4_GET(dev_cap->bmme_flags, outbox, | |
650 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
651 | MLX4_GET(dev_cap->reserved_lkey, outbox, | |
652 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); | |
955154fa MB |
653 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
654 | if (field & 1<<6) | |
655 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAGS2_REASSIGN_MAC_EN; | |
225c7b1f RD |
656 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
657 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); | |
f2a3f6a3 OG |
658 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
659 | MLX4_GET(dev_cap->max_counters, outbox, | |
660 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); | |
225c7b1f | 661 | |
3f7fb021 | 662 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
b01978ca JM |
663 | if (field32 & (1 << 16)) |
664 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; | |
3f7fb021 RE |
665 | if (field32 & (1 << 26)) |
666 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; | |
e6b6a231 RE |
667 | if (field32 & (1 << 20)) |
668 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; | |
3f7fb021 | 669 | |
5ae2a7a8 RD |
670 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
671 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
672 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); | |
673 | dev_cap->max_vl[i] = field >> 4; | |
674 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); | |
b79acb49 | 675 | dev_cap->ib_mtu[i] = field >> 4; |
5ae2a7a8 RD |
676 | dev_cap->max_port_width[i] = field & 0xf; |
677 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); | |
678 | dev_cap->max_gids[i] = 1 << (field & 0xf); | |
679 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); | |
680 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
681 | } | |
682 | } else { | |
7ff93f8b | 683 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
5ae2a7a8 | 684 | #define QUERY_PORT_MTU_OFFSET 0x01 |
b79acb49 | 685 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
5ae2a7a8 RD |
686 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
687 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 | |
93fc9e1b | 688 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
5ae2a7a8 | 689 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
e65b9591 | 690 | #define QUERY_PORT_MAC_OFFSET 0x10 |
7699517d YP |
691 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
692 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c | |
693 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 | |
5ae2a7a8 RD |
694 | |
695 | for (i = 1; i <= dev_cap->num_ports; ++i) { | |
696 | err = mlx4_cmd_box(dev, 0, mailbox->dma, i, 0, MLX4_CMD_QUERY_PORT, | |
401453a3 | 697 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
5ae2a7a8 RD |
698 | if (err) |
699 | goto out; | |
700 | ||
7ff93f8b YP |
701 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
702 | dev_cap->supported_port_types[i] = field & 3; | |
8d0fc7b6 YP |
703 | dev_cap->suggested_type[i] = (field >> 3) & 1; |
704 | dev_cap->default_sense[i] = (field >> 4) & 1; | |
5ae2a7a8 | 705 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
b79acb49 | 706 | dev_cap->ib_mtu[i] = field & 0xf; |
5ae2a7a8 RD |
707 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
708 | dev_cap->max_port_width[i] = field & 0xf; | |
709 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); | |
710 | dev_cap->max_gids[i] = 1 << (field >> 4); | |
711 | dev_cap->max_pkeys[i] = 1 << (field & 0xf); | |
712 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); | |
713 | dev_cap->max_vl[i] = field & 0xf; | |
93fc9e1b YP |
714 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
715 | dev_cap->log_max_macs[i] = field & 0xf; | |
716 | dev_cap->log_max_vlans[i] = field >> 4; | |
b79acb49 YP |
717 | MLX4_GET(dev_cap->eth_mtu[i], outbox, QUERY_PORT_ETH_MTU_OFFSET); |
718 | MLX4_GET(dev_cap->def_mac[i], outbox, QUERY_PORT_MAC_OFFSET); | |
7699517d YP |
719 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
720 | dev_cap->trans_type[i] = field32 >> 24; | |
721 | dev_cap->vendor_oui[i] = field32 & 0xffffff; | |
722 | MLX4_GET(dev_cap->wavelength[i], outbox, QUERY_PORT_WAVELENGTH_OFFSET); | |
723 | MLX4_GET(dev_cap->trans_code[i], outbox, QUERY_PORT_TRANS_CODE_OFFSET); | |
5ae2a7a8 RD |
724 | } |
725 | } | |
726 | ||
95d04f07 RD |
727 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
728 | dev_cap->bmme_flags, dev_cap->reserved_lkey); | |
225c7b1f RD |
729 | |
730 | /* | |
731 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then | |
732 | * we can't use any EQs whose doorbell falls on that page, | |
733 | * even if the EQ itself isn't reserved. | |
734 | */ | |
735 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, | |
736 | dev_cap->reserved_eqs); | |
737 | ||
738 | mlx4_dbg(dev, "Max ICM size %lld MB\n", | |
739 | (unsigned long long) dev_cap->max_icm_sz >> 20); | |
740 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", | |
741 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); | |
742 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", | |
743 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); | |
744 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", | |
745 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); | |
746 | mlx4_dbg(dev, "Max EQs: %d, reserved EQs: %d, entry size: %d\n", | |
747 | dev_cap->max_eqs, dev_cap->reserved_eqs, dev_cap->eqc_entry_sz); | |
748 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", | |
749 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); | |
750 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", | |
751 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); | |
752 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", | |
753 | dev_cap->max_pds, dev_cap->reserved_mgms); | |
754 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", | |
755 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); | |
756 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", | |
b79acb49 | 757 | dev_cap->local_ca_ack_delay, 128 << dev_cap->ib_mtu[1], |
5ae2a7a8 | 758 | dev_cap->max_port_width[1]); |
225c7b1f RD |
759 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
760 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); | |
761 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", | |
762 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); | |
b832be1e | 763 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
f2a3f6a3 | 764 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
b3416f44 | 765 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
225c7b1f RD |
766 | |
767 | dump_dev_cap_flags(dev, dev_cap->flags); | |
b3416f44 | 768 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
225c7b1f RD |
769 | |
770 | out: | |
771 | mlx4_free_cmd_mailbox(dev, mailbox); | |
772 | return err; | |
773 | } | |
774 | ||
b91cb3eb JM |
775 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
776 | struct mlx4_vhcr *vhcr, | |
777 | struct mlx4_cmd_mailbox *inbox, | |
778 | struct mlx4_cmd_mailbox *outbox, | |
779 | struct mlx4_cmd_info *cmd) | |
780 | { | |
2a4fae14 | 781 | u64 flags; |
b91cb3eb JM |
782 | int err = 0; |
783 | u8 field; | |
cc1ade94 | 784 | u32 bmme_flags; |
b91cb3eb JM |
785 | |
786 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, | |
787 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
788 | if (err) | |
789 | return err; | |
790 | ||
cc1ade94 SM |
791 | /* add port mng change event capability and disable mw type 1 |
792 | * unconditionally to slaves | |
793 | */ | |
2a4fae14 JM |
794 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
795 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; | |
cc1ade94 | 796 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
2a4fae14 JM |
797 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
798 | ||
30b40c31 AV |
799 | /* For guests, disable timestamp */ |
800 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); | |
801 | field &= 0x7f; | |
802 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); | |
803 | ||
b91cb3eb JM |
804 | /* For guests, report Blueflame disabled */ |
805 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); | |
806 | field &= 0x7f; | |
807 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); | |
808 | ||
cc1ade94 SM |
809 | /* For guests, disable mw type 2 */ |
810 | MLX4_GET(bmme_flags, outbox, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
811 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; | |
812 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); | |
813 | ||
0081c8f3 JM |
814 | /* turn off device-managed steering capability if not enabled */ |
815 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
816 | MLX4_GET(field, outbox->buf, | |
817 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); | |
818 | field &= 0x7f; | |
819 | MLX4_PUT(outbox->buf, field, | |
820 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); | |
821 | } | |
b91cb3eb JM |
822 | return 0; |
823 | } | |
824 | ||
5cc914f1 MA |
825 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
826 | struct mlx4_vhcr *vhcr, | |
827 | struct mlx4_cmd_mailbox *inbox, | |
828 | struct mlx4_cmd_mailbox *outbox, | |
829 | struct mlx4_cmd_info *cmd) | |
830 | { | |
0eb62b93 | 831 | struct mlx4_priv *priv = mlx4_priv(dev); |
5cc914f1 MA |
832 | u64 def_mac; |
833 | u8 port_type; | |
6634961c | 834 | u16 short_field; |
5cc914f1 | 835 | int err; |
948e306d | 836 | int admin_link_state; |
5cc914f1 | 837 | |
105c320f | 838 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
948e306d | 839 | #define MLX4_PORT_LINK_UP_MASK 0x80 |
6634961c JM |
840 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
841 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e | |
95f56e7a | 842 | |
5cc914f1 MA |
843 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
844 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
845 | MLX4_CMD_NATIVE); | |
846 | ||
847 | if (!err && dev->caps.function != slave) { | |
0eb62b93 RE |
848 | /* if config MAC in DB use it */ |
849 | if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac) | |
850 | def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; | |
c418253f OG |
851 | else { |
852 | /* set slave default_mac address */ | |
853 | MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET); | |
854 | def_mac += slave << 8; | |
855 | priv->mfunc.master.vf_admin[slave].vport[vhcr->in_modifier].mac = def_mac; | |
856 | } | |
857 | ||
5cc914f1 MA |
858 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
859 | ||
860 | /* get port type - currently only eth is enabled */ | |
861 | MLX4_GET(port_type, outbox->buf, | |
862 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
863 | ||
105c320f JM |
864 | /* No link sensing allowed */ |
865 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; | |
866 | /* set port type to currently operating port type */ | |
867 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); | |
5cc914f1 | 868 | |
948e306d RE |
869 | admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; |
870 | if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) | |
871 | port_type |= MLX4_PORT_LINK_UP_MASK; | |
872 | else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) | |
873 | port_type &= ~MLX4_PORT_LINK_UP_MASK; | |
874 | ||
5cc914f1 MA |
875 | MLX4_PUT(outbox->buf, port_type, |
876 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); | |
6634961c JM |
877 | |
878 | short_field = 1; /* slave max gids */ | |
879 | MLX4_PUT(outbox->buf, short_field, | |
880 | QUERY_PORT_CUR_MAX_GID_OFFSET); | |
881 | ||
882 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; | |
883 | MLX4_PUT(outbox->buf, short_field, | |
884 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); | |
5cc914f1 MA |
885 | } |
886 | ||
887 | return err; | |
888 | } | |
889 | ||
6634961c JM |
890 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
891 | int *gid_tbl_len, int *pkey_tbl_len) | |
892 | { | |
893 | struct mlx4_cmd_mailbox *mailbox; | |
894 | u32 *outbox; | |
895 | u16 field; | |
896 | int err; | |
897 | ||
898 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
899 | if (IS_ERR(mailbox)) | |
900 | return PTR_ERR(mailbox); | |
901 | ||
902 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, | |
903 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, | |
904 | MLX4_CMD_WRAPPED); | |
905 | if (err) | |
906 | goto out; | |
907 | ||
908 | outbox = mailbox->buf; | |
909 | ||
910 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); | |
911 | *gid_tbl_len = field; | |
912 | ||
913 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); | |
914 | *pkey_tbl_len = field; | |
915 | ||
916 | out: | |
917 | mlx4_free_cmd_mailbox(dev, mailbox); | |
918 | return err; | |
919 | } | |
920 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); | |
921 | ||
225c7b1f RD |
922 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
923 | { | |
924 | struct mlx4_cmd_mailbox *mailbox; | |
925 | struct mlx4_icm_iter iter; | |
926 | __be64 *pages; | |
927 | int lg; | |
928 | int nent = 0; | |
929 | int i; | |
930 | int err = 0; | |
931 | int ts = 0, tc = 0; | |
932 | ||
933 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
934 | if (IS_ERR(mailbox)) | |
935 | return PTR_ERR(mailbox); | |
936 | memset(mailbox->buf, 0, MLX4_MAILBOX_SIZE); | |
937 | pages = mailbox->buf; | |
938 | ||
939 | for (mlx4_icm_first(icm, &iter); | |
940 | !mlx4_icm_last(&iter); | |
941 | mlx4_icm_next(&iter)) { | |
942 | /* | |
943 | * We have to pass pages that are aligned to their | |
944 | * size, so find the least significant 1 in the | |
945 | * address or size and use that as our log2 size. | |
946 | */ | |
947 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; | |
948 | if (lg < MLX4_ICM_PAGE_SHIFT) { | |
949 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", | |
950 | MLX4_ICM_PAGE_SIZE, | |
951 | (unsigned long long) mlx4_icm_addr(&iter), | |
952 | mlx4_icm_size(&iter)); | |
953 | err = -EINVAL; | |
954 | goto out; | |
955 | } | |
956 | ||
957 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { | |
958 | if (virt != -1) { | |
959 | pages[nent * 2] = cpu_to_be64(virt); | |
960 | virt += 1 << lg; | |
961 | } | |
962 | ||
963 | pages[nent * 2 + 1] = | |
964 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | | |
965 | (lg - MLX4_ICM_PAGE_SHIFT)); | |
966 | ts += 1 << (lg - 10); | |
967 | ++tc; | |
968 | ||
969 | if (++nent == MLX4_MAILBOX_SIZE / 16) { | |
970 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, | |
f9baff50 JM |
971 | MLX4_CMD_TIME_CLASS_B, |
972 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
973 | if (err) |
974 | goto out; | |
975 | nent = 0; | |
976 | } | |
977 | } | |
978 | } | |
979 | ||
980 | if (nent) | |
f9baff50 JM |
981 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
982 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
983 | if (err) |
984 | goto out; | |
985 | ||
986 | switch (op) { | |
987 | case MLX4_CMD_MAP_FA: | |
988 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW.\n", tc, ts); | |
989 | break; | |
990 | case MLX4_CMD_MAP_ICM_AUX: | |
991 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux.\n", tc, ts); | |
992 | break; | |
993 | case MLX4_CMD_MAP_ICM: | |
994 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM.\n", | |
995 | tc, ts, (unsigned long long) virt - (ts << 10)); | |
996 | break; | |
997 | } | |
998 | ||
999 | out: | |
1000 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1001 | return err; | |
1002 | } | |
1003 | ||
1004 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) | |
1005 | { | |
1006 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); | |
1007 | } | |
1008 | ||
1009 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) | |
1010 | { | |
f9baff50 JM |
1011 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
1012 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); | |
225c7b1f RD |
1013 | } |
1014 | ||
1015 | ||
1016 | int mlx4_RUN_FW(struct mlx4_dev *dev) | |
1017 | { | |
f9baff50 JM |
1018 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
1019 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
225c7b1f RD |
1020 | } |
1021 | ||
1022 | int mlx4_QUERY_FW(struct mlx4_dev *dev) | |
1023 | { | |
1024 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; | |
1025 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; | |
1026 | struct mlx4_cmd_mailbox *mailbox; | |
1027 | u32 *outbox; | |
1028 | int err = 0; | |
1029 | u64 fw_ver; | |
fe40900f | 1030 | u16 cmd_if_rev; |
225c7b1f RD |
1031 | u8 lg; |
1032 | ||
1033 | #define QUERY_FW_OUT_SIZE 0x100 | |
1034 | #define QUERY_FW_VER_OFFSET 0x00 | |
5cc914f1 | 1035 | #define QUERY_FW_PPF_ID 0x09 |
fe40900f | 1036 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
225c7b1f RD |
1037 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
1038 | #define QUERY_FW_ERR_START_OFFSET 0x30 | |
1039 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 | |
1040 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c | |
1041 | ||
1042 | #define QUERY_FW_SIZE_OFFSET 0x00 | |
1043 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 | |
1044 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 | |
1045 | ||
5cc914f1 MA |
1046 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
1047 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 | |
1048 | ||
ddd8a6c1 EE |
1049 | #define QUERY_FW_CLOCK_OFFSET 0x50 |
1050 | #define QUERY_FW_CLOCK_BAR 0x58 | |
1051 | ||
225c7b1f RD |
1052 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1053 | if (IS_ERR(mailbox)) | |
1054 | return PTR_ERR(mailbox); | |
1055 | outbox = mailbox->buf; | |
1056 | ||
1057 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
f9baff50 | 1058 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1059 | if (err) |
1060 | goto out; | |
1061 | ||
1062 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); | |
1063 | /* | |
3e1db334 | 1064 | * FW subminor version is at more significant bits than minor |
225c7b1f RD |
1065 | * version, so swap here. |
1066 | */ | |
1067 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | | |
1068 | ((fw_ver & 0xffff0000ull) >> 16) | | |
1069 | ((fw_ver & 0x0000ffffull) << 16); | |
1070 | ||
752a50ca JM |
1071 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
1072 | dev->caps.function = lg; | |
1073 | ||
b91cb3eb JM |
1074 | if (mlx4_is_slave(dev)) |
1075 | goto out; | |
1076 | ||
5cc914f1 | 1077 | |
fe40900f | 1078 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
5ae2a7a8 RD |
1079 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
1080 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { | |
fe40900f RD |
1081 | mlx4_err(dev, "Installed FW has unsupported " |
1082 | "command interface revision %d.\n", | |
1083 | cmd_if_rev); | |
1084 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", | |
1085 | (int) (dev->caps.fw_ver >> 32), | |
1086 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
1087 | (int) dev->caps.fw_ver & 0xffff); | |
5ae2a7a8 RD |
1088 | mlx4_err(dev, "This driver version supports only revisions %d to %d.\n", |
1089 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); | |
fe40900f RD |
1090 | err = -ENODEV; |
1091 | goto out; | |
1092 | } | |
1093 | ||
5ae2a7a8 RD |
1094 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
1095 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; | |
1096 | ||
225c7b1f RD |
1097 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
1098 | cmd->max_cmds = 1 << lg; | |
1099 | ||
fe40900f | 1100 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
225c7b1f RD |
1101 | (int) (dev->caps.fw_ver >> 32), |
1102 | (int) (dev->caps.fw_ver >> 16) & 0xffff, | |
1103 | (int) dev->caps.fw_ver & 0xffff, | |
fe40900f | 1104 | cmd_if_rev, cmd->max_cmds); |
225c7b1f RD |
1105 | |
1106 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); | |
1107 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); | |
1108 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); | |
1109 | fw->catas_bar = (fw->catas_bar >> 6) * 2; | |
1110 | ||
1111 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", | |
1112 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); | |
1113 | ||
1114 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); | |
1115 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); | |
1116 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); | |
1117 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; | |
1118 | ||
5cc914f1 MA |
1119 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
1120 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); | |
1121 | fw->comm_bar = (fw->comm_bar >> 6) * 2; | |
1122 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", | |
1123 | fw->comm_bar, fw->comm_base); | |
225c7b1f RD |
1124 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
1125 | ||
ddd8a6c1 EE |
1126 | MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); |
1127 | MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); | |
1128 | fw->clock_bar = (fw->clock_bar >> 6) * 2; | |
1129 | mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", | |
1130 | fw->clock_bar, fw->clock_offset); | |
1131 | ||
225c7b1f RD |
1132 | /* |
1133 | * Round up number of system pages needed in case | |
1134 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1135 | */ | |
1136 | fw->fw_pages = | |
1137 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1138 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1139 | ||
1140 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", | |
1141 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); | |
1142 | ||
1143 | out: | |
1144 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1145 | return err; | |
1146 | } | |
1147 | ||
b91cb3eb JM |
1148 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
1149 | struct mlx4_vhcr *vhcr, | |
1150 | struct mlx4_cmd_mailbox *inbox, | |
1151 | struct mlx4_cmd_mailbox *outbox, | |
1152 | struct mlx4_cmd_info *cmd) | |
1153 | { | |
1154 | u8 *outbuf; | |
1155 | int err; | |
1156 | ||
1157 | outbuf = outbox->buf; | |
1158 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, | |
1159 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1160 | if (err) | |
1161 | return err; | |
1162 | ||
752a50ca JM |
1163 | /* for slaves, set pci PPF ID to invalid and zero out everything |
1164 | * else except FW version */ | |
b91cb3eb JM |
1165 | outbuf[0] = outbuf[1] = 0; |
1166 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); | |
752a50ca JM |
1167 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
1168 | ||
b91cb3eb JM |
1169 | return 0; |
1170 | } | |
1171 | ||
225c7b1f RD |
1172 | static void get_board_id(void *vsd, char *board_id) |
1173 | { | |
1174 | int i; | |
1175 | ||
1176 | #define VSD_OFFSET_SIG1 0x00 | |
1177 | #define VSD_OFFSET_SIG2 0xde | |
1178 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 | |
1179 | #define VSD_OFFSET_TS_BOARD_ID 0x20 | |
1180 | ||
1181 | #define VSD_SIGNATURE_TOPSPIN 0x5ad | |
1182 | ||
1183 | memset(board_id, 0, MLX4_BOARD_ID_LEN); | |
1184 | ||
1185 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && | |
1186 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { | |
1187 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); | |
1188 | } else { | |
1189 | /* | |
1190 | * The board ID is a string but the firmware byte | |
1191 | * swaps each 4-byte word before passing it back to | |
1192 | * us. Therefore we need to swab it before printing. | |
1193 | */ | |
1194 | for (i = 0; i < 4; ++i) | |
1195 | ((u32 *) board_id)[i] = | |
1196 | swab32(*(u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4)); | |
1197 | } | |
1198 | } | |
1199 | ||
1200 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) | |
1201 | { | |
1202 | struct mlx4_cmd_mailbox *mailbox; | |
1203 | u32 *outbox; | |
1204 | int err; | |
1205 | ||
1206 | #define QUERY_ADAPTER_OUT_SIZE 0x100 | |
225c7b1f RD |
1207 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
1208 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 | |
1209 | ||
1210 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1211 | if (IS_ERR(mailbox)) | |
1212 | return PTR_ERR(mailbox); | |
1213 | outbox = mailbox->buf; | |
1214 | ||
1215 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, | |
f9baff50 | 1216 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1217 | if (err) |
1218 | goto out; | |
1219 | ||
225c7b1f RD |
1220 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
1221 | ||
1222 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, | |
1223 | adapter->board_id); | |
1224 | ||
1225 | out: | |
1226 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1227 | return err; | |
1228 | } | |
1229 | ||
1230 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) | |
1231 | { | |
1232 | struct mlx4_cmd_mailbox *mailbox; | |
1233 | __be32 *inbox; | |
1234 | int err; | |
1235 | ||
1236 | #define INIT_HCA_IN_SIZE 0x200 | |
1237 | #define INIT_HCA_VERSION_OFFSET 0x000 | |
1238 | #define INIT_HCA_VERSION 2 | |
c57e20dc | 1239 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
225c7b1f RD |
1240 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
1241 | #define INIT_HCA_QPC_OFFSET 0x020 | |
1242 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) | |
1243 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) | |
1244 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) | |
1245 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) | |
1246 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) | |
1247 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) | |
5cc914f1 | 1248 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
225c7b1f RD |
1249 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
1250 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) | |
1251 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) | |
1252 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) | |
1253 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) | |
1254 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) | |
1255 | #define INIT_HCA_MCAST_OFFSET 0x0c0 | |
1256 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) | |
1257 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) | |
1258 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) | |
1679200f | 1259 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
225c7b1f | 1260 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
0ff1fb65 HHZ |
1261 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
1262 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 | |
1263 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) | |
1264 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) | |
1265 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) | |
1266 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) | |
1267 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) | |
1268 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) | |
1269 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) | |
225c7b1f RD |
1270 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
1271 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) | |
e448834e | 1272 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
225c7b1f RD |
1273 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
1274 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) | |
1275 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) | |
1276 | #define INIT_HCA_UAR_OFFSET 0x120 | |
1277 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) | |
1278 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) | |
1279 | ||
1280 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1281 | if (IS_ERR(mailbox)) | |
1282 | return PTR_ERR(mailbox); | |
1283 | inbox = mailbox->buf; | |
1284 | ||
1285 | memset(inbox, 0, INIT_HCA_IN_SIZE); | |
1286 | ||
1287 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; | |
1288 | ||
c57e20dc EC |
1289 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
1290 | (ilog2(cache_line_size()) - 4) << 5; | |
1291 | ||
225c7b1f RD |
1292 | #if defined(__LITTLE_ENDIAN) |
1293 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); | |
1294 | #elif defined(__BIG_ENDIAN) | |
1295 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); | |
1296 | #else | |
1297 | #error Host endianness not defined | |
1298 | #endif | |
1299 | /* Check port for UD address vector: */ | |
1300 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); | |
1301 | ||
8ff095ec EC |
1302 | /* Enable IPoIB checksumming if we can: */ |
1303 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) | |
1304 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); | |
1305 | ||
51f5f0ee JM |
1306 | /* Enable QoS support if module parameter set */ |
1307 | if (enable_qos) | |
1308 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); | |
1309 | ||
f2a3f6a3 OG |
1310 | /* enable counters */ |
1311 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) | |
1312 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); | |
1313 | ||
08ff3235 OG |
1314 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
1315 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { | |
1316 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); | |
1317 | dev->caps.eqe_size = 64; | |
1318 | dev->caps.eqe_factor = 1; | |
1319 | } else { | |
1320 | dev->caps.eqe_size = 32; | |
1321 | dev->caps.eqe_factor = 0; | |
1322 | } | |
1323 | ||
1324 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { | |
1325 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); | |
1326 | dev->caps.cqe_size = 64; | |
1327 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; | |
1328 | } else { | |
1329 | dev->caps.cqe_size = 32; | |
1330 | } | |
1331 | ||
225c7b1f RD |
1332 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
1333 | ||
1334 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); | |
1335 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); | |
1336 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); | |
1337 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); | |
1338 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); | |
1339 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); | |
1340 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); | |
1341 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); | |
1342 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); | |
1343 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); | |
1344 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); | |
1345 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); | |
1346 | ||
0ff1fb65 HHZ |
1347 | /* steering attributes */ |
1348 | if (dev->caps.steering_mode == | |
1349 | MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
1350 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= | |
1351 | cpu_to_be32(1 << | |
1352 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); | |
1353 | ||
1354 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); | |
1355 | MLX4_PUT(inbox, param->log_mc_entry_sz, | |
1356 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); | |
1357 | MLX4_PUT(inbox, param->log_mc_table_sz, | |
1358 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); | |
1359 | /* Enable Ethernet flow steering | |
1360 | * with udp unicast and tcp unicast | |
1361 | */ | |
23537b73 | 1362 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
0ff1fb65 HHZ |
1363 | INIT_HCA_FS_ETH_BITS_OFFSET); |
1364 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, | |
1365 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); | |
1366 | /* Enable IPoIB flow steering | |
1367 | * with udp unicast and tcp unicast | |
1368 | */ | |
23537b73 | 1369 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
0ff1fb65 HHZ |
1370 | INIT_HCA_FS_IB_BITS_OFFSET); |
1371 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, | |
1372 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); | |
1373 | } else { | |
1374 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); | |
1375 | MLX4_PUT(inbox, param->log_mc_entry_sz, | |
1376 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1377 | MLX4_PUT(inbox, param->log_mc_hash_sz, | |
1378 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1379 | MLX4_PUT(inbox, param->log_mc_table_sz, | |
1380 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1381 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) | |
1382 | MLX4_PUT(inbox, (u8) (1 << 3), | |
1383 | INIT_HCA_UC_STEERING_OFFSET); | |
1384 | } | |
225c7b1f RD |
1385 | |
1386 | /* TPT attributes */ | |
1387 | ||
1388 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); | |
e448834e | 1389 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
225c7b1f RD |
1390 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
1391 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); | |
1392 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); | |
1393 | ||
1394 | /* UAR attributes */ | |
1395 | ||
ab9c17a0 | 1396 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
225c7b1f RD |
1397 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
1398 | ||
f9baff50 JM |
1399 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, 10000, |
1400 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1401 | |
1402 | if (err) | |
1403 | mlx4_err(dev, "INIT_HCA returns %d\n", err); | |
1404 | ||
1405 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1406 | return err; | |
1407 | } | |
1408 | ||
ab9c17a0 JM |
1409 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
1410 | struct mlx4_init_hca_param *param) | |
1411 | { | |
1412 | struct mlx4_cmd_mailbox *mailbox; | |
1413 | __be32 *outbox; | |
7b8157be | 1414 | u32 dword_field; |
ab9c17a0 | 1415 | int err; |
08ff3235 | 1416 | u8 byte_field; |
ab9c17a0 JM |
1417 | |
1418 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 | |
ddd8a6c1 | 1419 | #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c |
ab9c17a0 JM |
1420 | |
1421 | mailbox = mlx4_alloc_cmd_mailbox(dev); | |
1422 | if (IS_ERR(mailbox)) | |
1423 | return PTR_ERR(mailbox); | |
1424 | outbox = mailbox->buf; | |
1425 | ||
1426 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, | |
1427 | MLX4_CMD_QUERY_HCA, | |
1428 | MLX4_CMD_TIME_CLASS_B, | |
1429 | !mlx4_is_slave(dev)); | |
1430 | if (err) | |
1431 | goto out; | |
1432 | ||
1433 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); | |
ddd8a6c1 | 1434 | MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
ab9c17a0 JM |
1435 | |
1436 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ | |
1437 | ||
1438 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); | |
1439 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); | |
1440 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); | |
1441 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); | |
1442 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); | |
1443 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); | |
1444 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); | |
1445 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); | |
1446 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); | |
1447 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); | |
1448 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); | |
1449 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); | |
1450 | ||
7b8157be JM |
1451 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
1452 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { | |
1453 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; | |
1454 | } else { | |
1455 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); | |
1456 | if (byte_field & 0x8) | |
1457 | param->steering_mode = MLX4_STEERING_MODE_B0; | |
1458 | else | |
1459 | param->steering_mode = MLX4_STEERING_MODE_A0; | |
1460 | } | |
0ff1fb65 | 1461 | /* steering attributes */ |
7b8157be | 1462 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
0ff1fb65 HHZ |
1463 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
1464 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1465 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); | |
1466 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1467 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); | |
1468 | } else { | |
1469 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); | |
1470 | MLX4_GET(param->log_mc_entry_sz, outbox, | |
1471 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); | |
1472 | MLX4_GET(param->log_mc_hash_sz, outbox, | |
1473 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); | |
1474 | MLX4_GET(param->log_mc_table_sz, outbox, | |
1475 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); | |
1476 | } | |
ab9c17a0 | 1477 | |
08ff3235 OG |
1478 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
1479 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); | |
1480 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ | |
1481 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; | |
1482 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ | |
1483 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; | |
1484 | ||
ab9c17a0 JM |
1485 | /* TPT attributes */ |
1486 | ||
1487 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); | |
e448834e | 1488 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
ab9c17a0 JM |
1489 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
1490 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); | |
1491 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); | |
1492 | ||
1493 | /* UAR attributes */ | |
1494 | ||
1495 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); | |
1496 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); | |
1497 | ||
1498 | out: | |
1499 | mlx4_free_cmd_mailbox(dev, mailbox); | |
1500 | ||
1501 | return err; | |
1502 | } | |
1503 | ||
980e9001 JM |
1504 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
1505 | * and real QP0 are active, so that the paravirtualized QP0 is ready | |
1506 | * to operate */ | |
1507 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) | |
1508 | { | |
1509 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1510 | /* irrelevant if not infiniband */ | |
1511 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && | |
1512 | priv->mfunc.master.qp0_state[port].qp0_active) | |
1513 | return 1; | |
1514 | return 0; | |
1515 | } | |
1516 | ||
5cc914f1 MA |
1517 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1518 | struct mlx4_vhcr *vhcr, | |
1519 | struct mlx4_cmd_mailbox *inbox, | |
1520 | struct mlx4_cmd_mailbox *outbox, | |
1521 | struct mlx4_cmd_info *cmd) | |
1522 | { | |
1523 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1524 | int port = vhcr->in_modifier; | |
1525 | int err; | |
1526 | ||
1527 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) | |
1528 | return 0; | |
1529 | ||
980e9001 JM |
1530 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
1531 | /* Enable port only if it was previously disabled */ | |
1532 | if (!priv->mfunc.master.init_port_ref[port]) { | |
1533 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1534 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1535 | if (err) | |
1536 | return err; | |
1537 | } | |
1538 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
1539 | } else { | |
1540 | if (slave == mlx4_master_func_num(dev)) { | |
1541 | if (check_qp0_state(dev, slave, port) && | |
1542 | !priv->mfunc.master.qp0_state[port].port_active) { | |
1543 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
1544 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); | |
1545 | if (err) | |
1546 | return err; | |
1547 | priv->mfunc.master.qp0_state[port].port_active = 1; | |
1548 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
1549 | } | |
1550 | } else | |
1551 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); | |
5cc914f1 MA |
1552 | } |
1553 | ++priv->mfunc.master.init_port_ref[port]; | |
1554 | return 0; | |
1555 | } | |
1556 | ||
5ae2a7a8 | 1557 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
225c7b1f RD |
1558 | { |
1559 | struct mlx4_cmd_mailbox *mailbox; | |
1560 | u32 *inbox; | |
1561 | int err; | |
1562 | u32 flags; | |
5ae2a7a8 | 1563 | u16 field; |
225c7b1f | 1564 | |
5ae2a7a8 | 1565 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
225c7b1f RD |
1566 | #define INIT_PORT_IN_SIZE 256 |
1567 | #define INIT_PORT_FLAGS_OFFSET 0x00 | |
1568 | #define INIT_PORT_FLAG_SIG (1 << 18) | |
1569 | #define INIT_PORT_FLAG_NG (1 << 17) | |
1570 | #define INIT_PORT_FLAG_G0 (1 << 16) | |
1571 | #define INIT_PORT_VL_SHIFT 4 | |
1572 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 | |
1573 | #define INIT_PORT_MTU_OFFSET 0x04 | |
1574 | #define INIT_PORT_MAX_GID_OFFSET 0x06 | |
1575 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a | |
1576 | #define INIT_PORT_GUID0_OFFSET 0x10 | |
1577 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 | |
1578 | #define INIT_PORT_SI_GUID_OFFSET 0x20 | |
1579 | ||
5ae2a7a8 RD |
1580 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
1581 | if (IS_ERR(mailbox)) | |
1582 | return PTR_ERR(mailbox); | |
1583 | inbox = mailbox->buf; | |
225c7b1f | 1584 | |
5ae2a7a8 | 1585 | memset(inbox, 0, INIT_PORT_IN_SIZE); |
225c7b1f | 1586 | |
5ae2a7a8 RD |
1587 | flags = 0; |
1588 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; | |
1589 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; | |
1590 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); | |
225c7b1f | 1591 | |
b79acb49 | 1592 | field = 128 << dev->caps.ib_mtu_cap[port]; |
5ae2a7a8 RD |
1593 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
1594 | field = dev->caps.gid_table_len[port]; | |
1595 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); | |
1596 | field = dev->caps.pkey_table_len[port]; | |
1597 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); | |
225c7b1f | 1598 | |
5ae2a7a8 | 1599 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
f9baff50 | 1600 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f | 1601 | |
5ae2a7a8 RD |
1602 | mlx4_free_cmd_mailbox(dev, mailbox); |
1603 | } else | |
1604 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, | |
f9baff50 | 1605 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
225c7b1f RD |
1606 | |
1607 | return err; | |
1608 | } | |
1609 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); | |
1610 | ||
5cc914f1 MA |
1611 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1612 | struct mlx4_vhcr *vhcr, | |
1613 | struct mlx4_cmd_mailbox *inbox, | |
1614 | struct mlx4_cmd_mailbox *outbox, | |
1615 | struct mlx4_cmd_info *cmd) | |
1616 | { | |
1617 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1618 | int port = vhcr->in_modifier; | |
1619 | int err; | |
1620 | ||
1621 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & | |
1622 | (1 << port))) | |
1623 | return 0; | |
1624 | ||
980e9001 JM |
1625 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
1626 | if (priv->mfunc.master.init_port_ref[port] == 1) { | |
1627 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, | |
1628 | 1000, MLX4_CMD_NATIVE); | |
1629 | if (err) | |
1630 | return err; | |
1631 | } | |
1632 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1633 | } else { | |
1634 | /* infiniband port */ | |
1635 | if (slave == mlx4_master_func_num(dev)) { | |
1636 | if (!priv->mfunc.master.qp0_state[port].qp0_active && | |
1637 | priv->mfunc.master.qp0_state[port].port_active) { | |
1638 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, | |
1639 | 1000, MLX4_CMD_NATIVE); | |
1640 | if (err) | |
1641 | return err; | |
1642 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
1643 | priv->mfunc.master.qp0_state[port].port_active = 0; | |
1644 | } | |
1645 | } else | |
1646 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); | |
5cc914f1 | 1647 | } |
5cc914f1 MA |
1648 | --priv->mfunc.master.init_port_ref[port]; |
1649 | return 0; | |
1650 | } | |
1651 | ||
225c7b1f RD |
1652 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
1653 | { | |
f9baff50 JM |
1654 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, 1000, |
1655 | MLX4_CMD_WRAPPED); | |
225c7b1f RD |
1656 | } |
1657 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); | |
1658 | ||
1659 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) | |
1660 | { | |
f9baff50 JM |
1661 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, 1000, |
1662 | MLX4_CMD_NATIVE); | |
225c7b1f RD |
1663 | } |
1664 | ||
1665 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) | |
1666 | { | |
1667 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, | |
1668 | MLX4_CMD_SET_ICM_SIZE, | |
f9baff50 | 1669 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
225c7b1f RD |
1670 | if (ret) |
1671 | return ret; | |
1672 | ||
1673 | /* | |
1674 | * Round up number of system pages needed in case | |
1675 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. | |
1676 | */ | |
1677 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> | |
1678 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); | |
1679 | ||
1680 | return 0; | |
1681 | } | |
1682 | ||
1683 | int mlx4_NOP(struct mlx4_dev *dev) | |
1684 | { | |
1685 | /* Input modifier of 0x1f means "finish as soon as possible." */ | |
f9baff50 | 1686 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, 100, MLX4_CMD_NATIVE); |
225c7b1f | 1687 | } |
14c07b13 YP |
1688 | |
1689 | #define MLX4_WOL_SETUP_MODE (5 << 28) | |
1690 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) | |
1691 | { | |
1692 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1693 | ||
1694 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, | |
f9baff50 JM |
1695 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
1696 | MLX4_CMD_NATIVE); | |
14c07b13 YP |
1697 | } |
1698 | EXPORT_SYMBOL_GPL(mlx4_wol_read); | |
1699 | ||
1700 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) | |
1701 | { | |
1702 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; | |
1703 | ||
1704 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, | |
f9baff50 | 1705 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
14c07b13 YP |
1706 | } |
1707 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |