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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
c1b43dca | 42 | #include <linux/io-mapping.h> |
ab9c17a0 | 43 | #include <linux/delay.h> |
225c7b1f RD |
44 | |
45 | #include <linux/mlx4/device.h> | |
46 | #include <linux/mlx4/doorbell.h> | |
47 | ||
48 | #include "mlx4.h" | |
49 | #include "fw.h" | |
50 | #include "icm.h" | |
51 | ||
52 | MODULE_AUTHOR("Roland Dreier"); | |
53 | MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); | |
54 | MODULE_LICENSE("Dual BSD/GPL"); | |
55 | MODULE_VERSION(DRV_VERSION); | |
56 | ||
27bf91d6 YP |
57 | struct workqueue_struct *mlx4_wq; |
58 | ||
225c7b1f RD |
59 | #ifdef CONFIG_MLX4_DEBUG |
60 | ||
61 | int mlx4_debug_level = 0; | |
62 | module_param_named(debug_level, mlx4_debug_level, int, 0644); | |
63 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
64 | ||
65 | #endif /* CONFIG_MLX4_DEBUG */ | |
66 | ||
67 | #ifdef CONFIG_PCI_MSI | |
68 | ||
08fb1055 | 69 | static int msi_x = 1; |
225c7b1f RD |
70 | module_param(msi_x, int, 0444); |
71 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
72 | ||
73 | #else /* CONFIG_PCI_MSI */ | |
74 | ||
75 | #define msi_x (0) | |
76 | ||
77 | #endif /* CONFIG_PCI_MSI */ | |
78 | ||
ab9c17a0 JM |
79 | static int num_vfs; |
80 | module_param(num_vfs, int, 0444); | |
81 | MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0"); | |
82 | ||
83 | static int probe_vf; | |
84 | module_param(probe_vf, int, 0644); | |
85 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)"); | |
86 | ||
0ec2c0f8 EE |
87 | int mlx4_log_num_mgm_entry_size = 10; |
88 | module_param_named(log_num_mgm_entry_size, | |
89 | mlx4_log_num_mgm_entry_size, int, 0444); | |
90 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" | |
91 | " of qp per mcg, for example:" | |
92 | " 10 gives 248.range: 9<=" | |
93 | " log_num_mgm_entry_size <= 12"); | |
94 | ||
ab9c17a0 JM |
95 | #define MLX4_VF (1 << 0) |
96 | ||
97 | #define HCA_GLOBAL_CAP_MASK 0 | |
98 | #define PF_CONTEXT_BEHAVIOUR_MASK 0 | |
99 | ||
f33afc26 | 100 | static char mlx4_version[] __devinitdata = |
225c7b1f RD |
101 | DRV_NAME ": Mellanox ConnectX core driver v" |
102 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
103 | ||
104 | static struct mlx4_profile default_profile = { | |
ab9c17a0 | 105 | .num_qp = 1 << 18, |
225c7b1f | 106 | .num_srq = 1 << 16, |
c9f2ba5e | 107 | .rdmarc_per_qp = 1 << 4, |
225c7b1f RD |
108 | .num_cq = 1 << 16, |
109 | .num_mcg = 1 << 13, | |
ab9c17a0 | 110 | .num_mpt = 1 << 19, |
9fd7a1e1 | 111 | .num_mtt = 1 << 20, /* It is really num mtt segements */ |
225c7b1f RD |
112 | }; |
113 | ||
ab9c17a0 | 114 | static int log_num_mac = 7; |
93fc9e1b YP |
115 | module_param_named(log_num_mac, log_num_mac, int, 0444); |
116 | MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); | |
117 | ||
118 | static int log_num_vlan; | |
119 | module_param_named(log_num_vlan, log_num_vlan, int, 0444); | |
120 | MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); | |
cb29688a OG |
121 | /* Log2 max number of VLANs per ETH port (0-7) */ |
122 | #define MLX4_LOG_NUM_VLANS 7 | |
93fc9e1b | 123 | |
eb939922 | 124 | static bool use_prio; |
93fc9e1b YP |
125 | module_param_named(use_prio, use_prio, bool, 0444); |
126 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " | |
127 | "(0/1, default 0)"); | |
128 | ||
2b8fb286 | 129 | int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); |
ab6bf42e | 130 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); |
0498628f | 131 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); |
ab6bf42e | 132 | |
8d0fc7b6 | 133 | static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; |
ab9c17a0 JM |
134 | static int arr_argc = 2; |
135 | module_param_array(port_type_array, int, &arr_argc, 0444); | |
8d0fc7b6 YP |
136 | MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " |
137 | "1 for IB, 2 for Ethernet"); | |
ab9c17a0 JM |
138 | |
139 | struct mlx4_port_config { | |
140 | struct list_head list; | |
141 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; | |
142 | struct pci_dev *pdev; | |
143 | }; | |
144 | ||
27bf91d6 YP |
145 | int mlx4_check_port_params(struct mlx4_dev *dev, |
146 | enum mlx4_port_type *port_type) | |
7ff93f8b YP |
147 | { |
148 | int i; | |
149 | ||
150 | for (i = 0; i < dev->caps.num_ports - 1; i++) { | |
27bf91d6 YP |
151 | if (port_type[i] != port_type[i + 1]) { |
152 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { | |
153 | mlx4_err(dev, "Only same port types supported " | |
154 | "on this HCA, aborting.\n"); | |
155 | return -EINVAL; | |
156 | } | |
157 | if (port_type[i] == MLX4_PORT_TYPE_ETH && | |
158 | port_type[i + 1] == MLX4_PORT_TYPE_IB) | |
159 | return -EINVAL; | |
7ff93f8b YP |
160 | } |
161 | } | |
7ff93f8b YP |
162 | |
163 | for (i = 0; i < dev->caps.num_ports; i++) { | |
164 | if (!(port_type[i] & dev->caps.supported_type[i+1])) { | |
165 | mlx4_err(dev, "Requested port type for port %d is not " | |
166 | "supported on this HCA\n", i + 1); | |
167 | return -EINVAL; | |
168 | } | |
169 | } | |
170 | return 0; | |
171 | } | |
172 | ||
173 | static void mlx4_set_port_mask(struct mlx4_dev *dev) | |
174 | { | |
175 | int i; | |
176 | ||
7ff93f8b | 177 | for (i = 1; i <= dev->caps.num_ports; ++i) |
65dab25d | 178 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
7ff93f8b | 179 | } |
f2a3f6a3 | 180 | |
3d73c288 | 181 | static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
225c7b1f RD |
182 | { |
183 | int err; | |
5ae2a7a8 | 184 | int i; |
225c7b1f RD |
185 | |
186 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
187 | if (err) { | |
188 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
189 | return err; | |
190 | } | |
191 | ||
192 | if (dev_cap->min_page_sz > PAGE_SIZE) { | |
193 | mlx4_err(dev, "HCA minimum page size of %d bigger than " | |
194 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
195 | dev_cap->min_page_sz, PAGE_SIZE); | |
196 | return -ENODEV; | |
197 | } | |
198 | if (dev_cap->num_ports > MLX4_MAX_PORTS) { | |
199 | mlx4_err(dev, "HCA has %d ports, but we only support %d, " | |
200 | "aborting.\n", | |
201 | dev_cap->num_ports, MLX4_MAX_PORTS); | |
202 | return -ENODEV; | |
203 | } | |
204 | ||
205 | if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { | |
206 | mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than " | |
207 | "PCI resource 2 size of 0x%llx, aborting.\n", | |
208 | dev_cap->uar_size, | |
209 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
210 | return -ENODEV; | |
211 | } | |
212 | ||
213 | dev->caps.num_ports = dev_cap->num_ports; | |
3fc929e2 | 214 | dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; |
5ae2a7a8 RD |
215 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
216 | dev->caps.vl_cap[i] = dev_cap->max_vl[i]; | |
b79acb49 | 217 | dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; |
5ae2a7a8 RD |
218 | dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; |
219 | dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; | |
220 | dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; | |
b79acb49 YP |
221 | dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; |
222 | dev->caps.def_mac[i] = dev_cap->def_mac[i]; | |
7ff93f8b | 223 | dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; |
8d0fc7b6 YP |
224 | dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; |
225 | dev->caps.default_sense[i] = dev_cap->default_sense[i]; | |
7699517d YP |
226 | dev->caps.trans_type[i] = dev_cap->trans_type[i]; |
227 | dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; | |
228 | dev->caps.wavelength[i] = dev_cap->wavelength[i]; | |
229 | dev->caps.trans_code[i] = dev_cap->trans_code[i]; | |
5ae2a7a8 RD |
230 | } |
231 | ||
ab9c17a0 | 232 | dev->caps.uar_page_size = PAGE_SIZE; |
225c7b1f | 233 | dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; |
225c7b1f RD |
234 | dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; |
235 | dev->caps.bf_reg_size = dev_cap->bf_reg_size; | |
236 | dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; | |
237 | dev->caps.max_sq_sg = dev_cap->max_sq_sg; | |
238 | dev->caps.max_rq_sg = dev_cap->max_rq_sg; | |
239 | dev->caps.max_wqes = dev_cap->max_qp_sz; | |
240 | dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; | |
225c7b1f RD |
241 | dev->caps.max_srq_wqes = dev_cap->max_srq_sz; |
242 | dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; | |
243 | dev->caps.reserved_srqs = dev_cap->reserved_srqs; | |
244 | dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; | |
245 | dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; | |
0ec2c0f8 | 246 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); |
225c7b1f RD |
247 | /* |
248 | * Subtract 1 from the limit because we need to allocate a | |
249 | * spare CQE so the HCA HW can tell the difference between an | |
250 | * empty CQ and a full CQ. | |
251 | */ | |
252 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | |
253 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | |
254 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | |
2b8fb286 | 255 | dev->caps.reserved_mtts = dev_cap->reserved_mtts; |
225c7b1f | 256 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
ab9c17a0 JM |
257 | |
258 | /* The first 128 UARs are used for EQ doorbells */ | |
259 | dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); | |
225c7b1f | 260 | dev->caps.reserved_pds = dev_cap->reserved_pds; |
012a8ff5 SH |
261 | dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? |
262 | dev_cap->reserved_xrcds : 0; | |
263 | dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? | |
264 | dev_cap->max_xrcds : 0; | |
2b8fb286 MA |
265 | dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; |
266 | ||
149983af | 267 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
225c7b1f RD |
268 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
269 | dev->caps.flags = dev_cap->flags; | |
b3416f44 | 270 | dev->caps.flags2 = dev_cap->flags2; |
95d04f07 RD |
271 | dev->caps.bmme_flags = dev_cap->bmme_flags; |
272 | dev->caps.reserved_lkey = dev_cap->reserved_lkey; | |
225c7b1f | 273 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
b832be1e | 274 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
b3416f44 | 275 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
225c7b1f | 276 | |
58a60168 YP |
277 | /* Sense port always allowed on supported devices for ConnectX1 and 2 */ |
278 | if (dev->pdev->device != 0x1003) | |
279 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; | |
280 | ||
93fc9e1b | 281 | dev->caps.log_num_macs = log_num_mac; |
cb29688a | 282 | dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; |
93fc9e1b YP |
283 | dev->caps.log_num_prios = use_prio ? 3 : 0; |
284 | ||
285 | for (i = 1; i <= dev->caps.num_ports; ++i) { | |
ab9c17a0 JM |
286 | dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; |
287 | if (dev->caps.supported_type[i]) { | |
288 | /* if only ETH is supported - assign ETH */ | |
289 | if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) | |
290 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
291 | /* if only IB is supported, | |
292 | * assign IB only if SRIOV is off*/ | |
293 | else if (dev->caps.supported_type[i] == | |
294 | MLX4_PORT_TYPE_IB) { | |
295 | if (dev->flags & MLX4_FLAG_SRIOV) | |
296 | dev->caps.port_type[i] = | |
297 | MLX4_PORT_TYPE_NONE; | |
298 | else | |
299 | dev->caps.port_type[i] = | |
300 | MLX4_PORT_TYPE_IB; | |
301 | /* if IB and ETH are supported, | |
302 | * first of all check if SRIOV is on */ | |
303 | } else if (dev->flags & MLX4_FLAG_SRIOV) | |
304 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
ab9c17a0 | 305 | else { |
8d0fc7b6 YP |
306 | /* In non-SRIOV mode, we set the port type |
307 | * according to user selection of port type, | |
308 | * if usere selected none, take the FW hint */ | |
309 | if (port_type_array[i-1] == MLX4_PORT_TYPE_NONE) | |
310 | dev->caps.port_type[i] = dev->caps.suggested_type[i] ? | |
311 | MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 312 | else |
8d0fc7b6 | 313 | dev->caps.port_type[i] = port_type_array[i-1]; |
ab9c17a0 JM |
314 | } |
315 | } | |
8d0fc7b6 YP |
316 | /* |
317 | * Link sensing is allowed on the port if 3 conditions are true: | |
318 | * 1. Both protocols are supported on the port. | |
319 | * 2. Different types are supported on the port | |
320 | * 3. FW declared that it supports link sensing | |
321 | */ | |
27bf91d6 | 322 | mlx4_priv(dev)->sense.sense_allowed[i] = |
58a60168 | 323 | ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && |
8d0fc7b6 | 324 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
58a60168 | 325 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); |
7ff93f8b | 326 | |
8d0fc7b6 YP |
327 | /* |
328 | * If "default_sense" bit is set, we move the port to "AUTO" mode | |
329 | * and perform sense_port FW command to try and set the correct | |
330 | * port type from beginning | |
331 | */ | |
46c46747 | 332 | if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { |
8d0fc7b6 YP |
333 | enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; |
334 | dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; | |
335 | mlx4_SENSE_PORT(dev, i, &sensed_port); | |
336 | if (sensed_port != MLX4_PORT_TYPE_NONE) | |
337 | dev->caps.port_type[i] = sensed_port; | |
338 | } else { | |
339 | dev->caps.possible_type[i] = dev->caps.port_type[i]; | |
340 | } | |
341 | ||
93fc9e1b YP |
342 | if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { |
343 | dev->caps.log_num_macs = dev_cap->log_max_macs[i]; | |
344 | mlx4_warn(dev, "Requested number of MACs is too much " | |
345 | "for port %d, reducing to %d.\n", | |
346 | i, 1 << dev->caps.log_num_macs); | |
347 | } | |
348 | if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { | |
349 | dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; | |
350 | mlx4_warn(dev, "Requested number of VLANs is too much " | |
351 | "for port %d, reducing to %d.\n", | |
352 | i, 1 << dev->caps.log_num_vlans); | |
353 | } | |
354 | } | |
355 | ||
f2a3f6a3 OG |
356 | dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); |
357 | ||
93fc9e1b YP |
358 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; |
359 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = | |
360 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = | |
361 | (1 << dev->caps.log_num_macs) * | |
362 | (1 << dev->caps.log_num_vlans) * | |
363 | (1 << dev->caps.log_num_prios) * | |
364 | dev->caps.num_ports; | |
365 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; | |
366 | ||
367 | dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + | |
368 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + | |
369 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + | |
370 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | |
371 | ||
225c7b1f RD |
372 | return 0; |
373 | } | |
ab9c17a0 JM |
374 | /*The function checks if there are live vf, return the num of them*/ |
375 | static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) | |
376 | { | |
377 | struct mlx4_priv *priv = mlx4_priv(dev); | |
378 | struct mlx4_slave_state *s_state; | |
379 | int i; | |
380 | int ret = 0; | |
381 | ||
382 | for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { | |
383 | s_state = &priv->mfunc.master.slave_state[i]; | |
384 | if (s_state->active && s_state->last_cmd != | |
385 | MLX4_COMM_CMD_RESET) { | |
386 | mlx4_warn(dev, "%s: slave: %d is still active\n", | |
387 | __func__, i); | |
388 | ret++; | |
389 | } | |
390 | } | |
391 | return ret; | |
392 | } | |
393 | ||
e10903b0 | 394 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) |
ab9c17a0 JM |
395 | { |
396 | struct mlx4_priv *priv = mlx4_priv(dev); | |
397 | struct mlx4_slave_state *s_slave; | |
398 | ||
399 | if (!mlx4_is_master(dev)) | |
400 | return 0; | |
401 | ||
402 | s_slave = &priv->mfunc.master.slave_state[slave]; | |
403 | return !!s_slave->active; | |
404 | } | |
405 | EXPORT_SYMBOL(mlx4_is_slave_active); | |
406 | ||
407 | static int mlx4_slave_cap(struct mlx4_dev *dev) | |
408 | { | |
409 | int err; | |
410 | u32 page_size; | |
411 | struct mlx4_dev_cap dev_cap; | |
412 | struct mlx4_func_cap func_cap; | |
413 | struct mlx4_init_hca_param hca_param; | |
414 | int i; | |
415 | ||
416 | memset(&hca_param, 0, sizeof(hca_param)); | |
417 | err = mlx4_QUERY_HCA(dev, &hca_param); | |
418 | if (err) { | |
419 | mlx4_err(dev, "QUERY_HCA command failed, aborting.\n"); | |
420 | return err; | |
421 | } | |
422 | ||
423 | /*fail if the hca has an unknown capability */ | |
424 | if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != | |
425 | HCA_GLOBAL_CAP_MASK) { | |
426 | mlx4_err(dev, "Unknown hca global capabilities\n"); | |
427 | return -ENOSYS; | |
428 | } | |
429 | ||
430 | mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; | |
431 | ||
432 | memset(&dev_cap, 0, sizeof(dev_cap)); | |
433 | err = mlx4_dev_cap(dev, &dev_cap); | |
434 | if (err) { | |
435 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
436 | return err; | |
437 | } | |
438 | ||
439 | page_size = ~dev->caps.page_size_cap + 1; | |
440 | mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); | |
441 | if (page_size > PAGE_SIZE) { | |
442 | mlx4_err(dev, "HCA minimum page size of %d bigger than " | |
443 | "kernel PAGE_SIZE of %ld, aborting.\n", | |
444 | page_size, PAGE_SIZE); | |
445 | return -ENODEV; | |
446 | } | |
447 | ||
448 | /* slave gets uar page size from QUERY_HCA fw command */ | |
449 | dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); | |
450 | ||
451 | /* TODO: relax this assumption */ | |
452 | if (dev->caps.uar_page_size != PAGE_SIZE) { | |
453 | mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", | |
454 | dev->caps.uar_page_size, PAGE_SIZE); | |
455 | return -ENODEV; | |
456 | } | |
457 | ||
458 | memset(&func_cap, 0, sizeof(func_cap)); | |
459 | err = mlx4_QUERY_FUNC_CAP(dev, &func_cap); | |
460 | if (err) { | |
461 | mlx4_err(dev, "QUERY_FUNC_CAP command failed, aborting.\n"); | |
462 | return err; | |
463 | } | |
464 | ||
465 | if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != | |
466 | PF_CONTEXT_BEHAVIOUR_MASK) { | |
467 | mlx4_err(dev, "Unknown pf context behaviour\n"); | |
468 | return -ENOSYS; | |
469 | } | |
470 | ||
ab9c17a0 JM |
471 | dev->caps.num_ports = func_cap.num_ports; |
472 | dev->caps.num_qps = func_cap.qp_quota; | |
473 | dev->caps.num_srqs = func_cap.srq_quota; | |
474 | dev->caps.num_cqs = func_cap.cq_quota; | |
475 | dev->caps.num_eqs = func_cap.max_eq; | |
476 | dev->caps.reserved_eqs = func_cap.reserved_eq; | |
477 | dev->caps.num_mpts = func_cap.mpt_quota; | |
478 | dev->caps.num_mtts = func_cap.mtt_quota; | |
479 | dev->caps.num_pds = MLX4_NUM_PDS; | |
480 | dev->caps.num_mgms = 0; | |
481 | dev->caps.num_amgms = 0; | |
482 | ||
483 | for (i = 1; i <= dev->caps.num_ports; ++i) | |
484 | dev->caps.port_mask[i] = dev->caps.port_type[i]; | |
485 | ||
486 | if (dev->caps.num_ports > MLX4_MAX_PORTS) { | |
487 | mlx4_err(dev, "HCA has %d ports, but we only support %d, " | |
488 | "aborting.\n", dev->caps.num_ports, MLX4_MAX_PORTS); | |
489 | return -ENODEV; | |
490 | } | |
491 | ||
492 | if (dev->caps.uar_page_size * (dev->caps.num_uars - | |
493 | dev->caps.reserved_uars) > | |
494 | pci_resource_len(dev->pdev, 2)) { | |
495 | mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than " | |
496 | "PCI resource 2 size of 0x%llx, aborting.\n", | |
497 | dev->caps.uar_page_size * dev->caps.num_uars, | |
498 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
499 | return -ENODEV; | |
500 | } | |
501 | ||
502 | #if 0 | |
503 | mlx4_warn(dev, "sqp_demux:%d\n", dev->caps.sqp_demux); | |
504 | mlx4_warn(dev, "num_uars:%d reserved_uars:%d uar region:0x%x bar2:0x%llx\n", | |
505 | dev->caps.num_uars, dev->caps.reserved_uars, | |
506 | dev->caps.uar_page_size * dev->caps.num_uars, | |
507 | pci_resource_len(dev->pdev, 2)); | |
508 | mlx4_warn(dev, "num_eqs:%d reserved_eqs:%d\n", dev->caps.num_eqs, | |
509 | dev->caps.reserved_eqs); | |
510 | mlx4_warn(dev, "num_pds:%d reserved_pds:%d slave_pd_shift:%d pd_base:%d\n", | |
511 | dev->caps.num_pds, dev->caps.reserved_pds, | |
512 | dev->caps.slave_pd_shift, dev->caps.pd_base); | |
513 | #endif | |
514 | return 0; | |
515 | } | |
225c7b1f | 516 | |
7ff93f8b YP |
517 | /* |
518 | * Change the port configuration of the device. | |
519 | * Every user of this function must hold the port mutex. | |
520 | */ | |
27bf91d6 YP |
521 | int mlx4_change_port_types(struct mlx4_dev *dev, |
522 | enum mlx4_port_type *port_types) | |
7ff93f8b YP |
523 | { |
524 | int err = 0; | |
525 | int change = 0; | |
526 | int port; | |
527 | ||
528 | for (port = 0; port < dev->caps.num_ports; port++) { | |
27bf91d6 YP |
529 | /* Change the port type only if the new type is different |
530 | * from the current, and not set to Auto */ | |
3d8f9308 | 531 | if (port_types[port] != dev->caps.port_type[port + 1]) |
7ff93f8b | 532 | change = 1; |
7ff93f8b YP |
533 | } |
534 | if (change) { | |
535 | mlx4_unregister_device(dev); | |
536 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
537 | mlx4_CLOSE_PORT(dev, port); | |
1e0f03d5 | 538 | dev->caps.port_type[port] = port_types[port - 1]; |
7ff93f8b YP |
539 | err = mlx4_SET_PORT(dev, port); |
540 | if (err) { | |
541 | mlx4_err(dev, "Failed to set port %d, " | |
542 | "aborting\n", port); | |
543 | goto out; | |
544 | } | |
545 | } | |
546 | mlx4_set_port_mask(dev); | |
547 | err = mlx4_register_device(dev); | |
548 | } | |
549 | ||
550 | out: | |
551 | return err; | |
552 | } | |
553 | ||
554 | static ssize_t show_port_type(struct device *dev, | |
555 | struct device_attribute *attr, | |
556 | char *buf) | |
557 | { | |
558 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
559 | port_attr); | |
560 | struct mlx4_dev *mdev = info->dev; | |
27bf91d6 YP |
561 | char type[8]; |
562 | ||
563 | sprintf(type, "%s", | |
564 | (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? | |
565 | "ib" : "eth"); | |
566 | if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) | |
567 | sprintf(buf, "auto (%s)\n", type); | |
568 | else | |
569 | sprintf(buf, "%s\n", type); | |
7ff93f8b | 570 | |
27bf91d6 | 571 | return strlen(buf); |
7ff93f8b YP |
572 | } |
573 | ||
574 | static ssize_t set_port_type(struct device *dev, | |
575 | struct device_attribute *attr, | |
576 | const char *buf, size_t count) | |
577 | { | |
578 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
579 | port_attr); | |
580 | struct mlx4_dev *mdev = info->dev; | |
581 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
582 | enum mlx4_port_type types[MLX4_MAX_PORTS]; | |
27bf91d6 | 583 | enum mlx4_port_type new_types[MLX4_MAX_PORTS]; |
7ff93f8b YP |
584 | int i; |
585 | int err = 0; | |
586 | ||
587 | if (!strcmp(buf, "ib\n")) | |
588 | info->tmp_type = MLX4_PORT_TYPE_IB; | |
589 | else if (!strcmp(buf, "eth\n")) | |
590 | info->tmp_type = MLX4_PORT_TYPE_ETH; | |
27bf91d6 YP |
591 | else if (!strcmp(buf, "auto\n")) |
592 | info->tmp_type = MLX4_PORT_TYPE_AUTO; | |
7ff93f8b YP |
593 | else { |
594 | mlx4_err(mdev, "%s is not supported port type\n", buf); | |
595 | return -EINVAL; | |
596 | } | |
597 | ||
27bf91d6 | 598 | mlx4_stop_sense(mdev); |
7ff93f8b | 599 | mutex_lock(&priv->port_mutex); |
27bf91d6 YP |
600 | /* Possible type is always the one that was delivered */ |
601 | mdev->caps.possible_type[info->port] = info->tmp_type; | |
602 | ||
603 | for (i = 0; i < mdev->caps.num_ports; i++) { | |
7ff93f8b | 604 | types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : |
27bf91d6 YP |
605 | mdev->caps.possible_type[i+1]; |
606 | if (types[i] == MLX4_PORT_TYPE_AUTO) | |
607 | types[i] = mdev->caps.port_type[i+1]; | |
608 | } | |
7ff93f8b | 609 | |
58a60168 YP |
610 | if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
611 | !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { | |
27bf91d6 YP |
612 | for (i = 1; i <= mdev->caps.num_ports; i++) { |
613 | if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { | |
614 | mdev->caps.possible_type[i] = mdev->caps.port_type[i]; | |
615 | err = -EINVAL; | |
616 | } | |
617 | } | |
618 | } | |
619 | if (err) { | |
620 | mlx4_err(mdev, "Auto sensing is not supported on this HCA. " | |
621 | "Set only 'eth' or 'ib' for both ports " | |
622 | "(should be the same)\n"); | |
623 | goto out; | |
624 | } | |
625 | ||
626 | mlx4_do_sense_ports(mdev, new_types, types); | |
627 | ||
628 | err = mlx4_check_port_params(mdev, new_types); | |
7ff93f8b YP |
629 | if (err) |
630 | goto out; | |
631 | ||
27bf91d6 YP |
632 | /* We are about to apply the changes after the configuration |
633 | * was verified, no need to remember the temporary types | |
634 | * any more */ | |
635 | for (i = 0; i < mdev->caps.num_ports; i++) | |
636 | priv->port[i + 1].tmp_type = 0; | |
7ff93f8b | 637 | |
27bf91d6 | 638 | err = mlx4_change_port_types(mdev, new_types); |
7ff93f8b YP |
639 | |
640 | out: | |
27bf91d6 | 641 | mlx4_start_sense(mdev); |
7ff93f8b YP |
642 | mutex_unlock(&priv->port_mutex); |
643 | return err ? err : count; | |
644 | } | |
645 | ||
096335b3 OG |
646 | enum ibta_mtu { |
647 | IB_MTU_256 = 1, | |
648 | IB_MTU_512 = 2, | |
649 | IB_MTU_1024 = 3, | |
650 | IB_MTU_2048 = 4, | |
651 | IB_MTU_4096 = 5 | |
652 | }; | |
653 | ||
654 | static inline int int_to_ibta_mtu(int mtu) | |
655 | { | |
656 | switch (mtu) { | |
657 | case 256: return IB_MTU_256; | |
658 | case 512: return IB_MTU_512; | |
659 | case 1024: return IB_MTU_1024; | |
660 | case 2048: return IB_MTU_2048; | |
661 | case 4096: return IB_MTU_4096; | |
662 | default: return -1; | |
663 | } | |
664 | } | |
665 | ||
666 | static inline int ibta_mtu_to_int(enum ibta_mtu mtu) | |
667 | { | |
668 | switch (mtu) { | |
669 | case IB_MTU_256: return 256; | |
670 | case IB_MTU_512: return 512; | |
671 | case IB_MTU_1024: return 1024; | |
672 | case IB_MTU_2048: return 2048; | |
673 | case IB_MTU_4096: return 4096; | |
674 | default: return -1; | |
675 | } | |
676 | } | |
677 | ||
678 | static ssize_t show_port_ib_mtu(struct device *dev, | |
679 | struct device_attribute *attr, | |
680 | char *buf) | |
681 | { | |
682 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
683 | port_mtu_attr); | |
684 | struct mlx4_dev *mdev = info->dev; | |
685 | ||
686 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) | |
687 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
688 | ||
689 | sprintf(buf, "%d\n", | |
690 | ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); | |
691 | return strlen(buf); | |
692 | } | |
693 | ||
694 | static ssize_t set_port_ib_mtu(struct device *dev, | |
695 | struct device_attribute *attr, | |
696 | const char *buf, size_t count) | |
697 | { | |
698 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
699 | port_mtu_attr); | |
700 | struct mlx4_dev *mdev = info->dev; | |
701 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
702 | int err, port, mtu, ibta_mtu = -1; | |
703 | ||
704 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { | |
705 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
706 | return -EINVAL; | |
707 | } | |
708 | ||
709 | err = sscanf(buf, "%d", &mtu); | |
710 | if (err > 0) | |
711 | ibta_mtu = int_to_ibta_mtu(mtu); | |
712 | ||
713 | if (err <= 0 || ibta_mtu < 0) { | |
714 | mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); | |
715 | return -EINVAL; | |
716 | } | |
717 | ||
718 | mdev->caps.port_ib_mtu[info->port] = ibta_mtu; | |
719 | ||
720 | mlx4_stop_sense(mdev); | |
721 | mutex_lock(&priv->port_mutex); | |
722 | mlx4_unregister_device(mdev); | |
723 | for (port = 1; port <= mdev->caps.num_ports; port++) { | |
724 | mlx4_CLOSE_PORT(mdev, port); | |
725 | err = mlx4_SET_PORT(mdev, port); | |
726 | if (err) { | |
727 | mlx4_err(mdev, "Failed to set port %d, " | |
728 | "aborting\n", port); | |
729 | goto err_set_port; | |
730 | } | |
731 | } | |
732 | err = mlx4_register_device(mdev); | |
733 | err_set_port: | |
734 | mutex_unlock(&priv->port_mutex); | |
735 | mlx4_start_sense(mdev); | |
736 | return err ? err : count; | |
737 | } | |
738 | ||
e8f9b2ed | 739 | static int mlx4_load_fw(struct mlx4_dev *dev) |
225c7b1f RD |
740 | { |
741 | struct mlx4_priv *priv = mlx4_priv(dev); | |
742 | int err; | |
743 | ||
744 | priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, | |
5b0bf5e2 | 745 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f RD |
746 | if (!priv->fw.fw_icm) { |
747 | mlx4_err(dev, "Couldn't allocate FW area, aborting.\n"); | |
748 | return -ENOMEM; | |
749 | } | |
750 | ||
751 | err = mlx4_MAP_FA(dev, priv->fw.fw_icm); | |
752 | if (err) { | |
753 | mlx4_err(dev, "MAP_FA command failed, aborting.\n"); | |
754 | goto err_free; | |
755 | } | |
756 | ||
757 | err = mlx4_RUN_FW(dev); | |
758 | if (err) { | |
759 | mlx4_err(dev, "RUN_FW command failed, aborting.\n"); | |
760 | goto err_unmap_fa; | |
761 | } | |
762 | ||
763 | return 0; | |
764 | ||
765 | err_unmap_fa: | |
766 | mlx4_UNMAP_FA(dev); | |
767 | ||
768 | err_free: | |
5b0bf5e2 | 769 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
770 | return err; |
771 | } | |
772 | ||
e8f9b2ed RD |
773 | static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, |
774 | int cmpt_entry_sz) | |
225c7b1f RD |
775 | { |
776 | struct mlx4_priv *priv = mlx4_priv(dev); | |
777 | int err; | |
ab9c17a0 | 778 | int num_eqs; |
225c7b1f RD |
779 | |
780 | err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, | |
781 | cmpt_base + | |
782 | ((u64) (MLX4_CMPT_TYPE_QP * | |
783 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
784 | cmpt_entry_sz, dev->caps.num_qps, | |
93fc9e1b YP |
785 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
786 | 0, 0); | |
225c7b1f RD |
787 | if (err) |
788 | goto err; | |
789 | ||
790 | err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, | |
791 | cmpt_base + | |
792 | ((u64) (MLX4_CMPT_TYPE_SRQ * | |
793 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
794 | cmpt_entry_sz, dev->caps.num_srqs, | |
5b0bf5e2 | 795 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
796 | if (err) |
797 | goto err_qp; | |
798 | ||
799 | err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, | |
800 | cmpt_base + | |
801 | ((u64) (MLX4_CMPT_TYPE_CQ * | |
802 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
803 | cmpt_entry_sz, dev->caps.num_cqs, | |
5b0bf5e2 | 804 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
805 | if (err) |
806 | goto err_srq; | |
807 | ||
3fc929e2 MA |
808 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
809 | dev->caps.num_eqs; | |
225c7b1f RD |
810 | err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, |
811 | cmpt_base + | |
812 | ((u64) (MLX4_CMPT_TYPE_EQ * | |
813 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
ab9c17a0 | 814 | cmpt_entry_sz, num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
815 | if (err) |
816 | goto err_cq; | |
817 | ||
818 | return 0; | |
819 | ||
820 | err_cq: | |
821 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
822 | ||
823 | err_srq: | |
824 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
825 | ||
826 | err_qp: | |
827 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
828 | ||
829 | err: | |
830 | return err; | |
831 | } | |
832 | ||
3d73c288 RD |
833 | static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, |
834 | struct mlx4_init_hca_param *init_hca, u64 icm_size) | |
225c7b1f RD |
835 | { |
836 | struct mlx4_priv *priv = mlx4_priv(dev); | |
837 | u64 aux_pages; | |
ab9c17a0 | 838 | int num_eqs; |
225c7b1f RD |
839 | int err; |
840 | ||
841 | err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); | |
842 | if (err) { | |
843 | mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n"); | |
844 | return err; | |
845 | } | |
846 | ||
847 | mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n", | |
848 | (unsigned long long) icm_size >> 10, | |
849 | (unsigned long long) aux_pages << 2); | |
850 | ||
851 | priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, | |
5b0bf5e2 | 852 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f RD |
853 | if (!priv->fw.aux_icm) { |
854 | mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n"); | |
855 | return -ENOMEM; | |
856 | } | |
857 | ||
858 | err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); | |
859 | if (err) { | |
860 | mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n"); | |
861 | goto err_free_aux; | |
862 | } | |
863 | ||
864 | err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); | |
865 | if (err) { | |
866 | mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n"); | |
867 | goto err_unmap_aux; | |
868 | } | |
869 | ||
ab9c17a0 | 870 | |
3fc929e2 MA |
871 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
872 | dev->caps.num_eqs; | |
fa0681d2 RD |
873 | err = mlx4_init_icm_table(dev, &priv->eq_table.table, |
874 | init_hca->eqc_base, dev_cap->eqc_entry_sz, | |
ab9c17a0 | 875 | num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
876 | if (err) { |
877 | mlx4_err(dev, "Failed to map EQ context memory, aborting.\n"); | |
878 | goto err_unmap_cmpt; | |
879 | } | |
880 | ||
d7bb58fb JM |
881 | /* |
882 | * Reserved MTT entries must be aligned up to a cacheline | |
883 | * boundary, since the FW will write to them, while the driver | |
884 | * writes to all other MTT entries. (The variable | |
885 | * dev->caps.mtt_entry_sz below is really the MTT segment | |
886 | * size, not the raw entry size) | |
887 | */ | |
888 | dev->caps.reserved_mtts = | |
889 | ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, | |
890 | dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; | |
891 | ||
225c7b1f RD |
892 | err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, |
893 | init_hca->mtt_base, | |
894 | dev->caps.mtt_entry_sz, | |
2b8fb286 | 895 | dev->caps.num_mtts, |
5b0bf5e2 | 896 | dev->caps.reserved_mtts, 1, 0); |
225c7b1f RD |
897 | if (err) { |
898 | mlx4_err(dev, "Failed to map MTT context memory, aborting.\n"); | |
899 | goto err_unmap_eq; | |
900 | } | |
901 | ||
902 | err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, | |
903 | init_hca->dmpt_base, | |
904 | dev_cap->dmpt_entry_sz, | |
905 | dev->caps.num_mpts, | |
5b0bf5e2 | 906 | dev->caps.reserved_mrws, 1, 1); |
225c7b1f RD |
907 | if (err) { |
908 | mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n"); | |
909 | goto err_unmap_mtt; | |
910 | } | |
911 | ||
912 | err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, | |
913 | init_hca->qpc_base, | |
914 | dev_cap->qpc_entry_sz, | |
915 | dev->caps.num_qps, | |
93fc9e1b YP |
916 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
917 | 0, 0); | |
225c7b1f RD |
918 | if (err) { |
919 | mlx4_err(dev, "Failed to map QP context memory, aborting.\n"); | |
920 | goto err_unmap_dmpt; | |
921 | } | |
922 | ||
923 | err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, | |
924 | init_hca->auxc_base, | |
925 | dev_cap->aux_entry_sz, | |
926 | dev->caps.num_qps, | |
93fc9e1b YP |
927 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
928 | 0, 0); | |
225c7b1f RD |
929 | if (err) { |
930 | mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n"); | |
931 | goto err_unmap_qp; | |
932 | } | |
933 | ||
934 | err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, | |
935 | init_hca->altc_base, | |
936 | dev_cap->altc_entry_sz, | |
937 | dev->caps.num_qps, | |
93fc9e1b YP |
938 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
939 | 0, 0); | |
225c7b1f RD |
940 | if (err) { |
941 | mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n"); | |
942 | goto err_unmap_auxc; | |
943 | } | |
944 | ||
945 | err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, | |
946 | init_hca->rdmarc_base, | |
947 | dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, | |
948 | dev->caps.num_qps, | |
93fc9e1b YP |
949 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
950 | 0, 0); | |
225c7b1f RD |
951 | if (err) { |
952 | mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); | |
953 | goto err_unmap_altc; | |
954 | } | |
955 | ||
956 | err = mlx4_init_icm_table(dev, &priv->cq_table.table, | |
957 | init_hca->cqc_base, | |
958 | dev_cap->cqc_entry_sz, | |
959 | dev->caps.num_cqs, | |
5b0bf5e2 | 960 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
961 | if (err) { |
962 | mlx4_err(dev, "Failed to map CQ context memory, aborting.\n"); | |
963 | goto err_unmap_rdmarc; | |
964 | } | |
965 | ||
966 | err = mlx4_init_icm_table(dev, &priv->srq_table.table, | |
967 | init_hca->srqc_base, | |
968 | dev_cap->srq_entry_sz, | |
969 | dev->caps.num_srqs, | |
5b0bf5e2 | 970 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
971 | if (err) { |
972 | mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n"); | |
973 | goto err_unmap_cq; | |
974 | } | |
975 | ||
976 | /* | |
977 | * It's not strictly required, but for simplicity just map the | |
978 | * whole multicast group table now. The table isn't very big | |
979 | * and it's a lot easier than trying to track ref counts. | |
980 | */ | |
981 | err = mlx4_init_icm_table(dev, &priv->mcg_table.table, | |
0ec2c0f8 EE |
982 | init_hca->mc_base, |
983 | mlx4_get_mgm_entry_size(dev), | |
225c7b1f RD |
984 | dev->caps.num_mgms + dev->caps.num_amgms, |
985 | dev->caps.num_mgms + dev->caps.num_amgms, | |
5b0bf5e2 | 986 | 0, 0); |
225c7b1f RD |
987 | if (err) { |
988 | mlx4_err(dev, "Failed to map MCG context memory, aborting.\n"); | |
989 | goto err_unmap_srq; | |
990 | } | |
991 | ||
992 | return 0; | |
993 | ||
994 | err_unmap_srq: | |
995 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
996 | ||
997 | err_unmap_cq: | |
998 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
999 | ||
1000 | err_unmap_rdmarc: | |
1001 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1002 | ||
1003 | err_unmap_altc: | |
1004 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1005 | ||
1006 | err_unmap_auxc: | |
1007 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1008 | ||
1009 | err_unmap_qp: | |
1010 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1011 | ||
1012 | err_unmap_dmpt: | |
1013 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1014 | ||
1015 | err_unmap_mtt: | |
1016 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
1017 | ||
1018 | err_unmap_eq: | |
fa0681d2 | 1019 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1020 | |
1021 | err_unmap_cmpt: | |
1022 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
1023 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1024 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1025 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1026 | ||
1027 | err_unmap_aux: | |
1028 | mlx4_UNMAP_ICM_AUX(dev); | |
1029 | ||
1030 | err_free_aux: | |
5b0bf5e2 | 1031 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1032 | |
1033 | return err; | |
1034 | } | |
1035 | ||
1036 | static void mlx4_free_icms(struct mlx4_dev *dev) | |
1037 | { | |
1038 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1039 | ||
1040 | mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); | |
1041 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1042 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1043 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1044 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1045 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1046 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1047 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1048 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
fa0681d2 | 1049 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1050 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); |
1051 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1052 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1053 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
225c7b1f RD |
1054 | |
1055 | mlx4_UNMAP_ICM_AUX(dev); | |
5b0bf5e2 | 1056 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1057 | } |
1058 | ||
ab9c17a0 JM |
1059 | static void mlx4_slave_exit(struct mlx4_dev *dev) |
1060 | { | |
1061 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1062 | ||
1063 | down(&priv->cmd.slave_sem); | |
1064 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) | |
1065 | mlx4_warn(dev, "Failed to close slave function.\n"); | |
1066 | up(&priv->cmd.slave_sem); | |
1067 | } | |
1068 | ||
c1b43dca EC |
1069 | static int map_bf_area(struct mlx4_dev *dev) |
1070 | { | |
1071 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1072 | resource_size_t bf_start; | |
1073 | resource_size_t bf_len; | |
1074 | int err = 0; | |
1075 | ||
3d747473 JM |
1076 | if (!dev->caps.bf_reg_size) |
1077 | return -ENXIO; | |
1078 | ||
ab9c17a0 JM |
1079 | bf_start = pci_resource_start(dev->pdev, 2) + |
1080 | (dev->caps.num_uars << PAGE_SHIFT); | |
1081 | bf_len = pci_resource_len(dev->pdev, 2) - | |
1082 | (dev->caps.num_uars << PAGE_SHIFT); | |
c1b43dca EC |
1083 | priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); |
1084 | if (!priv->bf_mapping) | |
1085 | err = -ENOMEM; | |
1086 | ||
1087 | return err; | |
1088 | } | |
1089 | ||
1090 | static void unmap_bf_area(struct mlx4_dev *dev) | |
1091 | { | |
1092 | if (mlx4_priv(dev)->bf_mapping) | |
1093 | io_mapping_free(mlx4_priv(dev)->bf_mapping); | |
1094 | } | |
1095 | ||
225c7b1f RD |
1096 | static void mlx4_close_hca(struct mlx4_dev *dev) |
1097 | { | |
c1b43dca | 1098 | unmap_bf_area(dev); |
ab9c17a0 JM |
1099 | if (mlx4_is_slave(dev)) |
1100 | mlx4_slave_exit(dev); | |
1101 | else { | |
1102 | mlx4_CLOSE_HCA(dev, 0); | |
1103 | mlx4_free_icms(dev); | |
1104 | mlx4_UNMAP_FA(dev); | |
1105 | mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); | |
1106 | } | |
1107 | } | |
1108 | ||
1109 | static int mlx4_init_slave(struct mlx4_dev *dev) | |
1110 | { | |
1111 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1112 | u64 dma = (u64) priv->mfunc.vhcr_dma; | |
1113 | int num_of_reset_retries = NUM_OF_RESET_RETRIES; | |
1114 | int ret_from_reset = 0; | |
1115 | u32 slave_read; | |
1116 | u32 cmd_channel_ver; | |
1117 | ||
1118 | down(&priv->cmd.slave_sem); | |
1119 | priv->cmd.max_cmds = 1; | |
1120 | mlx4_warn(dev, "Sending reset\n"); | |
1121 | ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, | |
1122 | MLX4_COMM_TIME); | |
1123 | /* if we are in the middle of flr the slave will try | |
1124 | * NUM_OF_RESET_RETRIES times before leaving.*/ | |
1125 | if (ret_from_reset) { | |
1126 | if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { | |
1127 | msleep(SLEEP_TIME_IN_RESET); | |
1128 | while (ret_from_reset && num_of_reset_retries) { | |
1129 | mlx4_warn(dev, "slave is currently in the" | |
1130 | "middle of FLR. retrying..." | |
1131 | "(try num:%d)\n", | |
1132 | (NUM_OF_RESET_RETRIES - | |
1133 | num_of_reset_retries + 1)); | |
1134 | ret_from_reset = | |
1135 | mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, | |
1136 | 0, MLX4_COMM_TIME); | |
1137 | num_of_reset_retries = num_of_reset_retries - 1; | |
1138 | } | |
1139 | } else | |
1140 | goto err; | |
1141 | } | |
1142 | ||
1143 | /* check the driver version - the slave I/F revision | |
1144 | * must match the master's */ | |
1145 | slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); | |
1146 | cmd_channel_ver = mlx4_comm_get_version(); | |
1147 | ||
1148 | if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != | |
1149 | MLX4_COMM_GET_IF_REV(slave_read)) { | |
1150 | mlx4_err(dev, "slave driver version is not supported" | |
1151 | " by the master\n"); | |
1152 | goto err; | |
1153 | } | |
1154 | ||
1155 | mlx4_warn(dev, "Sending vhcr0\n"); | |
1156 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, | |
1157 | MLX4_COMM_TIME)) | |
1158 | goto err; | |
1159 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, | |
1160 | MLX4_COMM_TIME)) | |
1161 | goto err; | |
1162 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, | |
1163 | MLX4_COMM_TIME)) | |
1164 | goto err; | |
1165 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) | |
1166 | goto err; | |
1167 | up(&priv->cmd.slave_sem); | |
1168 | return 0; | |
1169 | ||
1170 | err: | |
1171 | mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); | |
1172 | up(&priv->cmd.slave_sem); | |
1173 | return -EIO; | |
225c7b1f RD |
1174 | } |
1175 | ||
3d73c288 | 1176 | static int mlx4_init_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1177 | { |
1178 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1179 | struct mlx4_adapter adapter; | |
1180 | struct mlx4_dev_cap dev_cap; | |
2d928651 | 1181 | struct mlx4_mod_stat_cfg mlx4_cfg; |
225c7b1f RD |
1182 | struct mlx4_profile profile; |
1183 | struct mlx4_init_hca_param init_hca; | |
1184 | u64 icm_size; | |
1185 | int err; | |
1186 | ||
ab9c17a0 JM |
1187 | if (!mlx4_is_slave(dev)) { |
1188 | err = mlx4_QUERY_FW(dev); | |
1189 | if (err) { | |
1190 | if (err == -EACCES) | |
1191 | mlx4_info(dev, "non-primary physical function, skipping.\n"); | |
1192 | else | |
1193 | mlx4_err(dev, "QUERY_FW command failed, aborting.\n"); | |
1194 | goto unmap_bf; | |
1195 | } | |
225c7b1f | 1196 | |
ab9c17a0 JM |
1197 | err = mlx4_load_fw(dev); |
1198 | if (err) { | |
1199 | mlx4_err(dev, "Failed to start FW, aborting.\n"); | |
1200 | goto unmap_bf; | |
1201 | } | |
225c7b1f | 1202 | |
ab9c17a0 JM |
1203 | mlx4_cfg.log_pg_sz_m = 1; |
1204 | mlx4_cfg.log_pg_sz = 0; | |
1205 | err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); | |
1206 | if (err) | |
1207 | mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); | |
2d928651 | 1208 | |
ab9c17a0 JM |
1209 | err = mlx4_dev_cap(dev, &dev_cap); |
1210 | if (err) { | |
1211 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n"); | |
1212 | goto err_stop_fw; | |
1213 | } | |
225c7b1f | 1214 | |
ab9c17a0 | 1215 | profile = default_profile; |
225c7b1f | 1216 | |
ab9c17a0 JM |
1217 | icm_size = mlx4_make_profile(dev, &profile, &dev_cap, |
1218 | &init_hca); | |
1219 | if ((long long) icm_size < 0) { | |
1220 | err = icm_size; | |
1221 | goto err_stop_fw; | |
1222 | } | |
225c7b1f | 1223 | |
a5bbe892 EC |
1224 | dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; |
1225 | ||
ab9c17a0 JM |
1226 | init_hca.log_uar_sz = ilog2(dev->caps.num_uars); |
1227 | init_hca.uar_page_sz = PAGE_SHIFT - 12; | |
c1b43dca | 1228 | |
ab9c17a0 JM |
1229 | err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); |
1230 | if (err) | |
1231 | goto err_stop_fw; | |
225c7b1f | 1232 | |
ab9c17a0 JM |
1233 | err = mlx4_INIT_HCA(dev, &init_hca); |
1234 | if (err) { | |
1235 | mlx4_err(dev, "INIT_HCA command failed, aborting.\n"); | |
1236 | goto err_free_icm; | |
1237 | } | |
1238 | } else { | |
1239 | err = mlx4_init_slave(dev); | |
1240 | if (err) { | |
1241 | mlx4_err(dev, "Failed to initialize slave\n"); | |
1242 | goto unmap_bf; | |
1243 | } | |
225c7b1f | 1244 | |
ab9c17a0 JM |
1245 | err = mlx4_slave_cap(dev); |
1246 | if (err) { | |
1247 | mlx4_err(dev, "Failed to obtain slave caps\n"); | |
1248 | goto err_close; | |
1249 | } | |
225c7b1f RD |
1250 | } |
1251 | ||
ab9c17a0 JM |
1252 | if (map_bf_area(dev)) |
1253 | mlx4_dbg(dev, "Failed to map blue flame area\n"); | |
1254 | ||
1255 | /*Only the master set the ports, all the rest got it from it.*/ | |
1256 | if (!mlx4_is_slave(dev)) | |
1257 | mlx4_set_port_mask(dev); | |
1258 | ||
225c7b1f RD |
1259 | err = mlx4_QUERY_ADAPTER(dev, &adapter); |
1260 | if (err) { | |
1261 | mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n"); | |
1262 | goto err_close; | |
1263 | } | |
1264 | ||
1265 | priv->eq_table.inta_pin = adapter.inta_pin; | |
cd9281d8 | 1266 | memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); |
225c7b1f RD |
1267 | |
1268 | return 0; | |
1269 | ||
1270 | err_close: | |
ab9c17a0 | 1271 | mlx4_close_hca(dev); |
225c7b1f RD |
1272 | |
1273 | err_free_icm: | |
ab9c17a0 JM |
1274 | if (!mlx4_is_slave(dev)) |
1275 | mlx4_free_icms(dev); | |
225c7b1f RD |
1276 | |
1277 | err_stop_fw: | |
ab9c17a0 JM |
1278 | if (!mlx4_is_slave(dev)) { |
1279 | mlx4_UNMAP_FA(dev); | |
1280 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); | |
1281 | } | |
1282 | unmap_bf: | |
c1b43dca | 1283 | unmap_bf_area(dev); |
225c7b1f RD |
1284 | return err; |
1285 | } | |
1286 | ||
f2a3f6a3 OG |
1287 | static int mlx4_init_counters_table(struct mlx4_dev *dev) |
1288 | { | |
1289 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1290 | int nent; | |
1291 | ||
1292 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1293 | return -ENOENT; | |
1294 | ||
1295 | nent = dev->caps.max_counters; | |
1296 | return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); | |
1297 | } | |
1298 | ||
1299 | static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) | |
1300 | { | |
1301 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); | |
1302 | } | |
1303 | ||
ba062d52 | 1304 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) |
f2a3f6a3 OG |
1305 | { |
1306 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1307 | ||
1308 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1309 | return -ENOENT; | |
1310 | ||
1311 | *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); | |
1312 | if (*idx == -1) | |
1313 | return -ENOMEM; | |
1314 | ||
1315 | return 0; | |
1316 | } | |
ba062d52 JM |
1317 | |
1318 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) | |
1319 | { | |
1320 | u64 out_param; | |
1321 | int err; | |
1322 | ||
1323 | if (mlx4_is_mfunc(dev)) { | |
1324 | err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, | |
1325 | RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, | |
1326 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
1327 | if (!err) | |
1328 | *idx = get_param_l(&out_param); | |
1329 | ||
1330 | return err; | |
1331 | } | |
1332 | return __mlx4_counter_alloc(dev, idx); | |
1333 | } | |
f2a3f6a3 OG |
1334 | EXPORT_SYMBOL_GPL(mlx4_counter_alloc); |
1335 | ||
ba062d52 | 1336 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) |
f2a3f6a3 OG |
1337 | { |
1338 | mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx); | |
1339 | return; | |
1340 | } | |
ba062d52 JM |
1341 | |
1342 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) | |
1343 | { | |
1344 | u64 in_param; | |
1345 | ||
1346 | if (mlx4_is_mfunc(dev)) { | |
1347 | set_param_l(&in_param, idx); | |
1348 | mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, | |
1349 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
1350 | MLX4_CMD_WRAPPED); | |
1351 | return; | |
1352 | } | |
1353 | __mlx4_counter_free(dev, idx); | |
1354 | } | |
f2a3f6a3 OG |
1355 | EXPORT_SYMBOL_GPL(mlx4_counter_free); |
1356 | ||
3d73c288 | 1357 | static int mlx4_setup_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1358 | { |
1359 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1360 | int err; | |
7ff93f8b | 1361 | int port; |
9a5aa622 | 1362 | __be32 ib_port_default_caps; |
225c7b1f | 1363 | |
225c7b1f RD |
1364 | err = mlx4_init_uar_table(dev); |
1365 | if (err) { | |
1366 | mlx4_err(dev, "Failed to initialize " | |
1367 | "user access region table, aborting.\n"); | |
1368 | return err; | |
1369 | } | |
1370 | ||
1371 | err = mlx4_uar_alloc(dev, &priv->driver_uar); | |
1372 | if (err) { | |
1373 | mlx4_err(dev, "Failed to allocate driver access region, " | |
1374 | "aborting.\n"); | |
1375 | goto err_uar_table_free; | |
1376 | } | |
1377 | ||
4979d18f | 1378 | priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); |
225c7b1f RD |
1379 | if (!priv->kar) { |
1380 | mlx4_err(dev, "Couldn't map kernel access region, " | |
1381 | "aborting.\n"); | |
1382 | err = -ENOMEM; | |
1383 | goto err_uar_free; | |
1384 | } | |
1385 | ||
1386 | err = mlx4_init_pd_table(dev); | |
1387 | if (err) { | |
1388 | mlx4_err(dev, "Failed to initialize " | |
1389 | "protection domain table, aborting.\n"); | |
1390 | goto err_kar_unmap; | |
1391 | } | |
1392 | ||
012a8ff5 SH |
1393 | err = mlx4_init_xrcd_table(dev); |
1394 | if (err) { | |
1395 | mlx4_err(dev, "Failed to initialize " | |
1396 | "reliable connection domain table, aborting.\n"); | |
1397 | goto err_pd_table_free; | |
1398 | } | |
1399 | ||
225c7b1f RD |
1400 | err = mlx4_init_mr_table(dev); |
1401 | if (err) { | |
1402 | mlx4_err(dev, "Failed to initialize " | |
1403 | "memory region table, aborting.\n"); | |
012a8ff5 | 1404 | goto err_xrcd_table_free; |
225c7b1f RD |
1405 | } |
1406 | ||
225c7b1f RD |
1407 | err = mlx4_init_eq_table(dev); |
1408 | if (err) { | |
1409 | mlx4_err(dev, "Failed to initialize " | |
1410 | "event queue table, aborting.\n"); | |
ee49bd93 | 1411 | goto err_mr_table_free; |
225c7b1f RD |
1412 | } |
1413 | ||
1414 | err = mlx4_cmd_use_events(dev); | |
1415 | if (err) { | |
1416 | mlx4_err(dev, "Failed to switch to event-driven " | |
1417 | "firmware commands, aborting.\n"); | |
1418 | goto err_eq_table_free; | |
1419 | } | |
1420 | ||
1421 | err = mlx4_NOP(dev); | |
1422 | if (err) { | |
08fb1055 MT |
1423 | if (dev->flags & MLX4_FLAG_MSI_X) { |
1424 | mlx4_warn(dev, "NOP command failed to generate MSI-X " | |
1425 | "interrupt IRQ %d).\n", | |
b8dd786f | 1426 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
08fb1055 MT |
1427 | mlx4_warn(dev, "Trying again without MSI-X.\n"); |
1428 | } else { | |
1429 | mlx4_err(dev, "NOP command failed to generate interrupt " | |
1430 | "(IRQ %d), aborting.\n", | |
b8dd786f | 1431 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
225c7b1f | 1432 | mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
08fb1055 | 1433 | } |
225c7b1f RD |
1434 | |
1435 | goto err_cmd_poll; | |
1436 | } | |
1437 | ||
1438 | mlx4_dbg(dev, "NOP command IRQ test passed\n"); | |
1439 | ||
1440 | err = mlx4_init_cq_table(dev); | |
1441 | if (err) { | |
1442 | mlx4_err(dev, "Failed to initialize " | |
1443 | "completion queue table, aborting.\n"); | |
1444 | goto err_cmd_poll; | |
1445 | } | |
1446 | ||
1447 | err = mlx4_init_srq_table(dev); | |
1448 | if (err) { | |
1449 | mlx4_err(dev, "Failed to initialize " | |
1450 | "shared receive queue table, aborting.\n"); | |
1451 | goto err_cq_table_free; | |
1452 | } | |
1453 | ||
1454 | err = mlx4_init_qp_table(dev); | |
1455 | if (err) { | |
1456 | mlx4_err(dev, "Failed to initialize " | |
1457 | "queue pair table, aborting.\n"); | |
1458 | goto err_srq_table_free; | |
1459 | } | |
1460 | ||
ab9c17a0 JM |
1461 | if (!mlx4_is_slave(dev)) { |
1462 | err = mlx4_init_mcg_table(dev); | |
1463 | if (err) { | |
1464 | mlx4_err(dev, "Failed to initialize " | |
1465 | "multicast group table, aborting.\n"); | |
1466 | goto err_qp_table_free; | |
1467 | } | |
225c7b1f RD |
1468 | } |
1469 | ||
f2a3f6a3 OG |
1470 | err = mlx4_init_counters_table(dev); |
1471 | if (err && err != -ENOENT) { | |
1472 | mlx4_err(dev, "Failed to initialize counters table, aborting.\n"); | |
ab9c17a0 | 1473 | goto err_mcg_table_free; |
f2a3f6a3 OG |
1474 | } |
1475 | ||
ab9c17a0 JM |
1476 | if (!mlx4_is_slave(dev)) { |
1477 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
ab9c17a0 JM |
1478 | ib_port_default_caps = 0; |
1479 | err = mlx4_get_port_ib_caps(dev, port, | |
1480 | &ib_port_default_caps); | |
1481 | if (err) | |
1482 | mlx4_warn(dev, "failed to get port %d default " | |
1483 | "ib capabilities (%d). Continuing " | |
1484 | "with caps = 0\n", port, err); | |
1485 | dev->caps.ib_port_def_cap[port] = ib_port_default_caps; | |
1486 | ||
096335b3 OG |
1487 | if (mlx4_is_mfunc(dev)) |
1488 | dev->caps.port_ib_mtu[port] = IB_MTU_2048; | |
1489 | else | |
1490 | dev->caps.port_ib_mtu[port] = IB_MTU_4096; | |
97285b78 | 1491 | |
ab9c17a0 JM |
1492 | err = mlx4_SET_PORT(dev, port); |
1493 | if (err) { | |
1494 | mlx4_err(dev, "Failed to set port %d, aborting\n", | |
1495 | port); | |
1496 | goto err_counters_table_free; | |
1497 | } | |
7ff93f8b YP |
1498 | } |
1499 | } | |
1500 | ||
225c7b1f RD |
1501 | return 0; |
1502 | ||
f2a3f6a3 OG |
1503 | err_counters_table_free: |
1504 | mlx4_cleanup_counters_table(dev); | |
1505 | ||
ab9c17a0 JM |
1506 | err_mcg_table_free: |
1507 | mlx4_cleanup_mcg_table(dev); | |
1508 | ||
225c7b1f RD |
1509 | err_qp_table_free: |
1510 | mlx4_cleanup_qp_table(dev); | |
1511 | ||
1512 | err_srq_table_free: | |
1513 | mlx4_cleanup_srq_table(dev); | |
1514 | ||
1515 | err_cq_table_free: | |
1516 | mlx4_cleanup_cq_table(dev); | |
1517 | ||
1518 | err_cmd_poll: | |
1519 | mlx4_cmd_use_polling(dev); | |
1520 | ||
1521 | err_eq_table_free: | |
1522 | mlx4_cleanup_eq_table(dev); | |
1523 | ||
ee49bd93 | 1524 | err_mr_table_free: |
225c7b1f RD |
1525 | mlx4_cleanup_mr_table(dev); |
1526 | ||
012a8ff5 SH |
1527 | err_xrcd_table_free: |
1528 | mlx4_cleanup_xrcd_table(dev); | |
1529 | ||
225c7b1f RD |
1530 | err_pd_table_free: |
1531 | mlx4_cleanup_pd_table(dev); | |
1532 | ||
1533 | err_kar_unmap: | |
1534 | iounmap(priv->kar); | |
1535 | ||
1536 | err_uar_free: | |
1537 | mlx4_uar_free(dev, &priv->driver_uar); | |
1538 | ||
1539 | err_uar_table_free: | |
1540 | mlx4_cleanup_uar_table(dev); | |
1541 | return err; | |
1542 | } | |
1543 | ||
e8f9b2ed | 1544 | static void mlx4_enable_msi_x(struct mlx4_dev *dev) |
225c7b1f RD |
1545 | { |
1546 | struct mlx4_priv *priv = mlx4_priv(dev); | |
b8dd786f | 1547 | struct msix_entry *entries; |
0b7ca5a9 YP |
1548 | int nreq = min_t(int, dev->caps.num_ports * |
1549 | min_t(int, num_online_cpus() + 1, MAX_MSIX_P_PORT) | |
1550 | + MSIX_LEGACY_SZ, MAX_MSIX); | |
225c7b1f RD |
1551 | int err; |
1552 | int i; | |
1553 | ||
1554 | if (msi_x) { | |
ab9c17a0 JM |
1555 | /* In multifunction mode each function gets 2 msi-X vectors |
1556 | * one for data path completions anf the other for asynch events | |
1557 | * or command completions */ | |
1558 | if (mlx4_is_mfunc(dev)) { | |
1559 | nreq = 2; | |
1560 | } else { | |
1561 | nreq = min_t(int, dev->caps.num_eqs - | |
1562 | dev->caps.reserved_eqs, nreq); | |
1563 | } | |
1564 | ||
b8dd786f YP |
1565 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
1566 | if (!entries) | |
1567 | goto no_msi; | |
1568 | ||
1569 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
1570 | entries[i].entry = i; |
1571 | ||
b8dd786f YP |
1572 | retry: |
1573 | err = pci_enable_msix(dev->pdev, entries, nreq); | |
225c7b1f | 1574 | if (err) { |
b8dd786f YP |
1575 | /* Try again if at least 2 vectors are available */ |
1576 | if (err > 1) { | |
1577 | mlx4_info(dev, "Requested %d vectors, " | |
1578 | "but only %d MSI-X vectors available, " | |
1579 | "trying again\n", nreq, err); | |
1580 | nreq = err; | |
1581 | goto retry; | |
1582 | } | |
5bf0da7d | 1583 | kfree(entries); |
225c7b1f RD |
1584 | goto no_msi; |
1585 | } | |
1586 | ||
0b7ca5a9 YP |
1587 | if (nreq < |
1588 | MSIX_LEGACY_SZ + dev->caps.num_ports * MIN_MSIX_P_PORT) { | |
1589 | /*Working in legacy mode , all EQ's shared*/ | |
1590 | dev->caps.comp_pool = 0; | |
1591 | dev->caps.num_comp_vectors = nreq - 1; | |
1592 | } else { | |
1593 | dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; | |
1594 | dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; | |
1595 | } | |
b8dd786f | 1596 | for (i = 0; i < nreq; ++i) |
225c7b1f RD |
1597 | priv->eq_table.eq[i].irq = entries[i].vector; |
1598 | ||
1599 | dev->flags |= MLX4_FLAG_MSI_X; | |
b8dd786f YP |
1600 | |
1601 | kfree(entries); | |
225c7b1f RD |
1602 | return; |
1603 | } | |
1604 | ||
1605 | no_msi: | |
b8dd786f | 1606 | dev->caps.num_comp_vectors = 1; |
0b7ca5a9 | 1607 | dev->caps.comp_pool = 0; |
b8dd786f YP |
1608 | |
1609 | for (i = 0; i < 2; ++i) | |
225c7b1f RD |
1610 | priv->eq_table.eq[i].irq = dev->pdev->irq; |
1611 | } | |
1612 | ||
7ff93f8b | 1613 | static int mlx4_init_port_info(struct mlx4_dev *dev, int port) |
2a2336f8 YP |
1614 | { |
1615 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
7ff93f8b | 1616 | int err = 0; |
2a2336f8 YP |
1617 | |
1618 | info->dev = dev; | |
1619 | info->port = port; | |
ab9c17a0 JM |
1620 | if (!mlx4_is_slave(dev)) { |
1621 | INIT_RADIX_TREE(&info->mac_tree, GFP_KERNEL); | |
1622 | mlx4_init_mac_table(dev, &info->mac_table); | |
1623 | mlx4_init_vlan_table(dev, &info->vlan_table); | |
1624 | info->base_qpn = | |
1625 | dev->caps.reserved_qps_base[MLX4_QP_REGION_ETH_ADDR] + | |
06fa0a88 | 1626 | (port - 1) * (1 << log_num_mac); |
ab9c17a0 | 1627 | } |
7ff93f8b YP |
1628 | |
1629 | sprintf(info->dev_name, "mlx4_port%d", port); | |
1630 | info->port_attr.attr.name = info->dev_name; | |
ab9c17a0 JM |
1631 | if (mlx4_is_mfunc(dev)) |
1632 | info->port_attr.attr.mode = S_IRUGO; | |
1633 | else { | |
1634 | info->port_attr.attr.mode = S_IRUGO | S_IWUSR; | |
1635 | info->port_attr.store = set_port_type; | |
1636 | } | |
7ff93f8b | 1637 | info->port_attr.show = show_port_type; |
3691c964 | 1638 | sysfs_attr_init(&info->port_attr.attr); |
7ff93f8b YP |
1639 | |
1640 | err = device_create_file(&dev->pdev->dev, &info->port_attr); | |
1641 | if (err) { | |
1642 | mlx4_err(dev, "Failed to create file for port %d\n", port); | |
1643 | info->port = -1; | |
1644 | } | |
1645 | ||
096335b3 OG |
1646 | sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); |
1647 | info->port_mtu_attr.attr.name = info->dev_mtu_name; | |
1648 | if (mlx4_is_mfunc(dev)) | |
1649 | info->port_mtu_attr.attr.mode = S_IRUGO; | |
1650 | else { | |
1651 | info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; | |
1652 | info->port_mtu_attr.store = set_port_ib_mtu; | |
1653 | } | |
1654 | info->port_mtu_attr.show = show_port_ib_mtu; | |
1655 | sysfs_attr_init(&info->port_mtu_attr.attr); | |
1656 | ||
1657 | err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); | |
1658 | if (err) { | |
1659 | mlx4_err(dev, "Failed to create mtu file for port %d\n", port); | |
1660 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
1661 | info->port = -1; | |
1662 | } | |
1663 | ||
7ff93f8b YP |
1664 | return err; |
1665 | } | |
1666 | ||
1667 | static void mlx4_cleanup_port_info(struct mlx4_port_info *info) | |
1668 | { | |
1669 | if (info->port < 0) | |
1670 | return; | |
1671 | ||
1672 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
096335b3 | 1673 | device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); |
2a2336f8 YP |
1674 | } |
1675 | ||
b12d93d6 YP |
1676 | static int mlx4_init_steering(struct mlx4_dev *dev) |
1677 | { | |
1678 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1679 | int num_entries = dev->caps.num_ports; | |
1680 | int i, j; | |
1681 | ||
1682 | priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); | |
1683 | if (!priv->steer) | |
1684 | return -ENOMEM; | |
1685 | ||
45b51365 | 1686 | for (i = 0; i < num_entries; i++) |
b12d93d6 YP |
1687 | for (j = 0; j < MLX4_NUM_STEERS; j++) { |
1688 | INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); | |
1689 | INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); | |
1690 | } | |
b12d93d6 YP |
1691 | return 0; |
1692 | } | |
1693 | ||
1694 | static void mlx4_clear_steering(struct mlx4_dev *dev) | |
1695 | { | |
1696 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1697 | struct mlx4_steer_index *entry, *tmp_entry; | |
1698 | struct mlx4_promisc_qp *pqp, *tmp_pqp; | |
1699 | int num_entries = dev->caps.num_ports; | |
1700 | int i, j; | |
1701 | ||
1702 | for (i = 0; i < num_entries; i++) { | |
1703 | for (j = 0; j < MLX4_NUM_STEERS; j++) { | |
1704 | list_for_each_entry_safe(pqp, tmp_pqp, | |
1705 | &priv->steer[i].promisc_qps[j], | |
1706 | list) { | |
1707 | list_del(&pqp->list); | |
1708 | kfree(pqp); | |
1709 | } | |
1710 | list_for_each_entry_safe(entry, tmp_entry, | |
1711 | &priv->steer[i].steer_entries[j], | |
1712 | list) { | |
1713 | list_del(&entry->list); | |
1714 | list_for_each_entry_safe(pqp, tmp_pqp, | |
1715 | &entry->duplicates, | |
1716 | list) { | |
1717 | list_del(&pqp->list); | |
1718 | kfree(pqp); | |
1719 | } | |
1720 | kfree(entry); | |
1721 | } | |
1722 | } | |
1723 | } | |
1724 | kfree(priv->steer); | |
1725 | } | |
1726 | ||
ab9c17a0 JM |
1727 | static int extended_func_num(struct pci_dev *pdev) |
1728 | { | |
1729 | return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); | |
1730 | } | |
1731 | ||
1732 | #define MLX4_OWNER_BASE 0x8069c | |
1733 | #define MLX4_OWNER_SIZE 4 | |
1734 | ||
1735 | static int mlx4_get_ownership(struct mlx4_dev *dev) | |
1736 | { | |
1737 | void __iomem *owner; | |
1738 | u32 ret; | |
1739 | ||
1740 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, | |
1741 | MLX4_OWNER_SIZE); | |
1742 | if (!owner) { | |
1743 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
1744 | return -ENOMEM; | |
1745 | } | |
1746 | ||
1747 | ret = readl(owner); | |
1748 | iounmap(owner); | |
1749 | return (int) !!ret; | |
1750 | } | |
1751 | ||
1752 | static void mlx4_free_ownership(struct mlx4_dev *dev) | |
1753 | { | |
1754 | void __iomem *owner; | |
1755 | ||
1756 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, | |
1757 | MLX4_OWNER_SIZE); | |
1758 | if (!owner) { | |
1759 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
1760 | return; | |
1761 | } | |
1762 | writel(0, owner); | |
1763 | msleep(1000); | |
1764 | iounmap(owner); | |
1765 | } | |
1766 | ||
3d73c288 | 1767 | static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
225c7b1f | 1768 | { |
225c7b1f RD |
1769 | struct mlx4_priv *priv; |
1770 | struct mlx4_dev *dev; | |
1771 | int err; | |
2a2336f8 | 1772 | int port; |
225c7b1f | 1773 | |
0a645e80 | 1774 | pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); |
225c7b1f RD |
1775 | |
1776 | err = pci_enable_device(pdev); | |
1777 | if (err) { | |
1778 | dev_err(&pdev->dev, "Cannot enable PCI device, " | |
1779 | "aborting.\n"); | |
1780 | return err; | |
1781 | } | |
ab9c17a0 JM |
1782 | if (num_vfs > MLX4_MAX_NUM_VF) { |
1783 | printk(KERN_ERR "There are more VF's (%d) than allowed(%d)\n", | |
1784 | num_vfs, MLX4_MAX_NUM_VF); | |
1785 | return -EINVAL; | |
1786 | } | |
225c7b1f | 1787 | /* |
ab9c17a0 | 1788 | * Check for BARs. |
225c7b1f | 1789 | */ |
ab9c17a0 JM |
1790 | if (((id == NULL) || !(id->driver_data & MLX4_VF)) && |
1791 | !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
1792 | dev_err(&pdev->dev, "Missing DCS, aborting." | |
1793 | "(id == 0X%p, id->driver_data: 0x%lx," | |
1794 | " pci_resource_flags(pdev, 0):0x%lx)\n", id, | |
1795 | id ? id->driver_data : 0, pci_resource_flags(pdev, 0)); | |
225c7b1f RD |
1796 | err = -ENODEV; |
1797 | goto err_disable_pdev; | |
1798 | } | |
1799 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
1800 | dev_err(&pdev->dev, "Missing UAR, aborting.\n"); | |
1801 | err = -ENODEV; | |
1802 | goto err_disable_pdev; | |
1803 | } | |
1804 | ||
a01df0fe | 1805 | err = pci_request_regions(pdev, DRV_NAME); |
225c7b1f | 1806 | if (err) { |
a01df0fe | 1807 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); |
225c7b1f RD |
1808 | goto err_disable_pdev; |
1809 | } | |
1810 | ||
225c7b1f RD |
1811 | pci_set_master(pdev); |
1812 | ||
6a35528a | 1813 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f RD |
1814 | if (err) { |
1815 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); | |
284901a9 | 1816 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f RD |
1817 | if (err) { |
1818 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); | |
a01df0fe | 1819 | goto err_release_regions; |
225c7b1f RD |
1820 | } |
1821 | } | |
6a35528a | 1822 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f RD |
1823 | if (err) { |
1824 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " | |
1825 | "consistent PCI DMA mask.\n"); | |
284901a9 | 1826 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f RD |
1827 | if (err) { |
1828 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " | |
1829 | "aborting.\n"); | |
a01df0fe | 1830 | goto err_release_regions; |
225c7b1f RD |
1831 | } |
1832 | } | |
1833 | ||
7f9e5c48 DD |
1834 | /* Allow large DMA segments, up to the firmware limit of 1 GB */ |
1835 | dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); | |
1836 | ||
225c7b1f RD |
1837 | priv = kzalloc(sizeof *priv, GFP_KERNEL); |
1838 | if (!priv) { | |
1839 | dev_err(&pdev->dev, "Device struct alloc failed, " | |
1840 | "aborting.\n"); | |
1841 | err = -ENOMEM; | |
a01df0fe | 1842 | goto err_release_regions; |
225c7b1f RD |
1843 | } |
1844 | ||
1845 | dev = &priv->dev; | |
1846 | dev->pdev = pdev; | |
b581401e RD |
1847 | INIT_LIST_HEAD(&priv->ctx_list); |
1848 | spin_lock_init(&priv->ctx_lock); | |
225c7b1f | 1849 | |
7ff93f8b YP |
1850 | mutex_init(&priv->port_mutex); |
1851 | ||
6296883c YP |
1852 | INIT_LIST_HEAD(&priv->pgdir_list); |
1853 | mutex_init(&priv->pgdir_mutex); | |
1854 | ||
c1b43dca EC |
1855 | INIT_LIST_HEAD(&priv->bf_list); |
1856 | mutex_init(&priv->bf_mutex); | |
1857 | ||
aca7a3ac | 1858 | dev->rev_id = pdev->revision; |
ab9c17a0 JM |
1859 | /* Detect if this device is a virtual function */ |
1860 | if (id && id->driver_data & MLX4_VF) { | |
1861 | /* When acting as pf, we normally skip vfs unless explicitly | |
1862 | * requested to probe them. */ | |
1863 | if (num_vfs && extended_func_num(pdev) > probe_vf) { | |
1864 | mlx4_warn(dev, "Skipping virtual function:%d\n", | |
1865 | extended_func_num(pdev)); | |
1866 | err = -ENODEV; | |
1867 | goto err_free_dev; | |
1868 | } | |
1869 | mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); | |
1870 | dev->flags |= MLX4_FLAG_SLAVE; | |
1871 | } else { | |
1872 | /* We reset the device and enable SRIOV only for physical | |
1873 | * devices. Try to claim ownership on the device; | |
1874 | * if already taken, skip -- do not allow multiple PFs */ | |
1875 | err = mlx4_get_ownership(dev); | |
1876 | if (err) { | |
1877 | if (err < 0) | |
1878 | goto err_free_dev; | |
1879 | else { | |
1880 | mlx4_warn(dev, "Multiple PFs not yet supported." | |
1881 | " Skipping PF.\n"); | |
1882 | err = -EINVAL; | |
1883 | goto err_free_dev; | |
1884 | } | |
1885 | } | |
aca7a3ac | 1886 | |
ab9c17a0 JM |
1887 | if (num_vfs) { |
1888 | mlx4_warn(dev, "Enabling sriov with:%d vfs\n", num_vfs); | |
1889 | err = pci_enable_sriov(pdev, num_vfs); | |
1890 | if (err) { | |
1891 | mlx4_err(dev, "Failed to enable sriov," | |
1892 | "continuing without sriov enabled" | |
1893 | " (err = %d).\n", err); | |
ab9c17a0 JM |
1894 | err = 0; |
1895 | } else { | |
1896 | mlx4_warn(dev, "Running in master mode\n"); | |
1897 | dev->flags |= MLX4_FLAG_SRIOV | | |
1898 | MLX4_FLAG_MASTER; | |
1899 | dev->num_vfs = num_vfs; | |
1900 | } | |
1901 | } | |
1902 | ||
1903 | /* | |
1904 | * Now reset the HCA before we touch the PCI capabilities or | |
1905 | * attempt a firmware command, since a boot ROM may have left | |
1906 | * the HCA in an undefined state. | |
1907 | */ | |
1908 | err = mlx4_reset(dev); | |
1909 | if (err) { | |
1910 | mlx4_err(dev, "Failed to reset HCA, aborting.\n"); | |
1911 | goto err_rel_own; | |
1912 | } | |
225c7b1f RD |
1913 | } |
1914 | ||
ab9c17a0 | 1915 | slave_start: |
225c7b1f RD |
1916 | if (mlx4_cmd_init(dev)) { |
1917 | mlx4_err(dev, "Failed to init command interface, aborting.\n"); | |
ab9c17a0 JM |
1918 | goto err_sriov; |
1919 | } | |
1920 | ||
1921 | /* In slave functions, the communication channel must be initialized | |
1922 | * before posting commands. Also, init num_slaves before calling | |
1923 | * mlx4_init_hca */ | |
1924 | if (mlx4_is_mfunc(dev)) { | |
1925 | if (mlx4_is_master(dev)) | |
1926 | dev->num_slaves = MLX4_MAX_NUM_SLAVES; | |
1927 | else { | |
1928 | dev->num_slaves = 0; | |
1929 | if (mlx4_multi_func_init(dev)) { | |
1930 | mlx4_err(dev, "Failed to init slave mfunc" | |
1931 | " interface, aborting.\n"); | |
1932 | goto err_cmd; | |
1933 | } | |
1934 | } | |
225c7b1f RD |
1935 | } |
1936 | ||
1937 | err = mlx4_init_hca(dev); | |
ab9c17a0 JM |
1938 | if (err) { |
1939 | if (err == -EACCES) { | |
1940 | /* Not primary Physical function | |
1941 | * Running in slave mode */ | |
1942 | mlx4_cmd_cleanup(dev); | |
1943 | dev->flags |= MLX4_FLAG_SLAVE; | |
1944 | dev->flags &= ~MLX4_FLAG_MASTER; | |
1945 | goto slave_start; | |
1946 | } else | |
1947 | goto err_mfunc; | |
1948 | } | |
1949 | ||
1950 | /* In master functions, the communication channel must be initialized | |
1951 | * after obtaining its address from fw */ | |
1952 | if (mlx4_is_master(dev)) { | |
1953 | if (mlx4_multi_func_init(dev)) { | |
1954 | mlx4_err(dev, "Failed to init master mfunc" | |
1955 | "interface, aborting.\n"); | |
1956 | goto err_close; | |
1957 | } | |
1958 | } | |
225c7b1f | 1959 | |
b8dd786f YP |
1960 | err = mlx4_alloc_eq_table(dev); |
1961 | if (err) | |
ab9c17a0 | 1962 | goto err_master_mfunc; |
b8dd786f | 1963 | |
0b7ca5a9 | 1964 | priv->msix_ctl.pool_bm = 0; |
730c41d5 | 1965 | mutex_init(&priv->msix_ctl.pool_lock); |
0b7ca5a9 | 1966 | |
08fb1055 | 1967 | mlx4_enable_msi_x(dev); |
ab9c17a0 JM |
1968 | if ((mlx4_is_mfunc(dev)) && |
1969 | !(dev->flags & MLX4_FLAG_MSI_X)) { | |
1970 | mlx4_err(dev, "INTx is not supported in multi-function mode." | |
1971 | " aborting.\n"); | |
b12d93d6 | 1972 | goto err_free_eq; |
ab9c17a0 JM |
1973 | } |
1974 | ||
1975 | if (!mlx4_is_slave(dev)) { | |
1976 | err = mlx4_init_steering(dev); | |
1977 | if (err) | |
1978 | goto err_free_eq; | |
1979 | } | |
b12d93d6 | 1980 | |
225c7b1f | 1981 | err = mlx4_setup_hca(dev); |
ab9c17a0 JM |
1982 | if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && |
1983 | !mlx4_is_mfunc(dev)) { | |
08fb1055 MT |
1984 | dev->flags &= ~MLX4_FLAG_MSI_X; |
1985 | pci_disable_msix(pdev); | |
1986 | err = mlx4_setup_hca(dev); | |
1987 | } | |
1988 | ||
225c7b1f | 1989 | if (err) |
b12d93d6 | 1990 | goto err_steer; |
225c7b1f | 1991 | |
7ff93f8b YP |
1992 | for (port = 1; port <= dev->caps.num_ports; port++) { |
1993 | err = mlx4_init_port_info(dev, port); | |
1994 | if (err) | |
1995 | goto err_port; | |
1996 | } | |
2a2336f8 | 1997 | |
225c7b1f RD |
1998 | err = mlx4_register_device(dev); |
1999 | if (err) | |
7ff93f8b | 2000 | goto err_port; |
225c7b1f | 2001 | |
27bf91d6 YP |
2002 | mlx4_sense_init(dev); |
2003 | mlx4_start_sense(dev); | |
2004 | ||
225c7b1f RD |
2005 | pci_set_drvdata(pdev, dev); |
2006 | ||
2007 | return 0; | |
2008 | ||
7ff93f8b | 2009 | err_port: |
b4f77264 | 2010 | for (--port; port >= 1; --port) |
7ff93f8b YP |
2011 | mlx4_cleanup_port_info(&priv->port[port]); |
2012 | ||
f2a3f6a3 | 2013 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2014 | mlx4_cleanup_mcg_table(dev); |
2015 | mlx4_cleanup_qp_table(dev); | |
2016 | mlx4_cleanup_srq_table(dev); | |
2017 | mlx4_cleanup_cq_table(dev); | |
2018 | mlx4_cmd_use_polling(dev); | |
2019 | mlx4_cleanup_eq_table(dev); | |
225c7b1f | 2020 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2021 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2022 | mlx4_cleanup_pd_table(dev); |
2023 | mlx4_cleanup_uar_table(dev); | |
2024 | ||
b12d93d6 | 2025 | err_steer: |
ab9c17a0 JM |
2026 | if (!mlx4_is_slave(dev)) |
2027 | mlx4_clear_steering(dev); | |
b12d93d6 | 2028 | |
b8dd786f YP |
2029 | err_free_eq: |
2030 | mlx4_free_eq_table(dev); | |
2031 | ||
ab9c17a0 JM |
2032 | err_master_mfunc: |
2033 | if (mlx4_is_master(dev)) | |
2034 | mlx4_multi_func_cleanup(dev); | |
2035 | ||
225c7b1f | 2036 | err_close: |
08fb1055 MT |
2037 | if (dev->flags & MLX4_FLAG_MSI_X) |
2038 | pci_disable_msix(pdev); | |
2039 | ||
225c7b1f RD |
2040 | mlx4_close_hca(dev); |
2041 | ||
ab9c17a0 JM |
2042 | err_mfunc: |
2043 | if (mlx4_is_slave(dev)) | |
2044 | mlx4_multi_func_cleanup(dev); | |
2045 | ||
225c7b1f RD |
2046 | err_cmd: |
2047 | mlx4_cmd_cleanup(dev); | |
2048 | ||
ab9c17a0 | 2049 | err_sriov: |
681372a7 | 2050 | if (dev->flags & MLX4_FLAG_SRIOV) |
ab9c17a0 JM |
2051 | pci_disable_sriov(pdev); |
2052 | ||
2053 | err_rel_own: | |
2054 | if (!mlx4_is_slave(dev)) | |
2055 | mlx4_free_ownership(dev); | |
2056 | ||
225c7b1f | 2057 | err_free_dev: |
225c7b1f RD |
2058 | kfree(priv); |
2059 | ||
a01df0fe RD |
2060 | err_release_regions: |
2061 | pci_release_regions(pdev); | |
225c7b1f RD |
2062 | |
2063 | err_disable_pdev: | |
2064 | pci_disable_device(pdev); | |
2065 | pci_set_drvdata(pdev, NULL); | |
2066 | return err; | |
2067 | } | |
2068 | ||
3d73c288 RD |
2069 | static int __devinit mlx4_init_one(struct pci_dev *pdev, |
2070 | const struct pci_device_id *id) | |
2071 | { | |
0a645e80 | 2072 | printk_once(KERN_INFO "%s", mlx4_version); |
3d73c288 | 2073 | |
b027cacd | 2074 | return __mlx4_init_one(pdev, id); |
3d73c288 RD |
2075 | } |
2076 | ||
2077 | static void mlx4_remove_one(struct pci_dev *pdev) | |
225c7b1f RD |
2078 | { |
2079 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2080 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2081 | int p; | |
2082 | ||
2083 | if (dev) { | |
ab9c17a0 JM |
2084 | /* in SRIOV it is not allowed to unload the pf's |
2085 | * driver while there are alive vf's */ | |
2086 | if (mlx4_is_master(dev)) { | |
2087 | if (mlx4_how_many_lives_vf(dev)) | |
2088 | printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n"); | |
2089 | } | |
27bf91d6 | 2090 | mlx4_stop_sense(dev); |
225c7b1f RD |
2091 | mlx4_unregister_device(dev); |
2092 | ||
7ff93f8b YP |
2093 | for (p = 1; p <= dev->caps.num_ports; p++) { |
2094 | mlx4_cleanup_port_info(&priv->port[p]); | |
225c7b1f | 2095 | mlx4_CLOSE_PORT(dev, p); |
7ff93f8b | 2096 | } |
225c7b1f | 2097 | |
b8924951 JM |
2098 | if (mlx4_is_master(dev)) |
2099 | mlx4_free_resource_tracker(dev, | |
2100 | RES_TR_FREE_SLAVES_ONLY); | |
2101 | ||
f2a3f6a3 | 2102 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2103 | mlx4_cleanup_mcg_table(dev); |
2104 | mlx4_cleanup_qp_table(dev); | |
2105 | mlx4_cleanup_srq_table(dev); | |
2106 | mlx4_cleanup_cq_table(dev); | |
2107 | mlx4_cmd_use_polling(dev); | |
2108 | mlx4_cleanup_eq_table(dev); | |
225c7b1f | 2109 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2110 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2111 | mlx4_cleanup_pd_table(dev); |
2112 | ||
ab9c17a0 | 2113 | if (mlx4_is_master(dev)) |
b8924951 JM |
2114 | mlx4_free_resource_tracker(dev, |
2115 | RES_TR_FREE_STRUCTS_ONLY); | |
ab9c17a0 | 2116 | |
225c7b1f RD |
2117 | iounmap(priv->kar); |
2118 | mlx4_uar_free(dev, &priv->driver_uar); | |
2119 | mlx4_cleanup_uar_table(dev); | |
ab9c17a0 JM |
2120 | if (!mlx4_is_slave(dev)) |
2121 | mlx4_clear_steering(dev); | |
b8dd786f | 2122 | mlx4_free_eq_table(dev); |
ab9c17a0 JM |
2123 | if (mlx4_is_master(dev)) |
2124 | mlx4_multi_func_cleanup(dev); | |
225c7b1f | 2125 | mlx4_close_hca(dev); |
ab9c17a0 JM |
2126 | if (mlx4_is_slave(dev)) |
2127 | mlx4_multi_func_cleanup(dev); | |
225c7b1f RD |
2128 | mlx4_cmd_cleanup(dev); |
2129 | ||
2130 | if (dev->flags & MLX4_FLAG_MSI_X) | |
2131 | pci_disable_msix(pdev); | |
681372a7 | 2132 | if (dev->flags & MLX4_FLAG_SRIOV) { |
ab9c17a0 JM |
2133 | mlx4_warn(dev, "Disabling sriov\n"); |
2134 | pci_disable_sriov(pdev); | |
2135 | } | |
225c7b1f | 2136 | |
ab9c17a0 JM |
2137 | if (!mlx4_is_slave(dev)) |
2138 | mlx4_free_ownership(dev); | |
225c7b1f | 2139 | kfree(priv); |
a01df0fe | 2140 | pci_release_regions(pdev); |
225c7b1f RD |
2141 | pci_disable_device(pdev); |
2142 | pci_set_drvdata(pdev, NULL); | |
2143 | } | |
2144 | } | |
2145 | ||
ee49bd93 JM |
2146 | int mlx4_restart_one(struct pci_dev *pdev) |
2147 | { | |
2148 | mlx4_remove_one(pdev); | |
3d73c288 | 2149 | return __mlx4_init_one(pdev, NULL); |
ee49bd93 JM |
2150 | } |
2151 | ||
a3aa1884 | 2152 | static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { |
ab9c17a0 JM |
2153 | /* MT25408 "Hermon" SDR */ |
2154 | { PCI_VDEVICE(MELLANOX, 0x6340), 0 }, | |
2155 | /* MT25408 "Hermon" DDR */ | |
2156 | { PCI_VDEVICE(MELLANOX, 0x634a), 0 }, | |
2157 | /* MT25408 "Hermon" QDR */ | |
2158 | { PCI_VDEVICE(MELLANOX, 0x6354), 0 }, | |
2159 | /* MT25408 "Hermon" DDR PCIe gen2 */ | |
2160 | { PCI_VDEVICE(MELLANOX, 0x6732), 0 }, | |
2161 | /* MT25408 "Hermon" QDR PCIe gen2 */ | |
2162 | { PCI_VDEVICE(MELLANOX, 0x673c), 0 }, | |
2163 | /* MT25408 "Hermon" EN 10GigE */ | |
2164 | { PCI_VDEVICE(MELLANOX, 0x6368), 0 }, | |
2165 | /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ | |
2166 | { PCI_VDEVICE(MELLANOX, 0x6750), 0 }, | |
2167 | /* MT25458 ConnectX EN 10GBASE-T 10GigE */ | |
2168 | { PCI_VDEVICE(MELLANOX, 0x6372), 0 }, | |
2169 | /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ | |
2170 | { PCI_VDEVICE(MELLANOX, 0x675a), 0 }, | |
2171 | /* MT26468 ConnectX EN 10GigE PCIe gen2*/ | |
2172 | { PCI_VDEVICE(MELLANOX, 0x6764), 0 }, | |
2173 | /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ | |
2174 | { PCI_VDEVICE(MELLANOX, 0x6746), 0 }, | |
2175 | /* MT26478 ConnectX2 40GigE PCIe gen2 */ | |
2176 | { PCI_VDEVICE(MELLANOX, 0x676e), 0 }, | |
2177 | /* MT25400 Family [ConnectX-2 Virtual Function] */ | |
2178 | { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_VF }, | |
2179 | /* MT27500 Family [ConnectX-3] */ | |
2180 | { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, | |
2181 | /* MT27500 Family [ConnectX-3 Virtual Function] */ | |
2182 | { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_VF }, | |
2183 | { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ | |
2184 | { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ | |
2185 | { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ | |
2186 | { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ | |
2187 | { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ | |
2188 | { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ | |
2189 | { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ | |
2190 | { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ | |
2191 | { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ | |
2192 | { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ | |
2193 | { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ | |
2194 | { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ | |
225c7b1f RD |
2195 | { 0, } |
2196 | }; | |
2197 | ||
2198 | MODULE_DEVICE_TABLE(pci, mlx4_pci_table); | |
2199 | ||
2200 | static struct pci_driver mlx4_driver = { | |
2201 | .name = DRV_NAME, | |
2202 | .id_table = mlx4_pci_table, | |
2203 | .probe = mlx4_init_one, | |
2204 | .remove = __devexit_p(mlx4_remove_one) | |
2205 | }; | |
2206 | ||
7ff93f8b YP |
2207 | static int __init mlx4_verify_params(void) |
2208 | { | |
2209 | if ((log_num_mac < 0) || (log_num_mac > 7)) { | |
0a645e80 | 2210 | pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); |
7ff93f8b YP |
2211 | return -1; |
2212 | } | |
2213 | ||
cb29688a OG |
2214 | if (log_num_vlan != 0) |
2215 | pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", | |
2216 | MLX4_LOG_NUM_VLANS); | |
7ff93f8b | 2217 | |
0498628f | 2218 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { |
0a645e80 | 2219 | pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); |
ab6bf42e EC |
2220 | return -1; |
2221 | } | |
2222 | ||
ab9c17a0 JM |
2223 | /* Check if module param for ports type has legal combination */ |
2224 | if (port_type_array[0] == false && port_type_array[1] == true) { | |
2225 | printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); | |
2226 | port_type_array[0] = true; | |
2227 | } | |
2228 | ||
7ff93f8b YP |
2229 | return 0; |
2230 | } | |
2231 | ||
225c7b1f RD |
2232 | static int __init mlx4_init(void) |
2233 | { | |
2234 | int ret; | |
2235 | ||
7ff93f8b YP |
2236 | if (mlx4_verify_params()) |
2237 | return -EINVAL; | |
2238 | ||
27bf91d6 YP |
2239 | mlx4_catas_init(); |
2240 | ||
2241 | mlx4_wq = create_singlethread_workqueue("mlx4"); | |
2242 | if (!mlx4_wq) | |
2243 | return -ENOMEM; | |
ee49bd93 | 2244 | |
225c7b1f RD |
2245 | ret = pci_register_driver(&mlx4_driver); |
2246 | return ret < 0 ? ret : 0; | |
2247 | } | |
2248 | ||
2249 | static void __exit mlx4_cleanup(void) | |
2250 | { | |
2251 | pci_unregister_driver(&mlx4_driver); | |
27bf91d6 | 2252 | destroy_workqueue(mlx4_wq); |
225c7b1f RD |
2253 | } |
2254 | ||
2255 | module_init(mlx4_init); | |
2256 | module_exit(mlx4_cleanup); |