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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
51a379d0 | 4 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
5 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. |
6 | * | |
7 | * This software is available to you under a choice of one of two | |
8 | * licenses. You may choose to be licensed under the terms of the GNU | |
9 | * General Public License (GPL) Version 2, available from the file | |
10 | * COPYING in the main directory of this source tree, or the | |
11 | * OpenIB.org BSD license below: | |
12 | * | |
13 | * Redistribution and use in source and binary forms, with or | |
14 | * without modification, are permitted provided that the following | |
15 | * conditions are met: | |
16 | * | |
17 | * - Redistributions of source code must retain the above | |
18 | * copyright notice, this list of conditions and the following | |
19 | * disclaimer. | |
20 | * | |
21 | * - Redistributions in binary form must reproduce the above | |
22 | * copyright notice, this list of conditions and the following | |
23 | * disclaimer in the documentation and/or other materials | |
24 | * provided with the distribution. | |
25 | * | |
26 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
27 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
28 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
29 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
30 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
31 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
32 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
33 | * SOFTWARE. | |
34 | */ | |
35 | ||
36 | #include <linux/module.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/errno.h> | |
39 | #include <linux/pci.h> | |
40 | #include <linux/dma-mapping.h> | |
5a0e3ad6 | 41 | #include <linux/slab.h> |
c1b43dca | 42 | #include <linux/io-mapping.h> |
ab9c17a0 | 43 | #include <linux/delay.h> |
b046ffe5 | 44 | #include <linux/kmod.h> |
225c7b1f RD |
45 | |
46 | #include <linux/mlx4/device.h> | |
47 | #include <linux/mlx4/doorbell.h> | |
48 | ||
49 | #include "mlx4.h" | |
50 | #include "fw.h" | |
51 | #include "icm.h" | |
52 | ||
53 | MODULE_AUTHOR("Roland Dreier"); | |
54 | MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver"); | |
55 | MODULE_LICENSE("Dual BSD/GPL"); | |
56 | MODULE_VERSION(DRV_VERSION); | |
57 | ||
27bf91d6 YP |
58 | struct workqueue_struct *mlx4_wq; |
59 | ||
225c7b1f RD |
60 | #ifdef CONFIG_MLX4_DEBUG |
61 | ||
62 | int mlx4_debug_level = 0; | |
63 | module_param_named(debug_level, mlx4_debug_level, int, 0644); | |
64 | MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0"); | |
65 | ||
66 | #endif /* CONFIG_MLX4_DEBUG */ | |
67 | ||
68 | #ifdef CONFIG_PCI_MSI | |
69 | ||
08fb1055 | 70 | static int msi_x = 1; |
225c7b1f RD |
71 | module_param(msi_x, int, 0444); |
72 | MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero"); | |
73 | ||
74 | #else /* CONFIG_PCI_MSI */ | |
75 | ||
76 | #define msi_x (0) | |
77 | ||
78 | #endif /* CONFIG_PCI_MSI */ | |
79 | ||
dd41cc3b MB |
80 | static uint8_t num_vfs[3] = {0, 0, 0}; |
81 | static int num_vfs_argc = 3; | |
82 | module_param_array(num_vfs, byte , &num_vfs_argc, 0444); | |
83 | MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n" | |
84 | "num_vfs=port1,port2,port1+2"); | |
85 | ||
86 | static uint8_t probe_vf[3] = {0, 0, 0}; | |
87 | static int probe_vfs_argc = 3; | |
88 | module_param_array(probe_vf, byte, &probe_vfs_argc, 0444); | |
89 | MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n" | |
90 | "probe_vf=port1,port2,port1+2"); | |
ab9c17a0 | 91 | |
3c439b55 | 92 | int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; |
0ec2c0f8 EE |
93 | module_param_named(log_num_mgm_entry_size, |
94 | mlx4_log_num_mgm_entry_size, int, 0444); | |
95 | MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num" | |
96 | " of qp per mcg, for example:" | |
3c439b55 | 97 | " 10 gives 248.range: 7 <=" |
0ff1fb65 | 98 | " log_num_mgm_entry_size <= 12." |
3c439b55 JM |
99 | " To activate device managed" |
100 | " flow steering when available, set to -1"); | |
0ec2c0f8 | 101 | |
be902ab1 | 102 | static bool enable_64b_cqe_eqe = true; |
08ff3235 OG |
103 | module_param(enable_64b_cqe_eqe, bool, 0444); |
104 | MODULE_PARM_DESC(enable_64b_cqe_eqe, | |
be902ab1 | 105 | "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)"); |
08ff3235 | 106 | |
ab9c17a0 | 107 | #define HCA_GLOBAL_CAP_MASK 0 |
08ff3235 OG |
108 | |
109 | #define PF_CONTEXT_BEHAVIOUR_MASK MLX4_FUNC_CAP_64B_EQE_CQE | |
ab9c17a0 | 110 | |
f57e6848 | 111 | static char mlx4_version[] = |
225c7b1f RD |
112 | DRV_NAME ": Mellanox ConnectX core driver v" |
113 | DRV_VERSION " (" DRV_RELDATE ")\n"; | |
114 | ||
115 | static struct mlx4_profile default_profile = { | |
ab9c17a0 | 116 | .num_qp = 1 << 18, |
225c7b1f | 117 | .num_srq = 1 << 16, |
c9f2ba5e | 118 | .rdmarc_per_qp = 1 << 4, |
225c7b1f RD |
119 | .num_cq = 1 << 16, |
120 | .num_mcg = 1 << 13, | |
ab9c17a0 | 121 | .num_mpt = 1 << 19, |
9fd7a1e1 | 122 | .num_mtt = 1 << 20, /* It is really num mtt segements */ |
225c7b1f RD |
123 | }; |
124 | ||
ab9c17a0 | 125 | static int log_num_mac = 7; |
93fc9e1b YP |
126 | module_param_named(log_num_mac, log_num_mac, int, 0444); |
127 | MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)"); | |
128 | ||
129 | static int log_num_vlan; | |
130 | module_param_named(log_num_vlan, log_num_vlan, int, 0444); | |
131 | MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)"); | |
cb29688a OG |
132 | /* Log2 max number of VLANs per ETH port (0-7) */ |
133 | #define MLX4_LOG_NUM_VLANS 7 | |
93fc9e1b | 134 | |
eb939922 | 135 | static bool use_prio; |
93fc9e1b YP |
136 | module_param_named(use_prio, use_prio, bool, 0444); |
137 | MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports " | |
138 | "(0/1, default 0)"); | |
139 | ||
2b8fb286 | 140 | int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG); |
ab6bf42e | 141 | module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); |
0498628f | 142 | MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)"); |
ab6bf42e | 143 | |
8d0fc7b6 | 144 | static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE}; |
ab9c17a0 JM |
145 | static int arr_argc = 2; |
146 | module_param_array(port_type_array, int, &arr_argc, 0444); | |
8d0fc7b6 YP |
147 | MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default " |
148 | "1 for IB, 2 for Ethernet"); | |
ab9c17a0 JM |
149 | |
150 | struct mlx4_port_config { | |
151 | struct list_head list; | |
152 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; | |
153 | struct pci_dev *pdev; | |
154 | }; | |
155 | ||
97989356 AV |
156 | static atomic_t pf_loading = ATOMIC_INIT(0); |
157 | ||
27bf91d6 YP |
158 | int mlx4_check_port_params(struct mlx4_dev *dev, |
159 | enum mlx4_port_type *port_type) | |
7ff93f8b YP |
160 | { |
161 | int i; | |
162 | ||
163 | for (i = 0; i < dev->caps.num_ports - 1; i++) { | |
27bf91d6 YP |
164 | if (port_type[i] != port_type[i + 1]) { |
165 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) { | |
1a91de28 | 166 | mlx4_err(dev, "Only same port types supported on this HCA, aborting\n"); |
27bf91d6 YP |
167 | return -EINVAL; |
168 | } | |
7ff93f8b YP |
169 | } |
170 | } | |
7ff93f8b YP |
171 | |
172 | for (i = 0; i < dev->caps.num_ports; i++) { | |
173 | if (!(port_type[i] & dev->caps.supported_type[i+1])) { | |
1a91de28 JP |
174 | mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n", |
175 | i + 1); | |
7ff93f8b YP |
176 | return -EINVAL; |
177 | } | |
178 | } | |
179 | return 0; | |
180 | } | |
181 | ||
182 | static void mlx4_set_port_mask(struct mlx4_dev *dev) | |
183 | { | |
184 | int i; | |
185 | ||
7ff93f8b | 186 | for (i = 1; i <= dev->caps.num_ports; ++i) |
65dab25d | 187 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
7ff93f8b | 188 | } |
f2a3f6a3 | 189 | |
3d73c288 | 190 | static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
225c7b1f RD |
191 | { |
192 | int err; | |
5ae2a7a8 | 193 | int i; |
225c7b1f RD |
194 | |
195 | err = mlx4_QUERY_DEV_CAP(dev, dev_cap); | |
196 | if (err) { | |
1a91de28 | 197 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
225c7b1f RD |
198 | return err; |
199 | } | |
200 | ||
201 | if (dev_cap->min_page_sz > PAGE_SIZE) { | |
1a91de28 | 202 | mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", |
225c7b1f RD |
203 | dev_cap->min_page_sz, PAGE_SIZE); |
204 | return -ENODEV; | |
205 | } | |
206 | if (dev_cap->num_ports > MLX4_MAX_PORTS) { | |
1a91de28 | 207 | mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", |
225c7b1f RD |
208 | dev_cap->num_ports, MLX4_MAX_PORTS); |
209 | return -ENODEV; | |
210 | } | |
211 | ||
212 | if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) { | |
1a91de28 | 213 | mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", |
225c7b1f RD |
214 | dev_cap->uar_size, |
215 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
216 | return -ENODEV; | |
217 | } | |
218 | ||
219 | dev->caps.num_ports = dev_cap->num_ports; | |
3fc929e2 | 220 | dev->phys_caps.num_phys_eqs = MLX4_MAX_EQ_NUM; |
5ae2a7a8 RD |
221 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
222 | dev->caps.vl_cap[i] = dev_cap->max_vl[i]; | |
b79acb49 | 223 | dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i]; |
6634961c JM |
224 | dev->phys_caps.gid_phys_table_len[i] = dev_cap->max_gids[i]; |
225 | dev->phys_caps.pkey_phys_table_len[i] = dev_cap->max_pkeys[i]; | |
226 | /* set gid and pkey table operating lengths by default | |
227 | * to non-sriov values */ | |
5ae2a7a8 RD |
228 | dev->caps.gid_table_len[i] = dev_cap->max_gids[i]; |
229 | dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i]; | |
230 | dev->caps.port_width_cap[i] = dev_cap->max_port_width[i]; | |
b79acb49 YP |
231 | dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i]; |
232 | dev->caps.def_mac[i] = dev_cap->def_mac[i]; | |
7ff93f8b | 233 | dev->caps.supported_type[i] = dev_cap->supported_port_types[i]; |
8d0fc7b6 YP |
234 | dev->caps.suggested_type[i] = dev_cap->suggested_type[i]; |
235 | dev->caps.default_sense[i] = dev_cap->default_sense[i]; | |
7699517d YP |
236 | dev->caps.trans_type[i] = dev_cap->trans_type[i]; |
237 | dev->caps.vendor_oui[i] = dev_cap->vendor_oui[i]; | |
238 | dev->caps.wavelength[i] = dev_cap->wavelength[i]; | |
239 | dev->caps.trans_code[i] = dev_cap->trans_code[i]; | |
5ae2a7a8 RD |
240 | } |
241 | ||
ab9c17a0 | 242 | dev->caps.uar_page_size = PAGE_SIZE; |
225c7b1f | 243 | dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE; |
225c7b1f RD |
244 | dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay; |
245 | dev->caps.bf_reg_size = dev_cap->bf_reg_size; | |
246 | dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page; | |
247 | dev->caps.max_sq_sg = dev_cap->max_sq_sg; | |
248 | dev->caps.max_rq_sg = dev_cap->max_rq_sg; | |
249 | dev->caps.max_wqes = dev_cap->max_qp_sz; | |
250 | dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp; | |
225c7b1f RD |
251 | dev->caps.max_srq_wqes = dev_cap->max_srq_sz; |
252 | dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1; | |
253 | dev->caps.reserved_srqs = dev_cap->reserved_srqs; | |
254 | dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz; | |
255 | dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz; | |
225c7b1f RD |
256 | /* |
257 | * Subtract 1 from the limit because we need to allocate a | |
258 | * spare CQE so the HCA HW can tell the difference between an | |
259 | * empty CQ and a full CQ. | |
260 | */ | |
261 | dev->caps.max_cqes = dev_cap->max_cq_sz - 1; | |
262 | dev->caps.reserved_cqs = dev_cap->reserved_cqs; | |
263 | dev->caps.reserved_eqs = dev_cap->reserved_eqs; | |
2b8fb286 | 264 | dev->caps.reserved_mtts = dev_cap->reserved_mtts; |
225c7b1f | 265 | dev->caps.reserved_mrws = dev_cap->reserved_mrws; |
ab9c17a0 JM |
266 | |
267 | /* The first 128 UARs are used for EQ doorbells */ | |
268 | dev->caps.reserved_uars = max_t(int, 128, dev_cap->reserved_uars); | |
225c7b1f | 269 | dev->caps.reserved_pds = dev_cap->reserved_pds; |
012a8ff5 SH |
270 | dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? |
271 | dev_cap->reserved_xrcds : 0; | |
272 | dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ? | |
273 | dev_cap->max_xrcds : 0; | |
2b8fb286 MA |
274 | dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz; |
275 | ||
149983af | 276 | dev->caps.max_msg_sz = dev_cap->max_msg_sz; |
225c7b1f RD |
277 | dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1); |
278 | dev->caps.flags = dev_cap->flags; | |
b3416f44 | 279 | dev->caps.flags2 = dev_cap->flags2; |
95d04f07 RD |
280 | dev->caps.bmme_flags = dev_cap->bmme_flags; |
281 | dev->caps.reserved_lkey = dev_cap->reserved_lkey; | |
225c7b1f | 282 | dev->caps.stat_rate_support = dev_cap->stat_rate_support; |
b832be1e | 283 | dev->caps.max_gso_sz = dev_cap->max_gso_sz; |
b3416f44 | 284 | dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz; |
225c7b1f | 285 | |
ca3e57a5 RD |
286 | /* Sense port always allowed on supported devices for ConnectX-1 and -2 */ |
287 | if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT) | |
58a60168 | 288 | dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; |
aadf4f3f RD |
289 | /* Don't do sense port on multifunction devices (for now at least) */ |
290 | if (mlx4_is_mfunc(dev)) | |
291 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT; | |
58a60168 | 292 | |
93fc9e1b | 293 | dev->caps.log_num_macs = log_num_mac; |
cb29688a | 294 | dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS; |
93fc9e1b YP |
295 | dev->caps.log_num_prios = use_prio ? 3 : 0; |
296 | ||
297 | for (i = 1; i <= dev->caps.num_ports; ++i) { | |
ab9c17a0 JM |
298 | dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE; |
299 | if (dev->caps.supported_type[i]) { | |
300 | /* if only ETH is supported - assign ETH */ | |
301 | if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH) | |
302 | dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH; | |
105c320f | 303 | /* if only IB is supported, assign IB */ |
ab9c17a0 | 304 | else if (dev->caps.supported_type[i] == |
105c320f JM |
305 | MLX4_PORT_TYPE_IB) |
306 | dev->caps.port_type[i] = MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 307 | else { |
105c320f JM |
308 | /* if IB and ETH are supported, we set the port |
309 | * type according to user selection of port type; | |
310 | * if user selected none, take the FW hint */ | |
311 | if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE) | |
8d0fc7b6 YP |
312 | dev->caps.port_type[i] = dev->caps.suggested_type[i] ? |
313 | MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB; | |
ab9c17a0 | 314 | else |
105c320f | 315 | dev->caps.port_type[i] = port_type_array[i - 1]; |
ab9c17a0 JM |
316 | } |
317 | } | |
8d0fc7b6 YP |
318 | /* |
319 | * Link sensing is allowed on the port if 3 conditions are true: | |
320 | * 1. Both protocols are supported on the port. | |
321 | * 2. Different types are supported on the port | |
322 | * 3. FW declared that it supports link sensing | |
323 | */ | |
27bf91d6 | 324 | mlx4_priv(dev)->sense.sense_allowed[i] = |
58a60168 | 325 | ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) && |
8d0fc7b6 | 326 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
58a60168 | 327 | (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)); |
7ff93f8b | 328 | |
8d0fc7b6 YP |
329 | /* |
330 | * If "default_sense" bit is set, we move the port to "AUTO" mode | |
331 | * and perform sense_port FW command to try and set the correct | |
332 | * port type from beginning | |
333 | */ | |
46c46747 | 334 | if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) { |
8d0fc7b6 YP |
335 | enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE; |
336 | dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO; | |
337 | mlx4_SENSE_PORT(dev, i, &sensed_port); | |
338 | if (sensed_port != MLX4_PORT_TYPE_NONE) | |
339 | dev->caps.port_type[i] = sensed_port; | |
340 | } else { | |
341 | dev->caps.possible_type[i] = dev->caps.port_type[i]; | |
342 | } | |
343 | ||
93fc9e1b YP |
344 | if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) { |
345 | dev->caps.log_num_macs = dev_cap->log_max_macs[i]; | |
1a91de28 | 346 | mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n", |
93fc9e1b YP |
347 | i, 1 << dev->caps.log_num_macs); |
348 | } | |
349 | if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) { | |
350 | dev->caps.log_num_vlans = dev_cap->log_max_vlans[i]; | |
1a91de28 | 351 | mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n", |
93fc9e1b YP |
352 | i, 1 << dev->caps.log_num_vlans); |
353 | } | |
354 | } | |
355 | ||
f2a3f6a3 OG |
356 | dev->caps.max_counters = 1 << ilog2(dev_cap->max_counters); |
357 | ||
93fc9e1b YP |
358 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps; |
359 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] = | |
360 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] = | |
361 | (1 << dev->caps.log_num_macs) * | |
362 | (1 << dev->caps.log_num_vlans) * | |
363 | (1 << dev->caps.log_num_prios) * | |
364 | dev->caps.num_ports; | |
365 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH; | |
366 | ||
367 | dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] + | |
368 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] + | |
369 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] + | |
370 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH]; | |
371 | ||
e2c76824 | 372 | dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0; |
08ff3235 | 373 | |
b3051320 | 374 | if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) { |
08ff3235 OG |
375 | if (dev_cap->flags & |
376 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) { | |
377 | mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n"); | |
378 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE; | |
379 | dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE; | |
380 | } | |
381 | } | |
382 | ||
f97b4b5d | 383 | if ((dev->caps.flags & |
08ff3235 OG |
384 | (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) && |
385 | mlx4_is_master(dev)) | |
386 | dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE; | |
387 | ||
225c7b1f RD |
388 | return 0; |
389 | } | |
b912b2f8 EP |
390 | |
391 | static int mlx4_get_pcie_dev_link_caps(struct mlx4_dev *dev, | |
392 | enum pci_bus_speed *speed, | |
393 | enum pcie_link_width *width) | |
394 | { | |
395 | u32 lnkcap1, lnkcap2; | |
396 | int err1, err2; | |
397 | ||
398 | #define PCIE_MLW_CAP_SHIFT 4 /* start of MLW mask in link capabilities */ | |
399 | ||
400 | *speed = PCI_SPEED_UNKNOWN; | |
401 | *width = PCIE_LNK_WIDTH_UNKNOWN; | |
402 | ||
403 | err1 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP, &lnkcap1); | |
404 | err2 = pcie_capability_read_dword(dev->pdev, PCI_EXP_LNKCAP2, &lnkcap2); | |
405 | if (!err2 && lnkcap2) { /* PCIe r3.0-compliant */ | |
406 | if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) | |
407 | *speed = PCIE_SPEED_8_0GT; | |
408 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) | |
409 | *speed = PCIE_SPEED_5_0GT; | |
410 | else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) | |
411 | *speed = PCIE_SPEED_2_5GT; | |
412 | } | |
413 | if (!err1) { | |
414 | *width = (lnkcap1 & PCI_EXP_LNKCAP_MLW) >> PCIE_MLW_CAP_SHIFT; | |
415 | if (!lnkcap2) { /* pre-r3.0 */ | |
416 | if (lnkcap1 & PCI_EXP_LNKCAP_SLS_5_0GB) | |
417 | *speed = PCIE_SPEED_5_0GT; | |
418 | else if (lnkcap1 & PCI_EXP_LNKCAP_SLS_2_5GB) | |
419 | *speed = PCIE_SPEED_2_5GT; | |
420 | } | |
421 | } | |
422 | ||
423 | if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN) { | |
424 | return err1 ? err1 : | |
425 | err2 ? err2 : -EINVAL; | |
426 | } | |
427 | return 0; | |
428 | } | |
429 | ||
430 | static void mlx4_check_pcie_caps(struct mlx4_dev *dev) | |
431 | { | |
432 | enum pcie_link_width width, width_cap; | |
433 | enum pci_bus_speed speed, speed_cap; | |
434 | int err; | |
435 | ||
436 | #define PCIE_SPEED_STR(speed) \ | |
437 | (speed == PCIE_SPEED_8_0GT ? "8.0GT/s" : \ | |
438 | speed == PCIE_SPEED_5_0GT ? "5.0GT/s" : \ | |
439 | speed == PCIE_SPEED_2_5GT ? "2.5GT/s" : \ | |
440 | "Unknown") | |
441 | ||
442 | err = mlx4_get_pcie_dev_link_caps(dev, &speed_cap, &width_cap); | |
443 | if (err) { | |
444 | mlx4_warn(dev, | |
445 | "Unable to determine PCIe device BW capabilities\n"); | |
446 | return; | |
447 | } | |
448 | ||
449 | err = pcie_get_minimum_link(dev->pdev, &speed, &width); | |
450 | if (err || speed == PCI_SPEED_UNKNOWN || | |
451 | width == PCIE_LNK_WIDTH_UNKNOWN) { | |
452 | mlx4_warn(dev, | |
453 | "Unable to determine PCI device chain minimum BW\n"); | |
454 | return; | |
455 | } | |
456 | ||
457 | if (width != width_cap || speed != speed_cap) | |
458 | mlx4_warn(dev, | |
459 | "PCIe BW is different than device's capability\n"); | |
460 | ||
461 | mlx4_info(dev, "PCIe link speed is %s, device supports %s\n", | |
462 | PCIE_SPEED_STR(speed), PCIE_SPEED_STR(speed_cap)); | |
463 | mlx4_info(dev, "PCIe link width is x%d, device supports x%d\n", | |
464 | width, width_cap); | |
465 | return; | |
466 | } | |
467 | ||
ab9c17a0 JM |
468 | /*The function checks if there are live vf, return the num of them*/ |
469 | static int mlx4_how_many_lives_vf(struct mlx4_dev *dev) | |
470 | { | |
471 | struct mlx4_priv *priv = mlx4_priv(dev); | |
472 | struct mlx4_slave_state *s_state; | |
473 | int i; | |
474 | int ret = 0; | |
475 | ||
476 | for (i = 1/*the ppf is 0*/; i < dev->num_slaves; ++i) { | |
477 | s_state = &priv->mfunc.master.slave_state[i]; | |
478 | if (s_state->active && s_state->last_cmd != | |
479 | MLX4_COMM_CMD_RESET) { | |
480 | mlx4_warn(dev, "%s: slave: %d is still active\n", | |
481 | __func__, i); | |
482 | ret++; | |
483 | } | |
484 | } | |
485 | return ret; | |
486 | } | |
487 | ||
396f2feb JM |
488 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey) |
489 | { | |
490 | u32 qk = MLX4_RESERVED_QKEY_BASE; | |
47605df9 JM |
491 | |
492 | if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX || | |
493 | qpn < dev->phys_caps.base_proxy_sqpn) | |
396f2feb JM |
494 | return -EINVAL; |
495 | ||
47605df9 | 496 | if (qpn >= dev->phys_caps.base_tunnel_sqpn) |
396f2feb | 497 | /* tunnel qp */ |
47605df9 | 498 | qk += qpn - dev->phys_caps.base_tunnel_sqpn; |
396f2feb | 499 | else |
47605df9 | 500 | qk += qpn - dev->phys_caps.base_proxy_sqpn; |
396f2feb JM |
501 | *qkey = qk; |
502 | return 0; | |
503 | } | |
504 | EXPORT_SYMBOL(mlx4_get_parav_qkey); | |
505 | ||
54679e14 JM |
506 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val) |
507 | { | |
508 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
509 | ||
510 | if (!mlx4_is_master(dev)) | |
511 | return; | |
512 | ||
513 | priv->virt2phys_pkey[slave][port - 1][i] = val; | |
514 | } | |
515 | EXPORT_SYMBOL(mlx4_sync_pkey_table); | |
516 | ||
afa8fd1d JM |
517 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid) |
518 | { | |
519 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
520 | ||
521 | if (!mlx4_is_master(dev)) | |
522 | return; | |
523 | ||
524 | priv->slave_node_guids[slave] = guid; | |
525 | } | |
526 | EXPORT_SYMBOL(mlx4_put_slave_node_guid); | |
527 | ||
528 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave) | |
529 | { | |
530 | struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev); | |
531 | ||
532 | if (!mlx4_is_master(dev)) | |
533 | return 0; | |
534 | ||
535 | return priv->slave_node_guids[slave]; | |
536 | } | |
537 | EXPORT_SYMBOL(mlx4_get_slave_node_guid); | |
538 | ||
e10903b0 | 539 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave) |
ab9c17a0 JM |
540 | { |
541 | struct mlx4_priv *priv = mlx4_priv(dev); | |
542 | struct mlx4_slave_state *s_slave; | |
543 | ||
544 | if (!mlx4_is_master(dev)) | |
545 | return 0; | |
546 | ||
547 | s_slave = &priv->mfunc.master.slave_state[slave]; | |
548 | return !!s_slave->active; | |
549 | } | |
550 | EXPORT_SYMBOL(mlx4_is_slave_active); | |
551 | ||
7b8157be JM |
552 | static void slave_adjust_steering_mode(struct mlx4_dev *dev, |
553 | struct mlx4_dev_cap *dev_cap, | |
554 | struct mlx4_init_hca_param *hca_param) | |
555 | { | |
556 | dev->caps.steering_mode = hca_param->steering_mode; | |
557 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { | |
558 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
559 | dev->caps.fs_log_max_ucast_qp_range_size = | |
560 | dev_cap->fs_log_max_ucast_qp_range_size; | |
561 | } else | |
562 | dev->caps.num_qp_per_mgm = | |
563 | 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2); | |
564 | ||
565 | mlx4_dbg(dev, "Steering mode is: %s\n", | |
566 | mlx4_steering_mode_str(dev->caps.steering_mode)); | |
567 | } | |
568 | ||
ab9c17a0 JM |
569 | static int mlx4_slave_cap(struct mlx4_dev *dev) |
570 | { | |
571 | int err; | |
572 | u32 page_size; | |
573 | struct mlx4_dev_cap dev_cap; | |
574 | struct mlx4_func_cap func_cap; | |
575 | struct mlx4_init_hca_param hca_param; | |
576 | int i; | |
577 | ||
578 | memset(&hca_param, 0, sizeof(hca_param)); | |
579 | err = mlx4_QUERY_HCA(dev, &hca_param); | |
580 | if (err) { | |
1a91de28 | 581 | mlx4_err(dev, "QUERY_HCA command failed, aborting\n"); |
ab9c17a0 JM |
582 | return err; |
583 | } | |
584 | ||
585 | /*fail if the hca has an unknown capability */ | |
586 | if ((hca_param.global_caps | HCA_GLOBAL_CAP_MASK) != | |
587 | HCA_GLOBAL_CAP_MASK) { | |
588 | mlx4_err(dev, "Unknown hca global capabilities\n"); | |
589 | return -ENOSYS; | |
590 | } | |
591 | ||
592 | mlx4_log_num_mgm_entry_size = hca_param.log_mc_entry_sz; | |
593 | ||
ddd8a6c1 EE |
594 | dev->caps.hca_core_clock = hca_param.hca_core_clock; |
595 | ||
ab9c17a0 | 596 | memset(&dev_cap, 0, sizeof(dev_cap)); |
b91cb3eb | 597 | dev->caps.max_qp_dest_rdma = 1 << hca_param.log_rd_per_qp; |
ab9c17a0 JM |
598 | err = mlx4_dev_cap(dev, &dev_cap); |
599 | if (err) { | |
1a91de28 | 600 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
ab9c17a0 JM |
601 | return err; |
602 | } | |
603 | ||
b91cb3eb JM |
604 | err = mlx4_QUERY_FW(dev); |
605 | if (err) | |
1a91de28 | 606 | mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n"); |
b91cb3eb | 607 | |
ab9c17a0 JM |
608 | page_size = ~dev->caps.page_size_cap + 1; |
609 | mlx4_warn(dev, "HCA minimum page size:%d\n", page_size); | |
610 | if (page_size > PAGE_SIZE) { | |
1a91de28 | 611 | mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n", |
ab9c17a0 JM |
612 | page_size, PAGE_SIZE); |
613 | return -ENODEV; | |
614 | } | |
615 | ||
616 | /* slave gets uar page size from QUERY_HCA fw command */ | |
617 | dev->caps.uar_page_size = 1 << (hca_param.uar_page_sz + 12); | |
618 | ||
619 | /* TODO: relax this assumption */ | |
620 | if (dev->caps.uar_page_size != PAGE_SIZE) { | |
621 | mlx4_err(dev, "UAR size:%d != kernel PAGE_SIZE of %ld\n", | |
622 | dev->caps.uar_page_size, PAGE_SIZE); | |
623 | return -ENODEV; | |
624 | } | |
625 | ||
626 | memset(&func_cap, 0, sizeof(func_cap)); | |
47605df9 | 627 | err = mlx4_QUERY_FUNC_CAP(dev, 0, &func_cap); |
ab9c17a0 | 628 | if (err) { |
1a91de28 JP |
629 | mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n", |
630 | err); | |
ab9c17a0 JM |
631 | return err; |
632 | } | |
633 | ||
634 | if ((func_cap.pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) != | |
635 | PF_CONTEXT_BEHAVIOUR_MASK) { | |
636 | mlx4_err(dev, "Unknown pf context behaviour\n"); | |
637 | return -ENOSYS; | |
638 | } | |
639 | ||
ab9c17a0 | 640 | dev->caps.num_ports = func_cap.num_ports; |
5a0d0a61 JM |
641 | dev->quotas.qp = func_cap.qp_quota; |
642 | dev->quotas.srq = func_cap.srq_quota; | |
643 | dev->quotas.cq = func_cap.cq_quota; | |
644 | dev->quotas.mpt = func_cap.mpt_quota; | |
645 | dev->quotas.mtt = func_cap.mtt_quota; | |
646 | dev->caps.num_qps = 1 << hca_param.log_num_qps; | |
647 | dev->caps.num_srqs = 1 << hca_param.log_num_srqs; | |
648 | dev->caps.num_cqs = 1 << hca_param.log_num_cqs; | |
649 | dev->caps.num_mpts = 1 << hca_param.log_mpt_sz; | |
650 | dev->caps.num_eqs = func_cap.max_eq; | |
651 | dev->caps.reserved_eqs = func_cap.reserved_eq; | |
ab9c17a0 JM |
652 | dev->caps.num_pds = MLX4_NUM_PDS; |
653 | dev->caps.num_mgms = 0; | |
654 | dev->caps.num_amgms = 0; | |
655 | ||
ab9c17a0 | 656 | if (dev->caps.num_ports > MLX4_MAX_PORTS) { |
1a91de28 JP |
657 | mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n", |
658 | dev->caps.num_ports, MLX4_MAX_PORTS); | |
ab9c17a0 JM |
659 | return -ENODEV; |
660 | } | |
661 | ||
47605df9 JM |
662 | dev->caps.qp0_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); |
663 | dev->caps.qp0_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
664 | dev->caps.qp1_tunnel = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
665 | dev->caps.qp1_proxy = kcalloc(dev->caps.num_ports, sizeof (u32), GFP_KERNEL); | |
666 | ||
667 | if (!dev->caps.qp0_tunnel || !dev->caps.qp0_proxy || | |
668 | !dev->caps.qp1_tunnel || !dev->caps.qp1_proxy) { | |
669 | err = -ENOMEM; | |
670 | goto err_mem; | |
671 | } | |
672 | ||
6634961c | 673 | for (i = 1; i <= dev->caps.num_ports; ++i) { |
47605df9 JM |
674 | err = mlx4_QUERY_FUNC_CAP(dev, (u32) i, &func_cap); |
675 | if (err) { | |
1a91de28 JP |
676 | mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n", |
677 | i, err); | |
47605df9 JM |
678 | goto err_mem; |
679 | } | |
680 | dev->caps.qp0_tunnel[i - 1] = func_cap.qp0_tunnel_qpn; | |
681 | dev->caps.qp0_proxy[i - 1] = func_cap.qp0_proxy_qpn; | |
682 | dev->caps.qp1_tunnel[i - 1] = func_cap.qp1_tunnel_qpn; | |
683 | dev->caps.qp1_proxy[i - 1] = func_cap.qp1_proxy_qpn; | |
6230bb23 | 684 | dev->caps.port_mask[i] = dev->caps.port_type[i]; |
8e1a28e8 | 685 | dev->caps.phys_port_id[i] = func_cap.phys_port_id; |
6634961c JM |
686 | if (mlx4_get_slave_pkey_gid_tbl_len(dev, i, |
687 | &dev->caps.gid_table_len[i], | |
688 | &dev->caps.pkey_table_len[i])) | |
47605df9 | 689 | goto err_mem; |
6634961c | 690 | } |
6230bb23 | 691 | |
ab9c17a0 JM |
692 | if (dev->caps.uar_page_size * (dev->caps.num_uars - |
693 | dev->caps.reserved_uars) > | |
694 | pci_resource_len(dev->pdev, 2)) { | |
1a91de28 | 695 | mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n", |
ab9c17a0 JM |
696 | dev->caps.uar_page_size * dev->caps.num_uars, |
697 | (unsigned long long) pci_resource_len(dev->pdev, 2)); | |
47605df9 | 698 | goto err_mem; |
ab9c17a0 JM |
699 | } |
700 | ||
08ff3235 OG |
701 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) { |
702 | dev->caps.eqe_size = 64; | |
703 | dev->caps.eqe_factor = 1; | |
704 | } else { | |
705 | dev->caps.eqe_size = 32; | |
706 | dev->caps.eqe_factor = 0; | |
707 | } | |
708 | ||
709 | if (hca_param.dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) { | |
710 | dev->caps.cqe_size = 64; | |
711 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_64B_CQE; | |
712 | } else { | |
713 | dev->caps.cqe_size = 32; | |
714 | } | |
715 | ||
f9bd2d7f | 716 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
1a91de28 | 717 | mlx4_warn(dev, "Timestamping is not supported in slave mode\n"); |
f9bd2d7f | 718 | |
7b8157be JM |
719 | slave_adjust_steering_mode(dev, &dev_cap, &hca_param); |
720 | ||
ab9c17a0 | 721 | return 0; |
47605df9 JM |
722 | |
723 | err_mem: | |
724 | kfree(dev->caps.qp0_tunnel); | |
725 | kfree(dev->caps.qp0_proxy); | |
726 | kfree(dev->caps.qp1_tunnel); | |
727 | kfree(dev->caps.qp1_proxy); | |
728 | dev->caps.qp0_tunnel = dev->caps.qp0_proxy = | |
729 | dev->caps.qp1_tunnel = dev->caps.qp1_proxy = NULL; | |
730 | ||
731 | return err; | |
ab9c17a0 | 732 | } |
225c7b1f | 733 | |
b046ffe5 EP |
734 | static void mlx4_request_modules(struct mlx4_dev *dev) |
735 | { | |
736 | int port; | |
737 | int has_ib_port = false; | |
738 | int has_eth_port = false; | |
739 | #define EN_DRV_NAME "mlx4_en" | |
740 | #define IB_DRV_NAME "mlx4_ib" | |
741 | ||
742 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
743 | if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB) | |
744 | has_ib_port = true; | |
745 | else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH) | |
746 | has_eth_port = true; | |
747 | } | |
748 | ||
7855bff4 | 749 | if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) |
b046ffe5 EP |
750 | request_module_nowait(IB_DRV_NAME); |
751 | if (has_eth_port) | |
752 | request_module_nowait(EN_DRV_NAME); | |
753 | } | |
754 | ||
7ff93f8b YP |
755 | /* |
756 | * Change the port configuration of the device. | |
757 | * Every user of this function must hold the port mutex. | |
758 | */ | |
27bf91d6 YP |
759 | int mlx4_change_port_types(struct mlx4_dev *dev, |
760 | enum mlx4_port_type *port_types) | |
7ff93f8b YP |
761 | { |
762 | int err = 0; | |
763 | int change = 0; | |
764 | int port; | |
765 | ||
766 | for (port = 0; port < dev->caps.num_ports; port++) { | |
27bf91d6 YP |
767 | /* Change the port type only if the new type is different |
768 | * from the current, and not set to Auto */ | |
3d8f9308 | 769 | if (port_types[port] != dev->caps.port_type[port + 1]) |
7ff93f8b | 770 | change = 1; |
7ff93f8b YP |
771 | } |
772 | if (change) { | |
773 | mlx4_unregister_device(dev); | |
774 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
775 | mlx4_CLOSE_PORT(dev, port); | |
1e0f03d5 | 776 | dev->caps.port_type[port] = port_types[port - 1]; |
6634961c | 777 | err = mlx4_SET_PORT(dev, port, -1); |
7ff93f8b | 778 | if (err) { |
1a91de28 JP |
779 | mlx4_err(dev, "Failed to set port %d, aborting\n", |
780 | port); | |
7ff93f8b YP |
781 | goto out; |
782 | } | |
783 | } | |
784 | mlx4_set_port_mask(dev); | |
785 | err = mlx4_register_device(dev); | |
b046ffe5 EP |
786 | if (err) { |
787 | mlx4_err(dev, "Failed to register device\n"); | |
788 | goto out; | |
789 | } | |
790 | mlx4_request_modules(dev); | |
7ff93f8b YP |
791 | } |
792 | ||
793 | out: | |
794 | return err; | |
795 | } | |
796 | ||
797 | static ssize_t show_port_type(struct device *dev, | |
798 | struct device_attribute *attr, | |
799 | char *buf) | |
800 | { | |
801 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
802 | port_attr); | |
803 | struct mlx4_dev *mdev = info->dev; | |
27bf91d6 YP |
804 | char type[8]; |
805 | ||
806 | sprintf(type, "%s", | |
807 | (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ? | |
808 | "ib" : "eth"); | |
809 | if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO) | |
810 | sprintf(buf, "auto (%s)\n", type); | |
811 | else | |
812 | sprintf(buf, "%s\n", type); | |
7ff93f8b | 813 | |
27bf91d6 | 814 | return strlen(buf); |
7ff93f8b YP |
815 | } |
816 | ||
817 | static ssize_t set_port_type(struct device *dev, | |
818 | struct device_attribute *attr, | |
819 | const char *buf, size_t count) | |
820 | { | |
821 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
822 | port_attr); | |
823 | struct mlx4_dev *mdev = info->dev; | |
824 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
825 | enum mlx4_port_type types[MLX4_MAX_PORTS]; | |
27bf91d6 | 826 | enum mlx4_port_type new_types[MLX4_MAX_PORTS]; |
7ff93f8b YP |
827 | int i; |
828 | int err = 0; | |
829 | ||
830 | if (!strcmp(buf, "ib\n")) | |
831 | info->tmp_type = MLX4_PORT_TYPE_IB; | |
832 | else if (!strcmp(buf, "eth\n")) | |
833 | info->tmp_type = MLX4_PORT_TYPE_ETH; | |
27bf91d6 YP |
834 | else if (!strcmp(buf, "auto\n")) |
835 | info->tmp_type = MLX4_PORT_TYPE_AUTO; | |
7ff93f8b YP |
836 | else { |
837 | mlx4_err(mdev, "%s is not supported port type\n", buf); | |
838 | return -EINVAL; | |
839 | } | |
840 | ||
27bf91d6 | 841 | mlx4_stop_sense(mdev); |
7ff93f8b | 842 | mutex_lock(&priv->port_mutex); |
27bf91d6 YP |
843 | /* Possible type is always the one that was delivered */ |
844 | mdev->caps.possible_type[info->port] = info->tmp_type; | |
845 | ||
846 | for (i = 0; i < mdev->caps.num_ports; i++) { | |
7ff93f8b | 847 | types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type : |
27bf91d6 YP |
848 | mdev->caps.possible_type[i+1]; |
849 | if (types[i] == MLX4_PORT_TYPE_AUTO) | |
850 | types[i] = mdev->caps.port_type[i+1]; | |
851 | } | |
7ff93f8b | 852 | |
58a60168 YP |
853 | if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) && |
854 | !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) { | |
27bf91d6 YP |
855 | for (i = 1; i <= mdev->caps.num_ports; i++) { |
856 | if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) { | |
857 | mdev->caps.possible_type[i] = mdev->caps.port_type[i]; | |
858 | err = -EINVAL; | |
859 | } | |
860 | } | |
861 | } | |
862 | if (err) { | |
1a91de28 | 863 | mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n"); |
27bf91d6 YP |
864 | goto out; |
865 | } | |
866 | ||
867 | mlx4_do_sense_ports(mdev, new_types, types); | |
868 | ||
869 | err = mlx4_check_port_params(mdev, new_types); | |
7ff93f8b YP |
870 | if (err) |
871 | goto out; | |
872 | ||
27bf91d6 YP |
873 | /* We are about to apply the changes after the configuration |
874 | * was verified, no need to remember the temporary types | |
875 | * any more */ | |
876 | for (i = 0; i < mdev->caps.num_ports; i++) | |
877 | priv->port[i + 1].tmp_type = 0; | |
7ff93f8b | 878 | |
27bf91d6 | 879 | err = mlx4_change_port_types(mdev, new_types); |
7ff93f8b YP |
880 | |
881 | out: | |
27bf91d6 | 882 | mlx4_start_sense(mdev); |
7ff93f8b YP |
883 | mutex_unlock(&priv->port_mutex); |
884 | return err ? err : count; | |
885 | } | |
886 | ||
096335b3 OG |
887 | enum ibta_mtu { |
888 | IB_MTU_256 = 1, | |
889 | IB_MTU_512 = 2, | |
890 | IB_MTU_1024 = 3, | |
891 | IB_MTU_2048 = 4, | |
892 | IB_MTU_4096 = 5 | |
893 | }; | |
894 | ||
895 | static inline int int_to_ibta_mtu(int mtu) | |
896 | { | |
897 | switch (mtu) { | |
898 | case 256: return IB_MTU_256; | |
899 | case 512: return IB_MTU_512; | |
900 | case 1024: return IB_MTU_1024; | |
901 | case 2048: return IB_MTU_2048; | |
902 | case 4096: return IB_MTU_4096; | |
903 | default: return -1; | |
904 | } | |
905 | } | |
906 | ||
907 | static inline int ibta_mtu_to_int(enum ibta_mtu mtu) | |
908 | { | |
909 | switch (mtu) { | |
910 | case IB_MTU_256: return 256; | |
911 | case IB_MTU_512: return 512; | |
912 | case IB_MTU_1024: return 1024; | |
913 | case IB_MTU_2048: return 2048; | |
914 | case IB_MTU_4096: return 4096; | |
915 | default: return -1; | |
916 | } | |
917 | } | |
918 | ||
919 | static ssize_t show_port_ib_mtu(struct device *dev, | |
920 | struct device_attribute *attr, | |
921 | char *buf) | |
922 | { | |
923 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
924 | port_mtu_attr); | |
925 | struct mlx4_dev *mdev = info->dev; | |
926 | ||
927 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) | |
928 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
929 | ||
930 | sprintf(buf, "%d\n", | |
931 | ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port])); | |
932 | return strlen(buf); | |
933 | } | |
934 | ||
935 | static ssize_t set_port_ib_mtu(struct device *dev, | |
936 | struct device_attribute *attr, | |
937 | const char *buf, size_t count) | |
938 | { | |
939 | struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info, | |
940 | port_mtu_attr); | |
941 | struct mlx4_dev *mdev = info->dev; | |
942 | struct mlx4_priv *priv = mlx4_priv(mdev); | |
943 | int err, port, mtu, ibta_mtu = -1; | |
944 | ||
945 | if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) { | |
946 | mlx4_warn(mdev, "port level mtu is only used for IB ports\n"); | |
947 | return -EINVAL; | |
948 | } | |
949 | ||
618fad95 DB |
950 | err = kstrtoint(buf, 0, &mtu); |
951 | if (!err) | |
096335b3 OG |
952 | ibta_mtu = int_to_ibta_mtu(mtu); |
953 | ||
618fad95 | 954 | if (err || ibta_mtu < 0) { |
096335b3 OG |
955 | mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf); |
956 | return -EINVAL; | |
957 | } | |
958 | ||
959 | mdev->caps.port_ib_mtu[info->port] = ibta_mtu; | |
960 | ||
961 | mlx4_stop_sense(mdev); | |
962 | mutex_lock(&priv->port_mutex); | |
963 | mlx4_unregister_device(mdev); | |
964 | for (port = 1; port <= mdev->caps.num_ports; port++) { | |
965 | mlx4_CLOSE_PORT(mdev, port); | |
6634961c | 966 | err = mlx4_SET_PORT(mdev, port, -1); |
096335b3 | 967 | if (err) { |
1a91de28 JP |
968 | mlx4_err(mdev, "Failed to set port %d, aborting\n", |
969 | port); | |
096335b3 OG |
970 | goto err_set_port; |
971 | } | |
972 | } | |
973 | err = mlx4_register_device(mdev); | |
974 | err_set_port: | |
975 | mutex_unlock(&priv->port_mutex); | |
976 | mlx4_start_sense(mdev); | |
977 | return err ? err : count; | |
978 | } | |
979 | ||
e8f9b2ed | 980 | static int mlx4_load_fw(struct mlx4_dev *dev) |
225c7b1f RD |
981 | { |
982 | struct mlx4_priv *priv = mlx4_priv(dev); | |
983 | int err; | |
984 | ||
985 | priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages, | |
5b0bf5e2 | 986 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f | 987 | if (!priv->fw.fw_icm) { |
1a91de28 | 988 | mlx4_err(dev, "Couldn't allocate FW area, aborting\n"); |
225c7b1f RD |
989 | return -ENOMEM; |
990 | } | |
991 | ||
992 | err = mlx4_MAP_FA(dev, priv->fw.fw_icm); | |
993 | if (err) { | |
1a91de28 | 994 | mlx4_err(dev, "MAP_FA command failed, aborting\n"); |
225c7b1f RD |
995 | goto err_free; |
996 | } | |
997 | ||
998 | err = mlx4_RUN_FW(dev); | |
999 | if (err) { | |
1a91de28 | 1000 | mlx4_err(dev, "RUN_FW command failed, aborting\n"); |
225c7b1f RD |
1001 | goto err_unmap_fa; |
1002 | } | |
1003 | ||
1004 | return 0; | |
1005 | ||
1006 | err_unmap_fa: | |
1007 | mlx4_UNMAP_FA(dev); | |
1008 | ||
1009 | err_free: | |
5b0bf5e2 | 1010 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); |
225c7b1f RD |
1011 | return err; |
1012 | } | |
1013 | ||
e8f9b2ed RD |
1014 | static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base, |
1015 | int cmpt_entry_sz) | |
225c7b1f RD |
1016 | { |
1017 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1018 | int err; | |
ab9c17a0 | 1019 | int num_eqs; |
225c7b1f RD |
1020 | |
1021 | err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table, | |
1022 | cmpt_base + | |
1023 | ((u64) (MLX4_CMPT_TYPE_QP * | |
1024 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1025 | cmpt_entry_sz, dev->caps.num_qps, | |
93fc9e1b YP |
1026 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1027 | 0, 0); | |
225c7b1f RD |
1028 | if (err) |
1029 | goto err; | |
1030 | ||
1031 | err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table, | |
1032 | cmpt_base + | |
1033 | ((u64) (MLX4_CMPT_TYPE_SRQ * | |
1034 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1035 | cmpt_entry_sz, dev->caps.num_srqs, | |
5b0bf5e2 | 1036 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f RD |
1037 | if (err) |
1038 | goto err_qp; | |
1039 | ||
1040 | err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table, | |
1041 | cmpt_base + | |
1042 | ((u64) (MLX4_CMPT_TYPE_CQ * | |
1043 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
1044 | cmpt_entry_sz, dev->caps.num_cqs, | |
5b0bf5e2 | 1045 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f RD |
1046 | if (err) |
1047 | goto err_srq; | |
1048 | ||
3fc929e2 MA |
1049 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
1050 | dev->caps.num_eqs; | |
225c7b1f RD |
1051 | err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table, |
1052 | cmpt_base + | |
1053 | ((u64) (MLX4_CMPT_TYPE_EQ * | |
1054 | cmpt_entry_sz) << MLX4_CMPT_SHIFT), | |
ab9c17a0 | 1055 | cmpt_entry_sz, num_eqs, num_eqs, 0, 0); |
225c7b1f RD |
1056 | if (err) |
1057 | goto err_cq; | |
1058 | ||
1059 | return 0; | |
1060 | ||
1061 | err_cq: | |
1062 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1063 | ||
1064 | err_srq: | |
1065 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1066 | ||
1067 | err_qp: | |
1068 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1069 | ||
1070 | err: | |
1071 | return err; | |
1072 | } | |
1073 | ||
3d73c288 RD |
1074 | static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap, |
1075 | struct mlx4_init_hca_param *init_hca, u64 icm_size) | |
225c7b1f RD |
1076 | { |
1077 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1078 | u64 aux_pages; | |
ab9c17a0 | 1079 | int num_eqs; |
225c7b1f RD |
1080 | int err; |
1081 | ||
1082 | err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages); | |
1083 | if (err) { | |
1a91de28 | 1084 | mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n"); |
225c7b1f RD |
1085 | return err; |
1086 | } | |
1087 | ||
1a91de28 | 1088 | mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n", |
225c7b1f RD |
1089 | (unsigned long long) icm_size >> 10, |
1090 | (unsigned long long) aux_pages << 2); | |
1091 | ||
1092 | priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages, | |
5b0bf5e2 | 1093 | GFP_HIGHUSER | __GFP_NOWARN, 0); |
225c7b1f | 1094 | if (!priv->fw.aux_icm) { |
1a91de28 | 1095 | mlx4_err(dev, "Couldn't allocate aux memory, aborting\n"); |
225c7b1f RD |
1096 | return -ENOMEM; |
1097 | } | |
1098 | ||
1099 | err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm); | |
1100 | if (err) { | |
1a91de28 | 1101 | mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n"); |
225c7b1f RD |
1102 | goto err_free_aux; |
1103 | } | |
1104 | ||
1105 | err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz); | |
1106 | if (err) { | |
1a91de28 | 1107 | mlx4_err(dev, "Failed to map cMPT context memory, aborting\n"); |
225c7b1f RD |
1108 | goto err_unmap_aux; |
1109 | } | |
1110 | ||
ab9c17a0 | 1111 | |
3fc929e2 MA |
1112 | num_eqs = (mlx4_is_master(dev)) ? dev->phys_caps.num_phys_eqs : |
1113 | dev->caps.num_eqs; | |
fa0681d2 RD |
1114 | err = mlx4_init_icm_table(dev, &priv->eq_table.table, |
1115 | init_hca->eqc_base, dev_cap->eqc_entry_sz, | |
ab9c17a0 | 1116 | num_eqs, num_eqs, 0, 0); |
225c7b1f | 1117 | if (err) { |
1a91de28 | 1118 | mlx4_err(dev, "Failed to map EQ context memory, aborting\n"); |
225c7b1f RD |
1119 | goto err_unmap_cmpt; |
1120 | } | |
1121 | ||
d7bb58fb JM |
1122 | /* |
1123 | * Reserved MTT entries must be aligned up to a cacheline | |
1124 | * boundary, since the FW will write to them, while the driver | |
1125 | * writes to all other MTT entries. (The variable | |
1126 | * dev->caps.mtt_entry_sz below is really the MTT segment | |
1127 | * size, not the raw entry size) | |
1128 | */ | |
1129 | dev->caps.reserved_mtts = | |
1130 | ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz, | |
1131 | dma_get_cache_alignment()) / dev->caps.mtt_entry_sz; | |
1132 | ||
225c7b1f RD |
1133 | err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table, |
1134 | init_hca->mtt_base, | |
1135 | dev->caps.mtt_entry_sz, | |
2b8fb286 | 1136 | dev->caps.num_mtts, |
5b0bf5e2 | 1137 | dev->caps.reserved_mtts, 1, 0); |
225c7b1f | 1138 | if (err) { |
1a91de28 | 1139 | mlx4_err(dev, "Failed to map MTT context memory, aborting\n"); |
225c7b1f RD |
1140 | goto err_unmap_eq; |
1141 | } | |
1142 | ||
1143 | err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table, | |
1144 | init_hca->dmpt_base, | |
1145 | dev_cap->dmpt_entry_sz, | |
1146 | dev->caps.num_mpts, | |
5b0bf5e2 | 1147 | dev->caps.reserved_mrws, 1, 1); |
225c7b1f | 1148 | if (err) { |
1a91de28 | 1149 | mlx4_err(dev, "Failed to map dMPT context memory, aborting\n"); |
225c7b1f RD |
1150 | goto err_unmap_mtt; |
1151 | } | |
1152 | ||
1153 | err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table, | |
1154 | init_hca->qpc_base, | |
1155 | dev_cap->qpc_entry_sz, | |
1156 | dev->caps.num_qps, | |
93fc9e1b YP |
1157 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1158 | 0, 0); | |
225c7b1f | 1159 | if (err) { |
1a91de28 | 1160 | mlx4_err(dev, "Failed to map QP context memory, aborting\n"); |
225c7b1f RD |
1161 | goto err_unmap_dmpt; |
1162 | } | |
1163 | ||
1164 | err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table, | |
1165 | init_hca->auxc_base, | |
1166 | dev_cap->aux_entry_sz, | |
1167 | dev->caps.num_qps, | |
93fc9e1b YP |
1168 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1169 | 0, 0); | |
225c7b1f | 1170 | if (err) { |
1a91de28 | 1171 | mlx4_err(dev, "Failed to map AUXC context memory, aborting\n"); |
225c7b1f RD |
1172 | goto err_unmap_qp; |
1173 | } | |
1174 | ||
1175 | err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table, | |
1176 | init_hca->altc_base, | |
1177 | dev_cap->altc_entry_sz, | |
1178 | dev->caps.num_qps, | |
93fc9e1b YP |
1179 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1180 | 0, 0); | |
225c7b1f | 1181 | if (err) { |
1a91de28 | 1182 | mlx4_err(dev, "Failed to map ALTC context memory, aborting\n"); |
225c7b1f RD |
1183 | goto err_unmap_auxc; |
1184 | } | |
1185 | ||
1186 | err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table, | |
1187 | init_hca->rdmarc_base, | |
1188 | dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift, | |
1189 | dev->caps.num_qps, | |
93fc9e1b YP |
1190 | dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW], |
1191 | 0, 0); | |
225c7b1f RD |
1192 | if (err) { |
1193 | mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n"); | |
1194 | goto err_unmap_altc; | |
1195 | } | |
1196 | ||
1197 | err = mlx4_init_icm_table(dev, &priv->cq_table.table, | |
1198 | init_hca->cqc_base, | |
1199 | dev_cap->cqc_entry_sz, | |
1200 | dev->caps.num_cqs, | |
5b0bf5e2 | 1201 | dev->caps.reserved_cqs, 0, 0); |
225c7b1f | 1202 | if (err) { |
1a91de28 | 1203 | mlx4_err(dev, "Failed to map CQ context memory, aborting\n"); |
225c7b1f RD |
1204 | goto err_unmap_rdmarc; |
1205 | } | |
1206 | ||
1207 | err = mlx4_init_icm_table(dev, &priv->srq_table.table, | |
1208 | init_hca->srqc_base, | |
1209 | dev_cap->srq_entry_sz, | |
1210 | dev->caps.num_srqs, | |
5b0bf5e2 | 1211 | dev->caps.reserved_srqs, 0, 0); |
225c7b1f | 1212 | if (err) { |
1a91de28 | 1213 | mlx4_err(dev, "Failed to map SRQ context memory, aborting\n"); |
225c7b1f RD |
1214 | goto err_unmap_cq; |
1215 | } | |
1216 | ||
1217 | /* | |
0ff1fb65 HHZ |
1218 | * For flow steering device managed mode it is required to use |
1219 | * mlx4_init_icm_table. For B0 steering mode it's not strictly | |
1220 | * required, but for simplicity just map the whole multicast | |
1221 | * group table now. The table isn't very big and it's a lot | |
1222 | * easier than trying to track ref counts. | |
225c7b1f RD |
1223 | */ |
1224 | err = mlx4_init_icm_table(dev, &priv->mcg_table.table, | |
0ec2c0f8 EE |
1225 | init_hca->mc_base, |
1226 | mlx4_get_mgm_entry_size(dev), | |
225c7b1f RD |
1227 | dev->caps.num_mgms + dev->caps.num_amgms, |
1228 | dev->caps.num_mgms + dev->caps.num_amgms, | |
5b0bf5e2 | 1229 | 0, 0); |
225c7b1f | 1230 | if (err) { |
1a91de28 | 1231 | mlx4_err(dev, "Failed to map MCG context memory, aborting\n"); |
225c7b1f RD |
1232 | goto err_unmap_srq; |
1233 | } | |
1234 | ||
1235 | return 0; | |
1236 | ||
1237 | err_unmap_srq: | |
1238 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1239 | ||
1240 | err_unmap_cq: | |
1241 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1242 | ||
1243 | err_unmap_rdmarc: | |
1244 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1245 | ||
1246 | err_unmap_altc: | |
1247 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1248 | ||
1249 | err_unmap_auxc: | |
1250 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1251 | ||
1252 | err_unmap_qp: | |
1253 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1254 | ||
1255 | err_unmap_dmpt: | |
1256 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1257 | ||
1258 | err_unmap_mtt: | |
1259 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
1260 | ||
1261 | err_unmap_eq: | |
fa0681d2 | 1262 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1263 | |
1264 | err_unmap_cmpt: | |
1265 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); | |
1266 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1267 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1268 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
1269 | ||
1270 | err_unmap_aux: | |
1271 | mlx4_UNMAP_ICM_AUX(dev); | |
1272 | ||
1273 | err_free_aux: | |
5b0bf5e2 | 1274 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1275 | |
1276 | return err; | |
1277 | } | |
1278 | ||
1279 | static void mlx4_free_icms(struct mlx4_dev *dev) | |
1280 | { | |
1281 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1282 | ||
1283 | mlx4_cleanup_icm_table(dev, &priv->mcg_table.table); | |
1284 | mlx4_cleanup_icm_table(dev, &priv->srq_table.table); | |
1285 | mlx4_cleanup_icm_table(dev, &priv->cq_table.table); | |
1286 | mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table); | |
1287 | mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table); | |
1288 | mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table); | |
1289 | mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table); | |
1290 | mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table); | |
1291 | mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table); | |
fa0681d2 | 1292 | mlx4_cleanup_icm_table(dev, &priv->eq_table.table); |
225c7b1f RD |
1293 | mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table); |
1294 | mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table); | |
1295 | mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table); | |
1296 | mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table); | |
225c7b1f RD |
1297 | |
1298 | mlx4_UNMAP_ICM_AUX(dev); | |
5b0bf5e2 | 1299 | mlx4_free_icm(dev, priv->fw.aux_icm, 0); |
225c7b1f RD |
1300 | } |
1301 | ||
ab9c17a0 JM |
1302 | static void mlx4_slave_exit(struct mlx4_dev *dev) |
1303 | { | |
1304 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1305 | ||
f3d4c89e | 1306 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1307 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_TIME)) |
1a91de28 | 1308 | mlx4_warn(dev, "Failed to close slave function\n"); |
f3d4c89e | 1309 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1310 | } |
1311 | ||
c1b43dca EC |
1312 | static int map_bf_area(struct mlx4_dev *dev) |
1313 | { | |
1314 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1315 | resource_size_t bf_start; | |
1316 | resource_size_t bf_len; | |
1317 | int err = 0; | |
1318 | ||
3d747473 JM |
1319 | if (!dev->caps.bf_reg_size) |
1320 | return -ENXIO; | |
1321 | ||
ab9c17a0 JM |
1322 | bf_start = pci_resource_start(dev->pdev, 2) + |
1323 | (dev->caps.num_uars << PAGE_SHIFT); | |
1324 | bf_len = pci_resource_len(dev->pdev, 2) - | |
1325 | (dev->caps.num_uars << PAGE_SHIFT); | |
c1b43dca EC |
1326 | priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len); |
1327 | if (!priv->bf_mapping) | |
1328 | err = -ENOMEM; | |
1329 | ||
1330 | return err; | |
1331 | } | |
1332 | ||
1333 | static void unmap_bf_area(struct mlx4_dev *dev) | |
1334 | { | |
1335 | if (mlx4_priv(dev)->bf_mapping) | |
1336 | io_mapping_free(mlx4_priv(dev)->bf_mapping); | |
1337 | } | |
1338 | ||
ec693d47 AV |
1339 | cycle_t mlx4_read_clock(struct mlx4_dev *dev) |
1340 | { | |
1341 | u32 clockhi, clocklo, clockhi1; | |
1342 | cycle_t cycles; | |
1343 | int i; | |
1344 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1345 | ||
1346 | for (i = 0; i < 10; i++) { | |
1347 | clockhi = swab32(readl(priv->clock_mapping)); | |
1348 | clocklo = swab32(readl(priv->clock_mapping + 4)); | |
1349 | clockhi1 = swab32(readl(priv->clock_mapping)); | |
1350 | if (clockhi == clockhi1) | |
1351 | break; | |
1352 | } | |
1353 | ||
1354 | cycles = (u64) clockhi << 32 | (u64) clocklo; | |
1355 | ||
1356 | return cycles; | |
1357 | } | |
1358 | EXPORT_SYMBOL_GPL(mlx4_read_clock); | |
1359 | ||
1360 | ||
ddd8a6c1 EE |
1361 | static int map_internal_clock(struct mlx4_dev *dev) |
1362 | { | |
1363 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1364 | ||
1365 | priv->clock_mapping = | |
1366 | ioremap(pci_resource_start(dev->pdev, priv->fw.clock_bar) + | |
1367 | priv->fw.clock_offset, MLX4_CLOCK_SIZE); | |
1368 | ||
1369 | if (!priv->clock_mapping) | |
1370 | return -ENOMEM; | |
1371 | ||
1372 | return 0; | |
1373 | } | |
1374 | ||
1375 | static void unmap_internal_clock(struct mlx4_dev *dev) | |
1376 | { | |
1377 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1378 | ||
1379 | if (priv->clock_mapping) | |
1380 | iounmap(priv->clock_mapping); | |
1381 | } | |
1382 | ||
225c7b1f RD |
1383 | static void mlx4_close_hca(struct mlx4_dev *dev) |
1384 | { | |
ddd8a6c1 | 1385 | unmap_internal_clock(dev); |
c1b43dca | 1386 | unmap_bf_area(dev); |
ab9c17a0 JM |
1387 | if (mlx4_is_slave(dev)) |
1388 | mlx4_slave_exit(dev); | |
1389 | else { | |
1390 | mlx4_CLOSE_HCA(dev, 0); | |
1391 | mlx4_free_icms(dev); | |
1392 | mlx4_UNMAP_FA(dev); | |
1393 | mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0); | |
1394 | } | |
1395 | } | |
1396 | ||
1397 | static int mlx4_init_slave(struct mlx4_dev *dev) | |
1398 | { | |
1399 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1400 | u64 dma = (u64) priv->mfunc.vhcr_dma; | |
ab9c17a0 JM |
1401 | int ret_from_reset = 0; |
1402 | u32 slave_read; | |
1403 | u32 cmd_channel_ver; | |
1404 | ||
97989356 | 1405 | if (atomic_read(&pf_loading)) { |
1a91de28 | 1406 | mlx4_warn(dev, "PF is not ready - Deferring probe\n"); |
97989356 AV |
1407 | return -EPROBE_DEFER; |
1408 | } | |
1409 | ||
f3d4c89e | 1410 | mutex_lock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 JM |
1411 | priv->cmd.max_cmds = 1; |
1412 | mlx4_warn(dev, "Sending reset\n"); | |
1413 | ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, | |
1414 | MLX4_COMM_TIME); | |
1415 | /* if we are in the middle of flr the slave will try | |
1416 | * NUM_OF_RESET_RETRIES times before leaving.*/ | |
1417 | if (ret_from_reset) { | |
1418 | if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) { | |
1a91de28 | 1419 | mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n"); |
5efe5355 JM |
1420 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
1421 | return -EPROBE_DEFER; | |
ab9c17a0 JM |
1422 | } else |
1423 | goto err; | |
1424 | } | |
1425 | ||
1426 | /* check the driver version - the slave I/F revision | |
1427 | * must match the master's */ | |
1428 | slave_read = swab32(readl(&priv->mfunc.comm->slave_read)); | |
1429 | cmd_channel_ver = mlx4_comm_get_version(); | |
1430 | ||
1431 | if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) != | |
1432 | MLX4_COMM_GET_IF_REV(slave_read)) { | |
1a91de28 | 1433 | mlx4_err(dev, "slave driver version is not supported by the master\n"); |
ab9c17a0 JM |
1434 | goto err; |
1435 | } | |
1436 | ||
1437 | mlx4_warn(dev, "Sending vhcr0\n"); | |
1438 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48, | |
1439 | MLX4_COMM_TIME)) | |
1440 | goto err; | |
1441 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32, | |
1442 | MLX4_COMM_TIME)) | |
1443 | goto err; | |
1444 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16, | |
1445 | MLX4_COMM_TIME)) | |
1446 | goto err; | |
1447 | if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma, MLX4_COMM_TIME)) | |
1448 | goto err; | |
f3d4c89e RD |
1449 | |
1450 | mutex_unlock(&priv->cmd.slave_cmd_mutex); | |
ab9c17a0 JM |
1451 | return 0; |
1452 | ||
1453 | err: | |
1454 | mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, 0); | |
f3d4c89e | 1455 | mutex_unlock(&priv->cmd.slave_cmd_mutex); |
ab9c17a0 | 1456 | return -EIO; |
225c7b1f RD |
1457 | } |
1458 | ||
6634961c JM |
1459 | static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev) |
1460 | { | |
1461 | int i; | |
1462 | ||
1463 | for (i = 1; i <= dev->caps.num_ports; i++) { | |
b6ffaeff JM |
1464 | if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) |
1465 | dev->caps.gid_table_len[i] = | |
449fc488 | 1466 | mlx4_get_slave_num_gids(dev, 0, i); |
b6ffaeff JM |
1467 | else |
1468 | dev->caps.gid_table_len[i] = 1; | |
6634961c JM |
1469 | dev->caps.pkey_table_len[i] = |
1470 | dev->phys_caps.pkey_phys_table_len[i] - 1; | |
1471 | } | |
1472 | } | |
1473 | ||
3c439b55 JM |
1474 | static int choose_log_fs_mgm_entry_size(int qp_per_entry) |
1475 | { | |
1476 | int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; | |
1477 | ||
1478 | for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE; | |
1479 | i++) { | |
1480 | if (qp_per_entry <= 4 * ((1 << i) / 16 - 2)) | |
1481 | break; | |
1482 | } | |
1483 | ||
1484 | return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1; | |
1485 | } | |
1486 | ||
7b8157be JM |
1487 | static void choose_steering_mode(struct mlx4_dev *dev, |
1488 | struct mlx4_dev_cap *dev_cap) | |
1489 | { | |
3c439b55 JM |
1490 | if (mlx4_log_num_mgm_entry_size == -1 && |
1491 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN && | |
7b8157be | 1492 | (!mlx4_is_mfunc(dev) || |
449fc488 | 1493 | (dev_cap->fs_max_num_qp_per_entry >= (dev->num_vfs + 1))) && |
3c439b55 JM |
1494 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >= |
1495 | MLX4_MIN_MGM_LOG_ENTRY_SIZE) { | |
1496 | dev->oper_log_mgm_entry_size = | |
1497 | choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry); | |
7b8157be JM |
1498 | dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
1499 | dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry; | |
1500 | dev->caps.fs_log_max_ucast_qp_range_size = | |
1501 | dev_cap->fs_log_max_ucast_qp_range_size; | |
1502 | } else { | |
1503 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER && | |
1504 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1505 | dev->caps.steering_mode = MLX4_STEERING_MODE_B0; | |
1506 | else { | |
1507 | dev->caps.steering_mode = MLX4_STEERING_MODE_A0; | |
1508 | ||
1509 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER || | |
1510 | dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER) | |
1a91de28 | 1511 | mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n"); |
7b8157be | 1512 | } |
3c439b55 JM |
1513 | dev->oper_log_mgm_entry_size = |
1514 | mlx4_log_num_mgm_entry_size > 0 ? | |
1515 | mlx4_log_num_mgm_entry_size : | |
1516 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE; | |
7b8157be JM |
1517 | dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev); |
1518 | } | |
1a91de28 | 1519 | mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n", |
3c439b55 JM |
1520 | mlx4_steering_mode_str(dev->caps.steering_mode), |
1521 | dev->oper_log_mgm_entry_size, | |
1522 | mlx4_log_num_mgm_entry_size); | |
7b8157be JM |
1523 | } |
1524 | ||
7ffdf726 OG |
1525 | static void choose_tunnel_offload_mode(struct mlx4_dev *dev, |
1526 | struct mlx4_dev_cap *dev_cap) | |
1527 | { | |
1528 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED && | |
1529 | dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) | |
1530 | dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN; | |
1531 | else | |
1532 | dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE; | |
1533 | ||
1534 | mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode | |
1535 | == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none"); | |
1536 | } | |
1537 | ||
3d73c288 | 1538 | static int mlx4_init_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1539 | { |
1540 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1541 | struct mlx4_adapter adapter; | |
1542 | struct mlx4_dev_cap dev_cap; | |
2d928651 | 1543 | struct mlx4_mod_stat_cfg mlx4_cfg; |
225c7b1f RD |
1544 | struct mlx4_profile profile; |
1545 | struct mlx4_init_hca_param init_hca; | |
1546 | u64 icm_size; | |
1547 | int err; | |
1548 | ||
ab9c17a0 JM |
1549 | if (!mlx4_is_slave(dev)) { |
1550 | err = mlx4_QUERY_FW(dev); | |
1551 | if (err) { | |
1552 | if (err == -EACCES) | |
1a91de28 | 1553 | mlx4_info(dev, "non-primary physical function, skipping\n"); |
ab9c17a0 | 1554 | else |
1a91de28 | 1555 | mlx4_err(dev, "QUERY_FW command failed, aborting\n"); |
bef772eb | 1556 | return err; |
ab9c17a0 | 1557 | } |
225c7b1f | 1558 | |
ab9c17a0 JM |
1559 | err = mlx4_load_fw(dev); |
1560 | if (err) { | |
1a91de28 | 1561 | mlx4_err(dev, "Failed to start FW, aborting\n"); |
bef772eb | 1562 | return err; |
ab9c17a0 | 1563 | } |
225c7b1f | 1564 | |
ab9c17a0 JM |
1565 | mlx4_cfg.log_pg_sz_m = 1; |
1566 | mlx4_cfg.log_pg_sz = 0; | |
1567 | err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg); | |
1568 | if (err) | |
1569 | mlx4_warn(dev, "Failed to override log_pg_sz parameter\n"); | |
2d928651 | 1570 | |
ab9c17a0 JM |
1571 | err = mlx4_dev_cap(dev, &dev_cap); |
1572 | if (err) { | |
1a91de28 | 1573 | mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n"); |
ab9c17a0 JM |
1574 | goto err_stop_fw; |
1575 | } | |
225c7b1f | 1576 | |
7b8157be | 1577 | choose_steering_mode(dev, &dev_cap); |
7ffdf726 | 1578 | choose_tunnel_offload_mode(dev, &dev_cap); |
7b8157be | 1579 | |
8e1a28e8 HHZ |
1580 | err = mlx4_get_phys_port_id(dev); |
1581 | if (err) | |
1582 | mlx4_err(dev, "Fail to get physical port id\n"); | |
1583 | ||
6634961c JM |
1584 | if (mlx4_is_master(dev)) |
1585 | mlx4_parav_master_pf_caps(dev); | |
1586 | ||
ab9c17a0 | 1587 | profile = default_profile; |
0ff1fb65 HHZ |
1588 | if (dev->caps.steering_mode == |
1589 | MLX4_STEERING_MODE_DEVICE_MANAGED) | |
1590 | profile.num_mcg = MLX4_FS_NUM_MCG; | |
225c7b1f | 1591 | |
ab9c17a0 JM |
1592 | icm_size = mlx4_make_profile(dev, &profile, &dev_cap, |
1593 | &init_hca); | |
1594 | if ((long long) icm_size < 0) { | |
1595 | err = icm_size; | |
1596 | goto err_stop_fw; | |
1597 | } | |
225c7b1f | 1598 | |
a5bbe892 EC |
1599 | dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1; |
1600 | ||
ab9c17a0 JM |
1601 | init_hca.log_uar_sz = ilog2(dev->caps.num_uars); |
1602 | init_hca.uar_page_sz = PAGE_SHIFT - 12; | |
e448834e SM |
1603 | init_hca.mw_enabled = 0; |
1604 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW || | |
1605 | dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) | |
1606 | init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE; | |
c1b43dca | 1607 | |
ab9c17a0 JM |
1608 | err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size); |
1609 | if (err) | |
1610 | goto err_stop_fw; | |
225c7b1f | 1611 | |
ab9c17a0 JM |
1612 | err = mlx4_INIT_HCA(dev, &init_hca); |
1613 | if (err) { | |
1a91de28 | 1614 | mlx4_err(dev, "INIT_HCA command failed, aborting\n"); |
ab9c17a0 JM |
1615 | goto err_free_icm; |
1616 | } | |
ddd8a6c1 EE |
1617 | /* |
1618 | * If TS is supported by FW | |
1619 | * read HCA frequency by QUERY_HCA command | |
1620 | */ | |
1621 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) { | |
1622 | memset(&init_hca, 0, sizeof(init_hca)); | |
1623 | err = mlx4_QUERY_HCA(dev, &init_hca); | |
1624 | if (err) { | |
1a91de28 | 1625 | mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n"); |
ddd8a6c1 EE |
1626 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; |
1627 | } else { | |
1628 | dev->caps.hca_core_clock = | |
1629 | init_hca.hca_core_clock; | |
1630 | } | |
1631 | ||
1632 | /* In case we got HCA frequency 0 - disable timestamping | |
1633 | * to avoid dividing by zero | |
1634 | */ | |
1635 | if (!dev->caps.hca_core_clock) { | |
1636 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1637 | mlx4_err(dev, | |
1a91de28 | 1638 | "HCA frequency is 0 - timestamping is not supported\n"); |
ddd8a6c1 EE |
1639 | } else if (map_internal_clock(dev)) { |
1640 | /* | |
1641 | * Map internal clock, | |
1642 | * in case of failure disable timestamping | |
1643 | */ | |
1644 | dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS; | |
1a91de28 | 1645 | mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n"); |
ddd8a6c1 EE |
1646 | } |
1647 | } | |
ab9c17a0 JM |
1648 | } else { |
1649 | err = mlx4_init_slave(dev); | |
1650 | if (err) { | |
5efe5355 JM |
1651 | if (err != -EPROBE_DEFER) |
1652 | mlx4_err(dev, "Failed to initialize slave\n"); | |
bef772eb | 1653 | return err; |
ab9c17a0 | 1654 | } |
225c7b1f | 1655 | |
ab9c17a0 JM |
1656 | err = mlx4_slave_cap(dev); |
1657 | if (err) { | |
1658 | mlx4_err(dev, "Failed to obtain slave caps\n"); | |
1659 | goto err_close; | |
1660 | } | |
225c7b1f RD |
1661 | } |
1662 | ||
ab9c17a0 JM |
1663 | if (map_bf_area(dev)) |
1664 | mlx4_dbg(dev, "Failed to map blue flame area\n"); | |
1665 | ||
1666 | /*Only the master set the ports, all the rest got it from it.*/ | |
1667 | if (!mlx4_is_slave(dev)) | |
1668 | mlx4_set_port_mask(dev); | |
1669 | ||
225c7b1f RD |
1670 | err = mlx4_QUERY_ADAPTER(dev, &adapter); |
1671 | if (err) { | |
1a91de28 | 1672 | mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n"); |
bef772eb | 1673 | goto unmap_bf; |
225c7b1f RD |
1674 | } |
1675 | ||
1676 | priv->eq_table.inta_pin = adapter.inta_pin; | |
cd9281d8 | 1677 | memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id); |
225c7b1f RD |
1678 | |
1679 | return 0; | |
1680 | ||
bef772eb | 1681 | unmap_bf: |
ddd8a6c1 | 1682 | unmap_internal_clock(dev); |
bef772eb AY |
1683 | unmap_bf_area(dev); |
1684 | ||
225c7b1f | 1685 | err_close: |
41929ed2 DB |
1686 | if (mlx4_is_slave(dev)) |
1687 | mlx4_slave_exit(dev); | |
1688 | else | |
1689 | mlx4_CLOSE_HCA(dev, 0); | |
225c7b1f RD |
1690 | |
1691 | err_free_icm: | |
ab9c17a0 JM |
1692 | if (!mlx4_is_slave(dev)) |
1693 | mlx4_free_icms(dev); | |
225c7b1f RD |
1694 | |
1695 | err_stop_fw: | |
ab9c17a0 JM |
1696 | if (!mlx4_is_slave(dev)) { |
1697 | mlx4_UNMAP_FA(dev); | |
1698 | mlx4_free_icm(dev, priv->fw.fw_icm, 0); | |
1699 | } | |
225c7b1f RD |
1700 | return err; |
1701 | } | |
1702 | ||
f2a3f6a3 OG |
1703 | static int mlx4_init_counters_table(struct mlx4_dev *dev) |
1704 | { | |
1705 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1706 | int nent; | |
1707 | ||
1708 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1709 | return -ENOENT; | |
1710 | ||
1711 | nent = dev->caps.max_counters; | |
1712 | return mlx4_bitmap_init(&priv->counters_bitmap, nent, nent - 1, 0, 0); | |
1713 | } | |
1714 | ||
1715 | static void mlx4_cleanup_counters_table(struct mlx4_dev *dev) | |
1716 | { | |
1717 | mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap); | |
1718 | } | |
1719 | ||
ba062d52 | 1720 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) |
f2a3f6a3 OG |
1721 | { |
1722 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1723 | ||
1724 | if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS)) | |
1725 | return -ENOENT; | |
1726 | ||
1727 | *idx = mlx4_bitmap_alloc(&priv->counters_bitmap); | |
1728 | if (*idx == -1) | |
1729 | return -ENOMEM; | |
1730 | ||
1731 | return 0; | |
1732 | } | |
ba062d52 JM |
1733 | |
1734 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx) | |
1735 | { | |
1736 | u64 out_param; | |
1737 | int err; | |
1738 | ||
1739 | if (mlx4_is_mfunc(dev)) { | |
1740 | err = mlx4_cmd_imm(dev, 0, &out_param, RES_COUNTER, | |
1741 | RES_OP_RESERVE, MLX4_CMD_ALLOC_RES, | |
1742 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); | |
1743 | if (!err) | |
1744 | *idx = get_param_l(&out_param); | |
1745 | ||
1746 | return err; | |
1747 | } | |
1748 | return __mlx4_counter_alloc(dev, idx); | |
1749 | } | |
f2a3f6a3 OG |
1750 | EXPORT_SYMBOL_GPL(mlx4_counter_alloc); |
1751 | ||
ba062d52 | 1752 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx) |
f2a3f6a3 | 1753 | { |
7c6d74d2 | 1754 | mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR); |
f2a3f6a3 OG |
1755 | return; |
1756 | } | |
ba062d52 JM |
1757 | |
1758 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx) | |
1759 | { | |
e7dbeba8 | 1760 | u64 in_param = 0; |
ba062d52 JM |
1761 | |
1762 | if (mlx4_is_mfunc(dev)) { | |
1763 | set_param_l(&in_param, idx); | |
1764 | mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE, | |
1765 | MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A, | |
1766 | MLX4_CMD_WRAPPED); | |
1767 | return; | |
1768 | } | |
1769 | __mlx4_counter_free(dev, idx); | |
1770 | } | |
f2a3f6a3 OG |
1771 | EXPORT_SYMBOL_GPL(mlx4_counter_free); |
1772 | ||
3d73c288 | 1773 | static int mlx4_setup_hca(struct mlx4_dev *dev) |
225c7b1f RD |
1774 | { |
1775 | struct mlx4_priv *priv = mlx4_priv(dev); | |
1776 | int err; | |
7ff93f8b | 1777 | int port; |
9a5aa622 | 1778 | __be32 ib_port_default_caps; |
225c7b1f | 1779 | |
225c7b1f RD |
1780 | err = mlx4_init_uar_table(dev); |
1781 | if (err) { | |
1a91de28 JP |
1782 | mlx4_err(dev, "Failed to initialize user access region table, aborting\n"); |
1783 | return err; | |
225c7b1f RD |
1784 | } |
1785 | ||
1786 | err = mlx4_uar_alloc(dev, &priv->driver_uar); | |
1787 | if (err) { | |
1a91de28 | 1788 | mlx4_err(dev, "Failed to allocate driver access region, aborting\n"); |
225c7b1f RD |
1789 | goto err_uar_table_free; |
1790 | } | |
1791 | ||
4979d18f | 1792 | priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); |
225c7b1f | 1793 | if (!priv->kar) { |
1a91de28 | 1794 | mlx4_err(dev, "Couldn't map kernel access region, aborting\n"); |
225c7b1f RD |
1795 | err = -ENOMEM; |
1796 | goto err_uar_free; | |
1797 | } | |
1798 | ||
1799 | err = mlx4_init_pd_table(dev); | |
1800 | if (err) { | |
1a91de28 | 1801 | mlx4_err(dev, "Failed to initialize protection domain table, aborting\n"); |
225c7b1f RD |
1802 | goto err_kar_unmap; |
1803 | } | |
1804 | ||
012a8ff5 SH |
1805 | err = mlx4_init_xrcd_table(dev); |
1806 | if (err) { | |
1a91de28 | 1807 | mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n"); |
012a8ff5 SH |
1808 | goto err_pd_table_free; |
1809 | } | |
1810 | ||
225c7b1f RD |
1811 | err = mlx4_init_mr_table(dev); |
1812 | if (err) { | |
1a91de28 | 1813 | mlx4_err(dev, "Failed to initialize memory region table, aborting\n"); |
012a8ff5 | 1814 | goto err_xrcd_table_free; |
225c7b1f RD |
1815 | } |
1816 | ||
fe6f700d YP |
1817 | if (!mlx4_is_slave(dev)) { |
1818 | err = mlx4_init_mcg_table(dev); | |
1819 | if (err) { | |
1a91de28 | 1820 | mlx4_err(dev, "Failed to initialize multicast group table, aborting\n"); |
fe6f700d YP |
1821 | goto err_mr_table_free; |
1822 | } | |
1823 | } | |
1824 | ||
225c7b1f RD |
1825 | err = mlx4_init_eq_table(dev); |
1826 | if (err) { | |
1a91de28 | 1827 | mlx4_err(dev, "Failed to initialize event queue table, aborting\n"); |
fe6f700d | 1828 | goto err_mcg_table_free; |
225c7b1f RD |
1829 | } |
1830 | ||
1831 | err = mlx4_cmd_use_events(dev); | |
1832 | if (err) { | |
1a91de28 | 1833 | mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n"); |
225c7b1f RD |
1834 | goto err_eq_table_free; |
1835 | } | |
1836 | ||
1837 | err = mlx4_NOP(dev); | |
1838 | if (err) { | |
08fb1055 | 1839 | if (dev->flags & MLX4_FLAG_MSI_X) { |
1a91de28 | 1840 | mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n", |
b8dd786f | 1841 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
1a91de28 | 1842 | mlx4_warn(dev, "Trying again without MSI-X\n"); |
08fb1055 | 1843 | } else { |
1a91de28 | 1844 | mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n", |
b8dd786f | 1845 | priv->eq_table.eq[dev->caps.num_comp_vectors].irq); |
225c7b1f | 1846 | mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n"); |
08fb1055 | 1847 | } |
225c7b1f RD |
1848 | |
1849 | goto err_cmd_poll; | |
1850 | } | |
1851 | ||
1852 | mlx4_dbg(dev, "NOP command IRQ test passed\n"); | |
1853 | ||
1854 | err = mlx4_init_cq_table(dev); | |
1855 | if (err) { | |
1a91de28 | 1856 | mlx4_err(dev, "Failed to initialize completion queue table, aborting\n"); |
225c7b1f RD |
1857 | goto err_cmd_poll; |
1858 | } | |
1859 | ||
1860 | err = mlx4_init_srq_table(dev); | |
1861 | if (err) { | |
1a91de28 | 1862 | mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n"); |
225c7b1f RD |
1863 | goto err_cq_table_free; |
1864 | } | |
1865 | ||
1866 | err = mlx4_init_qp_table(dev); | |
1867 | if (err) { | |
1a91de28 | 1868 | mlx4_err(dev, "Failed to initialize queue pair table, aborting\n"); |
225c7b1f RD |
1869 | goto err_srq_table_free; |
1870 | } | |
1871 | ||
f2a3f6a3 OG |
1872 | err = mlx4_init_counters_table(dev); |
1873 | if (err && err != -ENOENT) { | |
1a91de28 | 1874 | mlx4_err(dev, "Failed to initialize counters table, aborting\n"); |
fe6f700d | 1875 | goto err_qp_table_free; |
f2a3f6a3 OG |
1876 | } |
1877 | ||
ab9c17a0 JM |
1878 | if (!mlx4_is_slave(dev)) { |
1879 | for (port = 1; port <= dev->caps.num_ports; port++) { | |
ab9c17a0 JM |
1880 | ib_port_default_caps = 0; |
1881 | err = mlx4_get_port_ib_caps(dev, port, | |
1882 | &ib_port_default_caps); | |
1883 | if (err) | |
1a91de28 JP |
1884 | mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n", |
1885 | port, err); | |
ab9c17a0 JM |
1886 | dev->caps.ib_port_def_cap[port] = ib_port_default_caps; |
1887 | ||
2aca1172 JM |
1888 | /* initialize per-slave default ib port capabilities */ |
1889 | if (mlx4_is_master(dev)) { | |
1890 | int i; | |
1891 | for (i = 0; i < dev->num_slaves; i++) { | |
1892 | if (i == mlx4_master_func_num(dev)) | |
1893 | continue; | |
1894 | priv->mfunc.master.slave_state[i].ib_cap_mask[port] = | |
1a91de28 | 1895 | ib_port_default_caps; |
2aca1172 JM |
1896 | } |
1897 | } | |
1898 | ||
096335b3 OG |
1899 | if (mlx4_is_mfunc(dev)) |
1900 | dev->caps.port_ib_mtu[port] = IB_MTU_2048; | |
1901 | else | |
1902 | dev->caps.port_ib_mtu[port] = IB_MTU_4096; | |
97285b78 | 1903 | |
6634961c JM |
1904 | err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ? |
1905 | dev->caps.pkey_table_len[port] : -1); | |
ab9c17a0 JM |
1906 | if (err) { |
1907 | mlx4_err(dev, "Failed to set port %d, aborting\n", | |
1a91de28 | 1908 | port); |
ab9c17a0 JM |
1909 | goto err_counters_table_free; |
1910 | } | |
7ff93f8b YP |
1911 | } |
1912 | } | |
1913 | ||
225c7b1f RD |
1914 | return 0; |
1915 | ||
f2a3f6a3 OG |
1916 | err_counters_table_free: |
1917 | mlx4_cleanup_counters_table(dev); | |
1918 | ||
225c7b1f RD |
1919 | err_qp_table_free: |
1920 | mlx4_cleanup_qp_table(dev); | |
1921 | ||
1922 | err_srq_table_free: | |
1923 | mlx4_cleanup_srq_table(dev); | |
1924 | ||
1925 | err_cq_table_free: | |
1926 | mlx4_cleanup_cq_table(dev); | |
1927 | ||
1928 | err_cmd_poll: | |
1929 | mlx4_cmd_use_polling(dev); | |
1930 | ||
1931 | err_eq_table_free: | |
1932 | mlx4_cleanup_eq_table(dev); | |
1933 | ||
fe6f700d YP |
1934 | err_mcg_table_free: |
1935 | if (!mlx4_is_slave(dev)) | |
1936 | mlx4_cleanup_mcg_table(dev); | |
1937 | ||
ee49bd93 | 1938 | err_mr_table_free: |
225c7b1f RD |
1939 | mlx4_cleanup_mr_table(dev); |
1940 | ||
012a8ff5 SH |
1941 | err_xrcd_table_free: |
1942 | mlx4_cleanup_xrcd_table(dev); | |
1943 | ||
225c7b1f RD |
1944 | err_pd_table_free: |
1945 | mlx4_cleanup_pd_table(dev); | |
1946 | ||
1947 | err_kar_unmap: | |
1948 | iounmap(priv->kar); | |
1949 | ||
1950 | err_uar_free: | |
1951 | mlx4_uar_free(dev, &priv->driver_uar); | |
1952 | ||
1953 | err_uar_table_free: | |
1954 | mlx4_cleanup_uar_table(dev); | |
1955 | return err; | |
1956 | } | |
1957 | ||
e8f9b2ed | 1958 | static void mlx4_enable_msi_x(struct mlx4_dev *dev) |
225c7b1f RD |
1959 | { |
1960 | struct mlx4_priv *priv = mlx4_priv(dev); | |
b8dd786f | 1961 | struct msix_entry *entries; |
0b7ca5a9 | 1962 | int nreq = min_t(int, dev->caps.num_ports * |
bb2146bc | 1963 | min_t(int, num_online_cpus() + 1, |
90b1ebe7 | 1964 | MAX_MSIX_P_PORT) + MSIX_LEGACY_SZ, MAX_MSIX); |
225c7b1f RD |
1965 | int i; |
1966 | ||
1967 | if (msi_x) { | |
ca4c7b35 OG |
1968 | nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs, |
1969 | nreq); | |
ab9c17a0 | 1970 | |
b8dd786f YP |
1971 | entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL); |
1972 | if (!entries) | |
1973 | goto no_msi; | |
1974 | ||
1975 | for (i = 0; i < nreq; ++i) | |
225c7b1f RD |
1976 | entries[i].entry = i; |
1977 | ||
66e2f9c1 AG |
1978 | nreq = pci_enable_msix_range(dev->pdev, entries, 2, nreq); |
1979 | ||
1980 | if (nreq < 0) { | |
5bf0da7d | 1981 | kfree(entries); |
225c7b1f | 1982 | goto no_msi; |
66e2f9c1 | 1983 | } else if (nreq < MSIX_LEGACY_SZ + |
1a91de28 | 1984 | dev->caps.num_ports * MIN_MSIX_P_PORT) { |
0b7ca5a9 YP |
1985 | /*Working in legacy mode , all EQ's shared*/ |
1986 | dev->caps.comp_pool = 0; | |
1987 | dev->caps.num_comp_vectors = nreq - 1; | |
1988 | } else { | |
1989 | dev->caps.comp_pool = nreq - MSIX_LEGACY_SZ; | |
1990 | dev->caps.num_comp_vectors = MSIX_LEGACY_SZ - 1; | |
1991 | } | |
b8dd786f | 1992 | for (i = 0; i < nreq; ++i) |
225c7b1f RD |
1993 | priv->eq_table.eq[i].irq = entries[i].vector; |
1994 | ||
1995 | dev->flags |= MLX4_FLAG_MSI_X; | |
b8dd786f YP |
1996 | |
1997 | kfree(entries); | |
225c7b1f RD |
1998 | return; |
1999 | } | |
2000 | ||
2001 | no_msi: | |
b8dd786f | 2002 | dev->caps.num_comp_vectors = 1; |
0b7ca5a9 | 2003 | dev->caps.comp_pool = 0; |
b8dd786f YP |
2004 | |
2005 | for (i = 0; i < 2; ++i) | |
225c7b1f RD |
2006 | priv->eq_table.eq[i].irq = dev->pdev->irq; |
2007 | } | |
2008 | ||
7ff93f8b | 2009 | static int mlx4_init_port_info(struct mlx4_dev *dev, int port) |
2a2336f8 YP |
2010 | { |
2011 | struct mlx4_port_info *info = &mlx4_priv(dev)->port[port]; | |
7ff93f8b | 2012 | int err = 0; |
2a2336f8 YP |
2013 | |
2014 | info->dev = dev; | |
2015 | info->port = port; | |
ab9c17a0 | 2016 | if (!mlx4_is_slave(dev)) { |
ab9c17a0 JM |
2017 | mlx4_init_mac_table(dev, &info->mac_table); |
2018 | mlx4_init_vlan_table(dev, &info->vlan_table); | |
16a10ffd | 2019 | info->base_qpn = mlx4_get_base_qpn(dev, port); |
ab9c17a0 | 2020 | } |
7ff93f8b YP |
2021 | |
2022 | sprintf(info->dev_name, "mlx4_port%d", port); | |
2023 | info->port_attr.attr.name = info->dev_name; | |
ab9c17a0 JM |
2024 | if (mlx4_is_mfunc(dev)) |
2025 | info->port_attr.attr.mode = S_IRUGO; | |
2026 | else { | |
2027 | info->port_attr.attr.mode = S_IRUGO | S_IWUSR; | |
2028 | info->port_attr.store = set_port_type; | |
2029 | } | |
7ff93f8b | 2030 | info->port_attr.show = show_port_type; |
3691c964 | 2031 | sysfs_attr_init(&info->port_attr.attr); |
7ff93f8b YP |
2032 | |
2033 | err = device_create_file(&dev->pdev->dev, &info->port_attr); | |
2034 | if (err) { | |
2035 | mlx4_err(dev, "Failed to create file for port %d\n", port); | |
2036 | info->port = -1; | |
2037 | } | |
2038 | ||
096335b3 OG |
2039 | sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port); |
2040 | info->port_mtu_attr.attr.name = info->dev_mtu_name; | |
2041 | if (mlx4_is_mfunc(dev)) | |
2042 | info->port_mtu_attr.attr.mode = S_IRUGO; | |
2043 | else { | |
2044 | info->port_mtu_attr.attr.mode = S_IRUGO | S_IWUSR; | |
2045 | info->port_mtu_attr.store = set_port_ib_mtu; | |
2046 | } | |
2047 | info->port_mtu_attr.show = show_port_ib_mtu; | |
2048 | sysfs_attr_init(&info->port_mtu_attr.attr); | |
2049 | ||
2050 | err = device_create_file(&dev->pdev->dev, &info->port_mtu_attr); | |
2051 | if (err) { | |
2052 | mlx4_err(dev, "Failed to create mtu file for port %d\n", port); | |
2053 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
2054 | info->port = -1; | |
2055 | } | |
2056 | ||
7ff93f8b YP |
2057 | return err; |
2058 | } | |
2059 | ||
2060 | static void mlx4_cleanup_port_info(struct mlx4_port_info *info) | |
2061 | { | |
2062 | if (info->port < 0) | |
2063 | return; | |
2064 | ||
2065 | device_remove_file(&info->dev->pdev->dev, &info->port_attr); | |
096335b3 | 2066 | device_remove_file(&info->dev->pdev->dev, &info->port_mtu_attr); |
2a2336f8 YP |
2067 | } |
2068 | ||
b12d93d6 YP |
2069 | static int mlx4_init_steering(struct mlx4_dev *dev) |
2070 | { | |
2071 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2072 | int num_entries = dev->caps.num_ports; | |
2073 | int i, j; | |
2074 | ||
2075 | priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL); | |
2076 | if (!priv->steer) | |
2077 | return -ENOMEM; | |
2078 | ||
45b51365 | 2079 | for (i = 0; i < num_entries; i++) |
b12d93d6 YP |
2080 | for (j = 0; j < MLX4_NUM_STEERS; j++) { |
2081 | INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]); | |
2082 | INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]); | |
2083 | } | |
b12d93d6 YP |
2084 | return 0; |
2085 | } | |
2086 | ||
2087 | static void mlx4_clear_steering(struct mlx4_dev *dev) | |
2088 | { | |
2089 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2090 | struct mlx4_steer_index *entry, *tmp_entry; | |
2091 | struct mlx4_promisc_qp *pqp, *tmp_pqp; | |
2092 | int num_entries = dev->caps.num_ports; | |
2093 | int i, j; | |
2094 | ||
2095 | for (i = 0; i < num_entries; i++) { | |
2096 | for (j = 0; j < MLX4_NUM_STEERS; j++) { | |
2097 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2098 | &priv->steer[i].promisc_qps[j], | |
2099 | list) { | |
2100 | list_del(&pqp->list); | |
2101 | kfree(pqp); | |
2102 | } | |
2103 | list_for_each_entry_safe(entry, tmp_entry, | |
2104 | &priv->steer[i].steer_entries[j], | |
2105 | list) { | |
2106 | list_del(&entry->list); | |
2107 | list_for_each_entry_safe(pqp, tmp_pqp, | |
2108 | &entry->duplicates, | |
2109 | list) { | |
2110 | list_del(&pqp->list); | |
2111 | kfree(pqp); | |
2112 | } | |
2113 | kfree(entry); | |
2114 | } | |
2115 | } | |
2116 | } | |
2117 | kfree(priv->steer); | |
2118 | } | |
2119 | ||
ab9c17a0 JM |
2120 | static int extended_func_num(struct pci_dev *pdev) |
2121 | { | |
2122 | return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn); | |
2123 | } | |
2124 | ||
2125 | #define MLX4_OWNER_BASE 0x8069c | |
2126 | #define MLX4_OWNER_SIZE 4 | |
2127 | ||
2128 | static int mlx4_get_ownership(struct mlx4_dev *dev) | |
2129 | { | |
2130 | void __iomem *owner; | |
2131 | u32 ret; | |
2132 | ||
57dbf29a KSS |
2133 | if (pci_channel_offline(dev->pdev)) |
2134 | return -EIO; | |
2135 | ||
ab9c17a0 JM |
2136 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2137 | MLX4_OWNER_SIZE); | |
2138 | if (!owner) { | |
2139 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2140 | return -ENOMEM; | |
2141 | } | |
2142 | ||
2143 | ret = readl(owner); | |
2144 | iounmap(owner); | |
2145 | return (int) !!ret; | |
2146 | } | |
2147 | ||
2148 | static void mlx4_free_ownership(struct mlx4_dev *dev) | |
2149 | { | |
2150 | void __iomem *owner; | |
2151 | ||
57dbf29a KSS |
2152 | if (pci_channel_offline(dev->pdev)) |
2153 | return; | |
2154 | ||
ab9c17a0 JM |
2155 | owner = ioremap(pci_resource_start(dev->pdev, 0) + MLX4_OWNER_BASE, |
2156 | MLX4_OWNER_SIZE); | |
2157 | if (!owner) { | |
2158 | mlx4_err(dev, "Failed to obtain ownership bit\n"); | |
2159 | return; | |
2160 | } | |
2161 | writel(0, owner); | |
2162 | msleep(1000); | |
2163 | iounmap(owner); | |
2164 | } | |
2165 | ||
839f1243 | 2166 | static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data) |
225c7b1f | 2167 | { |
225c7b1f RD |
2168 | struct mlx4_priv *priv; |
2169 | struct mlx4_dev *dev; | |
2170 | int err; | |
2a2336f8 | 2171 | int port; |
dd41cc3b MB |
2172 | int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0}; |
2173 | int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0}; | |
2174 | const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = { | |
2175 | {2, 0, 0}, {0, 1, 2}, {0, 1, 2} }; | |
1ab95d37 MB |
2176 | unsigned total_vfs = 0; |
2177 | int sriov_initialized = 0; | |
2178 | unsigned int i; | |
225c7b1f | 2179 | |
0a645e80 | 2180 | pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev)); |
225c7b1f RD |
2181 | |
2182 | err = pci_enable_device(pdev); | |
2183 | if (err) { | |
1a91de28 | 2184 | dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); |
225c7b1f RD |
2185 | return err; |
2186 | } | |
5a0d0a61 JM |
2187 | |
2188 | /* Due to requirement that all VFs and the PF are *guaranteed* 2 MACS | |
2189 | * per port, we must limit the number of VFs to 63 (since their are | |
2190 | * 128 MACs) | |
2191 | */ | |
dd41cc3b MB |
2192 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && i < num_vfs_argc; |
2193 | total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) { | |
2194 | nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i]; | |
1ab95d37 MB |
2195 | if (nvfs[i] < 0) { |
2196 | dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n"); | |
2197 | return -EINVAL; | |
2198 | } | |
2199 | } | |
dd41cc3b MB |
2200 | for (i = 0; i < sizeof(prb_vf)/sizeof(prb_vf[0]) && i < probe_vfs_argc; |
2201 | i++) { | |
2202 | prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i]; | |
1ab95d37 MB |
2203 | if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) { |
2204 | dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n"); | |
2205 | return -EINVAL; | |
2206 | } | |
2207 | } | |
2208 | if (total_vfs >= MLX4_MAX_NUM_VF) { | |
5a0d0a61 JM |
2209 | dev_err(&pdev->dev, |
2210 | "Requested more VF's (%d) than allowed (%d)\n", | |
1ab95d37 | 2211 | total_vfs, MLX4_MAX_NUM_VF - 1); |
ab9c17a0 JM |
2212 | return -EINVAL; |
2213 | } | |
30e514a7 | 2214 | |
1ab95d37 MB |
2215 | for (i = 0; i < MLX4_MAX_PORTS; i++) { |
2216 | if (nvfs[i] + nvfs[2] >= MLX4_MAX_NUM_VF_P_PORT) { | |
2217 | dev_err(&pdev->dev, | |
2218 | "Requested more VF's (%d) for port (%d) than allowed (%d)\n", | |
2219 | nvfs[i] + nvfs[2], i + 1, | |
2220 | MLX4_MAX_NUM_VF_P_PORT - 1); | |
2221 | return -EINVAL; | |
2222 | } | |
30e514a7 | 2223 | } |
1ab95d37 MB |
2224 | |
2225 | ||
225c7b1f | 2226 | /* |
ab9c17a0 | 2227 | * Check for BARs. |
225c7b1f | 2228 | */ |
839f1243 | 2229 | if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) && |
ab9c17a0 | 2230 | !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { |
1a91de28 | 2231 | dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n", |
839f1243 | 2232 | pci_dev_data, pci_resource_flags(pdev, 0)); |
225c7b1f RD |
2233 | err = -ENODEV; |
2234 | goto err_disable_pdev; | |
2235 | } | |
2236 | if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { | |
1a91de28 | 2237 | dev_err(&pdev->dev, "Missing UAR, aborting\n"); |
225c7b1f RD |
2238 | err = -ENODEV; |
2239 | goto err_disable_pdev; | |
2240 | } | |
2241 | ||
a01df0fe | 2242 | err = pci_request_regions(pdev, DRV_NAME); |
225c7b1f | 2243 | if (err) { |
a01df0fe | 2244 | dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n"); |
225c7b1f RD |
2245 | goto err_disable_pdev; |
2246 | } | |
2247 | ||
225c7b1f RD |
2248 | pci_set_master(pdev); |
2249 | ||
6a35528a | 2250 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f | 2251 | if (err) { |
1a91de28 | 2252 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n"); |
284901a9 | 2253 | err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f | 2254 | if (err) { |
1a91de28 | 2255 | dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n"); |
a01df0fe | 2256 | goto err_release_regions; |
225c7b1f RD |
2257 | } |
2258 | } | |
6a35528a | 2259 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); |
225c7b1f | 2260 | if (err) { |
1a91de28 | 2261 | dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n"); |
284901a9 | 2262 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); |
225c7b1f | 2263 | if (err) { |
1a91de28 | 2264 | dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n"); |
a01df0fe | 2265 | goto err_release_regions; |
225c7b1f RD |
2266 | } |
2267 | } | |
2268 | ||
7f9e5c48 DD |
2269 | /* Allow large DMA segments, up to the firmware limit of 1 GB */ |
2270 | dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); | |
2271 | ||
befdf897 WY |
2272 | dev = pci_get_drvdata(pdev); |
2273 | priv = mlx4_priv(dev); | |
225c7b1f | 2274 | dev->pdev = pdev; |
b581401e RD |
2275 | INIT_LIST_HEAD(&priv->ctx_list); |
2276 | spin_lock_init(&priv->ctx_lock); | |
225c7b1f | 2277 | |
7ff93f8b YP |
2278 | mutex_init(&priv->port_mutex); |
2279 | ||
6296883c YP |
2280 | INIT_LIST_HEAD(&priv->pgdir_list); |
2281 | mutex_init(&priv->pgdir_mutex); | |
2282 | ||
c1b43dca EC |
2283 | INIT_LIST_HEAD(&priv->bf_list); |
2284 | mutex_init(&priv->bf_mutex); | |
2285 | ||
aca7a3ac | 2286 | dev->rev_id = pdev->revision; |
6e7136ed | 2287 | dev->numa_node = dev_to_node(&pdev->dev); |
ab9c17a0 | 2288 | /* Detect if this device is a virtual function */ |
839f1243 | 2289 | if (pci_dev_data & MLX4_PCI_DEV_IS_VF) { |
ab9c17a0 JM |
2290 | /* When acting as pf, we normally skip vfs unless explicitly |
2291 | * requested to probe them. */ | |
1ab95d37 MB |
2292 | if (total_vfs) { |
2293 | unsigned vfs_offset = 0; | |
2294 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]) && | |
1a91de28 | 2295 | vfs_offset + nvfs[i] < extended_func_num(pdev); |
1ab95d37 MB |
2296 | vfs_offset += nvfs[i], i++) |
2297 | ; | |
2298 | if (i == sizeof(nvfs)/sizeof(nvfs[0])) { | |
2299 | err = -ENODEV; | |
2300 | goto err_free_dev; | |
2301 | } | |
2302 | if ((extended_func_num(pdev) - vfs_offset) | |
2303 | > prb_vf[i]) { | |
2304 | mlx4_warn(dev, "Skipping virtual function:%d\n", | |
2305 | extended_func_num(pdev)); | |
2306 | err = -ENODEV; | |
2307 | goto err_free_dev; | |
2308 | } | |
ab9c17a0 JM |
2309 | } |
2310 | mlx4_warn(dev, "Detected virtual function - running in slave mode\n"); | |
2311 | dev->flags |= MLX4_FLAG_SLAVE; | |
2312 | } else { | |
2313 | /* We reset the device and enable SRIOV only for physical | |
2314 | * devices. Try to claim ownership on the device; | |
2315 | * if already taken, skip -- do not allow multiple PFs */ | |
2316 | err = mlx4_get_ownership(dev); | |
2317 | if (err) { | |
2318 | if (err < 0) | |
2319 | goto err_free_dev; | |
2320 | else { | |
1a91de28 | 2321 | mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n"); |
ab9c17a0 JM |
2322 | err = -EINVAL; |
2323 | goto err_free_dev; | |
2324 | } | |
2325 | } | |
aca7a3ac | 2326 | |
1ab95d37 MB |
2327 | if (total_vfs) { |
2328 | mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", | |
2329 | total_vfs); | |
2330 | dev->dev_vfs = kzalloc( | |
1a91de28 JP |
2331 | total_vfs * sizeof(*dev->dev_vfs), |
2332 | GFP_KERNEL); | |
1ab95d37 MB |
2333 | if (NULL == dev->dev_vfs) { |
2334 | mlx4_err(dev, "Failed to allocate memory for VFs\n"); | |
ab9c17a0 JM |
2335 | err = 0; |
2336 | } else { | |
1ab95d37 MB |
2337 | atomic_inc(&pf_loading); |
2338 | err = pci_enable_sriov(pdev, total_vfs); | |
1ab95d37 | 2339 | if (err) { |
1a91de28 | 2340 | mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n", |
1ab95d37 | 2341 | err); |
e1a5ddc5 | 2342 | atomic_dec(&pf_loading); |
1ab95d37 MB |
2343 | err = 0; |
2344 | } else { | |
2345 | mlx4_warn(dev, "Running in master mode\n"); | |
2346 | dev->flags |= MLX4_FLAG_SRIOV | | |
1a91de28 | 2347 | MLX4_FLAG_MASTER; |
1ab95d37 MB |
2348 | dev->num_vfs = total_vfs; |
2349 | sriov_initialized = 1; | |
2350 | } | |
ab9c17a0 JM |
2351 | } |
2352 | } | |
2353 | ||
fe6f700d YP |
2354 | atomic_set(&priv->opreq_count, 0); |
2355 | INIT_WORK(&priv->opreq_task, mlx4_opreq_action); | |
2356 | ||
ab9c17a0 JM |
2357 | /* |
2358 | * Now reset the HCA before we touch the PCI capabilities or | |
2359 | * attempt a firmware command, since a boot ROM may have left | |
2360 | * the HCA in an undefined state. | |
2361 | */ | |
2362 | err = mlx4_reset(dev); | |
2363 | if (err) { | |
1a91de28 | 2364 | mlx4_err(dev, "Failed to reset HCA, aborting\n"); |
ab9c17a0 JM |
2365 | goto err_rel_own; |
2366 | } | |
225c7b1f RD |
2367 | } |
2368 | ||
ab9c17a0 | 2369 | slave_start: |
521130d1 EE |
2370 | err = mlx4_cmd_init(dev); |
2371 | if (err) { | |
1a91de28 | 2372 | mlx4_err(dev, "Failed to init command interface, aborting\n"); |
ab9c17a0 JM |
2373 | goto err_sriov; |
2374 | } | |
2375 | ||
2376 | /* In slave functions, the communication channel must be initialized | |
2377 | * before posting commands. Also, init num_slaves before calling | |
2378 | * mlx4_init_hca */ | |
2379 | if (mlx4_is_mfunc(dev)) { | |
2380 | if (mlx4_is_master(dev)) | |
2381 | dev->num_slaves = MLX4_MAX_NUM_SLAVES; | |
2382 | else { | |
2383 | dev->num_slaves = 0; | |
f356fcbe JM |
2384 | err = mlx4_multi_func_init(dev); |
2385 | if (err) { | |
1a91de28 | 2386 | mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n"); |
ab9c17a0 JM |
2387 | goto err_cmd; |
2388 | } | |
2389 | } | |
225c7b1f RD |
2390 | } |
2391 | ||
2392 | err = mlx4_init_hca(dev); | |
ab9c17a0 JM |
2393 | if (err) { |
2394 | if (err == -EACCES) { | |
2395 | /* Not primary Physical function | |
2396 | * Running in slave mode */ | |
2397 | mlx4_cmd_cleanup(dev); | |
2398 | dev->flags |= MLX4_FLAG_SLAVE; | |
2399 | dev->flags &= ~MLX4_FLAG_MASTER; | |
2400 | goto slave_start; | |
2401 | } else | |
2402 | goto err_mfunc; | |
2403 | } | |
2404 | ||
b912b2f8 EP |
2405 | /* check if the device is functioning at its maximum possible speed. |
2406 | * No return code for this call, just warn the user in case of PCI | |
2407 | * express device capabilities are under-satisfied by the bus. | |
2408 | */ | |
2409 | mlx4_check_pcie_caps(dev); | |
2410 | ||
ab9c17a0 JM |
2411 | /* In master functions, the communication channel must be initialized |
2412 | * after obtaining its address from fw */ | |
2413 | if (mlx4_is_master(dev)) { | |
1ab95d37 | 2414 | unsigned sum = 0; |
f356fcbe JM |
2415 | err = mlx4_multi_func_init(dev); |
2416 | if (err) { | |
1a91de28 | 2417 | mlx4_err(dev, "Failed to init master mfunc interface, aborting\n"); |
ab9c17a0 JM |
2418 | goto err_close; |
2419 | } | |
1ab95d37 | 2420 | if (sriov_initialized) { |
dd41cc3b MB |
2421 | int ib_ports = 0; |
2422 | mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB) | |
2423 | ib_ports++; | |
2424 | ||
2425 | if (ib_ports && | |
2426 | (num_vfs_argc > 1 || probe_vfs_argc > 1)) { | |
2427 | mlx4_err(dev, | |
1a91de28 | 2428 | "Invalid syntax of num_vfs/probe_vfs with IB port - single port VFs syntax is only supported when all ports are configured as ethernet\n"); |
dd41cc3b MB |
2429 | goto err_close; |
2430 | } | |
1ab95d37 MB |
2431 | for (i = 0; i < sizeof(nvfs)/sizeof(nvfs[0]); i++) { |
2432 | unsigned j; | |
2433 | for (j = 0; j < nvfs[i]; ++sum, ++j) { | |
2434 | dev->dev_vfs[sum].min_port = | |
2435 | i < 2 ? i + 1 : 1; | |
2436 | dev->dev_vfs[sum].n_ports = i < 2 ? 1 : | |
2437 | dev->caps.num_ports; | |
2438 | } | |
2439 | } | |
2440 | } | |
ab9c17a0 | 2441 | } |
225c7b1f | 2442 | |
b8dd786f YP |
2443 | err = mlx4_alloc_eq_table(dev); |
2444 | if (err) | |
ab9c17a0 | 2445 | goto err_master_mfunc; |
b8dd786f | 2446 | |
0b7ca5a9 | 2447 | priv->msix_ctl.pool_bm = 0; |
730c41d5 | 2448 | mutex_init(&priv->msix_ctl.pool_lock); |
0b7ca5a9 | 2449 | |
08fb1055 | 2450 | mlx4_enable_msi_x(dev); |
ab9c17a0 JM |
2451 | if ((mlx4_is_mfunc(dev)) && |
2452 | !(dev->flags & MLX4_FLAG_MSI_X)) { | |
f356fcbe | 2453 | err = -ENOSYS; |
1a91de28 | 2454 | mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n"); |
b12d93d6 | 2455 | goto err_free_eq; |
ab9c17a0 JM |
2456 | } |
2457 | ||
2458 | if (!mlx4_is_slave(dev)) { | |
2459 | err = mlx4_init_steering(dev); | |
2460 | if (err) | |
2461 | goto err_free_eq; | |
2462 | } | |
b12d93d6 | 2463 | |
225c7b1f | 2464 | err = mlx4_setup_hca(dev); |
ab9c17a0 JM |
2465 | if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) && |
2466 | !mlx4_is_mfunc(dev)) { | |
08fb1055 | 2467 | dev->flags &= ~MLX4_FLAG_MSI_X; |
9858d2d1 YP |
2468 | dev->caps.num_comp_vectors = 1; |
2469 | dev->caps.comp_pool = 0; | |
08fb1055 MT |
2470 | pci_disable_msix(pdev); |
2471 | err = mlx4_setup_hca(dev); | |
2472 | } | |
2473 | ||
225c7b1f | 2474 | if (err) |
b12d93d6 | 2475 | goto err_steer; |
225c7b1f | 2476 | |
5a0d0a61 JM |
2477 | mlx4_init_quotas(dev); |
2478 | ||
7ff93f8b YP |
2479 | for (port = 1; port <= dev->caps.num_ports; port++) { |
2480 | err = mlx4_init_port_info(dev, port); | |
2481 | if (err) | |
2482 | goto err_port; | |
2483 | } | |
2a2336f8 | 2484 | |
225c7b1f RD |
2485 | err = mlx4_register_device(dev); |
2486 | if (err) | |
7ff93f8b | 2487 | goto err_port; |
225c7b1f | 2488 | |
b046ffe5 EP |
2489 | mlx4_request_modules(dev); |
2490 | ||
27bf91d6 YP |
2491 | mlx4_sense_init(dev); |
2492 | mlx4_start_sense(dev); | |
2493 | ||
befdf897 | 2494 | priv->removed = 0; |
225c7b1f | 2495 | |
e1a5ddc5 AV |
2496 | if (mlx4_is_master(dev) && dev->num_vfs) |
2497 | atomic_dec(&pf_loading); | |
2498 | ||
225c7b1f RD |
2499 | return 0; |
2500 | ||
7ff93f8b | 2501 | err_port: |
b4f77264 | 2502 | for (--port; port >= 1; --port) |
7ff93f8b YP |
2503 | mlx4_cleanup_port_info(&priv->port[port]); |
2504 | ||
f2a3f6a3 | 2505 | mlx4_cleanup_counters_table(dev); |
225c7b1f RD |
2506 | mlx4_cleanup_qp_table(dev); |
2507 | mlx4_cleanup_srq_table(dev); | |
2508 | mlx4_cleanup_cq_table(dev); | |
2509 | mlx4_cmd_use_polling(dev); | |
2510 | mlx4_cleanup_eq_table(dev); | |
fe6f700d | 2511 | mlx4_cleanup_mcg_table(dev); |
225c7b1f | 2512 | mlx4_cleanup_mr_table(dev); |
012a8ff5 | 2513 | mlx4_cleanup_xrcd_table(dev); |
225c7b1f RD |
2514 | mlx4_cleanup_pd_table(dev); |
2515 | mlx4_cleanup_uar_table(dev); | |
2516 | ||
b12d93d6 | 2517 | err_steer: |
ab9c17a0 JM |
2518 | if (!mlx4_is_slave(dev)) |
2519 | mlx4_clear_steering(dev); | |
b12d93d6 | 2520 | |
b8dd786f YP |
2521 | err_free_eq: |
2522 | mlx4_free_eq_table(dev); | |
2523 | ||
ab9c17a0 JM |
2524 | err_master_mfunc: |
2525 | if (mlx4_is_master(dev)) | |
2526 | mlx4_multi_func_cleanup(dev); | |
2527 | ||
225c7b1f | 2528 | err_close: |
08fb1055 MT |
2529 | if (dev->flags & MLX4_FLAG_MSI_X) |
2530 | pci_disable_msix(pdev); | |
2531 | ||
225c7b1f RD |
2532 | mlx4_close_hca(dev); |
2533 | ||
ab9c17a0 JM |
2534 | err_mfunc: |
2535 | if (mlx4_is_slave(dev)) | |
2536 | mlx4_multi_func_cleanup(dev); | |
2537 | ||
225c7b1f RD |
2538 | err_cmd: |
2539 | mlx4_cmd_cleanup(dev); | |
2540 | ||
ab9c17a0 | 2541 | err_sriov: |
681372a7 | 2542 | if (dev->flags & MLX4_FLAG_SRIOV) |
ab9c17a0 JM |
2543 | pci_disable_sriov(pdev); |
2544 | ||
2545 | err_rel_own: | |
2546 | if (!mlx4_is_slave(dev)) | |
2547 | mlx4_free_ownership(dev); | |
2548 | ||
e1a5ddc5 AV |
2549 | if (mlx4_is_master(dev) && dev->num_vfs) |
2550 | atomic_dec(&pf_loading); | |
2551 | ||
1ab95d37 MB |
2552 | kfree(priv->dev.dev_vfs); |
2553 | ||
225c7b1f | 2554 | err_free_dev: |
225c7b1f RD |
2555 | kfree(priv); |
2556 | ||
a01df0fe RD |
2557 | err_release_regions: |
2558 | pci_release_regions(pdev); | |
225c7b1f RD |
2559 | |
2560 | err_disable_pdev: | |
2561 | pci_disable_device(pdev); | |
2562 | pci_set_drvdata(pdev, NULL); | |
2563 | return err; | |
2564 | } | |
2565 | ||
1dd06ae8 | 2566 | static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id) |
3d73c288 | 2567 | { |
befdf897 WY |
2568 | struct mlx4_priv *priv; |
2569 | struct mlx4_dev *dev; | |
2570 | ||
0a645e80 | 2571 | printk_once(KERN_INFO "%s", mlx4_version); |
3d73c288 | 2572 | |
befdf897 WY |
2573 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
2574 | if (!priv) | |
2575 | return -ENOMEM; | |
2576 | ||
2577 | dev = &priv->dev; | |
2578 | pci_set_drvdata(pdev, dev); | |
2579 | priv->pci_dev_data = id->driver_data; | |
2580 | ||
839f1243 | 2581 | return __mlx4_init_one(pdev, id->driver_data); |
3d73c288 RD |
2582 | } |
2583 | ||
befdf897 | 2584 | static void __mlx4_remove_one(struct pci_dev *pdev) |
225c7b1f RD |
2585 | { |
2586 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2587 | struct mlx4_priv *priv = mlx4_priv(dev); | |
befdf897 | 2588 | int pci_dev_data; |
225c7b1f RD |
2589 | int p; |
2590 | ||
befdf897 WY |
2591 | if (priv->removed) |
2592 | return; | |
225c7b1f | 2593 | |
befdf897 | 2594 | pci_dev_data = priv->pci_dev_data; |
225c7b1f | 2595 | |
befdf897 WY |
2596 | /* in SRIOV it is not allowed to unload the pf's |
2597 | * driver while there are alive vf's */ | |
2598 | if (mlx4_is_master(dev) && mlx4_how_many_lives_vf(dev)) | |
2599 | printk(KERN_ERR "Removing PF when there are assigned VF's !!!\n"); | |
2600 | mlx4_stop_sense(dev); | |
2601 | mlx4_unregister_device(dev); | |
225c7b1f | 2602 | |
befdf897 WY |
2603 | for (p = 1; p <= dev->caps.num_ports; p++) { |
2604 | mlx4_cleanup_port_info(&priv->port[p]); | |
2605 | mlx4_CLOSE_PORT(dev, p); | |
2606 | } | |
2607 | ||
2608 | if (mlx4_is_master(dev)) | |
2609 | mlx4_free_resource_tracker(dev, | |
2610 | RES_TR_FREE_SLAVES_ONLY); | |
2611 | ||
2612 | mlx4_cleanup_counters_table(dev); | |
2613 | mlx4_cleanup_qp_table(dev); | |
2614 | mlx4_cleanup_srq_table(dev); | |
2615 | mlx4_cleanup_cq_table(dev); | |
2616 | mlx4_cmd_use_polling(dev); | |
2617 | mlx4_cleanup_eq_table(dev); | |
2618 | mlx4_cleanup_mcg_table(dev); | |
2619 | mlx4_cleanup_mr_table(dev); | |
2620 | mlx4_cleanup_xrcd_table(dev); | |
2621 | mlx4_cleanup_pd_table(dev); | |
225c7b1f | 2622 | |
befdf897 WY |
2623 | if (mlx4_is_master(dev)) |
2624 | mlx4_free_resource_tracker(dev, | |
2625 | RES_TR_FREE_STRUCTS_ONLY); | |
47605df9 | 2626 | |
befdf897 WY |
2627 | iounmap(priv->kar); |
2628 | mlx4_uar_free(dev, &priv->driver_uar); | |
2629 | mlx4_cleanup_uar_table(dev); | |
2630 | if (!mlx4_is_slave(dev)) | |
2631 | mlx4_clear_steering(dev); | |
2632 | mlx4_free_eq_table(dev); | |
2633 | if (mlx4_is_master(dev)) | |
2634 | mlx4_multi_func_cleanup(dev); | |
2635 | mlx4_close_hca(dev); | |
2636 | if (mlx4_is_slave(dev)) | |
2637 | mlx4_multi_func_cleanup(dev); | |
2638 | mlx4_cmd_cleanup(dev); | |
47605df9 | 2639 | |
befdf897 WY |
2640 | if (dev->flags & MLX4_FLAG_MSI_X) |
2641 | pci_disable_msix(pdev); | |
2642 | if (dev->flags & MLX4_FLAG_SRIOV) { | |
2643 | mlx4_warn(dev, "Disabling SR-IOV\n"); | |
2644 | pci_disable_sriov(pdev); | |
e1a5ddc5 | 2645 | dev->num_vfs = 0; |
225c7b1f | 2646 | } |
befdf897 WY |
2647 | |
2648 | if (!mlx4_is_slave(dev)) | |
2649 | mlx4_free_ownership(dev); | |
2650 | ||
2651 | kfree(dev->caps.qp0_tunnel); | |
2652 | kfree(dev->caps.qp0_proxy); | |
2653 | kfree(dev->caps.qp1_tunnel); | |
2654 | kfree(dev->caps.qp1_proxy); | |
2655 | kfree(dev->dev_vfs); | |
2656 | ||
2657 | pci_release_regions(pdev); | |
2658 | pci_disable_device(pdev); | |
2659 | memset(priv, 0, sizeof(*priv)); | |
2660 | priv->pci_dev_data = pci_dev_data; | |
2661 | priv->removed = 1; | |
2662 | } | |
2663 | ||
2664 | static void mlx4_remove_one(struct pci_dev *pdev) | |
2665 | { | |
2666 | struct mlx4_dev *dev = pci_get_drvdata(pdev); | |
2667 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2668 | ||
2669 | __mlx4_remove_one(pdev); | |
2670 | kfree(priv); | |
2671 | pci_set_drvdata(pdev, NULL); | |
225c7b1f RD |
2672 | } |
2673 | ||
ee49bd93 JM |
2674 | int mlx4_restart_one(struct pci_dev *pdev) |
2675 | { | |
839f1243 RD |
2676 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
2677 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2678 | int pci_dev_data; | |
2679 | ||
2680 | pci_dev_data = priv->pci_dev_data; | |
befdf897 | 2681 | __mlx4_remove_one(pdev); |
839f1243 | 2682 | return __mlx4_init_one(pdev, pci_dev_data); |
ee49bd93 JM |
2683 | } |
2684 | ||
a3aa1884 | 2685 | static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = { |
ab9c17a0 | 2686 | /* MT25408 "Hermon" SDR */ |
ca3e57a5 | 2687 | { PCI_VDEVICE(MELLANOX, 0x6340), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2688 | /* MT25408 "Hermon" DDR */ |
ca3e57a5 | 2689 | { PCI_VDEVICE(MELLANOX, 0x634a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2690 | /* MT25408 "Hermon" QDR */ |
ca3e57a5 | 2691 | { PCI_VDEVICE(MELLANOX, 0x6354), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2692 | /* MT25408 "Hermon" DDR PCIe gen2 */ |
ca3e57a5 | 2693 | { PCI_VDEVICE(MELLANOX, 0x6732), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2694 | /* MT25408 "Hermon" QDR PCIe gen2 */ |
ca3e57a5 | 2695 | { PCI_VDEVICE(MELLANOX, 0x673c), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2696 | /* MT25408 "Hermon" EN 10GigE */ |
ca3e57a5 | 2697 | { PCI_VDEVICE(MELLANOX, 0x6368), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2698 | /* MT25408 "Hermon" EN 10GigE PCIe gen2 */ |
ca3e57a5 | 2699 | { PCI_VDEVICE(MELLANOX, 0x6750), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2700 | /* MT25458 ConnectX EN 10GBASE-T 10GigE */ |
ca3e57a5 | 2701 | { PCI_VDEVICE(MELLANOX, 0x6372), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2702 | /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */ |
ca3e57a5 | 2703 | { PCI_VDEVICE(MELLANOX, 0x675a), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2704 | /* MT26468 ConnectX EN 10GigE PCIe gen2*/ |
ca3e57a5 | 2705 | { PCI_VDEVICE(MELLANOX, 0x6764), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2706 | /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */ |
ca3e57a5 | 2707 | { PCI_VDEVICE(MELLANOX, 0x6746), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2708 | /* MT26478 ConnectX2 40GigE PCIe gen2 */ |
ca3e57a5 | 2709 | { PCI_VDEVICE(MELLANOX, 0x676e), MLX4_PCI_DEV_FORCE_SENSE_PORT }, |
ab9c17a0 | 2710 | /* MT25400 Family [ConnectX-2 Virtual Function] */ |
839f1243 | 2711 | { PCI_VDEVICE(MELLANOX, 0x1002), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
2712 | /* MT27500 Family [ConnectX-3] */ |
2713 | { PCI_VDEVICE(MELLANOX, 0x1003), 0 }, | |
2714 | /* MT27500 Family [ConnectX-3 Virtual Function] */ | |
839f1243 | 2715 | { PCI_VDEVICE(MELLANOX, 0x1004), MLX4_PCI_DEV_IS_VF }, |
ab9c17a0 JM |
2716 | { PCI_VDEVICE(MELLANOX, 0x1005), 0 }, /* MT27510 Family */ |
2717 | { PCI_VDEVICE(MELLANOX, 0x1006), 0 }, /* MT27511 Family */ | |
2718 | { PCI_VDEVICE(MELLANOX, 0x1007), 0 }, /* MT27520 Family */ | |
2719 | { PCI_VDEVICE(MELLANOX, 0x1008), 0 }, /* MT27521 Family */ | |
2720 | { PCI_VDEVICE(MELLANOX, 0x1009), 0 }, /* MT27530 Family */ | |
2721 | { PCI_VDEVICE(MELLANOX, 0x100a), 0 }, /* MT27531 Family */ | |
2722 | { PCI_VDEVICE(MELLANOX, 0x100b), 0 }, /* MT27540 Family */ | |
2723 | { PCI_VDEVICE(MELLANOX, 0x100c), 0 }, /* MT27541 Family */ | |
2724 | { PCI_VDEVICE(MELLANOX, 0x100d), 0 }, /* MT27550 Family */ | |
2725 | { PCI_VDEVICE(MELLANOX, 0x100e), 0 }, /* MT27551 Family */ | |
2726 | { PCI_VDEVICE(MELLANOX, 0x100f), 0 }, /* MT27560 Family */ | |
2727 | { PCI_VDEVICE(MELLANOX, 0x1010), 0 }, /* MT27561 Family */ | |
225c7b1f RD |
2728 | { 0, } |
2729 | }; | |
2730 | ||
2731 | MODULE_DEVICE_TABLE(pci, mlx4_pci_table); | |
2732 | ||
57dbf29a KSS |
2733 | static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev, |
2734 | pci_channel_state_t state) | |
2735 | { | |
befdf897 | 2736 | __mlx4_remove_one(pdev); |
57dbf29a KSS |
2737 | |
2738 | return state == pci_channel_io_perm_failure ? | |
2739 | PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET; | |
2740 | } | |
2741 | ||
2742 | static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev) | |
2743 | { | |
befdf897 WY |
2744 | struct mlx4_dev *dev = pci_get_drvdata(pdev); |
2745 | struct mlx4_priv *priv = mlx4_priv(dev); | |
2746 | int ret; | |
97a5221f | 2747 | |
befdf897 | 2748 | ret = __mlx4_init_one(pdev, priv->pci_dev_data); |
57dbf29a KSS |
2749 | |
2750 | return ret ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED; | |
2751 | } | |
2752 | ||
3646f0e5 | 2753 | static const struct pci_error_handlers mlx4_err_handler = { |
57dbf29a KSS |
2754 | .error_detected = mlx4_pci_err_detected, |
2755 | .slot_reset = mlx4_pci_slot_reset, | |
2756 | }; | |
2757 | ||
225c7b1f RD |
2758 | static struct pci_driver mlx4_driver = { |
2759 | .name = DRV_NAME, | |
2760 | .id_table = mlx4_pci_table, | |
2761 | .probe = mlx4_init_one, | |
367d56f7 | 2762 | .shutdown = mlx4_remove_one, |
f57e6848 | 2763 | .remove = mlx4_remove_one, |
57dbf29a | 2764 | .err_handler = &mlx4_err_handler, |
225c7b1f RD |
2765 | }; |
2766 | ||
7ff93f8b YP |
2767 | static int __init mlx4_verify_params(void) |
2768 | { | |
2769 | if ((log_num_mac < 0) || (log_num_mac > 7)) { | |
0a645e80 | 2770 | pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac); |
7ff93f8b YP |
2771 | return -1; |
2772 | } | |
2773 | ||
cb29688a OG |
2774 | if (log_num_vlan != 0) |
2775 | pr_warning("mlx4_core: log_num_vlan - obsolete module param, using %d\n", | |
2776 | MLX4_LOG_NUM_VLANS); | |
7ff93f8b | 2777 | |
0498628f | 2778 | if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) { |
0a645e80 | 2779 | pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg); |
ab6bf42e EC |
2780 | return -1; |
2781 | } | |
2782 | ||
ab9c17a0 JM |
2783 | /* Check if module param for ports type has legal combination */ |
2784 | if (port_type_array[0] == false && port_type_array[1] == true) { | |
2785 | printk(KERN_WARNING "Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n"); | |
2786 | port_type_array[0] = true; | |
2787 | } | |
2788 | ||
3c439b55 JM |
2789 | if (mlx4_log_num_mgm_entry_size != -1 && |
2790 | (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE || | |
2791 | mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE)) { | |
1a91de28 JP |
2792 | pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-1 or %d..%d)\n", |
2793 | mlx4_log_num_mgm_entry_size, | |
2794 | MLX4_MIN_MGM_LOG_ENTRY_SIZE, | |
2795 | MLX4_MAX_MGM_LOG_ENTRY_SIZE); | |
3c439b55 JM |
2796 | return -1; |
2797 | } | |
2798 | ||
7ff93f8b YP |
2799 | return 0; |
2800 | } | |
2801 | ||
225c7b1f RD |
2802 | static int __init mlx4_init(void) |
2803 | { | |
2804 | int ret; | |
2805 | ||
7ff93f8b YP |
2806 | if (mlx4_verify_params()) |
2807 | return -EINVAL; | |
2808 | ||
27bf91d6 YP |
2809 | mlx4_catas_init(); |
2810 | ||
2811 | mlx4_wq = create_singlethread_workqueue("mlx4"); | |
2812 | if (!mlx4_wq) | |
2813 | return -ENOMEM; | |
ee49bd93 | 2814 | |
225c7b1f | 2815 | ret = pci_register_driver(&mlx4_driver); |
1b85ee09 WY |
2816 | if (ret < 0) |
2817 | destroy_workqueue(mlx4_wq); | |
225c7b1f RD |
2818 | return ret < 0 ? ret : 0; |
2819 | } | |
2820 | ||
2821 | static void __exit mlx4_cleanup(void) | |
2822 | { | |
2823 | pci_unregister_driver(&mlx4_driver); | |
27bf91d6 | 2824 | destroy_workqueue(mlx4_wq); |
225c7b1f RD |
2825 | } |
2826 | ||
2827 | module_init(mlx4_init); | |
2828 | module_exit(mlx4_cleanup); |