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net/mlx4_en: Fix improper use of "port" parameter in mlx4_en_event
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
ee49bd93 42#include <linux/timer.h>
3142788b 43#include <linux/semaphore.h>
27bf91d6 44#include <linux/workqueue.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
37608eea 47#include <linux/mlx4/driver.h>
225c7b1f 48#include <linux/mlx4/doorbell.h>
623ed84b 49#include <linux/mlx4/cmd.h>
225c7b1f
RD		 50
51#define DRV_NAME "mlx4_core"
ab9c17a0 52#define PFX DRV_NAME ": "
7d4b6bcc
YP		 53#define DRV_VERSION "1.1"
54#define DRV_RELDATE "Dec, 2011"
225c7b1f 55
e5395e92
AV		 56#define MLX4_NUM_UP 8
57#define MLX4_NUM_TC 8
58#define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */
59#define MLX4_RATELIMIT_DEFAULT 0xffff
60
61struct mlx4_set_port_prio2tc_context {
62 u8 prio2tc[4];
63};
64
65struct mlx4_port_scheduler_tc_cfg_be {
66 __be16 pg;
67 __be16 bw_precentage;
68 __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */
69 __be16 max_bw_value;
70};
71
72struct mlx4_set_port_scheduler_context {
73 struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC];
74};
75
225c7b1f
RD		 76enum {
77 MLX4_HCR_BASE = 0x80680,
78 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 79 MLX4_CLR_INT_SIZE = 0x00008,
80 MLX4_SLAVE_COMM_BASE = 0x0,
81 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 82};
83
225c7b1f 84enum {
0ec2c0f8
EE		 85 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
86 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
87 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 88};
89
225c7b1f
RD		 90enum {
91 MLX4_NUM_PDS = 1 << 15
92};
93
94enum {
95 MLX4_CMPT_TYPE_QP = 0,
96 MLX4_CMPT_TYPE_SRQ = 1,
97 MLX4_CMPT_TYPE_CQ = 2,
98 MLX4_CMPT_TYPE_EQ = 3,
99 MLX4_CMPT_NUM_TYPE
100};
101
102enum {
103 MLX4_CMPT_SHIFT = 24,
104 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
105};
106
623ed84b
JM		 107enum mlx4_mr_state {
108 MLX4_MR_DISABLED = 0,
109 MLX4_MR_EN_HW,
110 MLX4_MR_EN_SW
111};
112
113#define MLX4_COMM_TIME 10000
114enum {
115 MLX4_COMM_CMD_RESET,
116 MLX4_COMM_CMD_VHCR0,
117 MLX4_COMM_CMD_VHCR1,
118 MLX4_COMM_CMD_VHCR2,
119 MLX4_COMM_CMD_VHCR_EN,
120 MLX4_COMM_CMD_VHCR_POST,
121 MLX4_COMM_CMD_FLR = 254
122};
123
124/*The flag indicates that the slave should delay the RESET cmd*/
125#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
126/*indicates how many retries will be done if we are in the middle of FLR*/
127#define NUM_OF_RESET_RETRIES 10
128#define SLEEP_TIME_IN_RESET (2 * 1000)
129enum mlx4_resource {
130 RES_QP,
131 RES_CQ,
132 RES_SRQ,
133 RES_XRCD,
134 RES_MPT,
135 RES_MTT,
136 RES_MAC,
137 RES_VLAN,
138 RES_EQ,
139 RES_COUNTER,
140 MLX4_NUM_OF_RESOURCE_TYPE
141};
142
143enum mlx4_alloc_mode {
144 RES_OP_RESERVE,
145 RES_OP_RESERVE_AND_MAP,
146 RES_OP_MAP_ICM,
147};
148
b8924951
JM		 149enum mlx4_res_tracker_free_type {
150 RES_TR_FREE_ALL,
151 RES_TR_FREE_SLAVES_ONLY,
152 RES_TR_FREE_STRUCTS_ONLY,
153};
623ed84b
JM		 154
155/*
156 *Virtual HCR structures.
157 * mlx4_vhcr is the sw representation, in machine endianess
158 *
159 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
160 * to FW to go through communication channel.
161 * It is big endian, and has the same structure as the physical HCR
162 * used by command interface
163 */
164struct mlx4_vhcr {
165 u64 in_param;
166 u64 out_param;
167 u32 in_modifier;
168 u32 errno;
169 u16 op;
170 u16 token;
171 u8 op_modifier;
172 u8 e_bit;
173};
174
175struct mlx4_vhcr_cmd {
176 __be64 in_param;
177 __be32 in_modifier;
178 __be64 out_param;
179 __be16 token;
180 u16 reserved;
181 u8 status;
182 u8 flags;
183 __be16 opcode;
184};
185
186struct mlx4_cmd_info {
187 u16 opcode;
188 bool has_inbox;
189 bool has_outbox;
190 bool out_is_imm;
191 bool encode_slave_id;
192 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
193 struct mlx4_cmd_mailbox *inbox);
194 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
195 struct mlx4_cmd_mailbox *inbox,
196 struct mlx4_cmd_mailbox *outbox,
197 struct mlx4_cmd_info *cmd);
198};
199
225c7b1f
RD		 200#ifdef CONFIG_MLX4_DEBUG
201extern int mlx4_debug_level;
7b0f5df4
RD		 202#else /* CONFIG_MLX4_DEBUG */
203#define mlx4_debug_level (0)
204#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 205
206#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 207do { \
208 if (mlx4_debug_level) \
209 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
210} while (0)
225c7b1f 211
225c7b1f 212#define mlx4_err(mdev, format, arg...) \
0a645e80 213 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 214#define mlx4_info(mdev, format, arg...) \
0a645e80 215 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 216#define mlx4_warn(mdev, format, arg...) \
0a645e80 217 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 218
0ec2c0f8 219extern int mlx4_log_num_mgm_entry_size;
2b8fb286 220extern int log_mtts_per_seg;
0ec2c0f8 221
623ed84b
JM		 222#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
223#define ALL_SLAVES 0xff
224
225c7b1f
RD		 225struct mlx4_bitmap {
226 u32 last;
227 u32 top;
228 u32 max;
93fc9e1b 229 u32 reserved_top;
225c7b1f 230 u32 mask;
42d1e017 231 u32 avail;
225c7b1f
RD		 232 spinlock_t lock;
233 unsigned long *table;
234};
235
236struct mlx4_buddy {
237 unsigned long **bits;
e4044cfc 238 unsigned int *num_free;
225c7b1f
RD		 239 int max_order;
240 spinlock_t lock;
241};
242
243struct mlx4_icm;
244
245struct mlx4_icm_table {
246 u64 virt;
247 int num_icm;
248 int num_obj;
249 int obj_size;
250 int lowmem;
5b0bf5e2 251 int coherent;
225c7b1f
RD		 252 struct mutex mutex;
253 struct mlx4_icm **icm;
254};
255
c82e9aa0
EC		 256/*
257 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
258 */
259struct mlx4_mpt_entry {
260 __be32 flags;
261 __be32 qpn;
262 __be32 key;
263 __be32 pd_flags;
264 __be64 start;
265 __be64 length;
266 __be32 lkey;
267 __be32 win_cnt;
268 u8 reserved1[3];
269 u8 mtt_rep;
2b8fb286 270 __be64 mtt_addr;
c82e9aa0
EC		 271 __be32 mtt_sz;
272 __be32 entity_size;
273 __be32 first_byte_offset;
274} __packed;
275
276/*
277 * Must be packed because start is 64 bits but only aligned to 32 bits.
278 */
279struct mlx4_eq_context {
280 __be32 flags;
281 u16 reserved1[3];
282 __be16 page_offset;
283 u8 log_eq_size;
284 u8 reserved2[4];
285 u8 eq_period;
286 u8 reserved3;
287 u8 eq_max_count;
288 u8 reserved4[3];
289 u8 intr;
290 u8 log_page_size;
291 u8 reserved5[2];
292 u8 mtt_base_addr_h;
293 __be32 mtt_base_addr_l;
294 u32 reserved6[2];
295 __be32 consumer_index;
296 __be32 producer_index;
297 u32 reserved7[4];
298};
299
300struct mlx4_cq_context {
301 __be32 flags;
302 u16 reserved1[3];
303 __be16 page_offset;
304 __be32 logsize_usrpage;
305 __be16 cq_period;
306 __be16 cq_max_count;
307 u8 reserved2[3];
308 u8 comp_eqn;
309 u8 log_page_size;
310 u8 reserved3[2];
311 u8 mtt_base_addr_h;
312 __be32 mtt_base_addr_l;
313 __be32 last_notified_index;
314 __be32 solicit_producer_index;
315 __be32 consumer_index;
316 __be32 producer_index;
317 u32 reserved4[2];
318 __be64 db_rec_addr;
319};
320
321struct mlx4_srq_context {
322 __be32 state_logsize_srqn;
323 u8 logstride;
324 u8 reserved1;
325 __be16 xrcd;
326 __be32 pg_offset_cqn;
327 u32 reserved2;
328 u8 log_page_size;
329 u8 reserved3[2];
330 u8 mtt_base_addr_h;
331 __be32 mtt_base_addr_l;
332 __be32 pd;
333 __be16 limit_watermark;
334 __be16 wqe_cnt;
335 u16 reserved4;
336 __be16 wqe_counter;
337 u32 reserved5;
338 __be64 db_rec_addr;
339};
340
623ed84b
JM		 341struct mlx4_eqe {
342 u8 reserved1;
343 u8 type;
344 u8 reserved2;
345 u8 subtype;
346 union {
347 u32 raw[6];
348 struct {
349 __be32 cqn;
350 } __packed comp;
351 struct {
352 u16 reserved1;
353 __be16 token;
354 u32 reserved2;
355 u8 reserved3[3];
356 u8 status;
357 __be64 out_param;
358 } __packed cmd;
359 struct {
360 __be32 qpn;
361 } __packed qp;
362 struct {
363 __be32 srqn;
364 } __packed srq;
365 struct {
366 __be32 cqn;
367 u32 reserved1;
368 u8 reserved2[3];
369 u8 syndrome;
370 } __packed cq_err;
371 struct {
372 u32 reserved1[2];
373 __be32 port;
374 } __packed port_change;
375 struct {
376 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
377 u32 reserved;
378 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
379 } __packed comm_channel_arm;
380 struct {
381 u8 port;
382 u8 reserved[3];
383 __be64 mac;
384 } __packed mac_update;
385 struct {
386 u8 port;
387 } __packed sw_event;
388 struct {
389 __be32 slave_id;
390 } __packed flr_event;
5984be90
JM		 391 struct {
392 __be16 current_temperature;
393 __be16 warning_threshold;
394 } __packed warming;
623ed84b
JM		 395 } event;
396 u8 slave_id;
397 u8 reserved3[2];
398 u8 owner;
399} __packed;
400
225c7b1f
RD		 401struct mlx4_eq {
402 struct mlx4_dev *dev;
403 void __iomem *doorbell;
404 int eqn;
405 u32 cons_index;
406 u16 irq;
407 u16 have_irq;
408 int nent;
409 struct mlx4_buf_list *page_list;
410 struct mlx4_mtt mtt;
411};
412
623ed84b
JM		 413struct mlx4_slave_eqe {
414 u8 type;
415 u8 port;
416 u32 param;
417};
418
419struct mlx4_slave_event_eq_info {
803143fb 420 int eqn;
623ed84b 421 u16 token;
623ed84b
JM		 422};
423
225c7b1f
RD		 424struct mlx4_profile {
425 int num_qp;
426 int rdmarc_per_qp;
427 int num_srq;
428 int num_cq;
429 int num_mcg;
430 int num_mpt;
db5a7a65 431 unsigned num_mtt;
225c7b1f
RD		 432};
433
434struct mlx4_fw {
435 u64 clr_int_base;
436 u64 catas_offset;
623ed84b 437 u64 comm_base;
225c7b1f
RD		 438 struct mlx4_icm *fw_icm;
439 struct mlx4_icm *aux_icm;
440 u32 catas_size;
441 u16 fw_pages;
442 u8 clr_int_bar;
443 u8 catas_bar;
623ed84b
JM		 444 u8 comm_bar;
445};
446
447struct mlx4_comm {
448 u32 slave_write;
449 u32 slave_read;
225c7b1f
RD		 450};
451
ffe455ad
EE		 452enum {
453 MLX4_MCAST_CONFIG = 0,
454 MLX4_MCAST_DISABLE = 1,
455 MLX4_MCAST_ENABLE = 2,
456};
457
623ed84b
JM		 458#define VLAN_FLTR_SIZE 128
459
460struct mlx4_vlan_fltr {
461 __be32 entry[VLAN_FLTR_SIZE];
462};
463
ffe455ad
EE		 464struct mlx4_mcast_entry {
465 struct list_head list;
466 u64 addr;
467};
468
b12d93d6
YP		 469struct mlx4_promisc_qp {
470 struct list_head list;
471 u32 qpn;
472};
473
474struct mlx4_steer_index {
475 struct list_head list;
476 unsigned int index;
477 struct list_head duplicates;
478};
479
803143fb
MA		 480#define MLX4_EVENT_TYPES_NUM 64
481
623ed84b
JM		 482struct mlx4_slave_state {
483 u8 comm_toggle;
484 u8 last_cmd;
485 u8 init_port_mask;
486 bool active;
487 u8 function;
488 dma_addr_t vhcr_dma;
489 u16 mtu[MLX4_MAX_PORTS + 1];
490 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
491 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
492 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
493 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
803143fb
MA		 494 /* event type to eq number lookup */
495 struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM];
623ed84b
JM		 496 u16 eq_pi;
497 u16 eq_ci;
498 spinlock_t lock;
499 /*initialized via the kzalloc*/
500 u8 is_slave_going_down;
501 u32 cookie;
502};
503
504struct slave_list {
505 struct mutex mutex;
506 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
507};
508
509struct mlx4_resource_tracker {
510 spinlock_t lock;
511 /* tree for each resources */
512 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
513 /* num_of_slave's lists, one per slave */
514 struct slave_list *slave_list;
515};
516
517#define SLAVE_EVENT_EQ_SIZE 128
518struct mlx4_slave_event_eq {
519 u32 eqn;
520 u32 cons;
521 u32 prod;
522 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
523};
524
525struct mlx4_master_qp0_state {
526 int proxy_qp0_active;
527 int qp0_active;
528 int port_active;
529};
530
531struct mlx4_mfunc_master_ctx {
532 struct mlx4_slave_state *slave_state;
533 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
534 int init_port_ref[MLX4_MAX_PORTS + 1];
535 u16 max_mtu[MLX4_MAX_PORTS + 1];
536 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
537 struct mlx4_resource_tracker res_tracker;
538 struct workqueue_struct *comm_wq;
539 struct work_struct comm_work;
540 struct work_struct slave_event_work;
541 struct work_struct slave_flr_event_work;
542 spinlock_t slave_state_lock;
f5311ac1 543 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 544 struct mlx4_eqe cmd_eqe;
545 struct mlx4_slave_event_eq slave_eq;
546 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
547};
548
549struct mlx4_mfunc {
550 struct mlx4_comm __iomem *comm;
551 struct mlx4_vhcr_cmd *vhcr;
552 dma_addr_t vhcr_dma;
553
554 struct mlx4_mfunc_master_ctx master;
555};
556
225c7b1f
RD		 557struct mlx4_cmd {
558 struct pci_pool *pool;
559 void __iomem *hcr;
560 struct mutex hcr_mutex;
561 struct semaphore poll_sem;
562 struct semaphore event_sem;
623ed84b 563 struct semaphore slave_sem;
225c7b1f
RD		 564 int max_cmds;
565 spinlock_t context_lock;
566 int free_head;
567 struct mlx4_cmd_context *context;
568 u16 token_mask;
569 u8 use_events;
570 u8 toggle;
623ed84b 571 u8 comm_toggle;
225c7b1f
RD		 572};
573
574struct mlx4_uar_table {
575 struct mlx4_bitmap bitmap;
576};
577
578struct mlx4_mr_table {
579 struct mlx4_bitmap mpt_bitmap;
580 struct mlx4_buddy mtt_buddy;
581 u64 mtt_base;
582 u64 mpt_base;
583 struct mlx4_icm_table mtt_table;
584 struct mlx4_icm_table dmpt_table;
585};
586
587struct mlx4_cq_table {
588 struct mlx4_bitmap bitmap;
589 spinlock_t lock;
590 struct radix_tree_root tree;
591 struct mlx4_icm_table table;
592 struct mlx4_icm_table cmpt_table;
593};
594
595struct mlx4_eq_table {
596 struct mlx4_bitmap bitmap;
b8dd786f 597 char *irq_names;
225c7b1f 598 void __iomem *clr_int;
b8dd786f 599 void __iomem **uar_map;
225c7b1f 600 u32 clr_mask;
b8dd786f 601 struct mlx4_eq *eq;
fa0681d2 602 struct mlx4_icm_table table;
225c7b1f
RD		 603 struct mlx4_icm_table cmpt_table;
604 int have_irq;
605 u8 inta_pin;
606};
607
608struct mlx4_srq_table {
609 struct mlx4_bitmap bitmap;
610 spinlock_t lock;
611 struct radix_tree_root tree;
612 struct mlx4_icm_table table;
613 struct mlx4_icm_table cmpt_table;
614};
615
616struct mlx4_qp_table {
617 struct mlx4_bitmap bitmap;
618 u32 rdmarc_base;
619 int rdmarc_shift;
620 spinlock_t lock;
621 struct mlx4_icm_table qp_table;
622 struct mlx4_icm_table auxc_table;
623 struct mlx4_icm_table altc_table;
624 struct mlx4_icm_table rdmarc_table;
625 struct mlx4_icm_table cmpt_table;
626};
627
628struct mlx4_mcg_table {
629 struct mutex mutex;
630 struct mlx4_bitmap bitmap;
631 struct mlx4_icm_table table;
632};
633
634struct mlx4_catas_err {
635 u32 __iomem *map;
ee49bd93
JM		 636 struct timer_list timer;
637 struct list_head list;
225c7b1f
RD		 638};
639
2a2336f8
YP		 640#define MLX4_MAX_MAC_NUM 128
641#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
642
643struct mlx4_mac_table {
644 __be64 entries[MLX4_MAX_MAC_NUM];
645 int refs[MLX4_MAX_MAC_NUM];
646 struct mutex mutex;
647 int total;
648 int max;
649};
650
651#define MLX4_MAX_VLAN_NUM 128
652#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
653
654struct mlx4_vlan_table {
655 __be32 entries[MLX4_MAX_VLAN_NUM];
656 int refs[MLX4_MAX_VLAN_NUM];
657 struct mutex mutex;
658 int total;
659 int max;
660};
661
ffe455ad
EE		 662#define SET_PORT_GEN_ALL_VALID 0x7
663#define SET_PORT_PROMISC_SHIFT 31
664#define SET_PORT_MC_PROMISC_SHIFT 30
665
666enum {
667 MCAST_DIRECT_ONLY = 0,
668 MCAST_DIRECT = 1,
669 MCAST_DEFAULT = 2
670};
671
672
673struct mlx4_set_port_general_context {
674 u8 reserved[3];
675 u8 flags;
676 u16 reserved2;
677 __be16 mtu;
678 u8 pptx;
679 u8 pfctx;
680 u16 reserved3;
681 u8 pprx;
682 u8 pfcrx;
683 u16 reserved4;
684};
685
686struct mlx4_set_port_rqp_calc_context {
687 __be32 base_qpn;
688 u8 rererved;
689 u8 n_mac;
690 u8 n_vlan;
691 u8 n_prio;
692 u8 reserved2[3];
693 u8 mac_miss;
694 u8 intra_no_vlan;
695 u8 no_vlan;
696 u8 intra_vlan_miss;
697 u8 vlan_miss;
698 u8 reserved3[3];
699 u8 no_vlan_prio;
700 __be32 promisc;
701 __be32 mcast;
702};
703
1679200f
YP		 704struct mlx4_mac_entry {
705 u64 mac;
706};
707
2a2336f8
YP		 708struct mlx4_port_info {
709 struct mlx4_dev *dev;
710 int port;
7ff93f8b
YP		 711 char dev_name[16];
712 struct device_attribute port_attr;
713 enum mlx4_port_type tmp_type;
096335b3
OG		 714 char dev_mtu_name[16];
715 struct device_attribute port_mtu_attr;
2a2336f8 716 struct mlx4_mac_table mac_table;
1679200f 717 struct radix_tree_root mac_tree;
2a2336f8 718 struct mlx4_vlan_table vlan_table;
1679200f 719 int base_qpn;
2a2336f8
YP		 720};
721
27bf91d6
YP		 722struct mlx4_sense {
723 struct mlx4_dev *dev;
724 u8 do_sense_port[MLX4_MAX_PORTS + 1];
725 u8 sense_allowed[MLX4_MAX_PORTS + 1];
726 struct delayed_work sense_poll;
727};
728
0b7ca5a9
YP		 729struct mlx4_msix_ctl {
730 u64 pool_bm;
730c41d5 731 struct mutex pool_lock;
0b7ca5a9
YP		 732};
733
b12d93d6
YP		 734struct mlx4_steer {
735 struct list_head promisc_qps[MLX4_NUM_STEERS];
736 struct list_head steer_entries[MLX4_NUM_STEERS];
b12d93d6
YP		 737};
738
225c7b1f
RD		 739struct mlx4_priv {
740 struct mlx4_dev dev;
741
742 struct list_head dev_list;
743 struct list_head ctx_list;
744 spinlock_t ctx_lock;
745
6296883c
YP		 746 struct list_head pgdir_list;
747 struct mutex pgdir_mutex;
748
225c7b1f
RD		 749 struct mlx4_fw fw;
750 struct mlx4_cmd cmd;
623ed84b 751 struct mlx4_mfunc mfunc;
225c7b1f
RD		 752
753 struct mlx4_bitmap pd_bitmap;
012a8ff5 754 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 755 struct mlx4_uar_table uar_table;
756 struct mlx4_mr_table mr_table;
757 struct mlx4_cq_table cq_table;
758 struct mlx4_eq_table eq_table;
759 struct mlx4_srq_table srq_table;
760 struct mlx4_qp_table qp_table;
761 struct mlx4_mcg_table mcg_table;
f2a3f6a3 762 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 763
764 struct mlx4_catas_err catas_err;
765
766 void __iomem *clr_base;
767
768 struct mlx4_uar driver_uar;
769 void __iomem *kar;
2a2336f8 770 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 771 struct mlx4_sense sense;
7ff93f8b 772 struct mutex port_mutex;
0b7ca5a9 773 struct mlx4_msix_ctl msix_ctl;
b12d93d6 774 struct mlx4_steer *steer;
c1b43dca
EC		 775 struct list_head bf_list;
776 struct mutex bf_mutex;
777 struct io_mapping *bf_mapping;
ea51b377 778 int reserved_mtts;
225c7b1f
RD		 779};
780
781static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
782{
783 return container_of(dev, struct mlx4_priv, dev);
784}
785
27bf91d6
YP		 786#define MLX4_SENSE_RANGE (HZ * 3)
787
788extern struct workqueue_struct *mlx4_wq;
789
225c7b1f
RD		 790u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
791void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 792u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
793void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 794u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 795int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
796 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 797void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
798
799int mlx4_reset(struct mlx4_dev *dev);
800
b8dd786f
YP		 801int mlx4_alloc_eq_table(struct mlx4_dev *dev);
802void mlx4_free_eq_table(struct mlx4_dev *dev);
803
225c7b1f 804int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 805int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 806int mlx4_init_uar_table(struct mlx4_dev *dev);
807int mlx4_init_mr_table(struct mlx4_dev *dev);
808int mlx4_init_eq_table(struct mlx4_dev *dev);
809int mlx4_init_cq_table(struct mlx4_dev *dev);
810int mlx4_init_qp_table(struct mlx4_dev *dev);
811int mlx4_init_srq_table(struct mlx4_dev *dev);
812int mlx4_init_mcg_table(struct mlx4_dev *dev);
813
814void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 815void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 816void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
817void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
818void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
819void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
820void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
821void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
822void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 823int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
824void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
825int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
826void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
827int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
828void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
829int __mlx4_mr_reserve(struct mlx4_dev *dev);
830void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
831int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
832void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
833u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
834void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 835
623ed84b
JM		 836int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
837 struct mlx4_vhcr *vhcr,
838 struct mlx4_cmd_mailbox *inbox,
839 struct mlx4_cmd_mailbox *outbox,
840 struct mlx4_cmd_info *cmd);
841int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
842 struct mlx4_vhcr *vhcr,
843 struct mlx4_cmd_mailbox *inbox,
844 struct mlx4_cmd_mailbox *outbox,
845 struct mlx4_cmd_info *cmd);
846int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
847 struct mlx4_vhcr *vhcr,
848 struct mlx4_cmd_mailbox *inbox,
849 struct mlx4_cmd_mailbox *outbox,
850 struct mlx4_cmd_info *cmd);
851int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
852 struct mlx4_vhcr *vhcr,
853 struct mlx4_cmd_mailbox *inbox,
854 struct mlx4_cmd_mailbox *outbox,
855 struct mlx4_cmd_info *cmd);
856int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
857 struct mlx4_vhcr *vhcr,
858 struct mlx4_cmd_mailbox *inbox,
859 struct mlx4_cmd_mailbox *outbox,
860 struct mlx4_cmd_info *cmd);
861int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
862 struct mlx4_vhcr *vhcr,
863 struct mlx4_cmd_mailbox *inbox,
864 struct mlx4_cmd_mailbox *outbox,
865 struct mlx4_cmd_info *cmd);
866int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
867 struct mlx4_vhcr *vhcr,
868 struct mlx4_cmd_mailbox *inbox,
869 struct mlx4_cmd_mailbox *outbox,
870 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 871int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
872 int *base);
873void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
874int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
875void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
876int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
877int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
878 int start_index, int npages, u64 *page_list);
ba062d52
JM		 879int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
880void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
881int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
882void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
623ed84b 883
ee49bd93
JM		 884void mlx4_start_catas_poll(struct mlx4_dev *dev);
885void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 886void mlx4_catas_init(void);
ee49bd93 887int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 888int mlx4_register_device(struct mlx4_dev *dev);
889void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea 890void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f
RD		 891
892struct mlx4_dev_cap;
893struct mlx4_init_hca_param;
894
895u64 mlx4_make_profile(struct mlx4_dev *dev,
896 struct mlx4_profile *request,
897 struct mlx4_dev_cap *dev_cap,
898 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 899void mlx4_master_comm_channel(struct work_struct *work);
900void mlx4_gen_slave_eqe(struct work_struct *work);
901void mlx4_master_handle_slave_flr(struct work_struct *work);
902
903int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
904 struct mlx4_vhcr *vhcr,
905 struct mlx4_cmd_mailbox *inbox,
906 struct mlx4_cmd_mailbox *outbox,
907 struct mlx4_cmd_info *cmd);
908int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
909 struct mlx4_vhcr *vhcr,
910 struct mlx4_cmd_mailbox *inbox,
911 struct mlx4_cmd_mailbox *outbox,
912 struct mlx4_cmd_info *cmd);
913int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
914 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
915 struct mlx4_cmd_mailbox *outbox,
916 struct mlx4_cmd_info *cmd);
917int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
918 struct mlx4_vhcr *vhcr,
919 struct mlx4_cmd_mailbox *inbox,
920 struct mlx4_cmd_mailbox *outbox,
921 struct mlx4_cmd_info *cmd);
922int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
923 struct mlx4_vhcr *vhcr,
924 struct mlx4_cmd_mailbox *inbox,
925 struct mlx4_cmd_mailbox *outbox,
926 struct mlx4_cmd_info *cmd);
927int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
928 struct mlx4_vhcr *vhcr,
929 struct mlx4_cmd_mailbox *inbox,
930 struct mlx4_cmd_mailbox *outbox,
931 struct mlx4_cmd_info *cmd);
932int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
933 struct mlx4_vhcr *vhcr,
934 struct mlx4_cmd_mailbox *inbox,
935 struct mlx4_cmd_mailbox *outbox,
936 struct mlx4_cmd_info *cmd);
937int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
938 struct mlx4_vhcr *vhcr,
939 struct mlx4_cmd_mailbox *inbox,
940 struct mlx4_cmd_mailbox *outbox,
941 struct mlx4_cmd_info *cmd);
942int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
943 struct mlx4_vhcr *vhcr,
944 struct mlx4_cmd_mailbox *inbox,
945 struct mlx4_cmd_mailbox *outbox,
946 struct mlx4_cmd_info *cmd);
947int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
948 struct mlx4_vhcr *vhcr,
949 struct mlx4_cmd_mailbox *inbox,
950 struct mlx4_cmd_mailbox *outbox,
951 struct mlx4_cmd_info *cmd);
952int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
953 struct mlx4_vhcr *vhcr,
954 struct mlx4_cmd_mailbox *inbox,
955 struct mlx4_cmd_mailbox *outbox,
956 struct mlx4_cmd_info *cmd);
957int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
958 struct mlx4_vhcr *vhcr,
959 struct mlx4_cmd_mailbox *inbox,
960 struct mlx4_cmd_mailbox *outbox,
961 struct mlx4_cmd_info *cmd);
962int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
963 struct mlx4_vhcr *vhcr,
964 struct mlx4_cmd_mailbox *inbox,
965 struct mlx4_cmd_mailbox *outbox,
966 struct mlx4_cmd_info *cmd);
967int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
968 struct mlx4_vhcr *vhcr,
969 struct mlx4_cmd_mailbox *inbox,
970 struct mlx4_cmd_mailbox *outbox,
971 struct mlx4_cmd_info *cmd);
972int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
973 struct mlx4_vhcr *vhcr,
974 struct mlx4_cmd_mailbox *inbox,
975 struct mlx4_cmd_mailbox *outbox,
976 struct mlx4_cmd_info *cmd);
977int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
978 struct mlx4_vhcr *vhcr,
979 struct mlx4_cmd_mailbox *inbox,
980 struct mlx4_cmd_mailbox *outbox,
981 struct mlx4_cmd_info *cmd);
982int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
983 struct mlx4_vhcr *vhcr,
984 struct mlx4_cmd_mailbox *inbox,
985 struct mlx4_cmd_mailbox *outbox,
986 struct mlx4_cmd_info *cmd);
987int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
988 struct mlx4_vhcr *vhcr,
989 struct mlx4_cmd_mailbox *inbox,
990 struct mlx4_cmd_mailbox *outbox,
991 struct mlx4_cmd_info *cmd);
992
993int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 994
225c7b1f
RD		 995int mlx4_cmd_init(struct mlx4_dev *dev);
996void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 997int mlx4_multi_func_init(struct mlx4_dev *dev);
998void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 999void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
1000int mlx4_cmd_use_events(struct mlx4_dev *dev);
1001void mlx4_cmd_use_polling(struct mlx4_dev *dev);
1002
ab9c17a0
JM		 1003int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
1004 unsigned long timeout);
1005
225c7b1f
RD		 1006void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
1007void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
1008
1009void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
1010
1011void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
1012
1013void mlx4_handle_catas_err(struct mlx4_dev *dev);
1014
ab6dc30d
YP		 1015int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
1016 enum mlx4_port_type *type);
27bf91d6
YP		 1017void mlx4_do_sense_ports(struct mlx4_dev *dev,
1018 enum mlx4_port_type *stype,
1019 enum mlx4_port_type *defaults);
1020void mlx4_start_sense(struct mlx4_dev *dev);
1021void mlx4_stop_sense(struct mlx4_dev *dev);
1022void mlx4_sense_init(struct mlx4_dev *dev);
1023int mlx4_check_port_params(struct mlx4_dev *dev,
1024 enum mlx4_port_type *port_type);
1025int mlx4_change_port_types(struct mlx4_dev *dev,
1026 enum mlx4_port_type *port_types);
1027
2a2336f8
YP		 1028void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
1029void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
1030
7ff93f8b 1031int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 1032/* resource tracker functions*/
1033int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
1034 enum mlx4_resource resource_type,
1035 int resource_id, int *slave);
1036void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1037int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1038
b8924951
JM		 1039void mlx4_free_resource_tracker(struct mlx4_dev *dev,
1040 enum mlx4_res_tracker_free_type type);
623ed84b
JM		 1041
1042int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1043 struct mlx4_vhcr *vhcr,
1044 struct mlx4_cmd_mailbox *inbox,
1045 struct mlx4_cmd_mailbox *outbox,
1046 struct mlx4_cmd_info *cmd);
1047int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1048 struct mlx4_vhcr *vhcr,
1049 struct mlx4_cmd_mailbox *inbox,
1050 struct mlx4_cmd_mailbox *outbox,
1051 struct mlx4_cmd_info *cmd);
1052int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1053 struct mlx4_vhcr *vhcr,
1054 struct mlx4_cmd_mailbox *inbox,
1055 struct mlx4_cmd_mailbox *outbox,
1056 struct mlx4_cmd_info *cmd);
1057int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1058 struct mlx4_vhcr *vhcr,
1059 struct mlx4_cmd_mailbox *inbox,
1060 struct mlx4_cmd_mailbox *outbox,
1061 struct mlx4_cmd_info *cmd);
9a5aa622 1062int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
7ff93f8b 1063
623ed84b
JM		 1064
1065int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1066 struct mlx4_vhcr *vhcr,
1067 struct mlx4_cmd_mailbox *inbox,
1068 struct mlx4_cmd_mailbox *outbox,
1069 struct mlx4_cmd_info *cmd);
1070
1071int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1072 struct mlx4_vhcr *vhcr,
1073 struct mlx4_cmd_mailbox *inbox,
1074 struct mlx4_cmd_mailbox *outbox,
1075 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1076int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1077 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1078int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1079 int block_mcast_loopback, enum mlx4_protocol prot,
1080 enum mlx4_steer_type steer);
623ed84b
JM		 1081int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1082 struct mlx4_vhcr *vhcr,
1083 struct mlx4_cmd_mailbox *inbox,
1084 struct mlx4_cmd_mailbox *outbox,
1085 struct mlx4_cmd_info *cmd);
1086int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1087 struct mlx4_vhcr *vhcr,
1088 struct mlx4_cmd_mailbox *inbox,
1089 struct mlx4_cmd_mailbox *outbox,
1090 struct mlx4_cmd_info *cmd);
1091int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1092 int port, void *buf);
1093int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1094 struct mlx4_cmd_mailbox *outbox);
1095int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1096 struct mlx4_vhcr *vhcr,
1097 struct mlx4_cmd_mailbox *inbox,
1098 struct mlx4_cmd_mailbox *outbox,
1099 struct mlx4_cmd_info *cmd);
1100int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1101 struct mlx4_vhcr *vhcr,
1102 struct mlx4_cmd_mailbox *inbox,
1103 struct mlx4_cmd_mailbox *outbox,
1104 struct mlx4_cmd_info *cmd);
1105int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1106 struct mlx4_vhcr *vhcr,
1107 struct mlx4_cmd_mailbox *inbox,
1108 struct mlx4_cmd_mailbox *outbox,
1109 struct mlx4_cmd_info *cmd);
f5311ac1 1110
0ec2c0f8
EE		 1111int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1112int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1113
5cc914f1
MA		 1114static inline void set_param_l(u64 *arg, u32 val)
1115{
1116 *((u32 *)arg) = val;
1117}
1118
1119static inline void set_param_h(u64 *arg, u32 val)
1120{
1121 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1122}
1123
1124static inline u32 get_param_l(u64 *arg)
1125{
1126 return (u32) (*arg & 0xffffffff);
1127}
1128
1129static inline u32 get_param_h(u64 *arg)
1130{
1131 return (u32)(*arg >> 32);
1132}
1133
c82e9aa0
EC		 1134static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1135{
1136 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1137}
1138
f5311ac1
JM		 1139#define NOT_MASKED_PD_BITS 17
1140
225c7b1f 1141#endif /* MLX4_H */
Linux kernel - Deliverables
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