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mlx4_core: updated driver version to 1.1
[deliverable/linux.git] / drivers / net / ethernet / mellanox / mlx4 / mlx4.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved.
51a379d0 5 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
225c7b1f
RD		 6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7 *
8 * This software is available to you under a choice of one of two
9 * licenses. You may choose to be licensed under the terms of the GNU
10 * General Public License (GPL) Version 2, available from the file
11 * COPYING in the main directory of this source tree, or the
12 * OpenIB.org BSD license below:
13 *
14 * Redistribution and use in source and binary forms, with or
15 * without modification, are permitted provided that the following
16 * conditions are met:
17 *
18 * - Redistributions of source code must retain the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer.
21 *
22 * - Redistributions in binary form must reproduce the above
23 * copyright notice, this list of conditions and the following
24 * disclaimer in the documentation and/or other materials
25 * provided with the distribution.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE.
35 */
36
37#ifndef MLX4_H
38#define MLX4_H
39
525f5f44 40#include <linux/mutex.h>
225c7b1f 41#include <linux/radix-tree.h>
ee49bd93 42#include <linux/timer.h>
3142788b 43#include <linux/semaphore.h>
27bf91d6 44#include <linux/workqueue.h>
225c7b1f
RD		 45
46#include <linux/mlx4/device.h>
37608eea 47#include <linux/mlx4/driver.h>
225c7b1f 48#include <linux/mlx4/doorbell.h>
623ed84b 49#include <linux/mlx4/cmd.h>
225c7b1f
RD		 50
51#define DRV_NAME "mlx4_core"
ab9c17a0 52#define PFX DRV_NAME ": "
7d4b6bcc
YP		 53#define DRV_VERSION "1.1"
54#define DRV_RELDATE "Dec, 2011"
225c7b1f
RD		 55
56enum {
57 MLX4_HCR_BASE = 0x80680,
58 MLX4_HCR_SIZE = 0x0001c,
623ed84b
JM		 59 MLX4_CLR_INT_SIZE = 0x00008,
60 MLX4_SLAVE_COMM_BASE = 0x0,
61 MLX4_COMM_PAGESIZE = 0x1000
225c7b1f
RD		 62};
63
225c7b1f 64enum {
0ec2c0f8
EE		 65 MLX4_MAX_MGM_ENTRY_SIZE = 0x1000,
66 MLX4_MAX_QP_PER_MGM = 4 * (MLX4_MAX_MGM_ENTRY_SIZE / 16 - 2),
67 MLX4_MTT_ENTRY_PER_SEG = 8,
225c7b1f
RD		 68};
69
225c7b1f
RD		 70enum {
71 MLX4_NUM_PDS = 1 << 15
72};
73
74enum {
75 MLX4_CMPT_TYPE_QP = 0,
76 MLX4_CMPT_TYPE_SRQ = 1,
77 MLX4_CMPT_TYPE_CQ = 2,
78 MLX4_CMPT_TYPE_EQ = 3,
79 MLX4_CMPT_NUM_TYPE
80};
81
82enum {
83 MLX4_CMPT_SHIFT = 24,
84 MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT
85};
86
623ed84b
JM		 87enum mlx4_mr_state {
88 MLX4_MR_DISABLED = 0,
89 MLX4_MR_EN_HW,
90 MLX4_MR_EN_SW
91};
92
93#define MLX4_COMM_TIME 10000
94enum {
95 MLX4_COMM_CMD_RESET,
96 MLX4_COMM_CMD_VHCR0,
97 MLX4_COMM_CMD_VHCR1,
98 MLX4_COMM_CMD_VHCR2,
99 MLX4_COMM_CMD_VHCR_EN,
100 MLX4_COMM_CMD_VHCR_POST,
101 MLX4_COMM_CMD_FLR = 254
102};
103
104/*The flag indicates that the slave should delay the RESET cmd*/
105#define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb
106/*indicates how many retries will be done if we are in the middle of FLR*/
107#define NUM_OF_RESET_RETRIES 10
108#define SLEEP_TIME_IN_RESET (2 * 1000)
109enum mlx4_resource {
110 RES_QP,
111 RES_CQ,
112 RES_SRQ,
113 RES_XRCD,
114 RES_MPT,
115 RES_MTT,
116 RES_MAC,
117 RES_VLAN,
118 RES_EQ,
119 RES_COUNTER,
120 MLX4_NUM_OF_RESOURCE_TYPE
121};
122
123enum mlx4_alloc_mode {
124 RES_OP_RESERVE,
125 RES_OP_RESERVE_AND_MAP,
126 RES_OP_MAP_ICM,
127};
128
129
130/*
131 *Virtual HCR structures.
132 * mlx4_vhcr is the sw representation, in machine endianess
133 *
134 * mlx4_vhcr_cmd is the formalized structure, the one that is passed
135 * to FW to go through communication channel.
136 * It is big endian, and has the same structure as the physical HCR
137 * used by command interface
138 */
139struct mlx4_vhcr {
140 u64 in_param;
141 u64 out_param;
142 u32 in_modifier;
143 u32 errno;
144 u16 op;
145 u16 token;
146 u8 op_modifier;
147 u8 e_bit;
148};
149
150struct mlx4_vhcr_cmd {
151 __be64 in_param;
152 __be32 in_modifier;
153 __be64 out_param;
154 __be16 token;
155 u16 reserved;
156 u8 status;
157 u8 flags;
158 __be16 opcode;
159};
160
161struct mlx4_cmd_info {
162 u16 opcode;
163 bool has_inbox;
164 bool has_outbox;
165 bool out_is_imm;
166 bool encode_slave_id;
167 int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
168 struct mlx4_cmd_mailbox *inbox);
169 int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr,
170 struct mlx4_cmd_mailbox *inbox,
171 struct mlx4_cmd_mailbox *outbox,
172 struct mlx4_cmd_info *cmd);
173};
174
225c7b1f
RD		 175#ifdef CONFIG_MLX4_DEBUG
176extern int mlx4_debug_level;
7b0f5df4
RD		 177#else /* CONFIG_MLX4_DEBUG */
178#define mlx4_debug_level (0)
179#endif /* CONFIG_MLX4_DEBUG */
225c7b1f
RD		 180
181#define mlx4_dbg(mdev, format, arg...) \
0a645e80
JP		 182do { \
183 if (mlx4_debug_level) \
184 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ##arg); \
185} while (0)
225c7b1f 186
225c7b1f 187#define mlx4_err(mdev, format, arg...) \
0a645e80 188 dev_err(&mdev->pdev->dev, format, ##arg)
225c7b1f 189#define mlx4_info(mdev, format, arg...) \
0a645e80 190 dev_info(&mdev->pdev->dev, format, ##arg)
225c7b1f 191#define mlx4_warn(mdev, format, arg...) \
0a645e80 192 dev_warn(&mdev->pdev->dev, format, ##arg)
225c7b1f 193
0ec2c0f8 194extern int mlx4_log_num_mgm_entry_size;
2b8fb286 195extern int log_mtts_per_seg;
0ec2c0f8 196
623ed84b
JM		 197#define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF)
198#define ALL_SLAVES 0xff
199
225c7b1f
RD		 200struct mlx4_bitmap {
201 u32 last;
202 u32 top;
203 u32 max;
93fc9e1b 204 u32 reserved_top;
225c7b1f 205 u32 mask;
42d1e017 206 u32 avail;
225c7b1f
RD		 207 spinlock_t lock;
208 unsigned long *table;
209};
210
211struct mlx4_buddy {
212 unsigned long **bits;
e4044cfc 213 unsigned int *num_free;
225c7b1f
RD		 214 int max_order;
215 spinlock_t lock;
216};
217
218struct mlx4_icm;
219
220struct mlx4_icm_table {
221 u64 virt;
222 int num_icm;
223 int num_obj;
224 int obj_size;
225 int lowmem;
5b0bf5e2 226 int coherent;
225c7b1f
RD		 227 struct mutex mutex;
228 struct mlx4_icm **icm;
229};
230
c82e9aa0
EC		 231/*
232 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
233 */
234struct mlx4_mpt_entry {
235 __be32 flags;
236 __be32 qpn;
237 __be32 key;
238 __be32 pd_flags;
239 __be64 start;
240 __be64 length;
241 __be32 lkey;
242 __be32 win_cnt;
243 u8 reserved1[3];
244 u8 mtt_rep;
2b8fb286 245 __be64 mtt_addr;
c82e9aa0
EC		 246 __be32 mtt_sz;
247 __be32 entity_size;
248 __be32 first_byte_offset;
249} __packed;
250
251/*
252 * Must be packed because start is 64 bits but only aligned to 32 bits.
253 */
254struct mlx4_eq_context {
255 __be32 flags;
256 u16 reserved1[3];
257 __be16 page_offset;
258 u8 log_eq_size;
259 u8 reserved2[4];
260 u8 eq_period;
261 u8 reserved3;
262 u8 eq_max_count;
263 u8 reserved4[3];
264 u8 intr;
265 u8 log_page_size;
266 u8 reserved5[2];
267 u8 mtt_base_addr_h;
268 __be32 mtt_base_addr_l;
269 u32 reserved6[2];
270 __be32 consumer_index;
271 __be32 producer_index;
272 u32 reserved7[4];
273};
274
275struct mlx4_cq_context {
276 __be32 flags;
277 u16 reserved1[3];
278 __be16 page_offset;
279 __be32 logsize_usrpage;
280 __be16 cq_period;
281 __be16 cq_max_count;
282 u8 reserved2[3];
283 u8 comp_eqn;
284 u8 log_page_size;
285 u8 reserved3[2];
286 u8 mtt_base_addr_h;
287 __be32 mtt_base_addr_l;
288 __be32 last_notified_index;
289 __be32 solicit_producer_index;
290 __be32 consumer_index;
291 __be32 producer_index;
292 u32 reserved4[2];
293 __be64 db_rec_addr;
294};
295
296struct mlx4_srq_context {
297 __be32 state_logsize_srqn;
298 u8 logstride;
299 u8 reserved1;
300 __be16 xrcd;
301 __be32 pg_offset_cqn;
302 u32 reserved2;
303 u8 log_page_size;
304 u8 reserved3[2];
305 u8 mtt_base_addr_h;
306 __be32 mtt_base_addr_l;
307 __be32 pd;
308 __be16 limit_watermark;
309 __be16 wqe_cnt;
310 u16 reserved4;
311 __be16 wqe_counter;
312 u32 reserved5;
313 __be64 db_rec_addr;
314};
315
623ed84b
JM		 316struct mlx4_eqe {
317 u8 reserved1;
318 u8 type;
319 u8 reserved2;
320 u8 subtype;
321 union {
322 u32 raw[6];
323 struct {
324 __be32 cqn;
325 } __packed comp;
326 struct {
327 u16 reserved1;
328 __be16 token;
329 u32 reserved2;
330 u8 reserved3[3];
331 u8 status;
332 __be64 out_param;
333 } __packed cmd;
334 struct {
335 __be32 qpn;
336 } __packed qp;
337 struct {
338 __be32 srqn;
339 } __packed srq;
340 struct {
341 __be32 cqn;
342 u32 reserved1;
343 u8 reserved2[3];
344 u8 syndrome;
345 } __packed cq_err;
346 struct {
347 u32 reserved1[2];
348 __be32 port;
349 } __packed port_change;
350 struct {
351 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
352 u32 reserved;
353 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
354 } __packed comm_channel_arm;
355 struct {
356 u8 port;
357 u8 reserved[3];
358 __be64 mac;
359 } __packed mac_update;
360 struct {
361 u8 port;
362 } __packed sw_event;
363 struct {
364 __be32 slave_id;
365 } __packed flr_event;
366 } event;
367 u8 slave_id;
368 u8 reserved3[2];
369 u8 owner;
370} __packed;
371
225c7b1f
RD		 372struct mlx4_eq {
373 struct mlx4_dev *dev;
374 void __iomem *doorbell;
375 int eqn;
376 u32 cons_index;
377 u16 irq;
378 u16 have_irq;
379 int nent;
380 struct mlx4_buf_list *page_list;
381 struct mlx4_mtt mtt;
382};
383
623ed84b
JM		 384struct mlx4_slave_eqe {
385 u8 type;
386 u8 port;
387 u32 param;
388};
389
390struct mlx4_slave_event_eq_info {
391 u32 eqn;
392 u16 token;
393 u64 event_type;
394};
395
225c7b1f
RD		 396struct mlx4_profile {
397 int num_qp;
398 int rdmarc_per_qp;
399 int num_srq;
400 int num_cq;
401 int num_mcg;
402 int num_mpt;
403 int num_mtt;
404};
405
406struct mlx4_fw {
407 u64 clr_int_base;
408 u64 catas_offset;
623ed84b 409 u64 comm_base;
225c7b1f
RD		 410 struct mlx4_icm *fw_icm;
411 struct mlx4_icm *aux_icm;
412 u32 catas_size;
413 u16 fw_pages;
414 u8 clr_int_bar;
415 u8 catas_bar;
623ed84b
JM		 416 u8 comm_bar;
417};
418
419struct mlx4_comm {
420 u32 slave_write;
421 u32 slave_read;
225c7b1f
RD		 422};
423
ffe455ad
EE		 424enum {
425 MLX4_MCAST_CONFIG = 0,
426 MLX4_MCAST_DISABLE = 1,
427 MLX4_MCAST_ENABLE = 2,
428};
429
623ed84b
JM		 430#define VLAN_FLTR_SIZE 128
431
432struct mlx4_vlan_fltr {
433 __be32 entry[VLAN_FLTR_SIZE];
434};
435
ffe455ad
EE		 436struct mlx4_mcast_entry {
437 struct list_head list;
438 u64 addr;
439};
440
b12d93d6
YP		 441struct mlx4_promisc_qp {
442 struct list_head list;
443 u32 qpn;
444};
445
446struct mlx4_steer_index {
447 struct list_head list;
448 unsigned int index;
449 struct list_head duplicates;
450};
451
623ed84b
JM		 452struct mlx4_slave_state {
453 u8 comm_toggle;
454 u8 last_cmd;
455 u8 init_port_mask;
456 bool active;
457 u8 function;
458 dma_addr_t vhcr_dma;
459 u16 mtu[MLX4_MAX_PORTS + 1];
460 __be32 ib_cap_mask[MLX4_MAX_PORTS + 1];
461 struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES];
462 struct list_head mcast_filters[MLX4_MAX_PORTS + 1];
463 struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1];
464 struct mlx4_slave_event_eq_info event_eq;
465 u16 eq_pi;
466 u16 eq_ci;
467 spinlock_t lock;
468 /*initialized via the kzalloc*/
469 u8 is_slave_going_down;
470 u32 cookie;
471};
472
473struct slave_list {
474 struct mutex mutex;
475 struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE];
476};
477
478struct mlx4_resource_tracker {
479 spinlock_t lock;
480 /* tree for each resources */
481 struct radix_tree_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE];
482 /* num_of_slave's lists, one per slave */
483 struct slave_list *slave_list;
484};
485
486#define SLAVE_EVENT_EQ_SIZE 128
487struct mlx4_slave_event_eq {
488 u32 eqn;
489 u32 cons;
490 u32 prod;
491 struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE];
492};
493
494struct mlx4_master_qp0_state {
495 int proxy_qp0_active;
496 int qp0_active;
497 int port_active;
498};
499
500struct mlx4_mfunc_master_ctx {
501 struct mlx4_slave_state *slave_state;
502 struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1];
503 int init_port_ref[MLX4_MAX_PORTS + 1];
504 u16 max_mtu[MLX4_MAX_PORTS + 1];
505 int disable_mcast_ref[MLX4_MAX_PORTS + 1];
506 struct mlx4_resource_tracker res_tracker;
507 struct workqueue_struct *comm_wq;
508 struct work_struct comm_work;
509 struct work_struct slave_event_work;
510 struct work_struct slave_flr_event_work;
511 spinlock_t slave_state_lock;
f5311ac1 512 __be32 comm_arm_bit_vector[4];
623ed84b
JM		 513 struct mlx4_eqe cmd_eqe;
514 struct mlx4_slave_event_eq slave_eq;
515 struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX];
516};
517
518struct mlx4_mfunc {
519 struct mlx4_comm __iomem *comm;
520 struct mlx4_vhcr_cmd *vhcr;
521 dma_addr_t vhcr_dma;
522
523 struct mlx4_mfunc_master_ctx master;
524};
525
225c7b1f
RD		 526struct mlx4_cmd {
527 struct pci_pool *pool;
528 void __iomem *hcr;
529 struct mutex hcr_mutex;
530 struct semaphore poll_sem;
531 struct semaphore event_sem;
623ed84b 532 struct semaphore slave_sem;
225c7b1f
RD		 533 int max_cmds;
534 spinlock_t context_lock;
535 int free_head;
536 struct mlx4_cmd_context *context;
537 u16 token_mask;
538 u8 use_events;
539 u8 toggle;
623ed84b 540 u8 comm_toggle;
225c7b1f
RD		 541};
542
543struct mlx4_uar_table {
544 struct mlx4_bitmap bitmap;
545};
546
547struct mlx4_mr_table {
548 struct mlx4_bitmap mpt_bitmap;
549 struct mlx4_buddy mtt_buddy;
550 u64 mtt_base;
551 u64 mpt_base;
552 struct mlx4_icm_table mtt_table;
553 struct mlx4_icm_table dmpt_table;
554};
555
556struct mlx4_cq_table {
557 struct mlx4_bitmap bitmap;
558 spinlock_t lock;
559 struct radix_tree_root tree;
560 struct mlx4_icm_table table;
561 struct mlx4_icm_table cmpt_table;
562};
563
564struct mlx4_eq_table {
565 struct mlx4_bitmap bitmap;
b8dd786f 566 char *irq_names;
225c7b1f 567 void __iomem *clr_int;
b8dd786f 568 void __iomem **uar_map;
225c7b1f 569 u32 clr_mask;
b8dd786f 570 struct mlx4_eq *eq;
fa0681d2 571 struct mlx4_icm_table table;
225c7b1f
RD		 572 struct mlx4_icm_table cmpt_table;
573 int have_irq;
574 u8 inta_pin;
575};
576
577struct mlx4_srq_table {
578 struct mlx4_bitmap bitmap;
579 spinlock_t lock;
580 struct radix_tree_root tree;
581 struct mlx4_icm_table table;
582 struct mlx4_icm_table cmpt_table;
583};
584
585struct mlx4_qp_table {
586 struct mlx4_bitmap bitmap;
587 u32 rdmarc_base;
588 int rdmarc_shift;
589 spinlock_t lock;
590 struct mlx4_icm_table qp_table;
591 struct mlx4_icm_table auxc_table;
592 struct mlx4_icm_table altc_table;
593 struct mlx4_icm_table rdmarc_table;
594 struct mlx4_icm_table cmpt_table;
595};
596
597struct mlx4_mcg_table {
598 struct mutex mutex;
599 struct mlx4_bitmap bitmap;
600 struct mlx4_icm_table table;
601};
602
603struct mlx4_catas_err {
604 u32 __iomem *map;
ee49bd93
JM		 605 struct timer_list timer;
606 struct list_head list;
225c7b1f
RD		 607};
608
2a2336f8
YP		 609#define MLX4_MAX_MAC_NUM 128
610#define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3)
611
612struct mlx4_mac_table {
613 __be64 entries[MLX4_MAX_MAC_NUM];
614 int refs[MLX4_MAX_MAC_NUM];
615 struct mutex mutex;
616 int total;
617 int max;
618};
619
620#define MLX4_MAX_VLAN_NUM 128
621#define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2)
622
623struct mlx4_vlan_table {
624 __be32 entries[MLX4_MAX_VLAN_NUM];
625 int refs[MLX4_MAX_VLAN_NUM];
626 struct mutex mutex;
627 int total;
628 int max;
629};
630
ffe455ad
EE		 631#define SET_PORT_GEN_ALL_VALID 0x7
632#define SET_PORT_PROMISC_SHIFT 31
633#define SET_PORT_MC_PROMISC_SHIFT 30
634
635enum {
636 MCAST_DIRECT_ONLY = 0,
637 MCAST_DIRECT = 1,
638 MCAST_DEFAULT = 2
639};
640
641
642struct mlx4_set_port_general_context {
643 u8 reserved[3];
644 u8 flags;
645 u16 reserved2;
646 __be16 mtu;
647 u8 pptx;
648 u8 pfctx;
649 u16 reserved3;
650 u8 pprx;
651 u8 pfcrx;
652 u16 reserved4;
653};
654
655struct mlx4_set_port_rqp_calc_context {
656 __be32 base_qpn;
657 u8 rererved;
658 u8 n_mac;
659 u8 n_vlan;
660 u8 n_prio;
661 u8 reserved2[3];
662 u8 mac_miss;
663 u8 intra_no_vlan;
664 u8 no_vlan;
665 u8 intra_vlan_miss;
666 u8 vlan_miss;
667 u8 reserved3[3];
668 u8 no_vlan_prio;
669 __be32 promisc;
670 __be32 mcast;
671};
672
1679200f
YP		 673struct mlx4_mac_entry {
674 u64 mac;
675};
676
2a2336f8
YP		 677struct mlx4_port_info {
678 struct mlx4_dev *dev;
679 int port;
7ff93f8b
YP		 680 char dev_name[16];
681 struct device_attribute port_attr;
682 enum mlx4_port_type tmp_type;
2a2336f8 683 struct mlx4_mac_table mac_table;
1679200f 684 struct radix_tree_root mac_tree;
2a2336f8 685 struct mlx4_vlan_table vlan_table;
1679200f 686 int base_qpn;
2a2336f8
YP		 687};
688
27bf91d6
YP		 689struct mlx4_sense {
690 struct mlx4_dev *dev;
691 u8 do_sense_port[MLX4_MAX_PORTS + 1];
692 u8 sense_allowed[MLX4_MAX_PORTS + 1];
693 struct delayed_work sense_poll;
694};
695
0b7ca5a9
YP		 696struct mlx4_msix_ctl {
697 u64 pool_bm;
698 spinlock_t pool_lock;
699};
700
b12d93d6
YP		 701struct mlx4_steer {
702 struct list_head promisc_qps[MLX4_NUM_STEERS];
703 struct list_head steer_entries[MLX4_NUM_STEERS];
704 struct list_head high_prios;
705};
706
225c7b1f
RD		 707struct mlx4_priv {
708 struct mlx4_dev dev;
709
710 struct list_head dev_list;
711 struct list_head ctx_list;
712 spinlock_t ctx_lock;
713
6296883c
YP		 714 struct list_head pgdir_list;
715 struct mutex pgdir_mutex;
716
225c7b1f
RD		 717 struct mlx4_fw fw;
718 struct mlx4_cmd cmd;
623ed84b 719 struct mlx4_mfunc mfunc;
225c7b1f
RD		 720
721 struct mlx4_bitmap pd_bitmap;
012a8ff5 722 struct mlx4_bitmap xrcd_bitmap;
225c7b1f
RD		 723 struct mlx4_uar_table uar_table;
724 struct mlx4_mr_table mr_table;
725 struct mlx4_cq_table cq_table;
726 struct mlx4_eq_table eq_table;
727 struct mlx4_srq_table srq_table;
728 struct mlx4_qp_table qp_table;
729 struct mlx4_mcg_table mcg_table;
f2a3f6a3 730 struct mlx4_bitmap counters_bitmap;
225c7b1f
RD		 731
732 struct mlx4_catas_err catas_err;
733
734 void __iomem *clr_base;
735
736 struct mlx4_uar driver_uar;
737 void __iomem *kar;
2a2336f8 738 struct mlx4_port_info port[MLX4_MAX_PORTS + 1];
27bf91d6 739 struct mlx4_sense sense;
7ff93f8b 740 struct mutex port_mutex;
0b7ca5a9 741 struct mlx4_msix_ctl msix_ctl;
b12d93d6 742 struct mlx4_steer *steer;
c1b43dca
EC		 743 struct list_head bf_list;
744 struct mutex bf_mutex;
745 struct io_mapping *bf_mapping;
ea51b377 746 int reserved_mtts;
225c7b1f
RD		 747};
748
749static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev)
750{
751 return container_of(dev, struct mlx4_priv, dev);
752}
753
27bf91d6
YP		 754#define MLX4_SENSE_RANGE (HZ * 3)
755
756extern struct workqueue_struct *mlx4_wq;
757
225c7b1f
RD		 758u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap);
759void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj);
a3cdcbfa
YP		 760u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align);
761void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt);
42d1e017 762u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap);
93fc9e1b
YP		 763int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask,
764 u32 reserved_bot, u32 resetrved_top);
225c7b1f
RD		 765void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap);
766
767int mlx4_reset(struct mlx4_dev *dev);
768
b8dd786f
YP		 769int mlx4_alloc_eq_table(struct mlx4_dev *dev);
770void mlx4_free_eq_table(struct mlx4_dev *dev);
771
225c7b1f 772int mlx4_init_pd_table(struct mlx4_dev *dev);
012a8ff5 773int mlx4_init_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 774int mlx4_init_uar_table(struct mlx4_dev *dev);
775int mlx4_init_mr_table(struct mlx4_dev *dev);
776int mlx4_init_eq_table(struct mlx4_dev *dev);
777int mlx4_init_cq_table(struct mlx4_dev *dev);
778int mlx4_init_qp_table(struct mlx4_dev *dev);
779int mlx4_init_srq_table(struct mlx4_dev *dev);
780int mlx4_init_mcg_table(struct mlx4_dev *dev);
781
782void mlx4_cleanup_pd_table(struct mlx4_dev *dev);
012a8ff5 783void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev);
225c7b1f
RD		 784void mlx4_cleanup_uar_table(struct mlx4_dev *dev);
785void mlx4_cleanup_mr_table(struct mlx4_dev *dev);
786void mlx4_cleanup_eq_table(struct mlx4_dev *dev);
787void mlx4_cleanup_cq_table(struct mlx4_dev *dev);
788void mlx4_cleanup_qp_table(struct mlx4_dev *dev);
789void mlx4_cleanup_srq_table(struct mlx4_dev *dev);
790void mlx4_cleanup_mcg_table(struct mlx4_dev *dev);
c82e9aa0
EC		 791int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn);
792void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn);
793int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn);
794void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn);
795int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn);
796void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn);
797int __mlx4_mr_reserve(struct mlx4_dev *dev);
798void __mlx4_mr_release(struct mlx4_dev *dev, u32 index);
799int __mlx4_mr_alloc_icm(struct mlx4_dev *dev, u32 index);
800void __mlx4_mr_free_icm(struct mlx4_dev *dev, u32 index);
801u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order);
802void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order);
225c7b1f 803
623ed84b
JM		 804int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
805 struct mlx4_vhcr *vhcr,
806 struct mlx4_cmd_mailbox *inbox,
807 struct mlx4_cmd_mailbox *outbox,
808 struct mlx4_cmd_info *cmd);
809int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave,
810 struct mlx4_vhcr *vhcr,
811 struct mlx4_cmd_mailbox *inbox,
812 struct mlx4_cmd_mailbox *outbox,
813 struct mlx4_cmd_info *cmd);
814int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
815 struct mlx4_vhcr *vhcr,
816 struct mlx4_cmd_mailbox *inbox,
817 struct mlx4_cmd_mailbox *outbox,
818 struct mlx4_cmd_info *cmd);
819int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
820 struct mlx4_vhcr *vhcr,
821 struct mlx4_cmd_mailbox *inbox,
822 struct mlx4_cmd_mailbox *outbox,
823 struct mlx4_cmd_info *cmd);
824int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
825 struct mlx4_vhcr *vhcr,
826 struct mlx4_cmd_mailbox *inbox,
827 struct mlx4_cmd_mailbox *outbox,
828 struct mlx4_cmd_info *cmd);
829int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
830 struct mlx4_vhcr *vhcr,
831 struct mlx4_cmd_mailbox *inbox,
832 struct mlx4_cmd_mailbox *outbox,
833 struct mlx4_cmd_info *cmd);
834int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave,
835 struct mlx4_vhcr *vhcr,
836 struct mlx4_cmd_mailbox *inbox,
837 struct mlx4_cmd_mailbox *outbox,
838 struct mlx4_cmd_info *cmd);
c82e9aa0
EC		 839int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align,
840 int *base);
841void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
842int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
843void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
844int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
845int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
846 int start_index, int npages, u64 *page_list);
623ed84b 847
ee49bd93
JM		 848void mlx4_start_catas_poll(struct mlx4_dev *dev);
849void mlx4_stop_catas_poll(struct mlx4_dev *dev);
27bf91d6 850void mlx4_catas_init(void);
ee49bd93 851int mlx4_restart_one(struct pci_dev *pdev);
225c7b1f
RD		 852int mlx4_register_device(struct mlx4_dev *dev);
853void mlx4_unregister_device(struct mlx4_dev *dev);
37608eea 854void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, int port);
225c7b1f
RD		 855
856struct mlx4_dev_cap;
857struct mlx4_init_hca_param;
858
859u64 mlx4_make_profile(struct mlx4_dev *dev,
860 struct mlx4_profile *request,
861 struct mlx4_dev_cap *dev_cap,
862 struct mlx4_init_hca_param *init_hca);
623ed84b
JM		 863void mlx4_master_comm_channel(struct work_struct *work);
864void mlx4_gen_slave_eqe(struct work_struct *work);
865void mlx4_master_handle_slave_flr(struct work_struct *work);
866
867int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
868 struct mlx4_vhcr *vhcr,
869 struct mlx4_cmd_mailbox *inbox,
870 struct mlx4_cmd_mailbox *outbox,
871 struct mlx4_cmd_info *cmd);
872int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
873 struct mlx4_vhcr *vhcr,
874 struct mlx4_cmd_mailbox *inbox,
875 struct mlx4_cmd_mailbox *outbox,
876 struct mlx4_cmd_info *cmd);
877int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave,
878 struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox,
879 struct mlx4_cmd_mailbox *outbox,
880 struct mlx4_cmd_info *cmd);
881int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave,
882 struct mlx4_vhcr *vhcr,
883 struct mlx4_cmd_mailbox *inbox,
884 struct mlx4_cmd_mailbox *outbox,
885 struct mlx4_cmd_info *cmd);
886int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
887 struct mlx4_vhcr *vhcr,
888 struct mlx4_cmd_mailbox *inbox,
889 struct mlx4_cmd_mailbox *outbox,
890 struct mlx4_cmd_info *cmd);
891int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
892 struct mlx4_vhcr *vhcr,
893 struct mlx4_cmd_mailbox *inbox,
894 struct mlx4_cmd_mailbox *outbox,
895 struct mlx4_cmd_info *cmd);
896int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
897 struct mlx4_vhcr *vhcr,
898 struct mlx4_cmd_mailbox *inbox,
899 struct mlx4_cmd_mailbox *outbox,
900 struct mlx4_cmd_info *cmd);
901int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
902 struct mlx4_vhcr *vhcr,
903 struct mlx4_cmd_mailbox *inbox,
904 struct mlx4_cmd_mailbox *outbox,
905 struct mlx4_cmd_info *cmd);
906int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
907 struct mlx4_vhcr *vhcr,
908 struct mlx4_cmd_mailbox *inbox,
909 struct mlx4_cmd_mailbox *outbox,
910 struct mlx4_cmd_info *cmd);
911int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
912 struct mlx4_vhcr *vhcr,
913 struct mlx4_cmd_mailbox *inbox,
914 struct mlx4_cmd_mailbox *outbox,
915 struct mlx4_cmd_info *cmd);
916int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
917 struct mlx4_vhcr *vhcr,
918 struct mlx4_cmd_mailbox *inbox,
919 struct mlx4_cmd_mailbox *outbox,
920 struct mlx4_cmd_info *cmd);
921int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
922 struct mlx4_vhcr *vhcr,
923 struct mlx4_cmd_mailbox *inbox,
924 struct mlx4_cmd_mailbox *outbox,
925 struct mlx4_cmd_info *cmd);
926int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
927 struct mlx4_vhcr *vhcr,
928 struct mlx4_cmd_mailbox *inbox,
929 struct mlx4_cmd_mailbox *outbox,
930 struct mlx4_cmd_info *cmd);
931int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
932 struct mlx4_vhcr *vhcr,
933 struct mlx4_cmd_mailbox *inbox,
934 struct mlx4_cmd_mailbox *outbox,
935 struct mlx4_cmd_info *cmd);
936int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
937 struct mlx4_vhcr *vhcr,
938 struct mlx4_cmd_mailbox *inbox,
939 struct mlx4_cmd_mailbox *outbox,
940 struct mlx4_cmd_info *cmd);
941int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
942 struct mlx4_vhcr *vhcr,
943 struct mlx4_cmd_mailbox *inbox,
944 struct mlx4_cmd_mailbox *outbox,
945 struct mlx4_cmd_info *cmd);
946int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
947 struct mlx4_vhcr *vhcr,
948 struct mlx4_cmd_mailbox *inbox,
949 struct mlx4_cmd_mailbox *outbox,
950 struct mlx4_cmd_info *cmd);
951int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
952 struct mlx4_vhcr *vhcr,
953 struct mlx4_cmd_mailbox *inbox,
954 struct mlx4_cmd_mailbox *outbox,
955 struct mlx4_cmd_info *cmd);
956
957int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe);
225c7b1f 958
225c7b1f
RD		 959int mlx4_cmd_init(struct mlx4_dev *dev);
960void mlx4_cmd_cleanup(struct mlx4_dev *dev);
ab9c17a0
JM		 961int mlx4_multi_func_init(struct mlx4_dev *dev);
962void mlx4_multi_func_cleanup(struct mlx4_dev *dev);
225c7b1f
RD		 963void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param);
964int mlx4_cmd_use_events(struct mlx4_dev *dev);
965void mlx4_cmd_use_polling(struct mlx4_dev *dev);
966
ab9c17a0
JM		 967int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param,
968 unsigned long timeout);
969
225c7b1f
RD		 970void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn);
971void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type);
972
973void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type);
974
975void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type);
976
977void mlx4_handle_catas_err(struct mlx4_dev *dev);
978
ab6dc30d
YP		 979int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port,
980 enum mlx4_port_type *type);
27bf91d6
YP		 981void mlx4_do_sense_ports(struct mlx4_dev *dev,
982 enum mlx4_port_type *stype,
983 enum mlx4_port_type *defaults);
984void mlx4_start_sense(struct mlx4_dev *dev);
985void mlx4_stop_sense(struct mlx4_dev *dev);
986void mlx4_sense_init(struct mlx4_dev *dev);
987int mlx4_check_port_params(struct mlx4_dev *dev,
988 enum mlx4_port_type *port_type);
989int mlx4_change_port_types(struct mlx4_dev *dev,
990 enum mlx4_port_type *port_types);
991
2a2336f8
YP		 992void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table);
993void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table);
994
7ff93f8b 995int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port);
623ed84b
JM		 996/* resource tracker functions*/
997int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
998 enum mlx4_resource resource_type,
999 int resource_id, int *slave);
1000void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id);
1001int mlx4_init_resource_tracker(struct mlx4_dev *dev);
1002
1003void mlx4_free_resource_tracker(struct mlx4_dev *dev);
1004
1005int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave,
1006 struct mlx4_vhcr *vhcr,
1007 struct mlx4_cmd_mailbox *inbox,
1008 struct mlx4_cmd_mailbox *outbox,
1009 struct mlx4_cmd_info *cmd);
1010int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave,
1011 struct mlx4_vhcr *vhcr,
1012 struct mlx4_cmd_mailbox *inbox,
1013 struct mlx4_cmd_mailbox *outbox,
1014 struct mlx4_cmd_info *cmd);
1015int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave,
1016 struct mlx4_vhcr *vhcr,
1017 struct mlx4_cmd_mailbox *inbox,
1018 struct mlx4_cmd_mailbox *outbox,
1019 struct mlx4_cmd_info *cmd);
1020int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
1021 struct mlx4_vhcr *vhcr,
1022 struct mlx4_cmd_mailbox *inbox,
1023 struct mlx4_cmd_mailbox *outbox,
1024 struct mlx4_cmd_info *cmd);
9a5aa622 1025int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps);
97285b78 1026int mlx4_check_ext_port_caps(struct mlx4_dev *dev, u8 port);
7ff93f8b 1027
623ed84b
JM		 1028
1029int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
1030 struct mlx4_vhcr *vhcr,
1031 struct mlx4_cmd_mailbox *inbox,
1032 struct mlx4_cmd_mailbox *outbox,
1033 struct mlx4_cmd_info *cmd);
1034
1035int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave,
1036 struct mlx4_vhcr *vhcr,
1037 struct mlx4_cmd_mailbox *inbox,
1038 struct mlx4_cmd_mailbox *outbox,
1039 struct mlx4_cmd_info *cmd);
b12d93d6
YP		 1040int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1041 enum mlx4_protocol prot, enum mlx4_steer_type steer);
1042int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
1043 int block_mcast_loopback, enum mlx4_protocol prot,
1044 enum mlx4_steer_type steer);
623ed84b
JM		 1045int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1046 struct mlx4_vhcr *vhcr,
1047 struct mlx4_cmd_mailbox *inbox,
1048 struct mlx4_cmd_mailbox *outbox,
1049 struct mlx4_cmd_info *cmd);
1050int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave,
1051 struct mlx4_vhcr *vhcr,
1052 struct mlx4_cmd_mailbox *inbox,
1053 struct mlx4_cmd_mailbox *outbox,
1054 struct mlx4_cmd_info *cmd);
1055int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function,
1056 int port, void *buf);
1057int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod,
1058 struct mlx4_cmd_mailbox *outbox);
1059int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave,
1060 struct mlx4_vhcr *vhcr,
1061 struct mlx4_cmd_mailbox *inbox,
1062 struct mlx4_cmd_mailbox *outbox,
1063 struct mlx4_cmd_info *cmd);
1064int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave,
1065 struct mlx4_vhcr *vhcr,
1066 struct mlx4_cmd_mailbox *inbox,
1067 struct mlx4_cmd_mailbox *outbox,
1068 struct mlx4_cmd_info *cmd);
1069int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
1070 struct mlx4_vhcr *vhcr,
1071 struct mlx4_cmd_mailbox *inbox,
1072 struct mlx4_cmd_mailbox *outbox,
1073 struct mlx4_cmd_info *cmd);
f5311ac1 1074
0ec2c0f8
EE		 1075int mlx4_get_mgm_entry_size(struct mlx4_dev *dev);
1076int mlx4_get_qp_per_mgm(struct mlx4_dev *dev);
1077
5cc914f1
MA		 1078static inline void set_param_l(u64 *arg, u32 val)
1079{
1080 *((u32 *)arg) = val;
1081}
1082
1083static inline void set_param_h(u64 *arg, u32 val)
1084{
1085 *arg = (*arg & 0xffffffff) | ((u64) val << 32);
1086}
1087
1088static inline u32 get_param_l(u64 *arg)
1089{
1090 return (u32) (*arg & 0xffffffff);
1091}
1092
1093static inline u32 get_param_h(u64 *arg)
1094{
1095 return (u32)(*arg >> 32);
1096}
1097
c82e9aa0
EC		 1098static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev)
1099{
1100 return &mlx4_priv(dev)->mfunc.master.res_tracker.lock;
1101}
1102
f5311ac1
JM		 1103#define NOT_MASKED_PD_BITS 17
1104
225c7b1f 1105#endif /* MLX4_H */
Linux kernel - Deliverables
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