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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. | |
3 | * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved. | |
4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems. All rights reserved. | |
51a379d0 | 5 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
225c7b1f RD |
6 | * Copyright (c) 2004 Voltaire, Inc. All rights reserved. |
7 | * | |
8 | * This software is available to you under a choice of one of two | |
9 | * licenses. You may choose to be licensed under the terms of the GNU | |
10 | * General Public License (GPL) Version 2, available from the file | |
11 | * COPYING in the main directory of this source tree, or the | |
12 | * OpenIB.org BSD license below: | |
13 | * | |
14 | * Redistribution and use in source and binary forms, with or | |
15 | * without modification, are permitted provided that the following | |
16 | * conditions are met: | |
17 | * | |
18 | * - Redistributions of source code must retain the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer. | |
21 | * | |
22 | * - Redistributions in binary form must reproduce the above | |
23 | * copyright notice, this list of conditions and the following | |
24 | * disclaimer in the documentation and/or other materials | |
25 | * provided with the distribution. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
28 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
29 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
30 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
31 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
32 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
33 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
34 | * SOFTWARE. | |
35 | */ | |
36 | ||
37 | #ifndef MLX4_H | |
38 | #define MLX4_H | |
39 | ||
525f5f44 | 40 | #include <linux/mutex.h> |
225c7b1f | 41 | #include <linux/radix-tree.h> |
4af1c048 | 42 | #include <linux/rbtree.h> |
ee49bd93 | 43 | #include <linux/timer.h> |
3142788b | 44 | #include <linux/semaphore.h> |
27bf91d6 | 45 | #include <linux/workqueue.h> |
225c7b1f RD |
46 | |
47 | #include <linux/mlx4/device.h> | |
37608eea | 48 | #include <linux/mlx4/driver.h> |
225c7b1f | 49 | #include <linux/mlx4/doorbell.h> |
623ed84b | 50 | #include <linux/mlx4/cmd.h> |
225c7b1f RD |
51 | |
52 | #define DRV_NAME "mlx4_core" | |
ab9c17a0 | 53 | #define PFX DRV_NAME ": " |
169a1d85 AV |
54 | #define DRV_VERSION "2.2-1" |
55 | #define DRV_RELDATE "Feb, 2014" | |
225c7b1f | 56 | |
0ff1fb65 HHZ |
57 | #define MLX4_FS_UDP_UC_EN (1 << 1) |
58 | #define MLX4_FS_TCP_UC_EN (1 << 2) | |
59 | #define MLX4_FS_NUM_OF_L2_ADDR 8 | |
60 | #define MLX4_FS_MGM_LOG_ENTRY_SIZE 7 | |
61 | #define MLX4_FS_NUM_MCG (1 << 17) | |
62 | ||
e448834e SM |
63 | #define INIT_HCA_TPT_MW_ENABLE (1 << 7) |
64 | ||
e5395e92 AV |
65 | #define MLX4_NUM_UP 8 |
66 | #define MLX4_NUM_TC 8 | |
67 | #define MLX4_RATELIMIT_UNITS 3 /* 100 Mbps */ | |
68 | #define MLX4_RATELIMIT_DEFAULT 0xffff | |
69 | ||
70 | struct mlx4_set_port_prio2tc_context { | |
71 | u8 prio2tc[4]; | |
72 | }; | |
73 | ||
74 | struct mlx4_port_scheduler_tc_cfg_be { | |
75 | __be16 pg; | |
76 | __be16 bw_precentage; | |
77 | __be16 max_bw_units; /* 3-100Mbps, 4-1Gbps, other values - reserved */ | |
78 | __be16 max_bw_value; | |
79 | }; | |
80 | ||
81 | struct mlx4_set_port_scheduler_context { | |
82 | struct mlx4_port_scheduler_tc_cfg_be tc[MLX4_NUM_TC]; | |
83 | }; | |
84 | ||
225c7b1f RD |
85 | enum { |
86 | MLX4_HCR_BASE = 0x80680, | |
87 | MLX4_HCR_SIZE = 0x0001c, | |
623ed84b JM |
88 | MLX4_CLR_INT_SIZE = 0x00008, |
89 | MLX4_SLAVE_COMM_BASE = 0x0, | |
ddd8a6c1 EE |
90 | MLX4_COMM_PAGESIZE = 0x1000, |
91 | MLX4_CLOCK_SIZE = 0x00008 | |
225c7b1f RD |
92 | }; |
93 | ||
225c7b1f | 94 | enum { |
3c439b55 JM |
95 | MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE = 10, |
96 | MLX4_MIN_MGM_LOG_ENTRY_SIZE = 7, | |
97 | MLX4_MAX_MGM_LOG_ENTRY_SIZE = 12, | |
98 | MLX4_MAX_QP_PER_MGM = 4 * ((1 << MLX4_MAX_MGM_LOG_ENTRY_SIZE) / 16 - 2), | |
0ec2c0f8 | 99 | MLX4_MTT_ENTRY_PER_SEG = 8, |
225c7b1f RD |
100 | }; |
101 | ||
225c7b1f RD |
102 | enum { |
103 | MLX4_NUM_PDS = 1 << 15 | |
104 | }; | |
105 | ||
106 | enum { | |
107 | MLX4_CMPT_TYPE_QP = 0, | |
108 | MLX4_CMPT_TYPE_SRQ = 1, | |
109 | MLX4_CMPT_TYPE_CQ = 2, | |
110 | MLX4_CMPT_TYPE_EQ = 3, | |
111 | MLX4_CMPT_NUM_TYPE | |
112 | }; | |
113 | ||
114 | enum { | |
115 | MLX4_CMPT_SHIFT = 24, | |
116 | MLX4_NUM_CMPTS = MLX4_CMPT_NUM_TYPE << MLX4_CMPT_SHIFT | |
117 | }; | |
118 | ||
b20e519a SM |
119 | enum mlx4_mpt_state { |
120 | MLX4_MPT_DISABLED = 0, | |
121 | MLX4_MPT_EN_HW, | |
122 | MLX4_MPT_EN_SW | |
623ed84b JM |
123 | }; |
124 | ||
125 | #define MLX4_COMM_TIME 10000 | |
126 | enum { | |
127 | MLX4_COMM_CMD_RESET, | |
128 | MLX4_COMM_CMD_VHCR0, | |
129 | MLX4_COMM_CMD_VHCR1, | |
130 | MLX4_COMM_CMD_VHCR2, | |
131 | MLX4_COMM_CMD_VHCR_EN, | |
132 | MLX4_COMM_CMD_VHCR_POST, | |
133 | MLX4_COMM_CMD_FLR = 254 | |
134 | }; | |
135 | ||
99ec41d0 JM |
136 | enum { |
137 | MLX4_VF_SMI_DISABLED, | |
138 | MLX4_VF_SMI_ENABLED | |
139 | }; | |
140 | ||
623ed84b JM |
141 | /*The flag indicates that the slave should delay the RESET cmd*/ |
142 | #define MLX4_DELAY_RESET_SLAVE 0xbbbbbbb | |
143 | /*indicates how many retries will be done if we are in the middle of FLR*/ | |
144 | #define NUM_OF_RESET_RETRIES 10 | |
145 | #define SLEEP_TIME_IN_RESET (2 * 1000) | |
146 | enum mlx4_resource { | |
147 | RES_QP, | |
148 | RES_CQ, | |
149 | RES_SRQ, | |
150 | RES_XRCD, | |
151 | RES_MPT, | |
152 | RES_MTT, | |
153 | RES_MAC, | |
154 | RES_VLAN, | |
155 | RES_EQ, | |
156 | RES_COUNTER, | |
1b9c6b06 | 157 | RES_FS_RULE, |
623ed84b JM |
158 | MLX4_NUM_OF_RESOURCE_TYPE |
159 | }; | |
160 | ||
161 | enum mlx4_alloc_mode { | |
162 | RES_OP_RESERVE, | |
163 | RES_OP_RESERVE_AND_MAP, | |
164 | RES_OP_MAP_ICM, | |
165 | }; | |
166 | ||
b8924951 JM |
167 | enum mlx4_res_tracker_free_type { |
168 | RES_TR_FREE_ALL, | |
169 | RES_TR_FREE_SLAVES_ONLY, | |
170 | RES_TR_FREE_STRUCTS_ONLY, | |
171 | }; | |
623ed84b JM |
172 | |
173 | /* | |
174 | *Virtual HCR structures. | |
175 | * mlx4_vhcr is the sw representation, in machine endianess | |
176 | * | |
177 | * mlx4_vhcr_cmd is the formalized structure, the one that is passed | |
178 | * to FW to go through communication channel. | |
179 | * It is big endian, and has the same structure as the physical HCR | |
180 | * used by command interface | |
181 | */ | |
182 | struct mlx4_vhcr { | |
183 | u64 in_param; | |
184 | u64 out_param; | |
185 | u32 in_modifier; | |
186 | u32 errno; | |
187 | u16 op; | |
188 | u16 token; | |
189 | u8 op_modifier; | |
190 | u8 e_bit; | |
191 | }; | |
192 | ||
193 | struct mlx4_vhcr_cmd { | |
194 | __be64 in_param; | |
195 | __be32 in_modifier; | |
196 | __be64 out_param; | |
197 | __be16 token; | |
198 | u16 reserved; | |
199 | u8 status; | |
200 | u8 flags; | |
201 | __be16 opcode; | |
202 | }; | |
203 | ||
204 | struct mlx4_cmd_info { | |
205 | u16 opcode; | |
206 | bool has_inbox; | |
207 | bool has_outbox; | |
208 | bool out_is_imm; | |
209 | bool encode_slave_id; | |
210 | int (*verify)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, | |
211 | struct mlx4_cmd_mailbox *inbox); | |
212 | int (*wrapper)(struct mlx4_dev *dev, int slave, struct mlx4_vhcr *vhcr, | |
213 | struct mlx4_cmd_mailbox *inbox, | |
214 | struct mlx4_cmd_mailbox *outbox, | |
215 | struct mlx4_cmd_info *cmd); | |
216 | }; | |
217 | ||
225c7b1f RD |
218 | #ifdef CONFIG_MLX4_DEBUG |
219 | extern int mlx4_debug_level; | |
7b0f5df4 RD |
220 | #else /* CONFIG_MLX4_DEBUG */ |
221 | #define mlx4_debug_level (0) | |
222 | #endif /* CONFIG_MLX4_DEBUG */ | |
225c7b1f | 223 | |
1a91de28 | 224 | #define mlx4_dbg(mdev, format, ...) \ |
0a645e80 JP |
225 | do { \ |
226 | if (mlx4_debug_level) \ | |
1a91de28 JP |
227 | dev_printk(KERN_DEBUG, &(mdev)->pdev->dev, format, \ |
228 | ##__VA_ARGS__); \ | |
0a645e80 | 229 | } while (0) |
225c7b1f | 230 | |
1a91de28 JP |
231 | #define mlx4_err(mdev, format, ...) \ |
232 | dev_err(&(mdev)->pdev->dev, format, ##__VA_ARGS__) | |
233 | #define mlx4_info(mdev, format, ...) \ | |
234 | dev_info(&(mdev)->pdev->dev, format, ##__VA_ARGS__) | |
235 | #define mlx4_warn(mdev, format, ...) \ | |
236 | dev_warn(&(mdev)->pdev->dev, format, ##__VA_ARGS__) | |
225c7b1f | 237 | |
0ec2c0f8 | 238 | extern int mlx4_log_num_mgm_entry_size; |
2b8fb286 | 239 | extern int log_mtts_per_seg; |
0ec2c0f8 | 240 | |
623ed84b JM |
241 | #define MLX4_MAX_NUM_SLAVES (MLX4_MAX_NUM_PF + MLX4_MAX_NUM_VF) |
242 | #define ALL_SLAVES 0xff | |
243 | ||
225c7b1f RD |
244 | struct mlx4_bitmap { |
245 | u32 last; | |
246 | u32 top; | |
247 | u32 max; | |
93fc9e1b | 248 | u32 reserved_top; |
225c7b1f | 249 | u32 mask; |
42d1e017 | 250 | u32 avail; |
225c7b1f RD |
251 | spinlock_t lock; |
252 | unsigned long *table; | |
253 | }; | |
254 | ||
255 | struct mlx4_buddy { | |
256 | unsigned long **bits; | |
e4044cfc | 257 | unsigned int *num_free; |
3de819e6 | 258 | u32 max_order; |
225c7b1f RD |
259 | spinlock_t lock; |
260 | }; | |
261 | ||
262 | struct mlx4_icm; | |
263 | ||
264 | struct mlx4_icm_table { | |
265 | u64 virt; | |
266 | int num_icm; | |
3de819e6 | 267 | u32 num_obj; |
225c7b1f RD |
268 | int obj_size; |
269 | int lowmem; | |
5b0bf5e2 | 270 | int coherent; |
225c7b1f RD |
271 | struct mutex mutex; |
272 | struct mlx4_icm **icm; | |
273 | }; | |
274 | ||
cc1ade94 SM |
275 | #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28) |
276 | #define MLX4_MPT_FLAG_FREE (0x3UL << 28) | |
277 | #define MLX4_MPT_FLAG_MIO (1 << 17) | |
278 | #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15) | |
279 | #define MLX4_MPT_FLAG_PHYSICAL (1 << 9) | |
280 | #define MLX4_MPT_FLAG_REGION (1 << 8) | |
281 | ||
e630664c MB |
282 | #define MLX4_MPT_PD_MASK (0x1FFFFUL) |
283 | #define MLX4_MPT_PD_VF_MASK (0xFE0000UL) | |
cc1ade94 SM |
284 | #define MLX4_MPT_PD_FLAG_FAST_REG (1 << 27) |
285 | #define MLX4_MPT_PD_FLAG_RAE (1 << 28) | |
286 | #define MLX4_MPT_PD_FLAG_EN_INV (3 << 24) | |
287 | ||
288 | #define MLX4_MPT_QP_FLAG_BOUND_QP (1 << 7) | |
289 | ||
290 | #define MLX4_MPT_STATUS_SW 0xF0 | |
291 | #define MLX4_MPT_STATUS_HW 0x00 | |
292 | ||
c82e9aa0 EC |
293 | /* |
294 | * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. | |
295 | */ | |
296 | struct mlx4_mpt_entry { | |
297 | __be32 flags; | |
298 | __be32 qpn; | |
299 | __be32 key; | |
300 | __be32 pd_flags; | |
301 | __be64 start; | |
302 | __be64 length; | |
303 | __be32 lkey; | |
304 | __be32 win_cnt; | |
305 | u8 reserved1[3]; | |
306 | u8 mtt_rep; | |
2b8fb286 | 307 | __be64 mtt_addr; |
c82e9aa0 EC |
308 | __be32 mtt_sz; |
309 | __be32 entity_size; | |
310 | __be32 first_byte_offset; | |
311 | } __packed; | |
312 | ||
313 | /* | |
314 | * Must be packed because start is 64 bits but only aligned to 32 bits. | |
315 | */ | |
316 | struct mlx4_eq_context { | |
317 | __be32 flags; | |
318 | u16 reserved1[3]; | |
319 | __be16 page_offset; | |
320 | u8 log_eq_size; | |
321 | u8 reserved2[4]; | |
322 | u8 eq_period; | |
323 | u8 reserved3; | |
324 | u8 eq_max_count; | |
325 | u8 reserved4[3]; | |
326 | u8 intr; | |
327 | u8 log_page_size; | |
328 | u8 reserved5[2]; | |
329 | u8 mtt_base_addr_h; | |
330 | __be32 mtt_base_addr_l; | |
331 | u32 reserved6[2]; | |
332 | __be32 consumer_index; | |
333 | __be32 producer_index; | |
334 | u32 reserved7[4]; | |
335 | }; | |
336 | ||
337 | struct mlx4_cq_context { | |
338 | __be32 flags; | |
339 | u16 reserved1[3]; | |
340 | __be16 page_offset; | |
341 | __be32 logsize_usrpage; | |
342 | __be16 cq_period; | |
343 | __be16 cq_max_count; | |
344 | u8 reserved2[3]; | |
345 | u8 comp_eqn; | |
346 | u8 log_page_size; | |
347 | u8 reserved3[2]; | |
348 | u8 mtt_base_addr_h; | |
349 | __be32 mtt_base_addr_l; | |
350 | __be32 last_notified_index; | |
351 | __be32 solicit_producer_index; | |
352 | __be32 consumer_index; | |
353 | __be32 producer_index; | |
354 | u32 reserved4[2]; | |
355 | __be64 db_rec_addr; | |
356 | }; | |
357 | ||
358 | struct mlx4_srq_context { | |
359 | __be32 state_logsize_srqn; | |
360 | u8 logstride; | |
361 | u8 reserved1; | |
362 | __be16 xrcd; | |
363 | __be32 pg_offset_cqn; | |
364 | u32 reserved2; | |
365 | u8 log_page_size; | |
366 | u8 reserved3[2]; | |
367 | u8 mtt_base_addr_h; | |
368 | __be32 mtt_base_addr_l; | |
369 | __be32 pd; | |
370 | __be16 limit_watermark; | |
371 | __be16 wqe_cnt; | |
372 | u16 reserved4; | |
373 | __be16 wqe_counter; | |
374 | u32 reserved5; | |
375 | __be64 db_rec_addr; | |
376 | }; | |
377 | ||
225c7b1f RD |
378 | struct mlx4_eq { |
379 | struct mlx4_dev *dev; | |
380 | void __iomem *doorbell; | |
381 | int eqn; | |
382 | u32 cons_index; | |
383 | u16 irq; | |
384 | u16 have_irq; | |
385 | int nent; | |
386 | struct mlx4_buf_list *page_list; | |
387 | struct mlx4_mtt mtt; | |
388 | }; | |
389 | ||
623ed84b JM |
390 | struct mlx4_slave_eqe { |
391 | u8 type; | |
392 | u8 port; | |
393 | u32 param; | |
394 | }; | |
395 | ||
396 | struct mlx4_slave_event_eq_info { | |
803143fb | 397 | int eqn; |
623ed84b | 398 | u16 token; |
623ed84b JM |
399 | }; |
400 | ||
225c7b1f RD |
401 | struct mlx4_profile { |
402 | int num_qp; | |
403 | int rdmarc_per_qp; | |
404 | int num_srq; | |
405 | int num_cq; | |
406 | int num_mcg; | |
407 | int num_mpt; | |
db5a7a65 | 408 | unsigned num_mtt; |
225c7b1f RD |
409 | }; |
410 | ||
411 | struct mlx4_fw { | |
412 | u64 clr_int_base; | |
413 | u64 catas_offset; | |
623ed84b | 414 | u64 comm_base; |
ddd8a6c1 | 415 | u64 clock_offset; |
225c7b1f RD |
416 | struct mlx4_icm *fw_icm; |
417 | struct mlx4_icm *aux_icm; | |
418 | u32 catas_size; | |
419 | u16 fw_pages; | |
420 | u8 clr_int_bar; | |
421 | u8 catas_bar; | |
623ed84b | 422 | u8 comm_bar; |
ddd8a6c1 | 423 | u8 clock_bar; |
623ed84b JM |
424 | }; |
425 | ||
426 | struct mlx4_comm { | |
427 | u32 slave_write; | |
428 | u32 slave_read; | |
225c7b1f RD |
429 | }; |
430 | ||
ffe455ad EE |
431 | enum { |
432 | MLX4_MCAST_CONFIG = 0, | |
433 | MLX4_MCAST_DISABLE = 1, | |
434 | MLX4_MCAST_ENABLE = 2, | |
435 | }; | |
436 | ||
623ed84b JM |
437 | #define VLAN_FLTR_SIZE 128 |
438 | ||
439 | struct mlx4_vlan_fltr { | |
440 | __be32 entry[VLAN_FLTR_SIZE]; | |
441 | }; | |
442 | ||
ffe455ad EE |
443 | struct mlx4_mcast_entry { |
444 | struct list_head list; | |
445 | u64 addr; | |
446 | }; | |
447 | ||
b12d93d6 YP |
448 | struct mlx4_promisc_qp { |
449 | struct list_head list; | |
450 | u32 qpn; | |
451 | }; | |
452 | ||
453 | struct mlx4_steer_index { | |
454 | struct list_head list; | |
455 | unsigned int index; | |
456 | struct list_head duplicates; | |
457 | }; | |
458 | ||
803143fb MA |
459 | #define MLX4_EVENT_TYPES_NUM 64 |
460 | ||
623ed84b JM |
461 | struct mlx4_slave_state { |
462 | u8 comm_toggle; | |
463 | u8 last_cmd; | |
464 | u8 init_port_mask; | |
465 | bool active; | |
2c957ff2 | 466 | bool old_vlan_api; |
623ed84b JM |
467 | u8 function; |
468 | dma_addr_t vhcr_dma; | |
469 | u16 mtu[MLX4_MAX_PORTS + 1]; | |
470 | __be32 ib_cap_mask[MLX4_MAX_PORTS + 1]; | |
471 | struct mlx4_slave_eqe eq[MLX4_MFUNC_MAX_EQES]; | |
472 | struct list_head mcast_filters[MLX4_MAX_PORTS + 1]; | |
473 | struct mlx4_vlan_fltr *vlan_filter[MLX4_MAX_PORTS + 1]; | |
803143fb MA |
474 | /* event type to eq number lookup */ |
475 | struct mlx4_slave_event_eq_info event_eq[MLX4_EVENT_TYPES_NUM]; | |
623ed84b JM |
476 | u16 eq_pi; |
477 | u16 eq_ci; | |
478 | spinlock_t lock; | |
479 | /*initialized via the kzalloc*/ | |
480 | u8 is_slave_going_down; | |
481 | u32 cookie; | |
993c401e | 482 | enum slave_port_state port_state[MLX4_MAX_PORTS + 1]; |
623ed84b JM |
483 | }; |
484 | ||
0eb62b93 RE |
485 | #define MLX4_VGT 4095 |
486 | #define NO_INDX (-1) | |
487 | ||
488 | struct mlx4_vport_state { | |
489 | u64 mac; | |
490 | u16 default_vlan; | |
491 | u8 default_qos; | |
492 | u32 tx_rate; | |
493 | bool spoofchk; | |
948e306d | 494 | u32 link_state; |
0eb62b93 RE |
495 | }; |
496 | ||
497 | struct mlx4_vf_admin_state { | |
498 | struct mlx4_vport_state vport[MLX4_MAX_PORTS + 1]; | |
99ec41d0 | 499 | u8 enable_smi[MLX4_MAX_PORTS + 1]; |
0eb62b93 RE |
500 | }; |
501 | ||
502 | struct mlx4_vport_oper_state { | |
503 | struct mlx4_vport_state state; | |
504 | int mac_idx; | |
505 | int vlan_idx; | |
506 | }; | |
99ec41d0 | 507 | |
0eb62b93 RE |
508 | struct mlx4_vf_oper_state { |
509 | struct mlx4_vport_oper_state vport[MLX4_MAX_PORTS + 1]; | |
99ec41d0 | 510 | u8 smi_enabled[MLX4_MAX_PORTS + 1]; |
0eb62b93 RE |
511 | }; |
512 | ||
623ed84b JM |
513 | struct slave_list { |
514 | struct mutex mutex; | |
515 | struct list_head res_list[MLX4_NUM_OF_RESOURCE_TYPE]; | |
516 | }; | |
517 | ||
5a0d0a61 | 518 | struct resource_allocator { |
146f3ef4 | 519 | spinlock_t alloc_lock; /* protect quotas */ |
5a0d0a61 JM |
520 | union { |
521 | int res_reserved; | |
522 | int res_port_rsvd[MLX4_MAX_PORTS]; | |
523 | }; | |
524 | union { | |
525 | int res_free; | |
526 | int res_port_free[MLX4_MAX_PORTS]; | |
527 | }; | |
528 | int *quota; | |
529 | int *allocated; | |
530 | int *guaranteed; | |
531 | }; | |
532 | ||
623ed84b JM |
533 | struct mlx4_resource_tracker { |
534 | spinlock_t lock; | |
535 | /* tree for each resources */ | |
4af1c048 | 536 | struct rb_root res_tree[MLX4_NUM_OF_RESOURCE_TYPE]; |
623ed84b JM |
537 | /* num_of_slave's lists, one per slave */ |
538 | struct slave_list *slave_list; | |
5a0d0a61 | 539 | struct resource_allocator res_alloc[MLX4_NUM_OF_RESOURCE_TYPE]; |
623ed84b JM |
540 | }; |
541 | ||
542 | #define SLAVE_EVENT_EQ_SIZE 128 | |
543 | struct mlx4_slave_event_eq { | |
544 | u32 eqn; | |
545 | u32 cons; | |
546 | u32 prod; | |
992e8e6e | 547 | spinlock_t event_lock; |
623ed84b JM |
548 | struct mlx4_eqe event_eqe[SLAVE_EVENT_EQ_SIZE]; |
549 | }; | |
550 | ||
551 | struct mlx4_master_qp0_state { | |
552 | int proxy_qp0_active; | |
553 | int qp0_active; | |
554 | int port_active; | |
555 | }; | |
556 | ||
557 | struct mlx4_mfunc_master_ctx { | |
558 | struct mlx4_slave_state *slave_state; | |
0eb62b93 RE |
559 | struct mlx4_vf_admin_state *vf_admin; |
560 | struct mlx4_vf_oper_state *vf_oper; | |
623ed84b JM |
561 | struct mlx4_master_qp0_state qp0_state[MLX4_MAX_PORTS + 1]; |
562 | int init_port_ref[MLX4_MAX_PORTS + 1]; | |
563 | u16 max_mtu[MLX4_MAX_PORTS + 1]; | |
564 | int disable_mcast_ref[MLX4_MAX_PORTS + 1]; | |
565 | struct mlx4_resource_tracker res_tracker; | |
566 | struct workqueue_struct *comm_wq; | |
567 | struct work_struct comm_work; | |
568 | struct work_struct slave_event_work; | |
569 | struct work_struct slave_flr_event_work; | |
570 | spinlock_t slave_state_lock; | |
f5311ac1 | 571 | __be32 comm_arm_bit_vector[4]; |
623ed84b JM |
572 | struct mlx4_eqe cmd_eqe; |
573 | struct mlx4_slave_event_eq slave_eq; | |
574 | struct mutex gen_eqe_mutex[MLX4_MFUNC_MAX]; | |
575 | }; | |
576 | ||
577 | struct mlx4_mfunc { | |
578 | struct mlx4_comm __iomem *comm; | |
579 | struct mlx4_vhcr_cmd *vhcr; | |
580 | dma_addr_t vhcr_dma; | |
581 | ||
582 | struct mlx4_mfunc_master_ctx master; | |
583 | }; | |
584 | ||
fe6f700d YP |
585 | #define MGM_QPN_MASK 0x00FFFFFF |
586 | #define MGM_BLCK_LB_BIT 30 | |
587 | ||
588 | struct mlx4_mgm { | |
589 | __be32 next_gid_index; | |
590 | __be32 members_count; | |
591 | u32 reserved[2]; | |
592 | u8 gid[16]; | |
593 | __be32 qp[MLX4_MAX_QP_PER_MGM]; | |
594 | }; | |
595 | ||
225c7b1f RD |
596 | struct mlx4_cmd { |
597 | struct pci_pool *pool; | |
598 | void __iomem *hcr; | |
599 | struct mutex hcr_mutex; | |
f3d4c89e | 600 | struct mutex slave_cmd_mutex; |
225c7b1f RD |
601 | struct semaphore poll_sem; |
602 | struct semaphore event_sem; | |
603 | int max_cmds; | |
604 | spinlock_t context_lock; | |
605 | int free_head; | |
606 | struct mlx4_cmd_context *context; | |
607 | u16 token_mask; | |
608 | u8 use_events; | |
609 | u8 toggle; | |
623ed84b | 610 | u8 comm_toggle; |
225c7b1f RD |
611 | }; |
612 | ||
b01978ca JM |
613 | enum { |
614 | MLX4_VF_IMMED_VLAN_FLAG_VLAN = 1 << 0, | |
615 | MLX4_VF_IMMED_VLAN_FLAG_QOS = 1 << 1, | |
0a6eac24 | 616 | MLX4_VF_IMMED_VLAN_FLAG_LINK_DISABLE = 1 << 2, |
b01978ca JM |
617 | }; |
618 | struct mlx4_vf_immed_vlan_work { | |
619 | struct work_struct work; | |
620 | struct mlx4_priv *priv; | |
621 | int flags; | |
622 | int slave; | |
623 | int vlan_ix; | |
624 | int orig_vlan_ix; | |
625 | u8 port; | |
626 | u8 qos; | |
627 | u16 vlan_id; | |
628 | u16 orig_vlan_id; | |
629 | }; | |
630 | ||
631 | ||
225c7b1f RD |
632 | struct mlx4_uar_table { |
633 | struct mlx4_bitmap bitmap; | |
634 | }; | |
635 | ||
636 | struct mlx4_mr_table { | |
637 | struct mlx4_bitmap mpt_bitmap; | |
638 | struct mlx4_buddy mtt_buddy; | |
639 | u64 mtt_base; | |
640 | u64 mpt_base; | |
641 | struct mlx4_icm_table mtt_table; | |
642 | struct mlx4_icm_table dmpt_table; | |
643 | }; | |
644 | ||
645 | struct mlx4_cq_table { | |
646 | struct mlx4_bitmap bitmap; | |
647 | spinlock_t lock; | |
648 | struct radix_tree_root tree; | |
649 | struct mlx4_icm_table table; | |
650 | struct mlx4_icm_table cmpt_table; | |
651 | }; | |
652 | ||
653 | struct mlx4_eq_table { | |
654 | struct mlx4_bitmap bitmap; | |
b8dd786f | 655 | char *irq_names; |
225c7b1f | 656 | void __iomem *clr_int; |
b8dd786f | 657 | void __iomem **uar_map; |
225c7b1f | 658 | u32 clr_mask; |
b8dd786f | 659 | struct mlx4_eq *eq; |
fa0681d2 | 660 | struct mlx4_icm_table table; |
225c7b1f RD |
661 | struct mlx4_icm_table cmpt_table; |
662 | int have_irq; | |
663 | u8 inta_pin; | |
664 | }; | |
665 | ||
666 | struct mlx4_srq_table { | |
667 | struct mlx4_bitmap bitmap; | |
668 | spinlock_t lock; | |
669 | struct radix_tree_root tree; | |
670 | struct mlx4_icm_table table; | |
671 | struct mlx4_icm_table cmpt_table; | |
672 | }; | |
673 | ||
674 | struct mlx4_qp_table { | |
675 | struct mlx4_bitmap bitmap; | |
676 | u32 rdmarc_base; | |
677 | int rdmarc_shift; | |
678 | spinlock_t lock; | |
679 | struct mlx4_icm_table qp_table; | |
680 | struct mlx4_icm_table auxc_table; | |
681 | struct mlx4_icm_table altc_table; | |
682 | struct mlx4_icm_table rdmarc_table; | |
683 | struct mlx4_icm_table cmpt_table; | |
684 | }; | |
685 | ||
686 | struct mlx4_mcg_table { | |
687 | struct mutex mutex; | |
688 | struct mlx4_bitmap bitmap; | |
689 | struct mlx4_icm_table table; | |
690 | }; | |
691 | ||
692 | struct mlx4_catas_err { | |
693 | u32 __iomem *map; | |
ee49bd93 JM |
694 | struct timer_list timer; |
695 | struct list_head list; | |
225c7b1f RD |
696 | }; |
697 | ||
2a2336f8 YP |
698 | #define MLX4_MAX_MAC_NUM 128 |
699 | #define MLX4_MAC_TABLE_SIZE (MLX4_MAX_MAC_NUM << 3) | |
700 | ||
701 | struct mlx4_mac_table { | |
702 | __be64 entries[MLX4_MAX_MAC_NUM]; | |
703 | int refs[MLX4_MAX_MAC_NUM]; | |
704 | struct mutex mutex; | |
705 | int total; | |
706 | int max; | |
707 | }; | |
708 | ||
111c6094 JM |
709 | #define MLX4_ROCE_GID_ENTRY_SIZE 16 |
710 | ||
711 | struct mlx4_roce_gid_entry { | |
712 | u8 raw[MLX4_ROCE_GID_ENTRY_SIZE]; | |
713 | }; | |
714 | ||
715 | struct mlx4_roce_gid_table { | |
716 | struct mlx4_roce_gid_entry roce_gids[MLX4_ROCE_MAX_GIDS]; | |
717 | struct mutex mutex; | |
718 | }; | |
719 | ||
2a2336f8 YP |
720 | #define MLX4_MAX_VLAN_NUM 128 |
721 | #define MLX4_VLAN_TABLE_SIZE (MLX4_MAX_VLAN_NUM << 2) | |
722 | ||
723 | struct mlx4_vlan_table { | |
724 | __be32 entries[MLX4_MAX_VLAN_NUM]; | |
725 | int refs[MLX4_MAX_VLAN_NUM]; | |
726 | struct mutex mutex; | |
727 | int total; | |
728 | int max; | |
729 | }; | |
730 | ||
ffe455ad EE |
731 | #define SET_PORT_GEN_ALL_VALID 0x7 |
732 | #define SET_PORT_PROMISC_SHIFT 31 | |
733 | #define SET_PORT_MC_PROMISC_SHIFT 30 | |
734 | ||
735 | enum { | |
736 | MCAST_DIRECT_ONLY = 0, | |
737 | MCAST_DIRECT = 1, | |
738 | MCAST_DEFAULT = 2 | |
739 | }; | |
740 | ||
741 | ||
742 | struct mlx4_set_port_general_context { | |
743 | u8 reserved[3]; | |
744 | u8 flags; | |
745 | u16 reserved2; | |
746 | __be16 mtu; | |
747 | u8 pptx; | |
748 | u8 pfctx; | |
749 | u16 reserved3; | |
750 | u8 pprx; | |
751 | u8 pfcrx; | |
752 | u16 reserved4; | |
753 | }; | |
754 | ||
755 | struct mlx4_set_port_rqp_calc_context { | |
756 | __be32 base_qpn; | |
757 | u8 rererved; | |
758 | u8 n_mac; | |
759 | u8 n_vlan; | |
760 | u8 n_prio; | |
761 | u8 reserved2[3]; | |
762 | u8 mac_miss; | |
763 | u8 intra_no_vlan; | |
764 | u8 no_vlan; | |
765 | u8 intra_vlan_miss; | |
766 | u8 vlan_miss; | |
767 | u8 reserved3[3]; | |
768 | u8 no_vlan_prio; | |
769 | __be32 promisc; | |
770 | __be32 mcast; | |
771 | }; | |
772 | ||
2a2336f8 YP |
773 | struct mlx4_port_info { |
774 | struct mlx4_dev *dev; | |
775 | int port; | |
7ff93f8b YP |
776 | char dev_name[16]; |
777 | struct device_attribute port_attr; | |
778 | enum mlx4_port_type tmp_type; | |
096335b3 OG |
779 | char dev_mtu_name[16]; |
780 | struct device_attribute port_mtu_attr; | |
2a2336f8 YP |
781 | struct mlx4_mac_table mac_table; |
782 | struct mlx4_vlan_table vlan_table; | |
111c6094 | 783 | struct mlx4_roce_gid_table gid_table; |
1679200f | 784 | int base_qpn; |
2a2336f8 YP |
785 | }; |
786 | ||
27bf91d6 YP |
787 | struct mlx4_sense { |
788 | struct mlx4_dev *dev; | |
789 | u8 do_sense_port[MLX4_MAX_PORTS + 1]; | |
790 | u8 sense_allowed[MLX4_MAX_PORTS + 1]; | |
791 | struct delayed_work sense_poll; | |
792 | }; | |
793 | ||
0b7ca5a9 YP |
794 | struct mlx4_msix_ctl { |
795 | u64 pool_bm; | |
730c41d5 | 796 | struct mutex pool_lock; |
0b7ca5a9 YP |
797 | }; |
798 | ||
b12d93d6 YP |
799 | struct mlx4_steer { |
800 | struct list_head promisc_qps[MLX4_NUM_STEERS]; | |
801 | struct list_head steer_entries[MLX4_NUM_STEERS]; | |
b12d93d6 YP |
802 | }; |
803 | ||
839f1243 RD |
804 | enum { |
805 | MLX4_PCI_DEV_IS_VF = 1 << 0, | |
ca3e57a5 | 806 | MLX4_PCI_DEV_FORCE_SENSE_PORT = 1 << 1, |
839f1243 RD |
807 | }; |
808 | ||
7c6d74d2 JM |
809 | enum { |
810 | MLX4_NO_RR = 0, | |
811 | MLX4_USE_RR = 1, | |
812 | }; | |
813 | ||
225c7b1f RD |
814 | struct mlx4_priv { |
815 | struct mlx4_dev dev; | |
816 | ||
817 | struct list_head dev_list; | |
818 | struct list_head ctx_list; | |
819 | spinlock_t ctx_lock; | |
820 | ||
839f1243 | 821 | int pci_dev_data; |
befdf897 | 822 | int removed; |
839f1243 | 823 | |
6296883c YP |
824 | struct list_head pgdir_list; |
825 | struct mutex pgdir_mutex; | |
826 | ||
225c7b1f RD |
827 | struct mlx4_fw fw; |
828 | struct mlx4_cmd cmd; | |
623ed84b | 829 | struct mlx4_mfunc mfunc; |
225c7b1f RD |
830 | |
831 | struct mlx4_bitmap pd_bitmap; | |
012a8ff5 | 832 | struct mlx4_bitmap xrcd_bitmap; |
225c7b1f RD |
833 | struct mlx4_uar_table uar_table; |
834 | struct mlx4_mr_table mr_table; | |
835 | struct mlx4_cq_table cq_table; | |
836 | struct mlx4_eq_table eq_table; | |
837 | struct mlx4_srq_table srq_table; | |
838 | struct mlx4_qp_table qp_table; | |
839 | struct mlx4_mcg_table mcg_table; | |
f2a3f6a3 | 840 | struct mlx4_bitmap counters_bitmap; |
225c7b1f RD |
841 | |
842 | struct mlx4_catas_err catas_err; | |
843 | ||
844 | void __iomem *clr_base; | |
845 | ||
846 | struct mlx4_uar driver_uar; | |
847 | void __iomem *kar; | |
2a2336f8 | 848 | struct mlx4_port_info port[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 849 | struct mlx4_sense sense; |
7ff93f8b | 850 | struct mutex port_mutex; |
0b7ca5a9 | 851 | struct mlx4_msix_ctl msix_ctl; |
b12d93d6 | 852 | struct mlx4_steer *steer; |
c1b43dca EC |
853 | struct list_head bf_list; |
854 | struct mutex bf_mutex; | |
855 | struct io_mapping *bf_mapping; | |
ddd8a6c1 | 856 | void __iomem *clock_mapping; |
ea51b377 | 857 | int reserved_mtts; |
0ff1fb65 | 858 | int fs_hash_mode; |
54679e14 | 859 | u8 virt2phys_pkey[MLX4_MFUNC_MAX][MLX4_MAX_PORTS][MLX4_MAX_PORT_PKEYS]; |
afa8fd1d | 860 | __be64 slave_node_guids[MLX4_MFUNC_MAX]; |
54679e14 | 861 | |
fe6f700d YP |
862 | atomic_t opreq_count; |
863 | struct work_struct opreq_task; | |
225c7b1f RD |
864 | }; |
865 | ||
866 | static inline struct mlx4_priv *mlx4_priv(struct mlx4_dev *dev) | |
867 | { | |
868 | return container_of(dev, struct mlx4_priv, dev); | |
869 | } | |
870 | ||
27bf91d6 YP |
871 | #define MLX4_SENSE_RANGE (HZ * 3) |
872 | ||
873 | extern struct workqueue_struct *mlx4_wq; | |
874 | ||
225c7b1f | 875 | u32 mlx4_bitmap_alloc(struct mlx4_bitmap *bitmap); |
7c6d74d2 | 876 | void mlx4_bitmap_free(struct mlx4_bitmap *bitmap, u32 obj, int use_rr); |
a3cdcbfa | 877 | u32 mlx4_bitmap_alloc_range(struct mlx4_bitmap *bitmap, int cnt, int align); |
7c6d74d2 JM |
878 | void mlx4_bitmap_free_range(struct mlx4_bitmap *bitmap, u32 obj, int cnt, |
879 | int use_rr); | |
42d1e017 | 880 | u32 mlx4_bitmap_avail(struct mlx4_bitmap *bitmap); |
93fc9e1b YP |
881 | int mlx4_bitmap_init(struct mlx4_bitmap *bitmap, u32 num, u32 mask, |
882 | u32 reserved_bot, u32 resetrved_top); | |
225c7b1f RD |
883 | void mlx4_bitmap_cleanup(struct mlx4_bitmap *bitmap); |
884 | ||
885 | int mlx4_reset(struct mlx4_dev *dev); | |
886 | ||
b8dd786f YP |
887 | int mlx4_alloc_eq_table(struct mlx4_dev *dev); |
888 | void mlx4_free_eq_table(struct mlx4_dev *dev); | |
889 | ||
225c7b1f | 890 | int mlx4_init_pd_table(struct mlx4_dev *dev); |
012a8ff5 | 891 | int mlx4_init_xrcd_table(struct mlx4_dev *dev); |
225c7b1f RD |
892 | int mlx4_init_uar_table(struct mlx4_dev *dev); |
893 | int mlx4_init_mr_table(struct mlx4_dev *dev); | |
894 | int mlx4_init_eq_table(struct mlx4_dev *dev); | |
895 | int mlx4_init_cq_table(struct mlx4_dev *dev); | |
896 | int mlx4_init_qp_table(struct mlx4_dev *dev); | |
897 | int mlx4_init_srq_table(struct mlx4_dev *dev); | |
898 | int mlx4_init_mcg_table(struct mlx4_dev *dev); | |
899 | ||
900 | void mlx4_cleanup_pd_table(struct mlx4_dev *dev); | |
012a8ff5 | 901 | void mlx4_cleanup_xrcd_table(struct mlx4_dev *dev); |
225c7b1f RD |
902 | void mlx4_cleanup_uar_table(struct mlx4_dev *dev); |
903 | void mlx4_cleanup_mr_table(struct mlx4_dev *dev); | |
904 | void mlx4_cleanup_eq_table(struct mlx4_dev *dev); | |
905 | void mlx4_cleanup_cq_table(struct mlx4_dev *dev); | |
906 | void mlx4_cleanup_qp_table(struct mlx4_dev *dev); | |
907 | void mlx4_cleanup_srq_table(struct mlx4_dev *dev); | |
908 | void mlx4_cleanup_mcg_table(struct mlx4_dev *dev); | |
40f2287b | 909 | int __mlx4_qp_alloc_icm(struct mlx4_dev *dev, int qpn, gfp_t gfp); |
c82e9aa0 EC |
910 | void __mlx4_qp_free_icm(struct mlx4_dev *dev, int qpn); |
911 | int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn); | |
912 | void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn); | |
913 | int __mlx4_srq_alloc_icm(struct mlx4_dev *dev, int *srqn); | |
914 | void __mlx4_srq_free_icm(struct mlx4_dev *dev, int srqn); | |
b20e519a SM |
915 | int __mlx4_mpt_reserve(struct mlx4_dev *dev); |
916 | void __mlx4_mpt_release(struct mlx4_dev *dev, u32 index); | |
40f2287b | 917 | int __mlx4_mpt_alloc_icm(struct mlx4_dev *dev, u32 index, gfp_t gfp); |
b20e519a | 918 | void __mlx4_mpt_free_icm(struct mlx4_dev *dev, u32 index); |
c82e9aa0 EC |
919 | u32 __mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order); |
920 | void __mlx4_free_mtt_range(struct mlx4_dev *dev, u32 first_seg, int order); | |
225c7b1f | 921 | |
623ed84b JM |
922 | int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave, |
923 | struct mlx4_vhcr *vhcr, | |
924 | struct mlx4_cmd_mailbox *inbox, | |
925 | struct mlx4_cmd_mailbox *outbox, | |
926 | struct mlx4_cmd_info *cmd); | |
927 | int mlx4_SYNC_TPT_wrapper(struct mlx4_dev *dev, int slave, | |
928 | struct mlx4_vhcr *vhcr, | |
929 | struct mlx4_cmd_mailbox *inbox, | |
930 | struct mlx4_cmd_mailbox *outbox, | |
931 | struct mlx4_cmd_info *cmd); | |
932 | int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
933 | struct mlx4_vhcr *vhcr, | |
934 | struct mlx4_cmd_mailbox *inbox, | |
935 | struct mlx4_cmd_mailbox *outbox, | |
936 | struct mlx4_cmd_info *cmd); | |
937 | int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
938 | struct mlx4_vhcr *vhcr, | |
939 | struct mlx4_cmd_mailbox *inbox, | |
940 | struct mlx4_cmd_mailbox *outbox, | |
941 | struct mlx4_cmd_info *cmd); | |
942 | int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave, | |
943 | struct mlx4_vhcr *vhcr, | |
944 | struct mlx4_cmd_mailbox *inbox, | |
945 | struct mlx4_cmd_mailbox *outbox, | |
946 | struct mlx4_cmd_info *cmd); | |
947 | int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
948 | struct mlx4_vhcr *vhcr, | |
949 | struct mlx4_cmd_mailbox *inbox, | |
950 | struct mlx4_cmd_mailbox *outbox, | |
951 | struct mlx4_cmd_info *cmd); | |
952 | int mlx4_DMA_wrapper(struct mlx4_dev *dev, int slave, | |
953 | struct mlx4_vhcr *vhcr, | |
954 | struct mlx4_cmd_mailbox *inbox, | |
955 | struct mlx4_cmd_mailbox *outbox, | |
956 | struct mlx4_cmd_info *cmd); | |
c82e9aa0 EC |
957 | int __mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, |
958 | int *base); | |
959 | void __mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
960 | int __mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
961 | void __mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
c82e9aa0 EC |
962 | int __mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
963 | int start_index, int npages, u64 *page_list); | |
ba062d52 JM |
964 | int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
965 | void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
966 | int __mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); | |
967 | void __mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
623ed84b | 968 | |
ee49bd93 JM |
969 | void mlx4_start_catas_poll(struct mlx4_dev *dev); |
970 | void mlx4_stop_catas_poll(struct mlx4_dev *dev); | |
27bf91d6 | 971 | void mlx4_catas_init(void); |
ee49bd93 | 972 | int mlx4_restart_one(struct pci_dev *pdev); |
225c7b1f RD |
973 | int mlx4_register_device(struct mlx4_dev *dev); |
974 | void mlx4_unregister_device(struct mlx4_dev *dev); | |
00f5ce99 JM |
975 | void mlx4_dispatch_event(struct mlx4_dev *dev, enum mlx4_dev_event type, |
976 | unsigned long param); | |
225c7b1f RD |
977 | |
978 | struct mlx4_dev_cap; | |
979 | struct mlx4_init_hca_param; | |
980 | ||
981 | u64 mlx4_make_profile(struct mlx4_dev *dev, | |
982 | struct mlx4_profile *request, | |
983 | struct mlx4_dev_cap *dev_cap, | |
984 | struct mlx4_init_hca_param *init_hca); | |
623ed84b JM |
985 | void mlx4_master_comm_channel(struct work_struct *work); |
986 | void mlx4_gen_slave_eqe(struct work_struct *work); | |
987 | void mlx4_master_handle_slave_flr(struct work_struct *work); | |
988 | ||
989 | int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave, | |
990 | struct mlx4_vhcr *vhcr, | |
991 | struct mlx4_cmd_mailbox *inbox, | |
992 | struct mlx4_cmd_mailbox *outbox, | |
993 | struct mlx4_cmd_info *cmd); | |
994 | int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave, | |
995 | struct mlx4_vhcr *vhcr, | |
996 | struct mlx4_cmd_mailbox *inbox, | |
997 | struct mlx4_cmd_mailbox *outbox, | |
998 | struct mlx4_cmd_info *cmd); | |
999 | int mlx4_MAP_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1000 | struct mlx4_vhcr *vhcr, struct mlx4_cmd_mailbox *inbox, | |
1001 | struct mlx4_cmd_mailbox *outbox, | |
1002 | struct mlx4_cmd_info *cmd); | |
1003 | int mlx4_COMM_INT_wrapper(struct mlx4_dev *dev, int slave, | |
1004 | struct mlx4_vhcr *vhcr, | |
1005 | struct mlx4_cmd_mailbox *inbox, | |
1006 | struct mlx4_cmd_mailbox *outbox, | |
1007 | struct mlx4_cmd_info *cmd); | |
1008 | int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1009 | struct mlx4_vhcr *vhcr, | |
1010 | struct mlx4_cmd_mailbox *inbox, | |
1011 | struct mlx4_cmd_mailbox *outbox, | |
1012 | struct mlx4_cmd_info *cmd); | |
1013 | int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave, | |
1014 | struct mlx4_vhcr *vhcr, | |
1015 | struct mlx4_cmd_mailbox *inbox, | |
1016 | struct mlx4_cmd_mailbox *outbox, | |
1017 | struct mlx4_cmd_info *cmd); | |
1018 | int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1019 | struct mlx4_vhcr *vhcr, | |
1020 | struct mlx4_cmd_mailbox *inbox, | |
1021 | struct mlx4_cmd_mailbox *outbox, | |
1022 | struct mlx4_cmd_info *cmd); | |
1023 | int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1024 | struct mlx4_vhcr *vhcr, | |
1025 | struct mlx4_cmd_mailbox *inbox, | |
1026 | struct mlx4_cmd_mailbox *outbox, | |
1027 | struct mlx4_cmd_info *cmd); | |
1028 | int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1029 | struct mlx4_vhcr *vhcr, | |
1030 | struct mlx4_cmd_mailbox *inbox, | |
1031 | struct mlx4_cmd_mailbox *outbox, | |
1032 | struct mlx4_cmd_info *cmd); | |
1033 | int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave, | |
1034 | struct mlx4_vhcr *vhcr, | |
1035 | struct mlx4_cmd_mailbox *inbox, | |
1036 | struct mlx4_cmd_mailbox *outbox, | |
1037 | struct mlx4_cmd_info *cmd); | |
1038 | int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1039 | struct mlx4_vhcr *vhcr, | |
1040 | struct mlx4_cmd_mailbox *inbox, | |
1041 | struct mlx4_cmd_mailbox *outbox, | |
1042 | struct mlx4_cmd_info *cmd); | |
1043 | int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1044 | struct mlx4_vhcr *vhcr, | |
1045 | struct mlx4_cmd_mailbox *inbox, | |
1046 | struct mlx4_cmd_mailbox *outbox, | |
1047 | struct mlx4_cmd_info *cmd); | |
1048 | int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1049 | struct mlx4_vhcr *vhcr, | |
1050 | struct mlx4_cmd_mailbox *inbox, | |
1051 | struct mlx4_cmd_mailbox *outbox, | |
1052 | struct mlx4_cmd_info *cmd); | |
1053 | int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave, | |
1054 | struct mlx4_vhcr *vhcr, | |
1055 | struct mlx4_cmd_mailbox *inbox, | |
1056 | struct mlx4_cmd_mailbox *outbox, | |
1057 | struct mlx4_cmd_info *cmd); | |
1058 | int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1059 | struct mlx4_vhcr *vhcr, | |
1060 | struct mlx4_cmd_mailbox *inbox, | |
1061 | struct mlx4_cmd_mailbox *outbox, | |
1062 | struct mlx4_cmd_info *cmd); | |
1063 | int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1064 | struct mlx4_vhcr *vhcr, | |
1065 | struct mlx4_cmd_mailbox *inbox, | |
1066 | struct mlx4_cmd_mailbox *outbox, | |
1067 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1068 | int mlx4_INIT2INIT_QP_wrapper(struct mlx4_dev *dev, int slave, |
1069 | struct mlx4_vhcr *vhcr, | |
1070 | struct mlx4_cmd_mailbox *inbox, | |
1071 | struct mlx4_cmd_mailbox *outbox, | |
1072 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1073 | int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave, |
1074 | struct mlx4_vhcr *vhcr, | |
1075 | struct mlx4_cmd_mailbox *inbox, | |
1076 | struct mlx4_cmd_mailbox *outbox, | |
1077 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1078 | int mlx4_RTR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, |
1079 | struct mlx4_vhcr *vhcr, | |
1080 | struct mlx4_cmd_mailbox *inbox, | |
1081 | struct mlx4_cmd_mailbox *outbox, | |
1082 | struct mlx4_cmd_info *cmd); | |
1083 | int mlx4_RTS2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1084 | struct mlx4_vhcr *vhcr, | |
1085 | struct mlx4_cmd_mailbox *inbox, | |
1086 | struct mlx4_cmd_mailbox *outbox, | |
1087 | struct mlx4_cmd_info *cmd); | |
1088 | int mlx4_SQERR2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1089 | struct mlx4_vhcr *vhcr, | |
1090 | struct mlx4_cmd_mailbox *inbox, | |
1091 | struct mlx4_cmd_mailbox *outbox, | |
1092 | struct mlx4_cmd_info *cmd); | |
1093 | int mlx4_2ERR_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1094 | struct mlx4_vhcr *vhcr, | |
1095 | struct mlx4_cmd_mailbox *inbox, | |
1096 | struct mlx4_cmd_mailbox *outbox, | |
1097 | struct mlx4_cmd_info *cmd); | |
1098 | int mlx4_RTS2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1099 | struct mlx4_vhcr *vhcr, | |
1100 | struct mlx4_cmd_mailbox *inbox, | |
1101 | struct mlx4_cmd_mailbox *outbox, | |
1102 | struct mlx4_cmd_info *cmd); | |
1103 | int mlx4_SQD2SQD_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1104 | struct mlx4_vhcr *vhcr, | |
1105 | struct mlx4_cmd_mailbox *inbox, | |
1106 | struct mlx4_cmd_mailbox *outbox, | |
1107 | struct mlx4_cmd_info *cmd); | |
1108 | int mlx4_SQD2RTS_QP_wrapper(struct mlx4_dev *dev, int slave, | |
1109 | struct mlx4_vhcr *vhcr, | |
1110 | struct mlx4_cmd_mailbox *inbox, | |
1111 | struct mlx4_cmd_mailbox *outbox, | |
1112 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1113 | int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave, |
1114 | struct mlx4_vhcr *vhcr, | |
1115 | struct mlx4_cmd_mailbox *inbox, | |
1116 | struct mlx4_cmd_mailbox *outbox, | |
1117 | struct mlx4_cmd_info *cmd); | |
54679e14 JM |
1118 | int mlx4_QUERY_QP_wrapper(struct mlx4_dev *dev, int slave, |
1119 | struct mlx4_vhcr *vhcr, | |
1120 | struct mlx4_cmd_mailbox *inbox, | |
1121 | struct mlx4_cmd_mailbox *outbox, | |
1122 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1123 | |
1124 | int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe); | |
225c7b1f | 1125 | |
225c7b1f RD |
1126 | int mlx4_cmd_init(struct mlx4_dev *dev); |
1127 | void mlx4_cmd_cleanup(struct mlx4_dev *dev); | |
ab9c17a0 JM |
1128 | int mlx4_multi_func_init(struct mlx4_dev *dev); |
1129 | void mlx4_multi_func_cleanup(struct mlx4_dev *dev); | |
225c7b1f RD |
1130 | void mlx4_cmd_event(struct mlx4_dev *dev, u16 token, u8 status, u64 out_param); |
1131 | int mlx4_cmd_use_events(struct mlx4_dev *dev); | |
1132 | void mlx4_cmd_use_polling(struct mlx4_dev *dev); | |
1133 | ||
ab9c17a0 JM |
1134 | int mlx4_comm_cmd(struct mlx4_dev *dev, u8 cmd, u16 param, |
1135 | unsigned long timeout); | |
1136 | ||
225c7b1f RD |
1137 | void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn); |
1138 | void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type); | |
1139 | ||
1140 | void mlx4_qp_event(struct mlx4_dev *dev, u32 qpn, int event_type); | |
1141 | ||
1142 | void mlx4_srq_event(struct mlx4_dev *dev, u32 srqn, int event_type); | |
1143 | ||
1144 | void mlx4_handle_catas_err(struct mlx4_dev *dev); | |
1145 | ||
ab6dc30d YP |
1146 | int mlx4_SENSE_PORT(struct mlx4_dev *dev, int port, |
1147 | enum mlx4_port_type *type); | |
27bf91d6 YP |
1148 | void mlx4_do_sense_ports(struct mlx4_dev *dev, |
1149 | enum mlx4_port_type *stype, | |
1150 | enum mlx4_port_type *defaults); | |
1151 | void mlx4_start_sense(struct mlx4_dev *dev); | |
1152 | void mlx4_stop_sense(struct mlx4_dev *dev); | |
1153 | void mlx4_sense_init(struct mlx4_dev *dev); | |
1154 | int mlx4_check_port_params(struct mlx4_dev *dev, | |
1155 | enum mlx4_port_type *port_type); | |
1156 | int mlx4_change_port_types(struct mlx4_dev *dev, | |
1157 | enum mlx4_port_type *port_types); | |
1158 | ||
2a2336f8 YP |
1159 | void mlx4_init_mac_table(struct mlx4_dev *dev, struct mlx4_mac_table *table); |
1160 | void mlx4_init_vlan_table(struct mlx4_dev *dev, struct mlx4_vlan_table *table); | |
111c6094 JM |
1161 | void mlx4_init_roce_gid_table(struct mlx4_dev *dev, |
1162 | struct mlx4_roce_gid_table *table); | |
2009d005 | 1163 | void __mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
3f7fb021 | 1164 | int __mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2a2336f8 | 1165 | |
6634961c | 1166 | int mlx4_SET_PORT(struct mlx4_dev *dev, u8 port, int pkey_tbl_sz); |
623ed84b JM |
1167 | /* resource tracker functions*/ |
1168 | int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev, | |
1169 | enum mlx4_resource resource_type, | |
aa1ec3dd | 1170 | u64 resource_id, int *slave); |
623ed84b | 1171 | void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave_id); |
111c6094 | 1172 | void mlx4_reset_roce_gids(struct mlx4_dev *dev, int slave); |
623ed84b JM |
1173 | int mlx4_init_resource_tracker(struct mlx4_dev *dev); |
1174 | ||
b8924951 JM |
1175 | void mlx4_free_resource_tracker(struct mlx4_dev *dev, |
1176 | enum mlx4_res_tracker_free_type type); | |
623ed84b | 1177 | |
b91cb3eb JM |
1178 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
1179 | struct mlx4_vhcr *vhcr, | |
1180 | struct mlx4_cmd_mailbox *inbox, | |
1181 | struct mlx4_cmd_mailbox *outbox, | |
1182 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1183 | int mlx4_SET_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1184 | struct mlx4_vhcr *vhcr, | |
1185 | struct mlx4_cmd_mailbox *inbox, | |
1186 | struct mlx4_cmd_mailbox *outbox, | |
1187 | struct mlx4_cmd_info *cmd); | |
1188 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
1189 | struct mlx4_vhcr *vhcr, | |
1190 | struct mlx4_cmd_mailbox *inbox, | |
1191 | struct mlx4_cmd_mailbox *outbox, | |
1192 | struct mlx4_cmd_info *cmd); | |
1193 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, | |
1194 | struct mlx4_vhcr *vhcr, | |
1195 | struct mlx4_cmd_mailbox *inbox, | |
1196 | struct mlx4_cmd_mailbox *outbox, | |
1197 | struct mlx4_cmd_info *cmd); | |
b91cb3eb JM |
1198 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
1199 | struct mlx4_vhcr *vhcr, | |
1200 | struct mlx4_cmd_mailbox *inbox, | |
1201 | struct mlx4_cmd_mailbox *outbox, | |
1202 | struct mlx4_cmd_info *cmd); | |
623ed84b JM |
1203 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
1204 | struct mlx4_vhcr *vhcr, | |
1205 | struct mlx4_cmd_mailbox *inbox, | |
1206 | struct mlx4_cmd_mailbox *outbox, | |
1207 | struct mlx4_cmd_info *cmd); | |
9a5aa622 | 1208 | int mlx4_get_port_ib_caps(struct mlx4_dev *dev, u8 port, __be32 *caps); |
7ff93f8b | 1209 | |
6634961c JM |
1210 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
1211 | int *gid_tbl_len, int *pkey_tbl_len); | |
623ed84b JM |
1212 | |
1213 | int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave, | |
1214 | struct mlx4_vhcr *vhcr, | |
1215 | struct mlx4_cmd_mailbox *inbox, | |
1216 | struct mlx4_cmd_mailbox *outbox, | |
1217 | struct mlx4_cmd_info *cmd); | |
1218 | ||
ce8d9e0d MB |
1219 | int mlx4_UPDATE_QP_wrapper(struct mlx4_dev *dev, int slave, |
1220 | struct mlx4_vhcr *vhcr, | |
1221 | struct mlx4_cmd_mailbox *inbox, | |
1222 | struct mlx4_cmd_mailbox *outbox, | |
1223 | struct mlx4_cmd_info *cmd); | |
1224 | ||
623ed84b JM |
1225 | int mlx4_PROMISC_wrapper(struct mlx4_dev *dev, int slave, |
1226 | struct mlx4_vhcr *vhcr, | |
1227 | struct mlx4_cmd_mailbox *inbox, | |
1228 | struct mlx4_cmd_mailbox *outbox, | |
1229 | struct mlx4_cmd_info *cmd); | |
b12d93d6 YP |
1230 | int mlx4_qp_detach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
1231 | enum mlx4_protocol prot, enum mlx4_steer_type steer); | |
1232 | int mlx4_qp_attach_common(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
1233 | int block_mcast_loopback, enum mlx4_protocol prot, | |
1234 | enum mlx4_steer_type steer); | |
fd91c49f HHZ |
1235 | int mlx4_trans_to_dmfs_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, |
1236 | u8 gid[16], u8 port, | |
1237 | int block_mcast_loopback, | |
1238 | enum mlx4_protocol prot, u64 *reg_id); | |
623ed84b JM |
1239 | int mlx4_SET_MCAST_FLTR_wrapper(struct mlx4_dev *dev, int slave, |
1240 | struct mlx4_vhcr *vhcr, | |
1241 | struct mlx4_cmd_mailbox *inbox, | |
1242 | struct mlx4_cmd_mailbox *outbox, | |
1243 | struct mlx4_cmd_info *cmd); | |
1244 | int mlx4_SET_VLAN_FLTR_wrapper(struct mlx4_dev *dev, int slave, | |
1245 | struct mlx4_vhcr *vhcr, | |
1246 | struct mlx4_cmd_mailbox *inbox, | |
1247 | struct mlx4_cmd_mailbox *outbox, | |
1248 | struct mlx4_cmd_info *cmd); | |
1249 | int mlx4_common_set_vlan_fltr(struct mlx4_dev *dev, int function, | |
1250 | int port, void *buf); | |
1251 | int mlx4_common_dump_eth_stats(struct mlx4_dev *dev, int slave, u32 in_mod, | |
1252 | struct mlx4_cmd_mailbox *outbox); | |
1253 | int mlx4_DUMP_ETH_STATS_wrapper(struct mlx4_dev *dev, int slave, | |
1254 | struct mlx4_vhcr *vhcr, | |
1255 | struct mlx4_cmd_mailbox *inbox, | |
1256 | struct mlx4_cmd_mailbox *outbox, | |
1257 | struct mlx4_cmd_info *cmd); | |
1258 | int mlx4_PKEY_TABLE_wrapper(struct mlx4_dev *dev, int slave, | |
1259 | struct mlx4_vhcr *vhcr, | |
1260 | struct mlx4_cmd_mailbox *inbox, | |
1261 | struct mlx4_cmd_mailbox *outbox, | |
1262 | struct mlx4_cmd_info *cmd); | |
1263 | int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave, | |
1264 | struct mlx4_vhcr *vhcr, | |
1265 | struct mlx4_cmd_mailbox *inbox, | |
1266 | struct mlx4_cmd_mailbox *outbox, | |
1267 | struct mlx4_cmd_info *cmd); | |
8fcfb4db HHZ |
1268 | int mlx4_QP_FLOW_STEERING_ATTACH_wrapper(struct mlx4_dev *dev, int slave, |
1269 | struct mlx4_vhcr *vhcr, | |
1270 | struct mlx4_cmd_mailbox *inbox, | |
1271 | struct mlx4_cmd_mailbox *outbox, | |
1272 | struct mlx4_cmd_info *cmd); | |
1273 | int mlx4_QP_FLOW_STEERING_DETACH_wrapper(struct mlx4_dev *dev, int slave, | |
1274 | struct mlx4_vhcr *vhcr, | |
1275 | struct mlx4_cmd_mailbox *inbox, | |
1276 | struct mlx4_cmd_mailbox *outbox, | |
1277 | struct mlx4_cmd_info *cmd); | |
f5311ac1 | 1278 | |
0ec2c0f8 EE |
1279 | int mlx4_get_mgm_entry_size(struct mlx4_dev *dev); |
1280 | int mlx4_get_qp_per_mgm(struct mlx4_dev *dev); | |
1281 | ||
5cc914f1 MA |
1282 | static inline void set_param_l(u64 *arg, u32 val) |
1283 | { | |
e7dbeba8 | 1284 | *arg = (*arg & 0xffffffff00000000ULL) | (u64) val; |
5cc914f1 MA |
1285 | } |
1286 | ||
1287 | static inline void set_param_h(u64 *arg, u32 val) | |
1288 | { | |
1289 | *arg = (*arg & 0xffffffff) | ((u64) val << 32); | |
1290 | } | |
1291 | ||
1292 | static inline u32 get_param_l(u64 *arg) | |
1293 | { | |
1294 | return (u32) (*arg & 0xffffffff); | |
1295 | } | |
1296 | ||
1297 | static inline u32 get_param_h(u64 *arg) | |
1298 | { | |
1299 | return (u32)(*arg >> 32); | |
1300 | } | |
1301 | ||
c82e9aa0 EC |
1302 | static inline spinlock_t *mlx4_tlock(struct mlx4_dev *dev) |
1303 | { | |
1304 | return &mlx4_priv(dev)->mfunc.master.res_tracker.lock; | |
1305 | } | |
1306 | ||
f5311ac1 JM |
1307 | #define NOT_MASKED_PD_BITS 17 |
1308 | ||
b01978ca JM |
1309 | void mlx4_vf_immed_vlan_work_handler(struct work_struct *_work); |
1310 | ||
5a0d0a61 JM |
1311 | void mlx4_init_quotas(struct mlx4_dev *dev); |
1312 | ||
449fc488 | 1313 | int mlx4_get_slave_num_gids(struct mlx4_dev *dev, int slave, int port); |
f74462ac MB |
1314 | /* Returns the VF index of slave */ |
1315 | int mlx4_get_vf_indx(struct mlx4_dev *dev, int slave); | |
b6ffaeff | 1316 | |
225c7b1f | 1317 | #endif /* MLX4_H */ |